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Staging: et131x: config is already zeroed
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / e1000e / hw.h
CommitLineData
bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
ad68076e 4 Copyright(c) 1999 - 2008 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#ifndef _E1000_HW_H_
30#define _E1000_HW_H_
31
32#include <linux/types.h>
33
34struct e1000_hw;
35struct e1000_adapter;
36
37#include "defines.h"
38
39#define er32(reg) __er32(hw, E1000_##reg)
40#define ew32(reg,val) __ew32(hw, E1000_##reg, (val))
41#define e1e_flush() er32(STATUS)
42
43#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
44 (writel((value), ((a)->hw_addr + reg + ((offset) << 2))))
45
46#define E1000_READ_REG_ARRAY(a, reg, offset) \
47 (readl((a)->hw_addr + reg + ((offset) << 2)))
48
49enum e1e_registers {
50 E1000_CTRL = 0x00000, /* Device Control - RW */
51 E1000_STATUS = 0x00008, /* Device Status - RO */
52 E1000_EECD = 0x00010, /* EEPROM/Flash Control - RW */
53 E1000_EERD = 0x00014, /* EEPROM Read - RW */
54 E1000_CTRL_EXT = 0x00018, /* Extended Device Control - RW */
55 E1000_FLA = 0x0001C, /* Flash Access - RW */
56 E1000_MDIC = 0x00020, /* MDI Control - RW */
57 E1000_SCTL = 0x00024, /* SerDes Control - RW */
58 E1000_FCAL = 0x00028, /* Flow Control Address Low - RW */
59 E1000_FCAH = 0x0002C, /* Flow Control Address High -RW */
60 E1000_FEXTNVM = 0x00028, /* Future Extended NVM - RW */
61 E1000_FCT = 0x00030, /* Flow Control Type - RW */
62 E1000_VET = 0x00038, /* VLAN Ether Type - RW */
63 E1000_ICR = 0x000C0, /* Interrupt Cause Read - R/clr */
64 E1000_ITR = 0x000C4, /* Interrupt Throttling Rate - RW */
65 E1000_ICS = 0x000C8, /* Interrupt Cause Set - WO */
66 E1000_IMS = 0x000D0, /* Interrupt Mask Set - RW */
67 E1000_IMC = 0x000D8, /* Interrupt Mask Clear - WO */
4662e82b 68 E1000_EIAC_82574 = 0x000DC, /* Ext. Interrupt Auto Clear - RW */
bc7f75fa 69 E1000_IAM = 0x000E0, /* Interrupt Acknowledge Auto Mask */
4662e82b
BA		 70 E1000_IVAR = 0x000E4, /* Interrupt Vector Allocation - RW */
71 E1000_EITR_82574_BASE = 0x000E8, /* Interrupt Throttling - RW */
72#define E1000_EITR_82574(_n) (E1000_EITR_82574_BASE + (_n << 2))
ad68076e 73 E1000_RCTL = 0x00100, /* Rx Control - RW */
bc7f75fa 74 E1000_FCTTV = 0x00170, /* Flow Control Transmit Timer Value - RW */
ad68076e
BA		 75 E1000_TXCW = 0x00178, /* Tx Configuration Word - RW */
76 E1000_RXCW = 0x00180, /* Rx Configuration Word - RO */
77 E1000_TCTL = 0x00400, /* Tx Control - RW */
78 E1000_TCTL_EXT = 0x00404, /* Extended Tx Control - RW */
79 E1000_TIPG = 0x00410, /* Tx Inter-packet gap -RW */
80 E1000_AIT = 0x00458, /* Adaptive Interframe Spacing Throttle -RW */
bc7f75fa
AK		 81 E1000_LEDCTL = 0x00E00, /* LED Control - RW */
82 E1000_EXTCNF_CTRL = 0x00F00, /* Extended Configuration Control */
83 E1000_EXTCNF_SIZE = 0x00F08, /* Extended Configuration Size */
84 E1000_PHY_CTRL = 0x00F10, /* PHY Control Register in CSR */
85 E1000_PBA = 0x01000, /* Packet Buffer Allocation - RW */
86 E1000_PBS = 0x01008, /* Packet Buffer Size */
87 E1000_EEMNGCTL = 0x01010, /* MNG EEprom Control */
88 E1000_EEWR = 0x0102C, /* EEPROM Write Register - RW */
89 E1000_FLOP = 0x0103C, /* FLASH Opcode Register */
6ea7ae1d 90 E1000_PBA_ECC = 0x01100, /* PBA ECC Register */
bc7f75fa
AK		 91 E1000_ERT = 0x02008, /* Early Rx Threshold - RW */
92 E1000_FCRTL = 0x02160, /* Flow Control Receive Threshold Low - RW */
93 E1000_FCRTH = 0x02168, /* Flow Control Receive Threshold High - RW */
94 E1000_PSRCTL = 0x02170, /* Packet Split Receive Control - RW */
ad68076e
BA		 95 E1000_RDBAL = 0x02800, /* Rx Descriptor Base Address Low - RW */
96 E1000_RDBAH = 0x02804, /* Rx Descriptor Base Address High - RW */
97 E1000_RDLEN = 0x02808, /* Rx Descriptor Length - RW */
98 E1000_RDH = 0x02810, /* Rx Descriptor Head - RW */
99 E1000_RDT = 0x02818, /* Rx Descriptor Tail - RW */
100 E1000_RDTR = 0x02820, /* Rx Delay Timer - RW */
e9ec2c0f
JK		 101 E1000_RXDCTL_BASE = 0x02828, /* Rx Descriptor Control - RW */
102#define E1000_RXDCTL(_n) (E1000_RXDCTL_BASE + (_n << 8))
bc7f75fa
AK		 103 E1000_RADV = 0x0282C, /* RX Interrupt Absolute Delay Timer - RW */
104
105/* Convenience macros
106 *
107 * Note: "_n" is the queue number of the register to be written to.
108 *
109 * Example usage:
110 * E1000_RDBAL_REG(current_rx_queue)
111 *
112 */
113#define E1000_RDBAL_REG(_n) (E1000_RDBAL + (_n << 8))
114 E1000_KABGTXD = 0x03004, /* AFE Band Gap Transmit Ref Data */
ad68076e
BA		 115 E1000_TDBAL = 0x03800, /* Tx Descriptor Base Address Low - RW */
116 E1000_TDBAH = 0x03804, /* Tx Descriptor Base Address High - RW */
117 E1000_TDLEN = 0x03808, /* Tx Descriptor Length - RW */
118 E1000_TDH = 0x03810, /* Tx Descriptor Head - RW */
119 E1000_TDT = 0x03818, /* Tx Descriptor Tail - RW */
120 E1000_TIDV = 0x03820, /* Tx Interrupt Delay Value - RW */
e9ec2c0f
JK		 121 E1000_TXDCTL_BASE = 0x03828, /* Tx Descriptor Control - RW */
122#define E1000_TXDCTL(_n) (E1000_TXDCTL_BASE + (_n << 8))
ad68076e 123 E1000_TADV = 0x0382C, /* Tx Interrupt Absolute Delay Val - RW */
e9ec2c0f
JK		 124 E1000_TARC_BASE = 0x03840, /* Tx Arbitration Count (0) */
125#define E1000_TARC(_n) (E1000_TARC_BASE + (_n << 8))
bc7f75fa
AK		 126 E1000_CRCERRS = 0x04000, /* CRC Error Count - R/clr */
127 E1000_ALGNERRC = 0x04004, /* Alignment Error Count - R/clr */
128 E1000_SYMERRS = 0x04008, /* Symbol Error Count - R/clr */
129 E1000_RXERRC = 0x0400C, /* Receive Error Count - R/clr */
130 E1000_MPC = 0x04010, /* Missed Packet Count - R/clr */
131 E1000_SCC = 0x04014, /* Single Collision Count - R/clr */
132 E1000_ECOL = 0x04018, /* Excessive Collision Count - R/clr */
133 E1000_MCC = 0x0401C, /* Multiple Collision Count - R/clr */
134 E1000_LATECOL = 0x04020, /* Late Collision Count - R/clr */
135 E1000_COLC = 0x04028, /* Collision Count - R/clr */
136 E1000_DC = 0x04030, /* Defer Count - R/clr */
ad68076e 137 E1000_TNCRS = 0x04034, /* Tx-No CRS - R/clr */
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AK		 138 E1000_SEC = 0x04038, /* Sequence Error Count - R/clr */
139 E1000_CEXTERR = 0x0403C, /* Carrier Extension Error Count - R/clr */
140 E1000_RLEC = 0x04040, /* Receive Length Error Count - R/clr */
ad68076e
BA		 141 E1000_XONRXC = 0x04048, /* XON Rx Count - R/clr */
142 E1000_XONTXC = 0x0404C, /* XON Tx Count - R/clr */
143 E1000_XOFFRXC = 0x04050, /* XOFF Rx Count - R/clr */
144 E1000_XOFFTXC = 0x04054, /* XOFF Tx Count - R/clr */
145 E1000_FCRUC = 0x04058, /* Flow Control Rx Unsupported Count- R/clr */
146 E1000_PRC64 = 0x0405C, /* Packets Rx (64 bytes) - R/clr */
147 E1000_PRC127 = 0x04060, /* Packets Rx (65-127 bytes) - R/clr */
148 E1000_PRC255 = 0x04064, /* Packets Rx (128-255 bytes) - R/clr */
149 E1000_PRC511 = 0x04068, /* Packets Rx (255-511 bytes) - R/clr */
150 E1000_PRC1023 = 0x0406C, /* Packets Rx (512-1023 bytes) - R/clr */
151 E1000_PRC1522 = 0x04070, /* Packets Rx (1024-1522 bytes) - R/clr */
152 E1000_GPRC = 0x04074, /* Good Packets Rx Count - R/clr */
153 E1000_BPRC = 0x04078, /* Broadcast Packets Rx Count - R/clr */
154 E1000_MPRC = 0x0407C, /* Multicast Packets Rx Count - R/clr */
155 E1000_GPTC = 0x04080, /* Good Packets Tx Count - R/clr */
156 E1000_GORCL = 0x04088, /* Good Octets Rx Count Low - R/clr */
157 E1000_GORCH = 0x0408C, /* Good Octets Rx Count High - R/clr */
158 E1000_GOTCL = 0x04090, /* Good Octets Tx Count Low - R/clr */
159 E1000_GOTCH = 0x04094, /* Good Octets Tx Count High - R/clr */
160 E1000_RNBC = 0x040A0, /* Rx No Buffers Count - R/clr */
161 E1000_RUC = 0x040A4, /* Rx Undersize Count - R/clr */
162 E1000_RFC = 0x040A8, /* Rx Fragment Count - R/clr */
163 E1000_ROC = 0x040AC, /* Rx Oversize Count - R/clr */
164 E1000_RJC = 0x040B0, /* Rx Jabber Count - R/clr */
165 E1000_MGTPRC = 0x040B4, /* Management Packets Rx Count - R/clr */
bc7f75fa 166 E1000_MGTPDC = 0x040B8, /* Management Packets Dropped Count - R/clr */
ad68076e
BA		 167 E1000_MGTPTC = 0x040BC, /* Management Packets Tx Count - R/clr */
168 E1000_TORL = 0x040C0, /* Total Octets Rx Low - R/clr */
169 E1000_TORH = 0x040C4, /* Total Octets Rx High - R/clr */
170 E1000_TOTL = 0x040C8, /* Total Octets Tx Low - R/clr */
171 E1000_TOTH = 0x040CC, /* Total Octets Tx High - R/clr */
172 E1000_TPR = 0x040D0, /* Total Packets Rx - R/clr */
173 E1000_TPT = 0x040D4, /* Total Packets Tx - R/clr */
174 E1000_PTC64 = 0x040D8, /* Packets Tx (64 bytes) - R/clr */
175 E1000_PTC127 = 0x040DC, /* Packets Tx (65-127 bytes) - R/clr */
176 E1000_PTC255 = 0x040E0, /* Packets Tx (128-255 bytes) - R/clr */
177 E1000_PTC511 = 0x040E4, /* Packets Tx (256-511 bytes) - R/clr */
178 E1000_PTC1023 = 0x040E8, /* Packets Tx (512-1023 bytes) - R/clr */
179 E1000_PTC1522 = 0x040EC, /* Packets Tx (1024-1522 Bytes) - R/clr */
180 E1000_MPTC = 0x040F0, /* Multicast Packets Tx Count - R/clr */
181 E1000_BPTC = 0x040F4, /* Broadcast Packets Tx Count - R/clr */
182 E1000_TSCTC = 0x040F8, /* TCP Segmentation Context Tx - R/clr */
183 E1000_TSCTFC = 0x040FC, /* TCP Segmentation Context Tx Fail - R/clr */
bc7f75fa
AK		 184 E1000_IAC = 0x04100, /* Interrupt Assertion Count */
185 E1000_ICRXPTC = 0x04104, /* Irq Cause Rx Packet Timer Expire Count */
186 E1000_ICRXATC = 0x04108, /* Irq Cause Rx Abs Timer Expire Count */
187 E1000_ICTXPTC = 0x0410C, /* Irq Cause Tx Packet Timer Expire Count */
188 E1000_ICTXATC = 0x04110, /* Irq Cause Tx Abs Timer Expire Count */
189 E1000_ICTXQEC = 0x04118, /* Irq Cause Tx Queue Empty Count */
190 E1000_ICTXQMTC = 0x0411C, /* Irq Cause Tx Queue MinThreshold Count */
191 E1000_ICRXDMTC = 0x04120, /* Irq Cause Rx Desc MinThreshold Count */
192 E1000_ICRXOC = 0x04124, /* Irq Cause Receiver Overrun Count */
ad68076e 193 E1000_RXCSUM = 0x05000, /* Rx Checksum Control - RW */
489815ce 194 E1000_RFCTL = 0x05008, /* Receive Filter Control */
bc7f75fa 195 E1000_MTA = 0x05200, /* Multicast Table Array - RW Array */
a4f58f54
BA		 196 E1000_RAL_BASE = 0x05400, /* Receive Address Low - RW */
197#define E1000_RAL(_n) (E1000_RAL_BASE + ((_n) * 8))
198#define E1000_RA (E1000_RAL(0))
199 E1000_RAH_BASE = 0x05404, /* Receive Address High - RW */
200#define E1000_RAH(_n) (E1000_RAH_BASE + ((_n) * 8))
bc7f75fa
AK		 201 E1000_VFTA = 0x05600, /* VLAN Filter Table Array - RW Array */
202 E1000_WUC = 0x05800, /* Wakeup Control - RW */
203 E1000_WUFC = 0x05808, /* Wakeup Filter Control - RW */
204 E1000_WUS = 0x05810, /* Wakeup Status - RO */
205 E1000_MANC = 0x05820, /* Management Control - RW */
206 E1000_FFLT = 0x05F00, /* Flexible Filter Length Table - RW Array */
207 E1000_HOST_IF = 0x08800, /* Host Interface */
208
209 E1000_KMRNCTRLSTA = 0x00034, /* MAC-PHY interface - RW */
210 E1000_MANC2H = 0x05860, /* Management Control To Host - RW */
211 E1000_SW_FW_SYNC = 0x05B5C, /* Software-Firmware Synchronization - RW */
212 E1000_GCR = 0x05B00, /* PCI-Ex Control */
78272bba 213 E1000_GCR2 = 0x05B64, /* PCI-Ex Control #2 */
bc7f75fa
AK		 214 E1000_FACTPS = 0x05B30, /* Function Active and Power State to MNG */
215 E1000_SWSM = 0x05B50, /* SW Semaphore */
216 E1000_FWSM = 0x05B54, /* FW Semaphore */
23a2d1b2 217 E1000_SWSM2 = 0x05B58, /* Driver-only SW semaphore */
7d3cabbc 218 E1000_CRC_OFFSET = 0x05F50, /* CRC Offset register */
489815ce 219 E1000_HICR = 0x08F00, /* Host Interface Control */
bc7f75fa
AK		 220};
221
222/* RSS registers */
223
224/* IGP01E1000 Specific Registers */
225#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
226#define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */
227#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
228#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
229#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
230#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
97ac8cae
BA		 231#define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */
232#define IGP_PAGE_SHIFT 5
233#define PHY_REG_MASK 0x1F
234
235#define BM_WUC_PAGE 800
236#define BM_WUC_ADDRESS_OPCODE 0x11
237#define BM_WUC_DATA_OPCODE 0x12
238#define BM_WUC_ENABLE_PAGE 769
239#define BM_WUC_ENABLE_REG 17
240#define BM_WUC_ENABLE_BIT (1 << 2)
241#define BM_WUC_HOST_WU_BIT (1 << 4)
242
243#define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
244#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
245#define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
bc7f75fa
AK		 246
247#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
248#define IGP01E1000_PHY_POLARITY_MASK 0x0078
249
250#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
251#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
252
253#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
254
255#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
256#define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */
257#define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */
258
259#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
260
261#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
cbe7a81a 262#define IGP01E1000_PSSR_MDIX 0x0800
bc7f75fa
AK		 263#define IGP01E1000_PSSR_SPEED_MASK 0xC000
264#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
265
266#define IGP02E1000_PHY_CHANNEL_NUM 4
267#define IGP02E1000_PHY_AGC_A 0x11B1
268#define IGP02E1000_PHY_AGC_B 0x12B1
269#define IGP02E1000_PHY_AGC_C 0x14B1
270#define IGP02E1000_PHY_AGC_D 0x18B1
271
272#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */
273#define IGP02E1000_AGC_LENGTH_MASK 0x7F
274#define IGP02E1000_AGC_RANGE 15
275
276/* manage.c */
277#define E1000_VFTA_ENTRY_SHIFT 5
278#define E1000_VFTA_ENTRY_MASK 0x7F
279#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
280
281#define E1000_HICR_EN 0x01 /* Enable bit - RO */
ad68076e
BA		 282/* Driver sets this bit when done to put command in RAM */
283#define E1000_HICR_C 0x02
bc7f75fa
AK		 284#define E1000_HICR_FW_RESET_ENABLE 0x40
285#define E1000_HICR_FW_RESET 0x80
286
287#define E1000_FWSM_MODE_MASK 0xE
288#define E1000_FWSM_MODE_SHIFT 1
289
290#define E1000_MNG_IAMT_MODE 0x3
291#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10
292#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0
293#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10
294#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
295#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1
296#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2
297
298/* nvm.c */
299#define E1000_STM_OPCODE 0xDB00
300
301#define E1000_KMRNCTRLSTA_OFFSET 0x001F0000
302#define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16
303#define E1000_KMRNCTRLSTA_REN 0x00200000
304#define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */
305#define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */
7d3cabbc
BA		 306#define E1000_KMRNCTRLSTA_K1_CONFIG 0x7
307#define E1000_KMRNCTRLSTA_K1_ENABLE 0x140E
308#define E1000_KMRNCTRLSTA_K1_DISABLE 0x1400
bc7f75fa
AK		 309
310#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
311#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Control */
312#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */
313#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */
314
315/* IFE PHY Extended Status Control */
316#define IFE_PESC_POLARITY_REVERSED 0x0100
317
318/* IFE PHY Special Control */
319#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010
320#define IFE_PSC_FORCE_POLARITY 0x0020
321
322/* IFE PHY Special Control and LED Control */
323#define IFE_PSCL_PROBE_MODE 0x0020
324#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
325#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
326
327/* IFE PHY MDIX Control */
328#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
329#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */
330#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
331
332#define E1000_CABLE_LENGTH_UNDEFINED 0xFF
333
334#define E1000_DEV_ID_82571EB_COPPER 0x105E
335#define E1000_DEV_ID_82571EB_FIBER 0x105F
336#define E1000_DEV_ID_82571EB_SERDES 0x1060
337#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
040babf9 338#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
bc7f75fa
AK		 339#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
340#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
040babf9
AK		 341#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
342#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
bc7f75fa
AK		 343#define E1000_DEV_ID_82572EI_COPPER 0x107D
344#define E1000_DEV_ID_82572EI_FIBER 0x107E
345#define E1000_DEV_ID_82572EI_SERDES 0x107F
346#define E1000_DEV_ID_82572EI 0x10B9
347#define E1000_DEV_ID_82573E 0x108B
348#define E1000_DEV_ID_82573E_IAMT 0x108C
349#define E1000_DEV_ID_82573L 0x109A
4662e82b 350#define E1000_DEV_ID_82574L 0x10D3
bef28b11 351#define E1000_DEV_ID_82574LA 0x10F6
8c81c9c3 352#define E1000_DEV_ID_82583V 0x150C
bc7f75fa
AK		 353
354#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
355#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
356#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
357#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
358
359#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
360#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
361#define E1000_DEV_ID_ICH8_IGP_C 0x104B
362#define E1000_DEV_ID_ICH8_IFE 0x104C
363#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
364#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
365#define E1000_DEV_ID_ICH8_IGP_M 0x104D
366#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
2f15f9d6 367#define E1000_DEV_ID_ICH9_BM 0x10E5
97ac8cae
BA		 368#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
369#define E1000_DEV_ID_ICH9_IGP_M 0x10BF
370#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
bc7f75fa
AK		 371#define E1000_DEV_ID_ICH9_IGP_C 0x294C
372#define E1000_DEV_ID_ICH9_IFE 0x10C0
373#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
374#define E1000_DEV_ID_ICH9_IFE_G 0x10C2
97ac8cae
BA		 375#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
376#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
377#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
f4187b56
BA		 378#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
379#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
a4f58f54
BA		 380#define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
381#define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
382#define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
383#define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
bc7f75fa 384
4662e82b
BA		 385#define E1000_REVISION_4 4
386
bc7f75fa
AK		 387#define E1000_FUNC_1 1
388
389enum e1000_mac_type {
390 e1000_82571,
391 e1000_82572,
392 e1000_82573,
4662e82b 393 e1000_82574,
8c81c9c3 394 e1000_82583,
bc7f75fa
AK		 395 e1000_80003es2lan,
396 e1000_ich8lan,
397 e1000_ich9lan,
f4187b56 398 e1000_ich10lan,
a4f58f54 399 e1000_pchlan,
bc7f75fa
AK		 400};
401
402enum e1000_media_type {
403 e1000_media_type_unknown = 0,
404 e1000_media_type_copper = 1,
405 e1000_media_type_fiber = 2,
406 e1000_media_type_internal_serdes = 3,
407 e1000_num_media_types
408};
409
410enum e1000_nvm_type {
411 e1000_nvm_unknown = 0,
412 e1000_nvm_none,
413 e1000_nvm_eeprom_spi,
414 e1000_nvm_flash_hw,
415 e1000_nvm_flash_sw
416};
417
418enum e1000_nvm_override {
419 e1000_nvm_override_none = 0,
420 e1000_nvm_override_spi_small,
421 e1000_nvm_override_spi_large
422};
423
424enum e1000_phy_type {
425 e1000_phy_unknown = 0,
426 e1000_phy_none,
427 e1000_phy_m88,
428 e1000_phy_igp,
429 e1000_phy_igp_2,
430 e1000_phy_gg82563,
431 e1000_phy_igp_3,
432 e1000_phy_ife,
97ac8cae 433 e1000_phy_bm,
a4f58f54
BA		 434 e1000_phy_82578,
435 e1000_phy_82577,
bc7f75fa
AK		 436};
437
438enum e1000_bus_width {
439 e1000_bus_width_unknown = 0,
440 e1000_bus_width_pcie_x1,
441 e1000_bus_width_pcie_x2,
442 e1000_bus_width_pcie_x4 = 4,
443 e1000_bus_width_32,
444 e1000_bus_width_64,
445 e1000_bus_width_reserved
446};
447
448enum e1000_1000t_rx_status {
449 e1000_1000t_rx_status_not_ok = 0,
450 e1000_1000t_rx_status_ok,
451 e1000_1000t_rx_status_undefined = 0xFF
452};
453
454enum e1000_rev_polarity{
455 e1000_rev_polarity_normal = 0,
456 e1000_rev_polarity_reversed,
457 e1000_rev_polarity_undefined = 0xFF
458};
459
5c48ef3e 460enum e1000_fc_mode {
bc7f75fa
AK		 461 e1000_fc_none = 0,
462 e1000_fc_rx_pause,
463 e1000_fc_tx_pause,
464 e1000_fc_full,
465 e1000_fc_default = 0xFF
466};
467
468enum e1000_ms_type {
469 e1000_ms_hw_default = 0,
470 e1000_ms_force_master,
471 e1000_ms_force_slave,
472 e1000_ms_auto
473};
474
475enum e1000_smart_speed {
476 e1000_smart_speed_default = 0,
477 e1000_smart_speed_on,
478 e1000_smart_speed_off
479};
480
c9523379 481enum e1000_serdes_link_state {
482 e1000_serdes_link_down = 0,
483 e1000_serdes_link_autoneg_progress,
484 e1000_serdes_link_autoneg_complete,
485 e1000_serdes_link_forced_up
486};
487
bc7f75fa
AK		 488/* Receive Descriptor */
489struct e1000_rx_desc {
a39fe742
AV		 490 __le64 buffer_addr; /* Address of the descriptor's data buffer */
491 __le16 length; /* Length of data DMAed into data buffer */
492 __le16 csum; /* Packet checksum */
bc7f75fa
AK		 493 u8 status; /* Descriptor status */
494 u8 errors; /* Descriptor Errors */
a39fe742 495 __le16 special;
bc7f75fa
AK		 496};
497
498/* Receive Descriptor - Extended */
499union e1000_rx_desc_extended {
500 struct {
a39fe742
AV		 501 __le64 buffer_addr;
502 __le64 reserved;
bc7f75fa
AK		 503 } read;
504 struct {
505 struct {
a39fe742 506 __le32 mrq; /* Multiple Rx Queues */
bc7f75fa 507 union {
a39fe742 508 __le32 rss; /* RSS Hash */
bc7f75fa 509 struct {
a39fe742
AV		 510 __le16 ip_id; /* IP id */
511 __le16 csum; /* Packet Checksum */
bc7f75fa
AK		 512 } csum_ip;
513 } hi_dword;
514 } lower;
515 struct {
a39fe742
AV		 516 __le32 status_error; /* ext status/error */
517 __le16 length;
518 __le16 vlan; /* VLAN tag */
bc7f75fa
AK		 519 } upper;
520 } wb; /* writeback */
521};
522
523#define MAX_PS_BUFFERS 4
524/* Receive Descriptor - Packet Split */
525union e1000_rx_desc_packet_split {
526 struct {
527 /* one buffer for protocol header(s), three data buffers */
a39fe742 528 __le64 buffer_addr[MAX_PS_BUFFERS];
bc7f75fa
AK		 529 } read;
530 struct {
531 struct {
a39fe742 532 __le32 mrq; /* Multiple Rx Queues */
bc7f75fa 533 union {
a39fe742 534 __le32 rss; /* RSS Hash */
bc7f75fa 535 struct {
a39fe742
AV		 536 __le16 ip_id; /* IP id */
537 __le16 csum; /* Packet Checksum */
bc7f75fa
AK		 538 } csum_ip;
539 } hi_dword;
540 } lower;
541 struct {
a39fe742
AV		 542 __le32 status_error; /* ext status/error */
543 __le16 length0; /* length of buffer 0 */
544 __le16 vlan; /* VLAN tag */
bc7f75fa
AK		 545 } middle;
546 struct {
a39fe742
AV		 547 __le16 header_status;
548 __le16 length[3]; /* length of buffers 1-3 */
bc7f75fa 549 } upper;
a39fe742 550 __le64 reserved;
bc7f75fa
AK		 551 } wb; /* writeback */
552};
553
554/* Transmit Descriptor */
555struct e1000_tx_desc {
a39fe742 556 __le64 buffer_addr; /* Address of the descriptor's data buffer */
bc7f75fa 557 union {
a39fe742 558 __le32 data;
bc7f75fa 559 struct {
a39fe742 560 __le16 length; /* Data buffer length */
bc7f75fa
AK		 561 u8 cso; /* Checksum offset */
562 u8 cmd; /* Descriptor control */
563 } flags;
564 } lower;
565 union {
a39fe742 566 __le32 data;
bc7f75fa
AK		 567 struct {
568 u8 status; /* Descriptor status */
569 u8 css; /* Checksum start */
a39fe742 570 __le16 special;
bc7f75fa
AK		 571 } fields;
572 } upper;
573};
574
575/* Offload Context Descriptor */
576struct e1000_context_desc {
577 union {
a39fe742 578 __le32 ip_config;
bc7f75fa
AK		 579 struct {
580 u8 ipcss; /* IP checksum start */
581 u8 ipcso; /* IP checksum offset */
a39fe742 582 __le16 ipcse; /* IP checksum end */
bc7f75fa
AK		 583 } ip_fields;
584 } lower_setup;
585 union {
a39fe742 586 __le32 tcp_config;
bc7f75fa
AK		 587 struct {
588 u8 tucss; /* TCP checksum start */
589 u8 tucso; /* TCP checksum offset */
a39fe742 590 __le16 tucse; /* TCP checksum end */
bc7f75fa
AK		 591 } tcp_fields;
592 } upper_setup;
a39fe742 593 __le32 cmd_and_length;
bc7f75fa 594 union {
a39fe742 595 __le32 data;
bc7f75fa
AK		 596 struct {
597 u8 status; /* Descriptor status */
598 u8 hdr_len; /* Header length */
a39fe742 599 __le16 mss; /* Maximum segment size */
bc7f75fa
AK		 600 } fields;
601 } tcp_seg_setup;
602};
603
604/* Offload data descriptor */
605struct e1000_data_desc {
a39fe742 606 __le64 buffer_addr; /* Address of the descriptor's buffer address */
bc7f75fa 607 union {
a39fe742 608 __le32 data;
bc7f75fa 609 struct {
a39fe742 610 __le16 length; /* Data buffer length */
bc7f75fa
AK		 611 u8 typ_len_ext;
612 u8 cmd;
613 } flags;
614 } lower;
615 union {
a39fe742 616 __le32 data;
bc7f75fa
AK		 617 struct {
618 u8 status; /* Descriptor status */
619 u8 popts; /* Packet Options */
a39fe742 620 __le16 special; /* */
bc7f75fa
AK		 621 } fields;
622 } upper;
623};
624
625/* Statistics counters collected by the MAC */
626struct e1000_hw_stats {
627 u64 crcerrs;
628 u64 algnerrc;
629 u64 symerrs;
630 u64 rxerrc;
631 u64 mpc;
632 u64 scc;
633 u64 ecol;
634 u64 mcc;
635 u64 latecol;
636 u64 colc;
637 u64 dc;
638 u64 tncrs;
639 u64 sec;
640 u64 cexterr;
641 u64 rlec;
642 u64 xonrxc;
643 u64 xontxc;
644 u64 xoffrxc;
645 u64 xofftxc;
646 u64 fcruc;
647 u64 prc64;
648 u64 prc127;
649 u64 prc255;
650 u64 prc511;
651 u64 prc1023;
652 u64 prc1522;
653 u64 gprc;
654 u64 bprc;
655 u64 mprc;
656 u64 gptc;
7c25769f
BA		 657 u64 gorc;
658 u64 gotc;
bc7f75fa
AK		 659 u64 rnbc;
660 u64 ruc;
661 u64 rfc;
662 u64 roc;
663 u64 rjc;
664 u64 mgprc;
665 u64 mgpdc;
666 u64 mgptc;
7c25769f
BA		 667 u64 tor;
668 u64 tot;
bc7f75fa
AK		 669 u64 tpr;
670 u64 tpt;
671 u64 ptc64;
672 u64 ptc127;
673 u64 ptc255;
674 u64 ptc511;
675 u64 ptc1023;
676 u64 ptc1522;
677 u64 mptc;
678 u64 bptc;
679 u64 tsctc;
680 u64 tsctfc;
681 u64 iac;
682 u64 icrxptc;
683 u64 icrxatc;
684 u64 ictxptc;
685 u64 ictxatc;
686 u64 ictxqec;
687 u64 ictxqmtc;
688 u64 icrxdmtc;
689 u64 icrxoc;
690};
691
692struct e1000_phy_stats {
693 u32 idle_errors;
694 u32 receive_errors;
695};
696
697struct e1000_host_mng_dhcp_cookie {
698 u32 signature;
699 u8 status;
700 u8 reserved0;
701 u16 vlan_id;
702 u32 reserved1;
703 u16 reserved2;
704 u8 reserved3;
705 u8 checksum;
706};
707
708/* Host Interface "Rev 1" */
709struct e1000_host_command_header {
710 u8 command_id;
711 u8 command_length;
712 u8 command_options;
713 u8 checksum;
714};
715
716#define E1000_HI_MAX_DATA_LENGTH 252
717struct e1000_host_command_info {
718 struct e1000_host_command_header command_header;
719 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
720};
721
722/* Host Interface "Rev 2" */
723struct e1000_host_mng_command_header {
724 u8 command_id;
725 u8 checksum;
726 u16 reserved1;
727 u16 reserved2;
728 u16 command_length;
729};
730
731#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
732struct e1000_host_mng_command_info {
733 struct e1000_host_mng_command_header command_header;
734 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
735};
736
737/* Function pointers and static data for the MAC. */
738struct e1000_mac_operations {
a4f58f54 739 s32 (*id_led_init)(struct e1000_hw *);
4662e82b 740 bool (*check_mng_mode)(struct e1000_hw *);
bc7f75fa
AK		 741 s32 (*check_for_link)(struct e1000_hw *);
742 s32 (*cleanup_led)(struct e1000_hw *);
743 void (*clear_hw_cntrs)(struct e1000_hw *);
744 s32 (*get_bus_info)(struct e1000_hw *);
745 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
746 s32 (*led_on)(struct e1000_hw *);
747 s32 (*led_off)(struct e1000_hw *);
e2de3eb6 748 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32, u32, u32);
bc7f75fa
AK		 749 s32 (*reset_hw)(struct e1000_hw *);
750 s32 (*init_hw)(struct e1000_hw *);
751 s32 (*setup_link)(struct e1000_hw *);
752 s32 (*setup_physical_interface)(struct e1000_hw *);
a4f58f54 753 s32 (*setup_led)(struct e1000_hw *);
bc7f75fa
AK		 754};
755
756/* Function pointers for the PHY. */
757struct e1000_phy_operations {
758 s32 (*acquire_phy)(struct e1000_hw *);
a4f58f54 759 s32 (*check_polarity)(struct e1000_hw *);
bc7f75fa
AK		 760 s32 (*check_reset_block)(struct e1000_hw *);
761 s32 (*commit_phy)(struct e1000_hw *);
762 s32 (*force_speed_duplex)(struct e1000_hw *);
763 s32 (*get_cfg_done)(struct e1000_hw *hw);
764 s32 (*get_cable_length)(struct e1000_hw *);
765 s32 (*get_phy_info)(struct e1000_hw *);
766 s32 (*read_phy_reg)(struct e1000_hw *, u32, u16 *);
767 void (*release_phy)(struct e1000_hw *);
768 s32 (*reset_phy)(struct e1000_hw *);
769 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
770 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
771 s32 (*write_phy_reg)(struct e1000_hw *, u32, u16);
75eb0fad 772 s32 (*cfg_on_link_up)(struct e1000_hw *);
bc7f75fa
AK		 773};
774
775/* Function pointers for the NVM. */
776struct e1000_nvm_operations {
777 s32 (*acquire_nvm)(struct e1000_hw *);
778 s32 (*read_nvm)(struct e1000_hw *, u16, u16, u16 *);
779 void (*release_nvm)(struct e1000_hw *);
780 s32 (*update_nvm)(struct e1000_hw *);
781 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
782 s32 (*validate_nvm)(struct e1000_hw *);
783 s32 (*write_nvm)(struct e1000_hw *, u16, u16, u16 *);
784};
785
786struct e1000_mac_info {
787 struct e1000_mac_operations ops;
788
789 u8 addr[6];
790 u8 perm_addr[6];
791
792 enum e1000_mac_type type;
bc7f75fa
AK		 793
794 u32 collision_delta;
795 u32 ledctl_default;
796 u32 ledctl_mode1;
797 u32 ledctl_mode2;
bc7f75fa 798 u32 mc_filter_type;
bc7f75fa
AK		 799 u32 tx_packet_delta;
800 u32 txcw;
801
802 u16 current_ifs_val;
803 u16 ifs_max_val;
804 u16 ifs_min_val;
805 u16 ifs_ratio;
806 u16 ifs_step_size;
807 u16 mta_reg_count;
808 u16 rar_entry_count;
bc7f75fa
AK		 809
810 u8 forced_speed_duplex;
811
812 bool arc_subsystem_valid;
813 bool autoneg;
814 bool autoneg_failed;
815 bool get_link_status;
816 bool in_ifs_mode;
817 bool serdes_has_link;
818 bool tx_pkt_filtering;
c9523379 819 enum e1000_serdes_link_state serdes_link_state;
bc7f75fa
AK		 820};
821
822struct e1000_phy_info {
823 struct e1000_phy_operations ops;
824
825 enum e1000_phy_type type;
826
827 enum e1000_1000t_rx_status local_rx;
828 enum e1000_1000t_rx_status remote_rx;
829 enum e1000_ms_type ms_type;
830 enum e1000_ms_type original_ms_type;
831 enum e1000_rev_polarity cable_polarity;
832 enum e1000_smart_speed smart_speed;
833
834 u32 addr;
835 u32 id;
836 u32 reset_delay_us; /* in usec */
837 u32 revision;
838
318a94d6
JK		 839 enum e1000_media_type media_type;
840
bc7f75fa
AK		 841 u16 autoneg_advertised;
842 u16 autoneg_mask;
843 u16 cable_length;
844 u16 max_cable_length;
845 u16 min_cable_length;
846
847 u8 mdix;
848
849 bool disable_polarity_correction;
850 bool is_mdix;
851 bool polarity_correction;
852 bool speed_downgraded;
318a94d6 853 bool autoneg_wait_to_complete;
bc7f75fa
AK		 854};
855
856struct e1000_nvm_info {
857 struct e1000_nvm_operations ops;
858
859 enum e1000_nvm_type type;
860 enum e1000_nvm_override override;
861
862 u32 flash_bank_size;
863 u32 flash_base_addr;
864
865 u16 word_size;
866 u16 delay_usec;
867 u16 address_bits;
868 u16 opcode_bits;
869 u16 page_size;
870};
871
872struct e1000_bus_info {
873 enum e1000_bus_width width;
874
875 u16 func;
876};
877
318a94d6
JK		 878struct e1000_fc_info {
879 u32 high_water; /* Flow control high-water mark */
880 u32 low_water; /* Flow control low-water mark */
881 u16 pause_time; /* Flow control pause timer */
882 bool send_xon; /* Flow control send XON */
883 bool strict_ieee; /* Strict IEEE mode */
5c48ef3e
BA		 884 enum e1000_fc_mode current_mode; /* FC mode in effect */
885 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
318a94d6
JK		 886};
887
bc7f75fa
AK		 888struct e1000_dev_spec_82571 {
889 bool laa_is_present;
93ca1610 890 bool alt_mac_addr_is_present;
23a2d1b2 891 u32 smb_counter;
bc7f75fa
AK		 892};
893
894struct e1000_shadow_ram {
895 u16 value;
896 bool modified;
897};
898
899#define E1000_ICH8_SHADOW_RAM_WORDS 2048
900
901struct e1000_dev_spec_ich8lan {
902 bool kmrn_lock_loss_workaround_enabled;
903 struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
904};
905
906struct e1000_hw {
907 struct e1000_adapter *adapter;
908
909 u8 __iomem *hw_addr;
910 u8 __iomem *flash_address;
911
912 struct e1000_mac_info mac;
318a94d6 913 struct e1000_fc_info fc;
bc7f75fa
AK		 914 struct e1000_phy_info phy;
915 struct e1000_nvm_info nvm;
916 struct e1000_bus_info bus;
917 struct e1000_host_mng_dhcp_cookie mng_cookie;
918
919 union {
920 struct e1000_dev_spec_82571 e82571;
921 struct e1000_dev_spec_ich8lan ich8lan;
922 } dev_spec;
bc7f75fa
AK		 923};
924
925#ifdef DEBUG
926#define hw_dbg(hw, format, arg...) \
121244a7 927 printk(KERN_DEBUG "%s: " format, e1000e_get_hw_dev_name(hw), ##arg)
bc7f75fa
AK		 928#else
929static inline int __attribute__ ((format (printf, 2, 3)))
930hw_dbg(struct e1000_hw *hw, const char *format, ...)
931{
932 return 0;
933}
934#endif
935
936#endif
kernel source for telekom puls (alcatel/mediatek)