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[PATCH] e1000: Cleaned up code and removed hard coded numbers
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / net / e1000 / e1000_main.c
CommitLineData
1da177e4
LT		 1/*******************************************************************************
2
3
2648345f 4 Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
1da177e4
LT		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include "e1000.h"
30
31/* Change Log
2b02893e
MC		 32 * 6.0.58 4/20/05
33 * o Accepted ethtool cleanup patch from Stephen Hemminger
2648345f
MC		 34 * 6.0.44+ 2/15/05
35 * o applied Anton's patch to resolve tx hang in hardware
36 * o Applied Andrew Mortons patch - e1000 stops working after resume
1da177e4
LT		 37 */
38
39char e1000_driver_name[] = "e1000";
3ad2cc67 40static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
1da177e4
LT		 41#ifndef CONFIG_E1000_NAPI
42#define DRIVERNAPI
43#else
44#define DRIVERNAPI "-NAPI"
45#endif
4ee9c020 46#define DRV_VERSION "6.3.9-k2"DRIVERNAPI
1da177e4 47char e1000_driver_version[] = DRV_VERSION;
3ad2cc67 48static char e1000_copyright[] = "Copyright (c) 1999-2005 Intel Corporation.";
1da177e4
LT		 49
50/* e1000_pci_tbl - PCI Device ID Table
51 *
52 * Last entry must be all 0s
53 *
54 * Macro expands to...
55 * {PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)}
56 */
57static struct pci_device_id e1000_pci_tbl[] = {
58 INTEL_E1000_ETHERNET_DEVICE(0x1000),
59 INTEL_E1000_ETHERNET_DEVICE(0x1001),
60 INTEL_E1000_ETHERNET_DEVICE(0x1004),
61 INTEL_E1000_ETHERNET_DEVICE(0x1008),
62 INTEL_E1000_ETHERNET_DEVICE(0x1009),
63 INTEL_E1000_ETHERNET_DEVICE(0x100C),
64 INTEL_E1000_ETHERNET_DEVICE(0x100D),
65 INTEL_E1000_ETHERNET_DEVICE(0x100E),
66 INTEL_E1000_ETHERNET_DEVICE(0x100F),
67 INTEL_E1000_ETHERNET_DEVICE(0x1010),
68 INTEL_E1000_ETHERNET_DEVICE(0x1011),
69 INTEL_E1000_ETHERNET_DEVICE(0x1012),
70 INTEL_E1000_ETHERNET_DEVICE(0x1013),
71 INTEL_E1000_ETHERNET_DEVICE(0x1014),
72 INTEL_E1000_ETHERNET_DEVICE(0x1015),
73 INTEL_E1000_ETHERNET_DEVICE(0x1016),
74 INTEL_E1000_ETHERNET_DEVICE(0x1017),
75 INTEL_E1000_ETHERNET_DEVICE(0x1018),
76 INTEL_E1000_ETHERNET_DEVICE(0x1019),
2648345f 77 INTEL_E1000_ETHERNET_DEVICE(0x101A),
1da177e4
LT		 78 INTEL_E1000_ETHERNET_DEVICE(0x101D),
79 INTEL_E1000_ETHERNET_DEVICE(0x101E),
80 INTEL_E1000_ETHERNET_DEVICE(0x1026),
81 INTEL_E1000_ETHERNET_DEVICE(0x1027),
82 INTEL_E1000_ETHERNET_DEVICE(0x1028),
07b8fede
MC		 83 INTEL_E1000_ETHERNET_DEVICE(0x105E),
84 INTEL_E1000_ETHERNET_DEVICE(0x105F),
85 INTEL_E1000_ETHERNET_DEVICE(0x1060),
1da177e4
LT		 86 INTEL_E1000_ETHERNET_DEVICE(0x1075),
87 INTEL_E1000_ETHERNET_DEVICE(0x1076),
88 INTEL_E1000_ETHERNET_DEVICE(0x1077),
89 INTEL_E1000_ETHERNET_DEVICE(0x1078),
90 INTEL_E1000_ETHERNET_DEVICE(0x1079),
91 INTEL_E1000_ETHERNET_DEVICE(0x107A),
92 INTEL_E1000_ETHERNET_DEVICE(0x107B),
93 INTEL_E1000_ETHERNET_DEVICE(0x107C),
07b8fede
MC		 94 INTEL_E1000_ETHERNET_DEVICE(0x107D),
95 INTEL_E1000_ETHERNET_DEVICE(0x107E),
96 INTEL_E1000_ETHERNET_DEVICE(0x107F),
1da177e4 97 INTEL_E1000_ETHERNET_DEVICE(0x108A),
2648345f
MC		 98 INTEL_E1000_ETHERNET_DEVICE(0x108B),
99 INTEL_E1000_ETHERNET_DEVICE(0x108C),
b7ee49db 100 INTEL_E1000_ETHERNET_DEVICE(0x1099),
07b8fede 101 INTEL_E1000_ETHERNET_DEVICE(0x109A),
b7ee49db 102 INTEL_E1000_ETHERNET_DEVICE(0x10B5),
1da177e4
LT		 103 /* required last entry */
104 {0,}
105};
106
107MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
108
109int e1000_up(struct e1000_adapter *adapter);
110void e1000_down(struct e1000_adapter *adapter);
111void e1000_reset(struct e1000_adapter *adapter);
112int e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx);
581d708e
MC		 113int e1000_setup_all_tx_resources(struct e1000_adapter *adapter);
114int e1000_setup_all_rx_resources(struct e1000_adapter *adapter);
115void e1000_free_all_tx_resources(struct e1000_adapter *adapter);
116void e1000_free_all_rx_resources(struct e1000_adapter *adapter);
3ad2cc67
AB		 117static int e1000_setup_tx_resources(struct e1000_adapter *adapter,
118 struct e1000_tx_ring *txdr);
119static int e1000_setup_rx_resources(struct e1000_adapter *adapter,
120 struct e1000_rx_ring *rxdr);
121static void e1000_free_tx_resources(struct e1000_adapter *adapter,
122 struct e1000_tx_ring *tx_ring);
123static void e1000_free_rx_resources(struct e1000_adapter *adapter,
124 struct e1000_rx_ring *rx_ring);
1da177e4
LT		 125void e1000_update_stats(struct e1000_adapter *adapter);
126
127/* Local Function Prototypes */
128
129static int e1000_init_module(void);
130static void e1000_exit_module(void);
131static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
132static void __devexit e1000_remove(struct pci_dev *pdev);
581d708e
MC		 133static int e1000_alloc_queues(struct e1000_adapter *adapter);
134#ifdef CONFIG_E1000_MQ
135static void e1000_setup_queue_mapping(struct e1000_adapter *adapter);
136#endif
1da177e4
LT		 137static int e1000_sw_init(struct e1000_adapter *adapter);
138static int e1000_open(struct net_device *netdev);
139static int e1000_close(struct net_device *netdev);
140static void e1000_configure_tx(struct e1000_adapter *adapter);
141static void e1000_configure_rx(struct e1000_adapter *adapter);
142static void e1000_setup_rctl(struct e1000_adapter *adapter);
581d708e
MC		 143static void e1000_clean_all_tx_rings(struct e1000_adapter *adapter);
144static void e1000_clean_all_rx_rings(struct e1000_adapter *adapter);
145static void e1000_clean_tx_ring(struct e1000_adapter *adapter,
146 struct e1000_tx_ring *tx_ring);
147static void e1000_clean_rx_ring(struct e1000_adapter *adapter,
148 struct e1000_rx_ring *rx_ring);
1da177e4
LT		 149static void e1000_set_multi(struct net_device *netdev);
150static void e1000_update_phy_info(unsigned long data);
151static void e1000_watchdog(unsigned long data);
152static void e1000_watchdog_task(struct e1000_adapter *adapter);
153static void e1000_82547_tx_fifo_stall(unsigned long data);
154static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
155static struct net_device_stats * e1000_get_stats(struct net_device *netdev);
156static int e1000_change_mtu(struct net_device *netdev, int new_mtu);
157static int e1000_set_mac(struct net_device *netdev, void *p);
158static irqreturn_t e1000_intr(int irq, void *data, struct pt_regs *regs);
581d708e
MC		 159static boolean_t e1000_clean_tx_irq(struct e1000_adapter *adapter,
160 struct e1000_tx_ring *tx_ring);
1da177e4 161#ifdef CONFIG_E1000_NAPI
581d708e 162static int e1000_clean(struct net_device *poll_dev, int *budget);
1da177e4 163static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
581d708e 164 struct e1000_rx_ring *rx_ring,
1da177e4 165 int *work_done, int work_to_do);
2d7edb92 166static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
581d708e 167 struct e1000_rx_ring *rx_ring,
2d7edb92 168 int *work_done, int work_to_do);
1da177e4 169#else
581d708e
MC		 170static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
171 struct e1000_rx_ring *rx_ring);
172static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
173 struct e1000_rx_ring *rx_ring);
1da177e4 174#endif
581d708e 175static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
72d64a43
JK		 176 struct e1000_rx_ring *rx_ring,
177 int cleaned_count);
581d708e 178static void e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
72d64a43
JK		 179 struct e1000_rx_ring *rx_ring,
180 int cleaned_count);
1da177e4
LT		 181static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
182static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
183 int cmd);
184void e1000_set_ethtool_ops(struct net_device *netdev);
185static void e1000_enter_82542_rst(struct e1000_adapter *adapter);
186static void e1000_leave_82542_rst(struct e1000_adapter *adapter);
187static void e1000_tx_timeout(struct net_device *dev);
188static void e1000_tx_timeout_task(struct net_device *dev);
189static void e1000_smartspeed(struct e1000_adapter *adapter);
190static inline int e1000_82547_fifo_workaround(struct e1000_adapter *adapter,
191 struct sk_buff *skb);
192
193static void e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp);
194static void e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid);
195static void e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
196static void e1000_restore_vlan(struct e1000_adapter *adapter);
197
1da177e4 198#ifdef CONFIG_PM
977e74b5 199static int e1000_suspend(struct pci_dev *pdev, pm_message_t state);
1da177e4
LT		 200static int e1000_resume(struct pci_dev *pdev);
201#endif
202
203#ifdef CONFIG_NET_POLL_CONTROLLER
204/* for netdump / net console */
205static void e1000_netpoll (struct net_device *netdev);
206#endif
207
24025e4e
MC		 208#ifdef CONFIG_E1000_MQ
209/* for multiple Rx queues */
210void e1000_rx_schedule(void *data);
211#endif
212
1da177e4
LT		 213/* Exported from other modules */
214
215extern void e1000_check_options(struct e1000_adapter *adapter);
216
217static struct pci_driver e1000_driver = {
218 .name = e1000_driver_name,
219 .id_table = e1000_pci_tbl,
220 .probe = e1000_probe,
221 .remove = __devexit_p(e1000_remove),
222 /* Power Managment Hooks */
223#ifdef CONFIG_PM
224 .suspend = e1000_suspend,
225 .resume = e1000_resume
226#endif
227};
228
229MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
230MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
231MODULE_LICENSE("GPL");
232MODULE_VERSION(DRV_VERSION);
233
234static int debug = NETIF_MSG_DRV | NETIF_MSG_PROBE;
235module_param(debug, int, 0);
236MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
237
238/**
239 * e1000_init_module - Driver Registration Routine
240 *
241 * e1000_init_module is the first routine called when the driver is
242 * loaded. All it does is register with the PCI subsystem.
243 **/
244
245static int __init
246e1000_init_module(void)
247{
248 int ret;
249 printk(KERN_INFO "%s - version %s\n",
250 e1000_driver_string, e1000_driver_version);
251
252 printk(KERN_INFO "%s\n", e1000_copyright);
253
254 ret = pci_module_init(&e1000_driver);
8b378def 255
1da177e4
LT		 256 return ret;
257}
258
259module_init(e1000_init_module);
260
261/**
262 * e1000_exit_module - Driver Exit Cleanup Routine
263 *
264 * e1000_exit_module is called just before the driver is removed
265 * from memory.
266 **/
267
268static void __exit
269e1000_exit_module(void)
270{
1da177e4
LT		 271 pci_unregister_driver(&e1000_driver);
272}
273
274module_exit(e1000_exit_module);
275
276/**
277 * e1000_irq_disable - Mask off interrupt generation on the NIC
278 * @adapter: board private structure
279 **/
280
281static inline void
282e1000_irq_disable(struct e1000_adapter *adapter)
283{
284 atomic_inc(&adapter->irq_sem);
285 E1000_WRITE_REG(&adapter->hw, IMC, ~0);
286 E1000_WRITE_FLUSH(&adapter->hw);
287 synchronize_irq(adapter->pdev->irq);
288}
289
290/**
291 * e1000_irq_enable - Enable default interrupt generation settings
292 * @adapter: board private structure
293 **/
294
295static inline void
296e1000_irq_enable(struct e1000_adapter *adapter)
297{
298 if(likely(atomic_dec_and_test(&adapter->irq_sem))) {
299 E1000_WRITE_REG(&adapter->hw, IMS, IMS_ENABLE_MASK);
300 E1000_WRITE_FLUSH(&adapter->hw);
301 }
302}
3ad2cc67
AB		 303
304static void
2d7edb92
MC		 305e1000_update_mng_vlan(struct e1000_adapter *adapter)
306{
307 struct net_device *netdev = adapter->netdev;
308 uint16_t vid = adapter->hw.mng_cookie.vlan_id;
309 uint16_t old_vid = adapter->mng_vlan_id;
310 if(adapter->vlgrp) {
311 if(!adapter->vlgrp->vlan_devices[vid]) {
312 if(adapter->hw.mng_cookie.status &
313 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) {
314 e1000_vlan_rx_add_vid(netdev, vid);
315 adapter->mng_vlan_id = vid;
316 } else
317 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
318
319 if((old_vid != (uint16_t)E1000_MNG_VLAN_NONE) &&
320 (vid != old_vid) &&
321 !adapter->vlgrp->vlan_devices[old_vid])
322 e1000_vlan_rx_kill_vid(netdev, old_vid);
323 }
324 }
325}
b55ccb35
JK		 326
327/**
328 * e1000_release_hw_control - release control of the h/w to f/w
329 * @adapter: address of board private structure
330 *
331 * e1000_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
332 * For ASF and Pass Through versions of f/w this means that the
333 * driver is no longer loaded. For AMT version (only with 82573) i
334 * of the f/w this means that the netowrk i/f is closed.
335 *
336 **/
337
338static inline void
339e1000_release_hw_control(struct e1000_adapter *adapter)
340{
341 uint32_t ctrl_ext;
342 uint32_t swsm;
343
344 /* Let firmware taken over control of h/w */
345 switch (adapter->hw.mac_type) {
346 case e1000_82571:
347 case e1000_82572:
348 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
349 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
350 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
351 break;
352 case e1000_82573:
353 swsm = E1000_READ_REG(&adapter->hw, SWSM);
354 E1000_WRITE_REG(&adapter->hw, SWSM,
355 swsm & ~E1000_SWSM_DRV_LOAD);
356 default:
357 break;
358 }
359}
360
361/**
362 * e1000_get_hw_control - get control of the h/w from f/w
363 * @adapter: address of board private structure
364 *
365 * e1000_get_hw_control sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
366 * For ASF and Pass Through versions of f/w this means that
367 * the driver is loaded. For AMT version (only with 82573)
368 * of the f/w this means that the netowrk i/f is open.
369 *
370 **/
371
372static inline void
373e1000_get_hw_control(struct e1000_adapter *adapter)
374{
375 uint32_t ctrl_ext;
376 uint32_t swsm;
377 /* Let firmware know the driver has taken over */
378 switch (adapter->hw.mac_type) {
379 case e1000_82571:
380 case e1000_82572:
381 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
382 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
383 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
384 break;
385 case e1000_82573:
386 swsm = E1000_READ_REG(&adapter->hw, SWSM);
387 E1000_WRITE_REG(&adapter->hw, SWSM,
388 swsm | E1000_SWSM_DRV_LOAD);
389 break;
390 default:
391 break;
392 }
393}
394
1da177e4
LT		 395int
396e1000_up(struct e1000_adapter *adapter)
397{
398 struct net_device *netdev = adapter->netdev;
581d708e 399 int i, err;
1da177e4
LT		 400
401 /* hardware has been reset, we need to reload some things */
402
403 /* Reset the PHY if it was previously powered down */
404 if(adapter->hw.media_type == e1000_media_type_copper) {
405 uint16_t mii_reg;
406 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
407 if(mii_reg & MII_CR_POWER_DOWN)
408 e1000_phy_reset(&adapter->hw);
409 }
410
411 e1000_set_multi(netdev);
412
413 e1000_restore_vlan(adapter);
414
415 e1000_configure_tx(adapter);
416 e1000_setup_rctl(adapter);
417 e1000_configure_rx(adapter);
72d64a43
JK		 418 /* call E1000_DESC_UNUSED which always leaves
419 * at least 1 descriptor unused to make sure
420 * next_to_use != next_to_clean */
f56799ea 421 for (i = 0; i < adapter->num_rx_queues; i++) {
72d64a43 422 struct e1000_rx_ring *ring = &adapter->rx_ring[i];
a292ca6e
JK		 423 adapter->alloc_rx_buf(adapter, ring,
424 E1000_DESC_UNUSED(ring));
f56799ea 425 }
1da177e4 426
fa4f7ef3
MC		 427#ifdef CONFIG_PCI_MSI
428 if(adapter->hw.mac_type > e1000_82547_rev_2) {
429 adapter->have_msi = TRUE;
430 if((err = pci_enable_msi(adapter->pdev))) {
431 DPRINTK(PROBE, ERR,
432 "Unable to allocate MSI interrupt Error: %d\n", err);
433 adapter->have_msi = FALSE;
434 }
435 }
436#endif
1da177e4
LT		 437 if((err = request_irq(adapter->pdev->irq, &e1000_intr,
438 SA_SHIRQ | SA_SAMPLE_RANDOM,
2648345f
MC		 439 netdev->name, netdev))) {
440 DPRINTK(PROBE, ERR,
441 "Unable to allocate interrupt Error: %d\n", err);
1da177e4 442 return err;
2648345f 443 }
1da177e4 444
7bfa4816
JK		 445#ifdef CONFIG_E1000_MQ
446 e1000_setup_queue_mapping(adapter);
447#endif
448
449 adapter->tx_queue_len = netdev->tx_queue_len;
450
1da177e4 451 mod_timer(&adapter->watchdog_timer, jiffies);
1da177e4
LT		 452
453#ifdef CONFIG_E1000_NAPI
454 netif_poll_enable(netdev);
455#endif
5de55624
MC		 456 e1000_irq_enable(adapter);
457
1da177e4
LT		 458 return 0;
459}
460
461void
462e1000_down(struct e1000_adapter *adapter)
463{
464 struct net_device *netdev = adapter->netdev;
57128197
JK		 465 boolean_t mng_mode_enabled = (adapter->hw.mac_type >= e1000_82571) &&
466 e1000_check_mng_mode(&adapter->hw);
1da177e4
LT		 467
468 e1000_irq_disable(adapter);
24025e4e
MC		 469#ifdef CONFIG_E1000_MQ
470 while (atomic_read(&adapter->rx_sched_call_data.count) != 0);
471#endif
1da177e4 472 free_irq(adapter->pdev->irq, netdev);
fa4f7ef3
MC		 473#ifdef CONFIG_PCI_MSI
474 if(adapter->hw.mac_type > e1000_82547_rev_2 &&
475 adapter->have_msi == TRUE)
476 pci_disable_msi(adapter->pdev);
477#endif
1da177e4
LT		 478 del_timer_sync(&adapter->tx_fifo_stall_timer);
479 del_timer_sync(&adapter->watchdog_timer);
480 del_timer_sync(&adapter->phy_info_timer);
481
482#ifdef CONFIG_E1000_NAPI
483 netif_poll_disable(netdev);
484#endif
7bfa4816 485 netdev->tx_queue_len = adapter->tx_queue_len;
1da177e4
LT		 486 adapter->link_speed = 0;
487 adapter->link_duplex = 0;
488 netif_carrier_off(netdev);
489 netif_stop_queue(netdev);
490
491 e1000_reset(adapter);
581d708e
MC		 492 e1000_clean_all_tx_rings(adapter);
493 e1000_clean_all_rx_rings(adapter);
1da177e4 494
57128197
JK		 495 /* Power down the PHY so no link is implied when interface is down *
496 * The PHY cannot be powered down if any of the following is TRUE *
497 * (a) WoL is enabled
498 * (b) AMT is active
499 * (c) SoL/IDER session is active */
500 if (!adapter->wol && adapter->hw.mac_type >= e1000_82540 &&
2d7edb92 501 adapter->hw.media_type == e1000_media_type_copper &&
57128197
JK		 502 !(E1000_READ_REG(&adapter->hw, MANC) & E1000_MANC_SMBUS_EN) &&
503 !mng_mode_enabled &&
504 !e1000_check_phy_reset_block(&adapter->hw)) {
1da177e4
LT		 505 uint16_t mii_reg;
506 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
507 mii_reg |= MII_CR_POWER_DOWN;
508 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
4e48a2b9 509 mdelay(1);
1da177e4
LT		 510 }
511}
512
513void
514e1000_reset(struct e1000_adapter *adapter)
515{
2d7edb92 516 uint32_t pba, manc;
1125ecbc 517 uint16_t fc_high_water_mark = E1000_FC_HIGH_DIFF;
1da177e4
LT		 518
519 /* Repartition Pba for greater than 9k mtu
520 * To take effect CTRL.RST is required.
521 */
522
2d7edb92
MC		 523 switch (adapter->hw.mac_type) {
524 case e1000_82547:
0e6ef3e0 525 case e1000_82547_rev_2:
2d7edb92
MC		 526 pba = E1000_PBA_30K;
527 break;
868d5309
MC		 528 case e1000_82571:
529 case e1000_82572:
530 pba = E1000_PBA_38K;
531 break;
2d7edb92
MC		 532 case e1000_82573:
533 pba = E1000_PBA_12K;
534 break;
535 default:
536 pba = E1000_PBA_48K;
537 break;
538 }
539
1125ecbc 540 if((adapter->hw.mac_type != e1000_82573) &&
f11b7f85 541 (adapter->netdev->mtu > E1000_RXBUFFER_8192))
1125ecbc 542 pba -= 8; /* allocate more FIFO for Tx */
2d7edb92
MC		 543
544
545 if(adapter->hw.mac_type == e1000_82547) {
1da177e4
LT		 546 adapter->tx_fifo_head = 0;
547 adapter->tx_head_addr = pba << E1000_TX_HEAD_ADDR_SHIFT;
548 adapter->tx_fifo_size =
549 (E1000_PBA_40K - pba) << E1000_PBA_BYTES_SHIFT;
550 atomic_set(&adapter->tx_fifo_stall, 0);
551 }
2d7edb92 552
1da177e4
LT		 553 E1000_WRITE_REG(&adapter->hw, PBA, pba);
554
555 /* flow control settings */
f11b7f85
JK		 556 /* Set the FC high water mark to 90% of the FIFO size.
557 * Required to clear last 3 LSB */
558 fc_high_water_mark = ((pba * 9216)/10) & 0xFFF8;
559
560 adapter->hw.fc_high_water = fc_high_water_mark;
561 adapter->hw.fc_low_water = fc_high_water_mark - 8;
1da177e4
LT		 562 adapter->hw.fc_pause_time = E1000_FC_PAUSE_TIME;
563 adapter->hw.fc_send_xon = 1;
564 adapter->hw.fc = adapter->hw.original_fc;
565
2d7edb92 566 /* Allow time for pending master requests to run */
1da177e4
LT		 567 e1000_reset_hw(&adapter->hw);
568 if(adapter->hw.mac_type >= e1000_82544)
569 E1000_WRITE_REG(&adapter->hw, WUC, 0);
570 if(e1000_init_hw(&adapter->hw))
571 DPRINTK(PROBE, ERR, "Hardware Error\n");
2d7edb92 572 e1000_update_mng_vlan(adapter);
1da177e4
LT		 573 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
574 E1000_WRITE_REG(&adapter->hw, VET, ETHERNET_IEEE_VLAN_TYPE);
575
576 e1000_reset_adaptive(&adapter->hw);
577 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
2d7edb92
MC		 578 if (adapter->en_mng_pt) {
579 manc = E1000_READ_REG(&adapter->hw, MANC);
580 manc |= (E1000_MANC_ARP_EN | E1000_MANC_EN_MNG2HOST);
581 E1000_WRITE_REG(&adapter->hw, MANC, manc);
582 }
1da177e4
LT		 583}
584
585/**
586 * e1000_probe - Device Initialization Routine
587 * @pdev: PCI device information struct
588 * @ent: entry in e1000_pci_tbl
589 *
590 * Returns 0 on success, negative on failure
591 *
592 * e1000_probe initializes an adapter identified by a pci_dev structure.
593 * The OS initialization, configuring of the adapter private structure,
594 * and a hardware reset occur.
595 **/
596
597static int __devinit
598e1000_probe(struct pci_dev *pdev,
599 const struct pci_device_id *ent)
600{
601 struct net_device *netdev;
602 struct e1000_adapter *adapter;
2d7edb92 603 unsigned long mmio_start, mmio_len;
2d7edb92 604
1da177e4 605 static int cards_found = 0;
2d7edb92 606 int i, err, pci_using_dac;
1da177e4
LT		 607 uint16_t eeprom_data;
608 uint16_t eeprom_apme_mask = E1000_EEPROM_APME;
1da177e4
LT		 609 if((err = pci_enable_device(pdev)))
610 return err;
611
612 if(!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
613 pci_using_dac = 1;
614 } else {
615 if((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
616 E1000_ERR("No usable DMA configuration, aborting\n");
617 return err;
618 }
619 pci_using_dac = 0;
620 }
621
622 if((err = pci_request_regions(pdev, e1000_driver_name)))
623 return err;
624
625 pci_set_master(pdev);
626
627 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
628 if(!netdev) {
629 err = -ENOMEM;
630 goto err_alloc_etherdev;
631 }
632
633 SET_MODULE_OWNER(netdev);
634 SET_NETDEV_DEV(netdev, &pdev->dev);
635
636 pci_set_drvdata(pdev, netdev);
60490fe0 637 adapter = netdev_priv(netdev);
1da177e4
LT		 638 adapter->netdev = netdev;
639 adapter->pdev = pdev;
640 adapter->hw.back = adapter;
641 adapter->msg_enable = (1 << debug) - 1;
642
643 mmio_start = pci_resource_start(pdev, BAR_0);
644 mmio_len = pci_resource_len(pdev, BAR_0);
645
646 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
647 if(!adapter->hw.hw_addr) {
648 err = -EIO;
649 goto err_ioremap;
650 }
651
652 for(i = BAR_1; i <= BAR_5; i++) {
653 if(pci_resource_len(pdev, i) == 0)
654 continue;
655 if(pci_resource_flags(pdev, i) & IORESOURCE_IO) {
656 adapter->hw.io_base = pci_resource_start(pdev, i);
657 break;
658 }
659 }
660
661 netdev->open = &e1000_open;
662 netdev->stop = &e1000_close;
663 netdev->hard_start_xmit = &e1000_xmit_frame;
664 netdev->get_stats = &e1000_get_stats;
665 netdev->set_multicast_list = &e1000_set_multi;
666 netdev->set_mac_address = &e1000_set_mac;
667 netdev->change_mtu = &e1000_change_mtu;
668 netdev->do_ioctl = &e1000_ioctl;
669 e1000_set_ethtool_ops(netdev);
670 netdev->tx_timeout = &e1000_tx_timeout;
671 netdev->watchdog_timeo = 5 * HZ;
672#ifdef CONFIG_E1000_NAPI
673 netdev->poll = &e1000_clean;
674 netdev->weight = 64;
675#endif
676 netdev->vlan_rx_register = e1000_vlan_rx_register;
677 netdev->vlan_rx_add_vid = e1000_vlan_rx_add_vid;
678 netdev->vlan_rx_kill_vid = e1000_vlan_rx_kill_vid;
679#ifdef CONFIG_NET_POLL_CONTROLLER
680 netdev->poll_controller = e1000_netpoll;
681#endif
682 strcpy(netdev->name, pci_name(pdev));
683
684 netdev->mem_start = mmio_start;
685 netdev->mem_end = mmio_start + mmio_len;
686 netdev->base_addr = adapter->hw.io_base;
687
688 adapter->bd_number = cards_found;
689
690 /* setup the private structure */
691
692 if((err = e1000_sw_init(adapter)))
693 goto err_sw_init;
694
2d7edb92
MC		 695 if((err = e1000_check_phy_reset_block(&adapter->hw)))
696 DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n");
697
1da177e4
LT		 698 if(adapter->hw.mac_type >= e1000_82543) {
699 netdev->features = NETIF_F_SG |
700 NETIF_F_HW_CSUM |
701 NETIF_F_HW_VLAN_TX |
702 NETIF_F_HW_VLAN_RX |
703 NETIF_F_HW_VLAN_FILTER;
704 }
705
706#ifdef NETIF_F_TSO
707 if((adapter->hw.mac_type >= e1000_82544) &&
708 (adapter->hw.mac_type != e1000_82547))
709 netdev->features |= NETIF_F_TSO;
2d7edb92
MC		 710
711#ifdef NETIF_F_TSO_IPV6
712 if(adapter->hw.mac_type > e1000_82547_rev_2)
713 netdev->features |= NETIF_F_TSO_IPV6;
714#endif
1da177e4
LT		 715#endif
716 if(pci_using_dac)
717 netdev->features |= NETIF_F_HIGHDMA;
718
719 /* hard_start_xmit is safe against parallel locking */
720 netdev->features |= NETIF_F_LLTX;
721
2d7edb92
MC		 722 adapter->en_mng_pt = e1000_enable_mng_pass_thru(&adapter->hw);
723
1da177e4
LT		 724 /* before reading the EEPROM, reset the controller to
725 * put the device in a known good starting state */
726
727 e1000_reset_hw(&adapter->hw);
728
729 /* make sure the EEPROM is good */
730
731 if(e1000_validate_eeprom_checksum(&adapter->hw) < 0) {
732 DPRINTK(PROBE, ERR, "The EEPROM Checksum Is Not Valid\n");
733 err = -EIO;
734 goto err_eeprom;
735 }
736
737 /* copy the MAC address out of the EEPROM */
738
2648345f 739 if(e1000_read_mac_addr(&adapter->hw))
1da177e4
LT		 740 DPRINTK(PROBE, ERR, "EEPROM Read Error\n");
741 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
9beb0ac1 742 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
1da177e4 743
9beb0ac1 744 if(!is_valid_ether_addr(netdev->perm_addr)) {
1da177e4
LT		 745 DPRINTK(PROBE, ERR, "Invalid MAC Address\n");
746 err = -EIO;
747 goto err_eeprom;
748 }
749
750 e1000_read_part_num(&adapter->hw, &(adapter->part_num));
751
752 e1000_get_bus_info(&adapter->hw);
753
754 init_timer(&adapter->tx_fifo_stall_timer);
755 adapter->tx_fifo_stall_timer.function = &e1000_82547_tx_fifo_stall;
756 adapter->tx_fifo_stall_timer.data = (unsigned long) adapter;
757
758 init_timer(&adapter->watchdog_timer);
759 adapter->watchdog_timer.function = &e1000_watchdog;
760 adapter->watchdog_timer.data = (unsigned long) adapter;
761
762 INIT_WORK(&adapter->watchdog_task,
763 (void (*)(void *))e1000_watchdog_task, adapter);
764
765 init_timer(&adapter->phy_info_timer);
766 adapter->phy_info_timer.function = &e1000_update_phy_info;
767 adapter->phy_info_timer.data = (unsigned long) adapter;
768
769 INIT_WORK(&adapter->tx_timeout_task,
770 (void (*)(void *))e1000_tx_timeout_task, netdev);
771
772 /* we're going to reset, so assume we have no link for now */
773
774 netif_carrier_off(netdev);
775 netif_stop_queue(netdev);
776
777 e1000_check_options(adapter);
778
779 /* Initial Wake on LAN setting
780 * If APM wake is enabled in the EEPROM,
781 * enable the ACPI Magic Packet filter
782 */
783
784 switch(adapter->hw.mac_type) {
785 case e1000_82542_rev2_0:
786 case e1000_82542_rev2_1:
787 case e1000_82543:
788 break;
789 case e1000_82544:
790 e1000_read_eeprom(&adapter->hw,
791 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
792 eeprom_apme_mask = E1000_EEPROM_82544_APM;
793 break;
794 case e1000_82546:
795 case e1000_82546_rev_3:
fd803241 796 case e1000_82571:
b7ee49db 797 if(E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_FUNC_1){
1da177e4
LT		 798 e1000_read_eeprom(&adapter->hw,
799 EEPROM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
800 break;
801 }
802 /* Fall Through */
803 default:
804 e1000_read_eeprom(&adapter->hw,
805 EEPROM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
806 break;
807 }
808 if(eeprom_data & eeprom_apme_mask)
809 adapter->wol |= E1000_WUFC_MAG;
810
fb3d47d4
JK		 811 /* print bus type/speed/width info */
812 {
813 struct e1000_hw *hw = &adapter->hw;
814 DPRINTK(PROBE, INFO, "(PCI%s:%s:%s) ",
815 ((hw->bus_type == e1000_bus_type_pcix) ? "-X" :
816 (hw->bus_type == e1000_bus_type_pci_express ? " Express":"")),
817 ((hw->bus_speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
818 (hw->bus_speed == e1000_bus_speed_133) ? "133MHz" :
819 (hw->bus_speed == e1000_bus_speed_120) ? "120MHz" :
820 (hw->bus_speed == e1000_bus_speed_100) ? "100MHz" :
821 (hw->bus_speed == e1000_bus_speed_66) ? "66MHz" : "33MHz"),
822 ((hw->bus_width == e1000_bus_width_64) ? "64-bit" :
823 (hw->bus_width == e1000_bus_width_pciex_4) ? "Width x4" :
824 (hw->bus_width == e1000_bus_width_pciex_1) ? "Width x1" :
825 "32-bit"));
826 }
827
828 for (i = 0; i < 6; i++)
829 printk("%2.2x%c", netdev->dev_addr[i], i == 5 ? '\n' : ':');
830
1da177e4
LT		 831 /* reset the hardware with the new settings */
832 e1000_reset(adapter);
833
b55ccb35
JK		 834 /* If the controller is 82573 and f/w is AMT, do not set
835 * DRV_LOAD until the interface is up. For all other cases,
836 * let the f/w know that the h/w is now under the control
837 * of the driver. */
838 if (adapter->hw.mac_type != e1000_82573 ||
839 !e1000_check_mng_mode(&adapter->hw))
840 e1000_get_hw_control(adapter);
2d7edb92 841
1da177e4
LT		 842 strcpy(netdev->name, "eth%d");
843 if((err = register_netdev(netdev)))
844 goto err_register;
845
846 DPRINTK(PROBE, INFO, "Intel(R) PRO/1000 Network Connection\n");
847
848 cards_found++;
849 return 0;
850
851err_register:
852err_sw_init:
853err_eeprom:
854 iounmap(adapter->hw.hw_addr);
855err_ioremap:
856 free_netdev(netdev);
857err_alloc_etherdev:
858 pci_release_regions(pdev);
859 return err;
860}
861
862/**
863 * e1000_remove - Device Removal Routine
864 * @pdev: PCI device information struct
865 *
866 * e1000_remove is called by the PCI subsystem to alert the driver
867 * that it should release a PCI device. The could be caused by a
868 * Hot-Plug event, or because the driver is going to be removed from
869 * memory.
870 **/
871
872static void __devexit
873e1000_remove(struct pci_dev *pdev)
874{
875 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 876 struct e1000_adapter *adapter = netdev_priv(netdev);
b55ccb35 877 uint32_t manc;
581d708e
MC		 878#ifdef CONFIG_E1000_NAPI
879 int i;
880#endif
1da177e4 881
be2b28ed
JG		 882 flush_scheduled_work();
883
1da177e4
LT		 884 if(adapter->hw.mac_type >= e1000_82540 &&
885 adapter->hw.media_type == e1000_media_type_copper) {
886 manc = E1000_READ_REG(&adapter->hw, MANC);
887 if(manc & E1000_MANC_SMBUS_EN) {
888 manc |= E1000_MANC_ARP_EN;
889 E1000_WRITE_REG(&adapter->hw, MANC, manc);
890 }
891 }
892
b55ccb35
JK		 893 /* Release control of h/w to f/w. If f/w is AMT enabled, this
894 * would have already happened in close and is redundant. */
895 e1000_release_hw_control(adapter);
2d7edb92 896
1da177e4 897 unregister_netdev(netdev);
581d708e 898#ifdef CONFIG_E1000_NAPI
f56799ea 899 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e
MC		 900 __dev_put(&adapter->polling_netdev[i]);
901#endif
1da177e4 902
2d7edb92
MC		 903 if(!e1000_check_phy_reset_block(&adapter->hw))
904 e1000_phy_hw_reset(&adapter->hw);
1da177e4 905
24025e4e
MC		 906 kfree(adapter->tx_ring);
907 kfree(adapter->rx_ring);
908#ifdef CONFIG_E1000_NAPI
909 kfree(adapter->polling_netdev);
910#endif
911
1da177e4
LT		 912 iounmap(adapter->hw.hw_addr);
913 pci_release_regions(pdev);
914
24025e4e
MC		 915#ifdef CONFIG_E1000_MQ
916 free_percpu(adapter->cpu_netdev);
917 free_percpu(adapter->cpu_tx_ring);
918#endif
1da177e4
LT		 919 free_netdev(netdev);
920
921 pci_disable_device(pdev);
922}
923
924/**
925 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
926 * @adapter: board private structure to initialize
927 *
928 * e1000_sw_init initializes the Adapter private data structure.
929 * Fields are initialized based on PCI device information and
930 * OS network device settings (MTU size).
931 **/
932
933static int __devinit
934e1000_sw_init(struct e1000_adapter *adapter)
935{
936 struct e1000_hw *hw = &adapter->hw;
937 struct net_device *netdev = adapter->netdev;
938 struct pci_dev *pdev = adapter->pdev;
581d708e
MC		 939#ifdef CONFIG_E1000_NAPI
940 int i;
941#endif
1da177e4
LT		 942
943 /* PCI config space info */
944
945 hw->vendor_id = pdev->vendor;
946 hw->device_id = pdev->device;
947 hw->subsystem_vendor_id = pdev->subsystem_vendor;
948 hw->subsystem_id = pdev->subsystem_device;
949
950 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
951
952 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
953
954 adapter->rx_buffer_len = E1000_RXBUFFER_2048;
2d7edb92 955 adapter->rx_ps_bsize0 = E1000_RXBUFFER_256;
1da177e4
LT		 956 hw->max_frame_size = netdev->mtu +
957 ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
958 hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE;
959
960 /* identify the MAC */
961
962 if(e1000_set_mac_type(hw)) {
963 DPRINTK(PROBE, ERR, "Unknown MAC Type\n");
964 return -EIO;
965 }
966
967 /* initialize eeprom parameters */
968
2d7edb92
MC		 969 if(e1000_init_eeprom_params(hw)) {
970 E1000_ERR("EEPROM initialization failed\n");
971 return -EIO;
972 }
1da177e4
LT		 973
974 switch(hw->mac_type) {
975 default:
976 break;
977 case e1000_82541:
978 case e1000_82547:
979 case e1000_82541_rev_2:
980 case e1000_82547_rev_2:
981 hw->phy_init_script = 1;
982 break;
983 }
984
985 e1000_set_media_type(hw);
986
987 hw->wait_autoneg_complete = FALSE;
988 hw->tbi_compatibility_en = TRUE;
989 hw->adaptive_ifs = TRUE;
990
991 /* Copper options */
992
993 if(hw->media_type == e1000_media_type_copper) {
994 hw->mdix = AUTO_ALL_MODES;
995 hw->disable_polarity_correction = FALSE;
996 hw->master_slave = E1000_MASTER_SLAVE;
997 }
998
24025e4e
MC		 999#ifdef CONFIG_E1000_MQ
1000 /* Number of supported queues */
1001 switch (hw->mac_type) {
1002 case e1000_82571:
1003 case e1000_82572:
f56799ea
JK		 1004 /* These controllers support 2 tx queues, but with a single
1005 * qdisc implementation, multiple tx queues aren't quite as
1006 * interesting. If we can find a logical way of mapping
1007 * flows to a queue, then perhaps we can up the num_tx_queue
1008 * count back to its default. Until then, we run the risk of
1009 * terrible performance due to SACK overload. */
1010 adapter->num_tx_queues = 1;
1011 adapter->num_rx_queues = 2;
24025e4e
MC		 1012 break;
1013 default:
f56799ea
JK		 1014 adapter->num_tx_queues = 1;
1015 adapter->num_rx_queues = 1;
24025e4e
MC		 1016 break;
1017 }
f56799ea
JK		 1018 adapter->num_rx_queues = min(adapter->num_rx_queues, num_online_cpus());
1019 adapter->num_tx_queues = min(adapter->num_tx_queues, num_online_cpus());
7bfa4816
JK		 1020 DPRINTK(DRV, INFO, "Multiqueue Enabled: Rx Queue count = %u %s\n",
1021 adapter->num_rx_queues,
1022 ((adapter->num_rx_queues == 1)
1023 ? ((num_online_cpus() > 1)
1024 ? "(due to unsupported feature in current adapter)"
1025 : "(due to unsupported system configuration)")
1026 : ""));
1027 DPRINTK(DRV, INFO, "Multiqueue Enabled: Tx Queue count = %u\n",
1028 adapter->num_tx_queues);
24025e4e 1029#else
f56799ea
JK		 1030 adapter->num_tx_queues = 1;
1031 adapter->num_rx_queues = 1;
24025e4e 1032#endif
581d708e
MC		 1033
1034 if (e1000_alloc_queues(adapter)) {
1035 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
1036 return -ENOMEM;
1037 }
1038
1039#ifdef CONFIG_E1000_NAPI
f56799ea 1040 for (i = 0; i < adapter->num_rx_queues; i++) {
581d708e
MC		 1041 adapter->polling_netdev[i].priv = adapter;
1042 adapter->polling_netdev[i].poll = &e1000_clean;
1043 adapter->polling_netdev[i].weight = 64;
1044 dev_hold(&adapter->polling_netdev[i]);
1045 set_bit(__LINK_STATE_START, &adapter->polling_netdev[i].state);
1046 }
7bfa4816 1047 spin_lock_init(&adapter->tx_queue_lock);
24025e4e
MC		 1048#endif
1049
1da177e4
LT		 1050 atomic_set(&adapter->irq_sem, 1);
1051 spin_lock_init(&adapter->stats_lock);
1da177e4
LT		 1052
1053 return 0;
1054}
1055
581d708e
MC		 1056/**
1057 * e1000_alloc_queues - Allocate memory for all rings
1058 * @adapter: board private structure to initialize
1059 *
1060 * We allocate one ring per queue at run-time since we don't know the
1061 * number of queues at compile-time. The polling_netdev array is
1062 * intended for Multiqueue, but should work fine with a single queue.
1063 **/
1064
1065static int __devinit
1066e1000_alloc_queues(struct e1000_adapter *adapter)
1067{
1068 int size;
1069
f56799ea 1070 size = sizeof(struct e1000_tx_ring) * adapter->num_tx_queues;
581d708e
MC		 1071 adapter->tx_ring = kmalloc(size, GFP_KERNEL);
1072 if (!adapter->tx_ring)
1073 return -ENOMEM;
1074 memset(adapter->tx_ring, 0, size);
1075
f56799ea 1076 size = sizeof(struct e1000_rx_ring) * adapter->num_rx_queues;
581d708e
MC		 1077 adapter->rx_ring = kmalloc(size, GFP_KERNEL);
1078 if (!adapter->rx_ring) {
1079 kfree(adapter->tx_ring);
1080 return -ENOMEM;
1081 }
1082 memset(adapter->rx_ring, 0, size);
1083
1084#ifdef CONFIG_E1000_NAPI
f56799ea 1085 size = sizeof(struct net_device) * adapter->num_rx_queues;
581d708e
MC		 1086 adapter->polling_netdev = kmalloc(size, GFP_KERNEL);
1087 if (!adapter->polling_netdev) {
1088 kfree(adapter->tx_ring);
1089 kfree(adapter->rx_ring);
1090 return -ENOMEM;
1091 }
1092 memset(adapter->polling_netdev, 0, size);
1093#endif
1094
7bfa4816
JK		 1095#ifdef CONFIG_E1000_MQ
1096 adapter->rx_sched_call_data.func = e1000_rx_schedule;
1097 adapter->rx_sched_call_data.info = adapter->netdev;
1098
1099 adapter->cpu_netdev = alloc_percpu(struct net_device *);
1100 adapter->cpu_tx_ring = alloc_percpu(struct e1000_tx_ring *);
1101#endif
1102
581d708e
MC		 1103 return E1000_SUCCESS;
1104}
1105
24025e4e
MC		 1106#ifdef CONFIG_E1000_MQ
1107static void __devinit
1108e1000_setup_queue_mapping(struct e1000_adapter *adapter)
1109{
1110 int i, cpu;
1111
1112 adapter->rx_sched_call_data.func = e1000_rx_schedule;
1113 adapter->rx_sched_call_data.info = adapter->netdev;
1114 cpus_clear(adapter->rx_sched_call_data.cpumask);
1115
1116 adapter->cpu_netdev = alloc_percpu(struct net_device *);
1117 adapter->cpu_tx_ring = alloc_percpu(struct e1000_tx_ring *);
1118
1119 lock_cpu_hotplug();
1120 i = 0;
1121 for_each_online_cpu(cpu) {
f56799ea 1122 *per_cpu_ptr(adapter->cpu_tx_ring, cpu) = &adapter->tx_ring[i % adapter->num_tx_queues];
24025e4e
MC		 1123 /* This is incomplete because we'd like to assign separate
1124 * physical cpus to these netdev polling structures and
1125 * avoid saturating a subset of cpus.
1126 */
f56799ea 1127 if (i < adapter->num_rx_queues) {
24025e4e 1128 *per_cpu_ptr(adapter->cpu_netdev, cpu) = &adapter->polling_netdev[i];
7bfa4816
JK		 1129 adapter->rx_ring[i].cpu = cpu;
1130 cpu_set(cpu, adapter->cpumask);
24025e4e
MC		 1131 } else
1132 *per_cpu_ptr(adapter->cpu_netdev, cpu) = NULL;
1133
1134 i++;
1135 }
1136 unlock_cpu_hotplug();
1137}
1138#endif
1139
1da177e4
LT		 1140/**
1141 * e1000_open - Called when a network interface is made active
1142 * @netdev: network interface device structure
1143 *
1144 * Returns 0 on success, negative value on failure
1145 *
1146 * The open entry point is called when a network interface is made
1147 * active by the system (IFF_UP). At this point all resources needed
1148 * for transmit and receive operations are allocated, the interrupt
1149 * handler is registered with the OS, the watchdog timer is started,
1150 * and the stack is notified that the interface is ready.
1151 **/
1152
1153static int
1154e1000_open(struct net_device *netdev)
1155{
60490fe0 1156 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 1157 int err;
1158
1159 /* allocate transmit descriptors */
1160
581d708e 1161 if ((err = e1000_setup_all_tx_resources(adapter)))
1da177e4
LT		 1162 goto err_setup_tx;
1163
1164 /* allocate receive descriptors */
1165
581d708e 1166 if ((err = e1000_setup_all_rx_resources(adapter)))
1da177e4
LT		 1167 goto err_setup_rx;
1168
1169 if((err = e1000_up(adapter)))
1170 goto err_up;
2d7edb92
MC		 1171 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
1172 if((adapter->hw.mng_cookie.status &
1173 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
1174 e1000_update_mng_vlan(adapter);
1175 }
1da177e4 1176
b55ccb35
JK		 1177 /* If AMT is enabled, let the firmware know that the network
1178 * interface is now open */
1179 if (adapter->hw.mac_type == e1000_82573 &&
1180 e1000_check_mng_mode(&adapter->hw))
1181 e1000_get_hw_control(adapter);
1182
1da177e4
LT		 1183 return E1000_SUCCESS;
1184
1185err_up:
581d708e 1186 e1000_free_all_rx_resources(adapter);
1da177e4 1187err_setup_rx:
581d708e 1188 e1000_free_all_tx_resources(adapter);
1da177e4
LT		 1189err_setup_tx:
1190 e1000_reset(adapter);
1191
1192 return err;
1193}
1194
1195/**
1196 * e1000_close - Disables a network interface
1197 * @netdev: network interface device structure
1198 *
1199 * Returns 0, this is not allowed to fail
1200 *
1201 * The close entry point is called when an interface is de-activated
1202 * by the OS. The hardware is still under the drivers control, but
1203 * needs to be disabled. A global MAC reset is issued to stop the
1204 * hardware, and all transmit and receive resources are freed.
1205 **/
1206
1207static int
1208e1000_close(struct net_device *netdev)
1209{
60490fe0 1210 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 1211
1212 e1000_down(adapter);
1213
581d708e
MC		 1214 e1000_free_all_tx_resources(adapter);
1215 e1000_free_all_rx_resources(adapter);
1da177e4 1216
2d7edb92
MC		 1217 if((adapter->hw.mng_cookie.status &
1218 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
1219 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1220 }
b55ccb35
JK		 1221
1222 /* If AMT is enabled, let the firmware know that the network
1223 * interface is now closed */
1224 if (adapter->hw.mac_type == e1000_82573 &&
1225 e1000_check_mng_mode(&adapter->hw))
1226 e1000_release_hw_control(adapter);
1227
1da177e4
LT		 1228 return 0;
1229}
1230
1231/**
1232 * e1000_check_64k_bound - check that memory doesn't cross 64kB boundary
1233 * @adapter: address of board private structure
2d7edb92
MC		 1234 * @start: address of beginning of memory
1235 * @len: length of memory
1da177e4
LT		 1236 **/
1237static inline boolean_t
1238e1000_check_64k_bound(struct e1000_adapter *adapter,
1239 void *start, unsigned long len)
1240{
1241 unsigned long begin = (unsigned long) start;
1242 unsigned long end = begin + len;
1243
2648345f
MC		 1244 /* First rev 82545 and 82546 need to not allow any memory
1245 * write location to cross 64k boundary due to errata 23 */
1da177e4 1246 if (adapter->hw.mac_type == e1000_82545 ||
2648345f 1247 adapter->hw.mac_type == e1000_82546) {
1da177e4
LT		 1248 return ((begin ^ (end - 1)) >> 16) != 0 ? FALSE : TRUE;
1249 }
1250
1251 return TRUE;
1252}
1253
1254/**
1255 * e1000_setup_tx_resources - allocate Tx resources (Descriptors)
1256 * @adapter: board private structure
581d708e 1257 * @txdr: tx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1258 *
1259 * Return 0 on success, negative on failure
1260 **/
1261
3ad2cc67 1262static int
581d708e
MC		 1263e1000_setup_tx_resources(struct e1000_adapter *adapter,
1264 struct e1000_tx_ring *txdr)
1da177e4 1265{
1da177e4
LT		 1266 struct pci_dev *pdev = adapter->pdev;
1267 int size;
1268
1269 size = sizeof(struct e1000_buffer) * txdr->count;
a7ec15da
RT		 1270
1271 txdr->buffer_info = vmalloc_node(size, pcibus_to_node(pdev->bus));
1da177e4 1272 if(!txdr->buffer_info) {
2648345f
MC		 1273 DPRINTK(PROBE, ERR,
1274 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1275 return -ENOMEM;
1276 }
1277 memset(txdr->buffer_info, 0, size);
1278
1279 /* round up to nearest 4K */
1280
1281 txdr->size = txdr->count * sizeof(struct e1000_tx_desc);
1282 E1000_ROUNDUP(txdr->size, 4096);
1283
1284 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
1285 if(!txdr->desc) {
1286setup_tx_desc_die:
1da177e4 1287 vfree(txdr->buffer_info);
2648345f
MC		 1288 DPRINTK(PROBE, ERR,
1289 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1290 return -ENOMEM;
1291 }
1292
2648345f 1293 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1294 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1295 void *olddesc = txdr->desc;
1296 dma_addr_t olddma = txdr->dma;
2648345f
MC		 1297 DPRINTK(TX_ERR, ERR, "txdr align check failed: %u bytes "
1298 "at %p\n", txdr->size, txdr->desc);
1299 /* Try again, without freeing the previous */
1da177e4 1300 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
1da177e4 1301 if(!txdr->desc) {
2648345f 1302 /* Failed allocation, critical failure */
1da177e4
LT		 1303 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1304 goto setup_tx_desc_die;
1305 }
1306
1307 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1308 /* give up */
2648345f
MC		 1309 pci_free_consistent(pdev, txdr->size, txdr->desc,
1310 txdr->dma);
1da177e4
LT		 1311 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1312 DPRINTK(PROBE, ERR,
2648345f
MC		 1313 "Unable to allocate aligned memory "
1314 "for the transmit descriptor ring\n");
1da177e4
LT		 1315 vfree(txdr->buffer_info);
1316 return -ENOMEM;
1317 } else {
2648345f 1318 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1319 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1320 }
1321 }
1322 memset(txdr->desc, 0, txdr->size);
1323
1324 txdr->next_to_use = 0;
1325 txdr->next_to_clean = 0;
2ae76d98 1326 spin_lock_init(&txdr->tx_lock);
1da177e4
LT		 1327
1328 return 0;
1329}
1330
581d708e
MC		 1331/**
1332 * e1000_setup_all_tx_resources - wrapper to allocate Tx resources
1333 * (Descriptors) for all queues
1334 * @adapter: board private structure
1335 *
1336 * If this function returns with an error, then it's possible one or
1337 * more of the rings is populated (while the rest are not). It is the
1338 * callers duty to clean those orphaned rings.
1339 *
1340 * Return 0 on success, negative on failure
1341 **/
1342
1343int
1344e1000_setup_all_tx_resources(struct e1000_adapter *adapter)
1345{
1346 int i, err = 0;
1347
f56799ea 1348 for (i = 0; i < adapter->num_tx_queues; i++) {
581d708e
MC		 1349 err = e1000_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1350 if (err) {
1351 DPRINTK(PROBE, ERR,
1352 "Allocation for Tx Queue %u failed\n", i);
1353 break;
1354 }
1355 }
1356
1357 return err;
1358}
1359
1da177e4
LT		 1360/**
1361 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
1362 * @adapter: board private structure
1363 *
1364 * Configure the Tx unit of the MAC after a reset.
1365 **/
1366
1367static void
1368e1000_configure_tx(struct e1000_adapter *adapter)
1369{
581d708e
MC		 1370 uint64_t tdba;
1371 struct e1000_hw *hw = &adapter->hw;
1372 uint32_t tdlen, tctl, tipg, tarc;
0fadb059 1373 uint32_t ipgr1, ipgr2;
1da177e4
LT		 1374
1375 /* Setup the HW Tx Head and Tail descriptor pointers */
1376
f56799ea 1377 switch (adapter->num_tx_queues) {
24025e4e
MC		 1378 case 2:
1379 tdba = adapter->tx_ring[1].dma;
1380 tdlen = adapter->tx_ring[1].count *
1381 sizeof(struct e1000_tx_desc);
1382 E1000_WRITE_REG(hw, TDBAL1, (tdba & 0x00000000ffffffffULL));
1383 E1000_WRITE_REG(hw, TDBAH1, (tdba >> 32));
1384 E1000_WRITE_REG(hw, TDLEN1, tdlen);
1385 E1000_WRITE_REG(hw, TDH1, 0);
1386 E1000_WRITE_REG(hw, TDT1, 0);
1387 adapter->tx_ring[1].tdh = E1000_TDH1;
1388 adapter->tx_ring[1].tdt = E1000_TDT1;
1389 /* Fall Through */
1390 case 1:
1391 default:
581d708e
MC		 1392 tdba = adapter->tx_ring[0].dma;
1393 tdlen = adapter->tx_ring[0].count *
1394 sizeof(struct e1000_tx_desc);
1395 E1000_WRITE_REG(hw, TDBAL, (tdba & 0x00000000ffffffffULL));
1396 E1000_WRITE_REG(hw, TDBAH, (tdba >> 32));
1397 E1000_WRITE_REG(hw, TDLEN, tdlen);
1398 E1000_WRITE_REG(hw, TDH, 0);
1399 E1000_WRITE_REG(hw, TDT, 0);
1400 adapter->tx_ring[0].tdh = E1000_TDH;
1401 adapter->tx_ring[0].tdt = E1000_TDT;
24025e4e
MC		 1402 break;
1403 }
1da177e4
LT		 1404
1405 /* Set the default values for the Tx Inter Packet Gap timer */
1406
0fadb059
JK		 1407 if (hw->media_type == e1000_media_type_fiber ||
1408 hw->media_type == e1000_media_type_internal_serdes)
1409 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
1410 else
1411 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
1412
581d708e 1413 switch (hw->mac_type) {
1da177e4
LT		 1414 case e1000_82542_rev2_0:
1415 case e1000_82542_rev2_1:
1416 tipg = DEFAULT_82542_TIPG_IPGT;
0fadb059
JK		 1417 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
1418 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
1da177e4
LT		 1419 break;
1420 default:
0fadb059
JK		 1421 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
1422 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
1423 break;
1da177e4 1424 }
0fadb059
JK		 1425 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
1426 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
581d708e 1427 E1000_WRITE_REG(hw, TIPG, tipg);
1da177e4
LT		 1428
1429 /* Set the Tx Interrupt Delay register */
1430
581d708e
MC		 1431 E1000_WRITE_REG(hw, TIDV, adapter->tx_int_delay);
1432 if (hw->mac_type >= e1000_82540)
1433 E1000_WRITE_REG(hw, TADV, adapter->tx_abs_int_delay);
1da177e4
LT		 1434
1435 /* Program the Transmit Control Register */
1436
581d708e 1437 tctl = E1000_READ_REG(hw, TCTL);
1da177e4
LT		 1438
1439 tctl &= ~E1000_TCTL_CT;
24025e4e 1440 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP | E1000_TCTL_RTLC |
1da177e4
LT		 1441 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1442
581d708e 1443 E1000_WRITE_REG(hw, TCTL, tctl);
1da177e4 1444
2ae76d98
MC		 1445 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
1446 tarc = E1000_READ_REG(hw, TARC0);
1447 tarc |= ((1 << 25) | (1 << 21));
1448 E1000_WRITE_REG(hw, TARC0, tarc);
1449 tarc = E1000_READ_REG(hw, TARC1);
1450 tarc |= (1 << 25);
1451 if (tctl & E1000_TCTL_MULR)
1452 tarc &= ~(1 << 28);
1453 else
1454 tarc |= (1 << 28);
1455 E1000_WRITE_REG(hw, TARC1, tarc);
1456 }
1457
581d708e 1458 e1000_config_collision_dist(hw);
1da177e4
LT		 1459
1460 /* Setup Transmit Descriptor Settings for eop descriptor */
1461 adapter->txd_cmd = E1000_TXD_CMD_IDE | E1000_TXD_CMD_EOP |
1462 E1000_TXD_CMD_IFCS;
1463
581d708e 1464 if (hw->mac_type < e1000_82543)
1da177e4
LT		 1465 adapter->txd_cmd |= E1000_TXD_CMD_RPS;
1466 else
1467 adapter->txd_cmd |= E1000_TXD_CMD_RS;
1468
1469 /* Cache if we're 82544 running in PCI-X because we'll
1470 * need this to apply a workaround later in the send path. */
581d708e
MC		 1471 if (hw->mac_type == e1000_82544 &&
1472 hw->bus_type == e1000_bus_type_pcix)
1da177e4
LT		 1473 adapter->pcix_82544 = 1;
1474}
1475
1476/**
1477 * e1000_setup_rx_resources - allocate Rx resources (Descriptors)
1478 * @adapter: board private structure
581d708e 1479 * @rxdr: rx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1480 *
1481 * Returns 0 on success, negative on failure
1482 **/
1483
3ad2cc67 1484static int
581d708e
MC		 1485e1000_setup_rx_resources(struct e1000_adapter *adapter,
1486 struct e1000_rx_ring *rxdr)
1da177e4 1487{
1da177e4 1488 struct pci_dev *pdev = adapter->pdev;
2d7edb92 1489 int size, desc_len;
1da177e4
LT		 1490
1491 size = sizeof(struct e1000_buffer) * rxdr->count;
a7ec15da 1492 rxdr->buffer_info = vmalloc_node(size, pcibus_to_node(pdev->bus));
581d708e 1493 if (!rxdr->buffer_info) {
2648345f
MC		 1494 DPRINTK(PROBE, ERR,
1495 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4
LT		 1496 return -ENOMEM;
1497 }
1498 memset(rxdr->buffer_info, 0, size);
1499
2d7edb92
MC		 1500 size = sizeof(struct e1000_ps_page) * rxdr->count;
1501 rxdr->ps_page = kmalloc(size, GFP_KERNEL);
1502 if(!rxdr->ps_page) {
1503 vfree(rxdr->buffer_info);
1504 DPRINTK(PROBE, ERR,
1505 "Unable to allocate memory for the receive descriptor ring\n");
1506 return -ENOMEM;
1507 }
1508 memset(rxdr->ps_page, 0, size);
1509
1510 size = sizeof(struct e1000_ps_page_dma) * rxdr->count;
1511 rxdr->ps_page_dma = kmalloc(size, GFP_KERNEL);
1512 if(!rxdr->ps_page_dma) {
1513 vfree(rxdr->buffer_info);
1514 kfree(rxdr->ps_page);
1515 DPRINTK(PROBE, ERR,
1516 "Unable to allocate memory for the receive descriptor ring\n");
1517 return -ENOMEM;
1518 }
1519 memset(rxdr->ps_page_dma, 0, size);
1520
1521 if(adapter->hw.mac_type <= e1000_82547_rev_2)
1522 desc_len = sizeof(struct e1000_rx_desc);
1523 else
1524 desc_len = sizeof(union e1000_rx_desc_packet_split);
1525
1da177e4
LT		 1526 /* Round up to nearest 4K */
1527
2d7edb92 1528 rxdr->size = rxdr->count * desc_len;
1da177e4
LT		 1529 E1000_ROUNDUP(rxdr->size, 4096);
1530
1531 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
1532
581d708e
MC		 1533 if (!rxdr->desc) {
1534 DPRINTK(PROBE, ERR,
1535 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4 1536setup_rx_desc_die:
1da177e4 1537 vfree(rxdr->buffer_info);
2d7edb92
MC		 1538 kfree(rxdr->ps_page);
1539 kfree(rxdr->ps_page_dma);
1da177e4
LT		 1540 return -ENOMEM;
1541 }
1542
2648345f 1543 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1544 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1545 void *olddesc = rxdr->desc;
1546 dma_addr_t olddma = rxdr->dma;
2648345f
MC		 1547 DPRINTK(RX_ERR, ERR, "rxdr align check failed: %u bytes "
1548 "at %p\n", rxdr->size, rxdr->desc);
1549 /* Try again, without freeing the previous */
1da177e4 1550 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
2648345f 1551 /* Failed allocation, critical failure */
581d708e 1552 if (!rxdr->desc) {
1da177e4 1553 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
581d708e
MC		 1554 DPRINTK(PROBE, ERR,
1555 "Unable to allocate memory "
1556 "for the receive descriptor ring\n");
1da177e4
LT		 1557 goto setup_rx_desc_die;
1558 }
1559
1560 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1561 /* give up */
2648345f
MC		 1562 pci_free_consistent(pdev, rxdr->size, rxdr->desc,
1563 rxdr->dma);
1da177e4 1564 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
2648345f
MC		 1565 DPRINTK(PROBE, ERR,
1566 "Unable to allocate aligned memory "
1567 "for the receive descriptor ring\n");
581d708e 1568 goto setup_rx_desc_die;
1da177e4 1569 } else {
2648345f 1570 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1571 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
1572 }
1573 }
1574 memset(rxdr->desc, 0, rxdr->size);
1575
1576 rxdr->next_to_clean = 0;
1577 rxdr->next_to_use = 0;
997f5cbd
JK		 1578 rxdr->rx_skb_top = NULL;
1579 rxdr->rx_skb_prev = NULL;
1da177e4
LT		 1580
1581 return 0;
1582}
1583
581d708e
MC		 1584/**
1585 * e1000_setup_all_rx_resources - wrapper to allocate Rx resources
1586 * (Descriptors) for all queues
1587 * @adapter: board private structure
1588 *
1589 * If this function returns with an error, then it's possible one or
1590 * more of the rings is populated (while the rest are not). It is the
1591 * callers duty to clean those orphaned rings.
1592 *
1593 * Return 0 on success, negative on failure
1594 **/
1595
1596int
1597e1000_setup_all_rx_resources(struct e1000_adapter *adapter)
1598{
1599 int i, err = 0;
1600
f56799ea 1601 for (i = 0; i < adapter->num_rx_queues; i++) {
581d708e
MC		 1602 err = e1000_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1603 if (err) {
1604 DPRINTK(PROBE, ERR,
1605 "Allocation for Rx Queue %u failed\n", i);
1606 break;
1607 }
1608 }
1609
1610 return err;
1611}
1612
1da177e4 1613/**
2648345f 1614 * e1000_setup_rctl - configure the receive control registers
1da177e4
LT		 1615 * @adapter: Board private structure
1616 **/
e4c811c9
MC		 1617#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
1618 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
1da177e4
LT		 1619static void
1620e1000_setup_rctl(struct e1000_adapter *adapter)
1621{
2d7edb92
MC		 1622 uint32_t rctl, rfctl;
1623 uint32_t psrctl = 0;
e4c811c9
MC		 1624#ifdef CONFIG_E1000_PACKET_SPLIT
1625 uint32_t pages = 0;
1626#endif
1da177e4
LT		 1627
1628 rctl = E1000_READ_REG(&adapter->hw, RCTL);
1629
1630 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1631
1632 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1633 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1634 (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
1635
0fadb059
JK		 1636 if (adapter->hw.mac_type > e1000_82543)
1637 rctl |= E1000_RCTL_SECRC;
1638
1639 if (adapter->hw.tbi_compatibility_on == 1)
1da177e4
LT		 1640 rctl |= E1000_RCTL_SBP;
1641 else
1642 rctl &= ~E1000_RCTL_SBP;
1643
2d7edb92
MC		 1644 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1645 rctl &= ~E1000_RCTL_LPE;
1646 else
1647 rctl |= E1000_RCTL_LPE;
1648
1da177e4 1649 /* Setup buffer sizes */
868d5309 1650 if(adapter->hw.mac_type >= e1000_82571) {
2d7edb92
MC		 1651 /* We can now specify buffers in 1K increments.
1652 * BSIZE and BSEX are ignored in this case. */
1653 rctl |= adapter->rx_buffer_len << 0x11;
1654 } else {
1655 rctl &= ~E1000_RCTL_SZ_4096;
1656 rctl |= E1000_RCTL_BSEX;
1657 switch (adapter->rx_buffer_len) {
1658 case E1000_RXBUFFER_2048:
1659 default:
1660 rctl |= E1000_RCTL_SZ_2048;
1661 rctl &= ~E1000_RCTL_BSEX;
1662 break;
1663 case E1000_RXBUFFER_4096:
1664 rctl |= E1000_RCTL_SZ_4096;
1665 break;
1666 case E1000_RXBUFFER_8192:
1667 rctl |= E1000_RCTL_SZ_8192;
1668 break;
1669 case E1000_RXBUFFER_16384:
1670 rctl |= E1000_RCTL_SZ_16384;
1671 break;
1672 }
1673 }
1674
1675#ifdef CONFIG_E1000_PACKET_SPLIT
1676 /* 82571 and greater support packet-split where the protocol
1677 * header is placed in skb->data and the packet data is
1678 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1679 * In the case of a non-split, skb->data is linearly filled,
1680 * followed by the page buffers. Therefore, skb->data is
1681 * sized to hold the largest protocol header.
1682 */
e4c811c9
MC		 1683 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
1684 if ((adapter->hw.mac_type > e1000_82547_rev_2) && (pages <= 3) &&
1685 PAGE_SIZE <= 16384)
1686 adapter->rx_ps_pages = pages;
1687 else
1688 adapter->rx_ps_pages = 0;
2d7edb92 1689#endif
e4c811c9 1690 if (adapter->rx_ps_pages) {
2d7edb92
MC		 1691 /* Configure extra packet-split registers */
1692 rfctl = E1000_READ_REG(&adapter->hw, RFCTL);
1693 rfctl |= E1000_RFCTL_EXTEN;
1694 /* disable IPv6 packet split support */
1695 rfctl |= E1000_RFCTL_IPV6_DIS;
1696 E1000_WRITE_REG(&adapter->hw, RFCTL, rfctl);
1697
1698 rctl |= E1000_RCTL_DTYP_PS | E1000_RCTL_SECRC;
1699
1700 psrctl |= adapter->rx_ps_bsize0 >>
1701 E1000_PSRCTL_BSIZE0_SHIFT;
e4c811c9
MC		 1702
1703 switch (adapter->rx_ps_pages) {
1704 case 3:
1705 psrctl |= PAGE_SIZE <<
1706 E1000_PSRCTL_BSIZE3_SHIFT;
1707 case 2:
1708 psrctl |= PAGE_SIZE <<
1709 E1000_PSRCTL_BSIZE2_SHIFT;
1710 case 1:
1711 psrctl |= PAGE_SIZE >>
1712 E1000_PSRCTL_BSIZE1_SHIFT;
1713 break;
1714 }
2d7edb92
MC		 1715
1716 E1000_WRITE_REG(&adapter->hw, PSRCTL, psrctl);
1da177e4
LT		 1717 }
1718
1719 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1720}
1721
1722/**
1723 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
1724 * @adapter: board private structure
1725 *
1726 * Configure the Rx unit of the MAC after a reset.
1727 **/
1728
1729static void
1730e1000_configure_rx(struct e1000_adapter *adapter)
1731{
581d708e
MC		 1732 uint64_t rdba;
1733 struct e1000_hw *hw = &adapter->hw;
1734 uint32_t rdlen, rctl, rxcsum, ctrl_ext;
1735#ifdef CONFIG_E1000_MQ
1736 uint32_t reta, mrqc;
1737 int i;
1738#endif
2d7edb92 1739
e4c811c9 1740 if (adapter->rx_ps_pages) {
581d708e 1741 rdlen = adapter->rx_ring[0].count *
2d7edb92
MC		 1742 sizeof(union e1000_rx_desc_packet_split);
1743 adapter->clean_rx = e1000_clean_rx_irq_ps;
1744 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
1745 } else {
581d708e
MC		 1746 rdlen = adapter->rx_ring[0].count *
1747 sizeof(struct e1000_rx_desc);
2d7edb92
MC		 1748 adapter->clean_rx = e1000_clean_rx_irq;
1749 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
1750 }
1da177e4
LT		 1751
1752 /* disable receives while setting up the descriptors */
581d708e
MC		 1753 rctl = E1000_READ_REG(hw, RCTL);
1754 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
1da177e4
LT		 1755
1756 /* set the Receive Delay Timer Register */
581d708e 1757 E1000_WRITE_REG(hw, RDTR, adapter->rx_int_delay);
1da177e4 1758
581d708e
MC		 1759 if (hw->mac_type >= e1000_82540) {
1760 E1000_WRITE_REG(hw, RADV, adapter->rx_abs_int_delay);
1da177e4 1761 if(adapter->itr > 1)
581d708e 1762 E1000_WRITE_REG(hw, ITR,
1da177e4
LT		 1763 1000000000 / (adapter->itr * 256));
1764 }
1765
2ae76d98 1766 if (hw->mac_type >= e1000_82571) {
2ae76d98 1767 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1e613fd9 1768 /* Reset delay timers after every interrupt */
2ae76d98 1769 ctrl_ext |= E1000_CTRL_EXT_CANC;
1e613fd9
JK		 1770#ifdef CONFIG_E1000_NAPI
1771 /* Auto-Mask interrupts upon ICR read. */
1772 ctrl_ext |= E1000_CTRL_EXT_IAME;
1773#endif
2ae76d98 1774 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1e613fd9 1775 E1000_WRITE_REG(hw, IAM, ~0);
2ae76d98
MC		 1776 E1000_WRITE_FLUSH(hw);
1777 }
1778
581d708e
MC		 1779 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1780 * the Base and Length of the Rx Descriptor Ring */
f56799ea 1781 switch (adapter->num_rx_queues) {
24025e4e
MC		 1782#ifdef CONFIG_E1000_MQ
1783 case 2:
1784 rdba = adapter->rx_ring[1].dma;
1785 E1000_WRITE_REG(hw, RDBAL1, (rdba & 0x00000000ffffffffULL));
1786 E1000_WRITE_REG(hw, RDBAH1, (rdba >> 32));
1787 E1000_WRITE_REG(hw, RDLEN1, rdlen);
1788 E1000_WRITE_REG(hw, RDH1, 0);
1789 E1000_WRITE_REG(hw, RDT1, 0);
1790 adapter->rx_ring[1].rdh = E1000_RDH1;
1791 adapter->rx_ring[1].rdt = E1000_RDT1;
1792 /* Fall Through */
1793#endif
1794 case 1:
1795 default:
581d708e
MC		 1796 rdba = adapter->rx_ring[0].dma;
1797 E1000_WRITE_REG(hw, RDBAL, (rdba & 0x00000000ffffffffULL));
1798 E1000_WRITE_REG(hw, RDBAH, (rdba >> 32));
1799 E1000_WRITE_REG(hw, RDLEN, rdlen);
1800 E1000_WRITE_REG(hw, RDH, 0);
1801 E1000_WRITE_REG(hw, RDT, 0);
1802 adapter->rx_ring[0].rdh = E1000_RDH;
1803 adapter->rx_ring[0].rdt = E1000_RDT;
1804 break;
24025e4e
MC		 1805 }
1806
1807#ifdef CONFIG_E1000_MQ
f56799ea 1808 if (adapter->num_rx_queues > 1) {
24025e4e
MC		 1809 uint32_t random[10];
1810
1811 get_random_bytes(&random[0], 40);
1812
1813 if (hw->mac_type <= e1000_82572) {
1814 E1000_WRITE_REG(hw, RSSIR, 0);
1815 E1000_WRITE_REG(hw, RSSIM, 0);
1816 }
1817
f56799ea 1818 switch (adapter->num_rx_queues) {
24025e4e
MC		 1819 case 2:
1820 default:
1821 reta = 0x00800080;
1822 mrqc = E1000_MRQC_ENABLE_RSS_2Q;
1823 break;
1824 }
1825
1826 /* Fill out redirection table */
1827 for (i = 0; i < 32; i++)
1828 E1000_WRITE_REG_ARRAY(hw, RETA, i, reta);
1829 /* Fill out hash function seeds */
1830 for (i = 0; i < 10; i++)
1831 E1000_WRITE_REG_ARRAY(hw, RSSRK, i, random[i]);
1832
1833 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1834 E1000_MRQC_RSS_FIELD_IPV4_TCP);
1835 E1000_WRITE_REG(hw, MRQC, mrqc);
1836 }
1837
1838 /* Multiqueue and packet checksumming are mutually exclusive. */
1839 if (hw->mac_type >= e1000_82571) {
1840 rxcsum = E1000_READ_REG(hw, RXCSUM);
1841 rxcsum |= E1000_RXCSUM_PCSD;
1842 E1000_WRITE_REG(hw, RXCSUM, rxcsum);
1843 }
1844
1845#else
1da177e4
LT		 1846
1847 /* Enable 82543 Receive Checksum Offload for TCP and UDP */
581d708e
MC		 1848 if (hw->mac_type >= e1000_82543) {
1849 rxcsum = E1000_READ_REG(hw, RXCSUM);
2d7edb92
MC		 1850 if(adapter->rx_csum == TRUE) {
1851 rxcsum |= E1000_RXCSUM_TUOFL;
1852
868d5309 1853 /* Enable 82571 IPv4 payload checksum for UDP fragments
2d7edb92 1854 * Must be used in conjunction with packet-split. */
e4c811c9
MC		 1855 if ((hw->mac_type >= e1000_82571) &&
1856 (adapter->rx_ps_pages)) {
2d7edb92
MC		 1857 rxcsum |= E1000_RXCSUM_IPPCSE;
1858 }
1859 } else {
1860 rxcsum &= ~E1000_RXCSUM_TUOFL;
1861 /* don't need to clear IPPCSE as it defaults to 0 */
1862 }
581d708e 1863 E1000_WRITE_REG(hw, RXCSUM, rxcsum);
1da177e4 1864 }
24025e4e 1865#endif /* CONFIG_E1000_MQ */
1da177e4 1866
581d708e
MC		 1867 if (hw->mac_type == e1000_82573)
1868 E1000_WRITE_REG(hw, ERT, 0x0100);
2d7edb92 1869
1da177e4 1870 /* Enable Receives */
581d708e 1871 E1000_WRITE_REG(hw, RCTL, rctl);
1da177e4
LT		 1872}
1873
1874/**
581d708e 1875 * e1000_free_tx_resources - Free Tx Resources per Queue
1da177e4 1876 * @adapter: board private structure
581d708e 1877 * @tx_ring: Tx descriptor ring for a specific queue
1da177e4
LT		 1878 *
1879 * Free all transmit software resources
1880 **/
1881
3ad2cc67 1882static void
581d708e
MC		 1883e1000_free_tx_resources(struct e1000_adapter *adapter,
1884 struct e1000_tx_ring *tx_ring)
1da177e4
LT		 1885{
1886 struct pci_dev *pdev = adapter->pdev;
1887
581d708e 1888 e1000_clean_tx_ring(adapter, tx_ring);
1da177e4 1889
581d708e
MC		 1890 vfree(tx_ring->buffer_info);
1891 tx_ring->buffer_info = NULL;
1da177e4 1892
581d708e 1893 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1da177e4 1894
581d708e
MC		 1895 tx_ring->desc = NULL;
1896}
1897
1898/**
1899 * e1000_free_all_tx_resources - Free Tx Resources for All Queues
1900 * @adapter: board private structure
1901 *
1902 * Free all transmit software resources
1903 **/
1904
1905void
1906e1000_free_all_tx_resources(struct e1000_adapter *adapter)
1907{
1908 int i;
1909
f56799ea 1910 for (i = 0; i < adapter->num_tx_queues; i++)
581d708e 1911 e1000_free_tx_resources(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 1912}
1913
1914static inline void
1915e1000_unmap_and_free_tx_resource(struct e1000_adapter *adapter,
1916 struct e1000_buffer *buffer_info)
1917{
1da177e4 1918 if(buffer_info->dma) {
2648345f
MC		 1919 pci_unmap_page(adapter->pdev,
1920 buffer_info->dma,
1921 buffer_info->length,
1922 PCI_DMA_TODEVICE);
1da177e4 1923 }
8241e35e 1924 if (buffer_info->skb)
1da177e4 1925 dev_kfree_skb_any(buffer_info->skb);
8241e35e 1926 memset(buffer_info, 0, sizeof(struct e1000_buffer));
1da177e4
LT		 1927}
1928
1929/**
1930 * e1000_clean_tx_ring - Free Tx Buffers
1931 * @adapter: board private structure
581d708e 1932 * @tx_ring: ring to be cleaned
1da177e4
LT		 1933 **/
1934
1935static void
581d708e
MC		 1936e1000_clean_tx_ring(struct e1000_adapter *adapter,
1937 struct e1000_tx_ring *tx_ring)
1da177e4 1938{
1da177e4
LT		 1939 struct e1000_buffer *buffer_info;
1940 unsigned long size;
1941 unsigned int i;
1942
1943 /* Free all the Tx ring sk_buffs */
1944
1da177e4
LT		 1945 for(i = 0; i < tx_ring->count; i++) {
1946 buffer_info = &tx_ring->buffer_info[i];
1947 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
1948 }
1949
1950 size = sizeof(struct e1000_buffer) * tx_ring->count;
1951 memset(tx_ring->buffer_info, 0, size);
1952
1953 /* Zero out the descriptor ring */
1954
1955 memset(tx_ring->desc, 0, tx_ring->size);
1956
1957 tx_ring->next_to_use = 0;
1958 tx_ring->next_to_clean = 0;
fd803241 1959 tx_ring->last_tx_tso = 0;
1da177e4 1960
581d708e
MC		 1961 writel(0, adapter->hw.hw_addr + tx_ring->tdh);
1962 writel(0, adapter->hw.hw_addr + tx_ring->tdt);
1963}
1964
1965/**
1966 * e1000_clean_all_tx_rings - Free Tx Buffers for all queues
1967 * @adapter: board private structure
1968 **/
1969
1970static void
1971e1000_clean_all_tx_rings(struct e1000_adapter *adapter)
1972{
1973 int i;
1974
f56799ea 1975 for (i = 0; i < adapter->num_tx_queues; i++)
581d708e 1976 e1000_clean_tx_ring(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 1977}
1978
1979/**
1980 * e1000_free_rx_resources - Free Rx Resources
1981 * @adapter: board private structure
581d708e 1982 * @rx_ring: ring to clean the resources from
1da177e4
LT		 1983 *
1984 * Free all receive software resources
1985 **/
1986
3ad2cc67 1987static void
581d708e
MC		 1988e1000_free_rx_resources(struct e1000_adapter *adapter,
1989 struct e1000_rx_ring *rx_ring)
1da177e4 1990{
1da177e4
LT		 1991 struct pci_dev *pdev = adapter->pdev;
1992
581d708e 1993 e1000_clean_rx_ring(adapter, rx_ring);
1da177e4
LT		 1994
1995 vfree(rx_ring->buffer_info);
1996 rx_ring->buffer_info = NULL;
2d7edb92
MC		 1997 kfree(rx_ring->ps_page);
1998 rx_ring->ps_page = NULL;
1999 kfree(rx_ring->ps_page_dma);
2000 rx_ring->ps_page_dma = NULL;
1da177e4
LT		 2001
2002 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2003
2004 rx_ring->desc = NULL;
2005}
2006
2007/**
581d708e 2008 * e1000_free_all_rx_resources - Free Rx Resources for All Queues
1da177e4 2009 * @adapter: board private structure
581d708e
MC		 2010 *
2011 * Free all receive software resources
2012 **/
2013
2014void
2015e1000_free_all_rx_resources(struct e1000_adapter *adapter)
2016{
2017 int i;
2018
f56799ea 2019 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e
MC		 2020 e1000_free_rx_resources(adapter, &adapter->rx_ring[i]);
2021}
2022
2023/**
2024 * e1000_clean_rx_ring - Free Rx Buffers per Queue
2025 * @adapter: board private structure
2026 * @rx_ring: ring to free buffers from
1da177e4
LT		 2027 **/
2028
2029static void
581d708e
MC		 2030e1000_clean_rx_ring(struct e1000_adapter *adapter,
2031 struct e1000_rx_ring *rx_ring)
1da177e4 2032{
1da177e4 2033 struct e1000_buffer *buffer_info;
2d7edb92
MC		 2034 struct e1000_ps_page *ps_page;
2035 struct e1000_ps_page_dma *ps_page_dma;
1da177e4
LT		 2036 struct pci_dev *pdev = adapter->pdev;
2037 unsigned long size;
2d7edb92 2038 unsigned int i, j;
1da177e4
LT		 2039
2040 /* Free all the Rx ring sk_buffs */
2041
2042 for(i = 0; i < rx_ring->count; i++) {
2043 buffer_info = &rx_ring->buffer_info[i];
2044 if(buffer_info->skb) {
1da177e4
LT		 2045 pci_unmap_single(pdev,
2046 buffer_info->dma,
2047 buffer_info->length,
2048 PCI_DMA_FROMDEVICE);
2049
2050 dev_kfree_skb(buffer_info->skb);
2051 buffer_info->skb = NULL;
997f5cbd
JK		 2052 }
2053 ps_page = &rx_ring->ps_page[i];
2054 ps_page_dma = &rx_ring->ps_page_dma[i];
2055 for (j = 0; j < adapter->rx_ps_pages; j++) {
2056 if (!ps_page->ps_page[j]) break;
2057 pci_unmap_page(pdev,
2058 ps_page_dma->ps_page_dma[j],
2059 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2060 ps_page_dma->ps_page_dma[j] = 0;
2061 put_page(ps_page->ps_page[j]);
2062 ps_page->ps_page[j] = NULL;
1da177e4
LT		 2063 }
2064 }
2065
997f5cbd
JK		 2066 /* there also may be some cached data in our adapter */
2067 if (rx_ring->rx_skb_top) {
2068 dev_kfree_skb(rx_ring->rx_skb_top);
2069
2070 /* rx_skb_prev will be wiped out by rx_skb_top */
2071 rx_ring->rx_skb_top = NULL;
2072 rx_ring->rx_skb_prev = NULL;
2073 }
2074
2075
1da177e4
LT		 2076 size = sizeof(struct e1000_buffer) * rx_ring->count;
2077 memset(rx_ring->buffer_info, 0, size);
2d7edb92
MC		 2078 size = sizeof(struct e1000_ps_page) * rx_ring->count;
2079 memset(rx_ring->ps_page, 0, size);
2080 size = sizeof(struct e1000_ps_page_dma) * rx_ring->count;
2081 memset(rx_ring->ps_page_dma, 0, size);
1da177e4
LT		 2082
2083 /* Zero out the descriptor ring */
2084
2085 memset(rx_ring->desc, 0, rx_ring->size);
2086
2087 rx_ring->next_to_clean = 0;
2088 rx_ring->next_to_use = 0;
2089
581d708e
MC		 2090 writel(0, adapter->hw.hw_addr + rx_ring->rdh);
2091 writel(0, adapter->hw.hw_addr + rx_ring->rdt);
2092}
2093
2094/**
2095 * e1000_clean_all_rx_rings - Free Rx Buffers for all queues
2096 * @adapter: board private structure
2097 **/
2098
2099static void
2100e1000_clean_all_rx_rings(struct e1000_adapter *adapter)
2101{
2102 int i;
2103
f56799ea 2104 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e 2105 e1000_clean_rx_ring(adapter, &adapter->rx_ring[i]);
1da177e4
LT		 2106}
2107
2108/* The 82542 2.0 (revision 2) needs to have the receive unit in reset
2109 * and memory write and invalidate disabled for certain operations
2110 */
2111static void
2112e1000_enter_82542_rst(struct e1000_adapter *adapter)
2113{
2114 struct net_device *netdev = adapter->netdev;
2115 uint32_t rctl;
2116
2117 e1000_pci_clear_mwi(&adapter->hw);
2118
2119 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2120 rctl |= E1000_RCTL_RST;
2121 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2122 E1000_WRITE_FLUSH(&adapter->hw);
2123 mdelay(5);
2124
2125 if(netif_running(netdev))
581d708e 2126 e1000_clean_all_rx_rings(adapter);
1da177e4
LT		 2127}
2128
2129static void
2130e1000_leave_82542_rst(struct e1000_adapter *adapter)
2131{
2132 struct net_device *netdev = adapter->netdev;
2133 uint32_t rctl;
2134
2135 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2136 rctl &= ~E1000_RCTL_RST;
2137 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2138 E1000_WRITE_FLUSH(&adapter->hw);
2139 mdelay(5);
2140
2141 if(adapter->hw.pci_cmd_word & PCI_COMMAND_INVALIDATE)
2142 e1000_pci_set_mwi(&adapter->hw);
2143
2144 if(netif_running(netdev)) {
2145 e1000_configure_rx(adapter);
72d64a43
JK		 2146 /* No need to loop, because 82542 supports only 1 queue */
2147 struct e1000_rx_ring *ring = &adapter->rx_ring[0];
2148 adapter->alloc_rx_buf(adapter, ring, E1000_DESC_UNUSED(ring));
1da177e4
LT		 2149 }
2150}
2151
2152/**
2153 * e1000_set_mac - Change the Ethernet Address of the NIC
2154 * @netdev: network interface device structure
2155 * @p: pointer to an address structure
2156 *
2157 * Returns 0 on success, negative on failure
2158 **/
2159
2160static int
2161e1000_set_mac(struct net_device *netdev, void *p)
2162{
60490fe0 2163 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2164 struct sockaddr *addr = p;
2165
2166 if(!is_valid_ether_addr(addr->sa_data))
2167 return -EADDRNOTAVAIL;
2168
2169 /* 82542 2.0 needs to be in reset to write receive address registers */
2170
2171 if(adapter->hw.mac_type == e1000_82542_rev2_0)
2172 e1000_enter_82542_rst(adapter);
2173
2174 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2175 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
2176
2177 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2178
868d5309
MC		 2179 /* With 82571 controllers, LAA may be overwritten (with the default)
2180 * due to controller reset from the other port. */
2181 if (adapter->hw.mac_type == e1000_82571) {
2182 /* activate the work around */
2183 adapter->hw.laa_is_present = 1;
2184
2185 /* Hold a copy of the LAA in RAR[14] This is done so that
2186 * between the time RAR[0] gets clobbered and the time it
2187 * gets fixed (in e1000_watchdog), the actual LAA is in one
2188 * of the RARs and no incoming packets directed to this port
2189 * are dropped. Eventaully the LAA will be in RAR[0] and
2190 * RAR[14] */
2191 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr,
2192 E1000_RAR_ENTRIES - 1);
2193 }
2194
1da177e4
LT		 2195 if(adapter->hw.mac_type == e1000_82542_rev2_0)
2196 e1000_leave_82542_rst(adapter);
2197
2198 return 0;
2199}
2200
2201/**
2202 * e1000_set_multi - Multicast and Promiscuous mode set
2203 * @netdev: network interface device structure
2204 *
2205 * The set_multi entry point is called whenever the multicast address
2206 * list or the network interface flags are updated. This routine is
2207 * responsible for configuring the hardware for proper multicast,
2208 * promiscuous mode, and all-multi behavior.
2209 **/
2210
2211static void
2212e1000_set_multi(struct net_device *netdev)
2213{
60490fe0 2214 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2215 struct e1000_hw *hw = &adapter->hw;
2216 struct dev_mc_list *mc_ptr;
2217 uint32_t rctl;
2218 uint32_t hash_value;
868d5309 2219 int i, rar_entries = E1000_RAR_ENTRIES;
1da177e4 2220
868d5309
MC		 2221 /* reserve RAR[14] for LAA over-write work-around */
2222 if (adapter->hw.mac_type == e1000_82571)
2223 rar_entries--;
1da177e4 2224
2648345f
MC		 2225 /* Check for Promiscuous and All Multicast modes */
2226
1da177e4
LT		 2227 rctl = E1000_READ_REG(hw, RCTL);
2228
2229 if(netdev->flags & IFF_PROMISC) {
2230 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2231 } else if(netdev->flags & IFF_ALLMULTI) {
2232 rctl |= E1000_RCTL_MPE;
2233 rctl &= ~E1000_RCTL_UPE;
2234 } else {
2235 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2236 }
2237
2238 E1000_WRITE_REG(hw, RCTL, rctl);
2239
2240 /* 82542 2.0 needs to be in reset to write receive address registers */
2241
2242 if(hw->mac_type == e1000_82542_rev2_0)
2243 e1000_enter_82542_rst(adapter);
2244
2245 /* load the first 14 multicast address into the exact filters 1-14
2246 * RAR 0 is used for the station MAC adddress
2247 * if there are not 14 addresses, go ahead and clear the filters
868d5309 2248 * -- with 82571 controllers only 0-13 entries are filled here
1da177e4
LT		 2249 */
2250 mc_ptr = netdev->mc_list;
2251
868d5309
MC		 2252 for(i = 1; i < rar_entries; i++) {
2253 if (mc_ptr) {
1da177e4
LT		 2254 e1000_rar_set(hw, mc_ptr->dmi_addr, i);
2255 mc_ptr = mc_ptr->next;
2256 } else {
2257 E1000_WRITE_REG_ARRAY(hw, RA, i << 1, 0);
2258 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1) + 1, 0);
2259 }
2260 }
2261
2262 /* clear the old settings from the multicast hash table */
2263
2264 for(i = 0; i < E1000_NUM_MTA_REGISTERS; i++)
2265 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
2266
2267 /* load any remaining addresses into the hash table */
2268
2269 for(; mc_ptr; mc_ptr = mc_ptr->next) {
2270 hash_value = e1000_hash_mc_addr(hw, mc_ptr->dmi_addr);
2271 e1000_mta_set(hw, hash_value);
2272 }
2273
2274 if(hw->mac_type == e1000_82542_rev2_0)
2275 e1000_leave_82542_rst(adapter);
1da177e4
LT		 2276}
2277
2278/* Need to wait a few seconds after link up to get diagnostic information from
2279 * the phy */
2280
2281static void
2282e1000_update_phy_info(unsigned long data)
2283{
2284 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2285 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
2286}
2287
2288/**
2289 * e1000_82547_tx_fifo_stall - Timer Call-back
2290 * @data: pointer to adapter cast into an unsigned long
2291 **/
2292
2293static void
2294e1000_82547_tx_fifo_stall(unsigned long data)
2295{
2296 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2297 struct net_device *netdev = adapter->netdev;
2298 uint32_t tctl;
2299
2300 if(atomic_read(&adapter->tx_fifo_stall)) {
2301 if((E1000_READ_REG(&adapter->hw, TDT) ==
2302 E1000_READ_REG(&adapter->hw, TDH)) &&
2303 (E1000_READ_REG(&adapter->hw, TDFT) ==
2304 E1000_READ_REG(&adapter->hw, TDFH)) &&
2305 (E1000_READ_REG(&adapter->hw, TDFTS) ==
2306 E1000_READ_REG(&adapter->hw, TDFHS))) {
2307 tctl = E1000_READ_REG(&adapter->hw, TCTL);
2308 E1000_WRITE_REG(&adapter->hw, TCTL,
2309 tctl & ~E1000_TCTL_EN);
2310 E1000_WRITE_REG(&adapter->hw, TDFT,
2311 adapter->tx_head_addr);
2312 E1000_WRITE_REG(&adapter->hw, TDFH,
2313 adapter->tx_head_addr);
2314 E1000_WRITE_REG(&adapter->hw, TDFTS,
2315 adapter->tx_head_addr);
2316 E1000_WRITE_REG(&adapter->hw, TDFHS,
2317 adapter->tx_head_addr);
2318 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
2319 E1000_WRITE_FLUSH(&adapter->hw);
2320
2321 adapter->tx_fifo_head = 0;
2322 atomic_set(&adapter->tx_fifo_stall, 0);
2323 netif_wake_queue(netdev);
2324 } else {
2325 mod_timer(&adapter->tx_fifo_stall_timer, jiffies + 1);
2326 }
2327 }
2328}
2329
2330/**
2331 * e1000_watchdog - Timer Call-back
2332 * @data: pointer to adapter cast into an unsigned long
2333 **/
2334static void
2335e1000_watchdog(unsigned long data)
2336{
2337 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2338
2339 /* Do the rest outside of interrupt context */
2340 schedule_work(&adapter->watchdog_task);
2341}
2342
2343static void
2344e1000_watchdog_task(struct e1000_adapter *adapter)
2345{
2346 struct net_device *netdev = adapter->netdev;
545c67c0 2347 struct e1000_tx_ring *txdr = adapter->tx_ring;
1da177e4
LT		 2348 uint32_t link;
2349
2350 e1000_check_for_link(&adapter->hw);
2d7edb92
MC		 2351 if (adapter->hw.mac_type == e1000_82573) {
2352 e1000_enable_tx_pkt_filtering(&adapter->hw);
2353 if(adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)
2354 e1000_update_mng_vlan(adapter);
2355 }
1da177e4
LT		 2356
2357 if((adapter->hw.media_type == e1000_media_type_internal_serdes) &&
2358 !(E1000_READ_REG(&adapter->hw, TXCW) & E1000_TXCW_ANE))
2359 link = !adapter->hw.serdes_link_down;
2360 else
2361 link = E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU;
2362
2363 if(link) {
2364 if(!netif_carrier_ok(netdev)) {
2365 e1000_get_speed_and_duplex(&adapter->hw,
2366 &adapter->link_speed,
2367 &adapter->link_duplex);
2368
2369 DPRINTK(LINK, INFO, "NIC Link is Up %d Mbps %s\n",
2370 adapter->link_speed,
2371 adapter->link_duplex == FULL_DUPLEX ?
2372 "Full Duplex" : "Half Duplex");
2373
66a2b0a3
JK		 2374 /* tweak tx_queue_len according to speed/duplex */
2375 netdev->tx_queue_len = adapter->tx_queue_len;
2376 adapter->tx_timeout_factor = 1;
2377 if (adapter->link_duplex == HALF_DUPLEX) {
2378 switch (adapter->link_speed) {
2379 case SPEED_10:
2380 netdev->tx_queue_len = 10;
2381 adapter->tx_timeout_factor = 8;
2382 break;
2383 case SPEED_100:
2384 netdev->tx_queue_len = 100;
2385 break;
2386 }
2387 }
2388
1da177e4
LT		 2389 netif_carrier_on(netdev);
2390 netif_wake_queue(netdev);
2391 mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
2392 adapter->smartspeed = 0;
2393 }
2394 } else {
2395 if(netif_carrier_ok(netdev)) {
2396 adapter->link_speed = 0;
2397 adapter->link_duplex = 0;
2398 DPRINTK(LINK, INFO, "NIC Link is Down\n");
2399 netif_carrier_off(netdev);
2400 netif_stop_queue(netdev);
2401 mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
2402 }
2403
2404 e1000_smartspeed(adapter);
2405 }
2406
2407 e1000_update_stats(adapter);
2408
2409 adapter->hw.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2410 adapter->tpt_old = adapter->stats.tpt;
2411 adapter->hw.collision_delta = adapter->stats.colc - adapter->colc_old;
2412 adapter->colc_old = adapter->stats.colc;
2413
2414 adapter->gorcl = adapter->stats.gorcl - adapter->gorcl_old;
2415 adapter->gorcl_old = adapter->stats.gorcl;
2416 adapter->gotcl = adapter->stats.gotcl - adapter->gotcl_old;
2417 adapter->gotcl_old = adapter->stats.gotcl;
2418
2419 e1000_update_adaptive(&adapter->hw);
2420
f56799ea
JK		 2421#ifdef CONFIG_E1000_MQ
2422 txdr = *per_cpu_ptr(adapter->cpu_tx_ring, smp_processor_id());
2423#endif
2424 if (!netif_carrier_ok(netdev)) {
581d708e 2425 if (E1000_DESC_UNUSED(txdr) + 1 < txdr->count) {
1da177e4
LT		 2426 /* We've lost link, so the controller stops DMA,
2427 * but we've got queued Tx work that's never going
2428 * to get done, so reset controller to flush Tx.
2429 * (Do the reset outside of interrupt context). */
2430 schedule_work(&adapter->tx_timeout_task);
2431 }
2432 }
2433
2434 /* Dynamic mode for Interrupt Throttle Rate (ITR) */
2435 if(adapter->hw.mac_type >= e1000_82540 && adapter->itr == 1) {
2436 /* Symmetric Tx/Rx gets a reduced ITR=2000; Total
2437 * asymmetrical Tx or Rx gets ITR=8000; everyone
2438 * else is between 2000-8000. */
2439 uint32_t goc = (adapter->gotcl + adapter->gorcl) / 10000;
2440 uint32_t dif = (adapter->gotcl > adapter->gorcl ?
2441 adapter->gotcl - adapter->gorcl :
2442 adapter->gorcl - adapter->gotcl) / 10000;
2443 uint32_t itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
2444 E1000_WRITE_REG(&adapter->hw, ITR, 1000000000 / (itr * 256));
2445 }
2446
2447 /* Cause software interrupt to ensure rx ring is cleaned */
2448 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_RXDMT0);
2449
2648345f 2450 /* Force detection of hung controller every watchdog period */
1da177e4
LT		 2451 adapter->detect_tx_hung = TRUE;
2452
868d5309
MC		 2453 /* With 82571 controllers, LAA may be overwritten due to controller
2454 * reset from the other port. Set the appropriate LAA in RAR[0] */
2455 if (adapter->hw.mac_type == e1000_82571 && adapter->hw.laa_is_present)
2456 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2457
1da177e4
LT		 2458 /* Reset the timer */
2459 mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
2460}
2461
2462#define E1000_TX_FLAGS_CSUM 0x00000001
2463#define E1000_TX_FLAGS_VLAN 0x00000002
2464#define E1000_TX_FLAGS_TSO 0x00000004
2d7edb92 2465#define E1000_TX_FLAGS_IPV4 0x00000008
1da177e4
LT		 2466#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
2467#define E1000_TX_FLAGS_VLAN_SHIFT 16
2468
2469static inline int
581d708e
MC		 2470e1000_tso(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2471 struct sk_buff *skb)
1da177e4
LT		 2472{
2473#ifdef NETIF_F_TSO
2474 struct e1000_context_desc *context_desc;
545c67c0 2475 struct e1000_buffer *buffer_info;
1da177e4
LT		 2476 unsigned int i;
2477 uint32_t cmd_length = 0;
2d7edb92 2478 uint16_t ipcse = 0, tucse, mss;
1da177e4
LT		 2479 uint8_t ipcss, ipcso, tucss, tucso, hdr_len;
2480 int err;
2481
2482 if(skb_shinfo(skb)->tso_size) {
2483 if (skb_header_cloned(skb)) {
2484 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2485 if (err)
2486 return err;
2487 }
2488
2489 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
2490 mss = skb_shinfo(skb)->tso_size;
2d7edb92
MC		 2491 if(skb->protocol == ntohs(ETH_P_IP)) {
2492 skb->nh.iph->tot_len = 0;
2493 skb->nh.iph->check = 0;
2494 skb->h.th->check =
2495 ~csum_tcpudp_magic(skb->nh.iph->saddr,
2496 skb->nh.iph->daddr,
2497 0,
2498 IPPROTO_TCP,
2499 0);
2500 cmd_length = E1000_TXD_CMD_IP;
2501 ipcse = skb->h.raw - skb->data - 1;
2502#ifdef NETIF_F_TSO_IPV6
2503 } else if(skb->protocol == ntohs(ETH_P_IPV6)) {
2504 skb->nh.ipv6h->payload_len = 0;
2505 skb->h.th->check =
2506 ~csum_ipv6_magic(&skb->nh.ipv6h->saddr,
2507 &skb->nh.ipv6h->daddr,
2508 0,
2509 IPPROTO_TCP,
2510 0);
2511 ipcse = 0;
2512#endif
2513 }
1da177e4
LT		 2514 ipcss = skb->nh.raw - skb->data;
2515 ipcso = (void *)&(skb->nh.iph->check) - (void *)skb->data;
1da177e4
LT		 2516 tucss = skb->h.raw - skb->data;
2517 tucso = (void *)&(skb->h.th->check) - (void *)skb->data;
2518 tucse = 0;
2519
2520 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
2d7edb92 2521 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
1da177e4 2522
581d708e
MC		 2523 i = tx_ring->next_to_use;
2524 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
545c67c0 2525 buffer_info = &tx_ring->buffer_info[i];
1da177e4
LT		 2526
2527 context_desc->lower_setup.ip_fields.ipcss = ipcss;
2528 context_desc->lower_setup.ip_fields.ipcso = ipcso;
2529 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
2530 context_desc->upper_setup.tcp_fields.tucss = tucss;
2531 context_desc->upper_setup.tcp_fields.tucso = tucso;
2532 context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse);
2533 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
2534 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
2535 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
2536
545c67c0
JK		 2537 buffer_info->time_stamp = jiffies;
2538
581d708e
MC		 2539 if (++i == tx_ring->count) i = 0;
2540 tx_ring->next_to_use = i;
1da177e4 2541
8241e35e 2542 return TRUE;
1da177e4
LT		 2543 }
2544#endif
2545
8241e35e 2546 return FALSE;
1da177e4
LT		 2547}
2548
2549static inline boolean_t
581d708e
MC		 2550e1000_tx_csum(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2551 struct sk_buff *skb)
1da177e4
LT		 2552{
2553 struct e1000_context_desc *context_desc;
545c67c0 2554 struct e1000_buffer *buffer_info;
1da177e4
LT		 2555 unsigned int i;
2556 uint8_t css;
2557
2558 if(likely(skb->ip_summed == CHECKSUM_HW)) {
2559 css = skb->h.raw - skb->data;
2560
581d708e 2561 i = tx_ring->next_to_use;
545c67c0 2562 buffer_info = &tx_ring->buffer_info[i];
581d708e 2563 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
1da177e4
LT		 2564
2565 context_desc->upper_setup.tcp_fields.tucss = css;
2566 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum;
2567 context_desc->upper_setup.tcp_fields.tucse = 0;
2568 context_desc->tcp_seg_setup.data = 0;
2569 context_desc->cmd_and_length = cpu_to_le32(E1000_TXD_CMD_DEXT);
2570
545c67c0
JK		 2571 buffer_info->time_stamp = jiffies;
2572
581d708e
MC		 2573 if (unlikely(++i == tx_ring->count)) i = 0;
2574 tx_ring->next_to_use = i;
1da177e4
LT		 2575
2576 return TRUE;
2577 }
2578
2579 return FALSE;
2580}
2581
2582#define E1000_MAX_TXD_PWR 12
2583#define E1000_MAX_DATA_PER_TXD (1<<E1000_MAX_TXD_PWR)
2584
2585static inline int
581d708e
MC		 2586e1000_tx_map(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2587 struct sk_buff *skb, unsigned int first, unsigned int max_per_txd,
2588 unsigned int nr_frags, unsigned int mss)
1da177e4 2589{
1da177e4
LT		 2590 struct e1000_buffer *buffer_info;
2591 unsigned int len = skb->len;
2592 unsigned int offset = 0, size, count = 0, i;
2593 unsigned int f;
2594 len -= skb->data_len;
2595
2596 i = tx_ring->next_to_use;
2597
2598 while(len) {
2599 buffer_info = &tx_ring->buffer_info[i];
2600 size = min(len, max_per_txd);
2601#ifdef NETIF_F_TSO
fd803241
JK		 2602 /* Workaround for Controller erratum --
2603 * descriptor for non-tso packet in a linear SKB that follows a
2604 * tso gets written back prematurely before the data is fully
2605 * DMAd to the controller */
2606 if (!skb->data_len && tx_ring->last_tx_tso &&
2607 !skb_shinfo(skb)->tso_size) {
2608 tx_ring->last_tx_tso = 0;
2609 size -= 4;
2610 }
2611
1da177e4
LT		 2612 /* Workaround for premature desc write-backs
2613 * in TSO mode. Append 4-byte sentinel desc */
2614 if(unlikely(mss && !nr_frags && size == len && size > 8))
2615 size -= 4;
2616#endif
97338bde
MC		 2617 /* work-around for errata 10 and it applies
2618 * to all controllers in PCI-X mode
2619 * The fix is to make sure that the first descriptor of a
2620 * packet is smaller than 2048 - 16 - 16 (or 2016) bytes
2621 */
2622 if(unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
2623 (size > 2015) && count == 0))
2624 size = 2015;
2625
1da177e4
LT		 2626 /* Workaround for potential 82544 hang in PCI-X. Avoid
2627 * terminating buffers within evenly-aligned dwords. */
2628 if(unlikely(adapter->pcix_82544 &&
2629 !((unsigned long)(skb->data + offset + size - 1) & 4) &&
2630 size > 4))
2631 size -= 4;
2632
2633 buffer_info->length = size;
2634 buffer_info->dma =
2635 pci_map_single(adapter->pdev,
2636 skb->data + offset,
2637 size,
2638 PCI_DMA_TODEVICE);
2639 buffer_info->time_stamp = jiffies;
2640
2641 len -= size;
2642 offset += size;
2643 count++;
2644 if(unlikely(++i == tx_ring->count)) i = 0;
2645 }
2646
2647 for(f = 0; f < nr_frags; f++) {
2648 struct skb_frag_struct *frag;
2649
2650 frag = &skb_shinfo(skb)->frags[f];
2651 len = frag->size;
2652 offset = frag->page_offset;
2653
2654 while(len) {
2655 buffer_info = &tx_ring->buffer_info[i];
2656 size = min(len, max_per_txd);
2657#ifdef NETIF_F_TSO
2658 /* Workaround for premature desc write-backs
2659 * in TSO mode. Append 4-byte sentinel desc */
2660 if(unlikely(mss && f == (nr_frags-1) && size == len && size > 8))
2661 size -= 4;
2662#endif
2663 /* Workaround for potential 82544 hang in PCI-X.
2664 * Avoid terminating buffers within evenly-aligned
2665 * dwords. */
2666 if(unlikely(adapter->pcix_82544 &&
2667 !((unsigned long)(frag->page+offset+size-1) & 4) &&
2668 size > 4))
2669 size -= 4;
2670
2671 buffer_info->length = size;
2672 buffer_info->dma =
2673 pci_map_page(adapter->pdev,
2674 frag->page,
2675 offset,
2676 size,
2677 PCI_DMA_TODEVICE);
2678 buffer_info->time_stamp = jiffies;
2679
2680 len -= size;
2681 offset += size;
2682 count++;
2683 if(unlikely(++i == tx_ring->count)) i = 0;
2684 }
2685 }
2686
2687 i = (i == 0) ? tx_ring->count - 1 : i - 1;
2688 tx_ring->buffer_info[i].skb = skb;
2689 tx_ring->buffer_info[first].next_to_watch = i;
2690
2691 return count;
2692}
2693
2694static inline void
581d708e
MC		 2695e1000_tx_queue(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2696 int tx_flags, int count)
1da177e4 2697{
1da177e4
LT		 2698 struct e1000_tx_desc *tx_desc = NULL;
2699 struct e1000_buffer *buffer_info;
2700 uint32_t txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
2701 unsigned int i;
2702
2703 if(likely(tx_flags & E1000_TX_FLAGS_TSO)) {
2704 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
2705 E1000_TXD_CMD_TSE;
2d7edb92
MC		 2706 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2707
2708 if(likely(tx_flags & E1000_TX_FLAGS_IPV4))
2709 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
1da177e4
LT		 2710 }
2711
2712 if(likely(tx_flags & E1000_TX_FLAGS_CSUM)) {
2713 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
2714 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2715 }
2716
2717 if(unlikely(tx_flags & E1000_TX_FLAGS_VLAN)) {
2718 txd_lower |= E1000_TXD_CMD_VLE;
2719 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
2720 }
2721
2722 i = tx_ring->next_to_use;
2723
2724 while(count--) {
2725 buffer_info = &tx_ring->buffer_info[i];
2726 tx_desc = E1000_TX_DESC(*tx_ring, i);
2727 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
2728 tx_desc->lower.data =
2729 cpu_to_le32(txd_lower | buffer_info->length);
2730 tx_desc->upper.data = cpu_to_le32(txd_upper);
2731 if(unlikely(++i == tx_ring->count)) i = 0;
2732 }
2733
2734 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
2735
2736 /* Force memory writes to complete before letting h/w
2737 * know there are new descriptors to fetch. (Only
2738 * applicable for weak-ordered memory model archs,
2739 * such as IA-64). */
2740 wmb();
2741
2742 tx_ring->next_to_use = i;
581d708e 2743 writel(i, adapter->hw.hw_addr + tx_ring->tdt);
1da177e4
LT		 2744}
2745
2746/**
2747 * 82547 workaround to avoid controller hang in half-duplex environment.
2748 * The workaround is to avoid queuing a large packet that would span
2749 * the internal Tx FIFO ring boundary by notifying the stack to resend
2750 * the packet at a later time. This gives the Tx FIFO an opportunity to
2751 * flush all packets. When that occurs, we reset the Tx FIFO pointers
2752 * to the beginning of the Tx FIFO.
2753 **/
2754
2755#define E1000_FIFO_HDR 0x10
2756#define E1000_82547_PAD_LEN 0x3E0
2757
2758static inline int
2759e1000_82547_fifo_workaround(struct e1000_adapter *adapter, struct sk_buff *skb)
2760{
2761 uint32_t fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
2762 uint32_t skb_fifo_len = skb->len + E1000_FIFO_HDR;
2763
2764 E1000_ROUNDUP(skb_fifo_len, E1000_FIFO_HDR);
2765
2766 if(adapter->link_duplex != HALF_DUPLEX)
2767 goto no_fifo_stall_required;
2768
2769 if(atomic_read(&adapter->tx_fifo_stall))
2770 return 1;
2771
2772 if(skb_fifo_len >= (E1000_82547_PAD_LEN + fifo_space)) {
2773 atomic_set(&adapter->tx_fifo_stall, 1);
2774 return 1;
2775 }
2776
2777no_fifo_stall_required:
2778 adapter->tx_fifo_head += skb_fifo_len;
2779 if(adapter->tx_fifo_head >= adapter->tx_fifo_size)
2780 adapter->tx_fifo_head -= adapter->tx_fifo_size;
2781 return 0;
2782}
2783
2d7edb92
MC		 2784#define MINIMUM_DHCP_PACKET_SIZE 282
2785static inline int
2786e1000_transfer_dhcp_info(struct e1000_adapter *adapter, struct sk_buff *skb)
2787{
2788 struct e1000_hw *hw = &adapter->hw;
2789 uint16_t length, offset;
2790 if(vlan_tx_tag_present(skb)) {
2791 if(!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
2792 ( adapter->hw.mng_cookie.status &
2793 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) )
2794 return 0;
2795 }
a174fd88 2796 if ((skb->len > MINIMUM_DHCP_PACKET_SIZE) && (!skb->protocol)) {
2d7edb92
MC		 2797 struct ethhdr *eth = (struct ethhdr *) skb->data;
2798 if((htons(ETH_P_IP) == eth->h_proto)) {
2799 const struct iphdr *ip =
2800 (struct iphdr *)((uint8_t *)skb->data+14);
2801 if(IPPROTO_UDP == ip->protocol) {
2802 struct udphdr *udp =
2803 (struct udphdr *)((uint8_t *)ip +
2804 (ip->ihl << 2));
2805 if(ntohs(udp->dest) == 67) {
2806 offset = (uint8_t *)udp + 8 - skb->data;
2807 length = skb->len - offset;
2808
2809 return e1000_mng_write_dhcp_info(hw,
2810 (uint8_t *)udp + 8,
2811 length);
2812 }
2813 }
2814 }
2815 }
2816 return 0;
2817}
2818
1da177e4
LT		 2819#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 )
2820static int
2821e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2822{
60490fe0 2823 struct e1000_adapter *adapter = netdev_priv(netdev);
581d708e 2824 struct e1000_tx_ring *tx_ring;
1da177e4
LT		 2825 unsigned int first, max_per_txd = E1000_MAX_DATA_PER_TXD;
2826 unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
2827 unsigned int tx_flags = 0;
2828 unsigned int len = skb->len;
2829 unsigned long flags;
2830 unsigned int nr_frags = 0;
2831 unsigned int mss = 0;
2832 int count = 0;
2833 int tso;
2834 unsigned int f;
2835 len -= skb->data_len;
2836
24025e4e
MC		 2837#ifdef CONFIG_E1000_MQ
2838 tx_ring = *per_cpu_ptr(adapter->cpu_tx_ring, smp_processor_id());
2839#else
581d708e 2840 tx_ring = adapter->tx_ring;
24025e4e
MC		 2841#endif
2842
581d708e 2843 if (unlikely(skb->len <= 0)) {
1da177e4
LT		 2844 dev_kfree_skb_any(skb);
2845 return NETDEV_TX_OK;
2846 }
2847
2848#ifdef NETIF_F_TSO
2849 mss = skb_shinfo(skb)->tso_size;
2648345f 2850 /* The controller does a simple calculation to
1da177e4
LT		 2851 * make sure there is enough room in the FIFO before
2852 * initiating the DMA for each buffer. The calc is:
2853 * 4 = ceil(buffer len/mss). To make sure we don't
2854 * overrun the FIFO, adjust the max buffer len if mss
2855 * drops. */
2856 if(mss) {
9a3056da 2857 uint8_t hdr_len;
1da177e4
LT		 2858 max_per_txd = min(mss << 2, max_per_txd);
2859 max_txd_pwr = fls(max_per_txd) - 1;
9a3056da
JK		 2860
2861 /* TSO Workaround for 82571/2 Controllers -- if skb->data
2862 * points to just header, pull a few bytes of payload from
2863 * frags into skb->data */
2864 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
2865 if (skb->data_len && (hdr_len == (skb->len - skb->data_len)) &&
2866 (adapter->hw.mac_type == e1000_82571 ||
2867 adapter->hw.mac_type == e1000_82572)) {
d74bbd3b
JK		 2868 unsigned int pull_size;
2869 pull_size = min((unsigned int)4, skb->data_len);
2870 if (!__pskb_pull_tail(skb, pull_size)) {
2871 printk(KERN_ERR "__pskb_pull_tail failed.\n");
2872 dev_kfree_skb_any(skb);
2873 return -EFAULT;
2874 }
9a3056da
JK		 2875 len = skb->len - skb->data_len;
2876 }
1da177e4
LT		 2877 }
2878
2879 if((mss) || (skb->ip_summed == CHECKSUM_HW))
9a3056da 2880 /* reserve a descriptor for the offload context */
1da177e4 2881 count++;
2648345f 2882 count++;
1da177e4
LT		 2883#else
2884 if(skb->ip_summed == CHECKSUM_HW)
2885 count++;
2886#endif
fd803241
JK		 2887
2888#ifdef NETIF_F_TSO
2889 /* Controller Erratum workaround */
2890 if (!skb->data_len && tx_ring->last_tx_tso &&
2891 !skb_shinfo(skb)->tso_size)
2892 count++;
2893#endif
2894
1da177e4
LT		 2895 count += TXD_USE_COUNT(len, max_txd_pwr);
2896
2897 if(adapter->pcix_82544)
2898 count++;
2899
97338bde
MC		 2900 /* work-around for errata 10 and it applies to all controllers
2901 * in PCI-X mode, so add one more descriptor to the count
2902 */
2903 if(unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
2904 (len > 2015)))
2905 count++;
2906
1da177e4
LT		 2907 nr_frags = skb_shinfo(skb)->nr_frags;
2908 for(f = 0; f < nr_frags; f++)
2909 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size,
2910 max_txd_pwr);
2911 if(adapter->pcix_82544)
2912 count += nr_frags;
2913
2d7edb92
MC		 2914 if(adapter->hw.tx_pkt_filtering && (adapter->hw.mac_type == e1000_82573) )
2915 e1000_transfer_dhcp_info(adapter, skb);
2916
581d708e
MC		 2917 local_irq_save(flags);
2918 if (!spin_trylock(&tx_ring->tx_lock)) {
2919 /* Collision - tell upper layer to requeue */
2920 local_irq_restore(flags);
2921 return NETDEV_TX_LOCKED;
2922 }
1da177e4
LT		 2923
2924 /* need: count + 2 desc gap to keep tail from touching
2925 * head, otherwise try next time */
581d708e 2926 if (unlikely(E1000_DESC_UNUSED(tx_ring) < count + 2)) {
1da177e4 2927 netif_stop_queue(netdev);
581d708e 2928 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2929 return NETDEV_TX_BUSY;
2930 }
2931
2932 if(unlikely(adapter->hw.mac_type == e1000_82547)) {
2933 if(unlikely(e1000_82547_fifo_workaround(adapter, skb))) {
2934 netif_stop_queue(netdev);
2935 mod_timer(&adapter->tx_fifo_stall_timer, jiffies);
581d708e 2936 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2937 return NETDEV_TX_BUSY;
2938 }
2939 }
2940
2941 if(unlikely(adapter->vlgrp && vlan_tx_tag_present(skb))) {
2942 tx_flags |= E1000_TX_FLAGS_VLAN;
2943 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
2944 }
2945
581d708e 2946 first = tx_ring->next_to_use;
1da177e4 2947
581d708e 2948 tso = e1000_tso(adapter, tx_ring, skb);
1da177e4
LT		 2949 if (tso < 0) {
2950 dev_kfree_skb_any(skb);
581d708e 2951 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2952 return NETDEV_TX_OK;
2953 }
2954
fd803241
JK		 2955 if (likely(tso)) {
2956 tx_ring->last_tx_tso = 1;
1da177e4 2957 tx_flags |= E1000_TX_FLAGS_TSO;
fd803241 2958 } else if (likely(e1000_tx_csum(adapter, tx_ring, skb)))
1da177e4
LT		 2959 tx_flags |= E1000_TX_FLAGS_CSUM;
2960
2d7edb92 2961 /* Old method was to assume IPv4 packet by default if TSO was enabled.
868d5309 2962 * 82571 hardware supports TSO capabilities for IPv6 as well...
2d7edb92 2963 * no longer assume, we must. */
581d708e 2964 if (likely(skb->protocol == ntohs(ETH_P_IP)))
2d7edb92
MC		 2965 tx_flags |= E1000_TX_FLAGS_IPV4;
2966
581d708e
MC		 2967 e1000_tx_queue(adapter, tx_ring, tx_flags,
2968 e1000_tx_map(adapter, tx_ring, skb, first,
2969 max_per_txd, nr_frags, mss));
1da177e4
LT		 2970
2971 netdev->trans_start = jiffies;
2972
2973 /* Make sure there is space in the ring for the next send. */
581d708e 2974 if (unlikely(E1000_DESC_UNUSED(tx_ring) < MAX_SKB_FRAGS + 2))
1da177e4
LT		 2975 netif_stop_queue(netdev);
2976
581d708e 2977 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2978 return NETDEV_TX_OK;
2979}
2980
2981/**
2982 * e1000_tx_timeout - Respond to a Tx Hang
2983 * @netdev: network interface device structure
2984 **/
2985
2986static void
2987e1000_tx_timeout(struct net_device *netdev)
2988{
60490fe0 2989 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2990
2991 /* Do the reset outside of interrupt context */
2992 schedule_work(&adapter->tx_timeout_task);
2993}
2994
2995static void
2996e1000_tx_timeout_task(struct net_device *netdev)
2997{
60490fe0 2998 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 2999
6b7660cd 3000 adapter->tx_timeout_count++;
1da177e4
LT		 3001 e1000_down(adapter);
3002 e1000_up(adapter);
3003}
3004
3005/**
3006 * e1000_get_stats - Get System Network Statistics
3007 * @netdev: network interface device structure
3008 *
3009 * Returns the address of the device statistics structure.
3010 * The statistics are actually updated from the timer callback.
3011 **/
3012
3013static struct net_device_stats *
3014e1000_get_stats(struct net_device *netdev)
3015{
60490fe0 3016 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3017
6b7660cd 3018 /* only return the current stats */
1da177e4
LT		 3019 return &adapter->net_stats;
3020}
3021
3022/**
3023 * e1000_change_mtu - Change the Maximum Transfer Unit
3024 * @netdev: network interface device structure
3025 * @new_mtu: new value for maximum frame size
3026 *
3027 * Returns 0 on success, negative on failure
3028 **/
3029
3030static int
3031e1000_change_mtu(struct net_device *netdev, int new_mtu)
3032{
60490fe0 3033 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 3034 int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
3035
3036 if((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) ||
3037 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3038 DPRINTK(PROBE, ERR, "Invalid MTU setting\n");
1da177e4 3039 return -EINVAL;
2d7edb92 3040 }
1da177e4 3041
997f5cbd
JK		 3042 /* Adapter-specific max frame size limits. */
3043 switch (adapter->hw.mac_type) {
3044 case e1000_82542_rev2_0:
3045 case e1000_82542_rev2_1:
3046 case e1000_82573:
3047 if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
3048 DPRINTK(PROBE, ERR, "Jumbo Frames not supported.\n");
2d7edb92 3049 return -EINVAL;
2d7edb92 3050 }
997f5cbd
JK		 3051 break;
3052 case e1000_82571:
3053 case e1000_82572:
3054#define MAX_STD_JUMBO_FRAME_SIZE 9234
3055 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3056 DPRINTK(PROBE, ERR, "MTU > 9216 not supported.\n");
3057 return -EINVAL;
3058 }
3059 break;
3060 default:
3061 /* Capable of supporting up to MAX_JUMBO_FRAME_SIZE limit. */
3062 break;
1da177e4
LT		 3063 }
3064
997f5cbd
JK		 3065 /* since the driver code now supports splitting a packet across
3066 * multiple descriptors, most of the fifo related limitations on
3067 * jumbo frame traffic have gone away.
3068 * simply use 2k descriptors for everything.
3069 *
3070 * NOTE: dev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3071 * means we reserve 2 more, this pushes us to allocate from the next
3072 * larger slab size
3073 * i.e. RXBUFFER_2048 --> size-4096 slab */
3074
3075 /* recent hardware supports 1KB granularity */
3076 if (adapter->hw.mac_type > e1000_82547_rev_2) {
3077 adapter->rx_buffer_len =
3078 ((max_frame < E1000_RXBUFFER_2048) ?
3079 max_frame : E1000_RXBUFFER_2048);
3080 E1000_ROUNDUP(adapter->rx_buffer_len, 1024);
3081 } else
3082 adapter->rx_buffer_len = E1000_RXBUFFER_2048;
3083
2d7edb92
MC		 3084 netdev->mtu = new_mtu;
3085
3086 if(netif_running(netdev)) {
1da177e4
LT		 3087 e1000_down(adapter);
3088 e1000_up(adapter);
3089 }
3090
1da177e4
LT		 3091 adapter->hw.max_frame_size = max_frame;
3092
3093 return 0;
3094}
3095
3096/**
3097 * e1000_update_stats - Update the board statistics counters
3098 * @adapter: board private structure
3099 **/
3100
3101void
3102e1000_update_stats(struct e1000_adapter *adapter)
3103{
3104 struct e1000_hw *hw = &adapter->hw;
3105 unsigned long flags;
3106 uint16_t phy_tmp;
3107
3108#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3109
3110 spin_lock_irqsave(&adapter->stats_lock, flags);
3111
3112 /* these counters are modified from e1000_adjust_tbi_stats,
3113 * called from the interrupt context, so they must only
3114 * be written while holding adapter->stats_lock
3115 */
3116
3117 adapter->stats.crcerrs += E1000_READ_REG(hw, CRCERRS);
3118 adapter->stats.gprc += E1000_READ_REG(hw, GPRC);
3119 adapter->stats.gorcl += E1000_READ_REG(hw, GORCL);
3120 adapter->stats.gorch += E1000_READ_REG(hw, GORCH);
3121 adapter->stats.bprc += E1000_READ_REG(hw, BPRC);
3122 adapter->stats.mprc += E1000_READ_REG(hw, MPRC);
3123 adapter->stats.roc += E1000_READ_REG(hw, ROC);
3124 adapter->stats.prc64 += E1000_READ_REG(hw, PRC64);
3125 adapter->stats.prc127 += E1000_READ_REG(hw, PRC127);
3126 adapter->stats.prc255 += E1000_READ_REG(hw, PRC255);
3127 adapter->stats.prc511 += E1000_READ_REG(hw, PRC511);
3128 adapter->stats.prc1023 += E1000_READ_REG(hw, PRC1023);
3129 adapter->stats.prc1522 += E1000_READ_REG(hw, PRC1522);
3130
3131 adapter->stats.symerrs += E1000_READ_REG(hw, SYMERRS);
3132 adapter->stats.mpc += E1000_READ_REG(hw, MPC);
3133 adapter->stats.scc += E1000_READ_REG(hw, SCC);
3134 adapter->stats.ecol += E1000_READ_REG(hw, ECOL);
3135 adapter->stats.mcc += E1000_READ_REG(hw, MCC);
3136 adapter->stats.latecol += E1000_READ_REG(hw, LATECOL);
3137 adapter->stats.dc += E1000_READ_REG(hw, DC);
3138 adapter->stats.sec += E1000_READ_REG(hw, SEC);
3139 adapter->stats.rlec += E1000_READ_REG(hw, RLEC);
3140 adapter->stats.xonrxc += E1000_READ_REG(hw, XONRXC);
3141 adapter->stats.xontxc += E1000_READ_REG(hw, XONTXC);
3142 adapter->stats.xoffrxc += E1000_READ_REG(hw, XOFFRXC);
3143 adapter->stats.xofftxc += E1000_READ_REG(hw, XOFFTXC);
3144 adapter->stats.fcruc += E1000_READ_REG(hw, FCRUC);
3145 adapter->stats.gptc += E1000_READ_REG(hw, GPTC);
3146 adapter->stats.gotcl += E1000_READ_REG(hw, GOTCL);
3147 adapter->stats.gotch += E1000_READ_REG(hw, GOTCH);
3148 adapter->stats.rnbc += E1000_READ_REG(hw, RNBC);
3149 adapter->stats.ruc += E1000_READ_REG(hw, RUC);
3150 adapter->stats.rfc += E1000_READ_REG(hw, RFC);
3151 adapter->stats.rjc += E1000_READ_REG(hw, RJC);
3152 adapter->stats.torl += E1000_READ_REG(hw, TORL);
3153 adapter->stats.torh += E1000_READ_REG(hw, TORH);
3154 adapter->stats.totl += E1000_READ_REG(hw, TOTL);
3155 adapter->stats.toth += E1000_READ_REG(hw, TOTH);
3156 adapter->stats.tpr += E1000_READ_REG(hw, TPR);
3157 adapter->stats.ptc64 += E1000_READ_REG(hw, PTC64);
3158 adapter->stats.ptc127 += E1000_READ_REG(hw, PTC127);
3159 adapter->stats.ptc255 += E1000_READ_REG(hw, PTC255);
3160 adapter->stats.ptc511 += E1000_READ_REG(hw, PTC511);
3161 adapter->stats.ptc1023 += E1000_READ_REG(hw, PTC1023);
3162 adapter->stats.ptc1522 += E1000_READ_REG(hw, PTC1522);
3163 adapter->stats.mptc += E1000_READ_REG(hw, MPTC);
3164 adapter->stats.bptc += E1000_READ_REG(hw, BPTC);
3165
3166 /* used for adaptive IFS */
3167
3168 hw->tx_packet_delta = E1000_READ_REG(hw, TPT);
3169 adapter->stats.tpt += hw->tx_packet_delta;
3170 hw->collision_delta = E1000_READ_REG(hw, COLC);
3171 adapter->stats.colc += hw->collision_delta;
3172
3173 if(hw->mac_type >= e1000_82543) {
3174 adapter->stats.algnerrc += E1000_READ_REG(hw, ALGNERRC);
3175 adapter->stats.rxerrc += E1000_READ_REG(hw, RXERRC);
3176 adapter->stats.tncrs += E1000_READ_REG(hw, TNCRS);
3177 adapter->stats.cexterr += E1000_READ_REG(hw, CEXTERR);
3178 adapter->stats.tsctc += E1000_READ_REG(hw, TSCTC);
3179 adapter->stats.tsctfc += E1000_READ_REG(hw, TSCTFC);
3180 }
2d7edb92
MC		 3181 if(hw->mac_type > e1000_82547_rev_2) {
3182 adapter->stats.iac += E1000_READ_REG(hw, IAC);
3183 adapter->stats.icrxoc += E1000_READ_REG(hw, ICRXOC);
3184 adapter->stats.icrxptc += E1000_READ_REG(hw, ICRXPTC);
3185 adapter->stats.icrxatc += E1000_READ_REG(hw, ICRXATC);
3186 adapter->stats.ictxptc += E1000_READ_REG(hw, ICTXPTC);
3187 adapter->stats.ictxatc += E1000_READ_REG(hw, ICTXATC);
3188 adapter->stats.ictxqec += E1000_READ_REG(hw, ICTXQEC);
3189 adapter->stats.ictxqmtc += E1000_READ_REG(hw, ICTXQMTC);
3190 adapter->stats.icrxdmtc += E1000_READ_REG(hw, ICRXDMTC);
3191 }
1da177e4
LT		 3192
3193 /* Fill out the OS statistics structure */
3194
3195 adapter->net_stats.rx_packets = adapter->stats.gprc;
3196 adapter->net_stats.tx_packets = adapter->stats.gptc;
3197 adapter->net_stats.rx_bytes = adapter->stats.gorcl;
3198 adapter->net_stats.tx_bytes = adapter->stats.gotcl;
3199 adapter->net_stats.multicast = adapter->stats.mprc;
3200 adapter->net_stats.collisions = adapter->stats.colc;
3201
3202 /* Rx Errors */
3203
3204 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3205 adapter->stats.crcerrs + adapter->stats.algnerrc +
6b7660cd
JK		 3206 adapter->stats.rlec + adapter->stats.cexterr;
3207 adapter->net_stats.rx_dropped = 0;
1da177e4
LT		 3208 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
3209 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3210 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
1da177e4
LT		 3211 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3212
3213 /* Tx Errors */
3214
3215 adapter->net_stats.tx_errors = adapter->stats.ecol +
3216 adapter->stats.latecol;
3217 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3218 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3219 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3220
3221 /* Tx Dropped needs to be maintained elsewhere */
3222
3223 /* Phy Stats */
3224
3225 if(hw->media_type == e1000_media_type_copper) {
3226 if((adapter->link_speed == SPEED_1000) &&
3227 (!e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3228 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3229 adapter->phy_stats.idle_errors += phy_tmp;
3230 }
3231
3232 if((hw->mac_type <= e1000_82546) &&
3233 (hw->phy_type == e1000_phy_m88) &&
3234 !e1000_read_phy_reg(hw, M88E1000_RX_ERR_CNTR, &phy_tmp))
3235 adapter->phy_stats.receive_errors += phy_tmp;
3236 }
3237
3238 spin_unlock_irqrestore(&adapter->stats_lock, flags);
3239}
3240
24025e4e
MC		 3241#ifdef CONFIG_E1000_MQ
3242void
3243e1000_rx_schedule(void *data)
3244{
3245 struct net_device *poll_dev, *netdev = data;
3246 struct e1000_adapter *adapter = netdev->priv;
3247 int this_cpu = get_cpu();
3248
3249 poll_dev = *per_cpu_ptr(adapter->cpu_netdev, this_cpu);
3250 if (poll_dev == NULL) {
3251 put_cpu();
3252 return;
3253 }
3254
3255 if (likely(netif_rx_schedule_prep(poll_dev)))
3256 __netif_rx_schedule(poll_dev);
3257 else
3258 e1000_irq_enable(adapter);
3259
3260 put_cpu();
3261}
3262#endif
3263
1da177e4
LT		 3264/**
3265 * e1000_intr - Interrupt Handler
3266 * @irq: interrupt number
3267 * @data: pointer to a network interface device structure
3268 * @pt_regs: CPU registers structure
3269 **/
3270
3271static irqreturn_t
3272e1000_intr(int irq, void *data, struct pt_regs *regs)
3273{
3274 struct net_device *netdev = data;
60490fe0 3275 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 3276 struct e1000_hw *hw = &adapter->hw;
3277 uint32_t icr = E1000_READ_REG(hw, ICR);
1e613fd9 3278#ifndef CONFIG_E1000_NAPI
581d708e 3279 int i;
1e613fd9
JK		 3280#else
3281 /* Interrupt Auto-Mask...upon reading ICR,
3282 * interrupts are masked. No need for the
3283 * IMC write, but it does mean we should
3284 * account for it ASAP. */
3285 if (likely(hw->mac_type >= e1000_82571))
3286 atomic_inc(&adapter->irq_sem);
be2b28ed 3287#endif
1da177e4 3288
1e613fd9
JK		 3289 if (unlikely(!icr)) {
3290#ifdef CONFIG_E1000_NAPI
3291 if (hw->mac_type >= e1000_82571)
3292 e1000_irq_enable(adapter);
3293#endif
1da177e4 3294 return IRQ_NONE; /* Not our interrupt */
1e613fd9 3295 }
1da177e4
LT		 3296
3297 if(unlikely(icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))) {
3298 hw->get_link_status = 1;
3299 mod_timer(&adapter->watchdog_timer, jiffies);
3300 }
3301
3302#ifdef CONFIG_E1000_NAPI
1e613fd9
JK		 3303 if (unlikely(hw->mac_type < e1000_82571)) {
3304 atomic_inc(&adapter->irq_sem);
3305 E1000_WRITE_REG(hw, IMC, ~0);
3306 E1000_WRITE_FLUSH(hw);
3307 }
24025e4e
MC		 3308#ifdef CONFIG_E1000_MQ
3309 if (atomic_read(&adapter->rx_sched_call_data.count) == 0) {
f56799ea
JK		 3310 /* We must setup the cpumask once count == 0 since
3311 * each cpu bit is cleared when the work is done. */
3312 adapter->rx_sched_call_data.cpumask = adapter->cpumask;
3313 atomic_add(adapter->num_rx_queues - 1, &adapter->irq_sem);
3314 atomic_set(&adapter->rx_sched_call_data.count,
3315 adapter->num_rx_queues);
24025e4e
MC		 3316 smp_call_async_mask(&adapter->rx_sched_call_data);
3317 } else {
3318 printk("call_data.count == %u\n", atomic_read(&adapter->rx_sched_call_data.count));
1da177e4 3319 }
be2b28ed 3320#else /* if !CONFIG_E1000_MQ */
581d708e
MC		 3321 if (likely(netif_rx_schedule_prep(&adapter->polling_netdev[0])))
3322 __netif_rx_schedule(&adapter->polling_netdev[0]);
3323 else
3324 e1000_irq_enable(adapter);
be2b28ed
JG		 3325#endif /* CONFIG_E1000_MQ */
3326
3327#else /* if !CONFIG_E1000_NAPI */
1da177e4
LT		 3328 /* Writing IMC and IMS is needed for 82547.
3329 Due to Hub Link bus being occupied, an interrupt
3330 de-assertion message is not able to be sent.
3331 When an interrupt assertion message is generated later,
3332 two messages are re-ordered and sent out.
3333 That causes APIC to think 82547 is in de-assertion
3334 state, while 82547 is in assertion state, resulting
3335 in dead lock. Writing IMC forces 82547 into
3336 de-assertion state.
3337 */
3338 if(hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2){
3339 atomic_inc(&adapter->irq_sem);
2648345f 3340 E1000_WRITE_REG(hw, IMC, ~0);
1da177e4
LT		 3341 }
3342
3343 for(i = 0; i < E1000_MAX_INTR; i++)
581d708e
MC		 3344 if(unlikely(!adapter->clean_rx(adapter, adapter->rx_ring) &
3345 !e1000_clean_tx_irq(adapter, adapter->tx_ring)))
1da177e4
LT		 3346 break;
3347
3348 if(hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2)
3349 e1000_irq_enable(adapter);
581d708e 3350
be2b28ed 3351#endif /* CONFIG_E1000_NAPI */
1da177e4
LT		 3352
3353 return IRQ_HANDLED;
3354}
3355
3356#ifdef CONFIG_E1000_NAPI
3357/**
3358 * e1000_clean - NAPI Rx polling callback
3359 * @adapter: board private structure
3360 **/
3361
3362static int
581d708e 3363e1000_clean(struct net_device *poll_dev, int *budget)
1da177e4 3364{
581d708e
MC		 3365 struct e1000_adapter *adapter;
3366 int work_to_do = min(*budget, poll_dev->quota);
3367 int tx_cleaned, i = 0, work_done = 0;
3368
3369 /* Must NOT use netdev_priv macro here. */
3370 adapter = poll_dev->priv;
3371
3372 /* Keep link state information with original netdev */
3373 if (!netif_carrier_ok(adapter->netdev))
3374 goto quit_polling;
2648345f 3375
581d708e
MC		 3376 while (poll_dev != &adapter->polling_netdev[i]) {
3377 i++;
f56799ea 3378 if (unlikely(i == adapter->num_rx_queues))
581d708e
MC		 3379 BUG();
3380 }
3381
8241e35e
JK		 3382 if (likely(adapter->num_tx_queues == 1)) {
3383 /* e1000_clean is called per-cpu. This lock protects
3384 * tx_ring[0] from being cleaned by multiple cpus
3385 * simultaneously. A failure obtaining the lock means
3386 * tx_ring[0] is currently being cleaned anyway. */
3387 if (spin_trylock(&adapter->tx_queue_lock)) {
3388 tx_cleaned = e1000_clean_tx_irq(adapter,
3389 &adapter->tx_ring[0]);
3390 spin_unlock(&adapter->tx_queue_lock);
3391 }
3392 } else
3393 tx_cleaned = e1000_clean_tx_irq(adapter, &adapter->tx_ring[i]);
3394
581d708e
MC		 3395 adapter->clean_rx(adapter, &adapter->rx_ring[i],
3396 &work_done, work_to_do);
1da177e4
LT		 3397
3398 *budget -= work_done;
581d708e 3399 poll_dev->quota -= work_done;
1da177e4 3400
2b02893e 3401 /* If no Tx and not enough Rx work done, exit the polling mode */
581d708e
MC		 3402 if((!tx_cleaned && (work_done == 0)) ||
3403 !netif_running(adapter->netdev)) {
3404quit_polling:
3405 netif_rx_complete(poll_dev);
1da177e4
LT		 3406 e1000_irq_enable(adapter);
3407 return 0;
3408 }
3409
3410 return 1;
3411}
3412
3413#endif
3414/**
3415 * e1000_clean_tx_irq - Reclaim resources after transmit completes
3416 * @adapter: board private structure
3417 **/
3418
3419static boolean_t
581d708e
MC		 3420e1000_clean_tx_irq(struct e1000_adapter *adapter,
3421 struct e1000_tx_ring *tx_ring)
1da177e4 3422{
1da177e4
LT		 3423 struct net_device *netdev = adapter->netdev;
3424 struct e1000_tx_desc *tx_desc, *eop_desc;
3425 struct e1000_buffer *buffer_info;
3426 unsigned int i, eop;
3427 boolean_t cleaned = FALSE;
3428
3429 i = tx_ring->next_to_clean;
3430 eop = tx_ring->buffer_info[i].next_to_watch;
3431 eop_desc = E1000_TX_DESC(*tx_ring, eop);
3432
581d708e 3433 while (eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) {
1da177e4
LT		 3434 for(cleaned = FALSE; !cleaned; ) {
3435 tx_desc = E1000_TX_DESC(*tx_ring, i);
3436 buffer_info = &tx_ring->buffer_info[i];
3437 cleaned = (i == eop);
3438
8241e35e
JK		 3439#ifdef CONFIG_E1000_MQ
3440 tx_ring->tx_stats.bytes += buffer_info->length;
3441#endif
fd803241 3442 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
8241e35e 3443 memset(tx_desc, 0, sizeof(struct e1000_tx_desc));
1da177e4 3444
1da177e4
LT		 3445 if(unlikely(++i == tx_ring->count)) i = 0;
3446 }
581d708e 3447
7bfa4816
JK		 3448#ifdef CONFIG_E1000_MQ
3449 tx_ring->tx_stats.packets++;
3450#endif
3451
1da177e4
LT		 3452 eop = tx_ring->buffer_info[i].next_to_watch;
3453 eop_desc = E1000_TX_DESC(*tx_ring, eop);
3454 }
3455
3456 tx_ring->next_to_clean = i;
3457
581d708e 3458 spin_lock(&tx_ring->tx_lock);
1da177e4
LT		 3459
3460 if(unlikely(cleaned && netif_queue_stopped(netdev) &&
3461 netif_carrier_ok(netdev)))
3462 netif_wake_queue(netdev);
3463
581d708e 3464 spin_unlock(&tx_ring->tx_lock);
2648345f 3465
581d708e 3466 if (adapter->detect_tx_hung) {
2648345f 3467 /* Detect a transmit hang in hardware, this serializes the
1da177e4
LT		 3468 * check with the clearing of time_stamp and movement of i */
3469 adapter->detect_tx_hung = FALSE;
392137fa
JK		 3470 if (tx_ring->buffer_info[eop].dma &&
3471 time_after(jiffies, tx_ring->buffer_info[eop].time_stamp +
3472 adapter->tx_timeout_factor * HZ)
70b8f1e1 3473 && !(E1000_READ_REG(&adapter->hw, STATUS) &
392137fa 3474 E1000_STATUS_TXOFF)) {
70b8f1e1
MC		 3475
3476 /* detected Tx unit hang */
c6963ef5 3477 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
7bfa4816 3478 " Tx Queue <%lu>\n"
70b8f1e1
MC		 3479 " TDH <%x>\n"
3480 " TDT <%x>\n"
3481 " next_to_use <%x>\n"
3482 " next_to_clean <%x>\n"
3483 "buffer_info[next_to_clean]\n"
70b8f1e1
MC		 3484 " time_stamp <%lx>\n"
3485 " next_to_watch <%x>\n"
3486 " jiffies <%lx>\n"
3487 " next_to_watch.status <%x>\n",
7bfa4816
JK		 3488 (unsigned long)((tx_ring - adapter->tx_ring) /
3489 sizeof(struct e1000_tx_ring)),
581d708e
MC		 3490 readl(adapter->hw.hw_addr + tx_ring->tdh),
3491 readl(adapter->hw.hw_addr + tx_ring->tdt),
70b8f1e1 3492 tx_ring->next_to_use,
392137fa
JK		 3493 tx_ring->next_to_clean,
3494 tx_ring->buffer_info[eop].time_stamp,
70b8f1e1
MC		 3495 eop,
3496 jiffies,
3497 eop_desc->upper.fields.status);
1da177e4 3498 netif_stop_queue(netdev);
70b8f1e1 3499 }
1da177e4 3500 }
1da177e4
LT		 3501 return cleaned;
3502}
3503
3504/**
3505 * e1000_rx_checksum - Receive Checksum Offload for 82543
2d7edb92
MC		 3506 * @adapter: board private structure
3507 * @status_err: receive descriptor status and error fields
3508 * @csum: receive descriptor csum field
3509 * @sk_buff: socket buffer with received data
1da177e4
LT		 3510 **/
3511
3512static inline void
3513e1000_rx_checksum(struct e1000_adapter *adapter,
2d7edb92
MC		 3514 uint32_t status_err, uint32_t csum,
3515 struct sk_buff *skb)
1da177e4 3516{
2d7edb92
MC		 3517 uint16_t status = (uint16_t)status_err;
3518 uint8_t errors = (uint8_t)(status_err >> 24);
3519 skb->ip_summed = CHECKSUM_NONE;
3520
1da177e4 3521 /* 82543 or newer only */
2d7edb92 3522 if(unlikely(adapter->hw.mac_type < e1000_82543)) return;
1da177e4 3523 /* Ignore Checksum bit is set */
2d7edb92
MC		 3524 if(unlikely(status & E1000_RXD_STAT_IXSM)) return;
3525 /* TCP/UDP checksum error bit is set */
3526 if(unlikely(errors & E1000_RXD_ERR_TCPE)) {
1da177e4 3527 /* let the stack verify checksum errors */
1da177e4 3528 adapter->hw_csum_err++;
2d7edb92
MC		 3529 return;
3530 }
3531 /* TCP/UDP Checksum has not been calculated */
3532 if(adapter->hw.mac_type <= e1000_82547_rev_2) {
3533 if(!(status & E1000_RXD_STAT_TCPCS))
3534 return;
1da177e4 3535 } else {
2d7edb92
MC		 3536 if(!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
3537 return;
3538 }
3539 /* It must be a TCP or UDP packet with a valid checksum */
3540 if (likely(status & E1000_RXD_STAT_TCPCS)) {
1da177e4
LT		 3541 /* TCP checksum is good */
3542 skb->ip_summed = CHECKSUM_UNNECESSARY;
2d7edb92
MC		 3543 } else if (adapter->hw.mac_type > e1000_82547_rev_2) {
3544 /* IP fragment with UDP payload */
3545 /* Hardware complements the payload checksum, so we undo it
3546 * and then put the value in host order for further stack use.
3547 */
3548 csum = ntohl(csum ^ 0xFFFF);
3549 skb->csum = csum;
3550 skb->ip_summed = CHECKSUM_HW;
1da177e4 3551 }
2d7edb92 3552 adapter->hw_csum_good++;
1da177e4
LT		 3553}
3554
3555/**
2d7edb92 3556 * e1000_clean_rx_irq - Send received data up the network stack; legacy
1da177e4
LT		 3557 * @adapter: board private structure
3558 **/
3559
3560static boolean_t
3561#ifdef CONFIG_E1000_NAPI
581d708e
MC		 3562e1000_clean_rx_irq(struct e1000_adapter *adapter,
3563 struct e1000_rx_ring *rx_ring,
3564 int *work_done, int work_to_do)
1da177e4 3565#else
581d708e
MC		 3566e1000_clean_rx_irq(struct e1000_adapter *adapter,
3567 struct e1000_rx_ring *rx_ring)
1da177e4
LT		 3568#endif
3569{
1da177e4
LT		 3570 struct net_device *netdev = adapter->netdev;
3571 struct pci_dev *pdev = adapter->pdev;
3572 struct e1000_rx_desc *rx_desc;
3573 struct e1000_buffer *buffer_info;
3574 struct sk_buff *skb;
3575 unsigned long flags;
3576 uint32_t length;
3577 uint8_t last_byte;
3578 unsigned int i;
72d64a43 3579 int cleaned_count = 0;
a292ca6e 3580 boolean_t cleaned = FALSE, multi_descriptor = FALSE;
1da177e4
LT		 3581
3582 i = rx_ring->next_to_clean;
3583 rx_desc = E1000_RX_DESC(*rx_ring, i);
3584
3585 while(rx_desc->status & E1000_RXD_STAT_DD) {
3586 buffer_info = &rx_ring->buffer_info[i];
a292ca6e 3587 u8 status;
1da177e4
LT		 3588#ifdef CONFIG_E1000_NAPI
3589 if(*work_done >= work_to_do)
3590 break;
3591 (*work_done)++;
3592#endif
a292ca6e 3593 status = rx_desc->status;
72d64a43
JK		 3594 cleaned = TRUE;
3595 cleaned_count++;
a292ca6e
JK		 3596 pci_unmap_single(pdev,
3597 buffer_info->dma,
3598 buffer_info->length,
1da177e4
LT		 3599 PCI_DMA_FROMDEVICE);
3600
3601 skb = buffer_info->skb;
3602 length = le16_to_cpu(rx_desc->length);
3603
3604 if(unlikely(!(rx_desc->status & E1000_RXD_STAT_EOP))) {
3605 /* All receives must fit into a single buffer */
3606 E1000_DBG("%s: Receive packet consumed multiple"
2648345f 3607 " buffers\n", netdev->name);
1da177e4
LT		 3608 dev_kfree_skb_irq(skb);
3609 goto next_desc;
3610 }
3611
3612 if(unlikely(rx_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK)) {
3613 last_byte = *(skb->data + length - 1);
3614 if(TBI_ACCEPT(&adapter->hw, rx_desc->status,
3615 rx_desc->errors, length, last_byte)) {
3616 spin_lock_irqsave(&adapter->stats_lock, flags);
a292ca6e
JK		 3617 e1000_tbi_adjust_stats(&adapter->hw,
3618 &adapter->stats,
1da177e4
LT		 3619 length, skb->data);
3620 spin_unlock_irqrestore(&adapter->stats_lock,
3621 flags);
3622 length--;
3623 } else {
3624 dev_kfree_skb_irq(skb);
3625 goto next_desc;
3626 }
3627 }
3628
a292ca6e
JK		 3629 /* code added for copybreak, this should improve
3630 * performance for small packets with large amounts
3631 * of reassembly being done in the stack */
3632#define E1000_CB_LENGTH 256
3633 if ((length < E1000_CB_LENGTH) &&
3634 !rx_ring->rx_skb_top &&
3635 /* or maybe (status & E1000_RXD_STAT_EOP) && */
3636 !multi_descriptor) {
3637 struct sk_buff *new_skb =
3638 dev_alloc_skb(length + NET_IP_ALIGN);
3639 if (new_skb) {
3640 skb_reserve(new_skb, NET_IP_ALIGN);
3641 new_skb->dev = netdev;
3642 memcpy(new_skb->data - NET_IP_ALIGN,
3643 skb->data - NET_IP_ALIGN,
3644 length + NET_IP_ALIGN);
3645 /* save the skb in buffer_info as good */
3646 buffer_info->skb = skb;
3647 skb = new_skb;
3648 skb_put(skb, length);
3649 }
3650 }
3651
3652 /* end copybreak code */
1da177e4
LT		 3653
3654 /* Receive Checksum Offload */
a292ca6e
JK		 3655 e1000_rx_checksum(adapter,
3656 (uint32_t)(status) |
2d7edb92
MC		 3657 ((uint32_t)(rx_desc->errors) << 24),
3658 rx_desc->csum, skb);
1da177e4
LT		 3659 skb->protocol = eth_type_trans(skb, netdev);
3660#ifdef CONFIG_E1000_NAPI
3661 if(unlikely(adapter->vlgrp &&
a292ca6e 3662 (status & E1000_RXD_STAT_VP))) {
1da177e4 3663 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
2d7edb92
MC		 3664 le16_to_cpu(rx_desc->special) &
3665 E1000_RXD_SPC_VLAN_MASK);
1da177e4
LT		 3666 } else {
3667 netif_receive_skb(skb);
3668 }
3669#else /* CONFIG_E1000_NAPI */
3670 if(unlikely(adapter->vlgrp &&
3671 (rx_desc->status & E1000_RXD_STAT_VP))) {
3672 vlan_hwaccel_rx(skb, adapter->vlgrp,
3673 le16_to_cpu(rx_desc->special) &
3674 E1000_RXD_SPC_VLAN_MASK);
3675 } else {
3676 netif_rx(skb);
3677 }
3678#endif /* CONFIG_E1000_NAPI */
3679 netdev->last_rx = jiffies;
7bfa4816
JK		 3680#ifdef CONFIG_E1000_MQ
3681 rx_ring->rx_stats.packets++;
3682 rx_ring->rx_stats.bytes += length;
3683#endif
1da177e4
LT		 3684
3685next_desc:
3686 rx_desc->status = 0;
1da177e4 3687
72d64a43
JK		 3688 /* return some buffers to hardware, one at a time is too slow */
3689 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
3690 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
3691 cleaned_count = 0;
3692 }
3693
1da177e4 3694 }
1da177e4 3695 rx_ring->next_to_clean = i;
72d64a43
JK		 3696
3697 cleaned_count = E1000_DESC_UNUSED(rx_ring);
3698 if (cleaned_count)
3699 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
2d7edb92
MC		 3700
3701 return cleaned;
3702}
3703
3704/**
3705 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
3706 * @adapter: board private structure
3707 **/
3708
3709static boolean_t
3710#ifdef CONFIG_E1000_NAPI
581d708e
MC		 3711e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3712 struct e1000_rx_ring *rx_ring,
3713 int *work_done, int work_to_do)
2d7edb92 3714#else
581d708e
MC		 3715e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3716 struct e1000_rx_ring *rx_ring)
2d7edb92
MC		 3717#endif
3718{
2d7edb92
MC		 3719 union e1000_rx_desc_packet_split *rx_desc;
3720 struct net_device *netdev = adapter->netdev;
3721 struct pci_dev *pdev = adapter->pdev;
3722 struct e1000_buffer *buffer_info;
3723 struct e1000_ps_page *ps_page;
3724 struct e1000_ps_page_dma *ps_page_dma;
3725 struct sk_buff *skb;
3726 unsigned int i, j;
3727 uint32_t length, staterr;
72d64a43 3728 int cleaned_count = 0;
2d7edb92
MC		 3729 boolean_t cleaned = FALSE;
3730
3731 i = rx_ring->next_to_clean;
3732 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
683a38f3 3733 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
2d7edb92
MC		 3734
3735 while(staterr & E1000_RXD_STAT_DD) {
3736 buffer_info = &rx_ring->buffer_info[i];
3737 ps_page = &rx_ring->ps_page[i];
3738 ps_page_dma = &rx_ring->ps_page_dma[i];
3739#ifdef CONFIG_E1000_NAPI
3740 if(unlikely(*work_done >= work_to_do))
3741 break;
3742 (*work_done)++;
3743#endif
3744 cleaned = TRUE;
72d64a43 3745 cleaned_count++;
2d7edb92
MC		 3746 pci_unmap_single(pdev, buffer_info->dma,
3747 buffer_info->length,
3748 PCI_DMA_FROMDEVICE);
3749
3750 skb = buffer_info->skb;
3751
3752 if(unlikely(!(staterr & E1000_RXD_STAT_EOP))) {
3753 E1000_DBG("%s: Packet Split buffers didn't pick up"
3754 " the full packet\n", netdev->name);
3755 dev_kfree_skb_irq(skb);
3756 goto next_desc;
3757 }
1da177e4 3758
2d7edb92
MC		 3759 if(unlikely(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
3760 dev_kfree_skb_irq(skb);
3761 goto next_desc;
3762 }
3763
3764 length = le16_to_cpu(rx_desc->wb.middle.length0);
3765
3766 if(unlikely(!length)) {
3767 E1000_DBG("%s: Last part of the packet spanning"
3768 " multiple descriptors\n", netdev->name);
3769 dev_kfree_skb_irq(skb);
3770 goto next_desc;
3771 }
3772
3773 /* Good Receive */
3774 skb_put(skb, length);
3775
e4c811c9 3776 for(j = 0; j < adapter->rx_ps_pages; j++) {
2d7edb92
MC		 3777 if(!(length = le16_to_cpu(rx_desc->wb.upper.length[j])))
3778 break;
3779
3780 pci_unmap_page(pdev, ps_page_dma->ps_page_dma[j],
3781 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3782 ps_page_dma->ps_page_dma[j] = 0;
3783 skb_shinfo(skb)->frags[j].page =
3784 ps_page->ps_page[j];
3785 ps_page->ps_page[j] = NULL;
3786 skb_shinfo(skb)->frags[j].page_offset = 0;
3787 skb_shinfo(skb)->frags[j].size = length;
3788 skb_shinfo(skb)->nr_frags++;
3789 skb->len += length;
3790 skb->data_len += length;
3791 }
3792
3793 e1000_rx_checksum(adapter, staterr,
3794 rx_desc->wb.lower.hi_dword.csum_ip.csum, skb);
3795 skb->protocol = eth_type_trans(skb, netdev);
3796
2d7edb92 3797 if(likely(rx_desc->wb.upper.header_status &
e4c811c9
MC		 3798 E1000_RXDPS_HDRSTAT_HDRSP)) {
3799 adapter->rx_hdr_split++;
3800#ifdef HAVE_RX_ZERO_COPY
2d7edb92
MC		 3801 skb_shinfo(skb)->zero_copy = TRUE;
3802#endif
e4c811c9 3803 }
2d7edb92
MC		 3804#ifdef CONFIG_E1000_NAPI
3805 if(unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
3806 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
683a38f3
MC		 3807 le16_to_cpu(rx_desc->wb.middle.vlan) &
3808 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 3809 } else {
3810 netif_receive_skb(skb);
3811 }
3812#else /* CONFIG_E1000_NAPI */
3813 if(unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
3814 vlan_hwaccel_rx(skb, adapter->vlgrp,
683a38f3
MC		 3815 le16_to_cpu(rx_desc->wb.middle.vlan) &
3816 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 3817 } else {
3818 netif_rx(skb);
3819 }
3820#endif /* CONFIG_E1000_NAPI */
3821 netdev->last_rx = jiffies;
7bfa4816
JK		 3822#ifdef CONFIG_E1000_MQ
3823 rx_ring->rx_stats.packets++;
3824 rx_ring->rx_stats.bytes += length;
3825#endif
2d7edb92
MC		 3826
3827next_desc:
3828 rx_desc->wb.middle.status_error &= ~0xFF;
3829 buffer_info->skb = NULL;
2d7edb92 3830
72d64a43
JK		 3831 /* return some buffers to hardware, one at a time is too slow */
3832 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
3833 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
3834 cleaned_count = 0;
3835 }
3836
683a38f3 3837 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
2d7edb92
MC		 3838 }
3839 rx_ring->next_to_clean = i;
72d64a43
JK		 3840
3841 cleaned_count = E1000_DESC_UNUSED(rx_ring);
3842 if (cleaned_count)
3843 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
1da177e4
LT		 3844
3845 return cleaned;
3846}
3847
3848/**
2d7edb92 3849 * e1000_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1da177e4
LT		 3850 * @adapter: address of board private structure
3851 **/
3852
3853static void
581d708e 3854e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
72d64a43 3855 struct e1000_rx_ring *rx_ring,
a292ca6e 3856 int cleaned_count)
1da177e4 3857{
1da177e4
LT		 3858 struct net_device *netdev = adapter->netdev;
3859 struct pci_dev *pdev = adapter->pdev;
3860 struct e1000_rx_desc *rx_desc;
3861 struct e1000_buffer *buffer_info;
3862 struct sk_buff *skb;
2648345f
MC		 3863 unsigned int i;
3864 unsigned int bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
1da177e4
LT		 3865
3866 i = rx_ring->next_to_use;
3867 buffer_info = &rx_ring->buffer_info[i];
3868
a292ca6e
JK		 3869 while (cleaned_count--) {
3870 if (!(skb = buffer_info->skb))
3871 skb = dev_alloc_skb(bufsz);
3872 else {
3873 skb_trim(skb, 0);
3874 goto map_skb;
3875 }
3876
2648345f 3877
1da177e4
LT		 3878 if(unlikely(!skb)) {
3879 /* Better luck next round */
72d64a43 3880 adapter->alloc_rx_buff_failed++;
1da177e4
LT		 3881 break;
3882 }
3883
2648345f 3884 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 3885 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
3886 struct sk_buff *oldskb = skb;
2648345f
MC		 3887 DPRINTK(RX_ERR, ERR, "skb align check failed: %u bytes "
3888 "at %p\n", bufsz, skb->data);
3889 /* Try again, without freeing the previous */
1da177e4 3890 skb = dev_alloc_skb(bufsz);
2648345f 3891 /* Failed allocation, critical failure */
1da177e4
LT		 3892 if (!skb) {
3893 dev_kfree_skb(oldskb);
3894 break;
3895 }
2648345f 3896
1da177e4
LT		 3897 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
3898 /* give up */
3899 dev_kfree_skb(skb);
3900 dev_kfree_skb(oldskb);
3901 break; /* while !buffer_info->skb */
3902 } else {
2648345f 3903 /* Use new allocation */
1da177e4
LT		 3904 dev_kfree_skb(oldskb);
3905 }
3906 }
1da177e4
LT		 3907 /* Make buffer alignment 2 beyond a 16 byte boundary
3908 * this will result in a 16 byte aligned IP header after
3909 * the 14 byte MAC header is removed
3910 */
3911 skb_reserve(skb, NET_IP_ALIGN);
3912
3913 skb->dev = netdev;
3914
3915 buffer_info->skb = skb;
3916 buffer_info->length = adapter->rx_buffer_len;
a292ca6e 3917map_skb:
1da177e4
LT		 3918 buffer_info->dma = pci_map_single(pdev,
3919 skb->data,
3920 adapter->rx_buffer_len,
3921 PCI_DMA_FROMDEVICE);
3922
2648345f
MC		 3923 /* Fix for errata 23, can't cross 64kB boundary */
3924 if (!e1000_check_64k_bound(adapter,
3925 (void *)(unsigned long)buffer_info->dma,
3926 adapter->rx_buffer_len)) {
3927 DPRINTK(RX_ERR, ERR,
3928 "dma align check failed: %u bytes at %p\n",
3929 adapter->rx_buffer_len,
3930 (void *)(unsigned long)buffer_info->dma);
1da177e4
LT		 3931 dev_kfree_skb(skb);
3932 buffer_info->skb = NULL;
3933
2648345f 3934 pci_unmap_single(pdev, buffer_info->dma,
1da177e4
LT		 3935 adapter->rx_buffer_len,
3936 PCI_DMA_FROMDEVICE);
3937
3938 break; /* while !buffer_info->skb */
3939 }
1da177e4
LT		 3940 rx_desc = E1000_RX_DESC(*rx_ring, i);
3941 rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
3942
3943 if(unlikely((i & ~(E1000_RX_BUFFER_WRITE - 1)) == i)) {
3944 /* Force memory writes to complete before letting h/w
3945 * know there are new descriptors to fetch. (Only
3946 * applicable for weak-ordered memory model archs,
3947 * such as IA-64). */
3948 wmb();
581d708e 3949 writel(i, adapter->hw.hw_addr + rx_ring->rdt);
1da177e4
LT		 3950 }
3951
3952 if(unlikely(++i == rx_ring->count)) i = 0;
3953 buffer_info = &rx_ring->buffer_info[i];
3954 }
3955
3956 rx_ring->next_to_use = i;
3957}
3958
2d7edb92
MC		 3959/**
3960 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
3961 * @adapter: address of board private structure
3962 **/
3963
3964static void
581d708e 3965e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
72d64a43
JK		 3966 struct e1000_rx_ring *rx_ring,
3967 int cleaned_count)
2d7edb92 3968{
2d7edb92
MC		 3969 struct net_device *netdev = adapter->netdev;
3970 struct pci_dev *pdev = adapter->pdev;
3971 union e1000_rx_desc_packet_split *rx_desc;
3972 struct e1000_buffer *buffer_info;
3973 struct e1000_ps_page *ps_page;
3974 struct e1000_ps_page_dma *ps_page_dma;
3975 struct sk_buff *skb;
3976 unsigned int i, j;
3977
3978 i = rx_ring->next_to_use;
3979 buffer_info = &rx_ring->buffer_info[i];
3980 ps_page = &rx_ring->ps_page[i];
3981 ps_page_dma = &rx_ring->ps_page_dma[i];
3982
72d64a43 3983 while (cleaned_count--) {
2d7edb92
MC		 3984 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
3985
3986 for(j = 0; j < PS_PAGE_BUFFERS; j++) {
e4c811c9
MC		 3987 if (j < adapter->rx_ps_pages) {
3988 if (likely(!ps_page->ps_page[j])) {
3989 ps_page->ps_page[j] =
3990 alloc_page(GFP_ATOMIC);
3991 if (unlikely(!ps_page->ps_page[j]))
3992 goto no_buffers;
3993 ps_page_dma->ps_page_dma[j] =
3994 pci_map_page(pdev,
3995 ps_page->ps_page[j],
3996 0, PAGE_SIZE,
3997 PCI_DMA_FROMDEVICE);
3998 }
3999 /* Refresh the desc even if buffer_addrs didn't
4000 * change because each write-back erases
4001 * this info.
4002 */
4003 rx_desc->read.buffer_addr[j+1] =
4004 cpu_to_le64(ps_page_dma->ps_page_dma[j]);
4005 } else
4006 rx_desc->read.buffer_addr[j+1] = ~0;
2d7edb92
MC		 4007 }
4008
4009 skb = dev_alloc_skb(adapter->rx_ps_bsize0 + NET_IP_ALIGN);
4010
4011 if(unlikely(!skb))
4012 break;
4013
4014 /* Make buffer alignment 2 beyond a 16 byte boundary
4015 * this will result in a 16 byte aligned IP header after
4016 * the 14 byte MAC header is removed
4017 */
4018 skb_reserve(skb, NET_IP_ALIGN);
4019
4020 skb->dev = netdev;
4021
4022 buffer_info->skb = skb;
4023 buffer_info->length = adapter->rx_ps_bsize0;
4024 buffer_info->dma = pci_map_single(pdev, skb->data,
4025 adapter->rx_ps_bsize0,
4026 PCI_DMA_FROMDEVICE);
4027
4028 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
4029
4030 if(unlikely((i & ~(E1000_RX_BUFFER_WRITE - 1)) == i)) {
4031 /* Force memory writes to complete before letting h/w
4032 * know there are new descriptors to fetch. (Only
4033 * applicable for weak-ordered memory model archs,
4034 * such as IA-64). */
4035 wmb();
4036 /* Hardware increments by 16 bytes, but packet split
4037 * descriptors are 32 bytes...so we increment tail
4038 * twice as much.
4039 */
581d708e 4040 writel(i<<1, adapter->hw.hw_addr + rx_ring->rdt);
2d7edb92
MC		 4041 }
4042
4043 if(unlikely(++i == rx_ring->count)) i = 0;
4044 buffer_info = &rx_ring->buffer_info[i];
4045 ps_page = &rx_ring->ps_page[i];
4046 ps_page_dma = &rx_ring->ps_page_dma[i];
4047 }
4048
4049no_buffers:
4050 rx_ring->next_to_use = i;
4051}
4052
1da177e4
LT		 4053/**
4054 * e1000_smartspeed - Workaround for SmartSpeed on 82541 and 82547 controllers.
4055 * @adapter:
4056 **/
4057
4058static void
4059e1000_smartspeed(struct e1000_adapter *adapter)
4060{
4061 uint16_t phy_status;
4062 uint16_t phy_ctrl;
4063
4064 if((adapter->hw.phy_type != e1000_phy_igp) || !adapter->hw.autoneg ||
4065 !(adapter->hw.autoneg_advertised & ADVERTISE_1000_FULL))
4066 return;
4067
4068 if(adapter->smartspeed == 0) {
4069 /* If Master/Slave config fault is asserted twice,
4070 * we assume back-to-back */
4071 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
4072 if(!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
4073 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
4074 if(!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
4075 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
4076 if(phy_ctrl & CR_1000T_MS_ENABLE) {
4077 phy_ctrl &= ~CR_1000T_MS_ENABLE;
4078 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL,
4079 phy_ctrl);
4080 adapter->smartspeed++;
4081 if(!e1000_phy_setup_autoneg(&adapter->hw) &&
4082 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL,
4083 &phy_ctrl)) {
4084 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
4085 MII_CR_RESTART_AUTO_NEG);
4086 e1000_write_phy_reg(&adapter->hw, PHY_CTRL,
4087 phy_ctrl);
4088 }
4089 }
4090 return;
4091 } else if(adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) {
4092 /* If still no link, perhaps using 2/3 pair cable */
4093 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
4094 phy_ctrl |= CR_1000T_MS_ENABLE;
4095 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_ctrl);
4096 if(!e1000_phy_setup_autoneg(&adapter->hw) &&
4097 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_ctrl)) {
4098 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
4099 MII_CR_RESTART_AUTO_NEG);
4100 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, phy_ctrl);
4101 }
4102 }
4103 /* Restart process after E1000_SMARTSPEED_MAX iterations */
4104 if(adapter->smartspeed++ == E1000_SMARTSPEED_MAX)
4105 adapter->smartspeed = 0;
4106}
4107
4108/**
4109 * e1000_ioctl -
4110 * @netdev:
4111 * @ifreq:
4112 * @cmd:
4113 **/
4114
4115static int
4116e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4117{
4118 switch (cmd) {
4119 case SIOCGMIIPHY:
4120 case SIOCGMIIREG:
4121 case SIOCSMIIREG:
4122 return e1000_mii_ioctl(netdev, ifr, cmd);
4123 default:
4124 return -EOPNOTSUPP;
4125 }
4126}
4127
4128/**
4129 * e1000_mii_ioctl -
4130 * @netdev:
4131 * @ifreq:
4132 * @cmd:
4133 **/
4134
4135static int
4136e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4137{
60490fe0 4138 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4139 struct mii_ioctl_data *data = if_mii(ifr);
4140 int retval;
4141 uint16_t mii_reg;
4142 uint16_t spddplx;
97876fc6 4143 unsigned long flags;
1da177e4
LT		 4144
4145 if(adapter->hw.media_type != e1000_media_type_copper)
4146 return -EOPNOTSUPP;
4147
4148 switch (cmd) {
4149 case SIOCGMIIPHY:
4150 data->phy_id = adapter->hw.phy_addr;
4151 break;
4152 case SIOCGMIIREG:
97876fc6 4153 if(!capable(CAP_NET_ADMIN))
1da177e4 4154 return -EPERM;
97876fc6
MC		 4155 spin_lock_irqsave(&adapter->stats_lock, flags);
4156 if(e1000_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4157 &data->val_out)) {
4158 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 4159 return -EIO;
97876fc6
MC		 4160 }
4161 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 4162 break;
4163 case SIOCSMIIREG:
97876fc6 4164 if(!capable(CAP_NET_ADMIN))
1da177e4 4165 return -EPERM;
97876fc6 4166 if(data->reg_num & ~(0x1F))
1da177e4
LT		 4167 return -EFAULT;
4168 mii_reg = data->val_in;
97876fc6
MC		 4169 spin_lock_irqsave(&adapter->stats_lock, flags);
4170 if(e1000_write_phy_reg(&adapter->hw, data->reg_num,
4171 mii_reg)) {
4172 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 4173 return -EIO;
97876fc6
MC		 4174 }
4175 if(adapter->hw.phy_type == e1000_phy_m88) {
1da177e4
LT		 4176 switch (data->reg_num) {
4177 case PHY_CTRL:
4178 if(mii_reg & MII_CR_POWER_DOWN)
4179 break;
4180 if(mii_reg & MII_CR_AUTO_NEG_EN) {
4181 adapter->hw.autoneg = 1;
4182 adapter->hw.autoneg_advertised = 0x2F;
4183 } else {
4184 if (mii_reg & 0x40)
4185 spddplx = SPEED_1000;
4186 else if (mii_reg & 0x2000)
4187 spddplx = SPEED_100;
4188 else
4189 spddplx = SPEED_10;
4190 spddplx += (mii_reg & 0x100)
4191 ? FULL_DUPLEX :
4192 HALF_DUPLEX;
4193 retval = e1000_set_spd_dplx(adapter,
4194 spddplx);
97876fc6
MC		 4195 if(retval) {
4196 spin_unlock_irqrestore(
4197 &adapter->stats_lock,
4198 flags);
1da177e4 4199 return retval;
97876fc6 4200 }
1da177e4
LT		 4201 }
4202 if(netif_running(adapter->netdev)) {
4203 e1000_down(adapter);
4204 e1000_up(adapter);
4205 } else
4206 e1000_reset(adapter);
4207 break;
4208 case M88E1000_PHY_SPEC_CTRL:
4209 case M88E1000_EXT_PHY_SPEC_CTRL:
97876fc6
MC		 4210 if(e1000_phy_reset(&adapter->hw)) {
4211 spin_unlock_irqrestore(
4212 &adapter->stats_lock, flags);
1da177e4 4213 return -EIO;
97876fc6 4214 }
1da177e4
LT		 4215 break;
4216 }
4217 } else {
4218 switch (data->reg_num) {
4219 case PHY_CTRL:
4220 if(mii_reg & MII_CR_POWER_DOWN)
4221 break;
4222 if(netif_running(adapter->netdev)) {
4223 e1000_down(adapter);
4224 e1000_up(adapter);
4225 } else
4226 e1000_reset(adapter);
4227 break;
4228 }
4229 }
97876fc6 4230 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 4231 break;
4232 default:
4233 return -EOPNOTSUPP;
4234 }
4235 return E1000_SUCCESS;
4236}
4237
4238void
4239e1000_pci_set_mwi(struct e1000_hw *hw)
4240{
4241 struct e1000_adapter *adapter = hw->back;
2648345f 4242 int ret_val = pci_set_mwi(adapter->pdev);
1da177e4 4243
2648345f
MC		 4244 if(ret_val)
4245 DPRINTK(PROBE, ERR, "Error in setting MWI\n");
1da177e4
LT		 4246}
4247
4248void
4249e1000_pci_clear_mwi(struct e1000_hw *hw)
4250{
4251 struct e1000_adapter *adapter = hw->back;
4252
4253 pci_clear_mwi(adapter->pdev);
4254}
4255
4256void
4257e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4258{
4259 struct e1000_adapter *adapter = hw->back;
4260
4261 pci_read_config_word(adapter->pdev, reg, value);
4262}
4263
4264void
4265e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4266{
4267 struct e1000_adapter *adapter = hw->back;
4268
4269 pci_write_config_word(adapter->pdev, reg, *value);
4270}
4271
4272uint32_t
4273e1000_io_read(struct e1000_hw *hw, unsigned long port)
4274{
4275 return inl(port);
4276}
4277
4278void
4279e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value)
4280{
4281 outl(value, port);
4282}
4283
4284static void
4285e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
4286{
60490fe0 4287 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4288 uint32_t ctrl, rctl;
4289
4290 e1000_irq_disable(adapter);
4291 adapter->vlgrp = grp;
4292
4293 if(grp) {
4294 /* enable VLAN tag insert/strip */
4295 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4296 ctrl |= E1000_CTRL_VME;
4297 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4298
4299 /* enable VLAN receive filtering */
4300 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4301 rctl |= E1000_RCTL_VFE;
4302 rctl &= ~E1000_RCTL_CFIEN;
4303 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2d7edb92 4304 e1000_update_mng_vlan(adapter);
1da177e4
LT		 4305 } else {
4306 /* disable VLAN tag insert/strip */
4307 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4308 ctrl &= ~E1000_CTRL_VME;
4309 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4310
4311 /* disable VLAN filtering */
4312 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4313 rctl &= ~E1000_RCTL_VFE;
4314 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2d7edb92
MC		 4315 if(adapter->mng_vlan_id != (uint16_t)E1000_MNG_VLAN_NONE) {
4316 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4317 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4318 }
1da177e4
LT		 4319 }
4320
4321 e1000_irq_enable(adapter);
4322}
4323
4324static void
4325e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid)
4326{
60490fe0 4327 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 4328 uint32_t vfta, index;
2d7edb92
MC		 4329 if((adapter->hw.mng_cookie.status &
4330 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
4331 (vid == adapter->mng_vlan_id))
4332 return;
1da177e4
LT		 4333 /* add VID to filter table */
4334 index = (vid >> 5) & 0x7F;
4335 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
4336 vfta |= (1 << (vid & 0x1F));
4337 e1000_write_vfta(&adapter->hw, index, vfta);
4338}
4339
4340static void
4341e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid)
4342{
60490fe0 4343 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4344 uint32_t vfta, index;
4345
4346 e1000_irq_disable(adapter);
4347
4348 if(adapter->vlgrp)
4349 adapter->vlgrp->vlan_devices[vid] = NULL;
4350
4351 e1000_irq_enable(adapter);
4352
2d7edb92
MC		 4353 if((adapter->hw.mng_cookie.status &
4354 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
ff147013
JK		 4355 (vid == adapter->mng_vlan_id)) {
4356 /* release control to f/w */
4357 e1000_release_hw_control(adapter);
2d7edb92 4358 return;
ff147013
JK		 4359 }
4360
1da177e4
LT		 4361 /* remove VID from filter table */
4362 index = (vid >> 5) & 0x7F;
4363 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
4364 vfta &= ~(1 << (vid & 0x1F));
4365 e1000_write_vfta(&adapter->hw, index, vfta);
4366}
4367
4368static void
4369e1000_restore_vlan(struct e1000_adapter *adapter)
4370{
4371 e1000_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4372
4373 if(adapter->vlgrp) {
4374 uint16_t vid;
4375 for(vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4376 if(!adapter->vlgrp->vlan_devices[vid])
4377 continue;
4378 e1000_vlan_rx_add_vid(adapter->netdev, vid);
4379 }
4380 }
4381}
4382
4383int
4384e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx)
4385{
4386 adapter->hw.autoneg = 0;
4387
6921368f
MC		 4388 /* Fiber NICs only allow 1000 gbps Full duplex */
4389 if((adapter->hw.media_type == e1000_media_type_fiber) &&
4390 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4391 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
4392 return -EINVAL;
4393 }
4394
1da177e4
LT		 4395 switch(spddplx) {
4396 case SPEED_10 + DUPLEX_HALF:
4397 adapter->hw.forced_speed_duplex = e1000_10_half;
4398 break;
4399 case SPEED_10 + DUPLEX_FULL:
4400 adapter->hw.forced_speed_duplex = e1000_10_full;
4401 break;
4402 case SPEED_100 + DUPLEX_HALF:
4403 adapter->hw.forced_speed_duplex = e1000_100_half;
4404 break;
4405 case SPEED_100 + DUPLEX_FULL:
4406 adapter->hw.forced_speed_duplex = e1000_100_full;
4407 break;
4408 case SPEED_1000 + DUPLEX_FULL:
4409 adapter->hw.autoneg = 1;
4410 adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL;
4411 break;
4412 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4413 default:
2648345f 4414 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
1da177e4
LT		 4415 return -EINVAL;
4416 }
4417 return 0;
4418}
4419
b6a1d5f8 4420#ifdef CONFIG_PM
1da177e4 4421static int
829ca9a3 4422e1000_suspend(struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 4423{
4424 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 4425 struct e1000_adapter *adapter = netdev_priv(netdev);
b55ccb35 4426 uint32_t ctrl, ctrl_ext, rctl, manc, status;
1da177e4 4427 uint32_t wufc = adapter->wol;
240b1710 4428 int retval = 0;
1da177e4
LT		 4429
4430 netif_device_detach(netdev);
4431
4432 if(netif_running(netdev))
4433 e1000_down(adapter);
4434
4435 status = E1000_READ_REG(&adapter->hw, STATUS);
4436 if(status & E1000_STATUS_LU)
4437 wufc &= ~E1000_WUFC_LNKC;
4438
4439 if(wufc) {
4440 e1000_setup_rctl(adapter);
4441 e1000_set_multi(netdev);
4442
4443 /* turn on all-multi mode if wake on multicast is enabled */
4444 if(adapter->wol & E1000_WUFC_MC) {
4445 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4446 rctl |= E1000_RCTL_MPE;
4447 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
4448 }
4449
4450 if(adapter->hw.mac_type >= e1000_82540) {
4451 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4452 /* advertise wake from D3Cold */
4453 #define E1000_CTRL_ADVD3WUC 0x00100000
4454 /* phy power management enable */
4455 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4456 ctrl |= E1000_CTRL_ADVD3WUC |
4457 E1000_CTRL_EN_PHY_PWR_MGMT;
4458 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4459 }
4460
4461 if(adapter->hw.media_type == e1000_media_type_fiber ||
4462 adapter->hw.media_type == e1000_media_type_internal_serdes) {
4463 /* keep the laser running in D3 */
4464 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
4465 ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
4466 E1000_WRITE_REG(&adapter->hw, CTRL_EXT, ctrl_ext);
4467 }
4468
2d7edb92
MC		 4469 /* Allow time for pending master requests to run */
4470 e1000_disable_pciex_master(&adapter->hw);
4471
1da177e4
LT		 4472 E1000_WRITE_REG(&adapter->hw, WUC, E1000_WUC_PME_EN);
4473 E1000_WRITE_REG(&adapter->hw, WUFC, wufc);
240b1710
JK		 4474 retval = pci_enable_wake(pdev, PCI_D3hot, 1);
4475 if (retval)
4476 DPRINTK(PROBE, ERR, "Error enabling D3 wake\n");
4477 retval = pci_enable_wake(pdev, PCI_D3cold, 1);
4478 if (retval)
4479 DPRINTK(PROBE, ERR, "Error enabling D3 cold wake\n");
1da177e4
LT		 4480 } else {
4481 E1000_WRITE_REG(&adapter->hw, WUC, 0);
4482 E1000_WRITE_REG(&adapter->hw, WUFC, 0);
240b1710
JK		 4483 retval = pci_enable_wake(pdev, PCI_D3hot, 0);
4484 if (retval)
4485 DPRINTK(PROBE, ERR, "Error enabling D3 wake\n");
4486 retval = pci_enable_wake(pdev, PCI_D3cold, 0); /* 4 == D3 cold */
4487 if (retval)
4488 DPRINTK(PROBE, ERR, "Error enabling D3 cold wake\n");
1da177e4
LT		 4489 }
4490
4491 pci_save_state(pdev);
4492
4493 if(adapter->hw.mac_type >= e1000_82540 &&
4494 adapter->hw.media_type == e1000_media_type_copper) {
4495 manc = E1000_READ_REG(&adapter->hw, MANC);
4496 if(manc & E1000_MANC_SMBUS_EN) {
4497 manc |= E1000_MANC_ARP_EN;
4498 E1000_WRITE_REG(&adapter->hw, MANC, manc);
240b1710
JK		 4499 retval = pci_enable_wake(pdev, PCI_D3hot, 1);
4500 if (retval)
4501 DPRINTK(PROBE, ERR, "Error enabling D3 wake\n");
4502 retval = pci_enable_wake(pdev, PCI_D3cold, 1);
4503 if (retval)
4504 DPRINTK(PROBE, ERR, "Error enabling D3 cold wake\n");
1da177e4
LT		 4505 }
4506 }
4507
b55ccb35
JK		 4508 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4509 * would have already happened in close and is redundant. */
4510 e1000_release_hw_control(adapter);
2d7edb92 4511
1da177e4 4512 pci_disable_device(pdev);
240b1710
JK		 4513
4514 retval = pci_set_power_state(pdev, pci_choose_state(pdev, state));
4515 if (retval)
4516 DPRINTK(PROBE, ERR, "Error in setting power state\n");
1da177e4
LT		 4517
4518 return 0;
4519}
4520
1da177e4
LT		 4521static int
4522e1000_resume(struct pci_dev *pdev)
4523{
4524 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 4525 struct e1000_adapter *adapter = netdev_priv(netdev);
240b1710 4526 int retval;
b55ccb35 4527 uint32_t manc, ret_val;
1da177e4 4528
240b1710
JK		 4529 retval = pci_set_power_state(pdev, PCI_D0);
4530 if (retval)
4531 DPRINTK(PROBE, ERR, "Error in setting power state\n");
2b02893e 4532 ret_val = pci_enable_device(pdev);
a4cb847d 4533 pci_set_master(pdev);
1da177e4 4534
240b1710
JK		 4535 retval = pci_enable_wake(pdev, PCI_D3hot, 0);
4536 if (retval)
4537 DPRINTK(PROBE, ERR, "Error enabling D3 wake\n");
4538 retval = pci_enable_wake(pdev, PCI_D3cold, 0);
4539 if (retval)
4540 DPRINTK(PROBE, ERR, "Error enabling D3 cold wake\n");
1da177e4
LT		 4541
4542 e1000_reset(adapter);
4543 E1000_WRITE_REG(&adapter->hw, WUS, ~0);
4544
4545 if(netif_running(netdev))
4546 e1000_up(adapter);
4547
4548 netif_device_attach(netdev);
4549
4550 if(adapter->hw.mac_type >= e1000_82540 &&
4551 adapter->hw.media_type == e1000_media_type_copper) {
4552 manc = E1000_READ_REG(&adapter->hw, MANC);
4553 manc &= ~(E1000_MANC_ARP_EN);
4554 E1000_WRITE_REG(&adapter->hw, MANC, manc);
4555 }
4556
b55ccb35
JK		 4557 /* If the controller is 82573 and f/w is AMT, do not set
4558 * DRV_LOAD until the interface is up. For all other cases,
4559 * let the f/w know that the h/w is now under the control
4560 * of the driver. */
4561 if (adapter->hw.mac_type != e1000_82573 ||
4562 !e1000_check_mng_mode(&adapter->hw))
4563 e1000_get_hw_control(adapter);
2d7edb92 4564
1da177e4
LT		 4565 return 0;
4566}
4567#endif
1da177e4
LT		 4568#ifdef CONFIG_NET_POLL_CONTROLLER
4569/*
4570 * Polling 'interrupt' - used by things like netconsole to send skbs
4571 * without having to re-enable interrupts. It's not called while
4572 * the interrupt routine is executing.
4573 */
4574static void
2648345f 4575e1000_netpoll(struct net_device *netdev)
1da177e4 4576{
60490fe0 4577 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4578 disable_irq(adapter->pdev->irq);
4579 e1000_intr(adapter->pdev->irq, netdev, NULL);
c4cfe567 4580 e1000_clean_tx_irq(adapter, adapter->tx_ring);
e8da8be1
JK		 4581#ifndef CONFIG_E1000_NAPI
4582 adapter->clean_rx(adapter, adapter->rx_ring);
4583#endif
1da177e4
LT		 4584 enable_irq(adapter->pdev->irq);
4585}
4586#endif
4587
4588/* e1000_main.c */