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e1000: Enable custom configuration bits for 82571/2 controllers
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / net / e1000 / e1000_main.c
CommitLineData
1da177e4
LT		 1/*******************************************************************************
2
3
2648345f 4 Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
1da177e4
LT		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include "e1000.h"
30
31/* Change Log
2b02893e
MC		 32 * 6.0.58 4/20/05
33 * o Accepted ethtool cleanup patch from Stephen Hemminger
2648345f
MC		 34 * 6.0.44+ 2/15/05
35 * o applied Anton's patch to resolve tx hang in hardware
36 * o Applied Andrew Mortons patch - e1000 stops working after resume
1da177e4
LT		 37 */
38
39char e1000_driver_name[] = "e1000";
40char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
41#ifndef CONFIG_E1000_NAPI
42#define DRIVERNAPI
43#else
44#define DRIVERNAPI "-NAPI"
45#endif
2b02893e 46#define DRV_VERSION "6.0.60-k2"DRIVERNAPI
1da177e4 47char e1000_driver_version[] = DRV_VERSION;
2b02893e 48char e1000_copyright[] = "Copyright (c) 1999-2005 Intel Corporation.";
1da177e4
LT		 49
50/* e1000_pci_tbl - PCI Device ID Table
51 *
52 * Last entry must be all 0s
53 *
54 * Macro expands to...
55 * {PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)}
56 */
57static struct pci_device_id e1000_pci_tbl[] = {
58 INTEL_E1000_ETHERNET_DEVICE(0x1000),
59 INTEL_E1000_ETHERNET_DEVICE(0x1001),
60 INTEL_E1000_ETHERNET_DEVICE(0x1004),
61 INTEL_E1000_ETHERNET_DEVICE(0x1008),
62 INTEL_E1000_ETHERNET_DEVICE(0x1009),
63 INTEL_E1000_ETHERNET_DEVICE(0x100C),
64 INTEL_E1000_ETHERNET_DEVICE(0x100D),
65 INTEL_E1000_ETHERNET_DEVICE(0x100E),
66 INTEL_E1000_ETHERNET_DEVICE(0x100F),
67 INTEL_E1000_ETHERNET_DEVICE(0x1010),
68 INTEL_E1000_ETHERNET_DEVICE(0x1011),
69 INTEL_E1000_ETHERNET_DEVICE(0x1012),
70 INTEL_E1000_ETHERNET_DEVICE(0x1013),
71 INTEL_E1000_ETHERNET_DEVICE(0x1014),
72 INTEL_E1000_ETHERNET_DEVICE(0x1015),
73 INTEL_E1000_ETHERNET_DEVICE(0x1016),
74 INTEL_E1000_ETHERNET_DEVICE(0x1017),
75 INTEL_E1000_ETHERNET_DEVICE(0x1018),
76 INTEL_E1000_ETHERNET_DEVICE(0x1019),
2648345f 77 INTEL_E1000_ETHERNET_DEVICE(0x101A),
1da177e4
LT		 78 INTEL_E1000_ETHERNET_DEVICE(0x101D),
79 INTEL_E1000_ETHERNET_DEVICE(0x101E),
80 INTEL_E1000_ETHERNET_DEVICE(0x1026),
81 INTEL_E1000_ETHERNET_DEVICE(0x1027),
82 INTEL_E1000_ETHERNET_DEVICE(0x1028),
83 INTEL_E1000_ETHERNET_DEVICE(0x1075),
84 INTEL_E1000_ETHERNET_DEVICE(0x1076),
85 INTEL_E1000_ETHERNET_DEVICE(0x1077),
86 INTEL_E1000_ETHERNET_DEVICE(0x1078),
87 INTEL_E1000_ETHERNET_DEVICE(0x1079),
88 INTEL_E1000_ETHERNET_DEVICE(0x107A),
89 INTEL_E1000_ETHERNET_DEVICE(0x107B),
90 INTEL_E1000_ETHERNET_DEVICE(0x107C),
91 INTEL_E1000_ETHERNET_DEVICE(0x108A),
2648345f
MC		 92 INTEL_E1000_ETHERNET_DEVICE(0x108B),
93 INTEL_E1000_ETHERNET_DEVICE(0x108C),
94 INTEL_E1000_ETHERNET_DEVICE(0x1099),
1da177e4
LT		 95 /* required last entry */
96 {0,}
97};
98
99MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
100
101int e1000_up(struct e1000_adapter *adapter);
102void e1000_down(struct e1000_adapter *adapter);
103void e1000_reset(struct e1000_adapter *adapter);
104int e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx);
581d708e
MC		 105int e1000_setup_all_tx_resources(struct e1000_adapter *adapter);
106int e1000_setup_all_rx_resources(struct e1000_adapter *adapter);
107void e1000_free_all_tx_resources(struct e1000_adapter *adapter);
108void e1000_free_all_rx_resources(struct e1000_adapter *adapter);
109int e1000_setup_tx_resources(struct e1000_adapter *adapter,
110 struct e1000_tx_ring *txdr);
111int e1000_setup_rx_resources(struct e1000_adapter *adapter,
112 struct e1000_rx_ring *rxdr);
113void e1000_free_tx_resources(struct e1000_adapter *adapter,
114 struct e1000_tx_ring *tx_ring);
115void e1000_free_rx_resources(struct e1000_adapter *adapter,
116 struct e1000_rx_ring *rx_ring);
1da177e4
LT		 117void e1000_update_stats(struct e1000_adapter *adapter);
118
119/* Local Function Prototypes */
120
121static int e1000_init_module(void);
122static void e1000_exit_module(void);
123static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
124static void __devexit e1000_remove(struct pci_dev *pdev);
581d708e
MC		 125static int e1000_alloc_queues(struct e1000_adapter *adapter);
126#ifdef CONFIG_E1000_MQ
127static void e1000_setup_queue_mapping(struct e1000_adapter *adapter);
128#endif
1da177e4
LT		 129static int e1000_sw_init(struct e1000_adapter *adapter);
130static int e1000_open(struct net_device *netdev);
131static int e1000_close(struct net_device *netdev);
132static void e1000_configure_tx(struct e1000_adapter *adapter);
133static void e1000_configure_rx(struct e1000_adapter *adapter);
134static void e1000_setup_rctl(struct e1000_adapter *adapter);
581d708e
MC		 135static void e1000_clean_all_tx_rings(struct e1000_adapter *adapter);
136static void e1000_clean_all_rx_rings(struct e1000_adapter *adapter);
137static void e1000_clean_tx_ring(struct e1000_adapter *adapter,
138 struct e1000_tx_ring *tx_ring);
139static void e1000_clean_rx_ring(struct e1000_adapter *adapter,
140 struct e1000_rx_ring *rx_ring);
1da177e4
LT		 141static void e1000_set_multi(struct net_device *netdev);
142static void e1000_update_phy_info(unsigned long data);
143static void e1000_watchdog(unsigned long data);
144static void e1000_watchdog_task(struct e1000_adapter *adapter);
145static void e1000_82547_tx_fifo_stall(unsigned long data);
146static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
147static struct net_device_stats * e1000_get_stats(struct net_device *netdev);
148static int e1000_change_mtu(struct net_device *netdev, int new_mtu);
149static int e1000_set_mac(struct net_device *netdev, void *p);
150static irqreturn_t e1000_intr(int irq, void *data, struct pt_regs *regs);
581d708e
MC		 151static boolean_t e1000_clean_tx_irq(struct e1000_adapter *adapter,
152 struct e1000_tx_ring *tx_ring);
1da177e4 153#ifdef CONFIG_E1000_NAPI
581d708e 154static int e1000_clean(struct net_device *poll_dev, int *budget);
1da177e4 155static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
581d708e 156 struct e1000_rx_ring *rx_ring,
1da177e4 157 int *work_done, int work_to_do);
2d7edb92 158static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
581d708e 159 struct e1000_rx_ring *rx_ring,
2d7edb92 160 int *work_done, int work_to_do);
1da177e4 161#else
581d708e
MC		 162static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
163 struct e1000_rx_ring *rx_ring);
164static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
165 struct e1000_rx_ring *rx_ring);
1da177e4 166#endif
581d708e
MC		 167static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
168 struct e1000_rx_ring *rx_ring);
169static void e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
170 struct e1000_rx_ring *rx_ring);
1da177e4
LT		 171static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
172static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
173 int cmd);
174void e1000_set_ethtool_ops(struct net_device *netdev);
175static void e1000_enter_82542_rst(struct e1000_adapter *adapter);
176static void e1000_leave_82542_rst(struct e1000_adapter *adapter);
177static void e1000_tx_timeout(struct net_device *dev);
178static void e1000_tx_timeout_task(struct net_device *dev);
179static void e1000_smartspeed(struct e1000_adapter *adapter);
180static inline int e1000_82547_fifo_workaround(struct e1000_adapter *adapter,
181 struct sk_buff *skb);
182
183static void e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp);
184static void e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid);
185static void e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
186static void e1000_restore_vlan(struct e1000_adapter *adapter);
187
829ca9a3 188static int e1000_suspend(struct pci_dev *pdev, pm_message_t state);
1da177e4
LT		 189#ifdef CONFIG_PM
190static int e1000_resume(struct pci_dev *pdev);
191#endif
192
193#ifdef CONFIG_NET_POLL_CONTROLLER
194/* for netdump / net console */
195static void e1000_netpoll (struct net_device *netdev);
196#endif
197
24025e4e
MC		 198#ifdef CONFIG_E1000_MQ
199/* for multiple Rx queues */
200void e1000_rx_schedule(void *data);
201#endif
202
1da177e4
LT		 203/* Exported from other modules */
204
205extern void e1000_check_options(struct e1000_adapter *adapter);
206
207static struct pci_driver e1000_driver = {
208 .name = e1000_driver_name,
209 .id_table = e1000_pci_tbl,
210 .probe = e1000_probe,
211 .remove = __devexit_p(e1000_remove),
212 /* Power Managment Hooks */
213#ifdef CONFIG_PM
214 .suspend = e1000_suspend,
215 .resume = e1000_resume
216#endif
217};
218
219MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
220MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
221MODULE_LICENSE("GPL");
222MODULE_VERSION(DRV_VERSION);
223
224static int debug = NETIF_MSG_DRV | NETIF_MSG_PROBE;
225module_param(debug, int, 0);
226MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
227
228/**
229 * e1000_init_module - Driver Registration Routine
230 *
231 * e1000_init_module is the first routine called when the driver is
232 * loaded. All it does is register with the PCI subsystem.
233 **/
234
235static int __init
236e1000_init_module(void)
237{
238 int ret;
239 printk(KERN_INFO "%s - version %s\n",
240 e1000_driver_string, e1000_driver_version);
241
242 printk(KERN_INFO "%s\n", e1000_copyright);
243
244 ret = pci_module_init(&e1000_driver);
8b378def 245
1da177e4
LT		 246 return ret;
247}
248
249module_init(e1000_init_module);
250
251/**
252 * e1000_exit_module - Driver Exit Cleanup Routine
253 *
254 * e1000_exit_module is called just before the driver is removed
255 * from memory.
256 **/
257
258static void __exit
259e1000_exit_module(void)
260{
1da177e4
LT		 261 pci_unregister_driver(&e1000_driver);
262}
263
264module_exit(e1000_exit_module);
265
266/**
267 * e1000_irq_disable - Mask off interrupt generation on the NIC
268 * @adapter: board private structure
269 **/
270
271static inline void
272e1000_irq_disable(struct e1000_adapter *adapter)
273{
274 atomic_inc(&adapter->irq_sem);
275 E1000_WRITE_REG(&adapter->hw, IMC, ~0);
276 E1000_WRITE_FLUSH(&adapter->hw);
277 synchronize_irq(adapter->pdev->irq);
278}
279
280/**
281 * e1000_irq_enable - Enable default interrupt generation settings
282 * @adapter: board private structure
283 **/
284
285static inline void
286e1000_irq_enable(struct e1000_adapter *adapter)
287{
288 if(likely(atomic_dec_and_test(&adapter->irq_sem))) {
289 E1000_WRITE_REG(&adapter->hw, IMS, IMS_ENABLE_MASK);
290 E1000_WRITE_FLUSH(&adapter->hw);
291 }
292}
2d7edb92
MC		 293void
294e1000_update_mng_vlan(struct e1000_adapter *adapter)
295{
296 struct net_device *netdev = adapter->netdev;
297 uint16_t vid = adapter->hw.mng_cookie.vlan_id;
298 uint16_t old_vid = adapter->mng_vlan_id;
299 if(adapter->vlgrp) {
300 if(!adapter->vlgrp->vlan_devices[vid]) {
301 if(adapter->hw.mng_cookie.status &
302 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) {
303 e1000_vlan_rx_add_vid(netdev, vid);
304 adapter->mng_vlan_id = vid;
305 } else
306 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
307
308 if((old_vid != (uint16_t)E1000_MNG_VLAN_NONE) &&
309 (vid != old_vid) &&
310 !adapter->vlgrp->vlan_devices[old_vid])
311 e1000_vlan_rx_kill_vid(netdev, old_vid);
312 }
313 }
314}
315
1da177e4
LT		 316int
317e1000_up(struct e1000_adapter *adapter)
318{
319 struct net_device *netdev = adapter->netdev;
581d708e 320 int i, err;
1da177e4
LT		 321
322 /* hardware has been reset, we need to reload some things */
323
324 /* Reset the PHY if it was previously powered down */
325 if(adapter->hw.media_type == e1000_media_type_copper) {
326 uint16_t mii_reg;
327 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
328 if(mii_reg & MII_CR_POWER_DOWN)
329 e1000_phy_reset(&adapter->hw);
330 }
331
332 e1000_set_multi(netdev);
333
334 e1000_restore_vlan(adapter);
335
336 e1000_configure_tx(adapter);
337 e1000_setup_rctl(adapter);
338 e1000_configure_rx(adapter);
581d708e
MC		 339 for (i = 0; i < adapter->num_queues; i++)
340 adapter->alloc_rx_buf(adapter, &adapter->rx_ring[i]);
1da177e4 341
fa4f7ef3
MC		 342#ifdef CONFIG_PCI_MSI
343 if(adapter->hw.mac_type > e1000_82547_rev_2) {
344 adapter->have_msi = TRUE;
345 if((err = pci_enable_msi(adapter->pdev))) {
346 DPRINTK(PROBE, ERR,
347 "Unable to allocate MSI interrupt Error: %d\n", err);
348 adapter->have_msi = FALSE;
349 }
350 }
351#endif
1da177e4
LT		 352 if((err = request_irq(adapter->pdev->irq, &e1000_intr,
353 SA_SHIRQ | SA_SAMPLE_RANDOM,
2648345f
MC		 354 netdev->name, netdev))) {
355 DPRINTK(PROBE, ERR,
356 "Unable to allocate interrupt Error: %d\n", err);
1da177e4 357 return err;
2648345f 358 }
1da177e4
LT		 359
360 mod_timer(&adapter->watchdog_timer, jiffies);
1da177e4
LT		 361
362#ifdef CONFIG_E1000_NAPI
363 netif_poll_enable(netdev);
364#endif
5de55624
MC		 365 e1000_irq_enable(adapter);
366
1da177e4
LT		 367 return 0;
368}
369
370void
371e1000_down(struct e1000_adapter *adapter)
372{
373 struct net_device *netdev = adapter->netdev;
374
375 e1000_irq_disable(adapter);
24025e4e
MC		 376#ifdef CONFIG_E1000_MQ
377 while (atomic_read(&adapter->rx_sched_call_data.count) != 0);
378#endif
1da177e4 379 free_irq(adapter->pdev->irq, netdev);
fa4f7ef3
MC		 380#ifdef CONFIG_PCI_MSI
381 if(adapter->hw.mac_type > e1000_82547_rev_2 &&
382 adapter->have_msi == TRUE)
383 pci_disable_msi(adapter->pdev);
384#endif
1da177e4
LT		 385 del_timer_sync(&adapter->tx_fifo_stall_timer);
386 del_timer_sync(&adapter->watchdog_timer);
387 del_timer_sync(&adapter->phy_info_timer);
388
389#ifdef CONFIG_E1000_NAPI
390 netif_poll_disable(netdev);
391#endif
392 adapter->link_speed = 0;
393 adapter->link_duplex = 0;
394 netif_carrier_off(netdev);
395 netif_stop_queue(netdev);
396
397 e1000_reset(adapter);
581d708e
MC		 398 e1000_clean_all_tx_rings(adapter);
399 e1000_clean_all_rx_rings(adapter);
1da177e4
LT		 400
401 /* If WoL is not enabled
2d7edb92 402 * and management mode is not IAMT
1da177e4 403 * Power down the PHY so no link is implied when interface is down */
2d7edb92
MC		 404 if(!adapter->wol && adapter->hw.mac_type >= e1000_82540 &&
405 adapter->hw.media_type == e1000_media_type_copper &&
406 !e1000_check_mng_mode(&adapter->hw) &&
407 !(E1000_READ_REG(&adapter->hw, MANC) & E1000_MANC_SMBUS_EN)) {
1da177e4
LT		 408 uint16_t mii_reg;
409 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
410 mii_reg |= MII_CR_POWER_DOWN;
411 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
4e48a2b9 412 mdelay(1);
1da177e4
LT		 413 }
414}
415
416void
417e1000_reset(struct e1000_adapter *adapter)
418{
1125ecbc 419 struct net_device *netdev = adapter->netdev;
2d7edb92 420 uint32_t pba, manc;
1125ecbc
MC		 421 uint16_t fc_high_water_mark = E1000_FC_HIGH_DIFF;
422 uint16_t fc_low_water_mark = E1000_FC_LOW_DIFF;
1da177e4
LT		 423
424 /* Repartition Pba for greater than 9k mtu
425 * To take effect CTRL.RST is required.
426 */
427
2d7edb92
MC		 428 switch (adapter->hw.mac_type) {
429 case e1000_82547:
0e6ef3e0 430 case e1000_82547_rev_2:
2d7edb92
MC		 431 pba = E1000_PBA_30K;
432 break;
868d5309
MC		 433 case e1000_82571:
434 case e1000_82572:
435 pba = E1000_PBA_38K;
436 break;
2d7edb92
MC		 437 case e1000_82573:
438 pba = E1000_PBA_12K;
439 break;
440 default:
441 pba = E1000_PBA_48K;
442 break;
443 }
444
1125ecbc
MC		 445 if((adapter->hw.mac_type != e1000_82573) &&
446 (adapter->rx_buffer_len > E1000_RXBUFFER_8192)) {
447 pba -= 8; /* allocate more FIFO for Tx */
448 /* send an XOFF when there is enough space in the
449 * Rx FIFO to hold one extra full size Rx packet
450 */
451 fc_high_water_mark = netdev->mtu + ENET_HEADER_SIZE +
452 ETHERNET_FCS_SIZE + 1;
453 fc_low_water_mark = fc_high_water_mark + 8;
454 }
2d7edb92
MC		 455
456
457 if(adapter->hw.mac_type == e1000_82547) {
1da177e4
LT		 458 adapter->tx_fifo_head = 0;
459 adapter->tx_head_addr = pba << E1000_TX_HEAD_ADDR_SHIFT;
460 adapter->tx_fifo_size =
461 (E1000_PBA_40K - pba) << E1000_PBA_BYTES_SHIFT;
462 atomic_set(&adapter->tx_fifo_stall, 0);
463 }
2d7edb92 464
1da177e4
LT		 465 E1000_WRITE_REG(&adapter->hw, PBA, pba);
466
467 /* flow control settings */
468 adapter->hw.fc_high_water = (pba << E1000_PBA_BYTES_SHIFT) -
1125ecbc 469 fc_high_water_mark;
1da177e4 470 adapter->hw.fc_low_water = (pba << E1000_PBA_BYTES_SHIFT) -
1125ecbc 471 fc_low_water_mark;
1da177e4
LT		 472 adapter->hw.fc_pause_time = E1000_FC_PAUSE_TIME;
473 adapter->hw.fc_send_xon = 1;
474 adapter->hw.fc = adapter->hw.original_fc;
475
2d7edb92 476 /* Allow time for pending master requests to run */
1da177e4
LT		 477 e1000_reset_hw(&adapter->hw);
478 if(adapter->hw.mac_type >= e1000_82544)
479 E1000_WRITE_REG(&adapter->hw, WUC, 0);
480 if(e1000_init_hw(&adapter->hw))
481 DPRINTK(PROBE, ERR, "Hardware Error\n");
2d7edb92 482 e1000_update_mng_vlan(adapter);
1da177e4
LT		 483 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
484 E1000_WRITE_REG(&adapter->hw, VET, ETHERNET_IEEE_VLAN_TYPE);
485
486 e1000_reset_adaptive(&adapter->hw);
487 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
2d7edb92
MC		 488 if (adapter->en_mng_pt) {
489 manc = E1000_READ_REG(&adapter->hw, MANC);
490 manc |= (E1000_MANC_ARP_EN | E1000_MANC_EN_MNG2HOST);
491 E1000_WRITE_REG(&adapter->hw, MANC, manc);
492 }
1da177e4
LT		 493}
494
495/**
496 * e1000_probe - Device Initialization Routine
497 * @pdev: PCI device information struct
498 * @ent: entry in e1000_pci_tbl
499 *
500 * Returns 0 on success, negative on failure
501 *
502 * e1000_probe initializes an adapter identified by a pci_dev structure.
503 * The OS initialization, configuring of the adapter private structure,
504 * and a hardware reset occur.
505 **/
506
507static int __devinit
508e1000_probe(struct pci_dev *pdev,
509 const struct pci_device_id *ent)
510{
511 struct net_device *netdev;
512 struct e1000_adapter *adapter;
2d7edb92 513 unsigned long mmio_start, mmio_len;
868d5309 514 uint32_t ctrl_ext;
2d7edb92
MC		 515 uint32_t swsm;
516
1da177e4 517 static int cards_found = 0;
2d7edb92 518 int i, err, pci_using_dac;
1da177e4
LT		 519 uint16_t eeprom_data;
520 uint16_t eeprom_apme_mask = E1000_EEPROM_APME;
1da177e4
LT		 521 if((err = pci_enable_device(pdev)))
522 return err;
523
524 if(!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
525 pci_using_dac = 1;
526 } else {
527 if((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
528 E1000_ERR("No usable DMA configuration, aborting\n");
529 return err;
530 }
531 pci_using_dac = 0;
532 }
533
534 if((err = pci_request_regions(pdev, e1000_driver_name)))
535 return err;
536
537 pci_set_master(pdev);
538
539 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
540 if(!netdev) {
541 err = -ENOMEM;
542 goto err_alloc_etherdev;
543 }
544
545 SET_MODULE_OWNER(netdev);
546 SET_NETDEV_DEV(netdev, &pdev->dev);
547
548 pci_set_drvdata(pdev, netdev);
60490fe0 549 adapter = netdev_priv(netdev);
1da177e4
LT		 550 adapter->netdev = netdev;
551 adapter->pdev = pdev;
552 adapter->hw.back = adapter;
553 adapter->msg_enable = (1 << debug) - 1;
554
555 mmio_start = pci_resource_start(pdev, BAR_0);
556 mmio_len = pci_resource_len(pdev, BAR_0);
557
558 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
559 if(!adapter->hw.hw_addr) {
560 err = -EIO;
561 goto err_ioremap;
562 }
563
564 for(i = BAR_1; i <= BAR_5; i++) {
565 if(pci_resource_len(pdev, i) == 0)
566 continue;
567 if(pci_resource_flags(pdev, i) & IORESOURCE_IO) {
568 adapter->hw.io_base = pci_resource_start(pdev, i);
569 break;
570 }
571 }
572
573 netdev->open = &e1000_open;
574 netdev->stop = &e1000_close;
575 netdev->hard_start_xmit = &e1000_xmit_frame;
576 netdev->get_stats = &e1000_get_stats;
577 netdev->set_multicast_list = &e1000_set_multi;
578 netdev->set_mac_address = &e1000_set_mac;
579 netdev->change_mtu = &e1000_change_mtu;
580 netdev->do_ioctl = &e1000_ioctl;
581 e1000_set_ethtool_ops(netdev);
582 netdev->tx_timeout = &e1000_tx_timeout;
583 netdev->watchdog_timeo = 5 * HZ;
584#ifdef CONFIG_E1000_NAPI
585 netdev->poll = &e1000_clean;
586 netdev->weight = 64;
587#endif
588 netdev->vlan_rx_register = e1000_vlan_rx_register;
589 netdev->vlan_rx_add_vid = e1000_vlan_rx_add_vid;
590 netdev->vlan_rx_kill_vid = e1000_vlan_rx_kill_vid;
591#ifdef CONFIG_NET_POLL_CONTROLLER
592 netdev->poll_controller = e1000_netpoll;
593#endif
594 strcpy(netdev->name, pci_name(pdev));
595
596 netdev->mem_start = mmio_start;
597 netdev->mem_end = mmio_start + mmio_len;
598 netdev->base_addr = adapter->hw.io_base;
599
600 adapter->bd_number = cards_found;
601
602 /* setup the private structure */
603
604 if((err = e1000_sw_init(adapter)))
605 goto err_sw_init;
606
2d7edb92
MC		 607 if((err = e1000_check_phy_reset_block(&adapter->hw)))
608 DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n");
609
1da177e4
LT		 610 if(adapter->hw.mac_type >= e1000_82543) {
611 netdev->features = NETIF_F_SG |
612 NETIF_F_HW_CSUM |
613 NETIF_F_HW_VLAN_TX |
614 NETIF_F_HW_VLAN_RX |
615 NETIF_F_HW_VLAN_FILTER;
616 }
617
618#ifdef NETIF_F_TSO
619 if((adapter->hw.mac_type >= e1000_82544) &&
620 (adapter->hw.mac_type != e1000_82547))
621 netdev->features |= NETIF_F_TSO;
2d7edb92
MC		 622
623#ifdef NETIF_F_TSO_IPV6
624 if(adapter->hw.mac_type > e1000_82547_rev_2)
625 netdev->features |= NETIF_F_TSO_IPV6;
626#endif
1da177e4
LT		 627#endif
628 if(pci_using_dac)
629 netdev->features |= NETIF_F_HIGHDMA;
630
631 /* hard_start_xmit is safe against parallel locking */
632 netdev->features |= NETIF_F_LLTX;
633
2d7edb92
MC		 634 adapter->en_mng_pt = e1000_enable_mng_pass_thru(&adapter->hw);
635
1da177e4
LT		 636 /* before reading the EEPROM, reset the controller to
637 * put the device in a known good starting state */
638
639 e1000_reset_hw(&adapter->hw);
640
641 /* make sure the EEPROM is good */
642
643 if(e1000_validate_eeprom_checksum(&adapter->hw) < 0) {
644 DPRINTK(PROBE, ERR, "The EEPROM Checksum Is Not Valid\n");
645 err = -EIO;
646 goto err_eeprom;
647 }
648
649 /* copy the MAC address out of the EEPROM */
650
2648345f 651 if(e1000_read_mac_addr(&adapter->hw))
1da177e4
LT		 652 DPRINTK(PROBE, ERR, "EEPROM Read Error\n");
653 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
9beb0ac1 654 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
1da177e4 655
9beb0ac1 656 if(!is_valid_ether_addr(netdev->perm_addr)) {
1da177e4
LT		 657 DPRINTK(PROBE, ERR, "Invalid MAC Address\n");
658 err = -EIO;
659 goto err_eeprom;
660 }
661
662 e1000_read_part_num(&adapter->hw, &(adapter->part_num));
663
664 e1000_get_bus_info(&adapter->hw);
665
666 init_timer(&adapter->tx_fifo_stall_timer);
667 adapter->tx_fifo_stall_timer.function = &e1000_82547_tx_fifo_stall;
668 adapter->tx_fifo_stall_timer.data = (unsigned long) adapter;
669
670 init_timer(&adapter->watchdog_timer);
671 adapter->watchdog_timer.function = &e1000_watchdog;
672 adapter->watchdog_timer.data = (unsigned long) adapter;
673
674 INIT_WORK(&adapter->watchdog_task,
675 (void (*)(void *))e1000_watchdog_task, adapter);
676
677 init_timer(&adapter->phy_info_timer);
678 adapter->phy_info_timer.function = &e1000_update_phy_info;
679 adapter->phy_info_timer.data = (unsigned long) adapter;
680
681 INIT_WORK(&adapter->tx_timeout_task,
682 (void (*)(void *))e1000_tx_timeout_task, netdev);
683
684 /* we're going to reset, so assume we have no link for now */
685
686 netif_carrier_off(netdev);
687 netif_stop_queue(netdev);
688
689 e1000_check_options(adapter);
690
691 /* Initial Wake on LAN setting
692 * If APM wake is enabled in the EEPROM,
693 * enable the ACPI Magic Packet filter
694 */
695
696 switch(adapter->hw.mac_type) {
697 case e1000_82542_rev2_0:
698 case e1000_82542_rev2_1:
699 case e1000_82543:
700 break;
701 case e1000_82544:
702 e1000_read_eeprom(&adapter->hw,
703 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
704 eeprom_apme_mask = E1000_EEPROM_82544_APM;
705 break;
706 case e1000_82546:
707 case e1000_82546_rev_3:
708 if((E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_FUNC_1)
709 && (adapter->hw.media_type == e1000_media_type_copper)) {
710 e1000_read_eeprom(&adapter->hw,
711 EEPROM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
712 break;
713 }
714 /* Fall Through */
715 default:
716 e1000_read_eeprom(&adapter->hw,
717 EEPROM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
718 break;
719 }
720 if(eeprom_data & eeprom_apme_mask)
721 adapter->wol |= E1000_WUFC_MAG;
722
723 /* reset the hardware with the new settings */
724 e1000_reset(adapter);
725
2d7edb92
MC		 726 /* Let firmware know the driver has taken over */
727 switch(adapter->hw.mac_type) {
868d5309
MC		 728 case e1000_82571:
729 case e1000_82572:
730 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
731 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
732 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
733 break;
2d7edb92
MC		 734 case e1000_82573:
735 swsm = E1000_READ_REG(&adapter->hw, SWSM);
736 E1000_WRITE_REG(&adapter->hw, SWSM,
737 swsm | E1000_SWSM_DRV_LOAD);
738 break;
739 default:
740 break;
741 }
742
1da177e4
LT		 743 strcpy(netdev->name, "eth%d");
744 if((err = register_netdev(netdev)))
745 goto err_register;
746
747 DPRINTK(PROBE, INFO, "Intel(R) PRO/1000 Network Connection\n");
748
749 cards_found++;
750 return 0;
751
752err_register:
753err_sw_init:
754err_eeprom:
755 iounmap(adapter->hw.hw_addr);
756err_ioremap:
757 free_netdev(netdev);
758err_alloc_etherdev:
759 pci_release_regions(pdev);
760 return err;
761}
762
763/**
764 * e1000_remove - Device Removal Routine
765 * @pdev: PCI device information struct
766 *
767 * e1000_remove is called by the PCI subsystem to alert the driver
768 * that it should release a PCI device. The could be caused by a
769 * Hot-Plug event, or because the driver is going to be removed from
770 * memory.
771 **/
772
773static void __devexit
774e1000_remove(struct pci_dev *pdev)
775{
776 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 777 struct e1000_adapter *adapter = netdev_priv(netdev);
868d5309 778 uint32_t ctrl_ext;
2d7edb92 779 uint32_t manc, swsm;
1da177e4
LT		 780
781 flush_scheduled_work();
581d708e
MC		 782#ifdef CONFIG_E1000_NAPI
783 int i;
784#endif
1da177e4
LT		 785
786 if(adapter->hw.mac_type >= e1000_82540 &&
787 adapter->hw.media_type == e1000_media_type_copper) {
788 manc = E1000_READ_REG(&adapter->hw, MANC);
789 if(manc & E1000_MANC_SMBUS_EN) {
790 manc |= E1000_MANC_ARP_EN;
791 E1000_WRITE_REG(&adapter->hw, MANC, manc);
792 }
793 }
794
2d7edb92 795 switch(adapter->hw.mac_type) {
868d5309
MC		 796 case e1000_82571:
797 case e1000_82572:
798 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
799 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
800 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
801 break;
2d7edb92
MC		 802 case e1000_82573:
803 swsm = E1000_READ_REG(&adapter->hw, SWSM);
804 E1000_WRITE_REG(&adapter->hw, SWSM,
805 swsm & ~E1000_SWSM_DRV_LOAD);
806 break;
807
808 default:
809 break;
810 }
811
1da177e4 812 unregister_netdev(netdev);
581d708e
MC		 813#ifdef CONFIG_E1000_NAPI
814 for (i = 0; i < adapter->num_queues; i++)
815 __dev_put(&adapter->polling_netdev[i]);
816#endif
1da177e4 817
2d7edb92
MC		 818 if(!e1000_check_phy_reset_block(&adapter->hw))
819 e1000_phy_hw_reset(&adapter->hw);
1da177e4 820
24025e4e
MC		 821 kfree(adapter->tx_ring);
822 kfree(adapter->rx_ring);
823#ifdef CONFIG_E1000_NAPI
824 kfree(adapter->polling_netdev);
825#endif
826
1da177e4
LT		 827 iounmap(adapter->hw.hw_addr);
828 pci_release_regions(pdev);
829
24025e4e
MC		 830#ifdef CONFIG_E1000_MQ
831 free_percpu(adapter->cpu_netdev);
832 free_percpu(adapter->cpu_tx_ring);
833#endif
1da177e4
LT		 834 free_netdev(netdev);
835
836 pci_disable_device(pdev);
837}
838
839/**
840 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
841 * @adapter: board private structure to initialize
842 *
843 * e1000_sw_init initializes the Adapter private data structure.
844 * Fields are initialized based on PCI device information and
845 * OS network device settings (MTU size).
846 **/
847
848static int __devinit
849e1000_sw_init(struct e1000_adapter *adapter)
850{
851 struct e1000_hw *hw = &adapter->hw;
852 struct net_device *netdev = adapter->netdev;
853 struct pci_dev *pdev = adapter->pdev;
581d708e
MC		 854#ifdef CONFIG_E1000_NAPI
855 int i;
856#endif
1da177e4
LT		 857
858 /* PCI config space info */
859
860 hw->vendor_id = pdev->vendor;
861 hw->device_id = pdev->device;
862 hw->subsystem_vendor_id = pdev->subsystem_vendor;
863 hw->subsystem_id = pdev->subsystem_device;
864
865 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
866
867 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
868
869 adapter->rx_buffer_len = E1000_RXBUFFER_2048;
2d7edb92 870 adapter->rx_ps_bsize0 = E1000_RXBUFFER_256;
1da177e4
LT		 871 hw->max_frame_size = netdev->mtu +
872 ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
873 hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE;
874
875 /* identify the MAC */
876
877 if(e1000_set_mac_type(hw)) {
878 DPRINTK(PROBE, ERR, "Unknown MAC Type\n");
879 return -EIO;
880 }
881
882 /* initialize eeprom parameters */
883
2d7edb92
MC		 884 if(e1000_init_eeprom_params(hw)) {
885 E1000_ERR("EEPROM initialization failed\n");
886 return -EIO;
887 }
1da177e4
LT		 888
889 switch(hw->mac_type) {
890 default:
891 break;
892 case e1000_82541:
893 case e1000_82547:
894 case e1000_82541_rev_2:
895 case e1000_82547_rev_2:
896 hw->phy_init_script = 1;
897 break;
898 }
899
900 e1000_set_media_type(hw);
901
902 hw->wait_autoneg_complete = FALSE;
903 hw->tbi_compatibility_en = TRUE;
904 hw->adaptive_ifs = TRUE;
905
906 /* Copper options */
907
908 if(hw->media_type == e1000_media_type_copper) {
909 hw->mdix = AUTO_ALL_MODES;
910 hw->disable_polarity_correction = FALSE;
911 hw->master_slave = E1000_MASTER_SLAVE;
912 }
913
24025e4e
MC		 914#ifdef CONFIG_E1000_MQ
915 /* Number of supported queues */
916 switch (hw->mac_type) {
917 case e1000_82571:
918 case e1000_82572:
919 adapter->num_queues = 2;
920 break;
921 default:
922 adapter->num_queues = 1;
923 break;
924 }
925 adapter->num_queues = min(adapter->num_queues, num_online_cpus());
926#else
581d708e 927 adapter->num_queues = 1;
24025e4e 928#endif
581d708e
MC		 929
930 if (e1000_alloc_queues(adapter)) {
931 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
932 return -ENOMEM;
933 }
934
935#ifdef CONFIG_E1000_NAPI
936 for (i = 0; i < adapter->num_queues; i++) {
937 adapter->polling_netdev[i].priv = adapter;
938 adapter->polling_netdev[i].poll = &e1000_clean;
939 adapter->polling_netdev[i].weight = 64;
940 dev_hold(&adapter->polling_netdev[i]);
941 set_bit(__LINK_STATE_START, &adapter->polling_netdev[i].state);
942 }
943#endif
24025e4e
MC		 944
945#ifdef CONFIG_E1000_MQ
946 e1000_setup_queue_mapping(adapter);
947#endif
948
1da177e4
LT		 949 atomic_set(&adapter->irq_sem, 1);
950 spin_lock_init(&adapter->stats_lock);
1da177e4
LT		 951
952 return 0;
953}
954
581d708e
MC		 955/**
956 * e1000_alloc_queues - Allocate memory for all rings
957 * @adapter: board private structure to initialize
958 *
959 * We allocate one ring per queue at run-time since we don't know the
960 * number of queues at compile-time. The polling_netdev array is
961 * intended for Multiqueue, but should work fine with a single queue.
962 **/
963
964static int __devinit
965e1000_alloc_queues(struct e1000_adapter *adapter)
966{
967 int size;
968
969 size = sizeof(struct e1000_tx_ring) * adapter->num_queues;
970 adapter->tx_ring = kmalloc(size, GFP_KERNEL);
971 if (!adapter->tx_ring)
972 return -ENOMEM;
973 memset(adapter->tx_ring, 0, size);
974
975 size = sizeof(struct e1000_rx_ring) * adapter->num_queues;
976 adapter->rx_ring = kmalloc(size, GFP_KERNEL);
977 if (!adapter->rx_ring) {
978 kfree(adapter->tx_ring);
979 return -ENOMEM;
980 }
981 memset(adapter->rx_ring, 0, size);
982
983#ifdef CONFIG_E1000_NAPI
984 size = sizeof(struct net_device) * adapter->num_queues;
985 adapter->polling_netdev = kmalloc(size, GFP_KERNEL);
986 if (!adapter->polling_netdev) {
987 kfree(adapter->tx_ring);
988 kfree(adapter->rx_ring);
989 return -ENOMEM;
990 }
991 memset(adapter->polling_netdev, 0, size);
992#endif
993
994 return E1000_SUCCESS;
995}
996
24025e4e
MC		 997#ifdef CONFIG_E1000_MQ
998static void __devinit
999e1000_setup_queue_mapping(struct e1000_adapter *adapter)
1000{
1001 int i, cpu;
1002
1003 adapter->rx_sched_call_data.func = e1000_rx_schedule;
1004 adapter->rx_sched_call_data.info = adapter->netdev;
1005 cpus_clear(adapter->rx_sched_call_data.cpumask);
1006
1007 adapter->cpu_netdev = alloc_percpu(struct net_device *);
1008 adapter->cpu_tx_ring = alloc_percpu(struct e1000_tx_ring *);
1009
1010 lock_cpu_hotplug();
1011 i = 0;
1012 for_each_online_cpu(cpu) {
1013 *per_cpu_ptr(adapter->cpu_tx_ring, cpu) = &adapter->tx_ring[i % adapter->num_queues];
1014 /* This is incomplete because we'd like to assign separate
1015 * physical cpus to these netdev polling structures and
1016 * avoid saturating a subset of cpus.
1017 */
1018 if (i < adapter->num_queues) {
1019 *per_cpu_ptr(adapter->cpu_netdev, cpu) = &adapter->polling_netdev[i];
1020 adapter->cpu_for_queue[i] = cpu;
1021 } else
1022 *per_cpu_ptr(adapter->cpu_netdev, cpu) = NULL;
1023
1024 i++;
1025 }
1026 unlock_cpu_hotplug();
1027}
1028#endif
1029
1da177e4
LT		 1030/**
1031 * e1000_open - Called when a network interface is made active
1032 * @netdev: network interface device structure
1033 *
1034 * Returns 0 on success, negative value on failure
1035 *
1036 * The open entry point is called when a network interface is made
1037 * active by the system (IFF_UP). At this point all resources needed
1038 * for transmit and receive operations are allocated, the interrupt
1039 * handler is registered with the OS, the watchdog timer is started,
1040 * and the stack is notified that the interface is ready.
1041 **/
1042
1043static int
1044e1000_open(struct net_device *netdev)
1045{
60490fe0 1046 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 1047 int err;
1048
1049 /* allocate transmit descriptors */
1050
581d708e 1051 if ((err = e1000_setup_all_tx_resources(adapter)))
1da177e4
LT		 1052 goto err_setup_tx;
1053
1054 /* allocate receive descriptors */
1055
581d708e 1056 if ((err = e1000_setup_all_rx_resources(adapter)))
1da177e4
LT		 1057 goto err_setup_rx;
1058
1059 if((err = e1000_up(adapter)))
1060 goto err_up;
2d7edb92
MC		 1061 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
1062 if((adapter->hw.mng_cookie.status &
1063 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
1064 e1000_update_mng_vlan(adapter);
1065 }
1da177e4
LT		 1066
1067 return E1000_SUCCESS;
1068
1069err_up:
581d708e 1070 e1000_free_all_rx_resources(adapter);
1da177e4 1071err_setup_rx:
581d708e 1072 e1000_free_all_tx_resources(adapter);
1da177e4
LT		 1073err_setup_tx:
1074 e1000_reset(adapter);
1075
1076 return err;
1077}
1078
1079/**
1080 * e1000_close - Disables a network interface
1081 * @netdev: network interface device structure
1082 *
1083 * Returns 0, this is not allowed to fail
1084 *
1085 * The close entry point is called when an interface is de-activated
1086 * by the OS. The hardware is still under the drivers control, but
1087 * needs to be disabled. A global MAC reset is issued to stop the
1088 * hardware, and all transmit and receive resources are freed.
1089 **/
1090
1091static int
1092e1000_close(struct net_device *netdev)
1093{
60490fe0 1094 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 1095
1096 e1000_down(adapter);
1097
581d708e
MC		 1098 e1000_free_all_tx_resources(adapter);
1099 e1000_free_all_rx_resources(adapter);
1da177e4 1100
2d7edb92
MC		 1101 if((adapter->hw.mng_cookie.status &
1102 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
1103 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1104 }
1da177e4
LT		 1105 return 0;
1106}
1107
1108/**
1109 * e1000_check_64k_bound - check that memory doesn't cross 64kB boundary
1110 * @adapter: address of board private structure
2d7edb92
MC		 1111 * @start: address of beginning of memory
1112 * @len: length of memory
1da177e4
LT		 1113 **/
1114static inline boolean_t
1115e1000_check_64k_bound(struct e1000_adapter *adapter,
1116 void *start, unsigned long len)
1117{
1118 unsigned long begin = (unsigned long) start;
1119 unsigned long end = begin + len;
1120
2648345f
MC		 1121 /* First rev 82545 and 82546 need to not allow any memory
1122 * write location to cross 64k boundary due to errata 23 */
1da177e4 1123 if (adapter->hw.mac_type == e1000_82545 ||
2648345f 1124 adapter->hw.mac_type == e1000_82546) {
1da177e4
LT		 1125 return ((begin ^ (end - 1)) >> 16) != 0 ? FALSE : TRUE;
1126 }
1127
1128 return TRUE;
1129}
1130
1131/**
1132 * e1000_setup_tx_resources - allocate Tx resources (Descriptors)
1133 * @adapter: board private structure
581d708e 1134 * @txdr: tx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1135 *
1136 * Return 0 on success, negative on failure
1137 **/
1138
1139int
581d708e
MC		 1140e1000_setup_tx_resources(struct e1000_adapter *adapter,
1141 struct e1000_tx_ring *txdr)
1da177e4 1142{
1da177e4
LT		 1143 struct pci_dev *pdev = adapter->pdev;
1144 int size;
1145
1146 size = sizeof(struct e1000_buffer) * txdr->count;
1147 txdr->buffer_info = vmalloc(size);
1148 if(!txdr->buffer_info) {
2648345f
MC		 1149 DPRINTK(PROBE, ERR,
1150 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1151 return -ENOMEM;
1152 }
1153 memset(txdr->buffer_info, 0, size);
2ae76d98 1154 memset(&txdr->previous_buffer_info, 0, sizeof(struct e1000_buffer));
1da177e4
LT		 1155
1156 /* round up to nearest 4K */
1157
1158 txdr->size = txdr->count * sizeof(struct e1000_tx_desc);
1159 E1000_ROUNDUP(txdr->size, 4096);
1160
1161 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
1162 if(!txdr->desc) {
1163setup_tx_desc_die:
1da177e4 1164 vfree(txdr->buffer_info);
2648345f
MC		 1165 DPRINTK(PROBE, ERR,
1166 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1167 return -ENOMEM;
1168 }
1169
2648345f 1170 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1171 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1172 void *olddesc = txdr->desc;
1173 dma_addr_t olddma = txdr->dma;
2648345f
MC		 1174 DPRINTK(TX_ERR, ERR, "txdr align check failed: %u bytes "
1175 "at %p\n", txdr->size, txdr->desc);
1176 /* Try again, without freeing the previous */
1da177e4 1177 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
1da177e4 1178 if(!txdr->desc) {
2648345f 1179 /* Failed allocation, critical failure */
1da177e4
LT		 1180 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1181 goto setup_tx_desc_die;
1182 }
1183
1184 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1185 /* give up */
2648345f
MC		 1186 pci_free_consistent(pdev, txdr->size, txdr->desc,
1187 txdr->dma);
1da177e4
LT		 1188 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1189 DPRINTK(PROBE, ERR,
2648345f
MC		 1190 "Unable to allocate aligned memory "
1191 "for the transmit descriptor ring\n");
1da177e4
LT		 1192 vfree(txdr->buffer_info);
1193 return -ENOMEM;
1194 } else {
2648345f 1195 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1196 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1197 }
1198 }
1199 memset(txdr->desc, 0, txdr->size);
1200
1201 txdr->next_to_use = 0;
1202 txdr->next_to_clean = 0;
2ae76d98 1203 spin_lock_init(&txdr->tx_lock);
1da177e4
LT		 1204
1205 return 0;
1206}
1207
581d708e
MC		 1208/**
1209 * e1000_setup_all_tx_resources - wrapper to allocate Tx resources
1210 * (Descriptors) for all queues
1211 * @adapter: board private structure
1212 *
1213 * If this function returns with an error, then it's possible one or
1214 * more of the rings is populated (while the rest are not). It is the
1215 * callers duty to clean those orphaned rings.
1216 *
1217 * Return 0 on success, negative on failure
1218 **/
1219
1220int
1221e1000_setup_all_tx_resources(struct e1000_adapter *adapter)
1222{
1223 int i, err = 0;
1224
1225 for (i = 0; i < adapter->num_queues; i++) {
1226 err = e1000_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1227 if (err) {
1228 DPRINTK(PROBE, ERR,
1229 "Allocation for Tx Queue %u failed\n", i);
1230 break;
1231 }
1232 }
1233
1234 return err;
1235}
1236
1da177e4
LT		 1237/**
1238 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
1239 * @adapter: board private structure
1240 *
1241 * Configure the Tx unit of the MAC after a reset.
1242 **/
1243
1244static void
1245e1000_configure_tx(struct e1000_adapter *adapter)
1246{
581d708e
MC		 1247 uint64_t tdba;
1248 struct e1000_hw *hw = &adapter->hw;
1249 uint32_t tdlen, tctl, tipg, tarc;
1da177e4
LT		 1250
1251 /* Setup the HW Tx Head and Tail descriptor pointers */
1252
24025e4e
MC		 1253 switch (adapter->num_queues) {
1254 case 2:
1255 tdba = adapter->tx_ring[1].dma;
1256 tdlen = adapter->tx_ring[1].count *
1257 sizeof(struct e1000_tx_desc);
1258 E1000_WRITE_REG(hw, TDBAL1, (tdba & 0x00000000ffffffffULL));
1259 E1000_WRITE_REG(hw, TDBAH1, (tdba >> 32));
1260 E1000_WRITE_REG(hw, TDLEN1, tdlen);
1261 E1000_WRITE_REG(hw, TDH1, 0);
1262 E1000_WRITE_REG(hw, TDT1, 0);
1263 adapter->tx_ring[1].tdh = E1000_TDH1;
1264 adapter->tx_ring[1].tdt = E1000_TDT1;
1265 /* Fall Through */
1266 case 1:
1267 default:
581d708e
MC		 1268 tdba = adapter->tx_ring[0].dma;
1269 tdlen = adapter->tx_ring[0].count *
1270 sizeof(struct e1000_tx_desc);
1271 E1000_WRITE_REG(hw, TDBAL, (tdba & 0x00000000ffffffffULL));
1272 E1000_WRITE_REG(hw, TDBAH, (tdba >> 32));
1273 E1000_WRITE_REG(hw, TDLEN, tdlen);
1274 E1000_WRITE_REG(hw, TDH, 0);
1275 E1000_WRITE_REG(hw, TDT, 0);
1276 adapter->tx_ring[0].tdh = E1000_TDH;
1277 adapter->tx_ring[0].tdt = E1000_TDT;
24025e4e
MC		 1278 break;
1279 }
1da177e4
LT		 1280
1281 /* Set the default values for the Tx Inter Packet Gap timer */
1282
581d708e 1283 switch (hw->mac_type) {
1da177e4
LT		 1284 case e1000_82542_rev2_0:
1285 case e1000_82542_rev2_1:
1286 tipg = DEFAULT_82542_TIPG_IPGT;
1287 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
1288 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
1289 break;
1290 default:
581d708e
MC		 1291 if (hw->media_type == e1000_media_type_fiber ||
1292 hw->media_type == e1000_media_type_internal_serdes)
1da177e4
LT		 1293 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
1294 else
1295 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
1296 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
1297 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
1298 }
581d708e 1299 E1000_WRITE_REG(hw, TIPG, tipg);
1da177e4
LT		 1300
1301 /* Set the Tx Interrupt Delay register */
1302
581d708e
MC		 1303 E1000_WRITE_REG(hw, TIDV, adapter->tx_int_delay);
1304 if (hw->mac_type >= e1000_82540)
1305 E1000_WRITE_REG(hw, TADV, adapter->tx_abs_int_delay);
1da177e4
LT		 1306
1307 /* Program the Transmit Control Register */
1308
581d708e 1309 tctl = E1000_READ_REG(hw, TCTL);
1da177e4
LT		 1310
1311 tctl &= ~E1000_TCTL_CT;
24025e4e 1312 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP | E1000_TCTL_RTLC |
1da177e4
LT		 1313 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1314
581d708e 1315 E1000_WRITE_REG(hw, TCTL, tctl);
1da177e4 1316
2ae76d98
MC		 1317 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
1318 tarc = E1000_READ_REG(hw, TARC0);
1319 tarc |= ((1 << 25) | (1 << 21));
1320 E1000_WRITE_REG(hw, TARC0, tarc);
1321 tarc = E1000_READ_REG(hw, TARC1);
1322 tarc |= (1 << 25);
1323 if (tctl & E1000_TCTL_MULR)
1324 tarc &= ~(1 << 28);
1325 else
1326 tarc |= (1 << 28);
1327 E1000_WRITE_REG(hw, TARC1, tarc);
1328 }
1329
581d708e 1330 e1000_config_collision_dist(hw);
1da177e4
LT		 1331
1332 /* Setup Transmit Descriptor Settings for eop descriptor */
1333 adapter->txd_cmd = E1000_TXD_CMD_IDE | E1000_TXD_CMD_EOP |
1334 E1000_TXD_CMD_IFCS;
1335
581d708e 1336 if (hw->mac_type < e1000_82543)
1da177e4
LT		 1337 adapter->txd_cmd |= E1000_TXD_CMD_RPS;
1338 else
1339 adapter->txd_cmd |= E1000_TXD_CMD_RS;
1340
1341 /* Cache if we're 82544 running in PCI-X because we'll
1342 * need this to apply a workaround later in the send path. */
581d708e
MC		 1343 if (hw->mac_type == e1000_82544 &&
1344 hw->bus_type == e1000_bus_type_pcix)
1da177e4
LT		 1345 adapter->pcix_82544 = 1;
1346}
1347
1348/**
1349 * e1000_setup_rx_resources - allocate Rx resources (Descriptors)
1350 * @adapter: board private structure
581d708e 1351 * @rxdr: rx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1352 *
1353 * Returns 0 on success, negative on failure
1354 **/
1355
1356int
581d708e
MC		 1357e1000_setup_rx_resources(struct e1000_adapter *adapter,
1358 struct e1000_rx_ring *rxdr)
1da177e4 1359{
1da177e4 1360 struct pci_dev *pdev = adapter->pdev;
2d7edb92 1361 int size, desc_len;
1da177e4
LT		 1362
1363 size = sizeof(struct e1000_buffer) * rxdr->count;
1364 rxdr->buffer_info = vmalloc(size);
581d708e 1365 if (!rxdr->buffer_info) {
2648345f
MC		 1366 DPRINTK(PROBE, ERR,
1367 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4
LT		 1368 return -ENOMEM;
1369 }
1370 memset(rxdr->buffer_info, 0, size);
1371
2d7edb92
MC		 1372 size = sizeof(struct e1000_ps_page) * rxdr->count;
1373 rxdr->ps_page = kmalloc(size, GFP_KERNEL);
1374 if(!rxdr->ps_page) {
1375 vfree(rxdr->buffer_info);
1376 DPRINTK(PROBE, ERR,
1377 "Unable to allocate memory for the receive descriptor ring\n");
1378 return -ENOMEM;
1379 }
1380 memset(rxdr->ps_page, 0, size);
1381
1382 size = sizeof(struct e1000_ps_page_dma) * rxdr->count;
1383 rxdr->ps_page_dma = kmalloc(size, GFP_KERNEL);
1384 if(!rxdr->ps_page_dma) {
1385 vfree(rxdr->buffer_info);
1386 kfree(rxdr->ps_page);
1387 DPRINTK(PROBE, ERR,
1388 "Unable to allocate memory for the receive descriptor ring\n");
1389 return -ENOMEM;
1390 }
1391 memset(rxdr->ps_page_dma, 0, size);
1392
1393 if(adapter->hw.mac_type <= e1000_82547_rev_2)
1394 desc_len = sizeof(struct e1000_rx_desc);
1395 else
1396 desc_len = sizeof(union e1000_rx_desc_packet_split);
1397
1da177e4
LT		 1398 /* Round up to nearest 4K */
1399
2d7edb92 1400 rxdr->size = rxdr->count * desc_len;
1da177e4
LT		 1401 E1000_ROUNDUP(rxdr->size, 4096);
1402
1403 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
1404
581d708e
MC		 1405 if (!rxdr->desc) {
1406 DPRINTK(PROBE, ERR,
1407 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4 1408setup_rx_desc_die:
1da177e4 1409 vfree(rxdr->buffer_info);
2d7edb92
MC		 1410 kfree(rxdr->ps_page);
1411 kfree(rxdr->ps_page_dma);
1da177e4
LT		 1412 return -ENOMEM;
1413 }
1414
2648345f 1415 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1416 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1417 void *olddesc = rxdr->desc;
1418 dma_addr_t olddma = rxdr->dma;
2648345f
MC		 1419 DPRINTK(RX_ERR, ERR, "rxdr align check failed: %u bytes "
1420 "at %p\n", rxdr->size, rxdr->desc);
1421 /* Try again, without freeing the previous */
1da177e4 1422 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
2648345f 1423 /* Failed allocation, critical failure */
581d708e 1424 if (!rxdr->desc) {
1da177e4 1425 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
581d708e
MC		 1426 DPRINTK(PROBE, ERR,
1427 "Unable to allocate memory "
1428 "for the receive descriptor ring\n");
1da177e4
LT		 1429 goto setup_rx_desc_die;
1430 }
1431
1432 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1433 /* give up */
2648345f
MC		 1434 pci_free_consistent(pdev, rxdr->size, rxdr->desc,
1435 rxdr->dma);
1da177e4 1436 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
2648345f
MC		 1437 DPRINTK(PROBE, ERR,
1438 "Unable to allocate aligned memory "
1439 "for the receive descriptor ring\n");
581d708e 1440 goto setup_rx_desc_die;
1da177e4 1441 } else {
2648345f 1442 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1443 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
1444 }
1445 }
1446 memset(rxdr->desc, 0, rxdr->size);
1447
1448 rxdr->next_to_clean = 0;
1449 rxdr->next_to_use = 0;
1450
1451 return 0;
1452}
1453
581d708e
MC		 1454/**
1455 * e1000_setup_all_rx_resources - wrapper to allocate Rx resources
1456 * (Descriptors) for all queues
1457 * @adapter: board private structure
1458 *
1459 * If this function returns with an error, then it's possible one or
1460 * more of the rings is populated (while the rest are not). It is the
1461 * callers duty to clean those orphaned rings.
1462 *
1463 * Return 0 on success, negative on failure
1464 **/
1465
1466int
1467e1000_setup_all_rx_resources(struct e1000_adapter *adapter)
1468{
1469 int i, err = 0;
1470
1471 for (i = 0; i < adapter->num_queues; i++) {
1472 err = e1000_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1473 if (err) {
1474 DPRINTK(PROBE, ERR,
1475 "Allocation for Rx Queue %u failed\n", i);
1476 break;
1477 }
1478 }
1479
1480 return err;
1481}
1482
1da177e4 1483/**
2648345f 1484 * e1000_setup_rctl - configure the receive control registers
1da177e4
LT		 1485 * @adapter: Board private structure
1486 **/
1487
1488static void
1489e1000_setup_rctl(struct e1000_adapter *adapter)
1490{
2d7edb92
MC		 1491 uint32_t rctl, rfctl;
1492 uint32_t psrctl = 0;
1da177e4
LT		 1493
1494 rctl = E1000_READ_REG(&adapter->hw, RCTL);
1495
1496 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1497
1498 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1499 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1500 (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
1501
1502 if(adapter->hw.tbi_compatibility_on == 1)
1503 rctl |= E1000_RCTL_SBP;
1504 else
1505 rctl &= ~E1000_RCTL_SBP;
1506
2d7edb92
MC		 1507 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1508 rctl &= ~E1000_RCTL_LPE;
1509 else
1510 rctl |= E1000_RCTL_LPE;
1511
1da177e4 1512 /* Setup buffer sizes */
868d5309 1513 if(adapter->hw.mac_type >= e1000_82571) {
2d7edb92
MC		 1514 /* We can now specify buffers in 1K increments.
1515 * BSIZE and BSEX are ignored in this case. */
1516 rctl |= adapter->rx_buffer_len << 0x11;
1517 } else {
1518 rctl &= ~E1000_RCTL_SZ_4096;
1519 rctl |= E1000_RCTL_BSEX;
1520 switch (adapter->rx_buffer_len) {
1521 case E1000_RXBUFFER_2048:
1522 default:
1523 rctl |= E1000_RCTL_SZ_2048;
1524 rctl &= ~E1000_RCTL_BSEX;
1525 break;
1526 case E1000_RXBUFFER_4096:
1527 rctl |= E1000_RCTL_SZ_4096;
1528 break;
1529 case E1000_RXBUFFER_8192:
1530 rctl |= E1000_RCTL_SZ_8192;
1531 break;
1532 case E1000_RXBUFFER_16384:
1533 rctl |= E1000_RCTL_SZ_16384;
1534 break;
1535 }
1536 }
1537
1538#ifdef CONFIG_E1000_PACKET_SPLIT
1539 /* 82571 and greater support packet-split where the protocol
1540 * header is placed in skb->data and the packet data is
1541 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1542 * In the case of a non-split, skb->data is linearly filled,
1543 * followed by the page buffers. Therefore, skb->data is
1544 * sized to hold the largest protocol header.
1545 */
1546 adapter->rx_ps = (adapter->hw.mac_type > e1000_82547_rev_2)
1547 && (adapter->netdev->mtu
1548 < ((3 * PAGE_SIZE) + adapter->rx_ps_bsize0));
1549#endif
1550 if(adapter->rx_ps) {
1551 /* Configure extra packet-split registers */
1552 rfctl = E1000_READ_REG(&adapter->hw, RFCTL);
1553 rfctl |= E1000_RFCTL_EXTEN;
1554 /* disable IPv6 packet split support */
1555 rfctl |= E1000_RFCTL_IPV6_DIS;
1556 E1000_WRITE_REG(&adapter->hw, RFCTL, rfctl);
1557
1558 rctl |= E1000_RCTL_DTYP_PS | E1000_RCTL_SECRC;
1559
1560 psrctl |= adapter->rx_ps_bsize0 >>
1561 E1000_PSRCTL_BSIZE0_SHIFT;
1562 psrctl |= PAGE_SIZE >>
1563 E1000_PSRCTL_BSIZE1_SHIFT;
1564 psrctl |= PAGE_SIZE <<
1565 E1000_PSRCTL_BSIZE2_SHIFT;
1566 psrctl |= PAGE_SIZE <<
1567 E1000_PSRCTL_BSIZE3_SHIFT;
1568
1569 E1000_WRITE_REG(&adapter->hw, PSRCTL, psrctl);
1da177e4
LT		 1570 }
1571
1572 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1573}
1574
1575/**
1576 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
1577 * @adapter: board private structure
1578 *
1579 * Configure the Rx unit of the MAC after a reset.
1580 **/
1581
1582static void
1583e1000_configure_rx(struct e1000_adapter *adapter)
1584{
581d708e
MC		 1585 uint64_t rdba;
1586 struct e1000_hw *hw = &adapter->hw;
1587 uint32_t rdlen, rctl, rxcsum, ctrl_ext;
1588#ifdef CONFIG_E1000_MQ
1589 uint32_t reta, mrqc;
1590 int i;
1591#endif
2d7edb92
MC		 1592
1593 if(adapter->rx_ps) {
581d708e 1594 rdlen = adapter->rx_ring[0].count *
2d7edb92
MC		 1595 sizeof(union e1000_rx_desc_packet_split);
1596 adapter->clean_rx = e1000_clean_rx_irq_ps;
1597 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
1598 } else {
581d708e
MC		 1599 rdlen = adapter->rx_ring[0].count *
1600 sizeof(struct e1000_rx_desc);
2d7edb92
MC		 1601 adapter->clean_rx = e1000_clean_rx_irq;
1602 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
1603 }
1da177e4
LT		 1604
1605 /* disable receives while setting up the descriptors */
581d708e
MC		 1606 rctl = E1000_READ_REG(hw, RCTL);
1607 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
1da177e4
LT		 1608
1609 /* set the Receive Delay Timer Register */
581d708e 1610 E1000_WRITE_REG(hw, RDTR, adapter->rx_int_delay);
1da177e4 1611
581d708e
MC		 1612 if (hw->mac_type >= e1000_82540) {
1613 E1000_WRITE_REG(hw, RADV, adapter->rx_abs_int_delay);
1da177e4 1614 if(adapter->itr > 1)
581d708e 1615 E1000_WRITE_REG(hw, ITR,
1da177e4
LT		 1616 1000000000 / (adapter->itr * 256));
1617 }
1618
2ae76d98
MC		 1619 if (hw->mac_type >= e1000_82571) {
1620 /* Reset delay timers after every interrupt */
1621 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1622 ctrl_ext |= E1000_CTRL_EXT_CANC;
1623 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1624 E1000_WRITE_FLUSH(hw);
1625 }
1626
581d708e
MC		 1627 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1628 * the Base and Length of the Rx Descriptor Ring */
24025e4e
MC		 1629 switch (adapter->num_queues) {
1630#ifdef CONFIG_E1000_MQ
1631 case 2:
1632 rdba = adapter->rx_ring[1].dma;
1633 E1000_WRITE_REG(hw, RDBAL1, (rdba & 0x00000000ffffffffULL));
1634 E1000_WRITE_REG(hw, RDBAH1, (rdba >> 32));
1635 E1000_WRITE_REG(hw, RDLEN1, rdlen);
1636 E1000_WRITE_REG(hw, RDH1, 0);
1637 E1000_WRITE_REG(hw, RDT1, 0);
1638 adapter->rx_ring[1].rdh = E1000_RDH1;
1639 adapter->rx_ring[1].rdt = E1000_RDT1;
1640 /* Fall Through */
1641#endif
1642 case 1:
1643 default:
581d708e
MC		 1644 rdba = adapter->rx_ring[0].dma;
1645 E1000_WRITE_REG(hw, RDBAL, (rdba & 0x00000000ffffffffULL));
1646 E1000_WRITE_REG(hw, RDBAH, (rdba >> 32));
1647 E1000_WRITE_REG(hw, RDLEN, rdlen);
1648 E1000_WRITE_REG(hw, RDH, 0);
1649 E1000_WRITE_REG(hw, RDT, 0);
1650 adapter->rx_ring[0].rdh = E1000_RDH;
1651 adapter->rx_ring[0].rdt = E1000_RDT;
1652 break;
24025e4e
MC		 1653 }
1654
1655#ifdef CONFIG_E1000_MQ
1656 if (adapter->num_queues > 1) {
1657 uint32_t random[10];
1658
1659 get_random_bytes(&random[0], 40);
1660
1661 if (hw->mac_type <= e1000_82572) {
1662 E1000_WRITE_REG(hw, RSSIR, 0);
1663 E1000_WRITE_REG(hw, RSSIM, 0);
1664 }
1665
1666 switch (adapter->num_queues) {
1667 case 2:
1668 default:
1669 reta = 0x00800080;
1670 mrqc = E1000_MRQC_ENABLE_RSS_2Q;
1671 break;
1672 }
1673
1674 /* Fill out redirection table */
1675 for (i = 0; i < 32; i++)
1676 E1000_WRITE_REG_ARRAY(hw, RETA, i, reta);
1677 /* Fill out hash function seeds */
1678 for (i = 0; i < 10; i++)
1679 E1000_WRITE_REG_ARRAY(hw, RSSRK, i, random[i]);
1680
1681 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1682 E1000_MRQC_RSS_FIELD_IPV4_TCP);
1683 E1000_WRITE_REG(hw, MRQC, mrqc);
1684 }
1685
1686 /* Multiqueue and packet checksumming are mutually exclusive. */
1687 if (hw->mac_type >= e1000_82571) {
1688 rxcsum = E1000_READ_REG(hw, RXCSUM);
1689 rxcsum |= E1000_RXCSUM_PCSD;
1690 E1000_WRITE_REG(hw, RXCSUM, rxcsum);
1691 }
1692
1693#else
1da177e4
LT		 1694
1695 /* Enable 82543 Receive Checksum Offload for TCP and UDP */
581d708e
MC		 1696 if (hw->mac_type >= e1000_82543) {
1697 rxcsum = E1000_READ_REG(hw, RXCSUM);
2d7edb92
MC		 1698 if(adapter->rx_csum == TRUE) {
1699 rxcsum |= E1000_RXCSUM_TUOFL;
1700
868d5309 1701 /* Enable 82571 IPv4 payload checksum for UDP fragments
2d7edb92
MC		 1702 * Must be used in conjunction with packet-split. */
1703 if((adapter->hw.mac_type > e1000_82547_rev_2) &&
1704 (adapter->rx_ps)) {
1705 rxcsum |= E1000_RXCSUM_IPPCSE;
1706 }
1707 } else {
1708 rxcsum &= ~E1000_RXCSUM_TUOFL;
1709 /* don't need to clear IPPCSE as it defaults to 0 */
1710 }
581d708e 1711 E1000_WRITE_REG(hw, RXCSUM, rxcsum);
1da177e4 1712 }
24025e4e 1713#endif /* CONFIG_E1000_MQ */
1da177e4 1714
581d708e
MC		 1715 if (hw->mac_type == e1000_82573)
1716 E1000_WRITE_REG(hw, ERT, 0x0100);
2d7edb92 1717
1da177e4 1718 /* Enable Receives */
581d708e 1719 E1000_WRITE_REG(hw, RCTL, rctl);
1da177e4
LT		 1720}
1721
1722/**
581d708e 1723 * e1000_free_tx_resources - Free Tx Resources per Queue
1da177e4 1724 * @adapter: board private structure
581d708e 1725 * @tx_ring: Tx descriptor ring for a specific queue
1da177e4
LT		 1726 *
1727 * Free all transmit software resources
1728 **/
1729
1730void
581d708e
MC		 1731e1000_free_tx_resources(struct e1000_adapter *adapter,
1732 struct e1000_tx_ring *tx_ring)
1da177e4
LT		 1733{
1734 struct pci_dev *pdev = adapter->pdev;
1735
581d708e 1736 e1000_clean_tx_ring(adapter, tx_ring);
1da177e4 1737
581d708e
MC		 1738 vfree(tx_ring->buffer_info);
1739 tx_ring->buffer_info = NULL;
1da177e4 1740
581d708e 1741 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1da177e4 1742
581d708e
MC		 1743 tx_ring->desc = NULL;
1744}
1745
1746/**
1747 * e1000_free_all_tx_resources - Free Tx Resources for All Queues
1748 * @adapter: board private structure
1749 *
1750 * Free all transmit software resources
1751 **/
1752
1753void
1754e1000_free_all_tx_resources(struct e1000_adapter *adapter)
1755{
1756 int i;
1757
1758 for (i = 0; i < adapter->num_queues; i++)
1759 e1000_free_tx_resources(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 1760}
1761
1762static inline void
1763e1000_unmap_and_free_tx_resource(struct e1000_adapter *adapter,
1764 struct e1000_buffer *buffer_info)
1765{
1da177e4 1766 if(buffer_info->dma) {
2648345f
MC		 1767 pci_unmap_page(adapter->pdev,
1768 buffer_info->dma,
1769 buffer_info->length,
1770 PCI_DMA_TODEVICE);
1da177e4
LT		 1771 buffer_info->dma = 0;
1772 }
1773 if(buffer_info->skb) {
1774 dev_kfree_skb_any(buffer_info->skb);
1775 buffer_info->skb = NULL;
1776 }
1777}
1778
1779/**
1780 * e1000_clean_tx_ring - Free Tx Buffers
1781 * @adapter: board private structure
581d708e 1782 * @tx_ring: ring to be cleaned
1da177e4
LT		 1783 **/
1784
1785static void
581d708e
MC		 1786e1000_clean_tx_ring(struct e1000_adapter *adapter,
1787 struct e1000_tx_ring *tx_ring)
1da177e4 1788{
1da177e4
LT		 1789 struct e1000_buffer *buffer_info;
1790 unsigned long size;
1791 unsigned int i;
1792
1793 /* Free all the Tx ring sk_buffs */
1794
581d708e 1795 if (likely(tx_ring->previous_buffer_info.skb != NULL)) {
2648345f 1796 e1000_unmap_and_free_tx_resource(adapter,
581d708e 1797 &tx_ring->previous_buffer_info);
1da177e4
LT		 1798 }
1799
1800 for(i = 0; i < tx_ring->count; i++) {
1801 buffer_info = &tx_ring->buffer_info[i];
1802 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
1803 }
1804
1805 size = sizeof(struct e1000_buffer) * tx_ring->count;
1806 memset(tx_ring->buffer_info, 0, size);
1807
1808 /* Zero out the descriptor ring */
1809
1810 memset(tx_ring->desc, 0, tx_ring->size);
1811
1812 tx_ring->next_to_use = 0;
1813 tx_ring->next_to_clean = 0;
1814
581d708e
MC		 1815 writel(0, adapter->hw.hw_addr + tx_ring->tdh);
1816 writel(0, adapter->hw.hw_addr + tx_ring->tdt);
1817}
1818
1819/**
1820 * e1000_clean_all_tx_rings - Free Tx Buffers for all queues
1821 * @adapter: board private structure
1822 **/
1823
1824static void
1825e1000_clean_all_tx_rings(struct e1000_adapter *adapter)
1826{
1827 int i;
1828
1829 for (i = 0; i < adapter->num_queues; i++)
1830 e1000_clean_tx_ring(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 1831}
1832
1833/**
1834 * e1000_free_rx_resources - Free Rx Resources
1835 * @adapter: board private structure
581d708e 1836 * @rx_ring: ring to clean the resources from
1da177e4
LT		 1837 *
1838 * Free all receive software resources
1839 **/
1840
1841void
581d708e
MC		 1842e1000_free_rx_resources(struct e1000_adapter *adapter,
1843 struct e1000_rx_ring *rx_ring)
1da177e4 1844{
1da177e4
LT		 1845 struct pci_dev *pdev = adapter->pdev;
1846
581d708e 1847 e1000_clean_rx_ring(adapter, rx_ring);
1da177e4
LT		 1848
1849 vfree(rx_ring->buffer_info);
1850 rx_ring->buffer_info = NULL;
2d7edb92
MC		 1851 kfree(rx_ring->ps_page);
1852 rx_ring->ps_page = NULL;
1853 kfree(rx_ring->ps_page_dma);
1854 rx_ring->ps_page_dma = NULL;
1da177e4
LT		 1855
1856 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1857
1858 rx_ring->desc = NULL;
1859}
1860
1861/**
581d708e 1862 * e1000_free_all_rx_resources - Free Rx Resources for All Queues
1da177e4 1863 * @adapter: board private structure
581d708e
MC		 1864 *
1865 * Free all receive software resources
1866 **/
1867
1868void
1869e1000_free_all_rx_resources(struct e1000_adapter *adapter)
1870{
1871 int i;
1872
1873 for (i = 0; i < adapter->num_queues; i++)
1874 e1000_free_rx_resources(adapter, &adapter->rx_ring[i]);
1875}
1876
1877/**
1878 * e1000_clean_rx_ring - Free Rx Buffers per Queue
1879 * @adapter: board private structure
1880 * @rx_ring: ring to free buffers from
1da177e4
LT		 1881 **/
1882
1883static void
581d708e
MC		 1884e1000_clean_rx_ring(struct e1000_adapter *adapter,
1885 struct e1000_rx_ring *rx_ring)
1da177e4 1886{
1da177e4 1887 struct e1000_buffer *buffer_info;
2d7edb92
MC		 1888 struct e1000_ps_page *ps_page;
1889 struct e1000_ps_page_dma *ps_page_dma;
1da177e4
LT		 1890 struct pci_dev *pdev = adapter->pdev;
1891 unsigned long size;
2d7edb92 1892 unsigned int i, j;
1da177e4
LT		 1893
1894 /* Free all the Rx ring sk_buffs */
1895
1896 for(i = 0; i < rx_ring->count; i++) {
1897 buffer_info = &rx_ring->buffer_info[i];
1898 if(buffer_info->skb) {
2d7edb92
MC		 1899 ps_page = &rx_ring->ps_page[i];
1900 ps_page_dma = &rx_ring->ps_page_dma[i];
1da177e4
LT		 1901 pci_unmap_single(pdev,
1902 buffer_info->dma,
1903 buffer_info->length,
1904 PCI_DMA_FROMDEVICE);
1905
1906 dev_kfree_skb(buffer_info->skb);
1907 buffer_info->skb = NULL;
2d7edb92
MC		 1908
1909 for(j = 0; j < PS_PAGE_BUFFERS; j++) {
1910 if(!ps_page->ps_page[j]) break;
1911 pci_unmap_single(pdev,
1912 ps_page_dma->ps_page_dma[j],
1913 PAGE_SIZE, PCI_DMA_FROMDEVICE);
1914 ps_page_dma->ps_page_dma[j] = 0;
1915 put_page(ps_page->ps_page[j]);
1916 ps_page->ps_page[j] = NULL;
1917 }
1da177e4
LT		 1918 }
1919 }
1920
1921 size = sizeof(struct e1000_buffer) * rx_ring->count;
1922 memset(rx_ring->buffer_info, 0, size);
2d7edb92
MC		 1923 size = sizeof(struct e1000_ps_page) * rx_ring->count;
1924 memset(rx_ring->ps_page, 0, size);
1925 size = sizeof(struct e1000_ps_page_dma) * rx_ring->count;
1926 memset(rx_ring->ps_page_dma, 0, size);
1da177e4
LT		 1927
1928 /* Zero out the descriptor ring */
1929
1930 memset(rx_ring->desc, 0, rx_ring->size);
1931
1932 rx_ring->next_to_clean = 0;
1933 rx_ring->next_to_use = 0;
1934
581d708e
MC		 1935 writel(0, adapter->hw.hw_addr + rx_ring->rdh);
1936 writel(0, adapter->hw.hw_addr + rx_ring->rdt);
1937}
1938
1939/**
1940 * e1000_clean_all_rx_rings - Free Rx Buffers for all queues
1941 * @adapter: board private structure
1942 **/
1943
1944static void
1945e1000_clean_all_rx_rings(struct e1000_adapter *adapter)
1946{
1947 int i;
1948
1949 for (i = 0; i < adapter->num_queues; i++)
1950 e1000_clean_rx_ring(adapter, &adapter->rx_ring[i]);
1da177e4
LT		 1951}
1952
1953/* The 82542 2.0 (revision 2) needs to have the receive unit in reset
1954 * and memory write and invalidate disabled for certain operations
1955 */
1956static void
1957e1000_enter_82542_rst(struct e1000_adapter *adapter)
1958{
1959 struct net_device *netdev = adapter->netdev;
1960 uint32_t rctl;
1961
1962 e1000_pci_clear_mwi(&adapter->hw);
1963
1964 rctl = E1000_READ_REG(&adapter->hw, RCTL);
1965 rctl |= E1000_RCTL_RST;
1966 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1967 E1000_WRITE_FLUSH(&adapter->hw);
1968 mdelay(5);
1969
1970 if(netif_running(netdev))
581d708e 1971 e1000_clean_all_rx_rings(adapter);
1da177e4
LT		 1972}
1973
1974static void
1975e1000_leave_82542_rst(struct e1000_adapter *adapter)
1976{
1977 struct net_device *netdev = adapter->netdev;
1978 uint32_t rctl;
1979
1980 rctl = E1000_READ_REG(&adapter->hw, RCTL);
1981 rctl &= ~E1000_RCTL_RST;
1982 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1983 E1000_WRITE_FLUSH(&adapter->hw);
1984 mdelay(5);
1985
1986 if(adapter->hw.pci_cmd_word & PCI_COMMAND_INVALIDATE)
1987 e1000_pci_set_mwi(&adapter->hw);
1988
1989 if(netif_running(netdev)) {
1990 e1000_configure_rx(adapter);
581d708e 1991 e1000_alloc_rx_buffers(adapter, &adapter->rx_ring[0]);
1da177e4
LT		 1992 }
1993}
1994
1995/**
1996 * e1000_set_mac - Change the Ethernet Address of the NIC
1997 * @netdev: network interface device structure
1998 * @p: pointer to an address structure
1999 *
2000 * Returns 0 on success, negative on failure
2001 **/
2002
2003static int
2004e1000_set_mac(struct net_device *netdev, void *p)
2005{
60490fe0 2006 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2007 struct sockaddr *addr = p;
2008
2009 if(!is_valid_ether_addr(addr->sa_data))
2010 return -EADDRNOTAVAIL;
2011
2012 /* 82542 2.0 needs to be in reset to write receive address registers */
2013
2014 if(adapter->hw.mac_type == e1000_82542_rev2_0)
2015 e1000_enter_82542_rst(adapter);
2016
2017 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2018 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
2019
2020 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2021
868d5309
MC		 2022 /* With 82571 controllers, LAA may be overwritten (with the default)
2023 * due to controller reset from the other port. */
2024 if (adapter->hw.mac_type == e1000_82571) {
2025 /* activate the work around */
2026 adapter->hw.laa_is_present = 1;
2027
2028 /* Hold a copy of the LAA in RAR[14] This is done so that
2029 * between the time RAR[0] gets clobbered and the time it
2030 * gets fixed (in e1000_watchdog), the actual LAA is in one
2031 * of the RARs and no incoming packets directed to this port
2032 * are dropped. Eventaully the LAA will be in RAR[0] and
2033 * RAR[14] */
2034 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr,
2035 E1000_RAR_ENTRIES - 1);
2036 }
2037
1da177e4
LT		 2038 if(adapter->hw.mac_type == e1000_82542_rev2_0)
2039 e1000_leave_82542_rst(adapter);
2040
2041 return 0;
2042}
2043
2044/**
2045 * e1000_set_multi - Multicast and Promiscuous mode set
2046 * @netdev: network interface device structure
2047 *
2048 * The set_multi entry point is called whenever the multicast address
2049 * list or the network interface flags are updated. This routine is
2050 * responsible for configuring the hardware for proper multicast,
2051 * promiscuous mode, and all-multi behavior.
2052 **/
2053
2054static void
2055e1000_set_multi(struct net_device *netdev)
2056{
60490fe0 2057 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2058 struct e1000_hw *hw = &adapter->hw;
2059 struct dev_mc_list *mc_ptr;
2060 uint32_t rctl;
2061 uint32_t hash_value;
868d5309 2062 int i, rar_entries = E1000_RAR_ENTRIES;
1da177e4 2063
868d5309
MC		 2064 /* reserve RAR[14] for LAA over-write work-around */
2065 if (adapter->hw.mac_type == e1000_82571)
2066 rar_entries--;
1da177e4 2067
2648345f
MC		 2068 /* Check for Promiscuous and All Multicast modes */
2069
1da177e4
LT		 2070 rctl = E1000_READ_REG(hw, RCTL);
2071
2072 if(netdev->flags & IFF_PROMISC) {
2073 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2074 } else if(netdev->flags & IFF_ALLMULTI) {
2075 rctl |= E1000_RCTL_MPE;
2076 rctl &= ~E1000_RCTL_UPE;
2077 } else {
2078 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2079 }
2080
2081 E1000_WRITE_REG(hw, RCTL, rctl);
2082
2083 /* 82542 2.0 needs to be in reset to write receive address registers */
2084
2085 if(hw->mac_type == e1000_82542_rev2_0)
2086 e1000_enter_82542_rst(adapter);
2087
2088 /* load the first 14 multicast address into the exact filters 1-14
2089 * RAR 0 is used for the station MAC adddress
2090 * if there are not 14 addresses, go ahead and clear the filters
868d5309 2091 * -- with 82571 controllers only 0-13 entries are filled here
1da177e4
LT		 2092 */
2093 mc_ptr = netdev->mc_list;
2094
868d5309
MC		 2095 for(i = 1; i < rar_entries; i++) {
2096 if (mc_ptr) {
1da177e4
LT		 2097 e1000_rar_set(hw, mc_ptr->dmi_addr, i);
2098 mc_ptr = mc_ptr->next;
2099 } else {
2100 E1000_WRITE_REG_ARRAY(hw, RA, i << 1, 0);
2101 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1) + 1, 0);
2102 }
2103 }
2104
2105 /* clear the old settings from the multicast hash table */
2106
2107 for(i = 0; i < E1000_NUM_MTA_REGISTERS; i++)
2108 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
2109
2110 /* load any remaining addresses into the hash table */
2111
2112 for(; mc_ptr; mc_ptr = mc_ptr->next) {
2113 hash_value = e1000_hash_mc_addr(hw, mc_ptr->dmi_addr);
2114 e1000_mta_set(hw, hash_value);
2115 }
2116
2117 if(hw->mac_type == e1000_82542_rev2_0)
2118 e1000_leave_82542_rst(adapter);
1da177e4
LT		 2119}
2120
2121/* Need to wait a few seconds after link up to get diagnostic information from
2122 * the phy */
2123
2124static void
2125e1000_update_phy_info(unsigned long data)
2126{
2127 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2128 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
2129}
2130
2131/**
2132 * e1000_82547_tx_fifo_stall - Timer Call-back
2133 * @data: pointer to adapter cast into an unsigned long
2134 **/
2135
2136static void
2137e1000_82547_tx_fifo_stall(unsigned long data)
2138{
2139 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2140 struct net_device *netdev = adapter->netdev;
2141 uint32_t tctl;
2142
2143 if(atomic_read(&adapter->tx_fifo_stall)) {
2144 if((E1000_READ_REG(&adapter->hw, TDT) ==
2145 E1000_READ_REG(&adapter->hw, TDH)) &&
2146 (E1000_READ_REG(&adapter->hw, TDFT) ==
2147 E1000_READ_REG(&adapter->hw, TDFH)) &&
2148 (E1000_READ_REG(&adapter->hw, TDFTS) ==
2149 E1000_READ_REG(&adapter->hw, TDFHS))) {
2150 tctl = E1000_READ_REG(&adapter->hw, TCTL);
2151 E1000_WRITE_REG(&adapter->hw, TCTL,
2152 tctl & ~E1000_TCTL_EN);
2153 E1000_WRITE_REG(&adapter->hw, TDFT,
2154 adapter->tx_head_addr);
2155 E1000_WRITE_REG(&adapter->hw, TDFH,
2156 adapter->tx_head_addr);
2157 E1000_WRITE_REG(&adapter->hw, TDFTS,
2158 adapter->tx_head_addr);
2159 E1000_WRITE_REG(&adapter->hw, TDFHS,
2160 adapter->tx_head_addr);
2161 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
2162 E1000_WRITE_FLUSH(&adapter->hw);
2163
2164 adapter->tx_fifo_head = 0;
2165 atomic_set(&adapter->tx_fifo_stall, 0);
2166 netif_wake_queue(netdev);
2167 } else {
2168 mod_timer(&adapter->tx_fifo_stall_timer, jiffies + 1);
2169 }
2170 }
2171}
2172
2173/**
2174 * e1000_watchdog - Timer Call-back
2175 * @data: pointer to adapter cast into an unsigned long
2176 **/
2177static void
2178e1000_watchdog(unsigned long data)
2179{
2180 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2181
2182 /* Do the rest outside of interrupt context */
2183 schedule_work(&adapter->watchdog_task);
2184}
2185
2186static void
2187e1000_watchdog_task(struct e1000_adapter *adapter)
2188{
2189 struct net_device *netdev = adapter->netdev;
581d708e 2190 struct e1000_tx_ring *txdr = &adapter->tx_ring[0];
1da177e4
LT		 2191 uint32_t link;
2192
2193 e1000_check_for_link(&adapter->hw);
2d7edb92
MC		 2194 if (adapter->hw.mac_type == e1000_82573) {
2195 e1000_enable_tx_pkt_filtering(&adapter->hw);
2196 if(adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)
2197 e1000_update_mng_vlan(adapter);
2198 }
1da177e4
LT		 2199
2200 if((adapter->hw.media_type == e1000_media_type_internal_serdes) &&
2201 !(E1000_READ_REG(&adapter->hw, TXCW) & E1000_TXCW_ANE))
2202 link = !adapter->hw.serdes_link_down;
2203 else
2204 link = E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU;
2205
2206 if(link) {
2207 if(!netif_carrier_ok(netdev)) {
2208 e1000_get_speed_and_duplex(&adapter->hw,
2209 &adapter->link_speed,
2210 &adapter->link_duplex);
2211
2212 DPRINTK(LINK, INFO, "NIC Link is Up %d Mbps %s\n",
2213 adapter->link_speed,
2214 adapter->link_duplex == FULL_DUPLEX ?
2215 "Full Duplex" : "Half Duplex");
2216
2217 netif_carrier_on(netdev);
2218 netif_wake_queue(netdev);
2219 mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
2220 adapter->smartspeed = 0;
2221 }
2222 } else {
2223 if(netif_carrier_ok(netdev)) {
2224 adapter->link_speed = 0;
2225 adapter->link_duplex = 0;
2226 DPRINTK(LINK, INFO, "NIC Link is Down\n");
2227 netif_carrier_off(netdev);
2228 netif_stop_queue(netdev);
2229 mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
2230 }
2231
2232 e1000_smartspeed(adapter);
2233 }
2234
2235 e1000_update_stats(adapter);
2236
2237 adapter->hw.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2238 adapter->tpt_old = adapter->stats.tpt;
2239 adapter->hw.collision_delta = adapter->stats.colc - adapter->colc_old;
2240 adapter->colc_old = adapter->stats.colc;
2241
2242 adapter->gorcl = adapter->stats.gorcl - adapter->gorcl_old;
2243 adapter->gorcl_old = adapter->stats.gorcl;
2244 adapter->gotcl = adapter->stats.gotcl - adapter->gotcl_old;
2245 adapter->gotcl_old = adapter->stats.gotcl;
2246
2247 e1000_update_adaptive(&adapter->hw);
2248
581d708e
MC		 2249 if (adapter->num_queues == 1 && !netif_carrier_ok(netdev)) {
2250 if (E1000_DESC_UNUSED(txdr) + 1 < txdr->count) {
1da177e4
LT		 2251 /* We've lost link, so the controller stops DMA,
2252 * but we've got queued Tx work that's never going
2253 * to get done, so reset controller to flush Tx.
2254 * (Do the reset outside of interrupt context). */
2255 schedule_work(&adapter->tx_timeout_task);
2256 }
2257 }
2258
2259 /* Dynamic mode for Interrupt Throttle Rate (ITR) */
2260 if(adapter->hw.mac_type >= e1000_82540 && adapter->itr == 1) {
2261 /* Symmetric Tx/Rx gets a reduced ITR=2000; Total
2262 * asymmetrical Tx or Rx gets ITR=8000; everyone
2263 * else is between 2000-8000. */
2264 uint32_t goc = (adapter->gotcl + adapter->gorcl) / 10000;
2265 uint32_t dif = (adapter->gotcl > adapter->gorcl ?
2266 adapter->gotcl - adapter->gorcl :
2267 adapter->gorcl - adapter->gotcl) / 10000;
2268 uint32_t itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
2269 E1000_WRITE_REG(&adapter->hw, ITR, 1000000000 / (itr * 256));
2270 }
2271
2272 /* Cause software interrupt to ensure rx ring is cleaned */
2273 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_RXDMT0);
2274
2648345f 2275 /* Force detection of hung controller every watchdog period */
1da177e4
LT		 2276 adapter->detect_tx_hung = TRUE;
2277
868d5309
MC		 2278 /* With 82571 controllers, LAA may be overwritten due to controller
2279 * reset from the other port. Set the appropriate LAA in RAR[0] */
2280 if (adapter->hw.mac_type == e1000_82571 && adapter->hw.laa_is_present)
2281 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2282
1da177e4
LT		 2283 /* Reset the timer */
2284 mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
2285}
2286
2287#define E1000_TX_FLAGS_CSUM 0x00000001
2288#define E1000_TX_FLAGS_VLAN 0x00000002
2289#define E1000_TX_FLAGS_TSO 0x00000004
2d7edb92 2290#define E1000_TX_FLAGS_IPV4 0x00000008
1da177e4
LT		 2291#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
2292#define E1000_TX_FLAGS_VLAN_SHIFT 16
2293
2294static inline int
581d708e
MC		 2295e1000_tso(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2296 struct sk_buff *skb)
1da177e4
LT		 2297{
2298#ifdef NETIF_F_TSO
2299 struct e1000_context_desc *context_desc;
2300 unsigned int i;
2301 uint32_t cmd_length = 0;
2d7edb92 2302 uint16_t ipcse = 0, tucse, mss;
1da177e4
LT		 2303 uint8_t ipcss, ipcso, tucss, tucso, hdr_len;
2304 int err;
2305
2306 if(skb_shinfo(skb)->tso_size) {
2307 if (skb_header_cloned(skb)) {
2308 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2309 if (err)
2310 return err;
2311 }
2312
2313 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
2314 mss = skb_shinfo(skb)->tso_size;
2d7edb92
MC		 2315 if(skb->protocol == ntohs(ETH_P_IP)) {
2316 skb->nh.iph->tot_len = 0;
2317 skb->nh.iph->check = 0;
2318 skb->h.th->check =
2319 ~csum_tcpudp_magic(skb->nh.iph->saddr,
2320 skb->nh.iph->daddr,
2321 0,
2322 IPPROTO_TCP,
2323 0);
2324 cmd_length = E1000_TXD_CMD_IP;
2325 ipcse = skb->h.raw - skb->data - 1;
2326#ifdef NETIF_F_TSO_IPV6
2327 } else if(skb->protocol == ntohs(ETH_P_IPV6)) {
2328 skb->nh.ipv6h->payload_len = 0;
2329 skb->h.th->check =
2330 ~csum_ipv6_magic(&skb->nh.ipv6h->saddr,
2331 &skb->nh.ipv6h->daddr,
2332 0,
2333 IPPROTO_TCP,
2334 0);
2335 ipcse = 0;
2336#endif
2337 }
1da177e4
LT		 2338 ipcss = skb->nh.raw - skb->data;
2339 ipcso = (void *)&(skb->nh.iph->check) - (void *)skb->data;
1da177e4
LT		 2340 tucss = skb->h.raw - skb->data;
2341 tucso = (void *)&(skb->h.th->check) - (void *)skb->data;
2342 tucse = 0;
2343
2344 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
2d7edb92 2345 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
1da177e4 2346
581d708e
MC		 2347 i = tx_ring->next_to_use;
2348 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
1da177e4
LT		 2349
2350 context_desc->lower_setup.ip_fields.ipcss = ipcss;
2351 context_desc->lower_setup.ip_fields.ipcso = ipcso;
2352 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
2353 context_desc->upper_setup.tcp_fields.tucss = tucss;
2354 context_desc->upper_setup.tcp_fields.tucso = tucso;
2355 context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse);
2356 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
2357 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
2358 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
2359
581d708e
MC		 2360 if (++i == tx_ring->count) i = 0;
2361 tx_ring->next_to_use = i;
1da177e4
LT		 2362
2363 return 1;
2364 }
2365#endif
2366
2367 return 0;
2368}
2369
2370static inline boolean_t
581d708e
MC		 2371e1000_tx_csum(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2372 struct sk_buff *skb)
1da177e4
LT		 2373{
2374 struct e1000_context_desc *context_desc;
2375 unsigned int i;
2376 uint8_t css;
2377
2378 if(likely(skb->ip_summed == CHECKSUM_HW)) {
2379 css = skb->h.raw - skb->data;
2380
581d708e
MC		 2381 i = tx_ring->next_to_use;
2382 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
1da177e4
LT		 2383
2384 context_desc->upper_setup.tcp_fields.tucss = css;
2385 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum;
2386 context_desc->upper_setup.tcp_fields.tucse = 0;
2387 context_desc->tcp_seg_setup.data = 0;
2388 context_desc->cmd_and_length = cpu_to_le32(E1000_TXD_CMD_DEXT);
2389
581d708e
MC		 2390 if (unlikely(++i == tx_ring->count)) i = 0;
2391 tx_ring->next_to_use = i;
1da177e4
LT		 2392
2393 return TRUE;
2394 }
2395
2396 return FALSE;
2397}
2398
2399#define E1000_MAX_TXD_PWR 12
2400#define E1000_MAX_DATA_PER_TXD (1<<E1000_MAX_TXD_PWR)
2401
2402static inline int
581d708e
MC		 2403e1000_tx_map(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2404 struct sk_buff *skb, unsigned int first, unsigned int max_per_txd,
2405 unsigned int nr_frags, unsigned int mss)
1da177e4 2406{
1da177e4
LT		 2407 struct e1000_buffer *buffer_info;
2408 unsigned int len = skb->len;
2409 unsigned int offset = 0, size, count = 0, i;
2410 unsigned int f;
2411 len -= skb->data_len;
2412
2413 i = tx_ring->next_to_use;
2414
2415 while(len) {
2416 buffer_info = &tx_ring->buffer_info[i];
2417 size = min(len, max_per_txd);
2418#ifdef NETIF_F_TSO
2419 /* Workaround for premature desc write-backs
2420 * in TSO mode. Append 4-byte sentinel desc */
2421 if(unlikely(mss && !nr_frags && size == len && size > 8))
2422 size -= 4;
2423#endif
97338bde
MC		 2424 /* work-around for errata 10 and it applies
2425 * to all controllers in PCI-X mode
2426 * The fix is to make sure that the first descriptor of a
2427 * packet is smaller than 2048 - 16 - 16 (or 2016) bytes
2428 */
2429 if(unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
2430 (size > 2015) && count == 0))
2431 size = 2015;
2432
1da177e4
LT		 2433 /* Workaround for potential 82544 hang in PCI-X. Avoid
2434 * terminating buffers within evenly-aligned dwords. */
2435 if(unlikely(adapter->pcix_82544 &&
2436 !((unsigned long)(skb->data + offset + size - 1) & 4) &&
2437 size > 4))
2438 size -= 4;
2439
2440 buffer_info->length = size;
2441 buffer_info->dma =
2442 pci_map_single(adapter->pdev,
2443 skb->data + offset,
2444 size,
2445 PCI_DMA_TODEVICE);
2446 buffer_info->time_stamp = jiffies;
2447
2448 len -= size;
2449 offset += size;
2450 count++;
2451 if(unlikely(++i == tx_ring->count)) i = 0;
2452 }
2453
2454 for(f = 0; f < nr_frags; f++) {
2455 struct skb_frag_struct *frag;
2456
2457 frag = &skb_shinfo(skb)->frags[f];
2458 len = frag->size;
2459 offset = frag->page_offset;
2460
2461 while(len) {
2462 buffer_info = &tx_ring->buffer_info[i];
2463 size = min(len, max_per_txd);
2464#ifdef NETIF_F_TSO
2465 /* Workaround for premature desc write-backs
2466 * in TSO mode. Append 4-byte sentinel desc */
2467 if(unlikely(mss && f == (nr_frags-1) && size == len && size > 8))
2468 size -= 4;
2469#endif
2470 /* Workaround for potential 82544 hang in PCI-X.
2471 * Avoid terminating buffers within evenly-aligned
2472 * dwords. */
2473 if(unlikely(adapter->pcix_82544 &&
2474 !((unsigned long)(frag->page+offset+size-1) & 4) &&
2475 size > 4))
2476 size -= 4;
2477
2478 buffer_info->length = size;
2479 buffer_info->dma =
2480 pci_map_page(adapter->pdev,
2481 frag->page,
2482 offset,
2483 size,
2484 PCI_DMA_TODEVICE);
2485 buffer_info->time_stamp = jiffies;
2486
2487 len -= size;
2488 offset += size;
2489 count++;
2490 if(unlikely(++i == tx_ring->count)) i = 0;
2491 }
2492 }
2493
2494 i = (i == 0) ? tx_ring->count - 1 : i - 1;
2495 tx_ring->buffer_info[i].skb = skb;
2496 tx_ring->buffer_info[first].next_to_watch = i;
2497
2498 return count;
2499}
2500
2501static inline void
581d708e
MC		 2502e1000_tx_queue(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2503 int tx_flags, int count)
1da177e4 2504{
1da177e4
LT		 2505 struct e1000_tx_desc *tx_desc = NULL;
2506 struct e1000_buffer *buffer_info;
2507 uint32_t txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
2508 unsigned int i;
2509
2510 if(likely(tx_flags & E1000_TX_FLAGS_TSO)) {
2511 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
2512 E1000_TXD_CMD_TSE;
2d7edb92
MC		 2513 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2514
2515 if(likely(tx_flags & E1000_TX_FLAGS_IPV4))
2516 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
1da177e4
LT		 2517 }
2518
2519 if(likely(tx_flags & E1000_TX_FLAGS_CSUM)) {
2520 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
2521 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2522 }
2523
2524 if(unlikely(tx_flags & E1000_TX_FLAGS_VLAN)) {
2525 txd_lower |= E1000_TXD_CMD_VLE;
2526 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
2527 }
2528
2529 i = tx_ring->next_to_use;
2530
2531 while(count--) {
2532 buffer_info = &tx_ring->buffer_info[i];
2533 tx_desc = E1000_TX_DESC(*tx_ring, i);
2534 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
2535 tx_desc->lower.data =
2536 cpu_to_le32(txd_lower | buffer_info->length);
2537 tx_desc->upper.data = cpu_to_le32(txd_upper);
2538 if(unlikely(++i == tx_ring->count)) i = 0;
2539 }
2540
2541 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
2542
2543 /* Force memory writes to complete before letting h/w
2544 * know there are new descriptors to fetch. (Only
2545 * applicable for weak-ordered memory model archs,
2546 * such as IA-64). */
2547 wmb();
2548
2549 tx_ring->next_to_use = i;
581d708e 2550 writel(i, adapter->hw.hw_addr + tx_ring->tdt);
1da177e4
LT		 2551}
2552
2553/**
2554 * 82547 workaround to avoid controller hang in half-duplex environment.
2555 * The workaround is to avoid queuing a large packet that would span
2556 * the internal Tx FIFO ring boundary by notifying the stack to resend
2557 * the packet at a later time. This gives the Tx FIFO an opportunity to
2558 * flush all packets. When that occurs, we reset the Tx FIFO pointers
2559 * to the beginning of the Tx FIFO.
2560 **/
2561
2562#define E1000_FIFO_HDR 0x10
2563#define E1000_82547_PAD_LEN 0x3E0
2564
2565static inline int
2566e1000_82547_fifo_workaround(struct e1000_adapter *adapter, struct sk_buff *skb)
2567{
2568 uint32_t fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
2569 uint32_t skb_fifo_len = skb->len + E1000_FIFO_HDR;
2570
2571 E1000_ROUNDUP(skb_fifo_len, E1000_FIFO_HDR);
2572
2573 if(adapter->link_duplex != HALF_DUPLEX)
2574 goto no_fifo_stall_required;
2575
2576 if(atomic_read(&adapter->tx_fifo_stall))
2577 return 1;
2578
2579 if(skb_fifo_len >= (E1000_82547_PAD_LEN + fifo_space)) {
2580 atomic_set(&adapter->tx_fifo_stall, 1);
2581 return 1;
2582 }
2583
2584no_fifo_stall_required:
2585 adapter->tx_fifo_head += skb_fifo_len;
2586 if(adapter->tx_fifo_head >= adapter->tx_fifo_size)
2587 adapter->tx_fifo_head -= adapter->tx_fifo_size;
2588 return 0;
2589}
2590
2d7edb92
MC		 2591#define MINIMUM_DHCP_PACKET_SIZE 282
2592static inline int
2593e1000_transfer_dhcp_info(struct e1000_adapter *adapter, struct sk_buff *skb)
2594{
2595 struct e1000_hw *hw = &adapter->hw;
2596 uint16_t length, offset;
2597 if(vlan_tx_tag_present(skb)) {
2598 if(!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
2599 ( adapter->hw.mng_cookie.status &
2600 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) )
2601 return 0;
2602 }
2603 if(htons(ETH_P_IP) == skb->protocol) {
2604 const struct iphdr *ip = skb->nh.iph;
2605 if(IPPROTO_UDP == ip->protocol) {
2606 struct udphdr *udp = (struct udphdr *)(skb->h.uh);
2607 if(ntohs(udp->dest) == 67) {
2608 offset = (uint8_t *)udp + 8 - skb->data;
2609 length = skb->len - offset;
2610
2611 return e1000_mng_write_dhcp_info(hw,
2612 (uint8_t *)udp + 8, length);
2613 }
2614 }
2615 } else if((skb->len > MINIMUM_DHCP_PACKET_SIZE) && (!skb->protocol)) {
2616 struct ethhdr *eth = (struct ethhdr *) skb->data;
2617 if((htons(ETH_P_IP) == eth->h_proto)) {
2618 const struct iphdr *ip =
2619 (struct iphdr *)((uint8_t *)skb->data+14);
2620 if(IPPROTO_UDP == ip->protocol) {
2621 struct udphdr *udp =
2622 (struct udphdr *)((uint8_t *)ip +
2623 (ip->ihl << 2));
2624 if(ntohs(udp->dest) == 67) {
2625 offset = (uint8_t *)udp + 8 - skb->data;
2626 length = skb->len - offset;
2627
2628 return e1000_mng_write_dhcp_info(hw,
2629 (uint8_t *)udp + 8,
2630 length);
2631 }
2632 }
2633 }
2634 }
2635 return 0;
2636}
2637
1da177e4
LT		 2638#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 )
2639static int
2640e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2641{
60490fe0 2642 struct e1000_adapter *adapter = netdev_priv(netdev);
581d708e 2643 struct e1000_tx_ring *tx_ring;
1da177e4
LT		 2644 unsigned int first, max_per_txd = E1000_MAX_DATA_PER_TXD;
2645 unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
2646 unsigned int tx_flags = 0;
2647 unsigned int len = skb->len;
2648 unsigned long flags;
2649 unsigned int nr_frags = 0;
2650 unsigned int mss = 0;
2651 int count = 0;
2652 int tso;
2653 unsigned int f;
2654 len -= skb->data_len;
2655
24025e4e
MC		 2656#ifdef CONFIG_E1000_MQ
2657 tx_ring = *per_cpu_ptr(adapter->cpu_tx_ring, smp_processor_id());
2658#else
581d708e 2659 tx_ring = adapter->tx_ring;
24025e4e
MC		 2660#endif
2661
581d708e 2662 if (unlikely(skb->len <= 0)) {
1da177e4
LT		 2663 dev_kfree_skb_any(skb);
2664 return NETDEV_TX_OK;
2665 }
2666
2667#ifdef NETIF_F_TSO
2668 mss = skb_shinfo(skb)->tso_size;
2648345f 2669 /* The controller does a simple calculation to
1da177e4
LT		 2670 * make sure there is enough room in the FIFO before
2671 * initiating the DMA for each buffer. The calc is:
2672 * 4 = ceil(buffer len/mss). To make sure we don't
2673 * overrun the FIFO, adjust the max buffer len if mss
2674 * drops. */
2675 if(mss) {
2676 max_per_txd = min(mss << 2, max_per_txd);
2677 max_txd_pwr = fls(max_per_txd) - 1;
2678 }
2679
2680 if((mss) || (skb->ip_summed == CHECKSUM_HW))
2681 count++;
2648345f 2682 count++;
1da177e4
LT		 2683#else
2684 if(skb->ip_summed == CHECKSUM_HW)
2685 count++;
2686#endif
2687 count += TXD_USE_COUNT(len, max_txd_pwr);
2688
2689 if(adapter->pcix_82544)
2690 count++;
2691
97338bde
MC		 2692 /* work-around for errata 10 and it applies to all controllers
2693 * in PCI-X mode, so add one more descriptor to the count
2694 */
2695 if(unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
2696 (len > 2015)))
2697 count++;
2698
1da177e4
LT		 2699 nr_frags = skb_shinfo(skb)->nr_frags;
2700 for(f = 0; f < nr_frags; f++)
2701 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size,
2702 max_txd_pwr);
2703 if(adapter->pcix_82544)
2704 count += nr_frags;
2705
868d5309
MC		 2706#ifdef NETIF_F_TSO
2707 /* TSO Workaround for 82571/2 Controllers -- if skb->data
2708 * points to just header, pull a few bytes of payload from
2709 * frags into skb->data */
2710 if (skb_shinfo(skb)->tso_size) {
2711 uint8_t hdr_len;
2712 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
2713 if (skb->data_len && (hdr_len < (skb->len - skb->data_len)) &&
2714 (adapter->hw.mac_type == e1000_82571 ||
2715 adapter->hw.mac_type == e1000_82572)) {
2716 unsigned int pull_size;
2717 pull_size = min((unsigned int)4, skb->data_len);
2718 if (!__pskb_pull_tail(skb, pull_size)) {
2719 printk(KERN_ERR "__pskb_pull_tail failed.\n");
2720 dev_kfree_skb_any(skb);
2721 return -EFAULT;
2722 }
2723 }
2724 }
2725#endif
2726
2d7edb92
MC		 2727 if(adapter->hw.tx_pkt_filtering && (adapter->hw.mac_type == e1000_82573) )
2728 e1000_transfer_dhcp_info(adapter, skb);
2729
581d708e
MC		 2730 local_irq_save(flags);
2731 if (!spin_trylock(&tx_ring->tx_lock)) {
2732 /* Collision - tell upper layer to requeue */
2733 local_irq_restore(flags);
2734 return NETDEV_TX_LOCKED;
2735 }
1da177e4
LT		 2736
2737 /* need: count + 2 desc gap to keep tail from touching
2738 * head, otherwise try next time */
581d708e 2739 if (unlikely(E1000_DESC_UNUSED(tx_ring) < count + 2)) {
1da177e4 2740 netif_stop_queue(netdev);
581d708e 2741 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2742 return NETDEV_TX_BUSY;
2743 }
2744
2745 if(unlikely(adapter->hw.mac_type == e1000_82547)) {
2746 if(unlikely(e1000_82547_fifo_workaround(adapter, skb))) {
2747 netif_stop_queue(netdev);
2748 mod_timer(&adapter->tx_fifo_stall_timer, jiffies);
581d708e 2749 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2750 return NETDEV_TX_BUSY;
2751 }
2752 }
2753
2754 if(unlikely(adapter->vlgrp && vlan_tx_tag_present(skb))) {
2755 tx_flags |= E1000_TX_FLAGS_VLAN;
2756 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
2757 }
2758
581d708e 2759 first = tx_ring->next_to_use;
1da177e4 2760
581d708e 2761 tso = e1000_tso(adapter, tx_ring, skb);
1da177e4
LT		 2762 if (tso < 0) {
2763 dev_kfree_skb_any(skb);
581d708e 2764 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2765 return NETDEV_TX_OK;
2766 }
2767
2768 if (likely(tso))
2769 tx_flags |= E1000_TX_FLAGS_TSO;
581d708e 2770 else if (likely(e1000_tx_csum(adapter, tx_ring, skb)))
1da177e4
LT		 2771 tx_flags |= E1000_TX_FLAGS_CSUM;
2772
2d7edb92 2773 /* Old method was to assume IPv4 packet by default if TSO was enabled.
868d5309 2774 * 82571 hardware supports TSO capabilities for IPv6 as well...
2d7edb92 2775 * no longer assume, we must. */
581d708e 2776 if (likely(skb->protocol == ntohs(ETH_P_IP)))
2d7edb92
MC		 2777 tx_flags |= E1000_TX_FLAGS_IPV4;
2778
581d708e
MC		 2779 e1000_tx_queue(adapter, tx_ring, tx_flags,
2780 e1000_tx_map(adapter, tx_ring, skb, first,
2781 max_per_txd, nr_frags, mss));
1da177e4
LT		 2782
2783 netdev->trans_start = jiffies;
2784
2785 /* Make sure there is space in the ring for the next send. */
581d708e 2786 if (unlikely(E1000_DESC_UNUSED(tx_ring) < MAX_SKB_FRAGS + 2))
1da177e4
LT		 2787 netif_stop_queue(netdev);
2788
581d708e 2789 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2790 return NETDEV_TX_OK;
2791}
2792
2793/**
2794 * e1000_tx_timeout - Respond to a Tx Hang
2795 * @netdev: network interface device structure
2796 **/
2797
2798static void
2799e1000_tx_timeout(struct net_device *netdev)
2800{
60490fe0 2801 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2802
2803 /* Do the reset outside of interrupt context */
2804 schedule_work(&adapter->tx_timeout_task);
2805}
2806
2807static void
2808e1000_tx_timeout_task(struct net_device *netdev)
2809{
60490fe0 2810 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2811
2812 e1000_down(adapter);
2813 e1000_up(adapter);
2814}
2815
2816/**
2817 * e1000_get_stats - Get System Network Statistics
2818 * @netdev: network interface device structure
2819 *
2820 * Returns the address of the device statistics structure.
2821 * The statistics are actually updated from the timer callback.
2822 **/
2823
2824static struct net_device_stats *
2825e1000_get_stats(struct net_device *netdev)
2826{
60490fe0 2827 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2828
2829 e1000_update_stats(adapter);
2830 return &adapter->net_stats;
2831}
2832
2833/**
2834 * e1000_change_mtu - Change the Maximum Transfer Unit
2835 * @netdev: network interface device structure
2836 * @new_mtu: new value for maximum frame size
2837 *
2838 * Returns 0 on success, negative on failure
2839 **/
2840
2841static int
2842e1000_change_mtu(struct net_device *netdev, int new_mtu)
2843{
60490fe0 2844 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2845 int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
2846
2847 if((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) ||
2848 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
2849 DPRINTK(PROBE, ERR, "Invalid MTU setting\n");
2850 return -EINVAL;
2851 }
2852
868d5309 2853#define MAX_STD_JUMBO_FRAME_SIZE 9234
2d7edb92 2854 /* might want this to be bigger enum check... */
868d5309
MC		 2855 /* 82571 controllers limit jumbo frame size to 10500 bytes */
2856 if ((adapter->hw.mac_type == e1000_82571 ||
2857 adapter->hw.mac_type == e1000_82572) &&
2858 max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
2859 DPRINTK(PROBE, ERR, "MTU > 9216 bytes not supported "
2860 "on 82571 and 82572 controllers.\n");
2861 return -EINVAL;
2862 }
2863
2864 if(adapter->hw.mac_type == e1000_82573 &&
2d7edb92
MC		 2865 max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
2866 DPRINTK(PROBE, ERR, "Jumbo Frames not supported "
2867 "on 82573\n");
1da177e4 2868 return -EINVAL;
2d7edb92 2869 }
1da177e4 2870
2d7edb92
MC		 2871 if(adapter->hw.mac_type > e1000_82547_rev_2) {
2872 adapter->rx_buffer_len = max_frame;
2873 E1000_ROUNDUP(adapter->rx_buffer_len, 1024);
1da177e4 2874 } else {
2d7edb92
MC		 2875 if(unlikely((adapter->hw.mac_type < e1000_82543) &&
2876 (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE))) {
2877 DPRINTK(PROBE, ERR, "Jumbo Frames not supported "
2878 "on 82542\n");
2879 return -EINVAL;
2880
2881 } else {
2882 if(max_frame <= E1000_RXBUFFER_2048) {
2883 adapter->rx_buffer_len = E1000_RXBUFFER_2048;
2884 } else if(max_frame <= E1000_RXBUFFER_4096) {
2885 adapter->rx_buffer_len = E1000_RXBUFFER_4096;
2886 } else if(max_frame <= E1000_RXBUFFER_8192) {
2887 adapter->rx_buffer_len = E1000_RXBUFFER_8192;
2888 } else if(max_frame <= E1000_RXBUFFER_16384) {
2889 adapter->rx_buffer_len = E1000_RXBUFFER_16384;
2890 }
2891 }
1da177e4
LT		 2892 }
2893
2d7edb92
MC		 2894 netdev->mtu = new_mtu;
2895
2896 if(netif_running(netdev)) {
1da177e4
LT		 2897 e1000_down(adapter);
2898 e1000_up(adapter);
2899 }
2900
1da177e4
LT		 2901 adapter->hw.max_frame_size = max_frame;
2902
2903 return 0;
2904}
2905
2906/**
2907 * e1000_update_stats - Update the board statistics counters
2908 * @adapter: board private structure
2909 **/
2910
2911void
2912e1000_update_stats(struct e1000_adapter *adapter)
2913{
2914 struct e1000_hw *hw = &adapter->hw;
2915 unsigned long flags;
2916 uint16_t phy_tmp;
2917
2918#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
2919
2920 spin_lock_irqsave(&adapter->stats_lock, flags);
2921
2922 /* these counters are modified from e1000_adjust_tbi_stats,
2923 * called from the interrupt context, so they must only
2924 * be written while holding adapter->stats_lock
2925 */
2926
2927 adapter->stats.crcerrs += E1000_READ_REG(hw, CRCERRS);
2928 adapter->stats.gprc += E1000_READ_REG(hw, GPRC);
2929 adapter->stats.gorcl += E1000_READ_REG(hw, GORCL);
2930 adapter->stats.gorch += E1000_READ_REG(hw, GORCH);
2931 adapter->stats.bprc += E1000_READ_REG(hw, BPRC);
2932 adapter->stats.mprc += E1000_READ_REG(hw, MPRC);
2933 adapter->stats.roc += E1000_READ_REG(hw, ROC);
2934 adapter->stats.prc64 += E1000_READ_REG(hw, PRC64);
2935 adapter->stats.prc127 += E1000_READ_REG(hw, PRC127);
2936 adapter->stats.prc255 += E1000_READ_REG(hw, PRC255);
2937 adapter->stats.prc511 += E1000_READ_REG(hw, PRC511);
2938 adapter->stats.prc1023 += E1000_READ_REG(hw, PRC1023);
2939 adapter->stats.prc1522 += E1000_READ_REG(hw, PRC1522);
2940
2941 adapter->stats.symerrs += E1000_READ_REG(hw, SYMERRS);
2942 adapter->stats.mpc += E1000_READ_REG(hw, MPC);
2943 adapter->stats.scc += E1000_READ_REG(hw, SCC);
2944 adapter->stats.ecol += E1000_READ_REG(hw, ECOL);
2945 adapter->stats.mcc += E1000_READ_REG(hw, MCC);
2946 adapter->stats.latecol += E1000_READ_REG(hw, LATECOL);
2947 adapter->stats.dc += E1000_READ_REG(hw, DC);
2948 adapter->stats.sec += E1000_READ_REG(hw, SEC);
2949 adapter->stats.rlec += E1000_READ_REG(hw, RLEC);
2950 adapter->stats.xonrxc += E1000_READ_REG(hw, XONRXC);
2951 adapter->stats.xontxc += E1000_READ_REG(hw, XONTXC);
2952 adapter->stats.xoffrxc += E1000_READ_REG(hw, XOFFRXC);
2953 adapter->stats.xofftxc += E1000_READ_REG(hw, XOFFTXC);
2954 adapter->stats.fcruc += E1000_READ_REG(hw, FCRUC);
2955 adapter->stats.gptc += E1000_READ_REG(hw, GPTC);
2956 adapter->stats.gotcl += E1000_READ_REG(hw, GOTCL);
2957 adapter->stats.gotch += E1000_READ_REG(hw, GOTCH);
2958 adapter->stats.rnbc += E1000_READ_REG(hw, RNBC);
2959 adapter->stats.ruc += E1000_READ_REG(hw, RUC);
2960 adapter->stats.rfc += E1000_READ_REG(hw, RFC);
2961 adapter->stats.rjc += E1000_READ_REG(hw, RJC);
2962 adapter->stats.torl += E1000_READ_REG(hw, TORL);
2963 adapter->stats.torh += E1000_READ_REG(hw, TORH);
2964 adapter->stats.totl += E1000_READ_REG(hw, TOTL);
2965 adapter->stats.toth += E1000_READ_REG(hw, TOTH);
2966 adapter->stats.tpr += E1000_READ_REG(hw, TPR);
2967 adapter->stats.ptc64 += E1000_READ_REG(hw, PTC64);
2968 adapter->stats.ptc127 += E1000_READ_REG(hw, PTC127);
2969 adapter->stats.ptc255 += E1000_READ_REG(hw, PTC255);
2970 adapter->stats.ptc511 += E1000_READ_REG(hw, PTC511);
2971 adapter->stats.ptc1023 += E1000_READ_REG(hw, PTC1023);
2972 adapter->stats.ptc1522 += E1000_READ_REG(hw, PTC1522);
2973 adapter->stats.mptc += E1000_READ_REG(hw, MPTC);
2974 adapter->stats.bptc += E1000_READ_REG(hw, BPTC);
2975
2976 /* used for adaptive IFS */
2977
2978 hw->tx_packet_delta = E1000_READ_REG(hw, TPT);
2979 adapter->stats.tpt += hw->tx_packet_delta;
2980 hw->collision_delta = E1000_READ_REG(hw, COLC);
2981 adapter->stats.colc += hw->collision_delta;
2982
2983 if(hw->mac_type >= e1000_82543) {
2984 adapter->stats.algnerrc += E1000_READ_REG(hw, ALGNERRC);
2985 adapter->stats.rxerrc += E1000_READ_REG(hw, RXERRC);
2986 adapter->stats.tncrs += E1000_READ_REG(hw, TNCRS);
2987 adapter->stats.cexterr += E1000_READ_REG(hw, CEXTERR);
2988 adapter->stats.tsctc += E1000_READ_REG(hw, TSCTC);
2989 adapter->stats.tsctfc += E1000_READ_REG(hw, TSCTFC);
2990 }
2d7edb92
MC		 2991 if(hw->mac_type > e1000_82547_rev_2) {
2992 adapter->stats.iac += E1000_READ_REG(hw, IAC);
2993 adapter->stats.icrxoc += E1000_READ_REG(hw, ICRXOC);
2994 adapter->stats.icrxptc += E1000_READ_REG(hw, ICRXPTC);
2995 adapter->stats.icrxatc += E1000_READ_REG(hw, ICRXATC);
2996 adapter->stats.ictxptc += E1000_READ_REG(hw, ICTXPTC);
2997 adapter->stats.ictxatc += E1000_READ_REG(hw, ICTXATC);
2998 adapter->stats.ictxqec += E1000_READ_REG(hw, ICTXQEC);
2999 adapter->stats.ictxqmtc += E1000_READ_REG(hw, ICTXQMTC);
3000 adapter->stats.icrxdmtc += E1000_READ_REG(hw, ICRXDMTC);
3001 }
1da177e4
LT		 3002
3003 /* Fill out the OS statistics structure */
3004
3005 adapter->net_stats.rx_packets = adapter->stats.gprc;
3006 adapter->net_stats.tx_packets = adapter->stats.gptc;
3007 adapter->net_stats.rx_bytes = adapter->stats.gorcl;
3008 adapter->net_stats.tx_bytes = adapter->stats.gotcl;
3009 adapter->net_stats.multicast = adapter->stats.mprc;
3010 adapter->net_stats.collisions = adapter->stats.colc;
3011
3012 /* Rx Errors */
3013
3014 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3015 adapter->stats.crcerrs + adapter->stats.algnerrc +
6d915757
MC		 3016 adapter->stats.rlec + adapter->stats.mpc +
3017 adapter->stats.cexterr;
1da177e4
LT		 3018 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
3019 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3020 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3021 adapter->net_stats.rx_fifo_errors = adapter->stats.mpc;
3022 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3023
3024 /* Tx Errors */
3025
3026 adapter->net_stats.tx_errors = adapter->stats.ecol +
3027 adapter->stats.latecol;
3028 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3029 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3030 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3031
3032 /* Tx Dropped needs to be maintained elsewhere */
3033
3034 /* Phy Stats */
3035
3036 if(hw->media_type == e1000_media_type_copper) {
3037 if((adapter->link_speed == SPEED_1000) &&
3038 (!e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3039 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3040 adapter->phy_stats.idle_errors += phy_tmp;
3041 }
3042
3043 if((hw->mac_type <= e1000_82546) &&
3044 (hw->phy_type == e1000_phy_m88) &&
3045 !e1000_read_phy_reg(hw, M88E1000_RX_ERR_CNTR, &phy_tmp))
3046 adapter->phy_stats.receive_errors += phy_tmp;
3047 }
3048
3049 spin_unlock_irqrestore(&adapter->stats_lock, flags);
3050}
3051
24025e4e
MC		 3052#ifdef CONFIG_E1000_MQ
3053void
3054e1000_rx_schedule(void *data)
3055{
3056 struct net_device *poll_dev, *netdev = data;
3057 struct e1000_adapter *adapter = netdev->priv;
3058 int this_cpu = get_cpu();
3059
3060 poll_dev = *per_cpu_ptr(adapter->cpu_netdev, this_cpu);
3061 if (poll_dev == NULL) {
3062 put_cpu();
3063 return;
3064 }
3065
3066 if (likely(netif_rx_schedule_prep(poll_dev)))
3067 __netif_rx_schedule(poll_dev);
3068 else
3069 e1000_irq_enable(adapter);
3070
3071 put_cpu();
3072}
3073#endif
3074
1da177e4
LT		 3075/**
3076 * e1000_intr - Interrupt Handler
3077 * @irq: interrupt number
3078 * @data: pointer to a network interface device structure
3079 * @pt_regs: CPU registers structure
3080 **/
3081
3082static irqreturn_t
3083e1000_intr(int irq, void *data, struct pt_regs *regs)
3084{
3085 struct net_device *netdev = data;
60490fe0 3086 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 3087 struct e1000_hw *hw = &adapter->hw;
3088 uint32_t icr = E1000_READ_REG(hw, ICR);
581d708e 3089 int i;
1da177e4
LT		 3090
3091 if(unlikely(!icr))
3092 return IRQ_NONE; /* Not our interrupt */
3093
3094 if(unlikely(icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))) {
3095 hw->get_link_status = 1;
3096 mod_timer(&adapter->watchdog_timer, jiffies);
3097 }
3098
3099#ifdef CONFIG_E1000_NAPI
581d708e
MC		 3100 atomic_inc(&adapter->irq_sem);
3101 E1000_WRITE_REG(hw, IMC, ~0);
3102 E1000_WRITE_FLUSH(hw);
24025e4e
MC		 3103#ifdef CONFIG_E1000_MQ
3104 if (atomic_read(&adapter->rx_sched_call_data.count) == 0) {
3105 cpu_set(adapter->cpu_for_queue[0],
3106 adapter->rx_sched_call_data.cpumask);
3107 for (i = 1; i < adapter->num_queues; i++) {
3108 cpu_set(adapter->cpu_for_queue[i],
3109 adapter->rx_sched_call_data.cpumask);
3110 atomic_inc(&adapter->irq_sem);
3111 }
3112 atomic_set(&adapter->rx_sched_call_data.count, i);
3113 smp_call_async_mask(&adapter->rx_sched_call_data);
3114 } else {
3115 printk("call_data.count == %u\n", atomic_read(&adapter->rx_sched_call_data.count));
1da177e4
LT		 3116 }
3117#else
581d708e
MC		 3118 if (likely(netif_rx_schedule_prep(&adapter->polling_netdev[0])))
3119 __netif_rx_schedule(&adapter->polling_netdev[0]);
3120 else
3121 e1000_irq_enable(adapter);
24025e4e
MC		 3122#endif
3123#else
1da177e4
LT		 3124 /* Writing IMC and IMS is needed for 82547.
3125 Due to Hub Link bus being occupied, an interrupt
3126 de-assertion message is not able to be sent.
3127 When an interrupt assertion message is generated later,
3128 two messages are re-ordered and sent out.
3129 That causes APIC to think 82547 is in de-assertion
3130 state, while 82547 is in assertion state, resulting
3131 in dead lock. Writing IMC forces 82547 into
3132 de-assertion state.
3133 */
3134 if(hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2){
3135 atomic_inc(&adapter->irq_sem);
2648345f 3136 E1000_WRITE_REG(hw, IMC, ~0);
1da177e4
LT		 3137 }
3138
3139 for(i = 0; i < E1000_MAX_INTR; i++)
581d708e
MC		 3140 if(unlikely(!adapter->clean_rx(adapter, adapter->rx_ring) &
3141 !e1000_clean_tx_irq(adapter, adapter->tx_ring)))
1da177e4
LT		 3142 break;
3143
3144 if(hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2)
3145 e1000_irq_enable(adapter);
581d708e 3146
1da177e4
LT		 3147#endif
3148
3149 return IRQ_HANDLED;
3150}
3151
3152#ifdef CONFIG_E1000_NAPI
3153/**
3154 * e1000_clean - NAPI Rx polling callback
3155 * @adapter: board private structure
3156 **/
3157
3158static int
581d708e 3159e1000_clean(struct net_device *poll_dev, int *budget)
1da177e4 3160{
581d708e
MC		 3161 struct e1000_adapter *adapter;
3162 int work_to_do = min(*budget, poll_dev->quota);
3163 int tx_cleaned, i = 0, work_done = 0;
3164
3165 /* Must NOT use netdev_priv macro here. */
3166 adapter = poll_dev->priv;
3167
3168 /* Keep link state information with original netdev */
3169 if (!netif_carrier_ok(adapter->netdev))
3170 goto quit_polling;
2648345f 3171
581d708e
MC		 3172 while (poll_dev != &adapter->polling_netdev[i]) {
3173 i++;
3174 if (unlikely(i == adapter->num_queues))
3175 BUG();
3176 }
3177
3178 tx_cleaned = e1000_clean_tx_irq(adapter, &adapter->tx_ring[i]);
3179 adapter->clean_rx(adapter, &adapter->rx_ring[i],
3180 &work_done, work_to_do);
1da177e4
LT		 3181
3182 *budget -= work_done;
581d708e 3183 poll_dev->quota -= work_done;
1da177e4 3184
2b02893e 3185 /* If no Tx and not enough Rx work done, exit the polling mode */
581d708e
MC		 3186 if((!tx_cleaned && (work_done == 0)) ||
3187 !netif_running(adapter->netdev)) {
3188quit_polling:
3189 netif_rx_complete(poll_dev);
1da177e4
LT		 3190 e1000_irq_enable(adapter);
3191 return 0;
3192 }
3193
3194 return 1;
3195}
3196
3197#endif
3198/**
3199 * e1000_clean_tx_irq - Reclaim resources after transmit completes
3200 * @adapter: board private structure
3201 **/
3202
3203static boolean_t
581d708e
MC		 3204e1000_clean_tx_irq(struct e1000_adapter *adapter,
3205 struct e1000_tx_ring *tx_ring)
1da177e4 3206{
1da177e4
LT		 3207 struct net_device *netdev = adapter->netdev;
3208 struct e1000_tx_desc *tx_desc, *eop_desc;
3209 struct e1000_buffer *buffer_info;
3210 unsigned int i, eop;
3211 boolean_t cleaned = FALSE;
3212
3213 i = tx_ring->next_to_clean;
3214 eop = tx_ring->buffer_info[i].next_to_watch;
3215 eop_desc = E1000_TX_DESC(*tx_ring, eop);
3216
581d708e 3217 while (eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) {
2701234f
MC		 3218 /* Premature writeback of Tx descriptors clear (free buffers
3219 * and unmap pci_mapping) previous_buffer_info */
581d708e 3220 if (likely(tx_ring->previous_buffer_info.skb != NULL)) {
2701234f 3221 e1000_unmap_and_free_tx_resource(adapter,
581d708e 3222 &tx_ring->previous_buffer_info);
1da177e4
LT		 3223 }
3224
3225 for(cleaned = FALSE; !cleaned; ) {
3226 tx_desc = E1000_TX_DESC(*tx_ring, i);
3227 buffer_info = &tx_ring->buffer_info[i];
3228 cleaned = (i == eop);
3229
2701234f
MC		 3230#ifdef NETIF_F_TSO
3231 if (!(netdev->features & NETIF_F_TSO)) {
3232#endif
3233 e1000_unmap_and_free_tx_resource(adapter,
3234 buffer_info);
3235#ifdef NETIF_F_TSO
1da177e4 3236 } else {
2701234f 3237 if (cleaned) {
581d708e 3238 memcpy(&tx_ring->previous_buffer_info,
2701234f
MC		 3239 buffer_info,
3240 sizeof(struct e1000_buffer));
3241 memset(buffer_info, 0,
3242 sizeof(struct e1000_buffer));
3243 } else {
3244 e1000_unmap_and_free_tx_resource(
3245 adapter, buffer_info);
3246 }
1da177e4 3247 }
2701234f 3248#endif
1da177e4
LT		 3249
3250 tx_desc->buffer_addr = 0;
3251 tx_desc->lower.data = 0;
3252 tx_desc->upper.data = 0;
3253
1da177e4
LT		 3254 if(unlikely(++i == tx_ring->count)) i = 0;
3255 }
581d708e
MC		 3256
3257 tx_ring->pkt++;
1da177e4
LT		 3258
3259 eop = tx_ring->buffer_info[i].next_to_watch;
3260 eop_desc = E1000_TX_DESC(*tx_ring, eop);
3261 }
3262
3263 tx_ring->next_to_clean = i;
3264
581d708e 3265 spin_lock(&tx_ring->tx_lock);
1da177e4
LT		 3266
3267 if(unlikely(cleaned && netif_queue_stopped(netdev) &&
3268 netif_carrier_ok(netdev)))
3269 netif_wake_queue(netdev);
3270
581d708e 3271 spin_unlock(&tx_ring->tx_lock);
2648345f 3272
581d708e 3273 if (adapter->detect_tx_hung) {
2648345f 3274 /* Detect a transmit hang in hardware, this serializes the
1da177e4
LT		 3275 * check with the clearing of time_stamp and movement of i */
3276 adapter->detect_tx_hung = FALSE;
70b8f1e1
MC		 3277 if (tx_ring->buffer_info[i].dma &&
3278 time_after(jiffies, tx_ring->buffer_info[i].time_stamp + HZ)
3279 && !(E1000_READ_REG(&adapter->hw, STATUS) &
3280 E1000_STATUS_TXOFF)) {
3281
3282 /* detected Tx unit hang */
3283 i = tx_ring->next_to_clean;
3284 eop = tx_ring->buffer_info[i].next_to_watch;
3285 eop_desc = E1000_TX_DESC(*tx_ring, eop);
c6963ef5 3286 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
70b8f1e1
MC		 3287 " TDH <%x>\n"
3288 " TDT <%x>\n"
3289 " next_to_use <%x>\n"
3290 " next_to_clean <%x>\n"
3291 "buffer_info[next_to_clean]\n"
b4ee21f4 3292 " dma <%llx>\n"
70b8f1e1
MC		 3293 " time_stamp <%lx>\n"
3294 " next_to_watch <%x>\n"
3295 " jiffies <%lx>\n"
3296 " next_to_watch.status <%x>\n",
581d708e
MC		 3297 readl(adapter->hw.hw_addr + tx_ring->tdh),
3298 readl(adapter->hw.hw_addr + tx_ring->tdt),
70b8f1e1
MC		 3299 tx_ring->next_to_use,
3300 i,
b4ee21f4 3301 (unsigned long long)tx_ring->buffer_info[i].dma,
70b8f1e1
MC		 3302 tx_ring->buffer_info[i].time_stamp,
3303 eop,
3304 jiffies,
3305 eop_desc->upper.fields.status);
1da177e4 3306 netif_stop_queue(netdev);
70b8f1e1 3307 }
1da177e4 3308 }
2701234f 3309#ifdef NETIF_F_TSO
581d708e
MC		 3310 if (unlikely(!(eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
3311 time_after(jiffies, tx_ring->previous_buffer_info.time_stamp + HZ)))
2701234f 3312 e1000_unmap_and_free_tx_resource(
581d708e 3313 adapter, &tx_ring->previous_buffer_info);
2701234f 3314#endif
1da177e4
LT		 3315 return cleaned;
3316}
3317
3318/**
3319 * e1000_rx_checksum - Receive Checksum Offload for 82543
2d7edb92
MC		 3320 * @adapter: board private structure
3321 * @status_err: receive descriptor status and error fields
3322 * @csum: receive descriptor csum field
3323 * @sk_buff: socket buffer with received data
1da177e4
LT		 3324 **/
3325
3326static inline void
3327e1000_rx_checksum(struct e1000_adapter *adapter,
2d7edb92
MC		 3328 uint32_t status_err, uint32_t csum,
3329 struct sk_buff *skb)
1da177e4 3330{
2d7edb92
MC		 3331 uint16_t status = (uint16_t)status_err;
3332 uint8_t errors = (uint8_t)(status_err >> 24);
3333 skb->ip_summed = CHECKSUM_NONE;
3334
1da177e4 3335 /* 82543 or newer only */
2d7edb92 3336 if(unlikely(adapter->hw.mac_type < e1000_82543)) return;
1da177e4 3337 /* Ignore Checksum bit is set */
2d7edb92
MC		 3338 if(unlikely(status & E1000_RXD_STAT_IXSM)) return;
3339 /* TCP/UDP checksum error bit is set */
3340 if(unlikely(errors & E1000_RXD_ERR_TCPE)) {
1da177e4 3341 /* let the stack verify checksum errors */
1da177e4 3342 adapter->hw_csum_err++;
2d7edb92
MC		 3343 return;
3344 }
3345 /* TCP/UDP Checksum has not been calculated */
3346 if(adapter->hw.mac_type <= e1000_82547_rev_2) {
3347 if(!(status & E1000_RXD_STAT_TCPCS))
3348 return;
1da177e4 3349 } else {
2d7edb92
MC		 3350 if(!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
3351 return;
3352 }
3353 /* It must be a TCP or UDP packet with a valid checksum */
3354 if (likely(status & E1000_RXD_STAT_TCPCS)) {
1da177e4
LT		 3355 /* TCP checksum is good */
3356 skb->ip_summed = CHECKSUM_UNNECESSARY;
2d7edb92
MC		 3357 } else if (adapter->hw.mac_type > e1000_82547_rev_2) {
3358 /* IP fragment with UDP payload */
3359 /* Hardware complements the payload checksum, so we undo it
3360 * and then put the value in host order for further stack use.
3361 */
3362 csum = ntohl(csum ^ 0xFFFF);
3363 skb->csum = csum;
3364 skb->ip_summed = CHECKSUM_HW;
1da177e4 3365 }
2d7edb92 3366 adapter->hw_csum_good++;
1da177e4
LT		 3367}
3368
3369/**
2d7edb92 3370 * e1000_clean_rx_irq - Send received data up the network stack; legacy
1da177e4
LT		 3371 * @adapter: board private structure
3372 **/
3373
3374static boolean_t
3375#ifdef CONFIG_E1000_NAPI
581d708e
MC		 3376e1000_clean_rx_irq(struct e1000_adapter *adapter,
3377 struct e1000_rx_ring *rx_ring,
3378 int *work_done, int work_to_do)
1da177e4 3379#else
581d708e
MC		 3380e1000_clean_rx_irq(struct e1000_adapter *adapter,
3381 struct e1000_rx_ring *rx_ring)
1da177e4
LT		 3382#endif
3383{
1da177e4
LT		 3384 struct net_device *netdev = adapter->netdev;
3385 struct pci_dev *pdev = adapter->pdev;
3386 struct e1000_rx_desc *rx_desc;
3387 struct e1000_buffer *buffer_info;
3388 struct sk_buff *skb;
3389 unsigned long flags;
3390 uint32_t length;
3391 uint8_t last_byte;
3392 unsigned int i;
3393 boolean_t cleaned = FALSE;
3394
3395 i = rx_ring->next_to_clean;
3396 rx_desc = E1000_RX_DESC(*rx_ring, i);
3397
3398 while(rx_desc->status & E1000_RXD_STAT_DD) {
3399 buffer_info = &rx_ring->buffer_info[i];
3400#ifdef CONFIG_E1000_NAPI
3401 if(*work_done >= work_to_do)
3402 break;
3403 (*work_done)++;
3404#endif
3405 cleaned = TRUE;
3406
3407 pci_unmap_single(pdev,
3408 buffer_info->dma,
3409 buffer_info->length,
3410 PCI_DMA_FROMDEVICE);
3411
3412 skb = buffer_info->skb;
3413 length = le16_to_cpu(rx_desc->length);
3414
3415 if(unlikely(!(rx_desc->status & E1000_RXD_STAT_EOP))) {
3416 /* All receives must fit into a single buffer */
3417 E1000_DBG("%s: Receive packet consumed multiple"
2648345f 3418 " buffers\n", netdev->name);
1da177e4
LT		 3419 dev_kfree_skb_irq(skb);
3420 goto next_desc;
3421 }
3422
3423 if(unlikely(rx_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK)) {
3424 last_byte = *(skb->data + length - 1);
3425 if(TBI_ACCEPT(&adapter->hw, rx_desc->status,
3426 rx_desc->errors, length, last_byte)) {
3427 spin_lock_irqsave(&adapter->stats_lock, flags);
3428 e1000_tbi_adjust_stats(&adapter->hw,
3429 &adapter->stats,
3430 length, skb->data);
3431 spin_unlock_irqrestore(&adapter->stats_lock,
3432 flags);
3433 length--;
3434 } else {
3435 dev_kfree_skb_irq(skb);
3436 goto next_desc;
3437 }
3438 }
3439
3440 /* Good Receive */
3441 skb_put(skb, length - ETHERNET_FCS_SIZE);
3442
3443 /* Receive Checksum Offload */
2d7edb92
MC		 3444 e1000_rx_checksum(adapter,
3445 (uint32_t)(rx_desc->status) |
3446 ((uint32_t)(rx_desc->errors) << 24),
3447 rx_desc->csum, skb);
1da177e4
LT		 3448 skb->protocol = eth_type_trans(skb, netdev);
3449#ifdef CONFIG_E1000_NAPI
3450 if(unlikely(adapter->vlgrp &&
3451 (rx_desc->status & E1000_RXD_STAT_VP))) {
3452 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
2d7edb92
MC		 3453 le16_to_cpu(rx_desc->special) &
3454 E1000_RXD_SPC_VLAN_MASK);
1da177e4
LT		 3455 } else {
3456 netif_receive_skb(skb);
3457 }
3458#else /* CONFIG_E1000_NAPI */
3459 if(unlikely(adapter->vlgrp &&
3460 (rx_desc->status & E1000_RXD_STAT_VP))) {
3461 vlan_hwaccel_rx(skb, adapter->vlgrp,
3462 le16_to_cpu(rx_desc->special) &
3463 E1000_RXD_SPC_VLAN_MASK);
3464 } else {
3465 netif_rx(skb);
3466 }
3467#endif /* CONFIG_E1000_NAPI */
3468 netdev->last_rx = jiffies;
581d708e 3469 rx_ring->pkt++;
1da177e4
LT		 3470
3471next_desc:
3472 rx_desc->status = 0;
3473 buffer_info->skb = NULL;
3474 if(unlikely(++i == rx_ring->count)) i = 0;
3475
3476 rx_desc = E1000_RX_DESC(*rx_ring, i);
3477 }
1da177e4 3478 rx_ring->next_to_clean = i;
581d708e 3479 adapter->alloc_rx_buf(adapter, rx_ring);
2d7edb92
MC		 3480
3481 return cleaned;
3482}
3483
3484/**
3485 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
3486 * @adapter: board private structure
3487 **/
3488
3489static boolean_t
3490#ifdef CONFIG_E1000_NAPI
581d708e
MC		 3491e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3492 struct e1000_rx_ring *rx_ring,
3493 int *work_done, int work_to_do)
2d7edb92 3494#else
581d708e
MC		 3495e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3496 struct e1000_rx_ring *rx_ring)
2d7edb92
MC		 3497#endif
3498{
2d7edb92
MC		 3499 union e1000_rx_desc_packet_split *rx_desc;
3500 struct net_device *netdev = adapter->netdev;
3501 struct pci_dev *pdev = adapter->pdev;
3502 struct e1000_buffer *buffer_info;
3503 struct e1000_ps_page *ps_page;
3504 struct e1000_ps_page_dma *ps_page_dma;
3505 struct sk_buff *skb;
3506 unsigned int i, j;
3507 uint32_t length, staterr;
3508 boolean_t cleaned = FALSE;
3509
3510 i = rx_ring->next_to_clean;
3511 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
683a38f3 3512 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
2d7edb92
MC		 3513
3514 while(staterr & E1000_RXD_STAT_DD) {
3515 buffer_info = &rx_ring->buffer_info[i];
3516 ps_page = &rx_ring->ps_page[i];
3517 ps_page_dma = &rx_ring->ps_page_dma[i];
3518#ifdef CONFIG_E1000_NAPI
3519 if(unlikely(*work_done >= work_to_do))
3520 break;
3521 (*work_done)++;
3522#endif
3523 cleaned = TRUE;
3524 pci_unmap_single(pdev, buffer_info->dma,
3525 buffer_info->length,
3526 PCI_DMA_FROMDEVICE);
3527
3528 skb = buffer_info->skb;
3529
3530 if(unlikely(!(staterr & E1000_RXD_STAT_EOP))) {
3531 E1000_DBG("%s: Packet Split buffers didn't pick up"
3532 " the full packet\n", netdev->name);
3533 dev_kfree_skb_irq(skb);
3534 goto next_desc;
3535 }
1da177e4 3536
2d7edb92
MC		 3537 if(unlikely(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
3538 dev_kfree_skb_irq(skb);
3539 goto next_desc;
3540 }
3541
3542 length = le16_to_cpu(rx_desc->wb.middle.length0);
3543
3544 if(unlikely(!length)) {
3545 E1000_DBG("%s: Last part of the packet spanning"
3546 " multiple descriptors\n", netdev->name);
3547 dev_kfree_skb_irq(skb);
3548 goto next_desc;
3549 }
3550
3551 /* Good Receive */
3552 skb_put(skb, length);
3553
3554 for(j = 0; j < PS_PAGE_BUFFERS; j++) {
3555 if(!(length = le16_to_cpu(rx_desc->wb.upper.length[j])))
3556 break;
3557
3558 pci_unmap_page(pdev, ps_page_dma->ps_page_dma[j],
3559 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3560 ps_page_dma->ps_page_dma[j] = 0;
3561 skb_shinfo(skb)->frags[j].page =
3562 ps_page->ps_page[j];
3563 ps_page->ps_page[j] = NULL;
3564 skb_shinfo(skb)->frags[j].page_offset = 0;
3565 skb_shinfo(skb)->frags[j].size = length;
3566 skb_shinfo(skb)->nr_frags++;
3567 skb->len += length;
3568 skb->data_len += length;
3569 }
3570
3571 e1000_rx_checksum(adapter, staterr,
3572 rx_desc->wb.lower.hi_dword.csum_ip.csum, skb);
3573 skb->protocol = eth_type_trans(skb, netdev);
3574
3575#ifdef HAVE_RX_ZERO_COPY
3576 if(likely(rx_desc->wb.upper.header_status &
3577 E1000_RXDPS_HDRSTAT_HDRSP))
3578 skb_shinfo(skb)->zero_copy = TRUE;
3579#endif
3580#ifdef CONFIG_E1000_NAPI
3581 if(unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
3582 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
683a38f3
MC		 3583 le16_to_cpu(rx_desc->wb.middle.vlan) &
3584 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 3585 } else {
3586 netif_receive_skb(skb);
3587 }
3588#else /* CONFIG_E1000_NAPI */
3589 if(unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
3590 vlan_hwaccel_rx(skb, adapter->vlgrp,
683a38f3
MC		 3591 le16_to_cpu(rx_desc->wb.middle.vlan) &
3592 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 3593 } else {
3594 netif_rx(skb);
3595 }
3596#endif /* CONFIG_E1000_NAPI */
3597 netdev->last_rx = jiffies;
581d708e 3598 rx_ring->pkt++;
2d7edb92
MC		 3599
3600next_desc:
3601 rx_desc->wb.middle.status_error &= ~0xFF;
3602 buffer_info->skb = NULL;
3603 if(unlikely(++i == rx_ring->count)) i = 0;
3604
3605 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
683a38f3 3606 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
2d7edb92
MC		 3607 }
3608 rx_ring->next_to_clean = i;
581d708e 3609 adapter->alloc_rx_buf(adapter, rx_ring);
1da177e4
LT		 3610
3611 return cleaned;
3612}
3613
3614/**
2d7edb92 3615 * e1000_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1da177e4
LT		 3616 * @adapter: address of board private structure
3617 **/
3618
3619static void
581d708e
MC		 3620e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
3621 struct e1000_rx_ring *rx_ring)
1da177e4 3622{
1da177e4
LT		 3623 struct net_device *netdev = adapter->netdev;
3624 struct pci_dev *pdev = adapter->pdev;
3625 struct e1000_rx_desc *rx_desc;
3626 struct e1000_buffer *buffer_info;
3627 struct sk_buff *skb;
2648345f
MC		 3628 unsigned int i;
3629 unsigned int bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
1da177e4
LT		 3630
3631 i = rx_ring->next_to_use;
3632 buffer_info = &rx_ring->buffer_info[i];
3633
3634 while(!buffer_info->skb) {
1da177e4 3635 skb = dev_alloc_skb(bufsz);
2648345f 3636
1da177e4
LT		 3637 if(unlikely(!skb)) {
3638 /* Better luck next round */
3639 break;
3640 }
3641
2648345f 3642 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 3643 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
3644 struct sk_buff *oldskb = skb;
2648345f
MC		 3645 DPRINTK(RX_ERR, ERR, "skb align check failed: %u bytes "
3646 "at %p\n", bufsz, skb->data);
3647 /* Try again, without freeing the previous */
1da177e4 3648 skb = dev_alloc_skb(bufsz);
2648345f 3649 /* Failed allocation, critical failure */
1da177e4
LT		 3650 if (!skb) {
3651 dev_kfree_skb(oldskb);
3652 break;
3653 }
2648345f 3654
1da177e4
LT		 3655 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
3656 /* give up */
3657 dev_kfree_skb(skb);
3658 dev_kfree_skb(oldskb);
3659 break; /* while !buffer_info->skb */
3660 } else {
2648345f 3661 /* Use new allocation */
1da177e4
LT		 3662 dev_kfree_skb(oldskb);
3663 }
3664 }
1da177e4
LT		 3665 /* Make buffer alignment 2 beyond a 16 byte boundary
3666 * this will result in a 16 byte aligned IP header after
3667 * the 14 byte MAC header is removed
3668 */
3669 skb_reserve(skb, NET_IP_ALIGN);
3670
3671 skb->dev = netdev;
3672
3673 buffer_info->skb = skb;
3674 buffer_info->length = adapter->rx_buffer_len;
3675 buffer_info->dma = pci_map_single(pdev,
3676 skb->data,
3677 adapter->rx_buffer_len,
3678 PCI_DMA_FROMDEVICE);
3679
2648345f
MC		 3680 /* Fix for errata 23, can't cross 64kB boundary */
3681 if (!e1000_check_64k_bound(adapter,
3682 (void *)(unsigned long)buffer_info->dma,
3683 adapter->rx_buffer_len)) {
3684 DPRINTK(RX_ERR, ERR,
3685 "dma align check failed: %u bytes at %p\n",
3686 adapter->rx_buffer_len,
3687 (void *)(unsigned long)buffer_info->dma);
1da177e4
LT		 3688 dev_kfree_skb(skb);
3689 buffer_info->skb = NULL;
3690
2648345f 3691 pci_unmap_single(pdev, buffer_info->dma,
1da177e4
LT		 3692 adapter->rx_buffer_len,
3693 PCI_DMA_FROMDEVICE);
3694
3695 break; /* while !buffer_info->skb */
3696 }
1da177e4
LT		 3697 rx_desc = E1000_RX_DESC(*rx_ring, i);
3698 rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
3699
3700 if(unlikely((i & ~(E1000_RX_BUFFER_WRITE - 1)) == i)) {
3701 /* Force memory writes to complete before letting h/w
3702 * know there are new descriptors to fetch. (Only
3703 * applicable for weak-ordered memory model archs,
3704 * such as IA-64). */
3705 wmb();
581d708e 3706 writel(i, adapter->hw.hw_addr + rx_ring->rdt);
1da177e4
LT		 3707 }
3708
3709 if(unlikely(++i == rx_ring->count)) i = 0;
3710 buffer_info = &rx_ring->buffer_info[i];
3711 }
3712
3713 rx_ring->next_to_use = i;
3714}
3715
2d7edb92
MC		 3716/**
3717 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
3718 * @adapter: address of board private structure
3719 **/
3720
3721static void
581d708e
MC		 3722e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
3723 struct e1000_rx_ring *rx_ring)
2d7edb92 3724{
2d7edb92
MC		 3725 struct net_device *netdev = adapter->netdev;
3726 struct pci_dev *pdev = adapter->pdev;
3727 union e1000_rx_desc_packet_split *rx_desc;
3728 struct e1000_buffer *buffer_info;
3729 struct e1000_ps_page *ps_page;
3730 struct e1000_ps_page_dma *ps_page_dma;
3731 struct sk_buff *skb;
3732 unsigned int i, j;
3733
3734 i = rx_ring->next_to_use;
3735 buffer_info = &rx_ring->buffer_info[i];
3736 ps_page = &rx_ring->ps_page[i];
3737 ps_page_dma = &rx_ring->ps_page_dma[i];
3738
3739 while(!buffer_info->skb) {
3740 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
3741
3742 for(j = 0; j < PS_PAGE_BUFFERS; j++) {
3743 if(unlikely(!ps_page->ps_page[j])) {
3744 ps_page->ps_page[j] =
3745 alloc_page(GFP_ATOMIC);
3746 if(unlikely(!ps_page->ps_page[j]))
3747 goto no_buffers;
3748 ps_page_dma->ps_page_dma[j] =
3749 pci_map_page(pdev,
3750 ps_page->ps_page[j],
3751 0, PAGE_SIZE,
3752 PCI_DMA_FROMDEVICE);
3753 }
3754 /* Refresh the desc even if buffer_addrs didn't
3755 * change because each write-back erases this info.
3756 */
3757 rx_desc->read.buffer_addr[j+1] =
3758 cpu_to_le64(ps_page_dma->ps_page_dma[j]);
3759 }
3760
3761 skb = dev_alloc_skb(adapter->rx_ps_bsize0 + NET_IP_ALIGN);
3762
3763 if(unlikely(!skb))
3764 break;
3765
3766 /* Make buffer alignment 2 beyond a 16 byte boundary
3767 * this will result in a 16 byte aligned IP header after
3768 * the 14 byte MAC header is removed
3769 */
3770 skb_reserve(skb, NET_IP_ALIGN);
3771
3772 skb->dev = netdev;
3773
3774 buffer_info->skb = skb;
3775 buffer_info->length = adapter->rx_ps_bsize0;
3776 buffer_info->dma = pci_map_single(pdev, skb->data,
3777 adapter->rx_ps_bsize0,
3778 PCI_DMA_FROMDEVICE);
3779
3780 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
3781
3782 if(unlikely((i & ~(E1000_RX_BUFFER_WRITE - 1)) == i)) {
3783 /* Force memory writes to complete before letting h/w
3784 * know there are new descriptors to fetch. (Only
3785 * applicable for weak-ordered memory model archs,
3786 * such as IA-64). */
3787 wmb();
3788 /* Hardware increments by 16 bytes, but packet split
3789 * descriptors are 32 bytes...so we increment tail
3790 * twice as much.
3791 */
581d708e 3792 writel(i<<1, adapter->hw.hw_addr + rx_ring->rdt);
2d7edb92
MC		 3793 }
3794
3795 if(unlikely(++i == rx_ring->count)) i = 0;
3796 buffer_info = &rx_ring->buffer_info[i];
3797 ps_page = &rx_ring->ps_page[i];
3798 ps_page_dma = &rx_ring->ps_page_dma[i];
3799 }
3800
3801no_buffers:
3802 rx_ring->next_to_use = i;
3803}
3804
1da177e4
LT		 3805/**
3806 * e1000_smartspeed - Workaround for SmartSpeed on 82541 and 82547 controllers.
3807 * @adapter:
3808 **/
3809
3810static void
3811e1000_smartspeed(struct e1000_adapter *adapter)
3812{
3813 uint16_t phy_status;
3814 uint16_t phy_ctrl;
3815
3816 if((adapter->hw.phy_type != e1000_phy_igp) || !adapter->hw.autoneg ||
3817 !(adapter->hw.autoneg_advertised & ADVERTISE_1000_FULL))
3818 return;
3819
3820 if(adapter->smartspeed == 0) {
3821 /* If Master/Slave config fault is asserted twice,
3822 * we assume back-to-back */
3823 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
3824 if(!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
3825 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
3826 if(!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
3827 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
3828 if(phy_ctrl & CR_1000T_MS_ENABLE) {
3829 phy_ctrl &= ~CR_1000T_MS_ENABLE;
3830 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL,
3831 phy_ctrl);
3832 adapter->smartspeed++;
3833 if(!e1000_phy_setup_autoneg(&adapter->hw) &&
3834 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL,
3835 &phy_ctrl)) {
3836 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
3837 MII_CR_RESTART_AUTO_NEG);
3838 e1000_write_phy_reg(&adapter->hw, PHY_CTRL,
3839 phy_ctrl);
3840 }
3841 }
3842 return;
3843 } else if(adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) {
3844 /* If still no link, perhaps using 2/3 pair cable */
3845 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
3846 phy_ctrl |= CR_1000T_MS_ENABLE;
3847 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_ctrl);
3848 if(!e1000_phy_setup_autoneg(&adapter->hw) &&
3849 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_ctrl)) {
3850 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
3851 MII_CR_RESTART_AUTO_NEG);
3852 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, phy_ctrl);
3853 }
3854 }
3855 /* Restart process after E1000_SMARTSPEED_MAX iterations */
3856 if(adapter->smartspeed++ == E1000_SMARTSPEED_MAX)
3857 adapter->smartspeed = 0;
3858}
3859
3860/**
3861 * e1000_ioctl -
3862 * @netdev:
3863 * @ifreq:
3864 * @cmd:
3865 **/
3866
3867static int
3868e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
3869{
3870 switch (cmd) {
3871 case SIOCGMIIPHY:
3872 case SIOCGMIIREG:
3873 case SIOCSMIIREG:
3874 return e1000_mii_ioctl(netdev, ifr, cmd);
3875 default:
3876 return -EOPNOTSUPP;
3877 }
3878}
3879
3880/**
3881 * e1000_mii_ioctl -
3882 * @netdev:
3883 * @ifreq:
3884 * @cmd:
3885 **/
3886
3887static int
3888e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
3889{
60490fe0 3890 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 3891 struct mii_ioctl_data *data = if_mii(ifr);
3892 int retval;
3893 uint16_t mii_reg;
3894 uint16_t spddplx;
97876fc6 3895 unsigned long flags;
1da177e4
LT		 3896
3897 if(adapter->hw.media_type != e1000_media_type_copper)
3898 return -EOPNOTSUPP;
3899
3900 switch (cmd) {
3901 case SIOCGMIIPHY:
3902 data->phy_id = adapter->hw.phy_addr;
3903 break;
3904 case SIOCGMIIREG:
97876fc6 3905 if(!capable(CAP_NET_ADMIN))
1da177e4 3906 return -EPERM;
97876fc6
MC		 3907 spin_lock_irqsave(&adapter->stats_lock, flags);
3908 if(e1000_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
3909 &data->val_out)) {
3910 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 3911 return -EIO;
97876fc6
MC		 3912 }
3913 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 3914 break;
3915 case SIOCSMIIREG:
97876fc6 3916 if(!capable(CAP_NET_ADMIN))
1da177e4 3917 return -EPERM;
97876fc6 3918 if(data->reg_num & ~(0x1F))
1da177e4
LT		 3919 return -EFAULT;
3920 mii_reg = data->val_in;
97876fc6
MC		 3921 spin_lock_irqsave(&adapter->stats_lock, flags);
3922 if(e1000_write_phy_reg(&adapter->hw, data->reg_num,
3923 mii_reg)) {
3924 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 3925 return -EIO;
97876fc6
MC		 3926 }
3927 if(adapter->hw.phy_type == e1000_phy_m88) {
1da177e4
LT		 3928 switch (data->reg_num) {
3929 case PHY_CTRL:
3930 if(mii_reg & MII_CR_POWER_DOWN)
3931 break;
3932 if(mii_reg & MII_CR_AUTO_NEG_EN) {
3933 adapter->hw.autoneg = 1;
3934 adapter->hw.autoneg_advertised = 0x2F;
3935 } else {
3936 if (mii_reg & 0x40)
3937 spddplx = SPEED_1000;
3938 else if (mii_reg & 0x2000)
3939 spddplx = SPEED_100;
3940 else
3941 spddplx = SPEED_10;
3942 spddplx += (mii_reg & 0x100)
3943 ? FULL_DUPLEX :
3944 HALF_DUPLEX;
3945 retval = e1000_set_spd_dplx(adapter,
3946 spddplx);
97876fc6
MC		 3947 if(retval) {
3948 spin_unlock_irqrestore(
3949 &adapter->stats_lock,
3950 flags);
1da177e4 3951 return retval;
97876fc6 3952 }
1da177e4
LT		 3953 }
3954 if(netif_running(adapter->netdev)) {
3955 e1000_down(adapter);
3956 e1000_up(adapter);
3957 } else
3958 e1000_reset(adapter);
3959 break;
3960 case M88E1000_PHY_SPEC_CTRL:
3961 case M88E1000_EXT_PHY_SPEC_CTRL:
97876fc6
MC		 3962 if(e1000_phy_reset(&adapter->hw)) {
3963 spin_unlock_irqrestore(
3964 &adapter->stats_lock, flags);
1da177e4 3965 return -EIO;
97876fc6 3966 }
1da177e4
LT		 3967 break;
3968 }
3969 } else {
3970 switch (data->reg_num) {
3971 case PHY_CTRL:
3972 if(mii_reg & MII_CR_POWER_DOWN)
3973 break;
3974 if(netif_running(adapter->netdev)) {
3975 e1000_down(adapter);
3976 e1000_up(adapter);
3977 } else
3978 e1000_reset(adapter);
3979 break;
3980 }
3981 }
97876fc6 3982 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 3983 break;
3984 default:
3985 return -EOPNOTSUPP;
3986 }
3987 return E1000_SUCCESS;
3988}
3989
3990void
3991e1000_pci_set_mwi(struct e1000_hw *hw)
3992{
3993 struct e1000_adapter *adapter = hw->back;
2648345f 3994 int ret_val = pci_set_mwi(adapter->pdev);
1da177e4 3995
2648345f
MC		 3996 if(ret_val)
3997 DPRINTK(PROBE, ERR, "Error in setting MWI\n");
1da177e4
LT		 3998}
3999
4000void
4001e1000_pci_clear_mwi(struct e1000_hw *hw)
4002{
4003 struct e1000_adapter *adapter = hw->back;
4004
4005 pci_clear_mwi(adapter->pdev);
4006}
4007
4008void
4009e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4010{
4011 struct e1000_adapter *adapter = hw->back;
4012
4013 pci_read_config_word(adapter->pdev, reg, value);
4014}
4015
4016void
4017e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4018{
4019 struct e1000_adapter *adapter = hw->back;
4020
4021 pci_write_config_word(adapter->pdev, reg, *value);
4022}
4023
4024uint32_t
4025e1000_io_read(struct e1000_hw *hw, unsigned long port)
4026{
4027 return inl(port);
4028}
4029
4030void
4031e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value)
4032{
4033 outl(value, port);
4034}
4035
4036static void
4037e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
4038{
60490fe0 4039 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4040 uint32_t ctrl, rctl;
4041
4042 e1000_irq_disable(adapter);
4043 adapter->vlgrp = grp;
4044
4045 if(grp) {
4046 /* enable VLAN tag insert/strip */
4047 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4048 ctrl |= E1000_CTRL_VME;
4049 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4050
4051 /* enable VLAN receive filtering */
4052 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4053 rctl |= E1000_RCTL_VFE;
4054 rctl &= ~E1000_RCTL_CFIEN;
4055 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2d7edb92 4056 e1000_update_mng_vlan(adapter);
1da177e4
LT		 4057 } else {
4058 /* disable VLAN tag insert/strip */
4059 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4060 ctrl &= ~E1000_CTRL_VME;
4061 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4062
4063 /* disable VLAN filtering */
4064 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4065 rctl &= ~E1000_RCTL_VFE;
4066 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2d7edb92
MC		 4067 if(adapter->mng_vlan_id != (uint16_t)E1000_MNG_VLAN_NONE) {
4068 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4069 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4070 }
1da177e4
LT		 4071 }
4072
4073 e1000_irq_enable(adapter);
4074}
4075
4076static void
4077e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid)
4078{
60490fe0 4079 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 4080 uint32_t vfta, index;
2d7edb92
MC		 4081 if((adapter->hw.mng_cookie.status &
4082 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
4083 (vid == adapter->mng_vlan_id))
4084 return;
1da177e4
LT		 4085 /* add VID to filter table */
4086 index = (vid >> 5) & 0x7F;
4087 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
4088 vfta |= (1 << (vid & 0x1F));
4089 e1000_write_vfta(&adapter->hw, index, vfta);
4090}
4091
4092static void
4093e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid)
4094{
60490fe0 4095 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4096 uint32_t vfta, index;
4097
4098 e1000_irq_disable(adapter);
4099
4100 if(adapter->vlgrp)
4101 adapter->vlgrp->vlan_devices[vid] = NULL;
4102
4103 e1000_irq_enable(adapter);
4104
2d7edb92
MC		 4105 if((adapter->hw.mng_cookie.status &
4106 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
4107 (vid == adapter->mng_vlan_id))
4108 return;
1da177e4
LT		 4109 /* remove VID from filter table */
4110 index = (vid >> 5) & 0x7F;
4111 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
4112 vfta &= ~(1 << (vid & 0x1F));
4113 e1000_write_vfta(&adapter->hw, index, vfta);
4114}
4115
4116static void
4117e1000_restore_vlan(struct e1000_adapter *adapter)
4118{
4119 e1000_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4120
4121 if(adapter->vlgrp) {
4122 uint16_t vid;
4123 for(vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4124 if(!adapter->vlgrp->vlan_devices[vid])
4125 continue;
4126 e1000_vlan_rx_add_vid(adapter->netdev, vid);
4127 }
4128 }
4129}
4130
4131int
4132e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx)
4133{
4134 adapter->hw.autoneg = 0;
4135
6921368f
MC		 4136 /* Fiber NICs only allow 1000 gbps Full duplex */
4137 if((adapter->hw.media_type == e1000_media_type_fiber) &&
4138 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4139 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
4140 return -EINVAL;
4141 }
4142
1da177e4
LT		 4143 switch(spddplx) {
4144 case SPEED_10 + DUPLEX_HALF:
4145 adapter->hw.forced_speed_duplex = e1000_10_half;
4146 break;
4147 case SPEED_10 + DUPLEX_FULL:
4148 adapter->hw.forced_speed_duplex = e1000_10_full;
4149 break;
4150 case SPEED_100 + DUPLEX_HALF:
4151 adapter->hw.forced_speed_duplex = e1000_100_half;
4152 break;
4153 case SPEED_100 + DUPLEX_FULL:
4154 adapter->hw.forced_speed_duplex = e1000_100_full;
4155 break;
4156 case SPEED_1000 + DUPLEX_FULL:
4157 adapter->hw.autoneg = 1;
4158 adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL;
4159 break;
4160 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4161 default:
2648345f 4162 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
1da177e4
LT		 4163 return -EINVAL;
4164 }
4165 return 0;
4166}
4167
1da177e4 4168static int
829ca9a3 4169e1000_suspend(struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 4170{
4171 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 4172 struct e1000_adapter *adapter = netdev_priv(netdev);
2d7edb92 4173 uint32_t ctrl, ctrl_ext, rctl, manc, status, swsm;
1da177e4
LT		 4174 uint32_t wufc = adapter->wol;
4175
4176 netif_device_detach(netdev);
4177
4178 if(netif_running(netdev))
4179 e1000_down(adapter);
4180
4181 status = E1000_READ_REG(&adapter->hw, STATUS);
4182 if(status & E1000_STATUS_LU)
4183 wufc &= ~E1000_WUFC_LNKC;
4184
4185 if(wufc) {
4186 e1000_setup_rctl(adapter);
4187 e1000_set_multi(netdev);
4188
4189 /* turn on all-multi mode if wake on multicast is enabled */
4190 if(adapter->wol & E1000_WUFC_MC) {
4191 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4192 rctl |= E1000_RCTL_MPE;
4193 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
4194 }
4195
4196 if(adapter->hw.mac_type >= e1000_82540) {
4197 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4198 /* advertise wake from D3Cold */
4199 #define E1000_CTRL_ADVD3WUC 0x00100000
4200 /* phy power management enable */
4201 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4202 ctrl |= E1000_CTRL_ADVD3WUC |
4203 E1000_CTRL_EN_PHY_PWR_MGMT;
4204 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4205 }
4206
4207 if(adapter->hw.media_type == e1000_media_type_fiber ||
4208 adapter->hw.media_type == e1000_media_type_internal_serdes) {
4209 /* keep the laser running in D3 */
4210 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
4211 ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
4212 E1000_WRITE_REG(&adapter->hw, CTRL_EXT, ctrl_ext);
4213 }
4214
2d7edb92
MC		 4215 /* Allow time for pending master requests to run */
4216 e1000_disable_pciex_master(&adapter->hw);
4217
1da177e4
LT		 4218 E1000_WRITE_REG(&adapter->hw, WUC, E1000_WUC_PME_EN);
4219 E1000_WRITE_REG(&adapter->hw, WUFC, wufc);
4220 pci_enable_wake(pdev, 3, 1);
4221 pci_enable_wake(pdev, 4, 1); /* 4 == D3 cold */
4222 } else {
4223 E1000_WRITE_REG(&adapter->hw, WUC, 0);
4224 E1000_WRITE_REG(&adapter->hw, WUFC, 0);
4225 pci_enable_wake(pdev, 3, 0);
4226 pci_enable_wake(pdev, 4, 0); /* 4 == D3 cold */
4227 }
4228
4229 pci_save_state(pdev);
4230
4231 if(adapter->hw.mac_type >= e1000_82540 &&
4232 adapter->hw.media_type == e1000_media_type_copper) {
4233 manc = E1000_READ_REG(&adapter->hw, MANC);
4234 if(manc & E1000_MANC_SMBUS_EN) {
4235 manc |= E1000_MANC_ARP_EN;
4236 E1000_WRITE_REG(&adapter->hw, MANC, manc);
4237 pci_enable_wake(pdev, 3, 1);
4238 pci_enable_wake(pdev, 4, 1); /* 4 == D3 cold */
4239 }
4240 }
4241
2d7edb92 4242 switch(adapter->hw.mac_type) {
868d5309
MC		 4243 case e1000_82571:
4244 case e1000_82572:
4245 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
4246 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
4247 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
4248 break;
2d7edb92
MC		 4249 case e1000_82573:
4250 swsm = E1000_READ_REG(&adapter->hw, SWSM);
4251 E1000_WRITE_REG(&adapter->hw, SWSM,
4252 swsm & ~E1000_SWSM_DRV_LOAD);
4253 break;
4254 default:
4255 break;
4256 }
4257
1da177e4 4258 pci_disable_device(pdev);
829ca9a3 4259 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 4260
4261 return 0;
4262}
4263
4264#ifdef CONFIG_PM
4265static int
4266e1000_resume(struct pci_dev *pdev)
4267{
4268 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 4269 struct e1000_adapter *adapter = netdev_priv(netdev);
2b02893e 4270 uint32_t manc, ret_val, swsm;
868d5309 4271 uint32_t ctrl_ext;
1da177e4 4272
829ca9a3 4273 pci_set_power_state(pdev, PCI_D0);
1da177e4 4274 pci_restore_state(pdev);
2b02893e 4275 ret_val = pci_enable_device(pdev);
a4cb847d 4276 pci_set_master(pdev);
1da177e4 4277
829ca9a3
PM		 4278 pci_enable_wake(pdev, PCI_D3hot, 0);
4279 pci_enable_wake(pdev, PCI_D3cold, 0);
1da177e4
LT		 4280
4281 e1000_reset(adapter);
4282 E1000_WRITE_REG(&adapter->hw, WUS, ~0);
4283
4284 if(netif_running(netdev))
4285 e1000_up(adapter);
4286
4287 netif_device_attach(netdev);
4288
4289 if(adapter->hw.mac_type >= e1000_82540 &&
4290 adapter->hw.media_type == e1000_media_type_copper) {
4291 manc = E1000_READ_REG(&adapter->hw, MANC);
4292 manc &= ~(E1000_MANC_ARP_EN);
4293 E1000_WRITE_REG(&adapter->hw, MANC, manc);
4294 }
4295
2d7edb92 4296 switch(adapter->hw.mac_type) {
868d5309
MC		 4297 case e1000_82571:
4298 case e1000_82572:
4299 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
4300 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
4301 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
4302 break;
2d7edb92
MC		 4303 case e1000_82573:
4304 swsm = E1000_READ_REG(&adapter->hw, SWSM);
4305 E1000_WRITE_REG(&adapter->hw, SWSM,
4306 swsm | E1000_SWSM_DRV_LOAD);
4307 break;
4308 default:
4309 break;
4310 }
4311
1da177e4
LT		 4312 return 0;
4313}
4314#endif
1da177e4
LT		 4315#ifdef CONFIG_NET_POLL_CONTROLLER
4316/*
4317 * Polling 'interrupt' - used by things like netconsole to send skbs
4318 * without having to re-enable interrupts. It's not called while
4319 * the interrupt routine is executing.
4320 */
4321static void
2648345f 4322e1000_netpoll(struct net_device *netdev)
1da177e4 4323{
60490fe0 4324 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4325 disable_irq(adapter->pdev->irq);
4326 e1000_intr(adapter->pdev->irq, netdev, NULL);
6b0b3157 4327 e1000_clean_tx_irq(adapter);
1da177e4
LT		 4328 enable_irq(adapter->pdev->irq);
4329}
4330#endif
4331
4332/* e1000_main.c */