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e100, e1000, ixgb: update copyright header and remove LICENSE
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / e1000 / e1000_hw.c
CommitLineData
1da177e4
LT		 1/*******************************************************************************
2
0abb6eb1
AK		 3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1da177e4 13 more details.
0abb6eb1 14
1da177e4 15 You should have received a copy of the GNU General Public License along with
0abb6eb1
AK		 16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
1da177e4
LT		 22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
3d41e30a 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
1da177e4
LT		 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/* e1000_hw.c
30 * Shared functions for accessing and configuring the MAC
31 */
32
8fc897b0 33
1da177e4
LT		 34#include "e1000_hw.h"
35
36static int32_t e1000_set_phy_type(struct e1000_hw *hw);
37static void e1000_phy_init_script(struct e1000_hw *hw);
38static int32_t e1000_setup_copper_link(struct e1000_hw *hw);
39static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
40static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
41static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw);
42static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw);
43static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
44static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
45static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data,
46 uint16_t count);
47static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw);
48static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw);
49static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset,
50 uint16_t words, uint16_t *data);
51static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw,
52 uint16_t offset, uint16_t words,
53 uint16_t *data);
54static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw);
55static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
56static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
57static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data,
58 uint16_t count);
59static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
60 uint16_t phy_data);
61static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr,
62 uint16_t *phy_data);
63static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count);
64static int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
65static void e1000_release_eeprom(struct e1000_hw *hw);
66static void e1000_standby_eeprom(struct e1000_hw *hw);
1da177e4
LT		 67static int32_t e1000_set_vco_speed(struct e1000_hw *hw);
68static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw);
69static int32_t e1000_set_phy_mode(struct e1000_hw *hw);
2d7edb92
MC		 70static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer);
71static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length);
3ad2cc67
AB		 72static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw);
73static int32_t e1000_check_downshift(struct e1000_hw *hw);
74static int32_t e1000_check_polarity(struct e1000_hw *hw, uint16_t *polarity);
75static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
76static void e1000_clear_vfta(struct e1000_hw *hw);
77static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw);
78static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw,
79 boolean_t link_up);
80static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw);
81static int32_t e1000_detect_gig_phy(struct e1000_hw *hw);
82static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw);
83static int32_t e1000_get_cable_length(struct e1000_hw *hw,
84 uint16_t *min_length,
85 uint16_t *max_length);
86static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
87static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw);
88static int32_t e1000_id_led_init(struct e1000_hw * hw);
89static void e1000_init_rx_addrs(struct e1000_hw *hw);
90static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
91static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
92static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
93static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset,
94 uint16_t words, uint16_t *data);
95static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active);
96static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
97static int32_t e1000_wait_autoneg(struct e1000_hw *hw);
98
99static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset,
100 uint32_t value);
101
102#define E1000_WRITE_REG_IO(a, reg, val) \
103 e1000_write_reg_io((a), E1000_##reg, val)
cd94dd0b
AK		 104static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw,
105 uint16_t duplex);
6418ecc6 106static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
1da177e4 107
e4c780b1
AB		 108static int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw,
109 uint32_t segment);
110static int32_t e1000_get_software_flag(struct e1000_hw *hw);
111static int32_t e1000_get_software_semaphore(struct e1000_hw *hw);
112static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw);
113static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
114static int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset,
115 uint16_t words, uint16_t *data);
116static int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index,
117 uint8_t* data);
118static int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index,
119 uint16_t *data);
120static int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr,
121 uint16_t *data);
122static void e1000_release_software_flag(struct e1000_hw *hw);
123static void e1000_release_software_semaphore(struct e1000_hw *hw);
124static int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw,
125 uint32_t no_snoop);
126static int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw,
127 uint32_t index, uint8_t byte);
128static int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset,
129 uint16_t words, uint16_t *data);
130static int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index,
131 uint8_t data);
132static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr,
133 uint16_t data);
134
1da177e4
LT		 135/* IGP cable length table */
136static const
137uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
138 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
139 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
140 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
141 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
142 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
143 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
144 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
145 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
146
2d7edb92
MC		 147static const
148uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
868d5309
MC		 149 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
150 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
151 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
152 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
153 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
154 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
155 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
156 104, 109, 114, 118, 121, 124};
2d7edb92 157
1da177e4
LT		 158
159/******************************************************************************
160 * Set the phy type member in the hw struct.
161 *
162 * hw - Struct containing variables accessed by shared code
163 *****************************************************************************/
164int32_t
165e1000_set_phy_type(struct e1000_hw *hw)
166{
167 DEBUGFUNC("e1000_set_phy_type");
168
8fc897b0 169 if (hw->mac_type == e1000_undefined)
2d7edb92
MC		 170 return -E1000_ERR_PHY_TYPE;
171
8fc897b0 172 switch (hw->phy_id) {
1da177e4
LT		 173 case M88E1000_E_PHY_ID:
174 case M88E1000_I_PHY_ID:
175 case M88E1011_I_PHY_ID:
2d7edb92 176 case M88E1111_I_PHY_ID:
1da177e4
LT		 177 hw->phy_type = e1000_phy_m88;
178 break;
179 case IGP01E1000_I_PHY_ID:
8fc897b0
AK		 180 if (hw->mac_type == e1000_82541 ||
181 hw->mac_type == e1000_82541_rev_2 ||
182 hw->mac_type == e1000_82547 ||
183 hw->mac_type == e1000_82547_rev_2) {
1da177e4
LT		 184 hw->phy_type = e1000_phy_igp;
185 break;
186 }
cd94dd0b
AK		 187 case IGP03E1000_E_PHY_ID:
188 hw->phy_type = e1000_phy_igp_3;
189 break;
190 case IFE_E_PHY_ID:
191 case IFE_PLUS_E_PHY_ID:
192 case IFE_C_E_PHY_ID:
193 hw->phy_type = e1000_phy_ife;
194 break;
6418ecc6
JK		 195 case GG82563_E_PHY_ID:
196 if (hw->mac_type == e1000_80003es2lan) {
197 hw->phy_type = e1000_phy_gg82563;
198 break;
199 }
1da177e4
LT		 200 /* Fall Through */
201 default:
202 /* Should never have loaded on this device */
203 hw->phy_type = e1000_phy_undefined;
204 return -E1000_ERR_PHY_TYPE;
205 }
206
207 return E1000_SUCCESS;
208}
209
8fc897b0 210
1da177e4
LT		 211/******************************************************************************
212 * IGP phy init script - initializes the GbE PHY
213 *
214 * hw - Struct containing variables accessed by shared code
215 *****************************************************************************/
216static void
217e1000_phy_init_script(struct e1000_hw *hw)
218{
219 uint32_t ret_val;
220 uint16_t phy_saved_data;
221
222 DEBUGFUNC("e1000_phy_init_script");
223
8fc897b0 224 if (hw->phy_init_script) {
f8ec4733 225 msleep(20);
1da177e4
LT		 226
227 /* Save off the current value of register 0x2F5B to be restored at
228 * the end of this routine. */
229 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
230
231 /* Disabled the PHY transmitter */
232 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
233
f8ec4733 234 msleep(20);
1da177e4
LT		 235
236 e1000_write_phy_reg(hw,0x0000,0x0140);
237
f8ec4733 238 msleep(5);
1da177e4 239
8fc897b0 240 switch (hw->mac_type) {
1da177e4
LT		 241 case e1000_82541:
242 case e1000_82547:
243 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
244
245 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
246
247 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
248
249 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
250
251 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
252
253 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
254
255 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
256
257 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
258
259 e1000_write_phy_reg(hw, 0x2010, 0x0008);
260 break;
261
262 case e1000_82541_rev_2:
263 case e1000_82547_rev_2:
264 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
265 break;
266 default:
267 break;
268 }
269
270 e1000_write_phy_reg(hw, 0x0000, 0x3300);
271
f8ec4733 272 msleep(20);
1da177e4
LT		 273
274 /* Now enable the transmitter */
275 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
276
8fc897b0 277 if (hw->mac_type == e1000_82547) {
1da177e4
LT		 278 uint16_t fused, fine, coarse;
279
280 /* Move to analog registers page */
281 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
282
8fc897b0 283 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
1da177e4
LT		 284 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
285
286 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
287 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
288
8fc897b0 289 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
1da177e4
LT		 290 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
291 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
8fc897b0 292 } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
1da177e4
LT		 293 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
294
295 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
296 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
297 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
298
299 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
300 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
301 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
302 }
303 }
304 }
305}
306
307/******************************************************************************
308 * Set the mac type member in the hw struct.
309 *
310 * hw - Struct containing variables accessed by shared code
311 *****************************************************************************/
312int32_t
313e1000_set_mac_type(struct e1000_hw *hw)
314{
315 DEBUGFUNC("e1000_set_mac_type");
316
317 switch (hw->device_id) {
318 case E1000_DEV_ID_82542:
319 switch (hw->revision_id) {
320 case E1000_82542_2_0_REV_ID:
321 hw->mac_type = e1000_82542_rev2_0;
322 break;
323 case E1000_82542_2_1_REV_ID:
324 hw->mac_type = e1000_82542_rev2_1;
325 break;
326 default:
327 /* Invalid 82542 revision ID */
328 return -E1000_ERR_MAC_TYPE;
329 }
330 break;
331 case E1000_DEV_ID_82543GC_FIBER:
332 case E1000_DEV_ID_82543GC_COPPER:
333 hw->mac_type = e1000_82543;
334 break;
335 case E1000_DEV_ID_82544EI_COPPER:
336 case E1000_DEV_ID_82544EI_FIBER:
337 case E1000_DEV_ID_82544GC_COPPER:
338 case E1000_DEV_ID_82544GC_LOM:
339 hw->mac_type = e1000_82544;
340 break;
341 case E1000_DEV_ID_82540EM:
342 case E1000_DEV_ID_82540EM_LOM:
343 case E1000_DEV_ID_82540EP:
344 case E1000_DEV_ID_82540EP_LOM:
345 case E1000_DEV_ID_82540EP_LP:
346 hw->mac_type = e1000_82540;
347 break;
348 case E1000_DEV_ID_82545EM_COPPER:
349 case E1000_DEV_ID_82545EM_FIBER:
350 hw->mac_type = e1000_82545;
351 break;
352 case E1000_DEV_ID_82545GM_COPPER:
353 case E1000_DEV_ID_82545GM_FIBER:
354 case E1000_DEV_ID_82545GM_SERDES:
355 hw->mac_type = e1000_82545_rev_3;
356 break;
357 case E1000_DEV_ID_82546EB_COPPER:
358 case E1000_DEV_ID_82546EB_FIBER:
359 case E1000_DEV_ID_82546EB_QUAD_COPPER:
360 hw->mac_type = e1000_82546;
361 break;
362 case E1000_DEV_ID_82546GB_COPPER:
363 case E1000_DEV_ID_82546GB_FIBER:
364 case E1000_DEV_ID_82546GB_SERDES:
365 case E1000_DEV_ID_82546GB_PCIE:
b7ee49db
JK		 366 case E1000_DEV_ID_82546GB_QUAD_COPPER:
367 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1da177e4
LT		 368 hw->mac_type = e1000_82546_rev_3;
369 break;
370 case E1000_DEV_ID_82541EI:
371 case E1000_DEV_ID_82541EI_MOBILE:
cd94dd0b 372 case E1000_DEV_ID_82541ER_LOM:
1da177e4
LT		 373 hw->mac_type = e1000_82541;
374 break;
375 case E1000_DEV_ID_82541ER:
376 case E1000_DEV_ID_82541GI:
377 case E1000_DEV_ID_82541GI_LF:
378 case E1000_DEV_ID_82541GI_MOBILE:
379 hw->mac_type = e1000_82541_rev_2;
380 break;
381 case E1000_DEV_ID_82547EI:
cd94dd0b 382 case E1000_DEV_ID_82547EI_MOBILE:
1da177e4
LT		 383 hw->mac_type = e1000_82547;
384 break;
385 case E1000_DEV_ID_82547GI:
386 hw->mac_type = e1000_82547_rev_2;
387 break;
868d5309
MC		 388 case E1000_DEV_ID_82571EB_COPPER:
389 case E1000_DEV_ID_82571EB_FIBER:
390 case E1000_DEV_ID_82571EB_SERDES:
5881cde8 391 case E1000_DEV_ID_82571EB_QUAD_COPPER:
868d5309
MC		 392 hw->mac_type = e1000_82571;
393 break;
394 case E1000_DEV_ID_82572EI_COPPER:
395 case E1000_DEV_ID_82572EI_FIBER:
396 case E1000_DEV_ID_82572EI_SERDES:
cd94dd0b 397 case E1000_DEV_ID_82572EI:
868d5309
MC		 398 hw->mac_type = e1000_82572;
399 break;
2d7edb92
MC		 400 case E1000_DEV_ID_82573E:
401 case E1000_DEV_ID_82573E_IAMT:
868d5309 402 case E1000_DEV_ID_82573L:
2d7edb92
MC		 403 hw->mac_type = e1000_82573;
404 break;
cd94dd0b
AK		 405 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
406 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
6418ecc6
JK		 407 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
408 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
409 hw->mac_type = e1000_80003es2lan;
410 break;
cd94dd0b
AK		 411 case E1000_DEV_ID_ICH8_IGP_M_AMT:
412 case E1000_DEV_ID_ICH8_IGP_AMT:
413 case E1000_DEV_ID_ICH8_IGP_C:
414 case E1000_DEV_ID_ICH8_IFE:
415 case E1000_DEV_ID_ICH8_IGP_M:
416 hw->mac_type = e1000_ich8lan;
417 break;
1da177e4
LT		 418 default:
419 /* Should never have loaded on this device */
420 return -E1000_ERR_MAC_TYPE;
421 }
422
8fc897b0 423 switch (hw->mac_type) {
cd94dd0b
AK		 424 case e1000_ich8lan:
425 hw->swfwhw_semaphore_present = TRUE;
426 hw->asf_firmware_present = TRUE;
427 break;
6418ecc6
JK		 428 case e1000_80003es2lan:
429 hw->swfw_sync_present = TRUE;
430 /* fall through */
868d5309
MC		 431 case e1000_82571:
432 case e1000_82572:
2d7edb92
MC		 433 case e1000_82573:
434 hw->eeprom_semaphore_present = TRUE;
435 /* fall through */
1da177e4
LT		 436 case e1000_82541:
437 case e1000_82547:
438 case e1000_82541_rev_2:
439 case e1000_82547_rev_2:
440 hw->asf_firmware_present = TRUE;
441 break;
442 default:
443 break;
444 }
445
446 return E1000_SUCCESS;
447}
448
449/*****************************************************************************
450 * Set media type and TBI compatibility.
451 *
452 * hw - Struct containing variables accessed by shared code
453 * **************************************************************************/
454void
455e1000_set_media_type(struct e1000_hw *hw)
456{
457 uint32_t status;
458
459 DEBUGFUNC("e1000_set_media_type");
460
8fc897b0 461 if (hw->mac_type != e1000_82543) {
1da177e4
LT		 462 /* tbi_compatibility is only valid on 82543 */
463 hw->tbi_compatibility_en = FALSE;
464 }
465
466 switch (hw->device_id) {
467 case E1000_DEV_ID_82545GM_SERDES:
468 case E1000_DEV_ID_82546GB_SERDES:
868d5309
MC		 469 case E1000_DEV_ID_82571EB_SERDES:
470 case E1000_DEV_ID_82572EI_SERDES:
6418ecc6 471 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
1da177e4
LT		 472 hw->media_type = e1000_media_type_internal_serdes;
473 break;
474 default:
3893d547
MC		 475 switch (hw->mac_type) {
476 case e1000_82542_rev2_0:
477 case e1000_82542_rev2_1:
478 hw->media_type = e1000_media_type_fiber;
479 break;
cd94dd0b 480 case e1000_ich8lan:
3893d547
MC		 481 case e1000_82573:
482 /* The STATUS_TBIMODE bit is reserved or reused for the this
483 * device.
484 */
485 hw->media_type = e1000_media_type_copper;
486 break;
487 default:
1da177e4 488 status = E1000_READ_REG(hw, STATUS);
3893d547 489 if (status & E1000_STATUS_TBIMODE) {
1da177e4
LT		 490 hw->media_type = e1000_media_type_fiber;
491 /* tbi_compatibility not valid on fiber */
492 hw->tbi_compatibility_en = FALSE;
493 } else {
494 hw->media_type = e1000_media_type_copper;
495 }
3893d547 496 break;
1da177e4
LT		 497 }
498 }
499}
500
501/******************************************************************************
502 * Reset the transmit and receive units; mask and clear all interrupts.
503 *
504 * hw - Struct containing variables accessed by shared code
505 *****************************************************************************/
506int32_t
507e1000_reset_hw(struct e1000_hw *hw)
508{
509 uint32_t ctrl;
510 uint32_t ctrl_ext;
511 uint32_t icr;
512 uint32_t manc;
513 uint32_t led_ctrl;
2d7edb92
MC		 514 uint32_t timeout;
515 uint32_t extcnf_ctrl;
516 int32_t ret_val;
1da177e4
LT		 517
518 DEBUGFUNC("e1000_reset_hw");
519
520 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
8fc897b0 521 if (hw->mac_type == e1000_82542_rev2_0) {
1da177e4
LT		 522 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
523 e1000_pci_clear_mwi(hw);
524 }
525
8fc897b0 526 if (hw->bus_type == e1000_bus_type_pci_express) {
2d7edb92
MC		 527 /* Prevent the PCI-E bus from sticking if there is no TLP connection
528 * on the last TLP read/write transaction when MAC is reset.
529 */
8fc897b0 530 if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
2d7edb92
MC		 531 DEBUGOUT("PCI-E Master disable polling has failed.\n");
532 }
533 }
534
1da177e4
LT		 535 /* Clear interrupt mask to stop board from generating interrupts */
536 DEBUGOUT("Masking off all interrupts\n");
537 E1000_WRITE_REG(hw, IMC, 0xffffffff);
538
539 /* Disable the Transmit and Receive units. Then delay to allow
540 * any pending transactions to complete before we hit the MAC with
541 * the global reset.
542 */
543 E1000_WRITE_REG(hw, RCTL, 0);
544 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
545 E1000_WRITE_FLUSH(hw);
546
547 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
548 hw->tbi_compatibility_on = FALSE;
549
550 /* Delay to allow any outstanding PCI transactions to complete before
551 * resetting the device
552 */
f8ec4733 553 msleep(10);
1da177e4
LT		 554
555 ctrl = E1000_READ_REG(hw, CTRL);
556
557 /* Must reset the PHY before resetting the MAC */
8fc897b0 558 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2d7edb92 559 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
f8ec4733 560 msleep(5);
1da177e4
LT		 561 }
562
2d7edb92
MC		 563 /* Must acquire the MDIO ownership before MAC reset.
564 * Ownership defaults to firmware after a reset. */
8fc897b0 565 if (hw->mac_type == e1000_82573) {
2d7edb92
MC		 566 timeout = 10;
567
568 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
569 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
570
571 do {
572 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
573 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
574
8fc897b0 575 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
2d7edb92
MC		 576 break;
577 else
578 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
579
f8ec4733 580 msleep(2);
2d7edb92 581 timeout--;
8fc897b0 582 } while (timeout);
2d7edb92
MC		 583 }
584
cd94dd0b
AK		 585 /* Workaround for ICH8 bit corruption issue in FIFO memory */
586 if (hw->mac_type == e1000_ich8lan) {
587 /* Set Tx and Rx buffer allocation to 8k apiece. */
588 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K);
589 /* Set Packet Buffer Size to 16k. */
590 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K);
591 }
592
1da177e4
LT		 593 /* Issue a global reset to the MAC. This will reset the chip's
594 * transmit, receive, DMA, and link units. It will not effect
595 * the current PCI configuration. The global reset bit is self-
596 * clearing, and should clear within a microsecond.
597 */
598 DEBUGOUT("Issuing a global reset to MAC\n");
599
8fc897b0 600 switch (hw->mac_type) {
1da177e4
LT		 601 case e1000_82544:
602 case e1000_82540:
603 case e1000_82545:
604 case e1000_82546:
605 case e1000_82541:
606 case e1000_82541_rev_2:
607 /* These controllers can't ack the 64-bit write when issuing the
608 * reset, so use IO-mapping as a workaround to issue the reset */
609 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
610 break;
611 case e1000_82545_rev_3:
612 case e1000_82546_rev_3:
613 /* Reset is performed on a shadow of the control register */
614 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
615 break;
cd94dd0b
AK		 616 case e1000_ich8lan:
617 if (!hw->phy_reset_disable &&
618 e1000_check_phy_reset_block(hw) == E1000_SUCCESS) {
619 /* e1000_ich8lan PHY HW reset requires MAC CORE reset
620 * at the same time to make sure the interface between
621 * MAC and the external PHY is reset.
622 */
623 ctrl |= E1000_CTRL_PHY_RST;
624 }
625
626 e1000_get_software_flag(hw);
627 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
f8ec4733 628 msleep(5);
cd94dd0b 629 break;
1da177e4
LT		 630 default:
631 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
632 break;
633 }
634
635 /* After MAC reset, force reload of EEPROM to restore power-on settings to
636 * device. Later controllers reload the EEPROM automatically, so just wait
637 * for reload to complete.
638 */
8fc897b0 639 switch (hw->mac_type) {
1da177e4
LT		 640 case e1000_82542_rev2_0:
641 case e1000_82542_rev2_1:
642 case e1000_82543:
643 case e1000_82544:
644 /* Wait for reset to complete */
645 udelay(10);
646 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
647 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
648 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
649 E1000_WRITE_FLUSH(hw);
650 /* Wait for EEPROM reload */
f8ec4733 651 msleep(2);
1da177e4
LT		 652 break;
653 case e1000_82541:
654 case e1000_82541_rev_2:
655 case e1000_82547:
656 case e1000_82547_rev_2:
657 /* Wait for EEPROM reload */
f8ec4733 658 msleep(20);
1da177e4 659 break;
2d7edb92 660 case e1000_82573:
fd803241
JK		 661 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
662 udelay(10);
663 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
664 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
665 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
666 E1000_WRITE_FLUSH(hw);
667 }
2d7edb92 668 /* fall through */
868d5309
MC		 669 case e1000_82571:
670 case e1000_82572:
cd94dd0b 671 case e1000_ich8lan:
6418ecc6 672 case e1000_80003es2lan:
2d7edb92 673 ret_val = e1000_get_auto_rd_done(hw);
8fc897b0 674 if (ret_val)
2d7edb92
MC		 675 /* We don't want to continue accessing MAC registers. */
676 return ret_val;
677 break;
1da177e4
LT		 678 default:
679 /* Wait for EEPROM reload (it happens automatically) */
f8ec4733 680 msleep(5);
1da177e4
LT		 681 break;
682 }
683
684 /* Disable HW ARPs on ASF enabled adapters */
8fc897b0 685 if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
1da177e4
LT		 686 manc = E1000_READ_REG(hw, MANC);
687 manc &= ~(E1000_MANC_ARP_EN);
688 E1000_WRITE_REG(hw, MANC, manc);
689 }
690
8fc897b0 691 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1da177e4
LT		 692 e1000_phy_init_script(hw);
693
694 /* Configure activity LED after PHY reset */
695 led_ctrl = E1000_READ_REG(hw, LEDCTL);
696 led_ctrl &= IGP_ACTIVITY_LED_MASK;
697 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
698 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
699 }
700
701 /* Clear interrupt mask to stop board from generating interrupts */
702 DEBUGOUT("Masking off all interrupts\n");
703 E1000_WRITE_REG(hw, IMC, 0xffffffff);
704
705 /* Clear any pending interrupt events. */
706 icr = E1000_READ_REG(hw, ICR);
707
708 /* If MWI was previously enabled, reenable it. */
8fc897b0 709 if (hw->mac_type == e1000_82542_rev2_0) {
f8ec4733 710 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
1da177e4
LT		 711 e1000_pci_set_mwi(hw);
712 }
713
cd94dd0b
AK		 714 if (hw->mac_type == e1000_ich8lan) {
715 uint32_t kab = E1000_READ_REG(hw, KABGTXD);
716 kab |= E1000_KABGTXD_BGSQLBIAS;
717 E1000_WRITE_REG(hw, KABGTXD, kab);
718 }
719
1da177e4
LT		 720 return E1000_SUCCESS;
721}
722
723/******************************************************************************
724 * Performs basic configuration of the adapter.
725 *
726 * hw - Struct containing variables accessed by shared code
727 *
728 * Assumes that the controller has previously been reset and is in a
729 * post-reset uninitialized state. Initializes the receive address registers,
730 * multicast table, and VLAN filter table. Calls routines to setup link
731 * configuration and flow control settings. Clears all on-chip counters. Leaves
732 * the transmit and receive units disabled and uninitialized.
733 *****************************************************************************/
734int32_t
735e1000_init_hw(struct e1000_hw *hw)
736{
737 uint32_t ctrl;
738 uint32_t i;
739 int32_t ret_val;
740 uint16_t pcix_cmd_word;
741 uint16_t pcix_stat_hi_word;
742 uint16_t cmd_mmrbc;
743 uint16_t stat_mmrbc;
2d7edb92 744 uint32_t mta_size;
6418ecc6 745 uint32_t reg_data;
b7ee49db 746 uint32_t ctrl_ext;
2d7edb92 747
1da177e4
LT		 748 DEBUGFUNC("e1000_init_hw");
749
7820d428
JK		 750 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
751 if (hw->mac_type == e1000_ich8lan) {
752 reg_data = E1000_READ_REG(hw, TARC0);
753 reg_data |= 0x30000000;
754 E1000_WRITE_REG(hw, TARC0, reg_data);
755
756 reg_data = E1000_READ_REG(hw, STATUS);
757 reg_data &= ~0x80000000;
758 E1000_WRITE_REG(hw, STATUS, reg_data);
759 }
760
1da177e4
LT		 761 /* Initialize Identification LED */
762 ret_val = e1000_id_led_init(hw);
8fc897b0 763 if (ret_val) {
1da177e4
LT		 764 DEBUGOUT("Error Initializing Identification LED\n");
765 return ret_val;
766 }
767
768 /* Set the media type and TBI compatibility */
769 e1000_set_media_type(hw);
770
771 /* Disabling VLAN filtering. */
772 DEBUGOUT("Initializing the IEEE VLAN\n");
cd94dd0b
AK		 773 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
774 if (hw->mac_type != e1000_ich8lan) {
775 if (hw->mac_type < e1000_82545_rev_3)
776 E1000_WRITE_REG(hw, VET, 0);
777 e1000_clear_vfta(hw);
778 }
1da177e4
LT		 779
780 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
8fc897b0 781 if (hw->mac_type == e1000_82542_rev2_0) {
1da177e4
LT		 782 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
783 e1000_pci_clear_mwi(hw);
784 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
785 E1000_WRITE_FLUSH(hw);
f8ec4733 786 msleep(5);
1da177e4
LT		 787 }
788
789 /* Setup the receive address. This involves initializing all of the Receive
790 * Address Registers (RARs 0 - 15).
791 */
792 e1000_init_rx_addrs(hw);
793
794 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
8fc897b0 795 if (hw->mac_type == e1000_82542_rev2_0) {
1da177e4
LT		 796 E1000_WRITE_REG(hw, RCTL, 0);
797 E1000_WRITE_FLUSH(hw);
f8ec4733
JG		 798 msleep(1);
799 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
1da177e4
LT		 800 e1000_pci_set_mwi(hw);
801 }
802
803 /* Zero out the Multicast HASH table */
804 DEBUGOUT("Zeroing the MTA\n");
2d7edb92 805 mta_size = E1000_MC_TBL_SIZE;
cd94dd0b
AK		 806 if (hw->mac_type == e1000_ich8lan)
807 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
8fc897b0 808 for (i = 0; i < mta_size; i++) {
1da177e4 809 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
4ca213a6
AK		 810 /* use write flush to prevent Memory Write Block (MWB) from
811 * occuring when accessing our register space */
812 E1000_WRITE_FLUSH(hw);
813 }
1da177e4
LT		 814
815 /* Set the PCI priority bit correctly in the CTRL register. This
816 * determines if the adapter gives priority to receives, or if it
2d7edb92
MC		 817 * gives equal priority to transmits and receives. Valid only on
818 * 82542 and 82543 silicon.
1da177e4 819 */
8fc897b0 820 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
1da177e4
LT		 821 ctrl = E1000_READ_REG(hw, CTRL);
822 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
823 }
824
8fc897b0 825 switch (hw->mac_type) {
1da177e4
LT		 826 case e1000_82545_rev_3:
827 case e1000_82546_rev_3:
828 break;
829 default:
830 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
8fc897b0 831 if (hw->bus_type == e1000_bus_type_pcix) {
1da177e4
LT		 832 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
833 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
834 &pcix_stat_hi_word);
835 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
836 PCIX_COMMAND_MMRBC_SHIFT;
837 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
838 PCIX_STATUS_HI_MMRBC_SHIFT;
8fc897b0 839 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1da177e4 840 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
8fc897b0 841 if (cmd_mmrbc > stat_mmrbc) {
1da177e4
LT		 842 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
843 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
844 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
845 &pcix_cmd_word);
846 }
847 }
848 break;
849 }
850
cd94dd0b
AK		 851 /* More time needed for PHY to initialize */
852 if (hw->mac_type == e1000_ich8lan)
f8ec4733 853 msleep(15);
cd94dd0b 854
1da177e4
LT		 855 /* Call a subroutine to configure the link and setup flow control. */
856 ret_val = e1000_setup_link(hw);
857
858 /* Set the transmit descriptor write-back policy */
8fc897b0 859 if (hw->mac_type > e1000_82544) {
1da177e4
LT		 860 ctrl = E1000_READ_REG(hw, TXDCTL);
861 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
2d7edb92
MC		 862 switch (hw->mac_type) {
863 default:
864 break;
868d5309
MC		 865 case e1000_82571:
866 case e1000_82572:
2d7edb92 867 case e1000_82573:
cd94dd0b 868 case e1000_ich8lan:
6418ecc6 869 case e1000_80003es2lan:
2d7edb92
MC		 870 ctrl |= E1000_TXDCTL_COUNT_DESC;
871 break;
872 }
1da177e4
LT		 873 E1000_WRITE_REG(hw, TXDCTL, ctrl);
874 }
875
2d7edb92 876 if (hw->mac_type == e1000_82573) {
76c224bc 877 e1000_enable_tx_pkt_filtering(hw);
2d7edb92
MC		 878 }
879
868d5309
MC		 880 switch (hw->mac_type) {
881 default:
882 break;
6418ecc6
JK		 883 case e1000_80003es2lan:
884 /* Enable retransmit on late collisions */
885 reg_data = E1000_READ_REG(hw, TCTL);
886 reg_data |= E1000_TCTL_RTLC;
887 E1000_WRITE_REG(hw, TCTL, reg_data);
888
889 /* Configure Gigabit Carry Extend Padding */
890 reg_data = E1000_READ_REG(hw, TCTL_EXT);
891 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
892 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
893 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
894
895 /* Configure Transmit Inter-Packet Gap */
896 reg_data = E1000_READ_REG(hw, TIPG);
897 reg_data &= ~E1000_TIPG_IPGT_MASK;
898 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
899 E1000_WRITE_REG(hw, TIPG, reg_data);
900
901 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
902 reg_data &= ~0x00100000;
903 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
904 /* Fall through */
868d5309 905 case e1000_82571:
a7990ba6 906 case e1000_82572:
cd94dd0b 907 case e1000_ich8lan:
868d5309 908 ctrl = E1000_READ_REG(hw, TXDCTL1);
6418ecc6 909 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
8fc897b0 910 if (hw->mac_type >= e1000_82571)
6418ecc6 911 ctrl |= E1000_TXDCTL_COUNT_DESC;
868d5309
MC		 912 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
913 break;
914 }
915
916
868d5309
MC		 917 if (hw->mac_type == e1000_82573) {
918 uint32_t gcr = E1000_READ_REG(hw, GCR);
919 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
920 E1000_WRITE_REG(hw, GCR, gcr);
921 }
2d7edb92 922
1da177e4
LT		 923 /* Clear all of the statistics registers (clear on read). It is
924 * important that we do this after we have tried to establish link
925 * because the symbol error count will increment wildly if there
926 * is no link.
927 */
928 e1000_clear_hw_cntrs(hw);
929
cd94dd0b
AK		 930 /* ICH8 No-snoop bits are opposite polarity.
931 * Set to snoop by default after reset. */
932 if (hw->mac_type == e1000_ich8lan)
933 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
934
b7ee49db
JK		 935 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
936 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
937 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
938 /* Relaxed ordering must be disabled to avoid a parity
939 * error crash in a PCI slot. */
940 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
941 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
942 }
943
1da177e4
LT		 944 return ret_val;
945}
946
947/******************************************************************************
948 * Adjust SERDES output amplitude based on EEPROM setting.
949 *
950 * hw - Struct containing variables accessed by shared code.
951 *****************************************************************************/
952static int32_t
953e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
954{
955 uint16_t eeprom_data;
956 int32_t ret_val;
957
958 DEBUGFUNC("e1000_adjust_serdes_amplitude");
959
8fc897b0 960 if (hw->media_type != e1000_media_type_internal_serdes)
1da177e4
LT		 961 return E1000_SUCCESS;
962
8fc897b0 963 switch (hw->mac_type) {
1da177e4
LT		 964 case e1000_82545_rev_3:
965 case e1000_82546_rev_3:
966 break;
967 default:
968 return E1000_SUCCESS;
969 }
970
971 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
972 if (ret_val) {
973 return ret_val;
974 }
975
8fc897b0 976 if (eeprom_data != EEPROM_RESERVED_WORD) {
1da177e4 977 /* Adjust SERDES output amplitude only. */
76c224bc 978 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
1da177e4 979 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
8fc897b0 980 if (ret_val)
1da177e4
LT		 981 return ret_val;
982 }
983
984 return E1000_SUCCESS;
985}
986
987/******************************************************************************
988 * Configures flow control and link settings.
989 *
990 * hw - Struct containing variables accessed by shared code
991 *
992 * Determines which flow control settings to use. Calls the apropriate media-
993 * specific link configuration function. Configures the flow control settings.
994 * Assuming the adapter has a valid link partner, a valid link should be
995 * established. Assumes the hardware has previously been reset and the
996 * transmitter and receiver are not enabled.
997 *****************************************************************************/
998int32_t
999e1000_setup_link(struct e1000_hw *hw)
1000{
1001 uint32_t ctrl_ext;
1002 int32_t ret_val;
1003 uint16_t eeprom_data;
1004
1005 DEBUGFUNC("e1000_setup_link");
1006
526f9957
JK		 1007 /* In the case of the phy reset being blocked, we already have a link.
1008 * We do not have to set it up again. */
1009 if (e1000_check_phy_reset_block(hw))
1010 return E1000_SUCCESS;
1011
1da177e4
LT		 1012 /* Read and store word 0x0F of the EEPROM. This word contains bits
1013 * that determine the hardware's default PAUSE (flow control) mode,
1014 * a bit that determines whether the HW defaults to enabling or
1015 * disabling auto-negotiation, and the direction of the
1016 * SW defined pins. If there is no SW over-ride of the flow
1017 * control setting, then the variable hw->fc will
1018 * be initialized based on a value in the EEPROM.
1019 */
fd803241
JK		 1020 if (hw->fc == e1000_fc_default) {
1021 switch (hw->mac_type) {
cd94dd0b 1022 case e1000_ich8lan:
fd803241 1023 case e1000_82573:
1da177e4 1024 hw->fc = e1000_fc_full;
fd803241
JK		 1025 break;
1026 default:
1027 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1028 1, &eeprom_data);
1029 if (ret_val) {
1030 DEBUGOUT("EEPROM Read Error\n");
1031 return -E1000_ERR_EEPROM;
1032 }
1033 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1034 hw->fc = e1000_fc_none;
1035 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1036 EEPROM_WORD0F_ASM_DIR)
1037 hw->fc = e1000_fc_tx_pause;
1038 else
1039 hw->fc = e1000_fc_full;
1040 break;
1041 }
1da177e4
LT		 1042 }
1043
1044 /* We want to save off the original Flow Control configuration just
1045 * in case we get disconnected and then reconnected into a different
1046 * hub or switch with different Flow Control capabilities.
1047 */
8fc897b0 1048 if (hw->mac_type == e1000_82542_rev2_0)
1da177e4
LT		 1049 hw->fc &= (~e1000_fc_tx_pause);
1050
8fc897b0 1051 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1da177e4
LT		 1052 hw->fc &= (~e1000_fc_rx_pause);
1053
1054 hw->original_fc = hw->fc;
1055
1056 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
1057
1058 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1059 * polarity value for the SW controlled pins, and setup the
1060 * Extended Device Control reg with that info.
1061 * This is needed because one of the SW controlled pins is used for
1062 * signal detection. So this should be done before e1000_setup_pcs_link()
1063 * or e1000_phy_setup() is called.
1064 */
497fce5e 1065 if (hw->mac_type == e1000_82543) {
8fc897b0
AK		 1066 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1067 1, &eeprom_data);
1068 if (ret_val) {
1069 DEBUGOUT("EEPROM Read Error\n");
1070 return -E1000_ERR_EEPROM;
1071 }
1da177e4
LT		 1072 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1073 SWDPIO__EXT_SHIFT);
1074 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1075 }
1076
1077 /* Call the necessary subroutine to configure the link. */
1078 ret_val = (hw->media_type == e1000_media_type_copper) ?
1079 e1000_setup_copper_link(hw) :
1080 e1000_setup_fiber_serdes_link(hw);
1081
1082 /* Initialize the flow control address, type, and PAUSE timer
1083 * registers to their default values. This is done even if flow
1084 * control is disabled, because it does not hurt anything to
1085 * initialize these registers.
1086 */
1087 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1088
cd94dd0b
AK		 1089 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1090 if (hw->mac_type != e1000_ich8lan) {
1091 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1092 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1093 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1094 }
2d7edb92 1095
1da177e4
LT		 1096 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1097
1098 /* Set the flow control receive threshold registers. Normally,
1099 * these registers will be set to a default threshold that may be
1100 * adjusted later by the driver's runtime code. However, if the
1101 * ability to transmit pause frames in not enabled, then these
1102 * registers will be set to 0.
1103 */
8fc897b0 1104 if (!(hw->fc & e1000_fc_tx_pause)) {
1da177e4
LT		 1105 E1000_WRITE_REG(hw, FCRTL, 0);
1106 E1000_WRITE_REG(hw, FCRTH, 0);
1107 } else {
1108 /* We need to set up the Receive Threshold high and low water marks
1109 * as well as (optionally) enabling the transmission of XON frames.
1110 */
8fc897b0 1111 if (hw->fc_send_xon) {
1da177e4
LT		 1112 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
1113 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1114 } else {
1115 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1116 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1117 }
1118 }
1119 return ret_val;
1120}
1121
1122/******************************************************************************
1123 * Sets up link for a fiber based or serdes based adapter
1124 *
1125 * hw - Struct containing variables accessed by shared code
1126 *
1127 * Manipulates Physical Coding Sublayer functions in order to configure
1128 * link. Assumes the hardware has been previously reset and the transmitter
1129 * and receiver are not enabled.
1130 *****************************************************************************/
1131static int32_t
1132e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1133{
1134 uint32_t ctrl;
1135 uint32_t status;
1136 uint32_t txcw = 0;
1137 uint32_t i;
1138 uint32_t signal = 0;
1139 int32_t ret_val;
1140
1141 DEBUGFUNC("e1000_setup_fiber_serdes_link");
1142
868d5309
MC		 1143 /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists
1144 * until explicitly turned off or a power cycle is performed. A read to
1145 * the register does not indicate its status. Therefore, we ensure
1146 * loopback mode is disabled during initialization.
1147 */
1148 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572)
1149 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK);
1150
1da177e4
LT		 1151 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
1152 * set when the optics detect a signal. On older adapters, it will be
1153 * cleared when there is a signal. This applies to fiber media only.
1154 * If we're on serdes media, adjust the output amplitude to value set in
1155 * the EEPROM.
1156 */
1157 ctrl = E1000_READ_REG(hw, CTRL);
8fc897b0 1158 if (hw->media_type == e1000_media_type_fiber)
1da177e4
LT		 1159 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1160
1161 ret_val = e1000_adjust_serdes_amplitude(hw);
8fc897b0 1162 if (ret_val)
1da177e4
LT		 1163 return ret_val;
1164
1165 /* Take the link out of reset */
1166 ctrl &= ~(E1000_CTRL_LRST);
1167
1168 /* Adjust VCO speed to improve BER performance */
1169 ret_val = e1000_set_vco_speed(hw);
8fc897b0 1170 if (ret_val)
1da177e4
LT		 1171 return ret_val;
1172
1173 e1000_config_collision_dist(hw);
1174
1175 /* Check for a software override of the flow control settings, and setup
1176 * the device accordingly. If auto-negotiation is enabled, then software
1177 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1178 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
1179 * auto-negotiation is disabled, then software will have to manually
1180 * configure the two flow control enable bits in the CTRL register.
1181 *
1182 * The possible values of the "fc" parameter are:
1183 * 0: Flow control is completely disabled
1184 * 1: Rx flow control is enabled (we can receive pause frames, but
1185 * not send pause frames).
1186 * 2: Tx flow control is enabled (we can send pause frames but we do
1187 * not support receiving pause frames).
1188 * 3: Both Rx and TX flow control (symmetric) are enabled.
1189 */
1190 switch (hw->fc) {
1191 case e1000_fc_none:
1192 /* Flow control is completely disabled by a software over-ride. */
1193 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1194 break;
1195 case e1000_fc_rx_pause:
1196 /* RX Flow control is enabled and TX Flow control is disabled by a
1197 * software over-ride. Since there really isn't a way to advertise
1198 * that we are capable of RX Pause ONLY, we will advertise that we
1199 * support both symmetric and asymmetric RX PAUSE. Later, we will
1200 * disable the adapter's ability to send PAUSE frames.
1201 */
1202 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1203 break;
1204 case e1000_fc_tx_pause:
1205 /* TX Flow control is enabled, and RX Flow control is disabled, by a
1206 * software over-ride.
1207 */
1208 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1209 break;
1210 case e1000_fc_full:
1211 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1212 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1213 break;
1214 default:
1215 DEBUGOUT("Flow control param set incorrectly\n");
1216 return -E1000_ERR_CONFIG;
1217 break;
1218 }
1219
1220 /* Since auto-negotiation is enabled, take the link out of reset (the link
1221 * will be in reset, because we previously reset the chip). This will
1222 * restart auto-negotiation. If auto-neogtiation is successful then the
1223 * link-up status bit will be set and the flow control enable bits (RFCE
1224 * and TFCE) will be set according to their negotiated value.
1225 */
1226 DEBUGOUT("Auto-negotiation enabled\n");
1227
1228 E1000_WRITE_REG(hw, TXCW, txcw);
1229 E1000_WRITE_REG(hw, CTRL, ctrl);
1230 E1000_WRITE_FLUSH(hw);
1231
1232 hw->txcw = txcw;
f8ec4733 1233 msleep(1);
1da177e4
LT		 1234
1235 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
1236 * indication in the Device Status Register. Time-out if a link isn't
1237 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
1238 * less than 500 milliseconds even if the other end is doing it in SW).
1239 * For internal serdes, we just assume a signal is present, then poll.
1240 */
8fc897b0 1241 if (hw->media_type == e1000_media_type_internal_serdes ||
1da177e4
LT		 1242 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1243 DEBUGOUT("Looking for Link\n");
8fc897b0 1244 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
f8ec4733 1245 msleep(10);
1da177e4 1246 status = E1000_READ_REG(hw, STATUS);
8fc897b0 1247 if (status & E1000_STATUS_LU) break;
1da177e4 1248 }
8fc897b0 1249 if (i == (LINK_UP_TIMEOUT / 10)) {
1da177e4
LT		 1250 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1251 hw->autoneg_failed = 1;
1252 /* AutoNeg failed to achieve a link, so we'll call
1253 * e1000_check_for_link. This routine will force the link up if
1254 * we detect a signal. This will allow us to communicate with
1255 * non-autonegotiating link partners.
1256 */
1257 ret_val = e1000_check_for_link(hw);
8fc897b0 1258 if (ret_val) {
1da177e4
LT		 1259 DEBUGOUT("Error while checking for link\n");
1260 return ret_val;
1261 }
1262 hw->autoneg_failed = 0;
1263 } else {
1264 hw->autoneg_failed = 0;
1265 DEBUGOUT("Valid Link Found\n");
1266 }
1267 } else {
1268 DEBUGOUT("No Signal Detected\n");
1269 }
1270 return E1000_SUCCESS;
1271}
1272
1273/******************************************************************************
2d7edb92 1274* Make sure we have a valid PHY and change PHY mode before link setup.
1da177e4
LT		 1275*
1276* hw - Struct containing variables accessed by shared code
1277******************************************************************************/
1278static int32_t
2d7edb92 1279e1000_copper_link_preconfig(struct e1000_hw *hw)
1da177e4
LT		 1280{
1281 uint32_t ctrl;
1da177e4 1282 int32_t ret_val;
1da177e4
LT		 1283 uint16_t phy_data;
1284
2d7edb92 1285 DEBUGFUNC("e1000_copper_link_preconfig");
1da177e4
LT		 1286
1287 ctrl = E1000_READ_REG(hw, CTRL);
1288 /* With 82543, we need to force speed and duplex on the MAC equal to what
1289 * the PHY speed and duplex configuration is. In addition, we need to
1290 * perform a hardware reset on the PHY to take it out of reset.
1291 */
8fc897b0 1292 if (hw->mac_type > e1000_82543) {
1da177e4
LT		 1293 ctrl |= E1000_CTRL_SLU;
1294 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1295 E1000_WRITE_REG(hw, CTRL, ctrl);
1296 } else {
1297 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1298 E1000_WRITE_REG(hw, CTRL, ctrl);
2d7edb92 1299 ret_val = e1000_phy_hw_reset(hw);
8fc897b0 1300 if (ret_val)
2d7edb92 1301 return ret_val;
1da177e4
LT		 1302 }
1303
1304 /* Make sure we have a valid PHY */
1305 ret_val = e1000_detect_gig_phy(hw);
8fc897b0 1306 if (ret_val) {
1da177e4
LT		 1307 DEBUGOUT("Error, did not detect valid phy.\n");
1308 return ret_val;
1309 }
1310 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
1311
1312 /* Set PHY to class A mode (if necessary) */
1313 ret_val = e1000_set_phy_mode(hw);
8fc897b0 1314 if (ret_val)
1da177e4
LT		 1315 return ret_val;
1316
8fc897b0 1317 if ((hw->mac_type == e1000_82545_rev_3) ||
1da177e4
LT		 1318 (hw->mac_type == e1000_82546_rev_3)) {
1319 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1320 phy_data |= 0x00000008;
1321 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1322 }
1323
8fc897b0
AK		 1324 if (hw->mac_type <= e1000_82543 ||
1325 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1326 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
1da177e4
LT		 1327 hw->phy_reset_disable = FALSE;
1328
2d7edb92
MC		 1329 return E1000_SUCCESS;
1330}
1da177e4 1331
1da177e4 1332
2d7edb92
MC		 1333/********************************************************************
1334* Copper link setup for e1000_phy_igp series.
1335*
1336* hw - Struct containing variables accessed by shared code
1337*********************************************************************/
1338static int32_t
1339e1000_copper_link_igp_setup(struct e1000_hw *hw)
1340{
1341 uint32_t led_ctrl;
1342 int32_t ret_val;
1343 uint16_t phy_data;
1da177e4 1344
2d7edb92 1345 DEBUGFUNC("e1000_copper_link_igp_setup");
1da177e4 1346
2d7edb92
MC		 1347 if (hw->phy_reset_disable)
1348 return E1000_SUCCESS;
76c224bc 1349
2d7edb92
MC		 1350 ret_val = e1000_phy_reset(hw);
1351 if (ret_val) {
1352 DEBUGOUT("Error Resetting the PHY\n");
1353 return ret_val;
1354 }
1da177e4 1355
8fc897b0 1356 /* Wait 15ms for MAC to configure PHY from eeprom settings */
f8ec4733 1357 msleep(15);
cd94dd0b 1358 if (hw->mac_type != e1000_ich8lan) {
2d7edb92
MC		 1359 /* Configure activity LED after PHY reset */
1360 led_ctrl = E1000_READ_REG(hw, LEDCTL);
1361 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1362 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1363 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
cd94dd0b 1364 }
1da177e4 1365
c9c1b834
JK		 1366 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
1367 if (hw->phy_type == e1000_phy_igp) {
1368 /* disable lplu d3 during driver init */
1369 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
1370 if (ret_val) {
1371 DEBUGOUT("Error Disabling LPLU D3\n");
1372 return ret_val;
1373 }
2d7edb92 1374 }
1da177e4 1375
2d7edb92
MC		 1376 /* disable lplu d0 during driver init */
1377 ret_val = e1000_set_d0_lplu_state(hw, FALSE);
1378 if (ret_val) {
1379 DEBUGOUT("Error Disabling LPLU D0\n");
1380 return ret_val;
1381 }
1382 /* Configure mdi-mdix settings */
1383 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1384 if (ret_val)
1385 return ret_val;
1da177e4 1386
2d7edb92
MC		 1387 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1388 hw->dsp_config_state = e1000_dsp_config_disabled;
1389 /* Force MDI for earlier revs of the IGP PHY */
1390 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);
1391 hw->mdix = 1;
1da177e4 1392
2d7edb92
MC		 1393 } else {
1394 hw->dsp_config_state = e1000_dsp_config_enabled;
1395 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1da177e4 1396
2d7edb92
MC		 1397 switch (hw->mdix) {
1398 case 1:
1399 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1400 break;
1401 case 2:
1402 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1403 break;
1404 case 0:
1405 default:
1406 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1407 break;
1408 }
1409 }
1410 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
8fc897b0 1411 if (ret_val)
2d7edb92 1412 return ret_val;
1da177e4 1413
2d7edb92 1414 /* set auto-master slave resolution settings */
8fc897b0 1415 if (hw->autoneg) {
2d7edb92 1416 e1000_ms_type phy_ms_setting = hw->master_slave;
1da177e4 1417
8fc897b0 1418 if (hw->ffe_config_state == e1000_ffe_config_active)
2d7edb92 1419 hw->ffe_config_state = e1000_ffe_config_enabled;
1da177e4 1420
8fc897b0 1421 if (hw->dsp_config_state == e1000_dsp_config_activated)
2d7edb92 1422 hw->dsp_config_state = e1000_dsp_config_enabled;
1da177e4 1423
2d7edb92
MC		 1424 /* when autonegotiation advertisment is only 1000Mbps then we
1425 * should disable SmartSpeed and enable Auto MasterSlave
1426 * resolution as hardware default. */
8fc897b0 1427 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
2d7edb92 1428 /* Disable SmartSpeed */
8fc897b0
AK		 1429 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1430 &phy_data);
1431 if (ret_val)
1da177e4 1432 return ret_val;
2d7edb92 1433 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
8fc897b0
AK		 1434 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1435 phy_data);
1436 if (ret_val)
1da177e4 1437 return ret_val;
2d7edb92
MC		 1438 /* Set auto Master/Slave resolution process */
1439 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
8fc897b0 1440 if (ret_val)
2d7edb92
MC		 1441 return ret_val;
1442 phy_data &= ~CR_1000T_MS_ENABLE;
1443 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
8fc897b0 1444 if (ret_val)
2d7edb92
MC		 1445 return ret_val;
1446 }
1da177e4 1447
2d7edb92 1448 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
8fc897b0 1449 if (ret_val)
2d7edb92 1450 return ret_val;
1da177e4 1451
2d7edb92
MC		 1452 /* load defaults for future use */
1453 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1454 ((phy_data & CR_1000T_MS_VALUE) ?
1455 e1000_ms_force_master :
1456 e1000_ms_force_slave) :
1457 e1000_ms_auto;
1da177e4 1458
2d7edb92
MC		 1459 switch (phy_ms_setting) {
1460 case e1000_ms_force_master:
1461 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1462 break;
1463 case e1000_ms_force_slave:
1464 phy_data |= CR_1000T_MS_ENABLE;
1465 phy_data &= ~(CR_1000T_MS_VALUE);
1466 break;
1467 case e1000_ms_auto:
1468 phy_data &= ~CR_1000T_MS_ENABLE;
1469 default:
1470 break;
1471 }
1472 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
8fc897b0 1473 if (ret_val)
2d7edb92 1474 return ret_val;
2b02893e 1475 }
1da177e4 1476
2b02893e 1477 return E1000_SUCCESS;
2d7edb92 1478}
1da177e4 1479
6418ecc6
JK		 1480/********************************************************************
1481* Copper link setup for e1000_phy_gg82563 series.
1482*
1483* hw - Struct containing variables accessed by shared code
1484*********************************************************************/
1485static int32_t
1486e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1487{
1488 int32_t ret_val;
1489 uint16_t phy_data;
1490 uint32_t reg_data;
1491
1492 DEBUGFUNC("e1000_copper_link_ggp_setup");
1493
8fc897b0 1494 if (!hw->phy_reset_disable) {
76c224bc 1495
6418ecc6
JK		 1496 /* Enable CRS on TX for half-duplex operation. */
1497 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1498 &phy_data);
8fc897b0 1499 if (ret_val)
6418ecc6
JK		 1500 return ret_val;
1501
1502 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1503 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
1504 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
1505
1506 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1507 phy_data);
8fc897b0 1508 if (ret_val)
6418ecc6
JK		 1509 return ret_val;
1510
1511 /* Options:
1512 * MDI/MDI-X = 0 (default)
1513 * 0 - Auto for all speeds
1514 * 1 - MDI mode
1515 * 2 - MDI-X mode
1516 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1517 */
1518 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
8fc897b0 1519 if (ret_val)
6418ecc6
JK		 1520 return ret_val;
1521
1522 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1523
1524 switch (hw->mdix) {
1525 case 1:
1526 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1527 break;
1528 case 2:
1529 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1530 break;
1531 case 0:
1532 default:
1533 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1534 break;
1535 }
1536
1537 /* Options:
1538 * disable_polarity_correction = 0 (default)
1539 * Automatic Correction for Reversed Cable Polarity
1540 * 0 - Disabled
1541 * 1 - Enabled
1542 */
1543 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
8fc897b0 1544 if (hw->disable_polarity_correction == 1)
6418ecc6
JK		 1545 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1546 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
1547
8fc897b0 1548 if (ret_val)
6418ecc6
JK		 1549 return ret_val;
1550
1551 /* SW Reset the PHY so all changes take effect */
1552 ret_val = e1000_phy_reset(hw);
1553 if (ret_val) {
1554 DEBUGOUT("Error Resetting the PHY\n");
1555 return ret_val;
1556 }
1557 } /* phy_reset_disable */
1558
1559 if (hw->mac_type == e1000_80003es2lan) {
1560 /* Bypass RX and TX FIFO's */
1561 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
1562 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS |
1563 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
1564 if (ret_val)
1565 return ret_val;
1566
1567 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data);
1568 if (ret_val)
1569 return ret_val;
1570
1571 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1572 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data);
1573
1574 if (ret_val)
1575 return ret_val;
1576
1577 reg_data = E1000_READ_REG(hw, CTRL_EXT);
1578 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1579 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
1580
1581 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1582 &phy_data);
1583 if (ret_val)
1584 return ret_val;
1585
1586 /* Do not init these registers when the HW is in IAMT mode, since the
1587 * firmware will have already initialized them. We only initialize
1588 * them if the HW is not in IAMT mode.
1589 */
1590 if (e1000_check_mng_mode(hw) == FALSE) {
1591 /* Enable Electrical Idle on the PHY */
1592 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1593 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1594 phy_data);
1595 if (ret_val)
1596 return ret_val;
1597
1598 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1599 &phy_data);
1600 if (ret_val)
1601 return ret_val;
1602
cd94dd0b 1603 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
6418ecc6
JK		 1604 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1605 phy_data);
8fc897b0 1606
6418ecc6
JK		 1607 if (ret_val)
1608 return ret_val;
1609 }
1610
1611 /* Workaround: Disable padding in Kumeran interface in the MAC
1612 * and in the PHY to avoid CRC errors.
1613 */
1614 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1615 &phy_data);
1616 if (ret_val)
1617 return ret_val;
1618 phy_data |= GG82563_ICR_DIS_PADDING;
1619 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1620 phy_data);
1621 if (ret_val)
1622 return ret_val;
1623 }
1624
1625 return E1000_SUCCESS;
1626}
1da177e4 1627
2d7edb92
MC		 1628/********************************************************************
1629* Copper link setup for e1000_phy_m88 series.
1630*
1631* hw - Struct containing variables accessed by shared code
1632*********************************************************************/
1633static int32_t
1634e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1635{
1636 int32_t ret_val;
1637 uint16_t phy_data;
1da177e4 1638
2d7edb92 1639 DEBUGFUNC("e1000_copper_link_mgp_setup");
1da177e4 1640
8fc897b0 1641 if (hw->phy_reset_disable)
2d7edb92 1642 return E1000_SUCCESS;
76c224bc 1643
2d7edb92
MC		 1644 /* Enable CRS on TX. This must be set for half-duplex operation. */
1645 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
8fc897b0 1646 if (ret_val)
2d7edb92 1647 return ret_val;
1da177e4 1648
2d7edb92 1649 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1da177e4 1650
2d7edb92
MC		 1651 /* Options:
1652 * MDI/MDI-X = 0 (default)
1653 * 0 - Auto for all speeds
1654 * 1 - MDI mode
1655 * 2 - MDI-X mode
1656 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1657 */
1658 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1da177e4 1659
2d7edb92
MC		 1660 switch (hw->mdix) {
1661 case 1:
1662 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1663 break;
1664 case 2:
1665 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1666 break;
1667 case 3:
1668 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1669 break;
1670 case 0:
1671 default:
1672 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1673 break;
1674 }
1675
1676 /* Options:
1677 * disable_polarity_correction = 0 (default)
1678 * Automatic Correction for Reversed Cable Polarity
1679 * 0 - Disabled
1680 * 1 - Enabled
1da177e4 1681 */
2d7edb92 1682 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
8fc897b0 1683 if (hw->disable_polarity_correction == 1)
2d7edb92 1684 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
ee04022a
AK		 1685 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1686 if (ret_val)
2d7edb92
MC		 1687 return ret_val;
1688
2d7edb92 1689 if (hw->phy_revision < M88E1011_I_REV_4) {
ee04022a
AK		 1690 /* Force TX_CLK in the Extended PHY Specific Control Register
1691 * to 25MHz clock.
1692 */
1693 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1694 if (ret_val)
1695 return ret_val;
1696
1697 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1698
1699 if ((hw->phy_revision == E1000_REVISION_2) &&
1700 (hw->phy_id == M88E1111_I_PHY_ID)) {
1701 /* Vidalia Phy, set the downshift counter to 5x */
1702 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1703 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1704 ret_val = e1000_write_phy_reg(hw,
1705 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1706 if (ret_val)
1707 return ret_val;
1708 } else {
1709 /* Configure Master and Slave downshift values */
1710 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
2d7edb92 1711 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
ee04022a 1712 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
2d7edb92 1713 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
ee04022a
AK		 1714 ret_val = e1000_write_phy_reg(hw,
1715 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1716 if (ret_val)
1717 return ret_val;
1718 }
2d7edb92 1719 }
1da177e4 1720
2d7edb92
MC		 1721 /* SW Reset the PHY so all changes take effect */
1722 ret_val = e1000_phy_reset(hw);
8fc897b0 1723 if (ret_val) {
2d7edb92
MC		 1724 DEBUGOUT("Error Resetting the PHY\n");
1725 return ret_val;
1da177e4
LT		 1726 }
1727
2d7edb92 1728 return E1000_SUCCESS;
1da177e4
LT		 1729}
1730
2d7edb92
MC		 1731/********************************************************************
1732* Setup auto-negotiation and flow control advertisements,
1733* and then perform auto-negotiation.
1da177e4
LT		 1734*
1735* hw - Struct containing variables accessed by shared code
2d7edb92
MC		 1736*********************************************************************/
1737static int32_t
1738e1000_copper_link_autoneg(struct e1000_hw *hw)
1da177e4
LT		 1739{
1740 int32_t ret_val;
2d7edb92 1741 uint16_t phy_data;
1da177e4 1742
2d7edb92 1743 DEBUGFUNC("e1000_copper_link_autoneg");
1da177e4 1744
2d7edb92
MC		 1745 /* Perform some bounds checking on the hw->autoneg_advertised
1746 * parameter. If this variable is zero, then set it to the default.
1747 */
1748 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1749
1750 /* If autoneg_advertised is zero, we assume it was not defaulted
1751 * by the calling code so we set to advertise full capability.
1752 */
8fc897b0 1753 if (hw->autoneg_advertised == 0)
2d7edb92
MC		 1754 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1755
cd94dd0b
AK		 1756 /* IFE phy only supports 10/100 */
1757 if (hw->phy_type == e1000_phy_ife)
1758 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1759
2d7edb92
MC		 1760 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1761 ret_val = e1000_phy_setup_autoneg(hw);
8fc897b0 1762 if (ret_val) {
2d7edb92
MC		 1763 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1764 return ret_val;
1765 }
1766 DEBUGOUT("Restarting Auto-Neg\n");
1767
1768 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1769 * the Auto Neg Restart bit in the PHY control register.
1770 */
1771 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
8fc897b0 1772 if (ret_val)
1da177e4
LT		 1773 return ret_val;
1774
2d7edb92
MC		 1775 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1776 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
8fc897b0 1777 if (ret_val)
1da177e4
LT		 1778 return ret_val;
1779
2d7edb92
MC		 1780 /* Does the user want to wait for Auto-Neg to complete here, or
1781 * check at a later time (for example, callback routine).
1782 */
8fc897b0 1783 if (hw->wait_autoneg_complete) {
2d7edb92 1784 ret_val = e1000_wait_autoneg(hw);
8fc897b0 1785 if (ret_val) {
2d7edb92
MC		 1786 DEBUGOUT("Error while waiting for autoneg to complete\n");
1787 return ret_val;
1788 }
1789 }
1790
1791 hw->get_link_status = TRUE;
1792
1793 return E1000_SUCCESS;
1794}
1795
2d7edb92
MC		 1796/******************************************************************************
1797* Config the MAC and the PHY after link is up.
1798* 1) Set up the MAC to the current PHY speed/duplex
1799* if we are on 82543. If we
1800* are on newer silicon, we only need to configure
1801* collision distance in the Transmit Control Register.
1802* 2) Set up flow control on the MAC to that established with
1803* the link partner.
76c224bc 1804* 3) Config DSP to improve Gigabit link quality for some PHY revisions.
2d7edb92
MC		 1805*
1806* hw - Struct containing variables accessed by shared code
1807******************************************************************************/
1808static int32_t
1809e1000_copper_link_postconfig(struct e1000_hw *hw)
1810{
1811 int32_t ret_val;
1812 DEBUGFUNC("e1000_copper_link_postconfig");
76c224bc 1813
8fc897b0 1814 if (hw->mac_type >= e1000_82544) {
2d7edb92
MC		 1815 e1000_config_collision_dist(hw);
1816 } else {
1817 ret_val = e1000_config_mac_to_phy(hw);
8fc897b0 1818 if (ret_val) {
2d7edb92
MC		 1819 DEBUGOUT("Error configuring MAC to PHY settings\n");
1820 return ret_val;
1821 }
1822 }
1823 ret_val = e1000_config_fc_after_link_up(hw);
8fc897b0 1824 if (ret_val) {
2d7edb92
MC		 1825 DEBUGOUT("Error Configuring Flow Control\n");
1826 return ret_val;
1827 }
1828
1829 /* Config DSP to improve Giga link quality */
8fc897b0 1830 if (hw->phy_type == e1000_phy_igp) {
2d7edb92 1831 ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
8fc897b0 1832 if (ret_val) {
2d7edb92
MC		 1833 DEBUGOUT("Error Configuring DSP after link up\n");
1834 return ret_val;
1835 }
1836 }
76c224bc 1837
2d7edb92
MC		 1838 return E1000_SUCCESS;
1839}
1840
1841/******************************************************************************
1842* Detects which PHY is present and setup the speed and duplex
1843*
1844* hw - Struct containing variables accessed by shared code
1845******************************************************************************/
1846static int32_t
1847e1000_setup_copper_link(struct e1000_hw *hw)
1848{
1849 int32_t ret_val;
1850 uint16_t i;
1851 uint16_t phy_data;
6418ecc6 1852 uint16_t reg_data;
2d7edb92
MC		 1853
1854 DEBUGFUNC("e1000_setup_copper_link");
1855
cd94dd0b
AK		 1856 switch (hw->mac_type) {
1857 case e1000_80003es2lan:
1858 case e1000_ich8lan:
1859 /* Set the mac to wait the maximum time between each
1860 * iteration and increase the max iterations when
1861 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
1862 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
1863 if (ret_val)
1864 return ret_val;
1865 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
1866 if (ret_val)
1867 return ret_val;
1868 reg_data |= 0x3F;
1869 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
1870 if (ret_val)
1871 return ret_val;
1872 default:
1873 break;
1874 }
1875
2d7edb92
MC		 1876 /* Check if it is a valid PHY and set PHY mode if necessary. */
1877 ret_val = e1000_copper_link_preconfig(hw);
8fc897b0 1878 if (ret_val)
2d7edb92
MC		 1879 return ret_val;
1880
6418ecc6
JK		 1881 switch (hw->mac_type) {
1882 case e1000_80003es2lan:
cd94dd0b
AK		 1883 /* Kumeran registers are written-only */
1884 reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
6418ecc6
JK		 1885 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
1886 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
1887 reg_data);
1888 if (ret_val)
1889 return ret_val;
1890 break;
1891 default:
1892 break;
1893 }
1894
2d7edb92 1895 if (hw->phy_type == e1000_phy_igp ||
cd94dd0b 1896 hw->phy_type == e1000_phy_igp_3 ||
2d7edb92
MC		 1897 hw->phy_type == e1000_phy_igp_2) {
1898 ret_val = e1000_copper_link_igp_setup(hw);
8fc897b0 1899 if (ret_val)
2d7edb92
MC		 1900 return ret_val;
1901 } else if (hw->phy_type == e1000_phy_m88) {
1902 ret_val = e1000_copper_link_mgp_setup(hw);
8fc897b0 1903 if (ret_val)
2d7edb92 1904 return ret_val;
6418ecc6
JK		 1905 } else if (hw->phy_type == e1000_phy_gg82563) {
1906 ret_val = e1000_copper_link_ggp_setup(hw);
8fc897b0 1907 if (ret_val)
6418ecc6 1908 return ret_val;
2d7edb92
MC		 1909 }
1910
8fc897b0 1911 if (hw->autoneg) {
76c224bc
AK		 1912 /* Setup autoneg and flow control advertisement
1913 * and perform autonegotiation */
2d7edb92 1914 ret_val = e1000_copper_link_autoneg(hw);
8fc897b0 1915 if (ret_val)
76c224bc 1916 return ret_val;
2d7edb92
MC		 1917 } else {
1918 /* PHY will be set to 10H, 10F, 100H,or 100F
1919 * depending on value from forced_speed_duplex. */
1920 DEBUGOUT("Forcing speed and duplex\n");
1921 ret_val = e1000_phy_force_speed_duplex(hw);
8fc897b0 1922 if (ret_val) {
2d7edb92
MC		 1923 DEBUGOUT("Error Forcing Speed and Duplex\n");
1924 return ret_val;
1925 }
1926 }
1927
1928 /* Check link status. Wait up to 100 microseconds for link to become
1929 * valid.
1930 */
8fc897b0 1931 for (i = 0; i < 10; i++) {
2d7edb92 1932 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 1933 if (ret_val)
2d7edb92
MC		 1934 return ret_val;
1935 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 1936 if (ret_val)
2d7edb92
MC		 1937 return ret_val;
1938
8fc897b0 1939 if (phy_data & MII_SR_LINK_STATUS) {
2d7edb92
MC		 1940 /* Config the MAC and PHY after link is up */
1941 ret_val = e1000_copper_link_postconfig(hw);
8fc897b0 1942 if (ret_val)
2d7edb92 1943 return ret_val;
76c224bc 1944
2d7edb92
MC		 1945 DEBUGOUT("Valid link established!!!\n");
1946 return E1000_SUCCESS;
1947 }
1948 udelay(10);
1949 }
1950
1951 DEBUGOUT("Unable to establish link!!!\n");
1952 return E1000_SUCCESS;
1953}
1954
6418ecc6
JK		 1955/******************************************************************************
1956* Configure the MAC-to-PHY interface for 10/100Mbps
1957*
1958* hw - Struct containing variables accessed by shared code
1959******************************************************************************/
1960static int32_t
cd94dd0b 1961e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
6418ecc6
JK		 1962{
1963 int32_t ret_val = E1000_SUCCESS;
1964 uint32_t tipg;
1965 uint16_t reg_data;
1966
1967 DEBUGFUNC("e1000_configure_kmrn_for_10_100");
1968
1969 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
1970 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
1971 reg_data);
1972 if (ret_val)
1973 return ret_val;
1974
1975 /* Configure Transmit Inter-Packet Gap */
1976 tipg = E1000_READ_REG(hw, TIPG);
1977 tipg &= ~E1000_TIPG_IPGT_MASK;
1978 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
1979 E1000_WRITE_REG(hw, TIPG, tipg);
1980
cd94dd0b
AK		 1981 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1982
1983 if (ret_val)
1984 return ret_val;
1985
1986 if (duplex == HALF_DUPLEX)
1987 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1988 else
1989 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1990
1991 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1992
6418ecc6
JK		 1993 return ret_val;
1994}
1995
1996static int32_t
1997e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
1998{
1999 int32_t ret_val = E1000_SUCCESS;
2000 uint16_t reg_data;
2001 uint32_t tipg;
2002
2003 DEBUGFUNC("e1000_configure_kmrn_for_1000");
2004
2005 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
2006 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
2007 reg_data);
2008 if (ret_val)
2009 return ret_val;
2010
2011 /* Configure Transmit Inter-Packet Gap */
2012 tipg = E1000_READ_REG(hw, TIPG);
2013 tipg &= ~E1000_TIPG_IPGT_MASK;
2014 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
2015 E1000_WRITE_REG(hw, TIPG, tipg);
2016
cd94dd0b
AK		 2017 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
2018
2019 if (ret_val)
2020 return ret_val;
2021
2022 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2023 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2024
6418ecc6
JK		 2025 return ret_val;
2026}
2027
2d7edb92
MC		 2028/******************************************************************************
2029* Configures PHY autoneg and flow control advertisement settings
2030*
2031* hw - Struct containing variables accessed by shared code
2032******************************************************************************/
2033int32_t
2034e1000_phy_setup_autoneg(struct e1000_hw *hw)
2035{
2036 int32_t ret_val;
2037 uint16_t mii_autoneg_adv_reg;
2038 uint16_t mii_1000t_ctrl_reg;
2039
2040 DEBUGFUNC("e1000_phy_setup_autoneg");
2041
2042 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2043 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
8fc897b0 2044 if (ret_val)
2d7edb92
MC		 2045 return ret_val;
2046
cd94dd0b
AK		 2047 if (hw->phy_type != e1000_phy_ife) {
2048 /* Read the MII 1000Base-T Control Register (Address 9). */
2049 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
2050 if (ret_val)
2051 return ret_val;
2052 } else
2053 mii_1000t_ctrl_reg=0;
2d7edb92
MC		 2054
2055 /* Need to parse both autoneg_advertised and fc and set up
2056 * the appropriate PHY registers. First we will parse for
1da177e4
LT		 2057 * autoneg_advertised software override. Since we can advertise
2058 * a plethora of combinations, we need to check each bit
2059 * individually.
2060 */
2061
2062 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2063 * Advertisement Register (Address 4) and the 1000 mb speed bits in
2064 * the 1000Base-T Control Register (Address 9).
2065 */
2066 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
2067 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
2068
2069 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
2070
2071 /* Do we want to advertise 10 Mb Half Duplex? */
8fc897b0 2072 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
1da177e4
LT		 2073 DEBUGOUT("Advertise 10mb Half duplex\n");
2074 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
2075 }
2076
2077 /* Do we want to advertise 10 Mb Full Duplex? */
8fc897b0 2078 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
1da177e4
LT		 2079 DEBUGOUT("Advertise 10mb Full duplex\n");
2080 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
2081 }
2082
2083 /* Do we want to advertise 100 Mb Half Duplex? */
8fc897b0 2084 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
1da177e4
LT		 2085 DEBUGOUT("Advertise 100mb Half duplex\n");
2086 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
2087 }
2088
2089 /* Do we want to advertise 100 Mb Full Duplex? */
8fc897b0 2090 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
1da177e4
LT		 2091 DEBUGOUT("Advertise 100mb Full duplex\n");
2092 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
2093 }
2094
2095 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
8fc897b0 2096 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1da177e4
LT		 2097 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
2098 }
2099
2100 /* Do we want to advertise 1000 Mb Full Duplex? */
8fc897b0 2101 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1da177e4
LT		 2102 DEBUGOUT("Advertise 1000mb Full duplex\n");
2103 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
cd94dd0b
AK		 2104 if (hw->phy_type == e1000_phy_ife) {
2105 DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n");
2106 }
1da177e4
LT		 2107 }
2108
2109 /* Check for a software override of the flow control settings, and
2110 * setup the PHY advertisement registers accordingly. If
2111 * auto-negotiation is enabled, then software will have to set the
2112 * "PAUSE" bits to the correct value in the Auto-Negotiation
2113 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
2114 *
2115 * The possible values of the "fc" parameter are:
2116 * 0: Flow control is completely disabled
2117 * 1: Rx flow control is enabled (we can receive pause frames
2118 * but not send pause frames).
2119 * 2: Tx flow control is enabled (we can send pause frames
2120 * but we do not support receiving pause frames).
2121 * 3: Both Rx and TX flow control (symmetric) are enabled.
2122 * other: No software override. The flow control configuration
2123 * in the EEPROM is used.
2124 */
2125 switch (hw->fc) {
2126 case e1000_fc_none: /* 0 */
2127 /* Flow control (RX & TX) is completely disabled by a
2128 * software over-ride.
2129 */
2130 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2131 break;
2132 case e1000_fc_rx_pause: /* 1 */
2133 /* RX Flow control is enabled, and TX Flow control is
2134 * disabled, by a software over-ride.
2135 */
2136 /* Since there really isn't a way to advertise that we are
2137 * capable of RX Pause ONLY, we will advertise that we
2138 * support both symmetric and asymmetric RX PAUSE. Later
2139 * (in e1000_config_fc_after_link_up) we will disable the
2140 *hw's ability to send PAUSE frames.
2141 */
2142 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2143 break;
2144 case e1000_fc_tx_pause: /* 2 */
2145 /* TX Flow control is enabled, and RX Flow control is
2146 * disabled, by a software over-ride.
2147 */
2148 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
2149 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
2150 break;
2151 case e1000_fc_full: /* 3 */
2152 /* Flow control (both RX and TX) is enabled by a software
2153 * over-ride.
2154 */
2155 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2156 break;
2157 default:
2158 DEBUGOUT("Flow control param set incorrectly\n");
2159 return -E1000_ERR_CONFIG;
2160 }
2161
2162 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
8fc897b0 2163 if (ret_val)
1da177e4
LT		 2164 return ret_val;
2165
2166 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
2167
cd94dd0b
AK		 2168 if (hw->phy_type != e1000_phy_ife) {
2169 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
2170 if (ret_val)
2171 return ret_val;
2172 }
1da177e4
LT		 2173
2174 return E1000_SUCCESS;
2175}
2176
2177/******************************************************************************
2178* Force PHY speed and duplex settings to hw->forced_speed_duplex
2179*
2180* hw - Struct containing variables accessed by shared code
2181******************************************************************************/
2182static int32_t
2183e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2184{
2185 uint32_t ctrl;
2186 int32_t ret_val;
2187 uint16_t mii_ctrl_reg;
2188 uint16_t mii_status_reg;
2189 uint16_t phy_data;
2190 uint16_t i;
2191
2192 DEBUGFUNC("e1000_phy_force_speed_duplex");
2193
2194 /* Turn off Flow control if we are forcing speed and duplex. */
2195 hw->fc = e1000_fc_none;
2196
2197 DEBUGOUT1("hw->fc = %d\n", hw->fc);
2198
2199 /* Read the Device Control Register. */
2200 ctrl = E1000_READ_REG(hw, CTRL);
2201
2202 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
2203 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2204 ctrl &= ~(DEVICE_SPEED_MASK);
2205
2206 /* Clear the Auto Speed Detect Enable bit. */
2207 ctrl &= ~E1000_CTRL_ASDE;
2208
2209 /* Read the MII Control Register. */
2210 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
8fc897b0 2211 if (ret_val)
1da177e4
LT		 2212 return ret_val;
2213
2214 /* We need to disable autoneg in order to force link and duplex. */
2215
2216 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
2217
2218 /* Are we forcing Full or Half Duplex? */
8fc897b0
AK		 2219 if (hw->forced_speed_duplex == e1000_100_full ||
2220 hw->forced_speed_duplex == e1000_10_full) {
1da177e4
LT		 2221 /* We want to force full duplex so we SET the full duplex bits in the
2222 * Device and MII Control Registers.
2223 */
2224 ctrl |= E1000_CTRL_FD;
2225 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
2226 DEBUGOUT("Full Duplex\n");
2227 } else {
2228 /* We want to force half duplex so we CLEAR the full duplex bits in
2229 * the Device and MII Control Registers.
2230 */
2231 ctrl &= ~E1000_CTRL_FD;
2232 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
2233 DEBUGOUT("Half Duplex\n");
2234 }
2235
2236 /* Are we forcing 100Mbps??? */
8fc897b0 2237 if (hw->forced_speed_duplex == e1000_100_full ||
1da177e4
LT		 2238 hw->forced_speed_duplex == e1000_100_half) {
2239 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
2240 ctrl |= E1000_CTRL_SPD_100;
2241 mii_ctrl_reg |= MII_CR_SPEED_100;
2242 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
2243 DEBUGOUT("Forcing 100mb ");
2244 } else {
2245 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
2246 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2247 mii_ctrl_reg |= MII_CR_SPEED_10;
2248 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2249 DEBUGOUT("Forcing 10mb ");
2250 }
2251
2252 e1000_config_collision_dist(hw);
2253
2254 /* Write the configured values back to the Device Control Reg. */
2255 E1000_WRITE_REG(hw, CTRL, ctrl);
2256
6418ecc6
JK		 2257 if ((hw->phy_type == e1000_phy_m88) ||
2258 (hw->phy_type == e1000_phy_gg82563)) {
1da177e4 2259 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
8fc897b0 2260 if (ret_val)
1da177e4
LT		 2261 return ret_val;
2262
2263 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
2264 * forced whenever speed are duplex are forced.
2265 */
2266 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2267 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
8fc897b0 2268 if (ret_val)
1da177e4
LT		 2269 return ret_val;
2270
2271 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
2272
2273 /* Need to reset the PHY or these changes will be ignored */
2274 mii_ctrl_reg |= MII_CR_RESET;
cd94dd0b
AK		 2275 /* Disable MDI-X support for 10/100 */
2276 } else if (hw->phy_type == e1000_phy_ife) {
2277 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
2278 if (ret_val)
2279 return ret_val;
2280
2281 phy_data &= ~IFE_PMC_AUTO_MDIX;
2282 phy_data &= ~IFE_PMC_FORCE_MDIX;
2283
2284 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
2285 if (ret_val)
2286 return ret_val;
1da177e4
LT		 2287 } else {
2288 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
2289 * forced whenever speed or duplex are forced.
2290 */
2291 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
8fc897b0 2292 if (ret_val)
1da177e4
LT		 2293 return ret_val;
2294
2295 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2296 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2297
2298 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
8fc897b0 2299 if (ret_val)
1da177e4
LT		 2300 return ret_val;
2301 }
2302
2303 /* Write back the modified PHY MII control register. */
2304 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
8fc897b0 2305 if (ret_val)
1da177e4
LT		 2306 return ret_val;
2307
2308 udelay(1);
2309
2310 /* The wait_autoneg_complete flag may be a little misleading here.
2311 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
2312 * But we do want to delay for a period while forcing only so we
2313 * don't generate false No Link messages. So we will wait here
2314 * only if the user has set wait_autoneg_complete to 1, which is
2315 * the default.
2316 */
8fc897b0 2317 if (hw->wait_autoneg_complete) {
1da177e4
LT		 2318 /* We will wait for autoneg to complete. */
2319 DEBUGOUT("Waiting for forced speed/duplex link.\n");
2320 mii_status_reg = 0;
2321
2322 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
8fc897b0 2323 for (i = PHY_FORCE_TIME; i > 0; i--) {
1da177e4
LT		 2324 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2325 * to be set.
2326 */
2327 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 2328 if (ret_val)
1da177e4
LT		 2329 return ret_val;
2330
2331 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 2332 if (ret_val)
1da177e4
LT		 2333 return ret_val;
2334
8fc897b0 2335 if (mii_status_reg & MII_SR_LINK_STATUS) break;
f8ec4733 2336 msleep(100);
1da177e4 2337 }
8fc897b0 2338 if ((i == 0) &&
6418ecc6
JK		 2339 ((hw->phy_type == e1000_phy_m88) ||
2340 (hw->phy_type == e1000_phy_gg82563))) {
1da177e4
LT		 2341 /* We didn't get link. Reset the DSP and wait again for link. */
2342 ret_val = e1000_phy_reset_dsp(hw);
8fc897b0 2343 if (ret_val) {
1da177e4
LT		 2344 DEBUGOUT("Error Resetting PHY DSP\n");
2345 return ret_val;
2346 }
2347 }
2348 /* This loop will early-out if the link condition has been met. */
8fc897b0
AK		 2349 for (i = PHY_FORCE_TIME; i > 0; i--) {
2350 if (mii_status_reg & MII_SR_LINK_STATUS) break;
f8ec4733 2351 msleep(100);
1da177e4
LT		 2352 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2353 * to be set.
2354 */
2355 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 2356 if (ret_val)
1da177e4
LT		 2357 return ret_val;
2358
2359 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 2360 if (ret_val)
1da177e4
LT		 2361 return ret_val;
2362 }
2363 }
2364
2365 if (hw->phy_type == e1000_phy_m88) {
2366 /* Because we reset the PHY above, we need to re-force TX_CLK in the
2367 * Extended PHY Specific Control Register to 25MHz clock. This value
2368 * defaults back to a 2.5MHz clock when the PHY is reset.
2369 */
2370 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
8fc897b0 2371 if (ret_val)
1da177e4
LT		 2372 return ret_val;
2373
2374 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2375 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
8fc897b0 2376 if (ret_val)
1da177e4
LT		 2377 return ret_val;
2378
2379 /* In addition, because of the s/w reset above, we need to enable CRS on
2380 * TX. This must be set for both full and half duplex operation.
2381 */
2382 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
8fc897b0 2383 if (ret_val)
1da177e4
LT		 2384 return ret_val;
2385
2386 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2387 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
8fc897b0 2388 if (ret_val)
1da177e4
LT		 2389 return ret_val;
2390
8fc897b0
AK		 2391 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2392 (!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full ||
2393 hw->forced_speed_duplex == e1000_10_half)) {
1da177e4 2394 ret_val = e1000_polarity_reversal_workaround(hw);
8fc897b0 2395 if (ret_val)
1da177e4
LT		 2396 return ret_val;
2397 }
6418ecc6
JK		 2398 } else if (hw->phy_type == e1000_phy_gg82563) {
2399 /* The TX_CLK of the Extended PHY Specific Control Register defaults
2400 * to 2.5MHz on a reset. We need to re-force it back to 25MHz, if
2401 * we're not in a forced 10/duplex configuration. */
2402 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2403 if (ret_val)
2404 return ret_val;
2405
2406 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
2407 if ((hw->forced_speed_duplex == e1000_10_full) ||
2408 (hw->forced_speed_duplex == e1000_10_half))
2409 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ;
2410 else
2411 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ;
2412
2413 /* Also due to the reset, we need to enable CRS on Tx. */
2414 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2415
2416 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2417 if (ret_val)
2418 return ret_val;
1da177e4
LT		 2419 }
2420 return E1000_SUCCESS;
2421}
2422
2423/******************************************************************************
2424* Sets the collision distance in the Transmit Control register
2425*
2426* hw - Struct containing variables accessed by shared code
2427*
2428* Link should have been established previously. Reads the speed and duplex
2429* information from the Device Status register.
2430******************************************************************************/
2431void
2432e1000_config_collision_dist(struct e1000_hw *hw)
2433{
0fadb059 2434 uint32_t tctl, coll_dist;
1da177e4
LT		 2435
2436 DEBUGFUNC("e1000_config_collision_dist");
2437
0fadb059
JK		 2438 if (hw->mac_type < e1000_82543)
2439 coll_dist = E1000_COLLISION_DISTANCE_82542;
2440 else
2441 coll_dist = E1000_COLLISION_DISTANCE;
2442
1da177e4
LT		 2443 tctl = E1000_READ_REG(hw, TCTL);
2444
2445 tctl &= ~E1000_TCTL_COLD;
0fadb059 2446 tctl |= coll_dist << E1000_COLD_SHIFT;
1da177e4
LT		 2447
2448 E1000_WRITE_REG(hw, TCTL, tctl);
2449 E1000_WRITE_FLUSH(hw);
2450}
2451
2452/******************************************************************************
2453* Sets MAC speed and duplex settings to reflect the those in the PHY
2454*
2455* hw - Struct containing variables accessed by shared code
2456* mii_reg - data to write to the MII control register
2457*
2458* The contents of the PHY register containing the needed information need to
2459* be passed in.
2460******************************************************************************/
2461static int32_t
2462e1000_config_mac_to_phy(struct e1000_hw *hw)
2463{
2464 uint32_t ctrl;
2465 int32_t ret_val;
2466 uint16_t phy_data;
2467
2468 DEBUGFUNC("e1000_config_mac_to_phy");
2469
76c224bc 2470 /* 82544 or newer MAC, Auto Speed Detection takes care of
2d7edb92
MC		 2471 * MAC speed/duplex configuration.*/
2472 if (hw->mac_type >= e1000_82544)
2473 return E1000_SUCCESS;
2474
1da177e4
LT		 2475 /* Read the Device Control Register and set the bits to Force Speed
2476 * and Duplex.
2477 */
2478 ctrl = E1000_READ_REG(hw, CTRL);
2479 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2480 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
2481
2482 /* Set up duplex in the Device Control and Transmit Control
2483 * registers depending on negotiated values.
2484 */
2d7edb92 2485 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
8fc897b0 2486 if (ret_val)
2d7edb92 2487 return ret_val;
1da177e4 2488
8fc897b0 2489 if (phy_data & M88E1000_PSSR_DPLX)
2d7edb92 2490 ctrl |= E1000_CTRL_FD;
76c224bc 2491 else
2d7edb92 2492 ctrl &= ~E1000_CTRL_FD;
1da177e4 2493
2d7edb92 2494 e1000_config_collision_dist(hw);
1da177e4 2495
2d7edb92
MC		 2496 /* Set up speed in the Device Control register depending on
2497 * negotiated values.
2498 */
8fc897b0 2499 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
2d7edb92 2500 ctrl |= E1000_CTRL_SPD_1000;
8fc897b0 2501 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
2d7edb92 2502 ctrl |= E1000_CTRL_SPD_100;
1da177e4 2503
1da177e4
LT		 2504 /* Write the configured values back to the Device Control Reg. */
2505 E1000_WRITE_REG(hw, CTRL, ctrl);
2506 return E1000_SUCCESS;
2507}
2508
2509/******************************************************************************
2510 * Forces the MAC's flow control settings.
2511 *
2512 * hw - Struct containing variables accessed by shared code
2513 *
2514 * Sets the TFCE and RFCE bits in the device control register to reflect
2515 * the adapter settings. TFCE and RFCE need to be explicitly set by
2516 * software when a Copper PHY is used because autonegotiation is managed
2517 * by the PHY rather than the MAC. Software must also configure these
2518 * bits when link is forced on a fiber connection.
2519 *****************************************************************************/
2520int32_t
2521e1000_force_mac_fc(struct e1000_hw *hw)
2522{
2523 uint32_t ctrl;
2524
2525 DEBUGFUNC("e1000_force_mac_fc");
2526
2527 /* Get the current configuration of the Device Control Register */
2528 ctrl = E1000_READ_REG(hw, CTRL);
2529
2530 /* Because we didn't get link via the internal auto-negotiation
2531 * mechanism (we either forced link or we got link via PHY
2532 * auto-neg), we have to manually enable/disable transmit an
2533 * receive flow control.
2534 *
2535 * The "Case" statement below enables/disable flow control
2536 * according to the "hw->fc" parameter.
2537 *
2538 * The possible values of the "fc" parameter are:
2539 * 0: Flow control is completely disabled
2540 * 1: Rx flow control is enabled (we can receive pause
2541 * frames but not send pause frames).
2542 * 2: Tx flow control is enabled (we can send pause frames
2543 * frames but we do not receive pause frames).
2544 * 3: Both Rx and TX flow control (symmetric) is enabled.
2545 * other: No other values should be possible at this point.
2546 */
2547
2548 switch (hw->fc) {
2549 case e1000_fc_none:
2550 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2551 break;
2552 case e1000_fc_rx_pause:
2553 ctrl &= (~E1000_CTRL_TFCE);
2554 ctrl |= E1000_CTRL_RFCE;
2555 break;
2556 case e1000_fc_tx_pause:
2557 ctrl &= (~E1000_CTRL_RFCE);
2558 ctrl |= E1000_CTRL_TFCE;
2559 break;
2560 case e1000_fc_full:
2561 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2562 break;
2563 default:
2564 DEBUGOUT("Flow control param set incorrectly\n");
2565 return -E1000_ERR_CONFIG;
2566 }
2567
2568 /* Disable TX Flow Control for 82542 (rev 2.0) */
8fc897b0 2569 if (hw->mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2570 ctrl &= (~E1000_CTRL_TFCE);
2571
2572 E1000_WRITE_REG(hw, CTRL, ctrl);
2573 return E1000_SUCCESS;
2574}
2575
2576/******************************************************************************
2577 * Configures flow control settings after link is established
2578 *
2579 * hw - Struct containing variables accessed by shared code
2580 *
2581 * Should be called immediately after a valid link has been established.
2582 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
2583 * and autonegotiation is enabled, the MAC flow control settings will be set
2584 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2585 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
2586 *****************************************************************************/
3ad2cc67 2587static int32_t
1da177e4
LT		 2588e1000_config_fc_after_link_up(struct e1000_hw *hw)
2589{
2590 int32_t ret_val;
2591 uint16_t mii_status_reg;
2592 uint16_t mii_nway_adv_reg;
2593 uint16_t mii_nway_lp_ability_reg;
2594 uint16_t speed;
2595 uint16_t duplex;
2596
2597 DEBUGFUNC("e1000_config_fc_after_link_up");
2598
2599 /* Check for the case where we have fiber media and auto-neg failed
2600 * so we had to force link. In this case, we need to force the
2601 * configuration of the MAC to match the "fc" parameter.
2602 */
8fc897b0
AK		 2603 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
2604 ((hw->media_type == e1000_media_type_internal_serdes) &&
2605 (hw->autoneg_failed)) ||
2606 ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
1da177e4 2607 ret_val = e1000_force_mac_fc(hw);
8fc897b0 2608 if (ret_val) {
1da177e4
LT		 2609 DEBUGOUT("Error forcing flow control settings\n");
2610 return ret_val;
2611 }
2612 }
2613
2614 /* Check for the case where we have copper media and auto-neg is
2615 * enabled. In this case, we need to check and see if Auto-Neg
2616 * has completed, and if so, how the PHY and link partner has
2617 * flow control configured.
2618 */
8fc897b0 2619 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
1da177e4
LT		 2620 /* Read the MII Status Register and check to see if AutoNeg
2621 * has completed. We read this twice because this reg has
2622 * some "sticky" (latched) bits.
2623 */
2624 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 2625 if (ret_val)
1da177e4
LT		 2626 return ret_val;
2627 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 2628 if (ret_val)
1da177e4
LT		 2629 return ret_val;
2630
8fc897b0 2631 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
1da177e4
LT		 2632 /* The AutoNeg process has completed, so we now need to
2633 * read both the Auto Negotiation Advertisement Register
2634 * (Address 4) and the Auto_Negotiation Base Page Ability
2635 * Register (Address 5) to determine how flow control was
2636 * negotiated.
2637 */
2638 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2639 &mii_nway_adv_reg);
8fc897b0 2640 if (ret_val)
1da177e4
LT		 2641 return ret_val;
2642 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2643 &mii_nway_lp_ability_reg);
8fc897b0 2644 if (ret_val)
1da177e4
LT		 2645 return ret_val;
2646
2647 /* Two bits in the Auto Negotiation Advertisement Register
2648 * (Address 4) and two bits in the Auto Negotiation Base
2649 * Page Ability Register (Address 5) determine flow control
2650 * for both the PHY and the link partner. The following
2651 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2652 * 1999, describes these PAUSE resolution bits and how flow
2653 * control is determined based upon these settings.
2654 * NOTE: DC = Don't Care
2655 *
2656 * LOCAL DEVICE | LINK PARTNER
2657 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2658 *-------|---------|-------|---------|--------------------
2659 * 0 | 0 | DC | DC | e1000_fc_none
2660 * 0 | 1 | 0 | DC | e1000_fc_none
2661 * 0 | 1 | 1 | 0 | e1000_fc_none
2662 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
2663 * 1 | 0 | 0 | DC | e1000_fc_none
2664 * 1 | DC | 1 | DC | e1000_fc_full
2665 * 1 | 1 | 0 | 0 | e1000_fc_none
2666 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
2667 *
2668 */
2669 /* Are both PAUSE bits set to 1? If so, this implies
2670 * Symmetric Flow Control is enabled at both ends. The
2671 * ASM_DIR bits are irrelevant per the spec.
2672 *
2673 * For Symmetric Flow Control:
2674 *
2675 * LOCAL DEVICE | LINK PARTNER
2676 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2677 *-------|---------|-------|---------|--------------------
2678 * 1 | DC | 1 | DC | e1000_fc_full
2679 *
2680 */
8fc897b0
AK		 2681 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2682 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1da177e4
LT		 2683 /* Now we need to check if the user selected RX ONLY
2684 * of pause frames. In this case, we had to advertise
2685 * FULL flow control because we could not advertise RX
2686 * ONLY. Hence, we must now check to see if we need to
2687 * turn OFF the TRANSMISSION of PAUSE frames.
2688 */
8fc897b0 2689 if (hw->original_fc == e1000_fc_full) {
1da177e4 2690 hw->fc = e1000_fc_full;
a42a507c 2691 DEBUGOUT("Flow Control = FULL.\n");
1da177e4
LT		 2692 } else {
2693 hw->fc = e1000_fc_rx_pause;
a42a507c 2694 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
1da177e4
LT		 2695 }
2696 }
2697 /* For receiving PAUSE frames ONLY.
2698 *
2699 * LOCAL DEVICE | LINK PARTNER
2700 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2701 *-------|---------|-------|---------|--------------------
2702 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
2703 *
2704 */
8fc897b0
AK		 2705 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2706 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2707 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2708 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1da177e4 2709 hw->fc = e1000_fc_tx_pause;
a42a507c 2710 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
1da177e4
LT		 2711 }
2712 /* For transmitting PAUSE frames ONLY.
2713 *
2714 * LOCAL DEVICE | LINK PARTNER
2715 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2716 *-------|---------|-------|---------|--------------------
2717 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
2718 *
2719 */
8fc897b0
AK		 2720 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2721 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2722 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2723 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1da177e4 2724 hw->fc = e1000_fc_rx_pause;
a42a507c 2725 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
1da177e4
LT		 2726 }
2727 /* Per the IEEE spec, at this point flow control should be
2728 * disabled. However, we want to consider that we could
2729 * be connected to a legacy switch that doesn't advertise
2730 * desired flow control, but can be forced on the link
2731 * partner. So if we advertised no flow control, that is
2732 * what we will resolve to. If we advertised some kind of
2733 * receive capability (Rx Pause Only or Full Flow Control)
2734 * and the link partner advertised none, we will configure
2735 * ourselves to enable Rx Flow Control only. We can do
2736 * this safely for two reasons: If the link partner really
2737 * didn't want flow control enabled, and we enable Rx, no
2738 * harm done since we won't be receiving any PAUSE frames
2739 * anyway. If the intent on the link partner was to have
2740 * flow control enabled, then by us enabling RX only, we
2741 * can at least receive pause frames and process them.
2742 * This is a good idea because in most cases, since we are
2743 * predominantly a server NIC, more times than not we will
2744 * be asked to delay transmission of packets than asking
2745 * our link partner to pause transmission of frames.
2746 */
8fc897b0
AK		 2747 else if ((hw->original_fc == e1000_fc_none ||
2748 hw->original_fc == e1000_fc_tx_pause) ||
2749 hw->fc_strict_ieee) {
1da177e4 2750 hw->fc = e1000_fc_none;
a42a507c 2751 DEBUGOUT("Flow Control = NONE.\n");
1da177e4
LT		 2752 } else {
2753 hw->fc = e1000_fc_rx_pause;
a42a507c 2754 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
1da177e4
LT		 2755 }
2756
2757 /* Now we need to do one last check... If we auto-
2758 * negotiated to HALF DUPLEX, flow control should not be
2759 * enabled per IEEE 802.3 spec.
2760 */
2761 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
8fc897b0 2762 if (ret_val) {
1da177e4
LT		 2763 DEBUGOUT("Error getting link speed and duplex\n");
2764 return ret_val;
2765 }
2766
8fc897b0 2767 if (duplex == HALF_DUPLEX)
1da177e4
LT		 2768 hw->fc = e1000_fc_none;
2769
2770 /* Now we call a subroutine to actually force the MAC
2771 * controller to use the correct flow control settings.
2772 */
2773 ret_val = e1000_force_mac_fc(hw);
8fc897b0 2774 if (ret_val) {
1da177e4
LT		 2775 DEBUGOUT("Error forcing flow control settings\n");
2776 return ret_val;
2777 }
2778 } else {
a42a507c 2779 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
1da177e4
LT		 2780 }
2781 }
2782 return E1000_SUCCESS;
2783}
2784
2785/******************************************************************************
2786 * Checks to see if the link status of the hardware has changed.
2787 *
2788 * hw - Struct containing variables accessed by shared code
2789 *
2790 * Called by any function that needs to check the link status of the adapter.
2791 *****************************************************************************/
2792int32_t
2793e1000_check_for_link(struct e1000_hw *hw)
2794{
2795 uint32_t rxcw = 0;
2796 uint32_t ctrl;
2797 uint32_t status;
2798 uint32_t rctl;
2799 uint32_t icr;
2800 uint32_t signal = 0;
2801 int32_t ret_val;
2802 uint16_t phy_data;
2803
2804 DEBUGFUNC("e1000_check_for_link");
2805
2806 ctrl = E1000_READ_REG(hw, CTRL);
2807 status = E1000_READ_REG(hw, STATUS);
2808
2809 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
2810 * set when the optics detect a signal. On older adapters, it will be
2811 * cleared when there is a signal. This applies to fiber media only.
2812 */
8fc897b0
AK		 2813 if ((hw->media_type == e1000_media_type_fiber) ||
2814 (hw->media_type == e1000_media_type_internal_serdes)) {
1da177e4
LT		 2815 rxcw = E1000_READ_REG(hw, RXCW);
2816
8fc897b0 2817 if (hw->media_type == e1000_media_type_fiber) {
1da177e4 2818 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
8fc897b0 2819 if (status & E1000_STATUS_LU)
1da177e4
LT		 2820 hw->get_link_status = FALSE;
2821 }
2822 }
2823
2824 /* If we have a copper PHY then we only want to go out to the PHY
2825 * registers to see if Auto-Neg has completed and/or if our link
2826 * status has changed. The get_link_status flag will be set if we
2827 * receive a Link Status Change interrupt or we have Rx Sequence
2828 * Errors.
2829 */
8fc897b0 2830 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
1da177e4
LT		 2831 /* First we want to see if the MII Status Register reports
2832 * link. If so, then we want to get the current speed/duplex
2833 * of the PHY.
2834 * Read the register twice since the link bit is sticky.
2835 */
2836 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 2837 if (ret_val)
1da177e4
LT		 2838 return ret_val;
2839 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 2840 if (ret_val)
1da177e4
LT		 2841 return ret_val;
2842
8fc897b0 2843 if (phy_data & MII_SR_LINK_STATUS) {
1da177e4
LT		 2844 hw->get_link_status = FALSE;
2845 /* Check if there was DownShift, must be checked immediately after
2846 * link-up */
2847 e1000_check_downshift(hw);
2848
2849 /* If we are on 82544 or 82543 silicon and speed/duplex
2850 * are forced to 10H or 10F, then we will implement the polarity
2851 * reversal workaround. We disable interrupts first, and upon
2852 * returning, place the devices interrupt state to its previous
2853 * value except for the link status change interrupt which will
2854 * happen due to the execution of this workaround.
2855 */
2856
8fc897b0
AK		 2857 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2858 (!hw->autoneg) &&
2859 (hw->forced_speed_duplex == e1000_10_full ||
2860 hw->forced_speed_duplex == e1000_10_half)) {
1da177e4
LT		 2861 E1000_WRITE_REG(hw, IMC, 0xffffffff);
2862 ret_val = e1000_polarity_reversal_workaround(hw);
2863 icr = E1000_READ_REG(hw, ICR);
2864 E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC));
2865 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK);
2866 }
2867
2868 } else {
2869 /* No link detected */
2870 e1000_config_dsp_after_link_change(hw, FALSE);
2871 return 0;
2872 }
2873
2874 /* If we are forcing speed/duplex, then we simply return since
2875 * we have already determined whether we have link or not.
2876 */
8fc897b0 2877 if (!hw->autoneg) return -E1000_ERR_CONFIG;
1da177e4
LT		 2878
2879 /* optimize the dsp settings for the igp phy */
2880 e1000_config_dsp_after_link_change(hw, TRUE);
2881
2882 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2883 * have Si on board that is 82544 or newer, Auto
2884 * Speed Detection takes care of MAC speed/duplex
2885 * configuration. So we only need to configure Collision
2886 * Distance in the MAC. Otherwise, we need to force
2887 * speed/duplex on the MAC to the current PHY speed/duplex
2888 * settings.
2889 */
8fc897b0 2890 if (hw->mac_type >= e1000_82544)
1da177e4
LT		 2891 e1000_config_collision_dist(hw);
2892 else {
2893 ret_val = e1000_config_mac_to_phy(hw);
8fc897b0 2894 if (ret_val) {
1da177e4
LT		 2895 DEBUGOUT("Error configuring MAC to PHY settings\n");
2896 return ret_val;
2897 }
2898 }
2899
2900 /* Configure Flow Control now that Auto-Neg has completed. First, we
2901 * need to restore the desired flow control settings because we may
2902 * have had to re-autoneg with a different link partner.
2903 */
2904 ret_val = e1000_config_fc_after_link_up(hw);
8fc897b0 2905 if (ret_val) {
1da177e4
LT		 2906 DEBUGOUT("Error configuring flow control\n");
2907 return ret_val;
2908 }
2909
2910 /* At this point we know that we are on copper and we have
2911 * auto-negotiated link. These are conditions for checking the link
2912 * partner capability register. We use the link speed to determine if
2913 * TBI compatibility needs to be turned on or off. If the link is not
2914 * at gigabit speed, then TBI compatibility is not needed. If we are
2915 * at gigabit speed, we turn on TBI compatibility.
2916 */
8fc897b0 2917 if (hw->tbi_compatibility_en) {
1da177e4 2918 uint16_t speed, duplex;
592600a0
AK		 2919 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
2920 if (ret_val) {
2921 DEBUGOUT("Error getting link speed and duplex\n");
2922 return ret_val;
2923 }
2924 if (speed != SPEED_1000) {
1da177e4
LT		 2925 /* If link speed is not set to gigabit speed, we do not need
2926 * to enable TBI compatibility.
2927 */
8fc897b0 2928 if (hw->tbi_compatibility_on) {
1da177e4
LT		 2929 /* If we previously were in the mode, turn it off. */
2930 rctl = E1000_READ_REG(hw, RCTL);
2931 rctl &= ~E1000_RCTL_SBP;
2932 E1000_WRITE_REG(hw, RCTL, rctl);
2933 hw->tbi_compatibility_on = FALSE;
2934 }
2935 } else {
2936 /* If TBI compatibility is was previously off, turn it on. For
2937 * compatibility with a TBI link partner, we will store bad
2938 * packets. Some frames have an additional byte on the end and
2939 * will look like CRC errors to to the hardware.
2940 */
8fc897b0 2941 if (!hw->tbi_compatibility_on) {
1da177e4
LT		 2942 hw->tbi_compatibility_on = TRUE;
2943 rctl = E1000_READ_REG(hw, RCTL);
2944 rctl |= E1000_RCTL_SBP;
2945 E1000_WRITE_REG(hw, RCTL, rctl);
2946 }
2947 }
2948 }
2949 }
2950 /* If we don't have link (auto-negotiation failed or link partner cannot
2951 * auto-negotiate), the cable is plugged in (we have signal), and our
2952 * link partner is not trying to auto-negotiate with us (we are receiving
2953 * idles or data), we need to force link up. We also need to give
2954 * auto-negotiation time to complete, in case the cable was just plugged
2955 * in. The autoneg_failed flag does this.
2956 */
8fc897b0 2957 else if ((((hw->media_type == e1000_media_type_fiber) &&
1da177e4 2958 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
8fc897b0
AK		 2959 (hw->media_type == e1000_media_type_internal_serdes)) &&
2960 (!(status & E1000_STATUS_LU)) &&
2961 (!(rxcw & E1000_RXCW_C))) {
2962 if (hw->autoneg_failed == 0) {
1da177e4
LT		 2963 hw->autoneg_failed = 1;
2964 return 0;
2965 }
a42a507c 2966 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
1da177e4
LT		 2967
2968 /* Disable auto-negotiation in the TXCW register */
2969 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2970
2971 /* Force link-up and also force full-duplex. */
2972 ctrl = E1000_READ_REG(hw, CTRL);
2973 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2974 E1000_WRITE_REG(hw, CTRL, ctrl);
2975
2976 /* Configure Flow Control after forcing link up. */
2977 ret_val = e1000_config_fc_after_link_up(hw);
8fc897b0 2978 if (ret_val) {
1da177e4
LT		 2979 DEBUGOUT("Error configuring flow control\n");
2980 return ret_val;
2981 }
2982 }
2983 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
2984 * auto-negotiation in the TXCW register and disable forced link in the
2985 * Device Control register in an attempt to auto-negotiate with our link
2986 * partner.
2987 */
8fc897b0
AK		 2988 else if (((hw->media_type == e1000_media_type_fiber) ||
2989 (hw->media_type == e1000_media_type_internal_serdes)) &&
2990 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
a42a507c 2991 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
1da177e4
LT		 2992 E1000_WRITE_REG(hw, TXCW, hw->txcw);
2993 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
2994
2995 hw->serdes_link_down = FALSE;
2996 }
2997 /* If we force link for non-auto-negotiation switch, check link status
2998 * based on MAC synchronization for internal serdes media type.
2999 */
8fc897b0
AK		 3000 else if ((hw->media_type == e1000_media_type_internal_serdes) &&
3001 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
1da177e4
LT		 3002 /* SYNCH bit and IV bit are sticky. */
3003 udelay(10);
8fc897b0
AK		 3004 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
3005 if (!(rxcw & E1000_RXCW_IV)) {
1da177e4
LT		 3006 hw->serdes_link_down = FALSE;
3007 DEBUGOUT("SERDES: Link is up.\n");
3008 }
3009 } else {
3010 hw->serdes_link_down = TRUE;
3011 DEBUGOUT("SERDES: Link is down.\n");
3012 }
3013 }
8fc897b0
AK		 3014 if ((hw->media_type == e1000_media_type_internal_serdes) &&
3015 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
1da177e4
LT		 3016 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
3017 }
3018 return E1000_SUCCESS;
3019}
3020
3021/******************************************************************************
3022 * Detects the current speed and duplex settings of the hardware.
3023 *
3024 * hw - Struct containing variables accessed by shared code
3025 * speed - Speed of the connection
3026 * duplex - Duplex setting of the connection
3027 *****************************************************************************/
3028int32_t
3029e1000_get_speed_and_duplex(struct e1000_hw *hw,
3030 uint16_t *speed,
3031 uint16_t *duplex)
3032{
3033 uint32_t status;
3034 int32_t ret_val;
3035 uint16_t phy_data;
3036
3037 DEBUGFUNC("e1000_get_speed_and_duplex");
3038
8fc897b0 3039 if (hw->mac_type >= e1000_82543) {
1da177e4 3040 status = E1000_READ_REG(hw, STATUS);
8fc897b0 3041 if (status & E1000_STATUS_SPEED_1000) {
1da177e4
LT		 3042 *speed = SPEED_1000;
3043 DEBUGOUT("1000 Mbs, ");
8fc897b0 3044 } else if (status & E1000_STATUS_SPEED_100) {
1da177e4
LT		 3045 *speed = SPEED_100;
3046 DEBUGOUT("100 Mbs, ");
3047 } else {
3048 *speed = SPEED_10;
3049 DEBUGOUT("10 Mbs, ");
3050 }
3051
8fc897b0 3052 if (status & E1000_STATUS_FD) {
1da177e4 3053 *duplex = FULL_DUPLEX;
a42a507c 3054 DEBUGOUT("Full Duplex\n");
1da177e4
LT		 3055 } else {
3056 *duplex = HALF_DUPLEX;
a42a507c 3057 DEBUGOUT(" Half Duplex\n");
1da177e4
LT		 3058 }
3059 } else {
a42a507c 3060 DEBUGOUT("1000 Mbs, Full Duplex\n");
1da177e4
LT		 3061 *speed = SPEED_1000;
3062 *duplex = FULL_DUPLEX;
3063 }
3064
3065 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
3066 * if it is operating at half duplex. Here we set the duplex settings to
3067 * match the duplex in the link partner's capabilities.
3068 */
8fc897b0 3069 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
1da177e4 3070 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
8fc897b0 3071 if (ret_val)
1da177e4
LT		 3072 return ret_val;
3073
8fc897b0 3074 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
1da177e4
LT		 3075 *duplex = HALF_DUPLEX;
3076 else {
3077 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
8fc897b0 3078 if (ret_val)
1da177e4 3079 return ret_val;
8fc897b0 3080 if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
1da177e4
LT		 3081 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3082 *duplex = HALF_DUPLEX;
3083 }
3084 }
3085
76c224bc 3086 if ((hw->mac_type == e1000_80003es2lan) &&
6418ecc6
JK		 3087 (hw->media_type == e1000_media_type_copper)) {
3088 if (*speed == SPEED_1000)
3089 ret_val = e1000_configure_kmrn_for_1000(hw);
3090 else
cd94dd0b
AK		 3091 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3092 if (ret_val)
3093 return ret_val;
3094 }
3095
3096 if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
3097 ret_val = e1000_kumeran_lock_loss_workaround(hw);
6418ecc6
JK		 3098 if (ret_val)
3099 return ret_val;
3100 }
3101
1da177e4
LT		 3102 return E1000_SUCCESS;
3103}
3104
3105/******************************************************************************
3106* Blocks until autoneg completes or times out (~4.5 seconds)
3107*
3108* hw - Struct containing variables accessed by shared code
3109******************************************************************************/
3ad2cc67 3110static int32_t
1da177e4
LT		 3111e1000_wait_autoneg(struct e1000_hw *hw)
3112{
3113 int32_t ret_val;
3114 uint16_t i;
3115 uint16_t phy_data;
3116
3117 DEBUGFUNC("e1000_wait_autoneg");
3118 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
3119
3120 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
8fc897b0 3121 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
1da177e4
LT		 3122 /* Read the MII Status Register and wait for Auto-Neg
3123 * Complete bit to be set.
3124 */
3125 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 3126 if (ret_val)
1da177e4
LT		 3127 return ret_val;
3128 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 3129 if (ret_val)
1da177e4 3130 return ret_val;
8fc897b0 3131 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
1da177e4
LT		 3132 return E1000_SUCCESS;
3133 }
f8ec4733 3134 msleep(100);
1da177e4
LT		 3135 }
3136 return E1000_SUCCESS;
3137}
3138
3139/******************************************************************************
3140* Raises the Management Data Clock
3141*
3142* hw - Struct containing variables accessed by shared code
3143* ctrl - Device control register's current value
3144******************************************************************************/
3145static void
3146e1000_raise_mdi_clk(struct e1000_hw *hw,
3147 uint32_t *ctrl)
3148{
3149 /* Raise the clock input to the Management Data Clock (by setting the MDC
3150 * bit), and then delay 10 microseconds.
3151 */
3152 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
3153 E1000_WRITE_FLUSH(hw);
3154 udelay(10);
3155}
3156
3157/******************************************************************************
3158* Lowers the Management Data Clock
3159*
3160* hw - Struct containing variables accessed by shared code
3161* ctrl - Device control register's current value
3162******************************************************************************/
3163static void
3164e1000_lower_mdi_clk(struct e1000_hw *hw,
3165 uint32_t *ctrl)
3166{
3167 /* Lower the clock input to the Management Data Clock (by clearing the MDC
3168 * bit), and then delay 10 microseconds.
3169 */
3170 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
3171 E1000_WRITE_FLUSH(hw);
3172 udelay(10);
3173}
3174
3175/******************************************************************************
3176* Shifts data bits out to the PHY
3177*
3178* hw - Struct containing variables accessed by shared code
3179* data - Data to send out to the PHY
3180* count - Number of bits to shift out
3181*
3182* Bits are shifted out in MSB to LSB order.
3183******************************************************************************/
3184static void
3185e1000_shift_out_mdi_bits(struct e1000_hw *hw,
3186 uint32_t data,
3187 uint16_t count)
3188{
3189 uint32_t ctrl;
3190 uint32_t mask;
3191
3192 /* We need to shift "count" number of bits out to the PHY. So, the value
3193 * in the "data" parameter will be shifted out to the PHY one bit at a
3194 * time. In order to do this, "data" must be broken down into bits.
3195 */
3196 mask = 0x01;
3197 mask <<= (count - 1);
3198
3199 ctrl = E1000_READ_REG(hw, CTRL);
3200
3201 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
3202 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
3203
8fc897b0 3204 while (mask) {
1da177e4
LT		 3205 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
3206 * then raising and lowering the Management Data Clock. A "0" is
3207 * shifted out to the PHY by setting the MDIO bit to "0" and then
3208 * raising and lowering the clock.
3209 */
8fc897b0
AK		 3210 if (data & mask)
3211 ctrl |= E1000_CTRL_MDIO;
3212 else
3213 ctrl &= ~E1000_CTRL_MDIO;
1da177e4
LT		 3214
3215 E1000_WRITE_REG(hw, CTRL, ctrl);
3216 E1000_WRITE_FLUSH(hw);
3217
3218 udelay(10);
3219
3220 e1000_raise_mdi_clk(hw, &ctrl);
3221 e1000_lower_mdi_clk(hw, &ctrl);
3222
3223 mask = mask >> 1;
3224 }
3225}
3226
3227/******************************************************************************
3228* Shifts data bits in from the PHY
3229*
3230* hw - Struct containing variables accessed by shared code
3231*
3232* Bits are shifted in in MSB to LSB order.
3233******************************************************************************/
3234static uint16_t
3235e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3236{
3237 uint32_t ctrl;
3238 uint16_t data = 0;
3239 uint8_t i;
3240
3241 /* In order to read a register from the PHY, we need to shift in a total
3242 * of 18 bits from the PHY. The first two bit (turnaround) times are used
3243 * to avoid contention on the MDIO pin when a read operation is performed.
3244 * These two bits are ignored by us and thrown away. Bits are "shifted in"
3245 * by raising the input to the Management Data Clock (setting the MDC bit),
3246 * and then reading the value of the MDIO bit.
3247 */
3248 ctrl = E1000_READ_REG(hw, CTRL);
3249
3250 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
3251 ctrl &= ~E1000_CTRL_MDIO_DIR;
3252 ctrl &= ~E1000_CTRL_MDIO;
3253
3254 E1000_WRITE_REG(hw, CTRL, ctrl);
3255 E1000_WRITE_FLUSH(hw);
3256
3257 /* Raise and Lower the clock before reading in the data. This accounts for
3258 * the turnaround bits. The first clock occurred when we clocked out the
3259 * last bit of the Register Address.
3260 */
3261 e1000_raise_mdi_clk(hw, &ctrl);
3262 e1000_lower_mdi_clk(hw, &ctrl);
3263
8fc897b0 3264 for (data = 0, i = 0; i < 16; i++) {
1da177e4
LT		 3265 data = data << 1;
3266 e1000_raise_mdi_clk(hw, &ctrl);
3267 ctrl = E1000_READ_REG(hw, CTRL);
3268 /* Check to see if we shifted in a "1". */
8fc897b0
AK		 3269 if (ctrl & E1000_CTRL_MDIO)
3270 data |= 1;
1da177e4
LT		 3271 e1000_lower_mdi_clk(hw, &ctrl);
3272 }
3273
3274 e1000_raise_mdi_clk(hw, &ctrl);
3275 e1000_lower_mdi_clk(hw, &ctrl);
3276
3277 return data;
3278}
3279
e4c780b1 3280static int32_t
6418ecc6
JK		 3281e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
3282{
3283 uint32_t swfw_sync = 0;
3284 uint32_t swmask = mask;
3285 uint32_t fwmask = mask << 16;
3286 int32_t timeout = 200;
3287
3288 DEBUGFUNC("e1000_swfw_sync_acquire");
3289
cd94dd0b
AK		 3290 if (hw->swfwhw_semaphore_present)
3291 return e1000_get_software_flag(hw);
3292
6418ecc6
JK		 3293 if (!hw->swfw_sync_present)
3294 return e1000_get_hw_eeprom_semaphore(hw);
3295
8fc897b0 3296 while (timeout) {
6418ecc6
JK		 3297 if (e1000_get_hw_eeprom_semaphore(hw))
3298 return -E1000_ERR_SWFW_SYNC;
3299
3300 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3301 if (!(swfw_sync & (fwmask | swmask))) {
3302 break;
3303 }
3304
3305 /* firmware currently using resource (fwmask) */
3306 /* or other software thread currently using resource (swmask) */
3307 e1000_put_hw_eeprom_semaphore(hw);
f8ec4733 3308 mdelay(5);
6418ecc6
JK		 3309 timeout--;
3310 }
3311
3312 if (!timeout) {
3313 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
3314 return -E1000_ERR_SWFW_SYNC;
3315 }
3316
3317 swfw_sync |= swmask;
3318 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3319
3320 e1000_put_hw_eeprom_semaphore(hw);
3321 return E1000_SUCCESS;
3322}
3323
e4c780b1 3324static void
6418ecc6
JK		 3325e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
3326{
3327 uint32_t swfw_sync;
3328 uint32_t swmask = mask;
3329
3330 DEBUGFUNC("e1000_swfw_sync_release");
3331
cd94dd0b
AK		 3332 if (hw->swfwhw_semaphore_present) {
3333 e1000_release_software_flag(hw);
3334 return;
3335 }
3336
6418ecc6
JK		 3337 if (!hw->swfw_sync_present) {
3338 e1000_put_hw_eeprom_semaphore(hw);
3339 return;
3340 }
3341
3342 /* if (e1000_get_hw_eeprom_semaphore(hw))
3343 * return -E1000_ERR_SWFW_SYNC; */
3344 while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS);
3345 /* empty */
3346
3347 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3348 swfw_sync &= ~swmask;
3349 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3350
3351 e1000_put_hw_eeprom_semaphore(hw);
3352}
3353
1da177e4
LT		 3354/*****************************************************************************
3355* Reads the value from a PHY register, if the value is on a specific non zero
3356* page, sets the page first.
3357* hw - Struct containing variables accessed by shared code
3358* reg_addr - address of the PHY register to read
3359******************************************************************************/
3360int32_t
3361e1000_read_phy_reg(struct e1000_hw *hw,
3362 uint32_t reg_addr,
3363 uint16_t *phy_data)
3364{
3365 uint32_t ret_val;
6418ecc6 3366 uint16_t swfw;
1da177e4
LT		 3367
3368 DEBUGFUNC("e1000_read_phy_reg");
3369
6418ecc6
JK		 3370 if ((hw->mac_type == e1000_80003es2lan) &&
3371 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3372 swfw = E1000_SWFW_PHY1_SM;
3373 } else {
3374 swfw = E1000_SWFW_PHY0_SM;
3375 }
3376 if (e1000_swfw_sync_acquire(hw, swfw))
3377 return -E1000_ERR_SWFW_SYNC;
3378
cd94dd0b
AK		 3379 if ((hw->phy_type == e1000_phy_igp ||
3380 hw->phy_type == e1000_phy_igp_3 ||
2d7edb92 3381 hw->phy_type == e1000_phy_igp_2) &&
1da177e4
LT		 3382 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3383 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3384 (uint16_t)reg_addr);
8fc897b0 3385 if (ret_val) {
6418ecc6 3386 e1000_swfw_sync_release(hw, swfw);
1da177e4
LT		 3387 return ret_val;
3388 }
6418ecc6
JK		 3389 } else if (hw->phy_type == e1000_phy_gg82563) {
3390 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3391 (hw->mac_type == e1000_80003es2lan)) {
3392 /* Select Configuration Page */
3393 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3394 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3395 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3396 } else {
3397 /* Use Alternative Page Select register to access
3398 * registers 30 and 31
3399 */
3400 ret_val = e1000_write_phy_reg_ex(hw,
3401 GG82563_PHY_PAGE_SELECT_ALT,
3402 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3403 }
3404
3405 if (ret_val) {
3406 e1000_swfw_sync_release(hw, swfw);
3407 return ret_val;
3408 }
3409 }
1da177e4
LT		 3410 }
3411
3412 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3413 phy_data);
3414
6418ecc6 3415 e1000_swfw_sync_release(hw, swfw);
1da177e4
LT		 3416 return ret_val;
3417}
3418
3419int32_t
3420e1000_read_phy_reg_ex(struct e1000_hw *hw,
3421 uint32_t reg_addr,
3422 uint16_t *phy_data)
3423{
3424 uint32_t i;
3425 uint32_t mdic = 0;
3426 const uint32_t phy_addr = 1;
3427
3428 DEBUGFUNC("e1000_read_phy_reg_ex");
3429
8fc897b0 3430 if (reg_addr > MAX_PHY_REG_ADDRESS) {
1da177e4
LT		 3431 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3432 return -E1000_ERR_PARAM;
3433 }
3434
8fc897b0 3435 if (hw->mac_type > e1000_82543) {
1da177e4
LT		 3436 /* Set up Op-code, Phy Address, and register address in the MDI
3437 * Control register. The MAC will take care of interfacing with the
3438 * PHY to retrieve the desired data.
3439 */
3440 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
3441 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3442 (E1000_MDIC_OP_READ));
3443
3444 E1000_WRITE_REG(hw, MDIC, mdic);
3445
3446 /* Poll the ready bit to see if the MDI read completed */
8fc897b0 3447 for (i = 0; i < 64; i++) {
1da177e4
LT		 3448 udelay(50);
3449 mdic = E1000_READ_REG(hw, MDIC);
8fc897b0 3450 if (mdic & E1000_MDIC_READY) break;
1da177e4 3451 }
8fc897b0 3452 if (!(mdic & E1000_MDIC_READY)) {
1da177e4
LT		 3453 DEBUGOUT("MDI Read did not complete\n");
3454 return -E1000_ERR_PHY;
3455 }
8fc897b0 3456 if (mdic & E1000_MDIC_ERROR) {
1da177e4
LT		 3457 DEBUGOUT("MDI Error\n");
3458 return -E1000_ERR_PHY;
3459 }
3460 *phy_data = (uint16_t) mdic;
3461 } else {
3462 /* We must first send a preamble through the MDIO pin to signal the
3463 * beginning of an MII instruction. This is done by sending 32
3464 * consecutive "1" bits.
3465 */
3466 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3467
3468 /* Now combine the next few fields that are required for a read
3469 * operation. We use this method instead of calling the
3470 * e1000_shift_out_mdi_bits routine five different times. The format of
3471 * a MII read instruction consists of a shift out of 14 bits and is
3472 * defined as follows:
3473 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
3474 * followed by a shift in of 18 bits. This first two bits shifted in
3475 * are TurnAround bits used to avoid contention on the MDIO pin when a
3476 * READ operation is performed. These two bits are thrown away
3477 * followed by a shift in of 16 bits which contains the desired data.
3478 */
3479 mdic = ((reg_addr) | (phy_addr << 5) |
3480 (PHY_OP_READ << 10) | (PHY_SOF << 12));
3481
3482 e1000_shift_out_mdi_bits(hw, mdic, 14);
3483
3484 /* Now that we've shifted out the read command to the MII, we need to
3485 * "shift in" the 16-bit value (18 total bits) of the requested PHY
3486 * register address.
3487 */
3488 *phy_data = e1000_shift_in_mdi_bits(hw);
3489 }
3490 return E1000_SUCCESS;
3491}
3492
3493/******************************************************************************
3494* Writes a value to a PHY register
3495*
3496* hw - Struct containing variables accessed by shared code
3497* reg_addr - address of the PHY register to write
3498* data - data to write to the PHY
3499******************************************************************************/
3500int32_t
3501e1000_write_phy_reg(struct e1000_hw *hw,
3502 uint32_t reg_addr,
3503 uint16_t phy_data)
3504{
3505 uint32_t ret_val;
6418ecc6 3506 uint16_t swfw;
1da177e4
LT		 3507
3508 DEBUGFUNC("e1000_write_phy_reg");
3509
6418ecc6
JK		 3510 if ((hw->mac_type == e1000_80003es2lan) &&
3511 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3512 swfw = E1000_SWFW_PHY1_SM;
3513 } else {
3514 swfw = E1000_SWFW_PHY0_SM;
3515 }
3516 if (e1000_swfw_sync_acquire(hw, swfw))
3517 return -E1000_ERR_SWFW_SYNC;
3518
cd94dd0b
AK		 3519 if ((hw->phy_type == e1000_phy_igp ||
3520 hw->phy_type == e1000_phy_igp_3 ||
2d7edb92 3521 hw->phy_type == e1000_phy_igp_2) &&
1da177e4
LT		 3522 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3523 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3524 (uint16_t)reg_addr);
8fc897b0 3525 if (ret_val) {
6418ecc6 3526 e1000_swfw_sync_release(hw, swfw);
1da177e4
LT		 3527 return ret_val;
3528 }
6418ecc6
JK		 3529 } else if (hw->phy_type == e1000_phy_gg82563) {
3530 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3531 (hw->mac_type == e1000_80003es2lan)) {
3532 /* Select Configuration Page */
3533 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3534 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3535 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3536 } else {
3537 /* Use Alternative Page Select register to access
3538 * registers 30 and 31
3539 */
3540 ret_val = e1000_write_phy_reg_ex(hw,
3541 GG82563_PHY_PAGE_SELECT_ALT,
3542 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3543 }
3544
3545 if (ret_val) {
3546 e1000_swfw_sync_release(hw, swfw);
3547 return ret_val;
3548 }
3549 }
1da177e4
LT		 3550 }
3551
3552 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3553 phy_data);
3554
6418ecc6 3555 e1000_swfw_sync_release(hw, swfw);
1da177e4
LT		 3556 return ret_val;
3557}
3558
3559int32_t
3560e1000_write_phy_reg_ex(struct e1000_hw *hw,
3561 uint32_t reg_addr,
3562 uint16_t phy_data)
3563{
3564 uint32_t i;
3565 uint32_t mdic = 0;
3566 const uint32_t phy_addr = 1;
3567
3568 DEBUGFUNC("e1000_write_phy_reg_ex");
3569
8fc897b0 3570 if (reg_addr > MAX_PHY_REG_ADDRESS) {
1da177e4
LT		 3571 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3572 return -E1000_ERR_PARAM;
3573 }
3574
8fc897b0 3575 if (hw->mac_type > e1000_82543) {
1da177e4
LT		 3576 /* Set up Op-code, Phy Address, register address, and data intended
3577 * for the PHY register in the MDI Control register. The MAC will take
3578 * care of interfacing with the PHY to send the desired data.
3579 */
3580 mdic = (((uint32_t) phy_data) |
3581 (reg_addr << E1000_MDIC_REG_SHIFT) |
3582 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3583 (E1000_MDIC_OP_WRITE));
3584
3585 E1000_WRITE_REG(hw, MDIC, mdic);
3586
3587 /* Poll the ready bit to see if the MDI read completed */
8fc897b0 3588 for (i = 0; i < 641; i++) {
1da177e4
LT		 3589 udelay(5);
3590 mdic = E1000_READ_REG(hw, MDIC);
8fc897b0 3591 if (mdic & E1000_MDIC_READY) break;
1da177e4 3592 }
8fc897b0 3593 if (!(mdic & E1000_MDIC_READY)) {
1da177e4
LT		 3594 DEBUGOUT("MDI Write did not complete\n");
3595 return -E1000_ERR_PHY;
3596 }
3597 } else {
3598 /* We'll need to use the SW defined pins to shift the write command
3599 * out to the PHY. We first send a preamble to the PHY to signal the
3600 * beginning of the MII instruction. This is done by sending 32
3601 * consecutive "1" bits.
3602 */
3603 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3604
3605 /* Now combine the remaining required fields that will indicate a
3606 * write operation. We use this method instead of calling the
3607 * e1000_shift_out_mdi_bits routine for each field in the command. The
3608 * format of a MII write instruction is as follows:
3609 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
3610 */
3611 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
3612 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
3613 mdic <<= 16;
3614 mdic |= (uint32_t) phy_data;
3615
3616 e1000_shift_out_mdi_bits(hw, mdic, 32);
3617 }
3618
3619 return E1000_SUCCESS;
3620}
3621
e4c780b1 3622static int32_t
6418ecc6
JK		 3623e1000_read_kmrn_reg(struct e1000_hw *hw,
3624 uint32_t reg_addr,
3625 uint16_t *data)
3626{
3627 uint32_t reg_val;
3628 uint16_t swfw;
3629 DEBUGFUNC("e1000_read_kmrn_reg");
3630
3631 if ((hw->mac_type == e1000_80003es2lan) &&
3632 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3633 swfw = E1000_SWFW_PHY1_SM;
3634 } else {
3635 swfw = E1000_SWFW_PHY0_SM;
3636 }
3637 if (e1000_swfw_sync_acquire(hw, swfw))
3638 return -E1000_ERR_SWFW_SYNC;
3639
3640 /* Write register address */
3641 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3642 E1000_KUMCTRLSTA_OFFSET) |
3643 E1000_KUMCTRLSTA_REN;
3644 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3645 udelay(2);
3646
3647 /* Read the data returned */
3648 reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
3649 *data = (uint16_t)reg_val;
3650
3651 e1000_swfw_sync_release(hw, swfw);
3652 return E1000_SUCCESS;
3653}
3654
e4c780b1 3655static int32_t
6418ecc6
JK		 3656e1000_write_kmrn_reg(struct e1000_hw *hw,
3657 uint32_t reg_addr,
3658 uint16_t data)
3659{
3660 uint32_t reg_val;
3661 uint16_t swfw;
3662 DEBUGFUNC("e1000_write_kmrn_reg");
3663
3664 if ((hw->mac_type == e1000_80003es2lan) &&
3665 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3666 swfw = E1000_SWFW_PHY1_SM;
3667 } else {
3668 swfw = E1000_SWFW_PHY0_SM;
3669 }
3670 if (e1000_swfw_sync_acquire(hw, swfw))
3671 return -E1000_ERR_SWFW_SYNC;
3672
3673 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3674 E1000_KUMCTRLSTA_OFFSET) | data;
3675 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3676 udelay(2);
3677
3678 e1000_swfw_sync_release(hw, swfw);
3679 return E1000_SUCCESS;
3680}
2d7edb92 3681
1da177e4
LT		 3682/******************************************************************************
3683* Returns the PHY to the power-on reset state
3684*
3685* hw - Struct containing variables accessed by shared code
3686******************************************************************************/
2d7edb92 3687int32_t
1da177e4
LT		 3688e1000_phy_hw_reset(struct e1000_hw *hw)
3689{
3690 uint32_t ctrl, ctrl_ext;
3691 uint32_t led_ctrl;
2d7edb92 3692 int32_t ret_val;
6418ecc6 3693 uint16_t swfw;
1da177e4
LT		 3694
3695 DEBUGFUNC("e1000_phy_hw_reset");
3696
2d7edb92
MC		 3697 /* In the case of the phy reset being blocked, it's not an error, we
3698 * simply return success without performing the reset. */
3699 ret_val = e1000_check_phy_reset_block(hw);
3700 if (ret_val)
3701 return E1000_SUCCESS;
3702
1da177e4
LT		 3703 DEBUGOUT("Resetting Phy...\n");
3704
8fc897b0 3705 if (hw->mac_type > e1000_82543) {
6418ecc6
JK		 3706 if ((hw->mac_type == e1000_80003es2lan) &&
3707 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3708 swfw = E1000_SWFW_PHY1_SM;
3709 } else {
3710 swfw = E1000_SWFW_PHY0_SM;
3711 }
3712 if (e1000_swfw_sync_acquire(hw, swfw)) {
3713 e1000_release_software_semaphore(hw);
3714 return -E1000_ERR_SWFW_SYNC;
3715 }
1da177e4
LT		 3716 /* Read the device control register and assert the E1000_CTRL_PHY_RST
3717 * bit. Then, take it out of reset.
76c224bc 3718 * For pre-e1000_82571 hardware, we delay for 10ms between the assert
fd803241 3719 * and deassert. For e1000_82571 hardware and later, we instead delay
0f15a8fa 3720 * for 50us between and 10ms after the deassertion.
1da177e4
LT		 3721 */
3722 ctrl = E1000_READ_REG(hw, CTRL);
3723 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
3724 E1000_WRITE_FLUSH(hw);
76c224bc
AK		 3725
3726 if (hw->mac_type < e1000_82571)
f8ec4733 3727 msleep(10);
b55ccb35
JK		 3728 else
3729 udelay(100);
76c224bc 3730
1da177e4
LT		 3731 E1000_WRITE_REG(hw, CTRL, ctrl);
3732 E1000_WRITE_FLUSH(hw);
76c224bc 3733
fd803241 3734 if (hw->mac_type >= e1000_82571)
f8ec4733 3735 mdelay(10);
6418ecc6 3736 e1000_swfw_sync_release(hw, swfw);
1da177e4
LT		 3737 } else {
3738 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
3739 * bit to put the PHY into reset. Then, take it out of reset.
3740 */
3741 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
3742 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3743 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3744 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3745 E1000_WRITE_FLUSH(hw);
f8ec4733 3746 msleep(10);
1da177e4
LT		 3747 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3748 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3749 E1000_WRITE_FLUSH(hw);
3750 }
3751 udelay(150);
3752
8fc897b0 3753 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1da177e4
LT		 3754 /* Configure activity LED after PHY reset */
3755 led_ctrl = E1000_READ_REG(hw, LEDCTL);
3756 led_ctrl &= IGP_ACTIVITY_LED_MASK;
3757 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
3758 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
3759 }
2d7edb92
MC		 3760
3761 /* Wait for FW to finish PHY configuration. */
3762 ret_val = e1000_get_phy_cfg_done(hw);
8fc897b0
AK		 3763 if (ret_val != E1000_SUCCESS)
3764 return ret_val;
6418ecc6 3765 e1000_release_software_semaphore(hw);
2d7edb92 3766
8fc897b0
AK		 3767 if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3))
3768 ret_val = e1000_init_lcd_from_nvm(hw);
3769
2d7edb92 3770 return ret_val;
1da177e4
LT		 3771}
3772
3773/******************************************************************************
3774* Resets the PHY
3775*
3776* hw - Struct containing variables accessed by shared code
3777*
3778* Sets bit 15 of the MII Control regiser
3779******************************************************************************/
3780int32_t
3781e1000_phy_reset(struct e1000_hw *hw)
3782{
3783 int32_t ret_val;
3784 uint16_t phy_data;
3785
3786 DEBUGFUNC("e1000_phy_reset");
3787
2d7edb92
MC		 3788 /* In the case of the phy reset being blocked, it's not an error, we
3789 * simply return success without performing the reset. */
3790 ret_val = e1000_check_phy_reset_block(hw);
3791 if (ret_val)
3792 return E1000_SUCCESS;
3793
3794 switch (hw->mac_type) {
3795 case e1000_82541_rev_2:
868d5309
MC		 3796 case e1000_82571:
3797 case e1000_82572:
cd94dd0b 3798 case e1000_ich8lan:
2d7edb92 3799 ret_val = e1000_phy_hw_reset(hw);
8fc897b0 3800 if (ret_val)
2d7edb92 3801 return ret_val;
cd94dd0b 3802
2d7edb92
MC		 3803 break;
3804 default:
1da177e4 3805 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
8fc897b0 3806 if (ret_val)
1da177e4
LT		 3807 return ret_val;
3808
3809 phy_data |= MII_CR_RESET;
3810 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
8fc897b0 3811 if (ret_val)
1da177e4
LT		 3812 return ret_val;
3813
3814 udelay(1);
2d7edb92
MC		 3815 break;
3816 }
1da177e4 3817
8fc897b0 3818 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
1da177e4
LT		 3819 e1000_phy_init_script(hw);
3820
3821 return E1000_SUCCESS;
3822}
3823
d37ea5d5
AK		 3824/******************************************************************************
3825* Work-around for 82566 power-down: on D3 entry-
3826* 1) disable gigabit link
3827* 2) write VR power-down enable
3828* 3) read it back
3829* if successful continue, else issue LCD reset and repeat
3830*
3831* hw - struct containing variables accessed by shared code
3832******************************************************************************/
3833void
3834e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3835{
3836 int32_t reg;
3837 uint16_t phy_data;
3838 int32_t retry = 0;
3839
3840 DEBUGFUNC("e1000_phy_powerdown_workaround");
3841
3842 if (hw->phy_type != e1000_phy_igp_3)
3843 return;
3844
3845 do {
3846 /* Disable link */
3847 reg = E1000_READ_REG(hw, PHY_CTRL);
3848 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3849 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3850
3851 /* Write VR power-down enable */
3852 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3853 e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data |
3854 IGP3_VR_CTRL_MODE_SHUT);
3855
3856 /* Read it back and test */
3857 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3858 if ((phy_data & IGP3_VR_CTRL_MODE_SHUT) || retry)
3859 break;
3860
3861 /* Issue PHY reset and repeat at most one more time */
3862 reg = E1000_READ_REG(hw, CTRL);
3863 E1000_WRITE_REG(hw, CTRL, reg | E1000_CTRL_PHY_RST);
3864 retry++;
3865 } while (retry);
3866
3867 return;
3868
3869}
3870
3871/******************************************************************************
3872* Work-around for 82566 Kumeran PCS lock loss:
3873* On link status change (i.e. PCI reset, speed change) and link is up and
3874* speed is gigabit-
3875* 0) if workaround is optionally disabled do nothing
3876* 1) wait 1ms for Kumeran link to come up
3877* 2) check Kumeran Diagnostic register PCS lock loss bit
3878* 3) if not set the link is locked (all is good), otherwise...
3879* 4) reset the PHY
3880* 5) repeat up to 10 times
3881* Note: this is only called for IGP3 copper when speed is 1gb.
3882*
3883* hw - struct containing variables accessed by shared code
3884******************************************************************************/
e4c780b1 3885static int32_t
d37ea5d5
AK		 3886e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
3887{
3888 int32_t ret_val;
3889 int32_t reg;
3890 int32_t cnt;
3891 uint16_t phy_data;
3892
3893 if (hw->kmrn_lock_loss_workaround_disabled)
3894 return E1000_SUCCESS;
3895
8fc897b0
AK		 3896 /* Make sure link is up before proceeding. If not just return.
3897 * Attempting this while link is negotiating fouled up link
d37ea5d5
AK		 3898 * stability */
3899 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3900 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3901
3902 if (phy_data & MII_SR_LINK_STATUS) {
3903 for (cnt = 0; cnt < 10; cnt++) {
3904 /* read once to clear */
3905 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
3906 if (ret_val)
3907 return ret_val;
3908 /* and again to get new status */
3909 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
3910 if (ret_val)
3911 return ret_val;
3912
3913 /* check for PCS lock */
3914 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3915 return E1000_SUCCESS;
3916
3917 /* Issue PHY reset */
3918 e1000_phy_hw_reset(hw);
f8ec4733 3919 mdelay(5);
d37ea5d5
AK		 3920 }
3921 /* Disable GigE link negotiation */
3922 reg = E1000_READ_REG(hw, PHY_CTRL);
3923 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3924 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3925
3926 /* unable to acquire PCS lock */
3927 return E1000_ERR_PHY;
3928 }
3929
3930 return E1000_SUCCESS;
3931}
3932
1da177e4
LT		 3933/******************************************************************************
3934* Probes the expected PHY address for known PHY IDs
3935*
3936* hw - Struct containing variables accessed by shared code
3937******************************************************************************/
d37ea5d5 3938int32_t
1da177e4
LT		 3939e1000_detect_gig_phy(struct e1000_hw *hw)
3940{
3941 int32_t phy_init_status, ret_val;
3942 uint16_t phy_id_high, phy_id_low;
3943 boolean_t match = FALSE;
3944
3945 DEBUGFUNC("e1000_detect_gig_phy");
3946
868d5309
MC		 3947 /* The 82571 firmware may still be configuring the PHY. In this
3948 * case, we cannot access the PHY until the configuration is done. So
3949 * we explicitly set the PHY values. */
cd94dd0b
AK		 3950 if (hw->mac_type == e1000_82571 ||
3951 hw->mac_type == e1000_82572) {
868d5309
MC		 3952 hw->phy_id = IGP01E1000_I_PHY_ID;
3953 hw->phy_type = e1000_phy_igp_2;
3954 return E1000_SUCCESS;
3955 }
3956
6418ecc6
JK		 3957 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work-
3958 * around that forces PHY page 0 to be set or the reads fail. The rest of
3959 * the code in this routine uses e1000_read_phy_reg to read the PHY ID.
3960 * So for ESB-2 we need to have this set so our reads won't fail. If the
3961 * attached PHY is not a e1000_phy_gg82563, the routines below will figure
3962 * this out as well. */
3963 if (hw->mac_type == e1000_80003es2lan)
3964 hw->phy_type = e1000_phy_gg82563;
3965
1da177e4
LT		 3966 /* Read the PHY ID Registers to identify which PHY is onboard. */
3967 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
cd94dd0b 3968 if (ret_val)
1da177e4
LT		 3969 return ret_val;
3970
3971 hw->phy_id = (uint32_t) (phy_id_high << 16);
3972 udelay(20);
3973 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
8fc897b0 3974 if (ret_val)
1da177e4
LT		 3975 return ret_val;
3976
3977 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
3978 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
3979
8fc897b0 3980 switch (hw->mac_type) {
1da177e4 3981 case e1000_82543:
8fc897b0 3982 if (hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
1da177e4
LT		 3983 break;
3984 case e1000_82544:
8fc897b0 3985 if (hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
1da177e4
LT		 3986 break;
3987 case e1000_82540:
3988 case e1000_82545:
3989 case e1000_82545_rev_3:
3990 case e1000_82546:
3991 case e1000_82546_rev_3:
8fc897b0 3992 if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
1da177e4
LT		 3993 break;
3994 case e1000_82541:
3995 case e1000_82541_rev_2:
3996 case e1000_82547:
3997 case e1000_82547_rev_2:
8fc897b0 3998 if (hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
1da177e4 3999 break;
2d7edb92 4000 case e1000_82573:
8fc897b0 4001 if (hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
2d7edb92 4002 break;
6418ecc6
JK		 4003 case e1000_80003es2lan:
4004 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
4005 break;
cd94dd0b
AK		 4006 case e1000_ich8lan:
4007 if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE;
4008 if (hw->phy_id == IFE_E_PHY_ID) match = TRUE;
4009 if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE;
4010 if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE;
4011 break;
1da177e4
LT		 4012 default:
4013 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
4014 return -E1000_ERR_CONFIG;
4015 }
4016 phy_init_status = e1000_set_phy_type(hw);
4017
4018 if ((match) && (phy_init_status == E1000_SUCCESS)) {
4019 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
4020 return E1000_SUCCESS;
4021 }
4022 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
4023 return -E1000_ERR_PHY;
4024}
4025
4026/******************************************************************************
4027* Resets the PHY's DSP
4028*
4029* hw - Struct containing variables accessed by shared code
4030******************************************************************************/
4031static int32_t
4032e1000_phy_reset_dsp(struct e1000_hw *hw)
4033{
4034 int32_t ret_val;
4035 DEBUGFUNC("e1000_phy_reset_dsp");
4036
4037 do {
6418ecc6
JK		 4038 if (hw->phy_type != e1000_phy_gg82563) {
4039 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
8fc897b0 4040 if (ret_val) break;
6418ecc6 4041 }
1da177e4 4042 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
8fc897b0 4043 if (ret_val) break;
1da177e4 4044 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
8fc897b0 4045 if (ret_val) break;
1da177e4 4046 ret_val = E1000_SUCCESS;
8fc897b0 4047 } while (0);
1da177e4
LT		 4048
4049 return ret_val;
4050}
4051
4052/******************************************************************************
4053* Get PHY information from various PHY registers for igp PHY only.
4054*
4055* hw - Struct containing variables accessed by shared code
4056* phy_info - PHY information structure
4057******************************************************************************/
cff93eb3 4058static int32_t
1da177e4
LT		 4059e1000_phy_igp_get_info(struct e1000_hw *hw,
4060 struct e1000_phy_info *phy_info)
4061{
4062 int32_t ret_val;
4063 uint16_t phy_data, polarity, min_length, max_length, average;
4064
4065 DEBUGFUNC("e1000_phy_igp_get_info");
4066
4067 /* The downshift status is checked only once, after link is established,
4068 * and it stored in the hw->speed_downgraded parameter. */
2d7edb92 4069 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
1da177e4
LT		 4070
4071 /* IGP01E1000 does not need to support it. */
4072 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4073
4074 /* IGP01E1000 always correct polarity reversal */
4075 phy_info->polarity_correction = e1000_polarity_reversal_enabled;
4076
4077 /* Check polarity status */
4078 ret_val = e1000_check_polarity(hw, &polarity);
8fc897b0 4079 if (ret_val)
1da177e4
LT		 4080 return ret_val;
4081
4082 phy_info->cable_polarity = polarity;
4083
4084 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
8fc897b0 4085 if (ret_val)
1da177e4
LT		 4086 return ret_val;
4087
4088 phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >>
4089 IGP01E1000_PSSR_MDIX_SHIFT;
4090
8fc897b0 4091 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1da177e4
LT		 4092 IGP01E1000_PSSR_SPEED_1000MBPS) {
4093 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
4094 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
8fc897b0 4095 if (ret_val)
1da177e4
LT		 4096 return ret_val;
4097
4098 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4099 SR_1000T_LOCAL_RX_STATUS_SHIFT;
4100 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4101 SR_1000T_REMOTE_RX_STATUS_SHIFT;
4102
4103 /* Get cable length */
4104 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
8fc897b0 4105 if (ret_val)
1da177e4
LT		 4106 return ret_val;
4107
2d7edb92 4108 /* Translate to old method */
1da177e4
LT		 4109 average = (max_length + min_length) / 2;
4110
8fc897b0 4111 if (average <= e1000_igp_cable_length_50)
1da177e4 4112 phy_info->cable_length = e1000_cable_length_50;
8fc897b0 4113 else if (average <= e1000_igp_cable_length_80)
1da177e4 4114 phy_info->cable_length = e1000_cable_length_50_80;
8fc897b0 4115 else if (average <= e1000_igp_cable_length_110)
1da177e4 4116 phy_info->cable_length = e1000_cable_length_80_110;
8fc897b0 4117 else if (average <= e1000_igp_cable_length_140)
1da177e4
LT		 4118 phy_info->cable_length = e1000_cable_length_110_140;
4119 else
4120 phy_info->cable_length = e1000_cable_length_140;
4121 }
4122
4123 return E1000_SUCCESS;
4124}
4125
d37ea5d5
AK		 4126/******************************************************************************
4127* Get PHY information from various PHY registers for ife PHY only.
4128*
4129* hw - Struct containing variables accessed by shared code
4130* phy_info - PHY information structure
4131******************************************************************************/
e4c780b1 4132static int32_t
d37ea5d5
AK		 4133e1000_phy_ife_get_info(struct e1000_hw *hw,
4134 struct e1000_phy_info *phy_info)
4135{
4136 int32_t ret_val;
4137 uint16_t phy_data, polarity;
4138
4139 DEBUGFUNC("e1000_phy_ife_get_info");
4140
4141 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4142 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4143
4144 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
4145 if (ret_val)
4146 return ret_val;
4147 phy_info->polarity_correction =
4148 (phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >>
4149 IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT;
4150
4151 if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) {
4152 ret_val = e1000_check_polarity(hw, &polarity);
4153 if (ret_val)
4154 return ret_val;
4155 } else {
4156 /* Polarity is forced. */
4157 polarity = (phy_data & IFE_PSC_FORCE_POLARITY) >>
4158 IFE_PSC_FORCE_POLARITY_SHIFT;
4159 }
4160 phy_info->cable_polarity = polarity;
4161
4162 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
4163 if (ret_val)
4164 return ret_val;
4165
4166 phy_info->mdix_mode =
4167 (phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >>
4168 IFE_PMC_MDIX_MODE_SHIFT;
4169
4170 return E1000_SUCCESS;
4171}
4172
1da177e4
LT		 4173/******************************************************************************
4174* Get PHY information from various PHY registers fot m88 PHY only.
4175*
4176* hw - Struct containing variables accessed by shared code
4177* phy_info - PHY information structure
4178******************************************************************************/
3ad2cc67 4179static int32_t
1da177e4
LT		 4180e1000_phy_m88_get_info(struct e1000_hw *hw,
4181 struct e1000_phy_info *phy_info)
4182{
4183 int32_t ret_val;
4184 uint16_t phy_data, polarity;
4185
4186 DEBUGFUNC("e1000_phy_m88_get_info");
4187
4188 /* The downshift status is checked only once, after link is established,
4189 * and it stored in the hw->speed_downgraded parameter. */
2d7edb92 4190 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
1da177e4
LT		 4191
4192 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
8fc897b0 4193 if (ret_val)
1da177e4
LT		 4194 return ret_val;
4195
4196 phy_info->extended_10bt_distance =
4197 (phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
4198 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT;
4199 phy_info->polarity_correction =
4200 (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
4201 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT;
4202
4203 /* Check polarity status */
4204 ret_val = e1000_check_polarity(hw, &polarity);
8fc897b0 4205 if (ret_val)
76c224bc 4206 return ret_val;
1da177e4
LT		 4207 phy_info->cable_polarity = polarity;
4208
4209 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
8fc897b0 4210 if (ret_val)
1da177e4
LT		 4211 return ret_val;
4212
4213 phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >>
4214 M88E1000_PSSR_MDIX_SHIFT;
4215
4216 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
4217 /* Cable Length Estimation and Local/Remote Receiver Information
4218 * are only valid at 1000 Mbps.
4219 */
6418ecc6
JK		 4220 if (hw->phy_type != e1000_phy_gg82563) {
4221 phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
4222 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
4223 } else {
4224 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
4225 &phy_data);
4226 if (ret_val)
4227 return ret_val;
4228
4229 phy_info->cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH;
4230 }
1da177e4
LT		 4231
4232 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
8fc897b0 4233 if (ret_val)
1da177e4
LT		 4234 return ret_val;
4235
4236 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4237 SR_1000T_LOCAL_RX_STATUS_SHIFT;
4238
4239 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4240 SR_1000T_REMOTE_RX_STATUS_SHIFT;
4241 }
4242
4243 return E1000_SUCCESS;
4244}
4245
4246/******************************************************************************
4247* Get PHY information from various PHY registers
4248*
4249* hw - Struct containing variables accessed by shared code
4250* phy_info - PHY information structure
4251******************************************************************************/
4252int32_t
4253e1000_phy_get_info(struct e1000_hw *hw,
4254 struct e1000_phy_info *phy_info)
4255{
4256 int32_t ret_val;
4257 uint16_t phy_data;
4258
4259 DEBUGFUNC("e1000_phy_get_info");
4260
4261 phy_info->cable_length = e1000_cable_length_undefined;
4262 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
4263 phy_info->cable_polarity = e1000_rev_polarity_undefined;
4264 phy_info->downshift = e1000_downshift_undefined;
4265 phy_info->polarity_correction = e1000_polarity_reversal_undefined;
4266 phy_info->mdix_mode = e1000_auto_x_mode_undefined;
4267 phy_info->local_rx = e1000_1000t_rx_status_undefined;
4268 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
4269
8fc897b0 4270 if (hw->media_type != e1000_media_type_copper) {
1da177e4
LT		 4271 DEBUGOUT("PHY info is only valid for copper media\n");
4272 return -E1000_ERR_CONFIG;
4273 }
4274
4275 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 4276 if (ret_val)
1da177e4
LT		 4277 return ret_val;
4278
4279 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 4280 if (ret_val)
1da177e4
LT		 4281 return ret_val;
4282
8fc897b0 4283 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
1da177e4
LT		 4284 DEBUGOUT("PHY info is only valid if link is up\n");
4285 return -E1000_ERR_CONFIG;
4286 }
4287
cd94dd0b
AK		 4288 if (hw->phy_type == e1000_phy_igp ||
4289 hw->phy_type == e1000_phy_igp_3 ||
2d7edb92 4290 hw->phy_type == e1000_phy_igp_2)
1da177e4 4291 return e1000_phy_igp_get_info(hw, phy_info);
cd94dd0b
AK		 4292 else if (hw->phy_type == e1000_phy_ife)
4293 return e1000_phy_ife_get_info(hw, phy_info);
1da177e4
LT		 4294 else
4295 return e1000_phy_m88_get_info(hw, phy_info);
4296}
4297
4298int32_t
4299e1000_validate_mdi_setting(struct e1000_hw *hw)
4300{
4301 DEBUGFUNC("e1000_validate_mdi_settings");
4302
8fc897b0 4303 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
1da177e4
LT		 4304 DEBUGOUT("Invalid MDI setting detected\n");
4305 hw->mdix = 1;
4306 return -E1000_ERR_CONFIG;
4307 }
4308 return E1000_SUCCESS;
4309}
4310
4311
4312/******************************************************************************
4313 * Sets up eeprom variables in the hw struct. Must be called after mac_type
0f15a8fa
JK		 4314 * is configured. Additionally, if this is ICH8, the flash controller GbE
4315 * registers must be mapped, or this will crash.
1da177e4
LT		 4316 *
4317 * hw - Struct containing variables accessed by shared code
4318 *****************************************************************************/
2d7edb92 4319int32_t
1da177e4
LT		 4320e1000_init_eeprom_params(struct e1000_hw *hw)
4321{
4322 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4323 uint32_t eecd = E1000_READ_REG(hw, EECD);
2d7edb92 4324 int32_t ret_val = E1000_SUCCESS;
1da177e4
LT		 4325 uint16_t eeprom_size;
4326
4327 DEBUGFUNC("e1000_init_eeprom_params");
4328
4329 switch (hw->mac_type) {
4330 case e1000_82542_rev2_0:
4331 case e1000_82542_rev2_1:
4332 case e1000_82543:
4333 case e1000_82544:
4334 eeprom->type = e1000_eeprom_microwire;
4335 eeprom->word_size = 64;
4336 eeprom->opcode_bits = 3;
4337 eeprom->address_bits = 6;
4338 eeprom->delay_usec = 50;
2d7edb92
MC		 4339 eeprom->use_eerd = FALSE;
4340 eeprom->use_eewr = FALSE;
1da177e4
LT		 4341 break;
4342 case e1000_82540:
4343 case e1000_82545:
4344 case e1000_82545_rev_3:
4345 case e1000_82546:
4346 case e1000_82546_rev_3:
4347 eeprom->type = e1000_eeprom_microwire;
4348 eeprom->opcode_bits = 3;
4349 eeprom->delay_usec = 50;
8fc897b0 4350 if (eecd & E1000_EECD_SIZE) {
1da177e4
LT		 4351 eeprom->word_size = 256;
4352 eeprom->address_bits = 8;
4353 } else {
4354 eeprom->word_size = 64;
4355 eeprom->address_bits = 6;
4356 }
2d7edb92
MC		 4357 eeprom->use_eerd = FALSE;
4358 eeprom->use_eewr = FALSE;
1da177e4
LT		 4359 break;
4360 case e1000_82541:
4361 case e1000_82541_rev_2:
4362 case e1000_82547:
4363 case e1000_82547_rev_2:
4364 if (eecd & E1000_EECD_TYPE) {
4365 eeprom->type = e1000_eeprom_spi;
4366 eeprom->opcode_bits = 8;
4367 eeprom->delay_usec = 1;
4368 if (eecd & E1000_EECD_ADDR_BITS) {
4369 eeprom->page_size = 32;
4370 eeprom->address_bits = 16;
4371 } else {
4372 eeprom->page_size = 8;
4373 eeprom->address_bits = 8;
4374 }
4375 } else {
4376 eeprom->type = e1000_eeprom_microwire;
4377 eeprom->opcode_bits = 3;
4378 eeprom->delay_usec = 50;
4379 if (eecd & E1000_EECD_ADDR_BITS) {
4380 eeprom->word_size = 256;
4381 eeprom->address_bits = 8;
4382 } else {
4383 eeprom->word_size = 64;
4384 eeprom->address_bits = 6;
4385 }
4386 }
2d7edb92
MC		 4387 eeprom->use_eerd = FALSE;
4388 eeprom->use_eewr = FALSE;
4389 break;
868d5309
MC		 4390 case e1000_82571:
4391 case e1000_82572:
4392 eeprom->type = e1000_eeprom_spi;
4393 eeprom->opcode_bits = 8;
4394 eeprom->delay_usec = 1;
4395 if (eecd & E1000_EECD_ADDR_BITS) {
4396 eeprom->page_size = 32;
4397 eeprom->address_bits = 16;
4398 } else {
4399 eeprom->page_size = 8;
4400 eeprom->address_bits = 8;
4401 }
4402 eeprom->use_eerd = FALSE;
4403 eeprom->use_eewr = FALSE;
4404 break;
2d7edb92
MC		 4405 case e1000_82573:
4406 eeprom->type = e1000_eeprom_spi;
4407 eeprom->opcode_bits = 8;
4408 eeprom->delay_usec = 1;
4409 if (eecd & E1000_EECD_ADDR_BITS) {
4410 eeprom->page_size = 32;
4411 eeprom->address_bits = 16;
4412 } else {
4413 eeprom->page_size = 8;
4414 eeprom->address_bits = 8;
4415 }
4416 eeprom->use_eerd = TRUE;
4417 eeprom->use_eewr = TRUE;
8fc897b0 4418 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
2d7edb92
MC		 4419 eeprom->type = e1000_eeprom_flash;
4420 eeprom->word_size = 2048;
4421
4422 /* Ensure that the Autonomous FLASH update bit is cleared due to
4423 * Flash update issue on parts which use a FLASH for NVM. */
4424 eecd &= ~E1000_EECD_AUPDEN;
4425 E1000_WRITE_REG(hw, EECD, eecd);
4426 }
1da177e4 4427 break;
6418ecc6
JK		 4428 case e1000_80003es2lan:
4429 eeprom->type = e1000_eeprom_spi;
4430 eeprom->opcode_bits = 8;
4431 eeprom->delay_usec = 1;
4432 if (eecd & E1000_EECD_ADDR_BITS) {
4433 eeprom->page_size = 32;
4434 eeprom->address_bits = 16;
4435 } else {
4436 eeprom->page_size = 8;
4437 eeprom->address_bits = 8;
4438 }
4439 eeprom->use_eerd = TRUE;
4440 eeprom->use_eewr = FALSE;
4441 break;
cd94dd0b
AK		 4442 case e1000_ich8lan:
4443 {
4444 int32_t i = 0;
4445 uint32_t flash_size = E1000_READ_ICH8_REG(hw, ICH8_FLASH_GFPREG);
4446
4447 eeprom->type = e1000_eeprom_ich8;
4448 eeprom->use_eerd = FALSE;
4449 eeprom->use_eewr = FALSE;
4450 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
4451
4452 /* Zero the shadow RAM structure. But don't load it from NVM
4453 * so as to save time for driver init */
4454 if (hw->eeprom_shadow_ram != NULL) {
4455 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4456 hw->eeprom_shadow_ram[i].modified = FALSE;
4457 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
4458 }
4459 }
4460
4461 hw->flash_base_addr = (flash_size & ICH8_GFPREG_BASE_MASK) *
4462 ICH8_FLASH_SECTOR_SIZE;
4463
4464 hw->flash_bank_size = ((flash_size >> 16) & ICH8_GFPREG_BASE_MASK) + 1;
4465 hw->flash_bank_size -= (flash_size & ICH8_GFPREG_BASE_MASK);
4466 hw->flash_bank_size *= ICH8_FLASH_SECTOR_SIZE;
4467 hw->flash_bank_size /= 2 * sizeof(uint16_t);
4468
4469 break;
4470 }
1da177e4
LT		 4471 default:
4472 break;
4473 }
4474
4475 if (eeprom->type == e1000_eeprom_spi) {
2d7edb92
MC		 4476 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
4477 * 32KB (incremented by powers of 2).
4478 */
8fc897b0 4479 if (hw->mac_type <= e1000_82547_rev_2) {
2d7edb92
MC		 4480 /* Set to default value for initial eeprom read. */
4481 eeprom->word_size = 64;
4482 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
8fc897b0 4483 if (ret_val)
2d7edb92
MC		 4484 return ret_val;
4485 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
4486 /* 256B eeprom size was not supported in earlier hardware, so we
4487 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
4488 * is never the result used in the shifting logic below. */
8fc897b0 4489 if (eeprom_size)
2d7edb92
MC		 4490 eeprom_size++;
4491 } else {
4492 eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >>
4493 E1000_EECD_SIZE_EX_SHIFT);
1da177e4 4494 }
2d7edb92
MC		 4495
4496 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
1da177e4 4497 }
2d7edb92 4498 return ret_val;
1da177e4
LT		 4499}
4500
4501/******************************************************************************
4502 * Raises the EEPROM's clock input.
4503 *
4504 * hw - Struct containing variables accessed by shared code
4505 * eecd - EECD's current value
4506 *****************************************************************************/
4507static void
4508e1000_raise_ee_clk(struct e1000_hw *hw,
4509 uint32_t *eecd)
4510{
4511 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
4512 * wait <delay> microseconds.
4513 */
4514 *eecd = *eecd | E1000_EECD_SK;
4515 E1000_WRITE_REG(hw, EECD, *eecd);
4516 E1000_WRITE_FLUSH(hw);
4517 udelay(hw->eeprom.delay_usec);
4518}
4519
4520/******************************************************************************
4521 * Lowers the EEPROM's clock input.
4522 *
4523 * hw - Struct containing variables accessed by shared code
4524 * eecd - EECD's current value
4525 *****************************************************************************/
4526static void
4527e1000_lower_ee_clk(struct e1000_hw *hw,
4528 uint32_t *eecd)
4529{
4530 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
4531 * wait 50 microseconds.
4532 */
4533 *eecd = *eecd & ~E1000_EECD_SK;
4534 E1000_WRITE_REG(hw, EECD, *eecd);
4535 E1000_WRITE_FLUSH(hw);
4536 udelay(hw->eeprom.delay_usec);
4537}
4538
4539/******************************************************************************
4540 * Shift data bits out to the EEPROM.
4541 *
4542 * hw - Struct containing variables accessed by shared code
4543 * data - data to send to the EEPROM
4544 * count - number of bits to shift out
4545 *****************************************************************************/
4546static void
4547e1000_shift_out_ee_bits(struct e1000_hw *hw,
4548 uint16_t data,
4549 uint16_t count)
4550{
4551 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4552 uint32_t eecd;
4553 uint32_t mask;
4554
4555 /* We need to shift "count" bits out to the EEPROM. So, value in the
4556 * "data" parameter will be shifted out to the EEPROM one bit at a time.
4557 * In order to do this, "data" must be broken down into bits.
4558 */
4559 mask = 0x01 << (count - 1);
4560 eecd = E1000_READ_REG(hw, EECD);
4561 if (eeprom->type == e1000_eeprom_microwire) {
4562 eecd &= ~E1000_EECD_DO;
4563 } else if (eeprom->type == e1000_eeprom_spi) {
4564 eecd |= E1000_EECD_DO;
4565 }
4566 do {
4567 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
4568 * and then raising and then lowering the clock (the SK bit controls
4569 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
4570 * by setting "DI" to "0" and then raising and then lowering the clock.
4571 */
4572 eecd &= ~E1000_EECD_DI;
4573
8fc897b0 4574 if (data & mask)
1da177e4
LT		 4575 eecd |= E1000_EECD_DI;
4576
4577 E1000_WRITE_REG(hw, EECD, eecd);
4578 E1000_WRITE_FLUSH(hw);
4579
4580 udelay(eeprom->delay_usec);
4581
4582 e1000_raise_ee_clk(hw, &eecd);
4583 e1000_lower_ee_clk(hw, &eecd);
4584
4585 mask = mask >> 1;
4586
8fc897b0 4587 } while (mask);
1da177e4
LT		 4588
4589 /* We leave the "DI" bit set to "0" when we leave this routine. */
4590 eecd &= ~E1000_EECD_DI;
4591 E1000_WRITE_REG(hw, EECD, eecd);
4592}
4593
4594/******************************************************************************
4595 * Shift data bits in from the EEPROM
4596 *
4597 * hw - Struct containing variables accessed by shared code
4598 *****************************************************************************/
4599static uint16_t
4600e1000_shift_in_ee_bits(struct e1000_hw *hw,
4601 uint16_t count)
4602{
4603 uint32_t eecd;
4604 uint32_t i;
4605 uint16_t data;
4606
4607 /* In order to read a register from the EEPROM, we need to shift 'count'
4608 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
4609 * input to the EEPROM (setting the SK bit), and then reading the value of
4610 * the "DO" bit. During this "shifting in" process the "DI" bit should
4611 * always be clear.
4612 */
4613
4614 eecd = E1000_READ_REG(hw, EECD);
4615
4616 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
4617 data = 0;
4618
8fc897b0 4619 for (i = 0; i < count; i++) {
1da177e4
LT		 4620 data = data << 1;
4621 e1000_raise_ee_clk(hw, &eecd);
4622
4623 eecd = E1000_READ_REG(hw, EECD);
4624
4625 eecd &= ~(E1000_EECD_DI);
8fc897b0 4626 if (eecd & E1000_EECD_DO)
1da177e4
LT		 4627 data |= 1;
4628
4629 e1000_lower_ee_clk(hw, &eecd);
4630 }
4631
4632 return data;
4633}
4634
4635/******************************************************************************
4636 * Prepares EEPROM for access
4637 *
4638 * hw - Struct containing variables accessed by shared code
4639 *
4640 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
4641 * function should be called before issuing a command to the EEPROM.
4642 *****************************************************************************/
4643static int32_t
4644e1000_acquire_eeprom(struct e1000_hw *hw)
4645{
4646 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4647 uint32_t eecd, i=0;
4648
4649 DEBUGFUNC("e1000_acquire_eeprom");
4650
6418ecc6
JK		 4651 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
4652 return -E1000_ERR_SWFW_SYNC;
1da177e4
LT		 4653 eecd = E1000_READ_REG(hw, EECD);
4654
2d7edb92 4655 if (hw->mac_type != e1000_82573) {
868d5309 4656 /* Request EEPROM Access */
8fc897b0 4657 if (hw->mac_type > e1000_82544) {
868d5309 4658 eecd |= E1000_EECD_REQ;
1da177e4 4659 E1000_WRITE_REG(hw, EECD, eecd);
868d5309 4660 eecd = E1000_READ_REG(hw, EECD);
8fc897b0 4661 while ((!(eecd & E1000_EECD_GNT)) &&
868d5309
MC		 4662 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
4663 i++;
4664 udelay(5);
4665 eecd = E1000_READ_REG(hw, EECD);
4666 }
8fc897b0 4667 if (!(eecd & E1000_EECD_GNT)) {
868d5309
MC		 4668 eecd &= ~E1000_EECD_REQ;
4669 E1000_WRITE_REG(hw, EECD, eecd);
4670 DEBUGOUT("Could not acquire EEPROM grant\n");
6418ecc6 4671 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
868d5309
MC		 4672 return -E1000_ERR_EEPROM;
4673 }
1da177e4
LT		 4674 }
4675 }
4676
4677 /* Setup EEPROM for Read/Write */
4678
4679 if (eeprom->type == e1000_eeprom_microwire) {
4680 /* Clear SK and DI */
4681 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
4682 E1000_WRITE_REG(hw, EECD, eecd);
4683
4684 /* Set CS */
4685 eecd |= E1000_EECD_CS;
4686 E1000_WRITE_REG(hw, EECD, eecd);
4687 } else if (eeprom->type == e1000_eeprom_spi) {
4688 /* Clear SK and CS */
4689 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4690 E1000_WRITE_REG(hw, EECD, eecd);
4691 udelay(1);
4692 }
4693
4694 return E1000_SUCCESS;
4695}
4696
4697/******************************************************************************
4698 * Returns EEPROM to a "standby" state
4699 *
4700 * hw - Struct containing variables accessed by shared code
4701 *****************************************************************************/
4702static void
4703e1000_standby_eeprom(struct e1000_hw *hw)
4704{
4705 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4706 uint32_t eecd;
4707
4708 eecd = E1000_READ_REG(hw, EECD);
4709
8fc897b0 4710 if (eeprom->type == e1000_eeprom_microwire) {
1da177e4
LT		 4711 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4712 E1000_WRITE_REG(hw, EECD, eecd);
4713 E1000_WRITE_FLUSH(hw);
4714 udelay(eeprom->delay_usec);
4715
4716 /* Clock high */
4717 eecd |= E1000_EECD_SK;
4718 E1000_WRITE_REG(hw, EECD, eecd);
4719 E1000_WRITE_FLUSH(hw);
4720 udelay(eeprom->delay_usec);
4721
4722 /* Select EEPROM */
4723 eecd |= E1000_EECD_CS;
4724 E1000_WRITE_REG(hw, EECD, eecd);
4725 E1000_WRITE_FLUSH(hw);
4726 udelay(eeprom->delay_usec);
4727
4728 /* Clock low */
4729 eecd &= ~E1000_EECD_SK;
4730 E1000_WRITE_REG(hw, EECD, eecd);
4731 E1000_WRITE_FLUSH(hw);
4732 udelay(eeprom->delay_usec);
8fc897b0 4733 } else if (eeprom->type == e1000_eeprom_spi) {
1da177e4
LT		 4734 /* Toggle CS to flush commands */
4735 eecd |= E1000_EECD_CS;
4736 E1000_WRITE_REG(hw, EECD, eecd);
4737 E1000_WRITE_FLUSH(hw);
4738 udelay(eeprom->delay_usec);
4739 eecd &= ~E1000_EECD_CS;
4740 E1000_WRITE_REG(hw, EECD, eecd);
4741 E1000_WRITE_FLUSH(hw);
4742 udelay(eeprom->delay_usec);
4743 }
4744}
4745
4746/******************************************************************************
4747 * Terminates a command by inverting the EEPROM's chip select pin
4748 *
4749 * hw - Struct containing variables accessed by shared code
4750 *****************************************************************************/
4751static void
4752e1000_release_eeprom(struct e1000_hw *hw)
4753{
4754 uint32_t eecd;
4755
4756 DEBUGFUNC("e1000_release_eeprom");
4757
4758 eecd = E1000_READ_REG(hw, EECD);
4759
4760 if (hw->eeprom.type == e1000_eeprom_spi) {
4761 eecd |= E1000_EECD_CS; /* Pull CS high */
4762 eecd &= ~E1000_EECD_SK; /* Lower SCK */
4763
4764 E1000_WRITE_REG(hw, EECD, eecd);
4765
4766 udelay(hw->eeprom.delay_usec);
8fc897b0 4767 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
1da177e4
LT		 4768 /* cleanup eeprom */
4769
4770 /* CS on Microwire is active-high */
4771 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
4772
4773 E1000_WRITE_REG(hw, EECD, eecd);
4774
4775 /* Rising edge of clock */
4776 eecd |= E1000_EECD_SK;
4777 E1000_WRITE_REG(hw, EECD, eecd);
4778 E1000_WRITE_FLUSH(hw);
4779 udelay(hw->eeprom.delay_usec);
4780
4781 /* Falling edge of clock */
4782 eecd &= ~E1000_EECD_SK;
4783 E1000_WRITE_REG(hw, EECD, eecd);
4784 E1000_WRITE_FLUSH(hw);
4785 udelay(hw->eeprom.delay_usec);
4786 }
4787
4788 /* Stop requesting EEPROM access */
8fc897b0 4789 if (hw->mac_type > e1000_82544) {
1da177e4
LT		 4790 eecd &= ~E1000_EECD_REQ;
4791 E1000_WRITE_REG(hw, EECD, eecd);
4792 }
2d7edb92 4793
6418ecc6 4794 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
1da177e4
LT		 4795}
4796
4797/******************************************************************************
4798 * Reads a 16 bit word from the EEPROM.
4799 *
4800 * hw - Struct containing variables accessed by shared code
4801 *****************************************************************************/
4802int32_t
4803e1000_spi_eeprom_ready(struct e1000_hw *hw)
4804{
4805 uint16_t retry_count = 0;
4806 uint8_t spi_stat_reg;
4807
4808 DEBUGFUNC("e1000_spi_eeprom_ready");
4809
4810 /* Read "Status Register" repeatedly until the LSB is cleared. The
4811 * EEPROM will signal that the command has been completed by clearing
4812 * bit 0 of the internal status register. If it's not cleared within
4813 * 5 milliseconds, then error out.
4814 */
4815 retry_count = 0;
4816 do {
4817 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
4818 hw->eeprom.opcode_bits);
4819 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
4820 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
4821 break;
4822
4823 udelay(5);
4824 retry_count += 5;
4825
4826 e1000_standby_eeprom(hw);
8fc897b0 4827 } while (retry_count < EEPROM_MAX_RETRY_SPI);
1da177e4
LT		 4828
4829 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
4830 * only 0-5mSec on 5V devices)
4831 */
8fc897b0 4832 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
1da177e4
LT		 4833 DEBUGOUT("SPI EEPROM Status error\n");
4834 return -E1000_ERR_EEPROM;
4835 }
4836
4837 return E1000_SUCCESS;
4838}
4839
4840/******************************************************************************
4841 * Reads a 16 bit word from the EEPROM.
4842 *
4843 * hw - Struct containing variables accessed by shared code
4844 * offset - offset of word in the EEPROM to read
4845 * data - word read from the EEPROM
4846 * words - number of words to read
4847 *****************************************************************************/
4848int32_t
4849e1000_read_eeprom(struct e1000_hw *hw,
4850 uint16_t offset,
4851 uint16_t words,
4852 uint16_t *data)
4853{
4854 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4855 uint32_t i = 0;
2d7edb92 4856 int32_t ret_val;
1da177e4
LT		 4857
4858 DEBUGFUNC("e1000_read_eeprom");
2d7edb92 4859
1da177e4
LT		 4860 /* A check for invalid values: offset too large, too many words, and not
4861 * enough words.
4862 */
8fc897b0 4863 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
1da177e4
LT		 4864 (words == 0)) {
4865 DEBUGOUT("\"words\" parameter out of bounds\n");
4866 return -E1000_ERR_EEPROM;
4867 }
4868
4d351858
JK		 4869 /* FLASH reads without acquiring the semaphore are safe */
4870 if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
8fc897b0 4871 hw->eeprom.use_eerd == FALSE) {
4d351858 4872 switch (hw->mac_type) {
6418ecc6
JK		 4873 case e1000_80003es2lan:
4874 break;
4d351858
JK		 4875 default:
4876 /* Prepare the EEPROM for reading */
4877 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4878 return -E1000_ERR_EEPROM;
4879 break;
4880 }
2d7edb92
MC		 4881 }
4882
96838a40 4883 if (eeprom->use_eerd == TRUE) {
2d7edb92
MC		 4884 ret_val = e1000_read_eeprom_eerd(hw, offset, words, data);
4885 if ((e1000_is_onboard_nvm_eeprom(hw) == TRUE) ||
4886 (hw->mac_type != e1000_82573))
4887 e1000_release_eeprom(hw);
4888 return ret_val;
4889 }
1da177e4 4890
cd94dd0b
AK		 4891 if (eeprom->type == e1000_eeprom_ich8)
4892 return e1000_read_eeprom_ich8(hw, offset, words, data);
4893
4894 if (eeprom->type == e1000_eeprom_spi) {
1da177e4
LT		 4895 uint16_t word_in;
4896 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
4897
8fc897b0 4898 if (e1000_spi_eeprom_ready(hw)) {
1da177e4
LT		 4899 e1000_release_eeprom(hw);
4900 return -E1000_ERR_EEPROM;
4901 }
4902
4903 e1000_standby_eeprom(hw);
4904
4905 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
8fc897b0 4906 if ((eeprom->address_bits == 8) && (offset >= 128))
1da177e4
LT		 4907 read_opcode |= EEPROM_A8_OPCODE_SPI;
4908
4909 /* Send the READ command (opcode + addr) */
4910 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
4911 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
4912
4913 /* Read the data. The address of the eeprom internally increments with
4914 * each byte (spi) being read, saving on the overhead of eeprom setup
4915 * and tear-down. The address counter will roll over if reading beyond
4916 * the size of the eeprom, thus allowing the entire memory to be read
4917 * starting from any offset. */
4918 for (i = 0; i < words; i++) {
4919 word_in = e1000_shift_in_ee_bits(hw, 16);
4920 data[i] = (word_in >> 8) | (word_in << 8);
4921 }
8fc897b0 4922 } else if (eeprom->type == e1000_eeprom_microwire) {
1da177e4
LT		 4923 for (i = 0; i < words; i++) {
4924 /* Send the READ command (opcode + addr) */
4925 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
4926 eeprom->opcode_bits);
4927 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
4928 eeprom->address_bits);
4929
4930 /* Read the data. For microwire, each word requires the overhead
4931 * of eeprom setup and tear-down. */
4932 data[i] = e1000_shift_in_ee_bits(hw, 16);
4933 e1000_standby_eeprom(hw);
4934 }
4935 }
4936
4937 /* End this read operation */
4938 e1000_release_eeprom(hw);
4939
4940 return E1000_SUCCESS;
4941}
4942
4943/******************************************************************************
2d7edb92 4944 * Reads a 16 bit word from the EEPROM using the EERD register.
1da177e4
LT		 4945 *
4946 * hw - Struct containing variables accessed by shared code
2d7edb92
MC		 4947 * offset - offset of word in the EEPROM to read
4948 * data - word read from the EEPROM
4949 * words - number of words to read
1da177e4 4950 *****************************************************************************/
3ad2cc67 4951static int32_t
2d7edb92
MC		 4952e1000_read_eeprom_eerd(struct e1000_hw *hw,
4953 uint16_t offset,
4954 uint16_t words,
4955 uint16_t *data)
1da177e4 4956{
2d7edb92
MC		 4957 uint32_t i, eerd = 0;
4958 int32_t error = 0;
1da177e4 4959
2d7edb92
MC		 4960 for (i = 0; i < words; i++) {
4961 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
4962 E1000_EEPROM_RW_REG_START;
1da177e4 4963
2d7edb92
MC		 4964 E1000_WRITE_REG(hw, EERD, eerd);
4965 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
76c224bc 4966
8fc897b0 4967 if (error) {
2d7edb92 4968 break;
1da177e4 4969 }
2d7edb92 4970 data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA);
76c224bc 4971
1da177e4 4972 }
76c224bc 4973
2d7edb92 4974 return error;
1da177e4
LT		 4975}
4976
4977/******************************************************************************
2d7edb92 4978 * Writes a 16 bit word from the EEPROM using the EEWR register.
1da177e4
LT		 4979 *
4980 * hw - Struct containing variables accessed by shared code
2d7edb92
MC		 4981 * offset - offset of word in the EEPROM to read
4982 * data - word read from the EEPROM
4983 * words - number of words to read
1da177e4 4984 *****************************************************************************/
3ad2cc67 4985static int32_t
2d7edb92
MC		 4986e1000_write_eeprom_eewr(struct e1000_hw *hw,
4987 uint16_t offset,
4988 uint16_t words,
4989 uint16_t *data)
1da177e4 4990{
2d7edb92
MC		 4991 uint32_t register_value = 0;
4992 uint32_t i = 0;
4993 int32_t error = 0;
1da177e4 4994
6418ecc6
JK		 4995 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
4996 return -E1000_ERR_SWFW_SYNC;
4997
2d7edb92 4998 for (i = 0; i < words; i++) {
76c224bc
AK		 4999 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) |
5000 ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) |
2d7edb92 5001 E1000_EEPROM_RW_REG_START;
1da177e4 5002
2d7edb92 5003 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
8fc897b0 5004 if (error) {
2d7edb92 5005 break;
76c224bc 5006 }
2d7edb92
MC		 5007
5008 E1000_WRITE_REG(hw, EEWR, register_value);
76c224bc 5009
2d7edb92 5010 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
76c224bc 5011
8fc897b0 5012 if (error) {
2d7edb92 5013 break;
76c224bc 5014 }
2d7edb92 5015 }
76c224bc 5016
6418ecc6 5017 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
2d7edb92
MC		 5018 return error;
5019}
5020
5021/******************************************************************************
5022 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
5023 *
5024 * hw - Struct containing variables accessed by shared code
5025 *****************************************************************************/
3ad2cc67 5026static int32_t
2d7edb92
MC		 5027e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
5028{
5029 uint32_t attempts = 100000;
5030 uint32_t i, reg = 0;
5031 int32_t done = E1000_ERR_EEPROM;
5032
8fc897b0
AK		 5033 for (i = 0; i < attempts; i++) {
5034 if (eerd == E1000_EEPROM_POLL_READ)
2d7edb92 5035 reg = E1000_READ_REG(hw, EERD);
76c224bc 5036 else
2d7edb92
MC		 5037 reg = E1000_READ_REG(hw, EEWR);
5038
8fc897b0 5039 if (reg & E1000_EEPROM_RW_REG_DONE) {
2d7edb92
MC		 5040 done = E1000_SUCCESS;
5041 break;
5042 }
5043 udelay(5);
5044 }
5045
5046 return done;
5047}
5048
5049/***************************************************************************
5050* Description: Determines if the onboard NVM is FLASH or EEPROM.
5051*
5052* hw - Struct containing variables accessed by shared code
5053****************************************************************************/
3ad2cc67 5054static boolean_t
2d7edb92
MC		 5055e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
5056{
5057 uint32_t eecd = 0;
5058
6418ecc6
JK		 5059 DEBUGFUNC("e1000_is_onboard_nvm_eeprom");
5060
cd94dd0b
AK		 5061 if (hw->mac_type == e1000_ich8lan)
5062 return FALSE;
5063
5064 if (hw->mac_type == e1000_82573) {
2d7edb92
MC		 5065 eecd = E1000_READ_REG(hw, EECD);
5066
5067 /* Isolate bits 15 & 16 */
5068 eecd = ((eecd >> 15) & 0x03);
5069
5070 /* If both bits are set, device is Flash type */
8fc897b0 5071 if (eecd == 0x03) {
2d7edb92
MC		 5072 return FALSE;
5073 }
5074 }
5075 return TRUE;
5076}
5077
5078/******************************************************************************
5079 * Verifies that the EEPROM has a valid checksum
5080 *
5081 * hw - Struct containing variables accessed by shared code
5082 *
5083 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
5084 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
5085 * valid.
5086 *****************************************************************************/
5087int32_t
5088e1000_validate_eeprom_checksum(struct e1000_hw *hw)
5089{
5090 uint16_t checksum = 0;
5091 uint16_t i, eeprom_data;
5092
5093 DEBUGFUNC("e1000_validate_eeprom_checksum");
5094
5095 if ((hw->mac_type == e1000_82573) &&
5096 (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) {
5097 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
5098 * 10h-12h. Checksum may need to be fixed. */
5099 e1000_read_eeprom(hw, 0x10, 1, &eeprom_data);
5100 if ((eeprom_data & 0x10) == 0) {
5101 /* Read 0x23 and check bit 15. This bit is a 1 when the checksum
5102 * has already been fixed. If the checksum is still wrong and this
5103 * bit is a 1, we need to return bad checksum. Otherwise, we need
5104 * to set this bit to a 1 and update the checksum. */
5105 e1000_read_eeprom(hw, 0x23, 1, &eeprom_data);
5106 if ((eeprom_data & 0x8000) == 0) {
5107 eeprom_data |= 0x8000;
5108 e1000_write_eeprom(hw, 0x23, 1, &eeprom_data);
5109 e1000_update_eeprom_checksum(hw);
5110 }
5111 }
5112 }
5113
cd94dd0b
AK		 5114 if (hw->mac_type == e1000_ich8lan) {
5115 /* Drivers must allocate the shadow ram structure for the
5116 * EEPROM checksum to be updated. Otherwise, this bit as well
5117 * as the checksum must both be set correctly for this
5118 * validation to pass.
5119 */
5120 e1000_read_eeprom(hw, 0x19, 1, &eeprom_data);
5121 if ((eeprom_data & 0x40) == 0) {
5122 eeprom_data |= 0x40;
5123 e1000_write_eeprom(hw, 0x19, 1, &eeprom_data);
5124 e1000_update_eeprom_checksum(hw);
5125 }
5126 }
5127
5128 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
5129 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
2d7edb92
MC		 5130 DEBUGOUT("EEPROM Read Error\n");
5131 return -E1000_ERR_EEPROM;
5132 }
5133 checksum += eeprom_data;
5134 }
5135
8fc897b0 5136 if (checksum == (uint16_t) EEPROM_SUM)
2d7edb92
MC		 5137 return E1000_SUCCESS;
5138 else {
5139 DEBUGOUT("EEPROM Checksum Invalid\n");
5140 return -E1000_ERR_EEPROM;
5141 }
5142}
5143
5144/******************************************************************************
5145 * Calculates the EEPROM checksum and writes it to the EEPROM
5146 *
5147 * hw - Struct containing variables accessed by shared code
5148 *
5149 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
5150 * Writes the difference to word offset 63 of the EEPROM.
5151 *****************************************************************************/
5152int32_t
5153e1000_update_eeprom_checksum(struct e1000_hw *hw)
5154{
cd94dd0b 5155 uint32_t ctrl_ext;
2d7edb92
MC		 5156 uint16_t checksum = 0;
5157 uint16_t i, eeprom_data;
5158
5159 DEBUGFUNC("e1000_update_eeprom_checksum");
5160
8fc897b0
AK		 5161 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
5162 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
2d7edb92
MC		 5163 DEBUGOUT("EEPROM Read Error\n");
5164 return -E1000_ERR_EEPROM;
5165 }
5166 checksum += eeprom_data;
5167 }
5168 checksum = (uint16_t) EEPROM_SUM - checksum;
8fc897b0 5169 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
1da177e4
LT		 5170 DEBUGOUT("EEPROM Write Error\n");
5171 return -E1000_ERR_EEPROM;
2d7edb92
MC		 5172 } else if (hw->eeprom.type == e1000_eeprom_flash) {
5173 e1000_commit_shadow_ram(hw);
cd94dd0b
AK		 5174 } else if (hw->eeprom.type == e1000_eeprom_ich8) {
5175 e1000_commit_shadow_ram(hw);
5176 /* Reload the EEPROM, or else modifications will not appear
5177 * until after next adapter reset. */
5178 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5179 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
5180 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
f8ec4733 5181 msleep(10);
1da177e4
LT		 5182 }
5183 return E1000_SUCCESS;
5184}
5185
5186/******************************************************************************
5187 * Parent function for writing words to the different EEPROM types.
5188 *
5189 * hw - Struct containing variables accessed by shared code
5190 * offset - offset within the EEPROM to be written to
5191 * words - number of words to write
5192 * data - 16 bit word to be written to the EEPROM
5193 *
5194 * If e1000_update_eeprom_checksum is not called after this function, the
5195 * EEPROM will most likely contain an invalid checksum.
5196 *****************************************************************************/
5197int32_t
5198e1000_write_eeprom(struct e1000_hw *hw,
5199 uint16_t offset,
5200 uint16_t words,
5201 uint16_t *data)
5202{
5203 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5204 int32_t status = 0;
5205
5206 DEBUGFUNC("e1000_write_eeprom");
5207
5208 /* A check for invalid values: offset too large, too many words, and not
5209 * enough words.
5210 */
8fc897b0 5211 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
1da177e4
LT		 5212 (words == 0)) {
5213 DEBUGOUT("\"words\" parameter out of bounds\n");
5214 return -E1000_ERR_EEPROM;
5215 }
5216
868d5309 5217 /* 82573 writes only through eewr */
8fc897b0 5218 if (eeprom->use_eewr == TRUE)
2d7edb92
MC		 5219 return e1000_write_eeprom_eewr(hw, offset, words, data);
5220
cd94dd0b
AK		 5221 if (eeprom->type == e1000_eeprom_ich8)
5222 return e1000_write_eeprom_ich8(hw, offset, words, data);
5223
1da177e4
LT		 5224 /* Prepare the EEPROM for writing */
5225 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
5226 return -E1000_ERR_EEPROM;
5227
8fc897b0 5228 if (eeprom->type == e1000_eeprom_microwire) {
1da177e4
LT		 5229 status = e1000_write_eeprom_microwire(hw, offset, words, data);
5230 } else {
5231 status = e1000_write_eeprom_spi(hw, offset, words, data);
f8ec4733 5232 msleep(10);
1da177e4
LT		 5233 }
5234
5235 /* Done with writing */
5236 e1000_release_eeprom(hw);
5237
5238 return status;
5239}
5240
5241/******************************************************************************
5242 * Writes a 16 bit word to a given offset in an SPI EEPROM.
5243 *
5244 * hw - Struct containing variables accessed by shared code
5245 * offset - offset within the EEPROM to be written to
5246 * words - number of words to write
5247 * data - pointer to array of 8 bit words to be written to the EEPROM
5248 *
5249 *****************************************************************************/
5250int32_t
5251e1000_write_eeprom_spi(struct e1000_hw *hw,
5252 uint16_t offset,
5253 uint16_t words,
5254 uint16_t *data)
5255{
5256 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5257 uint16_t widx = 0;
5258
5259 DEBUGFUNC("e1000_write_eeprom_spi");
5260
5261 while (widx < words) {
5262 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
5263
8fc897b0 5264 if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
1da177e4
LT		 5265
5266 e1000_standby_eeprom(hw);
5267
5268 /* Send the WRITE ENABLE command (8 bit opcode ) */
5269 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
5270 eeprom->opcode_bits);
5271
5272 e1000_standby_eeprom(hw);
5273
5274 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
8fc897b0 5275 if ((eeprom->address_bits == 8) && (offset >= 128))
1da177e4
LT		 5276 write_opcode |= EEPROM_A8_OPCODE_SPI;
5277
5278 /* Send the Write command (8-bit opcode + addr) */
5279 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
5280
5281 e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2),
5282 eeprom->address_bits);
5283
5284 /* Send the data */
5285
5286 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
5287 while (widx < words) {
5288 uint16_t word_out = data[widx];
5289 word_out = (word_out >> 8) | (word_out << 8);
5290 e1000_shift_out_ee_bits(hw, word_out, 16);
5291 widx++;
5292
5293 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
5294 * operation, while the smaller eeproms are capable of an 8-byte
5295 * PAGE WRITE operation. Break the inner loop to pass new address
5296 */
8fc897b0 5297 if ((((offset + widx)*2) % eeprom->page_size) == 0) {
1da177e4
LT		 5298 e1000_standby_eeprom(hw);
5299 break;
5300 }
5301 }
5302 }
5303
5304 return E1000_SUCCESS;
5305}
5306
5307/******************************************************************************
5308 * Writes a 16 bit word to a given offset in a Microwire EEPROM.
5309 *
5310 * hw - Struct containing variables accessed by shared code
5311 * offset - offset within the EEPROM to be written to
5312 * words - number of words to write
5313 * data - pointer to array of 16 bit words to be written to the EEPROM
5314 *
5315 *****************************************************************************/
5316int32_t
5317e1000_write_eeprom_microwire(struct e1000_hw *hw,
5318 uint16_t offset,
5319 uint16_t words,
5320 uint16_t *data)
5321{
5322 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5323 uint32_t eecd;
5324 uint16_t words_written = 0;
5325 uint16_t i = 0;
5326
5327 DEBUGFUNC("e1000_write_eeprom_microwire");
5328
5329 /* Send the write enable command to the EEPROM (3-bit opcode plus
5330 * 6/8-bit dummy address beginning with 11). It's less work to include
5331 * the 11 of the dummy address as part of the opcode than it is to shift
5332 * it over the correct number of bits for the address. This puts the
5333 * EEPROM into write/erase mode.
5334 */
5335 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
5336 (uint16_t)(eeprom->opcode_bits + 2));
5337
5338 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
5339
5340 /* Prepare the EEPROM */
5341 e1000_standby_eeprom(hw);
5342
5343 while (words_written < words) {
5344 /* Send the Write command (3-bit opcode + addr) */
5345 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
5346 eeprom->opcode_bits);
5347
5348 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written),
5349 eeprom->address_bits);
5350
5351 /* Send the data */
5352 e1000_shift_out_ee_bits(hw, data[words_written], 16);
5353
5354 /* Toggle the CS line. This in effect tells the EEPROM to execute
5355 * the previous command.
5356 */
5357 e1000_standby_eeprom(hw);
5358
5359 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
5360 * signal that the command has been completed by raising the DO signal.
5361 * If DO does not go high in 10 milliseconds, then error out.
5362 */
8fc897b0 5363 for (i = 0; i < 200; i++) {
1da177e4 5364 eecd = E1000_READ_REG(hw, EECD);
8fc897b0 5365 if (eecd & E1000_EECD_DO) break;
1da177e4
LT		 5366 udelay(50);
5367 }
8fc897b0 5368 if (i == 200) {
1da177e4
LT		 5369 DEBUGOUT("EEPROM Write did not complete\n");
5370 return -E1000_ERR_EEPROM;
5371 }
5372
5373 /* Recover from write */
5374 e1000_standby_eeprom(hw);
5375
5376 words_written++;
5377 }
5378
5379 /* Send the write disable command to the EEPROM (3-bit opcode plus
5380 * 6/8-bit dummy address beginning with 10). It's less work to include
5381 * the 10 of the dummy address as part of the opcode than it is to shift
5382 * it over the correct number of bits for the address. This takes the
5383 * EEPROM out of write/erase mode.
5384 */
5385 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
5386 (uint16_t)(eeprom->opcode_bits + 2));
5387
5388 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
5389
5390 return E1000_SUCCESS;
5391}
5392
2d7edb92
MC		 5393/******************************************************************************
5394 * Flushes the cached eeprom to NVM. This is done by saving the modified values
5395 * in the eeprom cache and the non modified values in the currently active bank
5396 * to the new bank.
5397 *
5398 * hw - Struct containing variables accessed by shared code
5399 * offset - offset of word in the EEPROM to read
5400 * data - word read from the EEPROM
5401 * words - number of words to read
5402 *****************************************************************************/
3ad2cc67 5403static int32_t
2d7edb92
MC		 5404e1000_commit_shadow_ram(struct e1000_hw *hw)
5405{
5406 uint32_t attempts = 100000;
5407 uint32_t eecd = 0;
5408 uint32_t flop = 0;
5409 uint32_t i = 0;
5410 int32_t error = E1000_SUCCESS;
cd94dd0b
AK		 5411 uint32_t old_bank_offset = 0;
5412 uint32_t new_bank_offset = 0;
5413 uint32_t sector_retries = 0;
5414 uint8_t low_byte = 0;
5415 uint8_t high_byte = 0;
5416 uint8_t temp_byte = 0;
5417 boolean_t sector_write_failed = FALSE;
2d7edb92
MC		 5418
5419 if (hw->mac_type == e1000_82573) {
cd94dd0b
AK		 5420 /* The flop register will be used to determine if flash type is STM */
5421 flop = E1000_READ_REG(hw, FLOP);
2d7edb92
MC		 5422 for (i=0; i < attempts; i++) {
5423 eecd = E1000_READ_REG(hw, EECD);
5424 if ((eecd & E1000_EECD_FLUPD) == 0) {
5425 break;
5426 }
5427 udelay(5);
5428 }
5429
5430 if (i == attempts) {
5431 return -E1000_ERR_EEPROM;
5432 }
5433
96838a40 5434 /* If STM opcode located in bits 15:8 of flop, reset firmware */
2d7edb92
MC		 5435 if ((flop & 0xFF00) == E1000_STM_OPCODE) {
5436 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET);
5437 }
5438
5439 /* Perform the flash update */
5440 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD);
5441
96838a40 5442 for (i=0; i < attempts; i++) {
2d7edb92
MC		 5443 eecd = E1000_READ_REG(hw, EECD);
5444 if ((eecd & E1000_EECD_FLUPD) == 0) {
5445 break;
5446 }
5447 udelay(5);
5448 }
5449
5450 if (i == attempts) {
5451 return -E1000_ERR_EEPROM;
5452 }
5453 }
5454
cd94dd0b
AK		 5455 if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) {
5456 /* We're writing to the opposite bank so if we're on bank 1,
5457 * write to bank 0 etc. We also need to erase the segment that
5458 * is going to be written */
5459 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) {
5460 new_bank_offset = hw->flash_bank_size * 2;
5461 old_bank_offset = 0;
5462 e1000_erase_ich8_4k_segment(hw, 1);
5463 } else {
5464 old_bank_offset = hw->flash_bank_size * 2;
5465 new_bank_offset = 0;
5466 e1000_erase_ich8_4k_segment(hw, 0);
5467 }
5468
5469 do {
5470 sector_write_failed = FALSE;
5471 /* Loop for every byte in the shadow RAM,
5472 * which is in units of words. */
5473 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5474 /* Determine whether to write the value stored
5475 * in the other NVM bank or a modified value stored
5476 * in the shadow RAM */
5477 if (hw->eeprom_shadow_ram[i].modified == TRUE) {
5478 low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word;
5479 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5480 &temp_byte);
5481 udelay(100);
5482 error = e1000_verify_write_ich8_byte(hw,
5483 (i << 1) + new_bank_offset,
5484 low_byte);
5485 if (error != E1000_SUCCESS)
5486 sector_write_failed = TRUE;
5487 high_byte =
5488 (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
5489 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5490 &temp_byte);
5491 udelay(100);
5492 } else {
5493 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5494 &low_byte);
5495 udelay(100);
5496 error = e1000_verify_write_ich8_byte(hw,
5497 (i << 1) + new_bank_offset, low_byte);
5498 if (error != E1000_SUCCESS)
5499 sector_write_failed = TRUE;
5500 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5501 &high_byte);
5502 }
5503
5504 /* If the word is 0x13, then make sure the signature bits
5505 * (15:14) are 11b until the commit has completed.
5506 * This will allow us to write 10b which indicates the
5507 * signature is valid. We want to do this after the write
5508 * has completed so that we don't mark the segment valid
5509 * while the write is still in progress */
5510 if (i == E1000_ICH8_NVM_SIG_WORD)
5511 high_byte = E1000_ICH8_NVM_SIG_MASK | high_byte;
5512
5513 error = e1000_verify_write_ich8_byte(hw,
5514 (i << 1) + new_bank_offset + 1, high_byte);
5515 if (error != E1000_SUCCESS)
5516 sector_write_failed = TRUE;
5517
5518 if (sector_write_failed == FALSE) {
5519 /* Clear the now not used entry in the cache */
5520 hw->eeprom_shadow_ram[i].modified = FALSE;
5521 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
5522 }
5523 }
5524
5525 /* Don't bother writing the segment valid bits if sector
5526 * programming failed. */
5527 if (sector_write_failed == FALSE) {
5528 /* Finally validate the new segment by setting bit 15:14
5529 * to 10b in word 0x13 , this can be done without an
5530 * erase as well since these bits are 11 to start with
5531 * and we need to change bit 14 to 0b */
5532 e1000_read_ich8_byte(hw,
5533 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5534 &high_byte);
5535 high_byte &= 0xBF;
5536 error = e1000_verify_write_ich8_byte(hw,
5537 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5538 high_byte);
5539 if (error != E1000_SUCCESS)
5540 sector_write_failed = TRUE;
5541
5542 /* And invalidate the previously valid segment by setting
5543 * its signature word (0x13) high_byte to 0b. This can be
5544 * done without an erase because flash erase sets all bits
5545 * to 1's. We can write 1's to 0's without an erase */
5546 error = e1000_verify_write_ich8_byte(hw,
5547 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + old_bank_offset,
5548 0);
5549 if (error != E1000_SUCCESS)
5550 sector_write_failed = TRUE;
5551 }
5552 } while (++sector_retries < 10 && sector_write_failed == TRUE);
5553 }
5554
2d7edb92
MC		 5555 return error;
5556}
5557
1da177e4
LT		 5558/******************************************************************************
5559 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
5560 * second function of dual function devices
5561 *
5562 * hw - Struct containing variables accessed by shared code
5563 *****************************************************************************/
5564int32_t
5565e1000_read_mac_addr(struct e1000_hw * hw)
5566{
5567 uint16_t offset;
5568 uint16_t eeprom_data, i;
5569
5570 DEBUGFUNC("e1000_read_mac_addr");
5571
8fc897b0 5572 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1da177e4 5573 offset = i >> 1;
8fc897b0 5574 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
1da177e4
LT		 5575 DEBUGOUT("EEPROM Read Error\n");
5576 return -E1000_ERR_EEPROM;
5577 }
5578 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
5579 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
5580 }
96838a40 5581
868d5309
MC		 5582 switch (hw->mac_type) {
5583 default:
5584 break;
5585 case e1000_82546:
5586 case e1000_82546_rev_3:
5587 case e1000_82571:
6418ecc6 5588 case e1000_80003es2lan:
8fc897b0 5589 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
1da177e4 5590 hw->perm_mac_addr[5] ^= 0x01;
868d5309
MC		 5591 break;
5592 }
1da177e4 5593
8fc897b0 5594 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
1da177e4
LT		 5595 hw->mac_addr[i] = hw->perm_mac_addr[i];
5596 return E1000_SUCCESS;
5597}
5598
5599/******************************************************************************
5600 * Initializes receive address filters.
5601 *
5602 * hw - Struct containing variables accessed by shared code
5603 *
5604 * Places the MAC address in receive address register 0 and clears the rest
5605 * of the receive addresss registers. Clears the multicast table. Assumes
5606 * the receiver is in reset when the routine is called.
5607 *****************************************************************************/
3ad2cc67 5608static void
1da177e4
LT		 5609e1000_init_rx_addrs(struct e1000_hw *hw)
5610{
5611 uint32_t i;
2d7edb92 5612 uint32_t rar_num;
1da177e4
LT		 5613
5614 DEBUGFUNC("e1000_init_rx_addrs");
5615
5616 /* Setup the receive address. */
5617 DEBUGOUT("Programming MAC Address into RAR[0]\n");
5618
5619 e1000_rar_set(hw, hw->mac_addr, 0);
5620
2d7edb92 5621 rar_num = E1000_RAR_ENTRIES;
868d5309
MC		 5622
5623 /* Reserve a spot for the Locally Administered Address to work around
5624 * an 82571 issue in which a reset on one port will reload the MAC on
5625 * the other port. */
5626 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
5627 rar_num -= 1;
cd94dd0b
AK		 5628 if (hw->mac_type == e1000_ich8lan)
5629 rar_num = E1000_RAR_ENTRIES_ICH8LAN;
5630
1da177e4
LT		 5631 /* Zero out the other 15 receive addresses. */
5632 DEBUGOUT("Clearing RAR[1-15]\n");
8fc897b0 5633 for (i = 1; i < rar_num; i++) {
1da177e4 5634 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
4ca213a6 5635 E1000_WRITE_FLUSH(hw);
1da177e4 5636 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
4ca213a6 5637 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 5638 }
5639}
5640
5641/******************************************************************************
5642 * Updates the MAC's list of multicast addresses.
5643 *
5644 * hw - Struct containing variables accessed by shared code
5645 * mc_addr_list - the list of new multicast addresses
5646 * mc_addr_count - number of addresses
5647 * pad - number of bytes between addresses in the list
5648 * rar_used_count - offset where to start adding mc addresses into the RAR's
5649 *
5650 * The given list replaces any existing list. Clears the last 15 receive
5651 * address registers and the multicast table. Uses receive address registers
5652 * for the first 15 multicast addresses, and hashes the rest into the
5653 * multicast table.
5654 *****************************************************************************/
e4c780b1 5655#if 0
1da177e4
LT		 5656void
5657e1000_mc_addr_list_update(struct e1000_hw *hw,
5658 uint8_t *mc_addr_list,
5659 uint32_t mc_addr_count,
5660 uint32_t pad,
5661 uint32_t rar_used_count)
5662{
5663 uint32_t hash_value;
5664 uint32_t i;
2d7edb92
MC		 5665 uint32_t num_rar_entry;
5666 uint32_t num_mta_entry;
76c224bc 5667
1da177e4
LT		 5668 DEBUGFUNC("e1000_mc_addr_list_update");
5669
5670 /* Set the new number of MC addresses that we are being requested to use. */
5671 hw->num_mc_addrs = mc_addr_count;
5672
5673 /* Clear RAR[1-15] */
5674 DEBUGOUT(" Clearing RAR[1-15]\n");
2d7edb92 5675 num_rar_entry = E1000_RAR_ENTRIES;
cd94dd0b
AK		 5676 if (hw->mac_type == e1000_ich8lan)
5677 num_rar_entry = E1000_RAR_ENTRIES_ICH8LAN;
868d5309
MC		 5678 /* Reserve a spot for the Locally Administered Address to work around
5679 * an 82571 issue in which a reset on one port will reload the MAC on
5680 * the other port. */
5681 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
5682 num_rar_entry -= 1;
5683
8fc897b0 5684 for (i = rar_used_count; i < num_rar_entry; i++) {
1da177e4 5685 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
4ca213a6 5686 E1000_WRITE_FLUSH(hw);
1da177e4 5687 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
4ca213a6 5688 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 5689 }
5690
5691 /* Clear the MTA */
5692 DEBUGOUT(" Clearing MTA\n");
2d7edb92 5693 num_mta_entry = E1000_NUM_MTA_REGISTERS;
cd94dd0b
AK		 5694 if (hw->mac_type == e1000_ich8lan)
5695 num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN;
8fc897b0 5696 for (i = 0; i < num_mta_entry; i++) {
1da177e4 5697 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
4ca213a6 5698 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 5699 }
5700
5701 /* Add the new addresses */
8fc897b0 5702 for (i = 0; i < mc_addr_count; i++) {
1da177e4
LT		 5703 DEBUGOUT(" Adding the multicast addresses:\n");
5704 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
5705 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)],
5706 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1],
5707 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2],
5708 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3],
5709 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4],
5710 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]);
5711
5712 hash_value = e1000_hash_mc_addr(hw,
5713 mc_addr_list +
5714 (i * (ETH_LENGTH_OF_ADDRESS + pad)));
5715
5716 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
5717
5718 /* Place this multicast address in the RAR if there is room, *
5719 * else put it in the MTA
5720 */
2d7edb92 5721 if (rar_used_count < num_rar_entry) {
1da177e4
LT		 5722 e1000_rar_set(hw,
5723 mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)),
5724 rar_used_count);
5725 rar_used_count++;
5726 } else {
5727 e1000_mta_set(hw, hash_value);
5728 }
5729 }
5730 DEBUGOUT("MC Update Complete\n");
5731}
e4c780b1 5732#endif /* 0 */
1da177e4
LT		 5733
5734/******************************************************************************
5735 * Hashes an address to determine its location in the multicast table
5736 *
5737 * hw - Struct containing variables accessed by shared code
5738 * mc_addr - the multicast address to hash
5739 *****************************************************************************/
5740uint32_t
5741e1000_hash_mc_addr(struct e1000_hw *hw,
5742 uint8_t *mc_addr)
5743{
5744 uint32_t hash_value = 0;
5745
5746 /* The portion of the address that is used for the hash table is
5747 * determined by the mc_filter_type setting.
5748 */
5749 switch (hw->mc_filter_type) {
5750 /* [0] [1] [2] [3] [4] [5]
5751 * 01 AA 00 12 34 56
5752 * LSB MSB
5753 */
5754 case 0:
cd94dd0b
AK		 5755 if (hw->mac_type == e1000_ich8lan) {
5756 /* [47:38] i.e. 0x158 for above example address */
5757 hash_value = ((mc_addr[4] >> 6) | (((uint16_t) mc_addr[5]) << 2));
5758 } else {
5759 /* [47:36] i.e. 0x563 for above example address */
5760 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5761 }
1da177e4
LT		 5762 break;
5763 case 1:
cd94dd0b
AK		 5764 if (hw->mac_type == e1000_ich8lan) {
5765 /* [46:37] i.e. 0x2B1 for above example address */
5766 hash_value = ((mc_addr[4] >> 5) | (((uint16_t) mc_addr[5]) << 3));
5767 } else {
5768 /* [46:35] i.e. 0xAC6 for above example address */
5769 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
5770 }
1da177e4
LT		 5771 break;
5772 case 2:
cd94dd0b
AK		 5773 if (hw->mac_type == e1000_ich8lan) {
5774 /*[45:36] i.e. 0x163 for above example address */
5775 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5776 } else {
5777 /* [45:34] i.e. 0x5D8 for above example address */
5778 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5779 }
1da177e4
LT		 5780 break;
5781 case 3:
cd94dd0b
AK		 5782 if (hw->mac_type == e1000_ich8lan) {
5783 /* [43:34] i.e. 0x18D for above example address */
5784 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5785 } else {
5786 /* [43:32] i.e. 0x634 for above example address */
5787 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
5788 }
1da177e4
LT		 5789 break;
5790 }
5791
5792 hash_value &= 0xFFF;
cd94dd0b
AK		 5793 if (hw->mac_type == e1000_ich8lan)
5794 hash_value &= 0x3FF;
2d7edb92 5795
1da177e4
LT		 5796 return hash_value;
5797}
5798
5799/******************************************************************************
5800 * Sets the bit in the multicast table corresponding to the hash value.
5801 *
5802 * hw - Struct containing variables accessed by shared code
5803 * hash_value - Multicast address hash value
5804 *****************************************************************************/
5805void
5806e1000_mta_set(struct e1000_hw *hw,
5807 uint32_t hash_value)
5808{
5809 uint32_t hash_bit, hash_reg;
5810 uint32_t mta;
5811 uint32_t temp;
5812
5813 /* The MTA is a register array of 128 32-bit registers.
5814 * It is treated like an array of 4096 bits. We want to set
5815 * bit BitArray[hash_value]. So we figure out what register
5816 * the bit is in, read it, OR in the new bit, then write
5817 * back the new value. The register is determined by the
5818 * upper 7 bits of the hash value and the bit within that
5819 * register are determined by the lower 5 bits of the value.
5820 */
5821 hash_reg = (hash_value >> 5) & 0x7F;
cd94dd0b
AK		 5822 if (hw->mac_type == e1000_ich8lan)
5823 hash_reg &= 0x1F;
1da177e4
LT		 5824 hash_bit = hash_value & 0x1F;
5825
5826 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
5827
5828 mta |= (1 << hash_bit);
5829
5830 /* If we are on an 82544 and we are trying to write an odd offset
5831 * in the MTA, save off the previous entry before writing and
5832 * restore the old value after writing.
5833 */
8fc897b0 5834 if ((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
1da177e4
LT		 5835 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
5836 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
4ca213a6 5837 E1000_WRITE_FLUSH(hw);
1da177e4 5838 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
4ca213a6 5839 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 5840 } else {
5841 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
4ca213a6 5842 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 5843 }
5844}
5845
5846/******************************************************************************
5847 * Puts an ethernet address into a receive address register.
5848 *
5849 * hw - Struct containing variables accessed by shared code
5850 * addr - Address to put into receive address register
5851 * index - Receive address register to write
5852 *****************************************************************************/
5853void
5854e1000_rar_set(struct e1000_hw *hw,
5855 uint8_t *addr,
5856 uint32_t index)
5857{
5858 uint32_t rar_low, rar_high;
5859
5860 /* HW expects these in little endian so we reverse the byte order
5861 * from network order (big endian) to little endian
5862 */
5863 rar_low = ((uint32_t) addr[0] |
5864 ((uint32_t) addr[1] << 8) |
5865 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
8df06e50 5866 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8));
1da177e4 5867
8df06e50
JK		 5868 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
5869 * unit hang.
5870 *
5871 * Description:
5872 * If there are any Rx frames queued up or otherwise present in the HW
5873 * before RSS is enabled, and then we enable RSS, the HW Rx unit will
5874 * hang. To work around this issue, we have to disable receives and
5875 * flush out all Rx frames before we enable RSS. To do so, we modify we
5876 * redirect all Rx traffic to manageability and then reset the HW.
5877 * This flushes away Rx frames, and (since the redirections to
5878 * manageability persists across resets) keeps new ones from coming in
5879 * while we work. Then, we clear the Address Valid AV bit for all MAC
5880 * addresses and undo the re-direction to manageability.
5881 * Now, frames are coming in again, but the MAC won't accept them, so
5882 * far so good. We now proceed to initialize RSS (if necessary) and
5883 * configure the Rx unit. Last, we re-enable the AV bits and continue
5884 * on our merry way.
5885 */
5886 switch (hw->mac_type) {
5887 case e1000_82571:
5888 case e1000_82572:
6418ecc6 5889 case e1000_80003es2lan:
8df06e50
JK		 5890 if (hw->leave_av_bit_off == TRUE)
5891 break;
5892 default:
5893 /* Indicate to hardware the Address is Valid. */
5894 rar_high |= E1000_RAH_AV;
5895 break;
5896 }
1da177e4
LT		 5897
5898 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
4ca213a6 5899 E1000_WRITE_FLUSH(hw);
1da177e4 5900 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
4ca213a6 5901 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 5902}
5903
5904/******************************************************************************
5905 * Writes a value to the specified offset in the VLAN filter table.
5906 *
5907 * hw - Struct containing variables accessed by shared code
5908 * offset - Offset in VLAN filer table to write
5909 * value - Value to write into VLAN filter table
5910 *****************************************************************************/
5911void
5912e1000_write_vfta(struct e1000_hw *hw,
5913 uint32_t offset,
5914 uint32_t value)
5915{
5916 uint32_t temp;
5917
cd94dd0b
AK		 5918 if (hw->mac_type == e1000_ich8lan)
5919 return;
5920
5921 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
1da177e4
LT		 5922 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
5923 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4ca213a6 5924 E1000_WRITE_FLUSH(hw);
1da177e4 5925 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
4ca213a6 5926 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 5927 } else {
5928 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4ca213a6 5929 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 5930 }
5931}
5932
5933/******************************************************************************
5934 * Clears the VLAN filer table
5935 *
5936 * hw - Struct containing variables accessed by shared code
5937 *****************************************************************************/
3ad2cc67 5938static void
1da177e4
LT		 5939e1000_clear_vfta(struct e1000_hw *hw)
5940{
5941 uint32_t offset;
2d7edb92
MC		 5942 uint32_t vfta_value = 0;
5943 uint32_t vfta_offset = 0;
5944 uint32_t vfta_bit_in_reg = 0;
5945
cd94dd0b
AK		 5946 if (hw->mac_type == e1000_ich8lan)
5947 return;
5948
2d7edb92
MC		 5949 if (hw->mac_type == e1000_82573) {
5950 if (hw->mng_cookie.vlan_id != 0) {
5951 /* The VFTA is a 4096b bit-field, each identifying a single VLAN
5952 * ID. The following operations determine which 32b entry
5953 * (i.e. offset) into the array we want to set the VLAN ID
5954 * (i.e. bit) of the manageability unit. */
5955 vfta_offset = (hw->mng_cookie.vlan_id >>
5956 E1000_VFTA_ENTRY_SHIFT) &
5957 E1000_VFTA_ENTRY_MASK;
5958 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
5959 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
5960 }
5961 }
5962 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
5963 /* If the offset we want to clear is the same offset of the
5964 * manageability VLAN ID, then clear all bits except that of the
5965 * manageability unit */
5966 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
5967 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
4ca213a6 5968 E1000_WRITE_FLUSH(hw);
2d7edb92 5969 }
1da177e4
LT		 5970}
5971
3ad2cc67 5972static int32_t
1da177e4
LT		 5973e1000_id_led_init(struct e1000_hw * hw)
5974{
5975 uint32_t ledctl;
5976 const uint32_t ledctl_mask = 0x000000FF;
5977 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
5978 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
5979 uint16_t eeprom_data, i, temp;
5980 const uint16_t led_mask = 0x0F;
5981
5982 DEBUGFUNC("e1000_id_led_init");
5983
8fc897b0 5984 if (hw->mac_type < e1000_82540) {
1da177e4
LT		 5985 /* Nothing to do */
5986 return E1000_SUCCESS;
5987 }
5988
5989 ledctl = E1000_READ_REG(hw, LEDCTL);
5990 hw->ledctl_default = ledctl;
5991 hw->ledctl_mode1 = hw->ledctl_default;
5992 hw->ledctl_mode2 = hw->ledctl_default;
5993
8fc897b0 5994 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
1da177e4
LT		 5995 DEBUGOUT("EEPROM Read Error\n");
5996 return -E1000_ERR_EEPROM;
5997 }
cd94dd0b
AK		 5998
5999 if ((hw->mac_type == e1000_82573) &&
6000 (eeprom_data == ID_LED_RESERVED_82573))
6001 eeprom_data = ID_LED_DEFAULT_82573;
6002 else if ((eeprom_data == ID_LED_RESERVED_0000) ||
6003 (eeprom_data == ID_LED_RESERVED_FFFF)) {
6004 if (hw->mac_type == e1000_ich8lan)
6005 eeprom_data = ID_LED_DEFAULT_ICH8LAN;
6006 else
6007 eeprom_data = ID_LED_DEFAULT;
6008 }
6009 for (i = 0; i < 4; i++) {
1da177e4 6010 temp = (eeprom_data >> (i << 2)) & led_mask;
8fc897b0 6011 switch (temp) {
1da177e4
LT		 6012 case ID_LED_ON1_DEF2:
6013 case ID_LED_ON1_ON2:
6014 case ID_LED_ON1_OFF2:
6015 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
6016 hw->ledctl_mode1 |= ledctl_on << (i << 3);
6017 break;
6018 case ID_LED_OFF1_DEF2:
6019 case ID_LED_OFF1_ON2:
6020 case ID_LED_OFF1_OFF2:
6021 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
6022 hw->ledctl_mode1 |= ledctl_off << (i << 3);
6023 break;
6024 default:
6025 /* Do nothing */
6026 break;
6027 }
8fc897b0 6028 switch (temp) {
1da177e4
LT		 6029 case ID_LED_DEF1_ON2:
6030 case ID_LED_ON1_ON2:
6031 case ID_LED_OFF1_ON2:
6032 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
6033 hw->ledctl_mode2 |= ledctl_on << (i << 3);
6034 break;
6035 case ID_LED_DEF1_OFF2:
6036 case ID_LED_ON1_OFF2:
6037 case ID_LED_OFF1_OFF2:
6038 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
6039 hw->ledctl_mode2 |= ledctl_off << (i << 3);
6040 break;
6041 default:
6042 /* Do nothing */
6043 break;
6044 }
6045 }
6046 return E1000_SUCCESS;
6047}
6048
6049/******************************************************************************
6050 * Prepares SW controlable LED for use and saves the current state of the LED.
6051 *
6052 * hw - Struct containing variables accessed by shared code
6053 *****************************************************************************/
6054int32_t
6055e1000_setup_led(struct e1000_hw *hw)
6056{
6057 uint32_t ledctl;
6058 int32_t ret_val = E1000_SUCCESS;
6059
6060 DEBUGFUNC("e1000_setup_led");
6061
8fc897b0 6062 switch (hw->mac_type) {
1da177e4
LT		 6063 case e1000_82542_rev2_0:
6064 case e1000_82542_rev2_1:
6065 case e1000_82543:
6066 case e1000_82544:
6067 /* No setup necessary */
6068 break;
6069 case e1000_82541:
6070 case e1000_82547:
6071 case e1000_82541_rev_2:
6072 case e1000_82547_rev_2:
6073 /* Turn off PHY Smart Power Down (if enabled) */
6074 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
6075 &hw->phy_spd_default);
8fc897b0 6076 if (ret_val)
1da177e4
LT		 6077 return ret_val;
6078 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6079 (uint16_t)(hw->phy_spd_default &
6080 ~IGP01E1000_GMII_SPD));
8fc897b0 6081 if (ret_val)
1da177e4
LT		 6082 return ret_val;
6083 /* Fall Through */
6084 default:
8fc897b0 6085 if (hw->media_type == e1000_media_type_fiber) {
1da177e4
LT		 6086 ledctl = E1000_READ_REG(hw, LEDCTL);
6087 /* Save current LEDCTL settings */
6088 hw->ledctl_default = ledctl;
6089 /* Turn off LED0 */
6090 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
6091 E1000_LEDCTL_LED0_BLINK |
6092 E1000_LEDCTL_LED0_MODE_MASK);
6093 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
6094 E1000_LEDCTL_LED0_MODE_SHIFT);
6095 E1000_WRITE_REG(hw, LEDCTL, ledctl);
8fc897b0 6096 } else if (hw->media_type == e1000_media_type_copper)
1da177e4
LT		 6097 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6098 break;
6099 }
6100
6101 return E1000_SUCCESS;
6102}
6103
8fc897b0 6104
f1b3a853
AK		 6105/******************************************************************************
6106 * Used on 82571 and later Si that has LED blink bits.
6107 * Callers must use their own timer and should have already called
6108 * e1000_id_led_init()
6109 * Call e1000_cleanup led() to stop blinking
6110 *
6111 * hw - Struct containing variables accessed by shared code
6112 *****************************************************************************/
6113int32_t
6114e1000_blink_led_start(struct e1000_hw *hw)
6115{
6116 int16_t i;
6117 uint32_t ledctl_blink = 0;
6118
6119 DEBUGFUNC("e1000_id_led_blink_on");
6120
6121 if (hw->mac_type < e1000_82571) {
6122 /* Nothing to do */
6123 return E1000_SUCCESS;
6124 }
6125 if (hw->media_type == e1000_media_type_fiber) {
6126 /* always blink LED0 for PCI-E fiber */
6127 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
6128 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
6129 } else {
6130 /* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */
6131 ledctl_blink = hw->ledctl_mode2;
6132 for (i=0; i < 4; i++)
6133 if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) ==
6134 E1000_LEDCTL_MODE_LED_ON)
6135 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8));
6136 }
6137
6138 E1000_WRITE_REG(hw, LEDCTL, ledctl_blink);
6139
6140 return E1000_SUCCESS;
6141}
6142
1da177e4
LT		 6143/******************************************************************************
6144 * Restores the saved state of the SW controlable LED.
6145 *
6146 * hw - Struct containing variables accessed by shared code
6147 *****************************************************************************/
6148int32_t
6149e1000_cleanup_led(struct e1000_hw *hw)
6150{
6151 int32_t ret_val = E1000_SUCCESS;
6152
6153 DEBUGFUNC("e1000_cleanup_led");
6154
8fc897b0 6155 switch (hw->mac_type) {
1da177e4
LT		 6156 case e1000_82542_rev2_0:
6157 case e1000_82542_rev2_1:
6158 case e1000_82543:
6159 case e1000_82544:
6160 /* No cleanup necessary */
6161 break;
6162 case e1000_82541:
6163 case e1000_82547:
6164 case e1000_82541_rev_2:
6165 case e1000_82547_rev_2:
6166 /* Turn on PHY Smart Power Down (if previously enabled) */
6167 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6168 hw->phy_spd_default);
8fc897b0 6169 if (ret_val)
1da177e4
LT		 6170 return ret_val;
6171 /* Fall Through */
6172 default:
cd94dd0b
AK		 6173 if (hw->phy_type == e1000_phy_ife) {
6174 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
6175 break;
6176 }
1da177e4
LT		 6177 /* Restore LEDCTL settings */
6178 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
6179 break;
6180 }
6181
6182 return E1000_SUCCESS;
6183}
6184
6185/******************************************************************************
6186 * Turns on the software controllable LED
6187 *
6188 * hw - Struct containing variables accessed by shared code
6189 *****************************************************************************/
6190int32_t
6191e1000_led_on(struct e1000_hw *hw)
6192{
6193 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
6194
6195 DEBUGFUNC("e1000_led_on");
6196
8fc897b0 6197 switch (hw->mac_type) {
1da177e4
LT		 6198 case e1000_82542_rev2_0:
6199 case e1000_82542_rev2_1:
6200 case e1000_82543:
6201 /* Set SW Defineable Pin 0 to turn on the LED */
6202 ctrl |= E1000_CTRL_SWDPIN0;
6203 ctrl |= E1000_CTRL_SWDPIO0;
6204 break;
6205 case e1000_82544:
8fc897b0 6206 if (hw->media_type == e1000_media_type_fiber) {
1da177e4
LT		 6207 /* Set SW Defineable Pin 0 to turn on the LED */
6208 ctrl |= E1000_CTRL_SWDPIN0;
6209 ctrl |= E1000_CTRL_SWDPIO0;
6210 } else {
6211 /* Clear SW Defineable Pin 0 to turn on the LED */
6212 ctrl &= ~E1000_CTRL_SWDPIN0;
6213 ctrl |= E1000_CTRL_SWDPIO0;
6214 }
6215 break;
6216 default:
8fc897b0 6217 if (hw->media_type == e1000_media_type_fiber) {
1da177e4
LT		 6218 /* Clear SW Defineable Pin 0 to turn on the LED */
6219 ctrl &= ~E1000_CTRL_SWDPIN0;
6220 ctrl |= E1000_CTRL_SWDPIO0;
cd94dd0b
AK		 6221 } else if (hw->phy_type == e1000_phy_ife) {
6222 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6223 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
6224 } else if (hw->media_type == e1000_media_type_copper) {
1da177e4
LT		 6225 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
6226 return E1000_SUCCESS;
6227 }
6228 break;
6229 }
6230
6231 E1000_WRITE_REG(hw, CTRL, ctrl);
6232
6233 return E1000_SUCCESS;
6234}
6235
6236/******************************************************************************
6237 * Turns off the software controllable LED
6238 *
6239 * hw - Struct containing variables accessed by shared code
6240 *****************************************************************************/
6241int32_t
6242e1000_led_off(struct e1000_hw *hw)
6243{
6244 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
6245
6246 DEBUGFUNC("e1000_led_off");
6247
8fc897b0 6248 switch (hw->mac_type) {
1da177e4
LT		 6249 case e1000_82542_rev2_0:
6250 case e1000_82542_rev2_1:
6251 case e1000_82543:
6252 /* Clear SW Defineable Pin 0 to turn off the LED */
6253 ctrl &= ~E1000_CTRL_SWDPIN0;
6254 ctrl |= E1000_CTRL_SWDPIO0;
6255 break;
6256 case e1000_82544:
8fc897b0 6257 if (hw->media_type == e1000_media_type_fiber) {
1da177e4
LT		 6258 /* Clear SW Defineable Pin 0 to turn off the LED */
6259 ctrl &= ~E1000_CTRL_SWDPIN0;
6260 ctrl |= E1000_CTRL_SWDPIO0;
6261 } else {
6262 /* Set SW Defineable Pin 0 to turn off the LED */
6263 ctrl |= E1000_CTRL_SWDPIN0;
6264 ctrl |= E1000_CTRL_SWDPIO0;
6265 }
6266 break;
6267 default:
8fc897b0 6268 if (hw->media_type == e1000_media_type_fiber) {
1da177e4
LT		 6269 /* Set SW Defineable Pin 0 to turn off the LED */
6270 ctrl |= E1000_CTRL_SWDPIN0;
6271 ctrl |= E1000_CTRL_SWDPIO0;
cd94dd0b
AK		 6272 } else if (hw->phy_type == e1000_phy_ife) {
6273 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6274 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
6275 } else if (hw->media_type == e1000_media_type_copper) {
1da177e4
LT		 6276 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6277 return E1000_SUCCESS;
6278 }
6279 break;
6280 }
6281
6282 E1000_WRITE_REG(hw, CTRL, ctrl);
6283
6284 return E1000_SUCCESS;
6285}
6286
6287/******************************************************************************
6288 * Clears all hardware statistics counters.
6289 *
6290 * hw - Struct containing variables accessed by shared code
6291 *****************************************************************************/
8fc897b0 6292void
1da177e4
LT		 6293e1000_clear_hw_cntrs(struct e1000_hw *hw)
6294{
6295 volatile uint32_t temp;
6296
6297 temp = E1000_READ_REG(hw, CRCERRS);
6298 temp = E1000_READ_REG(hw, SYMERRS);
6299 temp = E1000_READ_REG(hw, MPC);
6300 temp = E1000_READ_REG(hw, SCC);
6301 temp = E1000_READ_REG(hw, ECOL);
6302 temp = E1000_READ_REG(hw, MCC);
6303 temp = E1000_READ_REG(hw, LATECOL);
6304 temp = E1000_READ_REG(hw, COLC);
6305 temp = E1000_READ_REG(hw, DC);
6306 temp = E1000_READ_REG(hw, SEC);
6307 temp = E1000_READ_REG(hw, RLEC);
6308 temp = E1000_READ_REG(hw, XONRXC);
6309 temp = E1000_READ_REG(hw, XONTXC);
6310 temp = E1000_READ_REG(hw, XOFFRXC);
6311 temp = E1000_READ_REG(hw, XOFFTXC);
6312 temp = E1000_READ_REG(hw, FCRUC);
cd94dd0b
AK		 6313
6314 if (hw->mac_type != e1000_ich8lan) {
1da177e4
LT		 6315 temp = E1000_READ_REG(hw, PRC64);
6316 temp = E1000_READ_REG(hw, PRC127);
6317 temp = E1000_READ_REG(hw, PRC255);
6318 temp = E1000_READ_REG(hw, PRC511);
6319 temp = E1000_READ_REG(hw, PRC1023);
6320 temp = E1000_READ_REG(hw, PRC1522);
cd94dd0b
AK		 6321 }
6322
1da177e4
LT		 6323 temp = E1000_READ_REG(hw, GPRC);
6324 temp = E1000_READ_REG(hw, BPRC);
6325 temp = E1000_READ_REG(hw, MPRC);
6326 temp = E1000_READ_REG(hw, GPTC);
6327 temp = E1000_READ_REG(hw, GORCL);
6328 temp = E1000_READ_REG(hw, GORCH);
6329 temp = E1000_READ_REG(hw, GOTCL);
6330 temp = E1000_READ_REG(hw, GOTCH);
6331 temp = E1000_READ_REG(hw, RNBC);
6332 temp = E1000_READ_REG(hw, RUC);
6333 temp = E1000_READ_REG(hw, RFC);
6334 temp = E1000_READ_REG(hw, ROC);
6335 temp = E1000_READ_REG(hw, RJC);
6336 temp = E1000_READ_REG(hw, TORL);
6337 temp = E1000_READ_REG(hw, TORH);
6338 temp = E1000_READ_REG(hw, TOTL);
6339 temp = E1000_READ_REG(hw, TOTH);
6340 temp = E1000_READ_REG(hw, TPR);
6341 temp = E1000_READ_REG(hw, TPT);
cd94dd0b
AK		 6342
6343 if (hw->mac_type != e1000_ich8lan) {
1da177e4
LT		 6344 temp = E1000_READ_REG(hw, PTC64);
6345 temp = E1000_READ_REG(hw, PTC127);
6346 temp = E1000_READ_REG(hw, PTC255);
6347 temp = E1000_READ_REG(hw, PTC511);
6348 temp = E1000_READ_REG(hw, PTC1023);
6349 temp = E1000_READ_REG(hw, PTC1522);
cd94dd0b
AK		 6350 }
6351
1da177e4
LT		 6352 temp = E1000_READ_REG(hw, MPTC);
6353 temp = E1000_READ_REG(hw, BPTC);
6354
8fc897b0 6355 if (hw->mac_type < e1000_82543) return;
1da177e4
LT		 6356
6357 temp = E1000_READ_REG(hw, ALGNERRC);
6358 temp = E1000_READ_REG(hw, RXERRC);
6359 temp = E1000_READ_REG(hw, TNCRS);
6360 temp = E1000_READ_REG(hw, CEXTERR);
6361 temp = E1000_READ_REG(hw, TSCTC);
6362 temp = E1000_READ_REG(hw, TSCTFC);
6363
8fc897b0 6364 if (hw->mac_type <= e1000_82544) return;
1da177e4
LT		 6365
6366 temp = E1000_READ_REG(hw, MGTPRC);
6367 temp = E1000_READ_REG(hw, MGTPDC);
6368 temp = E1000_READ_REG(hw, MGTPTC);
2d7edb92 6369
8fc897b0 6370 if (hw->mac_type <= e1000_82547_rev_2) return;
2d7edb92
MC		 6371
6372 temp = E1000_READ_REG(hw, IAC);
6373 temp = E1000_READ_REG(hw, ICRXOC);
cd94dd0b
AK		 6374
6375 if (hw->mac_type == e1000_ich8lan) return;
6376
2d7edb92
MC		 6377 temp = E1000_READ_REG(hw, ICRXPTC);
6378 temp = E1000_READ_REG(hw, ICRXATC);
6379 temp = E1000_READ_REG(hw, ICTXPTC);
6380 temp = E1000_READ_REG(hw, ICTXATC);
6381 temp = E1000_READ_REG(hw, ICTXQEC);
6382 temp = E1000_READ_REG(hw, ICTXQMTC);
6383 temp = E1000_READ_REG(hw, ICRXDMTC);
1da177e4
LT		 6384}
6385
6386/******************************************************************************
6387 * Resets Adaptive IFS to its default state.
6388 *
6389 * hw - Struct containing variables accessed by shared code
6390 *
6391 * Call this after e1000_init_hw. You may override the IFS defaults by setting
6392 * hw->ifs_params_forced to TRUE. However, you must initialize hw->
6393 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
6394 * before calling this function.
6395 *****************************************************************************/
6396void
6397e1000_reset_adaptive(struct e1000_hw *hw)
6398{
6399 DEBUGFUNC("e1000_reset_adaptive");
6400
8fc897b0
AK		 6401 if (hw->adaptive_ifs) {
6402 if (!hw->ifs_params_forced) {
1da177e4
LT		 6403 hw->current_ifs_val = 0;
6404 hw->ifs_min_val = IFS_MIN;
6405 hw->ifs_max_val = IFS_MAX;
6406 hw->ifs_step_size = IFS_STEP;
6407 hw->ifs_ratio = IFS_RATIO;
6408 }
6409 hw->in_ifs_mode = FALSE;
6410 E1000_WRITE_REG(hw, AIT, 0);
6411 } else {
6412 DEBUGOUT("Not in Adaptive IFS mode!\n");
6413 }
6414}
6415
6416/******************************************************************************
6417 * Called during the callback/watchdog routine to update IFS value based on
6418 * the ratio of transmits to collisions.
6419 *
6420 * hw - Struct containing variables accessed by shared code
6421 * tx_packets - Number of transmits since last callback
6422 * total_collisions - Number of collisions since last callback
6423 *****************************************************************************/
6424void
6425e1000_update_adaptive(struct e1000_hw *hw)
6426{
6427 DEBUGFUNC("e1000_update_adaptive");
6428
8fc897b0
AK		 6429 if (hw->adaptive_ifs) {
6430 if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
6431 if (hw->tx_packet_delta > MIN_NUM_XMITS) {
1da177e4 6432 hw->in_ifs_mode = TRUE;
8fc897b0
AK		 6433 if (hw->current_ifs_val < hw->ifs_max_val) {
6434 if (hw->current_ifs_val == 0)
1da177e4
LT		 6435 hw->current_ifs_val = hw->ifs_min_val;
6436 else
6437 hw->current_ifs_val += hw->ifs_step_size;
6438 E1000_WRITE_REG(hw, AIT, hw->current_ifs_val);
6439 }
6440 }
6441 } else {
8fc897b0 6442 if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
1da177e4
LT		 6443 hw->current_ifs_val = 0;
6444 hw->in_ifs_mode = FALSE;
6445 E1000_WRITE_REG(hw, AIT, 0);
6446 }
6447 }
6448 } else {
6449 DEBUGOUT("Not in Adaptive IFS mode!\n");
6450 }
6451}
6452
6453/******************************************************************************
6454 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
6455 *
6456 * hw - Struct containing variables accessed by shared code
6457 * frame_len - The length of the frame in question
6458 * mac_addr - The Ethernet destination address of the frame in question
6459 *****************************************************************************/
6460void
6461e1000_tbi_adjust_stats(struct e1000_hw *hw,
6462 struct e1000_hw_stats *stats,
6463 uint32_t frame_len,
6464 uint8_t *mac_addr)
6465{
6466 uint64_t carry_bit;
6467
6468 /* First adjust the frame length. */
6469 frame_len--;
6470 /* We need to adjust the statistics counters, since the hardware
6471 * counters overcount this packet as a CRC error and undercount
6472 * the packet as a good packet
6473 */
6474 /* This packet should not be counted as a CRC error. */
6475 stats->crcerrs--;
6476 /* This packet does count as a Good Packet Received. */
6477 stats->gprc++;
6478
6479 /* Adjust the Good Octets received counters */
6480 carry_bit = 0x80000000 & stats->gorcl;
6481 stats->gorcl += frame_len;
6482 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
6483 * Received Count) was one before the addition,
6484 * AND it is zero after, then we lost the carry out,
6485 * need to add one to Gorch (Good Octets Received Count High).
6486 * This could be simplified if all environments supported
6487 * 64-bit integers.
6488 */
8fc897b0 6489 if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
1da177e4
LT		 6490 stats->gorch++;
6491 /* Is this a broadcast or multicast? Check broadcast first,
6492 * since the test for a multicast frame will test positive on
6493 * a broadcast frame.
6494 */
8fc897b0 6495 if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
1da177e4
LT		 6496 /* Broadcast packet */
6497 stats->bprc++;
8fc897b0 6498 else if (*mac_addr & 0x01)
1da177e4
LT		 6499 /* Multicast packet */
6500 stats->mprc++;
6501
8fc897b0 6502 if (frame_len == hw->max_frame_size) {
1da177e4
LT		 6503 /* In this case, the hardware has overcounted the number of
6504 * oversize frames.
6505 */
8fc897b0 6506 if (stats->roc > 0)
1da177e4
LT		 6507 stats->roc--;
6508 }
6509
6510 /* Adjust the bin counters when the extra byte put the frame in the
6511 * wrong bin. Remember that the frame_len was adjusted above.
6512 */
8fc897b0 6513 if (frame_len == 64) {
1da177e4
LT		 6514 stats->prc64++;
6515 stats->prc127--;
8fc897b0 6516 } else if (frame_len == 127) {
1da177e4
LT		 6517 stats->prc127++;
6518 stats->prc255--;
8fc897b0 6519 } else if (frame_len == 255) {
1da177e4
LT		 6520 stats->prc255++;
6521 stats->prc511--;
8fc897b0 6522 } else if (frame_len == 511) {
1da177e4
LT		 6523 stats->prc511++;
6524 stats->prc1023--;
8fc897b0 6525 } else if (frame_len == 1023) {
1da177e4
LT		 6526 stats->prc1023++;
6527 stats->prc1522--;
8fc897b0 6528 } else if (frame_len == 1522) {
1da177e4
LT		 6529 stats->prc1522++;
6530 }
6531}
6532
6533/******************************************************************************
6534 * Gets the current PCI bus type, speed, and width of the hardware
6535 *
6536 * hw - Struct containing variables accessed by shared code
6537 *****************************************************************************/
6538void
6539e1000_get_bus_info(struct e1000_hw *hw)
6540{
6541 uint32_t status;
6542
6543 switch (hw->mac_type) {
6544 case e1000_82542_rev2_0:
6545 case e1000_82542_rev2_1:
6546 hw->bus_type = e1000_bus_type_unknown;
6547 hw->bus_speed = e1000_bus_speed_unknown;
6548 hw->bus_width = e1000_bus_width_unknown;
6549 break;
868d5309 6550 case e1000_82572:
2d7edb92 6551 case e1000_82573:
fd803241
JK		 6552 hw->bus_type = e1000_bus_type_pci_express;
6553 hw->bus_speed = e1000_bus_speed_2500;
6554 hw->bus_width = e1000_bus_width_pciex_1;
6555 break;
6556 case e1000_82571:
cd94dd0b 6557 case e1000_ich8lan:
6418ecc6 6558 case e1000_80003es2lan:
2d7edb92
MC		 6559 hw->bus_type = e1000_bus_type_pci_express;
6560 hw->bus_speed = e1000_bus_speed_2500;
6561 hw->bus_width = e1000_bus_width_pciex_4;
6562 break;
1da177e4
LT		 6563 default:
6564 status = E1000_READ_REG(hw, STATUS);
6565 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
6566 e1000_bus_type_pcix : e1000_bus_type_pci;
6567
8fc897b0 6568 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
1da177e4
LT		 6569 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
6570 e1000_bus_speed_66 : e1000_bus_speed_120;
8fc897b0 6571 } else if (hw->bus_type == e1000_bus_type_pci) {
1da177e4
LT		 6572 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
6573 e1000_bus_speed_66 : e1000_bus_speed_33;
6574 } else {
6575 switch (status & E1000_STATUS_PCIX_SPEED) {
6576 case E1000_STATUS_PCIX_SPEED_66:
6577 hw->bus_speed = e1000_bus_speed_66;
6578 break;
6579 case E1000_STATUS_PCIX_SPEED_100:
6580 hw->bus_speed = e1000_bus_speed_100;
6581 break;
6582 case E1000_STATUS_PCIX_SPEED_133:
6583 hw->bus_speed = e1000_bus_speed_133;
6584 break;
6585 default:
6586 hw->bus_speed = e1000_bus_speed_reserved;
6587 break;
6588 }
6589 }
6590 hw->bus_width = (status & E1000_STATUS_BUS64) ?
6591 e1000_bus_width_64 : e1000_bus_width_32;
6592 break;
6593 }
6594}
6595/******************************************************************************
6596 * Reads a value from one of the devices registers using port I/O (as opposed
6597 * memory mapped I/O). Only 82544 and newer devices support port I/O.
6598 *
6599 * hw - Struct containing variables accessed by shared code
6600 * offset - offset to read from
6601 *****************************************************************************/
e4c780b1 6602#if 0
1da177e4
LT		 6603uint32_t
6604e1000_read_reg_io(struct e1000_hw *hw,
6605 uint32_t offset)
6606{
6607 unsigned long io_addr = hw->io_base;
6608 unsigned long io_data = hw->io_base + 4;
6609
6610 e1000_io_write(hw, io_addr, offset);
6611 return e1000_io_read(hw, io_data);
6612}
e4c780b1 6613#endif /* 0 */
1da177e4
LT		 6614
6615/******************************************************************************
6616 * Writes a value to one of the devices registers using port I/O (as opposed to
6617 * memory mapped I/O). Only 82544 and newer devices support port I/O.
6618 *
6619 * hw - Struct containing variables accessed by shared code
6620 * offset - offset to write to
6621 * value - value to write
6622 *****************************************************************************/
3ad2cc67 6623static void
1da177e4
LT		 6624e1000_write_reg_io(struct e1000_hw *hw,
6625 uint32_t offset,
6626 uint32_t value)
6627{
6628 unsigned long io_addr = hw->io_base;
6629 unsigned long io_data = hw->io_base + 4;
6630
6631 e1000_io_write(hw, io_addr, offset);
6632 e1000_io_write(hw, io_data, value);
6633}
6634
6635
6636/******************************************************************************
6637 * Estimates the cable length.
6638 *
6639 * hw - Struct containing variables accessed by shared code
6640 * min_length - The estimated minimum length
6641 * max_length - The estimated maximum length
6642 *
6643 * returns: - E1000_ERR_XXX
6644 * E1000_SUCCESS
6645 *
6646 * This function always returns a ranged length (minimum & maximum).
6647 * So for M88 phy's, this function interprets the one value returned from the
6648 * register to the minimum and maximum range.
6649 * For IGP phy's, the function calculates the range by the AGC registers.
6650 *****************************************************************************/
3ad2cc67 6651static int32_t
1da177e4
LT		 6652e1000_get_cable_length(struct e1000_hw *hw,
6653 uint16_t *min_length,
6654 uint16_t *max_length)
6655{
6656 int32_t ret_val;
6657 uint16_t agc_value = 0;
1da177e4
LT		 6658 uint16_t i, phy_data;
6659 uint16_t cable_length;
6660
6661 DEBUGFUNC("e1000_get_cable_length");
6662
6663 *min_length = *max_length = 0;
6664
6665 /* Use old method for Phy older than IGP */
8fc897b0 6666 if (hw->phy_type == e1000_phy_m88) {
2d7edb92 6667
1da177e4
LT		 6668 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6669 &phy_data);
8fc897b0 6670 if (ret_val)
1da177e4
LT		 6671 return ret_val;
6672 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
6673 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
6674
6675 /* Convert the enum value to ranged values */
6676 switch (cable_length) {
6677 case e1000_cable_length_50:
6678 *min_length = 0;
6679 *max_length = e1000_igp_cable_length_50;
6680 break;
6681 case e1000_cable_length_50_80:
6682 *min_length = e1000_igp_cable_length_50;
6683 *max_length = e1000_igp_cable_length_80;
6684 break;
6685 case e1000_cable_length_80_110:
6686 *min_length = e1000_igp_cable_length_80;
6687 *max_length = e1000_igp_cable_length_110;
6688 break;
6689 case e1000_cable_length_110_140:
6690 *min_length = e1000_igp_cable_length_110;
6691 *max_length = e1000_igp_cable_length_140;
6692 break;
6693 case e1000_cable_length_140:
6694 *min_length = e1000_igp_cable_length_140;
6695 *max_length = e1000_igp_cable_length_170;
6696 break;
6697 default:
6698 return -E1000_ERR_PHY;
6699 break;
6700 }
6418ecc6
JK		 6701 } else if (hw->phy_type == e1000_phy_gg82563) {
6702 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
6703 &phy_data);
6704 if (ret_val)
6705 return ret_val;
6706 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH;
6707
6708 switch (cable_length) {
6709 case e1000_gg_cable_length_60:
6710 *min_length = 0;
6711 *max_length = e1000_igp_cable_length_60;
6712 break;
6713 case e1000_gg_cable_length_60_115:
6714 *min_length = e1000_igp_cable_length_60;
6715 *max_length = e1000_igp_cable_length_115;
6716 break;
6717 case e1000_gg_cable_length_115_150:
6718 *min_length = e1000_igp_cable_length_115;
6719 *max_length = e1000_igp_cable_length_150;
6720 break;
6721 case e1000_gg_cable_length_150:
6722 *min_length = e1000_igp_cable_length_150;
6723 *max_length = e1000_igp_cable_length_180;
6724 break;
6725 default:
6726 return -E1000_ERR_PHY;
6727 break;
6728 }
8fc897b0 6729 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
cd94dd0b
AK		 6730 uint16_t cur_agc_value;
6731 uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
1da177e4
LT		 6732 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6733 {IGP01E1000_PHY_AGC_A,
6734 IGP01E1000_PHY_AGC_B,
6735 IGP01E1000_PHY_AGC_C,
6736 IGP01E1000_PHY_AGC_D};
6737 /* Read the AGC registers for all channels */
8fc897b0 6738 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
1da177e4
LT		 6739
6740 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
8fc897b0 6741 if (ret_val)
1da177e4
LT		 6742 return ret_val;
6743
cd94dd0b 6744 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
1da177e4 6745
cd94dd0b
AK		 6746 /* Value bound check. */
6747 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
6748 (cur_agc_value == 0))
1da177e4
LT		 6749 return -E1000_ERR_PHY;
6750
cd94dd0b 6751 agc_value += cur_agc_value;
1da177e4
LT		 6752
6753 /* Update minimal AGC value. */
cd94dd0b
AK		 6754 if (min_agc_value > cur_agc_value)
6755 min_agc_value = cur_agc_value;
1da177e4
LT		 6756 }
6757
6758 /* Remove the minimal AGC result for length < 50m */
cd94dd0b
AK		 6759 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
6760 agc_value -= min_agc_value;
1da177e4
LT		 6761
6762 /* Get the average length of the remaining 3 channels */
6763 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
6764 } else {
6765 /* Get the average length of all the 4 channels. */
6766 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
6767 }
6768
6769 /* Set the range of the calculated length. */
6770 *min_length = ((e1000_igp_cable_length_table[agc_value] -
6771 IGP01E1000_AGC_RANGE) > 0) ?
6772 (e1000_igp_cable_length_table[agc_value] -
6773 IGP01E1000_AGC_RANGE) : 0;
6774 *max_length = e1000_igp_cable_length_table[agc_value] +
6775 IGP01E1000_AGC_RANGE;
cd94dd0b
AK		 6776 } else if (hw->phy_type == e1000_phy_igp_2 ||
6777 hw->phy_type == e1000_phy_igp_3) {
6778 uint16_t cur_agc_index, max_agc_index = 0;
6779 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1;
868d5309
MC		 6780 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
6781 {IGP02E1000_PHY_AGC_A,
6782 IGP02E1000_PHY_AGC_B,
6783 IGP02E1000_PHY_AGC_C,
6784 IGP02E1000_PHY_AGC_D};
6785 /* Read the AGC registers for all channels */
6786 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
6787 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6788 if (ret_val)
6789 return ret_val;
6790
8fc897b0 6791 /* Getting bits 15:9, which represent the combination of course and
868d5309
MC		 6792 * fine gain values. The result is a number that can be put into
6793 * the lookup table to obtain the approximate cable length. */
cd94dd0b
AK		 6794 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
6795 IGP02E1000_AGC_LENGTH_MASK;
868d5309 6796
cd94dd0b
AK		 6797 /* Array index bound check. */
6798 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) ||
6799 (cur_agc_index == 0))
6800 return -E1000_ERR_PHY;
868d5309 6801
cd94dd0b
AK		 6802 /* Remove min & max AGC values from calculation. */
6803 if (e1000_igp_2_cable_length_table[min_agc_index] >
6804 e1000_igp_2_cable_length_table[cur_agc_index])
6805 min_agc_index = cur_agc_index;
6806 if (e1000_igp_2_cable_length_table[max_agc_index] <
6807 e1000_igp_2_cable_length_table[cur_agc_index])
6808 max_agc_index = cur_agc_index;
6809
6810 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
868d5309
MC		 6811 }
6812
cd94dd0b
AK		 6813 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
6814 e1000_igp_2_cable_length_table[max_agc_index]);
868d5309
MC		 6815 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
6816
6817 /* Calculate cable length with the error range of +/- 10 meters. */
6818 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
6819 (agc_value - IGP02E1000_AGC_RANGE) : 0;
6820 *max_length = agc_value + IGP02E1000_AGC_RANGE;
1da177e4
LT		 6821 }
6822
6823 return E1000_SUCCESS;
6824}
6825
6826/******************************************************************************
6827 * Check the cable polarity
6828 *
6829 * hw - Struct containing variables accessed by shared code
6830 * polarity - output parameter : 0 - Polarity is not reversed
6831 * 1 - Polarity is reversed.
6832 *
6833 * returns: - E1000_ERR_XXX
6834 * E1000_SUCCESS
6835 *
6836 * For phy's older then IGP, this function simply reads the polarity bit in the
6837 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
6838 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
6839 * return 0. If the link speed is 1000 Mbps the polarity status is in the
6840 * IGP01E1000_PHY_PCS_INIT_REG.
6841 *****************************************************************************/
3ad2cc67 6842static int32_t
1da177e4
LT		 6843e1000_check_polarity(struct e1000_hw *hw,
6844 uint16_t *polarity)
6845{
6846 int32_t ret_val;
6847 uint16_t phy_data;
6848
6849 DEBUGFUNC("e1000_check_polarity");
6850
6418ecc6
JK		 6851 if ((hw->phy_type == e1000_phy_m88) ||
6852 (hw->phy_type == e1000_phy_gg82563)) {
1da177e4
LT		 6853 /* return the Polarity bit in the Status register. */
6854 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6855 &phy_data);
8fc897b0 6856 if (ret_val)
1da177e4
LT		 6857 return ret_val;
6858 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
6859 M88E1000_PSSR_REV_POLARITY_SHIFT;
cd94dd0b
AK		 6860 } else if (hw->phy_type == e1000_phy_igp ||
6861 hw->phy_type == e1000_phy_igp_3 ||
2d7edb92 6862 hw->phy_type == e1000_phy_igp_2) {
1da177e4
LT		 6863 /* Read the Status register to check the speed */
6864 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
6865 &phy_data);
8fc897b0 6866 if (ret_val)
1da177e4
LT		 6867 return ret_val;
6868
6869 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
6870 * find the polarity status */
8fc897b0 6871 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1da177e4
LT		 6872 IGP01E1000_PSSR_SPEED_1000MBPS) {
6873
6874 /* Read the GIG initialization PCS register (0x00B4) */
6875 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
6876 &phy_data);
8fc897b0 6877 if (ret_val)
1da177e4
LT		 6878 return ret_val;
6879
6880 /* Check the polarity bits */
6881 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 1 : 0;
6882 } else {
6883 /* For 10 Mbps, read the polarity bit in the status register. (for
6884 * 100 Mbps this bit is always 0) */
6885 *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED;
6886 }
cd94dd0b
AK		 6887 } else if (hw->phy_type == e1000_phy_ife) {
6888 ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL,
6889 &phy_data);
6890 if (ret_val)
6891 return ret_val;
6892 *polarity = (phy_data & IFE_PESC_POLARITY_REVERSED) >>
6893 IFE_PESC_POLARITY_REVERSED_SHIFT;
1da177e4
LT		 6894 }
6895 return E1000_SUCCESS;
6896}
6897
6898/******************************************************************************
6899 * Check if Downshift occured
6900 *
6901 * hw - Struct containing variables accessed by shared code
6902 * downshift - output parameter : 0 - No Downshift ocured.
6903 * 1 - Downshift ocured.
6904 *
6905 * returns: - E1000_ERR_XXX
76c224bc 6906 * E1000_SUCCESS
1da177e4
LT		 6907 *
6908 * For phy's older then IGP, this function reads the Downshift bit in the Phy
6909 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
6910 * Link Health register. In IGP this bit is latched high, so the driver must
6911 * read it immediately after link is established.
6912 *****************************************************************************/
3ad2cc67 6913static int32_t
1da177e4
LT		 6914e1000_check_downshift(struct e1000_hw *hw)
6915{
6916 int32_t ret_val;
6917 uint16_t phy_data;
6918
6919 DEBUGFUNC("e1000_check_downshift");
6920
cd94dd0b
AK		 6921 if (hw->phy_type == e1000_phy_igp ||
6922 hw->phy_type == e1000_phy_igp_3 ||
2d7edb92 6923 hw->phy_type == e1000_phy_igp_2) {
1da177e4
LT		 6924 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
6925 &phy_data);
8fc897b0 6926 if (ret_val)
1da177e4
LT		 6927 return ret_val;
6928
6929 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
6418ecc6
JK		 6930 } else if ((hw->phy_type == e1000_phy_m88) ||
6931 (hw->phy_type == e1000_phy_gg82563)) {
1da177e4
LT		 6932 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6933 &phy_data);
8fc897b0 6934 if (ret_val)
1da177e4
LT		 6935 return ret_val;
6936
6937 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
6938 M88E1000_PSSR_DOWNSHIFT_SHIFT;
cd94dd0b
AK		 6939 } else if (hw->phy_type == e1000_phy_ife) {
6940 /* e1000_phy_ife supports 10/100 speed only */
6941 hw->speed_downgraded = FALSE;
1da177e4 6942 }
2d7edb92 6943
1da177e4
LT		 6944 return E1000_SUCCESS;
6945}
6946
6947/*****************************************************************************
6948 *
6949 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
6950 * gigabit link is achieved to improve link quality.
6951 *
6952 * hw: Struct containing variables accessed by shared code
6953 *
6954 * returns: - E1000_ERR_PHY if fail to read/write the PHY
6955 * E1000_SUCCESS at any other case.
6956 *
6957 ****************************************************************************/
6958
3ad2cc67 6959static int32_t
1da177e4
LT		 6960e1000_config_dsp_after_link_change(struct e1000_hw *hw,
6961 boolean_t link_up)
6962{
6963 int32_t ret_val;
6964 uint16_t phy_data, phy_saved_data, speed, duplex, i;
6965 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6966 {IGP01E1000_PHY_AGC_PARAM_A,
6967 IGP01E1000_PHY_AGC_PARAM_B,
6968 IGP01E1000_PHY_AGC_PARAM_C,
6969 IGP01E1000_PHY_AGC_PARAM_D};
6970 uint16_t min_length, max_length;
6971
6972 DEBUGFUNC("e1000_config_dsp_after_link_change");
6973
8fc897b0 6974 if (hw->phy_type != e1000_phy_igp)
1da177e4
LT		 6975 return E1000_SUCCESS;
6976
8fc897b0 6977 if (link_up) {
1da177e4 6978 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
8fc897b0 6979 if (ret_val) {
1da177e4
LT		 6980 DEBUGOUT("Error getting link speed and duplex\n");
6981 return ret_val;
6982 }
6983
8fc897b0 6984 if (speed == SPEED_1000) {
1da177e4 6985
cd94dd0b
AK		 6986 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
6987 if (ret_val)
6988 return ret_val;
1da177e4 6989
8fc897b0 6990 if ((hw->dsp_config_state == e1000_dsp_config_enabled) &&
1da177e4
LT		 6991 min_length >= e1000_igp_cable_length_50) {
6992
8fc897b0 6993 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
1da177e4
LT		 6994 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
6995 &phy_data);
8fc897b0 6996 if (ret_val)
1da177e4
LT		 6997 return ret_val;
6998
6999 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
7000
7001 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
7002 phy_data);
8fc897b0 7003 if (ret_val)
1da177e4
LT		 7004 return ret_val;
7005 }
7006 hw->dsp_config_state = e1000_dsp_config_activated;
7007 }
7008
8fc897b0 7009 if ((hw->ffe_config_state == e1000_ffe_config_enabled) &&
1da177e4
LT		 7010 (min_length < e1000_igp_cable_length_50)) {
7011
7012 uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
7013 uint32_t idle_errs = 0;
7014
7015 /* clear previous idle error counts */
7016 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
7017 &phy_data);
8fc897b0 7018 if (ret_val)
1da177e4
LT		 7019 return ret_val;
7020
8fc897b0 7021 for (i = 0; i < ffe_idle_err_timeout; i++) {
1da177e4
LT		 7022 udelay(1000);
7023 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
7024 &phy_data);
8fc897b0 7025 if (ret_val)
1da177e4
LT		 7026 return ret_val;
7027
7028 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
8fc897b0 7029 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
1da177e4
LT		 7030 hw->ffe_config_state = e1000_ffe_config_active;
7031
7032 ret_val = e1000_write_phy_reg(hw,
7033 IGP01E1000_PHY_DSP_FFE,
7034 IGP01E1000_PHY_DSP_FFE_CM_CP);
8fc897b0 7035 if (ret_val)
1da177e4
LT		 7036 return ret_val;
7037 break;
7038 }
7039
8fc897b0 7040 if (idle_errs)
1da177e4
LT		 7041 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
7042 }
7043 }
7044 }
7045 } else {
8fc897b0 7046 if (hw->dsp_config_state == e1000_dsp_config_activated) {
1da177e4
LT		 7047 /* Save off the current value of register 0x2F5B to be restored at
7048 * the end of the routines. */
7049 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7050
8fc897b0 7051 if (ret_val)
1da177e4
LT		 7052 return ret_val;
7053
7054 /* Disable the PHY transmitter */
7055 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7056
8fc897b0 7057 if (ret_val)
1da177e4
LT		 7058 return ret_val;
7059
f8ec4733 7060 mdelay(20);
1da177e4
LT		 7061
7062 ret_val = e1000_write_phy_reg(hw, 0x0000,
7063 IGP01E1000_IEEE_FORCE_GIGA);
8fc897b0 7064 if (ret_val)
1da177e4 7065 return ret_val;
8fc897b0 7066 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
1da177e4 7067 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
8fc897b0 7068 if (ret_val)
1da177e4
LT		 7069 return ret_val;
7070
7071 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
7072 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
7073
7074 ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data);
8fc897b0 7075 if (ret_val)
1da177e4
LT		 7076 return ret_val;
7077 }
7078
7079 ret_val = e1000_write_phy_reg(hw, 0x0000,
7080 IGP01E1000_IEEE_RESTART_AUTONEG);
8fc897b0 7081 if (ret_val)
1da177e4
LT		 7082 return ret_val;
7083
f8ec4733 7084 mdelay(20);
1da177e4
LT		 7085
7086 /* Now enable the transmitter */
7087 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7088
8fc897b0 7089 if (ret_val)
1da177e4
LT		 7090 return ret_val;
7091
7092 hw->dsp_config_state = e1000_dsp_config_enabled;
7093 }
7094
8fc897b0 7095 if (hw->ffe_config_state == e1000_ffe_config_active) {
1da177e4
LT		 7096 /* Save off the current value of register 0x2F5B to be restored at
7097 * the end of the routines. */
7098 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7099
8fc897b0 7100 if (ret_val)
1da177e4
LT		 7101 return ret_val;
7102
7103 /* Disable the PHY transmitter */
7104 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7105
8fc897b0 7106 if (ret_val)
1da177e4
LT		 7107 return ret_val;
7108
f8ec4733 7109 mdelay(20);
1da177e4
LT		 7110
7111 ret_val = e1000_write_phy_reg(hw, 0x0000,
7112 IGP01E1000_IEEE_FORCE_GIGA);
8fc897b0 7113 if (ret_val)
1da177e4
LT		 7114 return ret_val;
7115 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
7116 IGP01E1000_PHY_DSP_FFE_DEFAULT);
8fc897b0 7117 if (ret_val)
1da177e4
LT		 7118 return ret_val;
7119
7120 ret_val = e1000_write_phy_reg(hw, 0x0000,
7121 IGP01E1000_IEEE_RESTART_AUTONEG);
8fc897b0 7122 if (ret_val)
1da177e4
LT		 7123 return ret_val;
7124
f8ec4733 7125 mdelay(20);
1da177e4
LT		 7126
7127 /* Now enable the transmitter */
7128 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7129
8fc897b0 7130 if (ret_val)
1da177e4
LT		 7131 return ret_val;
7132
7133 hw->ffe_config_state = e1000_ffe_config_enabled;
7134 }
7135 }
7136 return E1000_SUCCESS;
7137}
7138
7139/*****************************************************************************
7140 * Set PHY to class A mode
7141 * Assumes the following operations will follow to enable the new class mode.
7142 * 1. Do a PHY soft reset
7143 * 2. Restart auto-negotiation or force link.
7144 *
7145 * hw - Struct containing variables accessed by shared code
7146 ****************************************************************************/
7147static int32_t
7148e1000_set_phy_mode(struct e1000_hw *hw)
7149{
7150 int32_t ret_val;
7151 uint16_t eeprom_data;
7152
7153 DEBUGFUNC("e1000_set_phy_mode");
7154
8fc897b0
AK		 7155 if ((hw->mac_type == e1000_82545_rev_3) &&
7156 (hw->media_type == e1000_media_type_copper)) {
1da177e4 7157 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
8fc897b0 7158 if (ret_val) {
1da177e4
LT		 7159 return ret_val;
7160 }
7161
8fc897b0
AK		 7162 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
7163 (eeprom_data & EEPROM_PHY_CLASS_A)) {
1da177e4 7164 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
8fc897b0 7165 if (ret_val)
1da177e4
LT		 7166 return ret_val;
7167 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
8fc897b0 7168 if (ret_val)
1da177e4
LT		 7169 return ret_val;
7170
7171 hw->phy_reset_disable = FALSE;
7172 }
7173 }
7174
7175 return E1000_SUCCESS;
7176}
7177
7178/*****************************************************************************
7179 *
7180 * This function sets the lplu state according to the active flag. When
7181 * activating lplu this function also disables smart speed and vise versa.
7182 * lplu will not be activated unless the device autonegotiation advertisment
7183 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7184 * hw: Struct containing variables accessed by shared code
7185 * active - true to enable lplu false to disable lplu.
7186 *
7187 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7188 * E1000_SUCCESS at any other case.
7189 *
7190 ****************************************************************************/
7191
3ad2cc67 7192static int32_t
1da177e4
LT		 7193e1000_set_d3_lplu_state(struct e1000_hw *hw,
7194 boolean_t active)
7195{
cd94dd0b 7196 uint32_t phy_ctrl = 0;
1da177e4
LT		 7197 int32_t ret_val;
7198 uint16_t phy_data;
7199 DEBUGFUNC("e1000_set_d3_lplu_state");
7200
cd94dd0b
AK		 7201 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
7202 && hw->phy_type != e1000_phy_igp_3)
1da177e4
LT		 7203 return E1000_SUCCESS;
7204
7205 /* During driver activity LPLU should not be used or it will attain link
7206 * from the lowest speeds starting from 10Mbps. The capability is used for
7207 * Dx transitions and states */
cd94dd0b 7208 if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
2d7edb92 7209 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
cd94dd0b 7210 if (ret_val)
2d7edb92 7211 return ret_val;
cd94dd0b
AK		 7212 } else if (hw->mac_type == e1000_ich8lan) {
7213 /* MAC writes into PHY register based on the state transition
7214 * and start auto-negotiation. SW driver can overwrite the settings
7215 * in CSR PHY power control E1000_PHY_CTRL register. */
7216 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2d7edb92
MC		 7217 } else {
7218 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
8fc897b0 7219 if (ret_val)
1da177e4 7220 return ret_val;
2d7edb92
MC		 7221 }
7222
8fc897b0
AK		 7223 if (!active) {
7224 if (hw->mac_type == e1000_82541_rev_2 ||
7225 hw->mac_type == e1000_82547_rev_2) {
2d7edb92
MC		 7226 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
7227 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
8fc897b0 7228 if (ret_val)
2d7edb92
MC		 7229 return ret_val;
7230 } else {
cd94dd0b
AK		 7231 if (hw->mac_type == e1000_ich8lan) {
7232 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
7233 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7234 } else {
2d7edb92
MC		 7235 phy_data &= ~IGP02E1000_PM_D3_LPLU;
7236 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7237 phy_data);
7238 if (ret_val)
7239 return ret_val;
cd94dd0b 7240 }
2d7edb92 7241 }
1da177e4
LT		 7242
7243 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7244 * Dx states where the power conservation is most important. During
7245 * driver activity we should enable SmartSpeed, so performance is
7246 * maintained. */
7247 if (hw->smart_speed == e1000_smart_speed_on) {
7248 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7249 &phy_data);
8fc897b0 7250 if (ret_val)
1da177e4
LT		 7251 return ret_val;
7252
7253 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7254 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7255 phy_data);
8fc897b0 7256 if (ret_val)
1da177e4
LT		 7257 return ret_val;
7258 } else if (hw->smart_speed == e1000_smart_speed_off) {
7259 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7260 &phy_data);
7261 if (ret_val)
7262 return ret_val;
7263
7264 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7265 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7266 phy_data);
8fc897b0 7267 if (ret_val)
1da177e4
LT		 7268 return ret_val;
7269 }
7270
8fc897b0
AK		 7271 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
7272 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
7273 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
1da177e4 7274
8fc897b0 7275 if (hw->mac_type == e1000_82541_rev_2 ||
cd94dd0b 7276 hw->mac_type == e1000_82547_rev_2) {
2d7edb92
MC		 7277 phy_data |= IGP01E1000_GMII_FLEX_SPD;
7278 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
8fc897b0 7279 if (ret_val)
2d7edb92
MC		 7280 return ret_val;
7281 } else {
cd94dd0b
AK		 7282 if (hw->mac_type == e1000_ich8lan) {
7283 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
7284 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7285 } else {
2d7edb92
MC		 7286 phy_data |= IGP02E1000_PM_D3_LPLU;
7287 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7288 phy_data);
7289 if (ret_val)
7290 return ret_val;
cd94dd0b 7291 }
2d7edb92
MC		 7292 }
7293
7294 /* When LPLU is enabled we should disable SmartSpeed */
7295 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
8fc897b0 7296 if (ret_val)
2d7edb92
MC		 7297 return ret_val;
7298
7299 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7300 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
8fc897b0 7301 if (ret_val)
2d7edb92
MC		 7302 return ret_val;
7303
7304 }
7305 return E1000_SUCCESS;
7306}
7307
7308/*****************************************************************************
7309 *
7310 * This function sets the lplu d0 state according to the active flag. When
7311 * activating lplu this function also disables smart speed and vise versa.
7312 * lplu will not be activated unless the device autonegotiation advertisment
7313 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7314 * hw: Struct containing variables accessed by shared code
7315 * active - true to enable lplu false to disable lplu.
7316 *
7317 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7318 * E1000_SUCCESS at any other case.
7319 *
7320 ****************************************************************************/
7321
3ad2cc67 7322static int32_t
2d7edb92
MC		 7323e1000_set_d0_lplu_state(struct e1000_hw *hw,
7324 boolean_t active)
7325{
cd94dd0b 7326 uint32_t phy_ctrl = 0;
2d7edb92
MC		 7327 int32_t ret_val;
7328 uint16_t phy_data;
7329 DEBUGFUNC("e1000_set_d0_lplu_state");
7330
8fc897b0 7331 if (hw->mac_type <= e1000_82547_rev_2)
2d7edb92
MC		 7332 return E1000_SUCCESS;
7333
cd94dd0b
AK		 7334 if (hw->mac_type == e1000_ich8lan) {
7335 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7336 } else {
2d7edb92 7337 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
8fc897b0 7338 if (ret_val)
1da177e4 7339 return ret_val;
cd94dd0b 7340 }
1da177e4 7341
2d7edb92 7342 if (!active) {
cd94dd0b
AK		 7343 if (hw->mac_type == e1000_ich8lan) {
7344 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
7345 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7346 } else {
2d7edb92
MC		 7347 phy_data &= ~IGP02E1000_PM_D0_LPLU;
7348 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7349 if (ret_val)
7350 return ret_val;
cd94dd0b 7351 }
2d7edb92
MC		 7352
7353 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7354 * Dx states where the power conservation is most important. During
7355 * driver activity we should enable SmartSpeed, so performance is
7356 * maintained. */
7357 if (hw->smart_speed == e1000_smart_speed_on) {
7358 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7359 &phy_data);
8fc897b0 7360 if (ret_val)
2d7edb92
MC		 7361 return ret_val;
7362
7363 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7364 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7365 phy_data);
8fc897b0 7366 if (ret_val)
2d7edb92
MC		 7367 return ret_val;
7368 } else if (hw->smart_speed == e1000_smart_speed_off) {
7369 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7370 &phy_data);
7371 if (ret_val)
7372 return ret_val;
7373
7374 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7375 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7376 phy_data);
8fc897b0 7377 if (ret_val)
2d7edb92
MC		 7378 return ret_val;
7379 }
7380
7381
7382 } else {
76c224bc 7383
cd94dd0b
AK		 7384 if (hw->mac_type == e1000_ich8lan) {
7385 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
7386 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7387 } else {
76c224bc 7388 phy_data |= IGP02E1000_PM_D0_LPLU;
2d7edb92
MC		 7389 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7390 if (ret_val)
7391 return ret_val;
cd94dd0b 7392 }
2d7edb92 7393
1da177e4
LT		 7394 /* When LPLU is enabled we should disable SmartSpeed */
7395 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
8fc897b0 7396 if (ret_val)
1da177e4
LT		 7397 return ret_val;
7398
7399 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7400 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
8fc897b0 7401 if (ret_val)
1da177e4
LT		 7402 return ret_val;
7403
7404 }
7405 return E1000_SUCCESS;
7406}
7407
7408/******************************************************************************
7409 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
7410 *
7411 * hw - Struct containing variables accessed by shared code
7412 *****************************************************************************/
7413static int32_t
7414e1000_set_vco_speed(struct e1000_hw *hw)
7415{
7416 int32_t ret_val;
7417 uint16_t default_page = 0;
7418 uint16_t phy_data;
7419
7420 DEBUGFUNC("e1000_set_vco_speed");
7421
8fc897b0 7422 switch (hw->mac_type) {
1da177e4
LT		 7423 case e1000_82545_rev_3:
7424 case e1000_82546_rev_3:
7425 break;
7426 default:
7427 return E1000_SUCCESS;
7428 }
7429
7430 /* Set PHY register 30, page 5, bit 8 to 0 */
7431
7432 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
8fc897b0 7433 if (ret_val)
1da177e4
LT		 7434 return ret_val;
7435
7436 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
8fc897b0 7437 if (ret_val)
1da177e4
LT		 7438 return ret_val;
7439
7440 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
8fc897b0 7441 if (ret_val)
1da177e4
LT		 7442 return ret_val;
7443
7444 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
7445 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
8fc897b0 7446 if (ret_val)
1da177e4
LT		 7447 return ret_val;
7448
7449 /* Set PHY register 30, page 4, bit 11 to 1 */
7450
7451 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
8fc897b0 7452 if (ret_val)
1da177e4
LT		 7453 return ret_val;
7454
7455 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
8fc897b0 7456 if (ret_val)
1da177e4
LT		 7457 return ret_val;
7458
7459 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
7460 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
8fc897b0 7461 if (ret_val)
1da177e4
LT		 7462 return ret_val;
7463
7464 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
8fc897b0 7465 if (ret_val)
1da177e4
LT		 7466 return ret_val;
7467
7468 return E1000_SUCCESS;
7469}
7470
1da177e4 7471
2d7edb92
MC		 7472/*****************************************************************************
7473 * This function reads the cookie from ARC ram.
7474 *
7475 * returns: - E1000_SUCCESS .
7476 ****************************************************************************/
7477int32_t
7478e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer)
7479{
7480 uint8_t i;
76c224bc 7481 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET;
2d7edb92 7482 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH;
1da177e4 7483
2d7edb92
MC		 7484 length = (length >> 2);
7485 offset = (offset >> 2);
1da177e4 7486
2d7edb92
MC		 7487 for (i = 0; i < length; i++) {
7488 *((uint32_t *) buffer + i) =
7489 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
7490 }
7491 return E1000_SUCCESS;
7492}
7493
7494
7495/*****************************************************************************
7496 * This function checks whether the HOST IF is enabled for command operaton
7497 * and also checks whether the previous command is completed.
7498 * It busy waits in case of previous command is not completed.
7499 *
76c224bc 7500 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
2d7edb92
MC		 7501 * timeout
7502 * - E1000_SUCCESS for success.
7503 ****************************************************************************/
3ad2cc67 7504static int32_t
2d7edb92
MC		 7505e1000_mng_enable_host_if(struct e1000_hw * hw)
7506{
7507 uint32_t hicr;
7508 uint8_t i;
7509
7510 /* Check that the host interface is enabled. */
7511 hicr = E1000_READ_REG(hw, HICR);
7512 if ((hicr & E1000_HICR_EN) == 0) {
7513 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
7514 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7515 }
7516 /* check the previous command is completed */
7517 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
7518 hicr = E1000_READ_REG(hw, HICR);
7519 if (!(hicr & E1000_HICR_C))
7520 break;
f8ec4733 7521 mdelay(1);
2d7edb92
MC		 7522 }
7523
76c224bc 7524 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
2d7edb92
MC		 7525 DEBUGOUT("Previous command timeout failed .\n");
7526 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7527 }
7528 return E1000_SUCCESS;
7529}
7530
7531/*****************************************************************************
7532 * This function writes the buffer content at the offset given on the host if.
7533 * It also does alignment considerations to do the writes in most efficient way.
7534 * Also fills up the sum of the buffer in *buffer parameter.
7535 *
7536 * returns - E1000_SUCCESS for success.
7537 ****************************************************************************/
3ad2cc67 7538static int32_t
2d7edb92
MC		 7539e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer,
7540 uint16_t length, uint16_t offset, uint8_t *sum)
7541{
7542 uint8_t *tmp;
7543 uint8_t *bufptr = buffer;
8fc897b0 7544 uint32_t data = 0;
2d7edb92
MC		 7545 uint16_t remaining, i, j, prev_bytes;
7546
7547 /* sum = only sum of the data and it is not checksum */
7548
7549 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
7550 return -E1000_ERR_PARAM;
7551 }
7552
7553 tmp = (uint8_t *)&data;
7554 prev_bytes = offset & 0x3;
7555 offset &= 0xFFFC;
7556 offset >>= 2;
7557
7558 if (prev_bytes) {
7559 data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset);
7560 for (j = prev_bytes; j < sizeof(uint32_t); j++) {
7561 *(tmp + j) = *bufptr++;
7562 *sum += *(tmp + j);
7563 }
7564 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data);
7565 length -= j - prev_bytes;
7566 offset++;
7567 }
7568
7569 remaining = length & 0x3;
7570 length -= remaining;
7571
7572 /* Calculate length in DWORDs */
7573 length >>= 2;
7574
7575 /* The device driver writes the relevant command block into the
7576 * ram area. */
7577 for (i = 0; i < length; i++) {
7578 for (j = 0; j < sizeof(uint32_t); j++) {
7579 *(tmp + j) = *bufptr++;
7580 *sum += *(tmp + j);
7581 }
7582
7583 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7584 }
7585 if (remaining) {
7586 for (j = 0; j < sizeof(uint32_t); j++) {
7587 if (j < remaining)
7588 *(tmp + j) = *bufptr++;
7589 else
7590 *(tmp + j) = 0;
7591
7592 *sum += *(tmp + j);
7593 }
7594 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7595 }
7596
7597 return E1000_SUCCESS;
7598}
7599
7600
7601/*****************************************************************************
7602 * This function writes the command header after does the checksum calculation.
7603 *
7604 * returns - E1000_SUCCESS for success.
7605 ****************************************************************************/
3ad2cc67 7606static int32_t
2d7edb92
MC		 7607e1000_mng_write_cmd_header(struct e1000_hw * hw,
7608 struct e1000_host_mng_command_header * hdr)
7609{
7610 uint16_t i;
7611 uint8_t sum;
7612 uint8_t *buffer;
7613
7614 /* Write the whole command header structure which includes sum of
7615 * the buffer */
7616
7617 uint16_t length = sizeof(struct e1000_host_mng_command_header);
7618
7619 sum = hdr->checksum;
7620 hdr->checksum = 0;
7621
7622 buffer = (uint8_t *) hdr;
7623 i = length;
8fc897b0 7624 while (i--)
2d7edb92
MC		 7625 sum += buffer[i];
7626
7627 hdr->checksum = 0 - sum;
7628
7629 length >>= 2;
7630 /* The device driver writes the relevant command block into the ram area. */
4ca213a6 7631 for (i = 0; i < length; i++) {
2d7edb92 7632 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i));
4ca213a6
AK		 7633 E1000_WRITE_FLUSH(hw);
7634 }
2d7edb92
MC		 7635
7636 return E1000_SUCCESS;
7637}
7638
7639
7640/*****************************************************************************
7641 * This function indicates to ARC that a new command is pending which completes
7642 * one write operation by the driver.
7643 *
7644 * returns - E1000_SUCCESS for success.
7645 ****************************************************************************/
3ad2cc67 7646static int32_t
8fc897b0 7647e1000_mng_write_commit(struct e1000_hw * hw)
2d7edb92
MC		 7648{
7649 uint32_t hicr;
7650
7651 hicr = E1000_READ_REG(hw, HICR);
7652 /* Setting this bit tells the ARC that a new command is pending. */
7653 E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C);
7654
7655 return E1000_SUCCESS;
7656}
7657
7658
7659/*****************************************************************************
7660 * This function checks the mode of the firmware.
7661 *
7662 * returns - TRUE when the mode is IAMT or FALSE.
7663 ****************************************************************************/
7664boolean_t
cd94dd0b 7665e1000_check_mng_mode(struct e1000_hw *hw)
2d7edb92
MC		 7666{
7667 uint32_t fwsm;
7668
7669 fwsm = E1000_READ_REG(hw, FWSM);
7670
cd94dd0b
AK		 7671 if (hw->mac_type == e1000_ich8lan) {
7672 if ((fwsm & E1000_FWSM_MODE_MASK) ==
7673 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7674 return TRUE;
7675 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
7676 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2d7edb92
MC		 7677 return TRUE;
7678
7679 return FALSE;
7680}
7681
7682
7683/*****************************************************************************
7684 * This function writes the dhcp info .
7685 ****************************************************************************/
7686int32_t
7687e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer,
7688 uint16_t length)
7689{
7690 int32_t ret_val;
7691 struct e1000_host_mng_command_header hdr;
7692
7693 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
7694 hdr.command_length = length;
7695 hdr.reserved1 = 0;
7696 hdr.reserved2 = 0;
7697 hdr.checksum = 0;
7698
7699 ret_val = e1000_mng_enable_host_if(hw);
7700 if (ret_val == E1000_SUCCESS) {
7701 ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr),
7702 &(hdr.checksum));
7703 if (ret_val == E1000_SUCCESS) {
7704 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
7705 if (ret_val == E1000_SUCCESS)
7706 ret_val = e1000_mng_write_commit(hw);
7707 }
7708 }
7709 return ret_val;
7710}
7711
7712
7713/*****************************************************************************
7714 * This function calculates the checksum.
7715 *
7716 * returns - checksum of buffer contents.
7717 ****************************************************************************/
7718uint8_t
7719e1000_calculate_mng_checksum(char *buffer, uint32_t length)
7720{
7721 uint8_t sum = 0;
7722 uint32_t i;
7723
7724 if (!buffer)
7725 return 0;
7726
7727 for (i=0; i < length; i++)
7728 sum += buffer[i];
7729
7730 return (uint8_t) (0 - sum);
7731}
7732
7733/*****************************************************************************
7734 * This function checks whether tx pkt filtering needs to be enabled or not.
7735 *
7736 * returns - TRUE for packet filtering or FALSE.
7737 ****************************************************************************/
7738boolean_t
7739e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
7740{
7741 /* called in init as well as watchdog timer functions */
7742
7743 int32_t ret_val, checksum;
7744 boolean_t tx_filter = FALSE;
7745 struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
7746 uint8_t *buffer = (uint8_t *) &(hw->mng_cookie);
7747
7748 if (e1000_check_mng_mode(hw)) {
7749 ret_val = e1000_mng_enable_host_if(hw);
7750 if (ret_val == E1000_SUCCESS) {
7751 ret_val = e1000_host_if_read_cookie(hw, buffer);
7752 if (ret_val == E1000_SUCCESS) {
7753 checksum = hdr->checksum;
7754 hdr->checksum = 0;
7755 if ((hdr->signature == E1000_IAMT_SIGNATURE) &&
7756 checksum == e1000_calculate_mng_checksum((char *)buffer,
7757 E1000_MNG_DHCP_COOKIE_LENGTH)) {
7758 if (hdr->status &
7759 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
7760 tx_filter = TRUE;
7761 } else
7762 tx_filter = TRUE;
7763 } else
7764 tx_filter = TRUE;
7765 }
7766 }
7767
7768 hw->tx_pkt_filtering = tx_filter;
7769 return tx_filter;
7770}
7771
7772/******************************************************************************
7773 * Verifies the hardware needs to allow ARPs to be processed by the host
7774 *
7775 * hw - Struct containing variables accessed by shared code
7776 *
7777 * returns: - TRUE/FALSE
7778 *
7779 *****************************************************************************/
7780uint32_t
7781e1000_enable_mng_pass_thru(struct e1000_hw *hw)
7782{
7783 uint32_t manc;
7784 uint32_t fwsm, factps;
7785
7786 if (hw->asf_firmware_present) {
7787 manc = E1000_READ_REG(hw, MANC);
7788
7789 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
7790 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
7791 return FALSE;
7792 if (e1000_arc_subsystem_valid(hw) == TRUE) {
7793 fwsm = E1000_READ_REG(hw, FWSM);
7794 factps = E1000_READ_REG(hw, FACTPS);
7795
7796 if (((fwsm & E1000_FWSM_MODE_MASK) ==
7797 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)) &&
7798 (factps & E1000_FACTPS_MNGCG))
7799 return TRUE;
7800 } else
7801 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
7802 return TRUE;
7803 }
7804 return FALSE;
7805}
7806
7807static int32_t
7808e1000_polarity_reversal_workaround(struct e1000_hw *hw)
7809{
7810 int32_t ret_val;
7811 uint16_t mii_status_reg;
7812 uint16_t i;
7813
7814 /* Polarity reversal workaround for forced 10F/10H links. */
7815
7816 /* Disable the transmitter on the PHY */
7817
7818 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
8fc897b0 7819 if (ret_val)
1da177e4
LT		 7820 return ret_val;
7821 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
8fc897b0 7822 if (ret_val)
1da177e4
LT		 7823 return ret_val;
7824
7825 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
8fc897b0 7826 if (ret_val)
1da177e4
LT		 7827 return ret_val;
7828
7829 /* This loop will early-out if the NO link condition has been met. */
8fc897b0 7830 for (i = PHY_FORCE_TIME; i > 0; i--) {
1da177e4
LT		 7831 /* Read the MII Status Register and wait for Link Status bit
7832 * to be clear.
7833 */
7834
7835 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 7836 if (ret_val)
1da177e4
LT		 7837 return ret_val;
7838
7839 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 7840 if (ret_val)
1da177e4
LT		 7841 return ret_val;
7842
8fc897b0 7843 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
f8ec4733 7844 mdelay(100);
1da177e4
LT		 7845 }
7846
7847 /* Recommended delay time after link has been lost */
f8ec4733 7848 mdelay(1000);
1da177e4
LT		 7849
7850 /* Now we will re-enable th transmitter on the PHY */
7851
7852 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
8fc897b0 7853 if (ret_val)
1da177e4 7854 return ret_val;
f8ec4733 7855 mdelay(50);
1da177e4 7856 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
8fc897b0 7857 if (ret_val)
1da177e4 7858 return ret_val;
f8ec4733 7859 mdelay(50);
1da177e4 7860 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
8fc897b0 7861 if (ret_val)
1da177e4 7862 return ret_val;
f8ec4733 7863 mdelay(50);
1da177e4 7864 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
8fc897b0 7865 if (ret_val)
1da177e4
LT		 7866 return ret_val;
7867
7868 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
8fc897b0 7869 if (ret_val)
1da177e4
LT		 7870 return ret_val;
7871
7872 /* This loop will early-out if the link condition has been met. */
8fc897b0 7873 for (i = PHY_FORCE_TIME; i > 0; i--) {
1da177e4
LT		 7874 /* Read the MII Status Register and wait for Link Status bit
7875 * to be set.
7876 */
7877
7878 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 7879 if (ret_val)
1da177e4
LT		 7880 return ret_val;
7881
7882 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 7883 if (ret_val)
1da177e4
LT		 7884 return ret_val;
7885
8fc897b0 7886 if (mii_status_reg & MII_SR_LINK_STATUS) break;
f8ec4733 7887 mdelay(100);
1da177e4
LT		 7888 }
7889 return E1000_SUCCESS;
7890}
7891
2d7edb92
MC		 7892/***************************************************************************
7893 *
7894 * Disables PCI-Express master access.
7895 *
7896 * hw: Struct containing variables accessed by shared code
7897 *
7898 * returns: - none.
7899 *
7900 ***************************************************************************/
3ad2cc67 7901static void
2d7edb92
MC		 7902e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7903{
7904 uint32_t ctrl;
7905
7906 DEBUGFUNC("e1000_set_pci_express_master_disable");
7907
7908 if (hw->bus_type != e1000_bus_type_pci_express)
7909 return;
7910
7911 ctrl = E1000_READ_REG(hw, CTRL);
7912 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
7913 E1000_WRITE_REG(hw, CTRL, ctrl);
7914}
7915
7916/***************************************************************************
7917 *
7918 * Enables PCI-Express master access.
7919 *
7920 * hw: Struct containing variables accessed by shared code
7921 *
7922 * returns: - none.
7923 *
7924 ***************************************************************************/
e4c780b1 7925#if 0
2d7edb92
MC		 7926void
7927e1000_enable_pciex_master(struct e1000_hw *hw)
7928{
7929 uint32_t ctrl;
7930
7931 DEBUGFUNC("e1000_enable_pciex_master");
7932
7933 if (hw->bus_type != e1000_bus_type_pci_express)
7934 return;
7935
7936 ctrl = E1000_READ_REG(hw, CTRL);
7937 ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE;
7938 E1000_WRITE_REG(hw, CTRL, ctrl);
7939}
e4c780b1 7940#endif /* 0 */
2d7edb92
MC		 7941
7942/*******************************************************************************
7943 *
7944 * Disables PCI-Express master access and verifies there are no pending requests
7945 *
7946 * hw: Struct containing variables accessed by shared code
7947 *
7948 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
7949 * caused the master requests to be disabled.
7950 * E1000_SUCCESS master requests disabled.
7951 *
7952 ******************************************************************************/
7953int32_t
7954e1000_disable_pciex_master(struct e1000_hw *hw)
7955{
7956 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */
7957
7958 DEBUGFUNC("e1000_disable_pciex_master");
7959
7960 if (hw->bus_type != e1000_bus_type_pci_express)
7961 return E1000_SUCCESS;
7962
7963 e1000_set_pci_express_master_disable(hw);
7964
8fc897b0
AK		 7965 while (timeout) {
7966 if (!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
2d7edb92
MC		 7967 break;
7968 else
7969 udelay(100);
7970 timeout--;
7971 }
7972
8fc897b0 7973 if (!timeout) {
2d7edb92
MC		 7974 DEBUGOUT("Master requests are pending.\n");
7975 return -E1000_ERR_MASTER_REQUESTS_PENDING;
7976 }
7977
7978 return E1000_SUCCESS;
7979}
7980
7981/*******************************************************************************
7982 *
7983 * Check for EEPROM Auto Read bit done.
7984 *
7985 * hw: Struct containing variables accessed by shared code
7986 *
7987 * returns: - E1000_ERR_RESET if fail to reset MAC
7988 * E1000_SUCCESS at any other case.
7989 *
7990 ******************************************************************************/
3ad2cc67 7991static int32_t
2d7edb92
MC		 7992e1000_get_auto_rd_done(struct e1000_hw *hw)
7993{
7994 int32_t timeout = AUTO_READ_DONE_TIMEOUT;
7995
7996 DEBUGFUNC("e1000_get_auto_rd_done");
7997
7998 switch (hw->mac_type) {
7999 default:
f8ec4733 8000 msleep(5);
2d7edb92 8001 break;
868d5309
MC		 8002 case e1000_82571:
8003 case e1000_82572:
2d7edb92 8004 case e1000_82573:
6418ecc6 8005 case e1000_80003es2lan:
cd94dd0b
AK		 8006 case e1000_ich8lan:
8007 while (timeout) {
8008 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD)
8009 break;
f8ec4733 8010 else msleep(1);
2d7edb92
MC		 8011 timeout--;
8012 }
8013
8fc897b0 8014 if (!timeout) {
2d7edb92
MC		 8015 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
8016 return -E1000_ERR_RESET;
8017 }
8018 break;
8019 }
8020
fd803241
JK		 8021 /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high.
8022 * Need to wait for PHY configuration completion before accessing NVM
8023 * and PHY. */
8024 if (hw->mac_type == e1000_82573)
f8ec4733 8025 msleep(25);
fd803241 8026
2d7edb92
MC		 8027 return E1000_SUCCESS;
8028}
8029
8030/***************************************************************************
8031 * Checks if the PHY configuration is done
8032 *
8033 * hw: Struct containing variables accessed by shared code
8034 *
8035 * returns: - E1000_ERR_RESET if fail to reset MAC
8036 * E1000_SUCCESS at any other case.
8037 *
8038 ***************************************************************************/
3ad2cc67 8039static int32_t
2d7edb92
MC		 8040e1000_get_phy_cfg_done(struct e1000_hw *hw)
8041{
868d5309
MC		 8042 int32_t timeout = PHY_CFG_TIMEOUT;
8043 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
8044
2d7edb92
MC		 8045 DEBUGFUNC("e1000_get_phy_cfg_done");
8046
868d5309
MC		 8047 switch (hw->mac_type) {
8048 default:
f8ec4733 8049 mdelay(10);
868d5309 8050 break;
6418ecc6
JK		 8051 case e1000_80003es2lan:
8052 /* Separate *_CFG_DONE_* bit for each port */
8053 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
8054 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
8055 /* Fall Through */
868d5309
MC		 8056 case e1000_82571:
8057 case e1000_82572:
8058 while (timeout) {
8059 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
8060 break;
8061 else
f8ec4733 8062 msleep(1);
868d5309
MC		 8063 timeout--;
8064 }
8065
8066 if (!timeout) {
8067 DEBUGOUT("MNG configuration cycle has not completed.\n");
8068 return -E1000_ERR_RESET;
8069 }
8070 break;
8071 }
2d7edb92
MC		 8072
8073 return E1000_SUCCESS;
8074}
8075
8076/***************************************************************************
8077 *
8078 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
8079 * adapter or Eeprom access.
8080 *
8081 * hw: Struct containing variables accessed by shared code
8082 *
8083 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
8084 * E1000_SUCCESS at any other case.
8085 *
8086 ***************************************************************************/
3ad2cc67 8087static int32_t
2d7edb92
MC		 8088e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
8089{
8090 int32_t timeout;
8091 uint32_t swsm;
8092
8093 DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
8094
8fc897b0 8095 if (!hw->eeprom_semaphore_present)
2d7edb92
MC		 8096 return E1000_SUCCESS;
8097
6418ecc6
JK		 8098 if (hw->mac_type == e1000_80003es2lan) {
8099 /* Get the SW semaphore. */
8100 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
8101 return -E1000_ERR_EEPROM;
8102 }
2d7edb92
MC		 8103
8104 /* Get the FW semaphore. */
8105 timeout = hw->eeprom.word_size + 1;
8fc897b0 8106 while (timeout) {
2d7edb92
MC		 8107 swsm = E1000_READ_REG(hw, SWSM);
8108 swsm |= E1000_SWSM_SWESMBI;
8109 E1000_WRITE_REG(hw, SWSM, swsm);
8110 /* if we managed to set the bit we got the semaphore. */
8111 swsm = E1000_READ_REG(hw, SWSM);
8fc897b0 8112 if (swsm & E1000_SWSM_SWESMBI)
2d7edb92
MC		 8113 break;
8114
8115 udelay(50);
8116 timeout--;
8117 }
8118
8fc897b0 8119 if (!timeout) {
2d7edb92
MC		 8120 /* Release semaphores */
8121 e1000_put_hw_eeprom_semaphore(hw);
8122 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
8123 return -E1000_ERR_EEPROM;
8124 }
8125
8126 return E1000_SUCCESS;
8127}
8128
8129/***************************************************************************
8130 * This function clears HW semaphore bits.
8131 *
8132 * hw: Struct containing variables accessed by shared code
8133 *
8134 * returns: - None.
8135 *
8136 ***************************************************************************/
3ad2cc67 8137static void
2d7edb92
MC		 8138e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
8139{
8140 uint32_t swsm;
8141
8142 DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
8143
8fc897b0 8144 if (!hw->eeprom_semaphore_present)
2d7edb92
MC		 8145 return;
8146
8147 swsm = E1000_READ_REG(hw, SWSM);
6418ecc6
JK		 8148 if (hw->mac_type == e1000_80003es2lan) {
8149 /* Release both semaphores. */
8150 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
8151 } else
868d5309 8152 swsm &= ~(E1000_SWSM_SWESMBI);
2d7edb92
MC		 8153 E1000_WRITE_REG(hw, SWSM, swsm);
8154}
8155
6418ecc6
JK		 8156/***************************************************************************
8157 *
8158 * Obtaining software semaphore bit (SMBI) before resetting PHY.
8159 *
8160 * hw: Struct containing variables accessed by shared code
8161 *
8162 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
8163 * E1000_SUCCESS at any other case.
8164 *
8165 ***************************************************************************/
e4c780b1 8166static int32_t
6418ecc6
JK		 8167e1000_get_software_semaphore(struct e1000_hw *hw)
8168{
8169 int32_t timeout = hw->eeprom.word_size + 1;
8170 uint32_t swsm;
8171
8172 DEBUGFUNC("e1000_get_software_semaphore");
8173
8174 if (hw->mac_type != e1000_80003es2lan)
8175 return E1000_SUCCESS;
8176
8fc897b0 8177 while (timeout) {
6418ecc6
JK		 8178 swsm = E1000_READ_REG(hw, SWSM);
8179 /* If SMBI bit cleared, it is now set and we hold the semaphore */
8fc897b0 8180 if (!(swsm & E1000_SWSM_SMBI))
6418ecc6 8181 break;
f8ec4733 8182 mdelay(1);
6418ecc6
JK		 8183 timeout--;
8184 }
8185
8fc897b0 8186 if (!timeout) {
6418ecc6
JK		 8187 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
8188 return -E1000_ERR_RESET;
8189 }
8190
8191 return E1000_SUCCESS;
8192}
8193
8194/***************************************************************************
8195 *
8196 * Release semaphore bit (SMBI).
8197 *
8198 * hw: Struct containing variables accessed by shared code
8199 *
8200 ***************************************************************************/
e4c780b1 8201static void
6418ecc6
JK		 8202e1000_release_software_semaphore(struct e1000_hw *hw)
8203{
8204 uint32_t swsm;
8205
8206 DEBUGFUNC("e1000_release_software_semaphore");
8207
8208 if (hw->mac_type != e1000_80003es2lan)
8209 return;
8210
8211 swsm = E1000_READ_REG(hw, SWSM);
8212 /* Release the SW semaphores.*/
8213 swsm &= ~E1000_SWSM_SMBI;
8214 E1000_WRITE_REG(hw, SWSM, swsm);
8215}
8216
2d7edb92
MC		 8217/******************************************************************************
8218 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
8219 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
8220 * the caller to figure out how to deal with it.
8221 *
8222 * hw - Struct containing variables accessed by shared code
8223 *
8224 * returns: - E1000_BLK_PHY_RESET
8225 * E1000_SUCCESS
8226 *
8227 *****************************************************************************/
8228int32_t
8229e1000_check_phy_reset_block(struct e1000_hw *hw)
8230{
8231 uint32_t manc = 0;
cd94dd0b
AK		 8232 uint32_t fwsm = 0;
8233
8234 if (hw->mac_type == e1000_ich8lan) {
8235 fwsm = E1000_READ_REG(hw, FWSM);
8236 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
8237 : E1000_BLK_PHY_RESET;
8238 }
96838a40
JB		 8239
8240 if (hw->mac_type > e1000_82547_rev_2)
2d7edb92
MC		 8241 manc = E1000_READ_REG(hw, MANC);
8242 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
8243 E1000_BLK_PHY_RESET : E1000_SUCCESS;
8244}
8245
3ad2cc67 8246static uint8_t
2d7edb92
MC		 8247e1000_arc_subsystem_valid(struct e1000_hw *hw)
8248{
8249 uint32_t fwsm;
8250
8251 /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
8252 * may not be provided a DMA clock when no manageability features are
8253 * enabled. We do not want to perform any reads/writes to these registers
8254 * if this is the case. We read FWSM to determine the manageability mode.
8255 */
8256 switch (hw->mac_type) {
868d5309
MC		 8257 case e1000_82571:
8258 case e1000_82572:
2d7edb92 8259 case e1000_82573:
6418ecc6 8260 case e1000_80003es2lan:
2d7edb92 8261 fwsm = E1000_READ_REG(hw, FWSM);
8fc897b0 8262 if ((fwsm & E1000_FWSM_MODE_MASK) != 0)
2d7edb92
MC		 8263 return TRUE;
8264 break;
cd94dd0b
AK		 8265 case e1000_ich8lan:
8266 return TRUE;
2d7edb92
MC		 8267 default:
8268 break;
8269 }
8270 return FALSE;
8271}
8272
8273
d37ea5d5
AK		 8274/******************************************************************************
8275 * Configure PCI-Ex no-snoop
8276 *
8277 * hw - Struct containing variables accessed by shared code.
8278 * no_snoop - Bitmap of no-snoop events.
8279 *
8280 * returns: E1000_SUCCESS
8281 *
8282 *****************************************************************************/
e4c780b1 8283static int32_t
d37ea5d5
AK		 8284e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop)
8285{
8286 uint32_t gcr_reg = 0;
8287
8288 DEBUGFUNC("e1000_set_pci_ex_no_snoop");
8289
8290 if (hw->bus_type == e1000_bus_type_unknown)
8291 e1000_get_bus_info(hw);
8292
8293 if (hw->bus_type != e1000_bus_type_pci_express)
8294 return E1000_SUCCESS;
8295
8296 if (no_snoop) {
8297 gcr_reg = E1000_READ_REG(hw, GCR);
8298 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL);
8299 gcr_reg |= no_snoop;
8300 E1000_WRITE_REG(hw, GCR, gcr_reg);
8301 }
8302 if (hw->mac_type == e1000_ich8lan) {
8303 uint32_t ctrl_ext;
8304
8305 E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL);
8306
8307 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
8308 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
8309 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
8310 }
8311
8312 return E1000_SUCCESS;
8313}
8314
8315/***************************************************************************
8316 *
8317 * Get software semaphore FLAG bit (SWFLAG).
8318 * SWFLAG is used to synchronize the access to all shared resource between
8319 * SW, FW and HW.
8320 *
8321 * hw: Struct containing variables accessed by shared code
8322 *
8323 ***************************************************************************/
e4c780b1 8324static int32_t
d37ea5d5
AK		 8325e1000_get_software_flag(struct e1000_hw *hw)
8326{
8327 int32_t timeout = PHY_CFG_TIMEOUT;
8328 uint32_t extcnf_ctrl;
8329
8330 DEBUGFUNC("e1000_get_software_flag");
8331
8332 if (hw->mac_type == e1000_ich8lan) {
8333 while (timeout) {
8334 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8335 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
8336 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8337
8338 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8339 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
8340 break;
f8ec4733 8341 mdelay(1);
d37ea5d5
AK		 8342 timeout--;
8343 }
8344
8345 if (!timeout) {
8346 DEBUGOUT("FW or HW locks the resource too long.\n");
8347 return -E1000_ERR_CONFIG;
8348 }
8349 }
8350
8351 return E1000_SUCCESS;
8352}
8353
8354/***************************************************************************
8355 *
8356 * Release software semaphore FLAG bit (SWFLAG).
8357 * SWFLAG is used to synchronize the access to all shared resource between
8358 * SW, FW and HW.
8359 *
8360 * hw: Struct containing variables accessed by shared code
8361 *
8362 ***************************************************************************/
e4c780b1 8363static void
d37ea5d5
AK		 8364e1000_release_software_flag(struct e1000_hw *hw)
8365{
8366 uint32_t extcnf_ctrl;
8367
8368 DEBUGFUNC("e1000_release_software_flag");
8369
8370 if (hw->mac_type == e1000_ich8lan) {
8371 extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL);
8372 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
8373 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8374 }
8375
8376 return;
8377}
8378
8379/***************************************************************************
8380 *
8381 * Disable dynamic power down mode in ife PHY.
8382 * It can be used to workaround band-gap problem.
8383 *
8384 * hw: Struct containing variables accessed by shared code
8385 *
8386 ***************************************************************************/
e4c780b1 8387#if 0
d37ea5d5
AK		 8388int32_t
8389e1000_ife_disable_dynamic_power_down(struct e1000_hw *hw)
8390{
8391 uint16_t phy_data;
8392 int32_t ret_val = E1000_SUCCESS;
8393
8394 DEBUGFUNC("e1000_ife_disable_dynamic_power_down");
8395
8396 if (hw->phy_type == e1000_phy_ife) {
8397 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
8398 if (ret_val)
8399 return ret_val;
8400
8401 phy_data |= IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN;
8402 ret_val = e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, phy_data);
8403 }
8404
8405 return ret_val;
8406}
e4c780b1 8407#endif /* 0 */
d37ea5d5
AK		 8408
8409/***************************************************************************
8410 *
8411 * Enable dynamic power down mode in ife PHY.
8412 * It can be used to workaround band-gap problem.
8413 *
8414 * hw: Struct containing variables accessed by shared code
8415 *
8416 ***************************************************************************/
e4c780b1 8417#if 0
d37ea5d5
AK		 8418int32_t
8419e1000_ife_enable_dynamic_power_down(struct e1000_hw *hw)
8420{
8421 uint16_t phy_data;
8422 int32_t ret_val = E1000_SUCCESS;
8423
8424 DEBUGFUNC("e1000_ife_enable_dynamic_power_down");
8425
8426 if (hw->phy_type == e1000_phy_ife) {
8427 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
8428 if (ret_val)
8429 return ret_val;
8430
8431 phy_data &= ~IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN;
8432 ret_val = e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, phy_data);
8433 }
8434
8435 return ret_val;
8436}
e4c780b1 8437#endif /* 0 */
d37ea5d5
AK		 8438
8439/******************************************************************************
8440 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
8441 * register.
8442 *
8443 * hw - Struct containing variables accessed by shared code
8444 * offset - offset of word in the EEPROM to read
8445 * data - word read from the EEPROM
8446 * words - number of words to read
8447 *****************************************************************************/
e4c780b1 8448static int32_t
d37ea5d5
AK		 8449e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8450 uint16_t *data)
8451{
8452 int32_t error = E1000_SUCCESS;
8453 uint32_t flash_bank = 0;
8454 uint32_t act_offset = 0;
8455 uint32_t bank_offset = 0;
8456 uint16_t word = 0;
8457 uint16_t i = 0;
8458
8459 /* We need to know which is the valid flash bank. In the event
8460 * that we didn't allocate eeprom_shadow_ram, we may not be
8461 * managing flash_bank. So it cannot be trusted and needs
8462 * to be updated with each read.
8463 */
8464 /* Value of bit 22 corresponds to the flash bank we're on. */
8465 flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0;
8466
8467 /* Adjust offset appropriately if we're on bank 1 - adjust for word size */
8468 bank_offset = flash_bank * (hw->flash_bank_size * 2);
8469
8470 error = e1000_get_software_flag(hw);
8471 if (error != E1000_SUCCESS)
8472 return error;
8473
8474 for (i = 0; i < words; i++) {
8475 if (hw->eeprom_shadow_ram != NULL &&
8476 hw->eeprom_shadow_ram[offset+i].modified == TRUE) {
8477 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
8478 } else {
8479 /* The NVM part needs a byte offset, hence * 2 */
8480 act_offset = bank_offset + ((offset + i) * 2);
8481 error = e1000_read_ich8_word(hw, act_offset, &word);
8482 if (error != E1000_SUCCESS)
8483 break;
8484 data[i] = word;
8485 }
8486 }
8487
8488 e1000_release_software_flag(hw);
8489
8490 return error;
8491}
8492
8493/******************************************************************************
8494 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access
8495 * register. Actually, writes are written to the shadow ram cache in the hw
8496 * structure hw->e1000_shadow_ram. e1000_commit_shadow_ram flushes this to
8497 * the NVM, which occurs when the NVM checksum is updated.
8498 *
8499 * hw - Struct containing variables accessed by shared code
8500 * offset - offset of word in the EEPROM to write
8501 * words - number of words to write
8502 * data - words to write to the EEPROM
8503 *****************************************************************************/
e4c780b1 8504static int32_t
d37ea5d5
AK		 8505e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8506 uint16_t *data)
8507{
8508 uint32_t i = 0;
8509 int32_t error = E1000_SUCCESS;
8510
8511 error = e1000_get_software_flag(hw);
8512 if (error != E1000_SUCCESS)
8513 return error;
8514
8515 /* A driver can write to the NVM only if it has eeprom_shadow_ram
8516 * allocated. Subsequent reads to the modified words are read from
8517 * this cached structure as well. Writes will only go into this
8518 * cached structure unless it's followed by a call to
8519 * e1000_update_eeprom_checksum() where it will commit the changes
8520 * and clear the "modified" field.
8521 */
8522 if (hw->eeprom_shadow_ram != NULL) {
8523 for (i = 0; i < words; i++) {
8524 if ((offset + i) < E1000_SHADOW_RAM_WORDS) {
8525 hw->eeprom_shadow_ram[offset+i].modified = TRUE;
8526 hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i];
8527 } else {
8528 error = -E1000_ERR_EEPROM;
8529 break;
8530 }
8531 }
8532 } else {
8533 /* Drivers have the option to not allocate eeprom_shadow_ram as long
8534 * as they don't perform any NVM writes. An attempt in doing so
8535 * will result in this error.
8536 */
8537 error = -E1000_ERR_EEPROM;
8538 }
8539
8540 e1000_release_software_flag(hw);
8541
8542 return error;
8543}
8544
8545/******************************************************************************
8546 * This function does initial flash setup so that a new read/write/erase cycle
8547 * can be started.
8548 *
8549 * hw - The pointer to the hw structure
8550 ****************************************************************************/
e4c780b1 8551static int32_t
d37ea5d5
AK		 8552e1000_ich8_cycle_init(struct e1000_hw *hw)
8553{
8554 union ich8_hws_flash_status hsfsts;
8555 int32_t error = E1000_ERR_EEPROM;
8556 int32_t i = 0;
8557
8558 DEBUGFUNC("e1000_ich8_cycle_init");
8559
8560 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8561
8562 /* May be check the Flash Des Valid bit in Hw status */
8563 if (hsfsts.hsf_status.fldesvalid == 0) {
8564 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.");
8565 return error;
8566 }
8567
8568 /* Clear FCERR in Hw status by writing 1 */
8569 /* Clear DAEL in Hw status by writing a 1 */
8570 hsfsts.hsf_status.flcerr = 1;
8571 hsfsts.hsf_status.dael = 1;
8572
8573 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval);
8574
8575 /* Either we should have a hardware SPI cycle in progress bit to check
8576 * against, in order to start a new cycle or FDONE bit should be changed
8577 * in the hardware so that it is 1 after harware reset, which can then be
8578 * used as an indication whether a cycle is in progress or has been
8579 * completed .. we should also have some software semaphore mechanism to
8580 * guard FDONE or the cycle in progress bit so that two threads access to
8581 * those bits can be sequentiallized or a way so that 2 threads dont
8582 * start the cycle at the same time */
8583
8584 if (hsfsts.hsf_status.flcinprog == 0) {
8585 /* There is no cycle running at present, so we can start a cycle */
8586 /* Begin by setting Flash Cycle Done. */
8587 hsfsts.hsf_status.flcdone = 1;
8588 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval);
8589 error = E1000_SUCCESS;
8590 } else {
8591 /* otherwise poll for sometime so the current cycle has a chance
8592 * to end before giving up. */
8593 for (i = 0; i < ICH8_FLASH_COMMAND_TIMEOUT; i++) {
8594 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8595 if (hsfsts.hsf_status.flcinprog == 0) {
8596 error = E1000_SUCCESS;
8597 break;
8598 }
8599 udelay(1);
8600 }
8601 if (error == E1000_SUCCESS) {
8602 /* Successful in waiting for previous cycle to timeout,
8603 * now set the Flash Cycle Done. */
8604 hsfsts.hsf_status.flcdone = 1;
8605 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval);
8606 } else {
8607 DEBUGOUT("Flash controller busy, cannot get access");
8608 }
8609 }
8610 return error;
8611}
8612
8613/******************************************************************************
8614 * This function starts a flash cycle and waits for its completion
8615 *
8616 * hw - The pointer to the hw structure
8617 ****************************************************************************/
e4c780b1 8618static int32_t
d37ea5d5
AK		 8619e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout)
8620{
8621 union ich8_hws_flash_ctrl hsflctl;
8622 union ich8_hws_flash_status hsfsts;
8623 int32_t error = E1000_ERR_EEPROM;
8624 uint32_t i = 0;
8625
8626 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
8627 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8628 hsflctl.hsf_ctrl.flcgo = 1;
8629 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8630
8631 /* wait till FDONE bit is set to 1 */
8632 do {
8633 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8634 if (hsfsts.hsf_status.flcdone == 1)
8635 break;
8636 udelay(1);
8637 i++;
8638 } while (i < timeout);
8639 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) {
8640 error = E1000_SUCCESS;
8641 }
8642 return error;
8643}
8644
8645/******************************************************************************
8646 * Reads a byte or word from the NVM using the ICH8 flash access registers.
8647 *
8648 * hw - The pointer to the hw structure
8649 * index - The index of the byte or word to read.
8650 * size - Size of data to read, 1=byte 2=word
8651 * data - Pointer to the word to store the value read.
8652 *****************************************************************************/
e4c780b1 8653static int32_t
d37ea5d5
AK		 8654e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
8655 uint32_t size, uint16_t* data)
8656{
8657 union ich8_hws_flash_status hsfsts;
8658 union ich8_hws_flash_ctrl hsflctl;
8659 uint32_t flash_linear_address;
8660 uint32_t flash_data = 0;
8661 int32_t error = -E1000_ERR_EEPROM;
8662 int32_t count = 0;
8663
8664 DEBUGFUNC("e1000_read_ich8_data");
8665
8666 if (size < 1 || size > 2 || data == 0x0 ||
8667 index > ICH8_FLASH_LINEAR_ADDR_MASK)
8668 return error;
8669
8670 flash_linear_address = (ICH8_FLASH_LINEAR_ADDR_MASK & index) +
8671 hw->flash_base_addr;
8672
8673 do {
8674 udelay(1);
8675 /* Steps */
8676 error = e1000_ich8_cycle_init(hw);
8677 if (error != E1000_SUCCESS)
8678 break;
8679
8680 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8681 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8682 hsflctl.hsf_ctrl.fldbcount = size - 1;
8683 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_READ;
8684 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8685
8686 /* Write the last 24 bits of index into Flash Linear address field in
8687 * Flash Address */
8688 /* TODO: TBD maybe check the index against the size of flash */
8689
8690 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8691
8692 error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_COMMAND_TIMEOUT);
8693
8694 /* Check if FCERR is set to 1, if set to 1, clear it and try the whole
8695 * sequence a few more times, else read in (shift in) the Flash Data0,
8696 * the order is least significant byte first msb to lsb */
8697 if (error == E1000_SUCCESS) {
8698 flash_data = E1000_READ_ICH8_REG(hw, ICH8_FLASH_FDATA0);
8699 if (size == 1) {
8700 *data = (uint8_t)(flash_data & 0x000000FF);
8701 } else if (size == 2) {
8702 *data = (uint16_t)(flash_data & 0x0000FFFF);
8703 }
8704 break;
8705 } else {
8706 /* If we've gotten here, then things are probably completely hosed,
8707 * but if the error condition is detected, it won't hurt to give
8708 * it another try...ICH8_FLASH_CYCLE_REPEAT_COUNT times.
8709 */
8710 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8711 if (hsfsts.hsf_status.flcerr == 1) {
8712 /* Repeat for some time before giving up. */
8713 continue;
8714 } else if (hsfsts.hsf_status.flcdone == 0) {
8715 DEBUGOUT("Timeout error - flash cycle did not complete.");
8716 break;
8717 }
8718 }
8719 } while (count++ < ICH8_FLASH_CYCLE_REPEAT_COUNT);
8720
8721 return error;
8722}
8723
8724/******************************************************************************
8725 * Writes One /two bytes to the NVM using the ICH8 flash access registers.
8726 *
8727 * hw - The pointer to the hw structure
8728 * index - The index of the byte/word to read.
8729 * size - Size of data to read, 1=byte 2=word
8730 * data - The byte(s) to write to the NVM.
8731 *****************************************************************************/
e4c780b1 8732static int32_t
d37ea5d5
AK		 8733e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size,
8734 uint16_t data)
8735{
8736 union ich8_hws_flash_status hsfsts;
8737 union ich8_hws_flash_ctrl hsflctl;
8738 uint32_t flash_linear_address;
8739 uint32_t flash_data = 0;
8740 int32_t error = -E1000_ERR_EEPROM;
8741 int32_t count = 0;
8742
8743 DEBUGFUNC("e1000_write_ich8_data");
8744
8745 if (size < 1 || size > 2 || data > size * 0xff ||
8746 index > ICH8_FLASH_LINEAR_ADDR_MASK)
8747 return error;
8748
8749 flash_linear_address = (ICH8_FLASH_LINEAR_ADDR_MASK & index) +
8750 hw->flash_base_addr;
8751
8752 do {
8753 udelay(1);
8754 /* Steps */
8755 error = e1000_ich8_cycle_init(hw);
8756 if (error != E1000_SUCCESS)
8757 break;
8758
8759 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8760 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8761 hsflctl.hsf_ctrl.fldbcount = size -1;
8762 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_WRITE;
8763 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8764
8765 /* Write the last 24 bits of index into Flash Linear address field in
8766 * Flash Address */
8767 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8768
8769 if (size == 1)
8770 flash_data = (uint32_t)data & 0x00FF;
8771 else
8772 flash_data = (uint32_t)data;
8773
8774 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FDATA0, flash_data);
8775
8776 /* check if FCERR is set to 1 , if set to 1, clear it and try the whole
8777 * sequence a few more times else done */
8778 error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_COMMAND_TIMEOUT);
8779 if (error == E1000_SUCCESS) {
8780 break;
8781 } else {
8782 /* If we're here, then things are most likely completely hosed,
8783 * but if the error condition is detected, it won't hurt to give
8784 * it another try...ICH8_FLASH_CYCLE_REPEAT_COUNT times.
8785 */
8786 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8787 if (hsfsts.hsf_status.flcerr == 1) {
8788 /* Repeat for some time before giving up. */
8789 continue;
8790 } else if (hsfsts.hsf_status.flcdone == 0) {
8791 DEBUGOUT("Timeout error - flash cycle did not complete.");
8792 break;
8793 }
8794 }
8795 } while (count++ < ICH8_FLASH_CYCLE_REPEAT_COUNT);
8796
8797 return error;
8798}
8799
8800/******************************************************************************
8801 * Reads a single byte from the NVM using the ICH8 flash access registers.
8802 *
8803 * hw - pointer to e1000_hw structure
8804 * index - The index of the byte to read.
8805 * data - Pointer to a byte to store the value read.
8806 *****************************************************************************/
e4c780b1 8807static int32_t
d37ea5d5
AK		 8808e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t* data)
8809{
8810 int32_t status = E1000_SUCCESS;
8811 uint16_t word = 0;
8812
8813 status = e1000_read_ich8_data(hw, index, 1, &word);
8814 if (status == E1000_SUCCESS) {
8815 *data = (uint8_t)word;
8816 }
8817
8818 return status;
8819}
8820
8821/******************************************************************************
8822 * Writes a single byte to the NVM using the ICH8 flash access registers.
8823 * Performs verification by reading back the value and then going through
8824 * a retry algorithm before giving up.
8825 *
8826 * hw - pointer to e1000_hw structure
8827 * index - The index of the byte to write.
8828 * byte - The byte to write to the NVM.
8829 *****************************************************************************/
e4c780b1 8830static int32_t
d37ea5d5
AK		 8831e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte)
8832{
8833 int32_t error = E1000_SUCCESS;
8834 int32_t program_retries;
8835 uint8_t temp_byte;
8836
8837 e1000_write_ich8_byte(hw, index, byte);
8838 udelay(100);
8839
8840 for (program_retries = 0; program_retries < 100; program_retries++) {
8841 e1000_read_ich8_byte(hw, index, &temp_byte);
8842 if (temp_byte == byte)
8843 break;
8844 udelay(10);
8845 e1000_write_ich8_byte(hw, index, byte);
8846 udelay(100);
8847 }
8848 if (program_retries == 100)
8849 error = E1000_ERR_EEPROM;
8850
8851 return error;
8852}
8853
8854/******************************************************************************
8855 * Writes a single byte to the NVM using the ICH8 flash access registers.
8856 *
8857 * hw - pointer to e1000_hw structure
8858 * index - The index of the byte to read.
8859 * data - The byte to write to the NVM.
8860 *****************************************************************************/
e4c780b1 8861static int32_t
d37ea5d5
AK		 8862e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data)
8863{
8864 int32_t status = E1000_SUCCESS;
8865 uint16_t word = (uint16_t)data;
8866
8867 status = e1000_write_ich8_data(hw, index, 1, word);
8868
8869 return status;
8870}
8871
8872/******************************************************************************
8873 * Reads a word from the NVM using the ICH8 flash access registers.
8874 *
8875 * hw - pointer to e1000_hw structure
8876 * index - The starting byte index of the word to read.
8877 * data - Pointer to a word to store the value read.
8878 *****************************************************************************/
e4c780b1 8879static int32_t
d37ea5d5
AK		 8880e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data)
8881{
8882 int32_t status = E1000_SUCCESS;
8883 status = e1000_read_ich8_data(hw, index, 2, data);
8884 return status;
8885}
8886
8887/******************************************************************************
8888 * Writes a word to the NVM using the ICH8 flash access registers.
8889 *
8890 * hw - pointer to e1000_hw structure
8891 * index - The starting byte index of the word to read.
8892 * data - The word to write to the NVM.
8893 *****************************************************************************/
e4c780b1 8894#if 0
d37ea5d5
AK		 8895int32_t
8896e1000_write_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t data)
8897{
8898 int32_t status = E1000_SUCCESS;
8899 status = e1000_write_ich8_data(hw, index, 2, data);
8900 return status;
8901}
e4c780b1 8902#endif /* 0 */
d37ea5d5
AK		 8903
8904/******************************************************************************
8905 * Erases the bank specified. Each bank is a 4k block. Segments are 0 based.
8906 * segment N is 4096 * N + flash_reg_addr.
8907 *
8908 * hw - pointer to e1000_hw structure
8909 * segment - 0 for first segment, 1 for second segment, etc.
8910 *****************************************************************************/
e4c780b1 8911static int32_t
d37ea5d5
AK		 8912e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t segment)
8913{
8914 union ich8_hws_flash_status hsfsts;
8915 union ich8_hws_flash_ctrl hsflctl;
8916 uint32_t flash_linear_address;
8917 int32_t count = 0;
8918 int32_t error = E1000_ERR_EEPROM;
8919 int32_t iteration, seg_size;
8920 int32_t sector_size;
8921 int32_t j = 0;
8922 int32_t error_flag = 0;
8923
8924 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8925
8926 /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */
8927 /* 00: The Hw sector is 256 bytes, hence we need to erase 16
8928 * consecutive sectors. The start index for the nth Hw sector can be
8929 * calculated as = segment * 4096 + n * 256
8930 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
8931 * The start index for the nth Hw sector can be calculated
8932 * as = segment * 4096
8933 * 10: Error condition
8934 * 11: The Hw sector size is much bigger than the size asked to
8935 * erase...error condition */
8936 if (hsfsts.hsf_status.berasesz == 0x0) {
8937 /* Hw sector size 256 */
8938 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_256;
8939 iteration = ICH8_FLASH_SECTOR_SIZE / ICH8_FLASH_SEG_SIZE_256;
8940 } else if (hsfsts.hsf_status.berasesz == 0x1) {
8941 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_4K;
8942 iteration = 1;
8943 } else if (hsfsts.hsf_status.berasesz == 0x3) {
8944 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_64K;
8945 iteration = 1;
8946 } else {
8947 return error;
8948 }
8949
8950 for (j = 0; j < iteration ; j++) {
8951 do {
8952 count++;
8953 /* Steps */
8954 error = e1000_ich8_cycle_init(hw);
8955 if (error != E1000_SUCCESS) {
8956 error_flag = 1;
8957 break;
8958 }
8959
8960 /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash
8961 * Control */
8962 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8963 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_ERASE;
8964 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8965
8966 /* Write the last 24 bits of an index within the block into Flash
8967 * Linear address field in Flash Address. This probably needs to
8968 * be calculated here based off the on-chip segment size and the
8969 * software segment size assumed (4K) */
8970 /* TBD */
8971 flash_linear_address = segment * sector_size + j * seg_size;
8972 flash_linear_address &= ICH8_FLASH_LINEAR_ADDR_MASK;
8973 flash_linear_address += hw->flash_base_addr;
8974
8975 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8976
8977 error = e1000_ich8_flash_cycle(hw, 1000000);
8978 /* Check if FCERR is set to 1. If 1, clear it and try the whole
8979 * sequence a few more times else Done */
8980 if (error == E1000_SUCCESS) {
8981 break;
8982 } else {
8983 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8984 if (hsfsts.hsf_status.flcerr == 1) {
8985 /* repeat for some time before giving up */
8986 continue;
8987 } else if (hsfsts.hsf_status.flcdone == 0) {
8988 error_flag = 1;
8989 break;
8990 }
8991 }
8992 } while ((count < ICH8_FLASH_CYCLE_REPEAT_COUNT) && !error_flag);
8993 if (error_flag == 1)
8994 break;
8995 }
8996 if (error_flag != 1)
8997 error = E1000_SUCCESS;
8998 return error;
8999}
9000
9001/******************************************************************************
9002 *
9003 * Reverse duplex setting without breaking the link.
9004 *
9005 * hw: Struct containing variables accessed by shared code
9006 *
9007 *****************************************************************************/
e4c780b1 9008#if 0
d37ea5d5
AK		 9009int32_t
9010e1000_duplex_reversal(struct e1000_hw *hw)
9011{
9012 int32_t ret_val;
9013 uint16_t phy_data;
9014
9015 if (hw->phy_type != e1000_phy_igp_3)
9016 return E1000_SUCCESS;
9017
9018 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
9019 if (ret_val)
9020 return ret_val;
9021
9022 phy_data ^= MII_CR_FULL_DUPLEX;
9023
9024 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
9025 if (ret_val)
9026 return ret_val;
9027
9028 ret_val = e1000_read_phy_reg(hw, IGP3E1000_PHY_MISC_CTRL, &phy_data);
9029 if (ret_val)
9030 return ret_val;
9031
9032 phy_data |= IGP3_PHY_MISC_DUPLEX_MANUAL_SET;
9033 ret_val = e1000_write_phy_reg(hw, IGP3E1000_PHY_MISC_CTRL, phy_data);
9034
9035 return ret_val;
9036}
e4c780b1 9037#endif /* 0 */
d37ea5d5 9038
e4c780b1 9039static int32_t
d37ea5d5
AK		 9040e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
9041 uint32_t cnf_base_addr, uint32_t cnf_size)
9042{
9043 uint32_t ret_val = E1000_SUCCESS;
9044 uint16_t word_addr, reg_data, reg_addr;
9045 uint16_t i;
9046
9047 /* cnf_base_addr is in DWORD */
9048 word_addr = (uint16_t)(cnf_base_addr << 1);
9049
9050 /* cnf_size is returned in size of dwords */
9051 for (i = 0; i < cnf_size; i++) {
9052 ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, &reg_data);
9053 if (ret_val)
9054 return ret_val;
9055
9056 ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, &reg_addr);
9057 if (ret_val)
9058 return ret_val;
9059
9060 ret_val = e1000_get_software_flag(hw);
9061 if (ret_val != E1000_SUCCESS)
9062 return ret_val;
9063
9064 ret_val = e1000_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data);
9065
9066 e1000_release_software_flag(hw);
9067 }
9068
9069 return ret_val;
9070}
9071
9072
e4c780b1 9073static int32_t
d37ea5d5
AK		 9074e1000_init_lcd_from_nvm(struct e1000_hw *hw)
9075{
9076 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop;
9077
9078 if (hw->phy_type != e1000_phy_igp_3)
9079 return E1000_SUCCESS;
9080
9081 /* Check if SW needs configure the PHY */
9082 reg_data = E1000_READ_REG(hw, FEXTNVM);
9083 if (!(reg_data & FEXTNVM_SW_CONFIG))
9084 return E1000_SUCCESS;
9085
9086 /* Wait for basic configuration completes before proceeding*/
9087 loop = 0;
9088 do {
9089 reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE;
9090 udelay(100);
9091 loop++;
9092 } while ((!reg_data) && (loop < 50));
9093
9094 /* Clear the Init Done bit for the next init event */
9095 reg_data = E1000_READ_REG(hw, STATUS);
9096 reg_data &= ~E1000_STATUS_LAN_INIT_DONE;
9097 E1000_WRITE_REG(hw, STATUS, reg_data);
9098
9099 /* Make sure HW does not configure LCD from PHY extended configuration
9100 before SW configuration */
9101 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9102 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) {
9103 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE);
9104 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH;
9105 cnf_size >>= 16;
9106 if (cnf_size) {
9107 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9108 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER;
9109 /* cnf_base_addr is in DWORD */
9110 cnf_base_addr >>= 16;
9111
9112 /* Configure LCD from extended configuration region. */
9113 ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr,
9114 cnf_size);
9115 if (ret_val)
9116 return ret_val;
9117 }
9118 }
9119
9120 return E1000_SUCCESS;
9121}
9122
9123
2d7edb92 9124
kernel source for telekom puls (alcatel/mediatek)