Commit | Line | Data |
---|---|---|
a1365275 | 1 | /* |
41c340f0 | 2 | * Davicom DM9000 Fast Ethernet driver for Linux. |
a1365275 SH |
3 | * Copyright (C) 1997 Sten Wang |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
41c340f0 | 15 | * (C) Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved. |
9ef9ac51 | 16 | * |
41c340f0 BD |
17 | * Additional updates, Copyright: |
18 | * Ben Dooks <ben@simtec.co.uk> | |
19 | * Sascha Hauer <s.hauer@pengutronix.de> | |
a1365275 SH |
20 | */ |
21 | ||
22 | #include <linux/module.h> | |
23 | #include <linux/ioport.h> | |
24 | #include <linux/netdevice.h> | |
25 | #include <linux/etherdevice.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/skbuff.h> | |
a1365275 SH |
28 | #include <linux/spinlock.h> |
29 | #include <linux/crc32.h> | |
30 | #include <linux/mii.h> | |
7da99859 | 31 | #include <linux/ethtool.h> |
a1365275 SH |
32 | #include <linux/dm9000.h> |
33 | #include <linux/delay.h> | |
d052d1be | 34 | #include <linux/platform_device.h> |
4e4fc05a | 35 | #include <linux/irq.h> |
a1365275 SH |
36 | |
37 | #include <asm/delay.h> | |
38 | #include <asm/irq.h> | |
39 | #include <asm/io.h> | |
40 | ||
41 | #include "dm9000.h" | |
42 | ||
43 | /* Board/System/Debug information/definition ---------------- */ | |
44 | ||
45 | #define DM9000_PHY 0x40 /* PHY address 0x01 */ | |
46 | ||
59eae1fa BD |
47 | #define CARDNAME "dm9000" |
48 | #define DRV_VERSION "1.31" | |
a1365275 | 49 | |
f40d24d9 AL |
50 | #ifdef CONFIG_BLACKFIN |
51 | #define readsb insb | |
52 | #define readsw insw | |
53 | #define readsl insl | |
54 | #define writesb outsb | |
55 | #define writesw outsw | |
56 | #define writesl outsl | |
1a5f1c4f | 57 | #define DEFAULT_TRIGGER IRQF_TRIGGER_HIGH |
f40d24d9 | 58 | #else |
1a5f1c4f | 59 | #define DEFAULT_TRIGGER (0) |
f40d24d9 AL |
60 | #endif |
61 | ||
a1365275 SH |
62 | /* |
63 | * Transmit timeout, default 5 seconds. | |
64 | */ | |
65 | static int watchdog = 5000; | |
66 | module_param(watchdog, int, 0400); | |
67 | MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds"); | |
68 | ||
9a2f037c BD |
69 | /* DM9000 register address locking. |
70 | * | |
71 | * The DM9000 uses an address register to control where data written | |
72 | * to the data register goes. This means that the address register | |
73 | * must be preserved over interrupts or similar calls. | |
74 | * | |
75 | * During interrupt and other critical calls, a spinlock is used to | |
76 | * protect the system, but the calls themselves save the address | |
77 | * in the address register in case they are interrupting another | |
78 | * access to the device. | |
79 | * | |
80 | * For general accesses a lock is provided so that calls which are | |
81 | * allowed to sleep are serialised so that the address register does | |
82 | * not need to be saved. This lock also serves to serialise access | |
83 | * to the EEPROM and PHY access registers which are shared between | |
84 | * these two devices. | |
85 | */ | |
86 | ||
6d406b3c BD |
87 | /* The driver supports the original DM9000E, and now the two newer |
88 | * devices, DM9000A and DM9000B. | |
89 | */ | |
90 | ||
91 | enum dm9000_type { | |
92 | TYPE_DM9000E, /* original DM9000 */ | |
93 | TYPE_DM9000A, | |
94 | TYPE_DM9000B | |
95 | }; | |
96 | ||
a1365275 SH |
97 | /* Structure/enum declaration ------------------------------- */ |
98 | typedef struct board_info { | |
99 | ||
59eae1fa BD |
100 | void __iomem *io_addr; /* Register I/O base address */ |
101 | void __iomem *io_data; /* Data I/O address */ | |
102 | u16 irq; /* IRQ */ | |
a1365275 | 103 | |
59eae1fa BD |
104 | u16 tx_pkt_cnt; |
105 | u16 queue_pkt_len; | |
106 | u16 queue_start_addr; | |
107 | u16 dbug_cnt; | |
108 | u8 io_mode; /* 0:word, 2:byte */ | |
109 | u8 phy_addr; | |
110 | u8 imr_all; | |
111 | ||
112 | unsigned int flags; | |
113 | unsigned int in_suspend :1; | |
114 | int debug_level; | |
a1365275 | 115 | |
6d406b3c | 116 | enum dm9000_type type; |
5b2b4ff0 | 117 | |
a1365275 SH |
118 | void (*inblk)(void __iomem *port, void *data, int length); |
119 | void (*outblk)(void __iomem *port, void *data, int length); | |
120 | void (*dumpblk)(void __iomem *port, int length); | |
121 | ||
a76836f9 BD |
122 | struct device *dev; /* parent device */ |
123 | ||
a1365275 SH |
124 | struct resource *addr_res; /* resources found */ |
125 | struct resource *data_res; | |
126 | struct resource *addr_req; /* resources requested */ | |
127 | struct resource *data_req; | |
128 | struct resource *irq_res; | |
129 | ||
9a2f037c BD |
130 | struct mutex addr_lock; /* phy and eeprom access lock */ |
131 | ||
8f5bf5f2 BD |
132 | struct delayed_work phy_poll; |
133 | struct net_device *ndev; | |
134 | ||
59eae1fa | 135 | spinlock_t lock; |
a1365275 SH |
136 | |
137 | struct mii_if_info mii; | |
59eae1fa | 138 | u32 msg_enable; |
a1365275 SH |
139 | } board_info_t; |
140 | ||
5b2b4ff0 BD |
141 | /* debug code */ |
142 | ||
143 | #define dm9000_dbg(db, lev, msg...) do { \ | |
144 | if ((lev) < CONFIG_DM9000_DEBUGLEVEL && \ | |
145 | (lev) < db->debug_level) { \ | |
146 | dev_dbg(db->dev, msg); \ | |
147 | } \ | |
148 | } while (0) | |
149 | ||
7da99859 BD |
150 | static inline board_info_t *to_dm9000_board(struct net_device *dev) |
151 | { | |
152 | return dev->priv; | |
153 | } | |
154 | ||
a1365275 | 155 | /* function declaration ------------------------------------- */ |
a1365275 SH |
156 | static int dm9000_open(struct net_device *); |
157 | static int dm9000_start_xmit(struct sk_buff *, struct net_device *); | |
158 | static int dm9000_stop(struct net_device *); | |
a1365275 | 159 | |
a1365275 SH |
160 | static void dm9000_init_dm9000(struct net_device *); |
161 | ||
7d12e780 | 162 | static irqreturn_t dm9000_interrupt(int, void *); |
a1365275 | 163 | |
59eae1fa BD |
164 | static int dm9000_phy_read(struct net_device *dev, int phy, int reg); |
165 | static void dm9000_phy_write(struct net_device *dev, int phy, int reg, int v); | |
86c62fab | 166 | |
29d52e54 BD |
167 | static void dm9000_read_eeprom(board_info_t *, int addr, u8 *to); |
168 | static void dm9000_write_eeprom(board_info_t *, int addr, u8 *dp); | |
a1365275 SH |
169 | static void dm9000_rx(struct net_device *); |
170 | static void dm9000_hash_table(struct net_device *); | |
171 | ||
a1365275 SH |
172 | /* DM9000 network board routine ---------------------------- */ |
173 | ||
174 | static void | |
175 | dm9000_reset(board_info_t * db) | |
176 | { | |
a76836f9 BD |
177 | dev_dbg(db->dev, "resetting device\n"); |
178 | ||
a1365275 SH |
179 | /* RESET device */ |
180 | writeb(DM9000_NCR, db->io_addr); | |
181 | udelay(200); | |
182 | writeb(NCR_RST, db->io_data); | |
183 | udelay(200); | |
184 | } | |
185 | ||
186 | /* | |
187 | * Read a byte from I/O port | |
188 | */ | |
189 | static u8 | |
190 | ior(board_info_t * db, int reg) | |
191 | { | |
192 | writeb(reg, db->io_addr); | |
193 | return readb(db->io_data); | |
194 | } | |
195 | ||
196 | /* | |
197 | * Write a byte to I/O port | |
198 | */ | |
199 | ||
200 | static void | |
201 | iow(board_info_t * db, int reg, int value) | |
202 | { | |
203 | writeb(reg, db->io_addr); | |
204 | writeb(value, db->io_data); | |
205 | } | |
206 | ||
207 | /* routines for sending block to chip */ | |
208 | ||
209 | static void dm9000_outblk_8bit(void __iomem *reg, void *data, int count) | |
210 | { | |
211 | writesb(reg, data, count); | |
212 | } | |
213 | ||
214 | static void dm9000_outblk_16bit(void __iomem *reg, void *data, int count) | |
215 | { | |
216 | writesw(reg, data, (count+1) >> 1); | |
217 | } | |
218 | ||
219 | static void dm9000_outblk_32bit(void __iomem *reg, void *data, int count) | |
220 | { | |
221 | writesl(reg, data, (count+3) >> 2); | |
222 | } | |
223 | ||
224 | /* input block from chip to memory */ | |
225 | ||
226 | static void dm9000_inblk_8bit(void __iomem *reg, void *data, int count) | |
227 | { | |
5f6b5517 | 228 | readsb(reg, data, count); |
a1365275 SH |
229 | } |
230 | ||
231 | ||
232 | static void dm9000_inblk_16bit(void __iomem *reg, void *data, int count) | |
233 | { | |
234 | readsw(reg, data, (count+1) >> 1); | |
235 | } | |
236 | ||
237 | static void dm9000_inblk_32bit(void __iomem *reg, void *data, int count) | |
238 | { | |
239 | readsl(reg, data, (count+3) >> 2); | |
240 | } | |
241 | ||
242 | /* dump block from chip to null */ | |
243 | ||
244 | static void dm9000_dumpblk_8bit(void __iomem *reg, int count) | |
245 | { | |
246 | int i; | |
247 | int tmp; | |
248 | ||
249 | for (i = 0; i < count; i++) | |
250 | tmp = readb(reg); | |
251 | } | |
252 | ||
253 | static void dm9000_dumpblk_16bit(void __iomem *reg, int count) | |
254 | { | |
255 | int i; | |
256 | int tmp; | |
257 | ||
258 | count = (count + 1) >> 1; | |
259 | ||
260 | for (i = 0; i < count; i++) | |
261 | tmp = readw(reg); | |
262 | } | |
263 | ||
264 | static void dm9000_dumpblk_32bit(void __iomem *reg, int count) | |
265 | { | |
266 | int i; | |
267 | int tmp; | |
268 | ||
269 | count = (count + 3) >> 2; | |
270 | ||
271 | for (i = 0; i < count; i++) | |
272 | tmp = readl(reg); | |
273 | } | |
274 | ||
275 | /* dm9000_set_io | |
276 | * | |
277 | * select the specified set of io routines to use with the | |
278 | * device | |
279 | */ | |
280 | ||
281 | static void dm9000_set_io(struct board_info *db, int byte_width) | |
282 | { | |
283 | /* use the size of the data resource to work out what IO | |
284 | * routines we want to use | |
285 | */ | |
286 | ||
287 | switch (byte_width) { | |
288 | case 1: | |
289 | db->dumpblk = dm9000_dumpblk_8bit; | |
290 | db->outblk = dm9000_outblk_8bit; | |
291 | db->inblk = dm9000_inblk_8bit; | |
292 | break; | |
293 | ||
a1365275 SH |
294 | |
295 | case 3: | |
a76836f9 BD |
296 | dev_dbg(db->dev, ": 3 byte IO, falling back to 16bit\n"); |
297 | case 2: | |
a1365275 SH |
298 | db->dumpblk = dm9000_dumpblk_16bit; |
299 | db->outblk = dm9000_outblk_16bit; | |
300 | db->inblk = dm9000_inblk_16bit; | |
301 | break; | |
302 | ||
303 | case 4: | |
304 | default: | |
305 | db->dumpblk = dm9000_dumpblk_32bit; | |
306 | db->outblk = dm9000_outblk_32bit; | |
307 | db->inblk = dm9000_inblk_32bit; | |
308 | break; | |
309 | } | |
310 | } | |
311 | ||
8f5bf5f2 BD |
312 | static void dm9000_schedule_poll(board_info_t *db) |
313 | { | |
6d406b3c BD |
314 | if (db->type == TYPE_DM9000E) |
315 | schedule_delayed_work(&db->phy_poll, HZ * 2); | |
8f5bf5f2 | 316 | } |
a1365275 SH |
317 | |
318 | /* Our watchdog timed out. Called by the networking layer */ | |
319 | static void dm9000_timeout(struct net_device *dev) | |
320 | { | |
321 | board_info_t *db = (board_info_t *) dev->priv; | |
322 | u8 reg_save; | |
323 | unsigned long flags; | |
324 | ||
325 | /* Save previous register address */ | |
326 | reg_save = readb(db->io_addr); | |
9ef9ac51 | 327 | spin_lock_irqsave(&db->lock,flags); |
a1365275 SH |
328 | |
329 | netif_stop_queue(dev); | |
330 | dm9000_reset(db); | |
331 | dm9000_init_dm9000(dev); | |
332 | /* We can accept TX packets again */ | |
333 | dev->trans_start = jiffies; | |
334 | netif_wake_queue(dev); | |
335 | ||
336 | /* Restore previous register address */ | |
337 | writeb(reg_save, db->io_addr); | |
9ef9ac51 | 338 | spin_unlock_irqrestore(&db->lock,flags); |
a1365275 SH |
339 | } |
340 | ||
2fd0e33f KH |
341 | #ifdef CONFIG_NET_POLL_CONTROLLER |
342 | /* | |
343 | *Used by netconsole | |
344 | */ | |
345 | static void dm9000_poll_controller(struct net_device *dev) | |
346 | { | |
347 | disable_irq(dev->irq); | |
28431146 | 348 | dm9000_interrupt(dev->irq,dev); |
2fd0e33f KH |
349 | enable_irq(dev->irq); |
350 | } | |
351 | #endif | |
a1365275 | 352 | |
f42d8aea BD |
353 | static int dm9000_ioctl(struct net_device *dev, struct ifreq *req, int cmd) |
354 | { | |
355 | board_info_t *dm = to_dm9000_board(dev); | |
356 | ||
357 | if (!netif_running(dev)) | |
358 | return -EINVAL; | |
359 | ||
360 | return generic_mii_ioctl(&dm->mii, if_mii(req), cmd, NULL); | |
361 | } | |
362 | ||
7da99859 BD |
363 | /* ethtool ops */ |
364 | ||
365 | static void dm9000_get_drvinfo(struct net_device *dev, | |
366 | struct ethtool_drvinfo *info) | |
367 | { | |
368 | board_info_t *dm = to_dm9000_board(dev); | |
369 | ||
370 | strcpy(info->driver, CARDNAME); | |
371 | strcpy(info->version, DRV_VERSION); | |
372 | strcpy(info->bus_info, to_platform_device(dm->dev)->name); | |
373 | } | |
374 | ||
e662ee02 BD |
375 | static u32 dm9000_get_msglevel(struct net_device *dev) |
376 | { | |
377 | board_info_t *dm = to_dm9000_board(dev); | |
378 | ||
379 | return dm->msg_enable; | |
380 | } | |
381 | ||
382 | static void dm9000_set_msglevel(struct net_device *dev, u32 value) | |
383 | { | |
384 | board_info_t *dm = to_dm9000_board(dev); | |
385 | ||
386 | dm->msg_enable = value; | |
387 | } | |
388 | ||
7da99859 BD |
389 | static int dm9000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
390 | { | |
391 | board_info_t *dm = to_dm9000_board(dev); | |
7da99859 | 392 | |
7da99859 | 393 | mii_ethtool_gset(&dm->mii, cmd); |
7da99859 BD |
394 | return 0; |
395 | } | |
396 | ||
397 | static int dm9000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
398 | { | |
399 | board_info_t *dm = to_dm9000_board(dev); | |
7da99859 | 400 | |
9a2f037c | 401 | return mii_ethtool_sset(&dm->mii, cmd); |
7da99859 BD |
402 | } |
403 | ||
404 | static int dm9000_nway_reset(struct net_device *dev) | |
405 | { | |
406 | board_info_t *dm = to_dm9000_board(dev); | |
407 | return mii_nway_restart(&dm->mii); | |
408 | } | |
409 | ||
410 | static u32 dm9000_get_link(struct net_device *dev) | |
411 | { | |
412 | board_info_t *dm = to_dm9000_board(dev); | |
413 | return mii_link_ok(&dm->mii); | |
414 | } | |
415 | ||
29d52e54 BD |
416 | #define DM_EEPROM_MAGIC (0x444D394B) |
417 | ||
418 | static int dm9000_get_eeprom_len(struct net_device *dev) | |
419 | { | |
420 | return 128; | |
421 | } | |
422 | ||
423 | static int dm9000_get_eeprom(struct net_device *dev, | |
424 | struct ethtool_eeprom *ee, u8 *data) | |
425 | { | |
426 | board_info_t *dm = to_dm9000_board(dev); | |
427 | int offset = ee->offset; | |
428 | int len = ee->len; | |
429 | int i; | |
430 | ||
431 | /* EEPROM access is aligned to two bytes */ | |
432 | ||
433 | if ((len & 1) != 0 || (offset & 1) != 0) | |
434 | return -EINVAL; | |
435 | ||
bb44fb70 BD |
436 | if (dm->flags & DM9000_PLATF_NO_EEPROM) |
437 | return -ENOENT; | |
438 | ||
29d52e54 BD |
439 | ee->magic = DM_EEPROM_MAGIC; |
440 | ||
441 | for (i = 0; i < len; i += 2) | |
442 | dm9000_read_eeprom(dm, (offset + i) / 2, data + i); | |
443 | ||
444 | return 0; | |
445 | } | |
446 | ||
447 | static int dm9000_set_eeprom(struct net_device *dev, | |
448 | struct ethtool_eeprom *ee, u8 *data) | |
449 | { | |
450 | board_info_t *dm = to_dm9000_board(dev); | |
451 | int offset = ee->offset; | |
452 | int len = ee->len; | |
453 | int i; | |
454 | ||
455 | /* EEPROM access is aligned to two bytes */ | |
456 | ||
457 | if ((len & 1) != 0 || (offset & 1) != 0) | |
458 | return -EINVAL; | |
459 | ||
bb44fb70 BD |
460 | if (dm->flags & DM9000_PLATF_NO_EEPROM) |
461 | return -ENOENT; | |
462 | ||
29d52e54 BD |
463 | if (ee->magic != DM_EEPROM_MAGIC) |
464 | return -EINVAL; | |
465 | ||
466 | for (i = 0; i < len; i += 2) | |
467 | dm9000_write_eeprom(dm, (offset + i) / 2, data + i); | |
468 | ||
469 | return 0; | |
470 | } | |
471 | ||
7da99859 BD |
472 | static const struct ethtool_ops dm9000_ethtool_ops = { |
473 | .get_drvinfo = dm9000_get_drvinfo, | |
474 | .get_settings = dm9000_get_settings, | |
475 | .set_settings = dm9000_set_settings, | |
e662ee02 BD |
476 | .get_msglevel = dm9000_get_msglevel, |
477 | .set_msglevel = dm9000_set_msglevel, | |
7da99859 BD |
478 | .nway_reset = dm9000_nway_reset, |
479 | .get_link = dm9000_get_link, | |
29d52e54 BD |
480 | .get_eeprom_len = dm9000_get_eeprom_len, |
481 | .get_eeprom = dm9000_get_eeprom, | |
482 | .set_eeprom = dm9000_set_eeprom, | |
7da99859 BD |
483 | }; |
484 | ||
8f5bf5f2 BD |
485 | static void |
486 | dm9000_poll_work(struct work_struct *w) | |
487 | { | |
488 | struct delayed_work *dw = container_of(w, struct delayed_work, work); | |
489 | board_info_t *db = container_of(dw, board_info_t, phy_poll); | |
490 | ||
491 | mii_check_media(&db->mii, netif_msg_link(db), 0); | |
492 | ||
493 | if (netif_running(db->ndev)) | |
494 | dm9000_schedule_poll(db); | |
495 | } | |
7da99859 | 496 | |
a1365275 SH |
497 | /* dm9000_release_board |
498 | * | |
499 | * release a board, and any mapped resources | |
500 | */ | |
501 | ||
502 | static void | |
503 | dm9000_release_board(struct platform_device *pdev, struct board_info *db) | |
504 | { | |
a1365275 SH |
505 | /* unmap our resources */ |
506 | ||
507 | iounmap(db->io_addr); | |
508 | iounmap(db->io_data); | |
509 | ||
510 | /* release the resources */ | |
511 | ||
9088fa4f BD |
512 | release_resource(db->data_req); |
513 | kfree(db->data_req); | |
a1365275 | 514 | |
9088fa4f BD |
515 | release_resource(db->addr_req); |
516 | kfree(db->addr_req); | |
a1365275 SH |
517 | } |
518 | ||
6d406b3c BD |
519 | static unsigned char dm9000_type_to_char(enum dm9000_type type) |
520 | { | |
521 | switch (type) { | |
522 | case TYPE_DM9000E: return 'e'; | |
523 | case TYPE_DM9000A: return 'a'; | |
524 | case TYPE_DM9000B: return 'b'; | |
525 | } | |
526 | ||
527 | return '?'; | |
528 | } | |
529 | ||
a1365275 SH |
530 | #define res_size(_r) (((_r)->end - (_r)->start) + 1) |
531 | ||
532 | /* | |
533 | * Search DM9000 board, allocate space and register it | |
534 | */ | |
e21fd4f0 | 535 | static int __devinit |
3ae5eaec | 536 | dm9000_probe(struct platform_device *pdev) |
a1365275 | 537 | { |
a1365275 SH |
538 | struct dm9000_plat_data *pdata = pdev->dev.platform_data; |
539 | struct board_info *db; /* Point a board information structure */ | |
540 | struct net_device *ndev; | |
179c743f | 541 | const unsigned char *mac_src; |
a1365275 SH |
542 | int ret = 0; |
543 | int iosize; | |
544 | int i; | |
545 | u32 id_val; | |
546 | ||
a1365275 SH |
547 | /* Init network device */ |
548 | ndev = alloc_etherdev(sizeof (struct board_info)); | |
549 | if (!ndev) { | |
a76836f9 | 550 | dev_err(&pdev->dev, "could not allocate device.\n"); |
a1365275 SH |
551 | return -ENOMEM; |
552 | } | |
553 | ||
3ae5eaec | 554 | SET_NETDEV_DEV(ndev, &pdev->dev); |
a1365275 | 555 | |
37d5dca6 | 556 | dev_dbg(&pdev->dev, "dm9000_probe()\n"); |
a1365275 SH |
557 | |
558 | /* setup board info structure */ | |
559 | db = (struct board_info *) ndev->priv; | |
560 | memset(db, 0, sizeof (*db)); | |
561 | ||
a76836f9 | 562 | db->dev = &pdev->dev; |
8f5bf5f2 | 563 | db->ndev = ndev; |
a76836f9 | 564 | |
9ef9ac51 | 565 | spin_lock_init(&db->lock); |
9a2f037c | 566 | mutex_init(&db->addr_lock); |
9ef9ac51 | 567 | |
8f5bf5f2 BD |
568 | INIT_DELAYED_WORK(&db->phy_poll, dm9000_poll_work); |
569 | ||
08c3f57c LP |
570 | db->addr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
571 | db->data_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
572 | db->irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
573 | ||
574 | if (db->addr_res == NULL || db->data_res == NULL || | |
575 | db->irq_res == NULL) { | |
576 | dev_err(db->dev, "insufficient resources\n"); | |
577 | ret = -ENOENT; | |
578 | goto out; | |
579 | } | |
580 | ||
581 | iosize = res_size(db->addr_res); | |
582 | db->addr_req = request_mem_region(db->addr_res->start, iosize, | |
583 | pdev->name); | |
584 | ||
585 | if (db->addr_req == NULL) { | |
586 | dev_err(db->dev, "cannot claim address reg area\n"); | |
587 | ret = -EIO; | |
588 | goto out; | |
589 | } | |
590 | ||
591 | db->io_addr = ioremap(db->addr_res->start, iosize); | |
592 | ||
593 | if (db->io_addr == NULL) { | |
594 | dev_err(db->dev, "failed to ioremap address reg\n"); | |
595 | ret = -EINVAL; | |
596 | goto out; | |
597 | } | |
598 | ||
599 | iosize = res_size(db->data_res); | |
600 | db->data_req = request_mem_region(db->data_res->start, iosize, | |
601 | pdev->name); | |
602 | ||
603 | if (db->data_req == NULL) { | |
604 | dev_err(db->dev, "cannot claim data reg area\n"); | |
605 | ret = -EIO; | |
606 | goto out; | |
607 | } | |
608 | ||
609 | db->io_data = ioremap(db->data_res->start, iosize); | |
610 | ||
611 | if (db->io_data == NULL) { | |
612 | dev_err(db->dev, "failed to ioremap data reg\n"); | |
613 | ret = -EINVAL; | |
614 | goto out; | |
615 | } | |
616 | ||
617 | /* fill in parameters for net-dev structure */ | |
618 | ndev->base_addr = (unsigned long)db->io_addr; | |
619 | ndev->irq = db->irq_res->start; | |
620 | ||
621 | /* ensure at least we have a default set of IO routines */ | |
622 | dm9000_set_io(db, iosize); | |
623 | ||
a1365275 SH |
624 | /* check to see if anything is being over-ridden */ |
625 | if (pdata != NULL) { | |
626 | /* check to see if the driver wants to over-ride the | |
627 | * default IO width */ | |
628 | ||
629 | if (pdata->flags & DM9000_PLATF_8BITONLY) | |
630 | dm9000_set_io(db, 1); | |
631 | ||
632 | if (pdata->flags & DM9000_PLATF_16BITONLY) | |
633 | dm9000_set_io(db, 2); | |
634 | ||
635 | if (pdata->flags & DM9000_PLATF_32BITONLY) | |
636 | dm9000_set_io(db, 4); | |
637 | ||
638 | /* check to see if there are any IO routine | |
639 | * over-rides */ | |
640 | ||
641 | if (pdata->inblk != NULL) | |
642 | db->inblk = pdata->inblk; | |
643 | ||
644 | if (pdata->outblk != NULL) | |
645 | db->outblk = pdata->outblk; | |
646 | ||
647 | if (pdata->dumpblk != NULL) | |
648 | db->dumpblk = pdata->dumpblk; | |
33ba5091 BD |
649 | |
650 | db->flags = pdata->flags; | |
a1365275 SH |
651 | } |
652 | ||
653 | dm9000_reset(db); | |
654 | ||
59eae1fa | 655 | /* try multiple times, DM9000 sometimes gets the read wrong */ |
513b6bee | 656 | for (i = 0; i < 8; i++) { |
a1365275 SH |
657 | id_val = ior(db, DM9000_VIDL); |
658 | id_val |= (u32)ior(db, DM9000_VIDH) << 8; | |
659 | id_val |= (u32)ior(db, DM9000_PIDL) << 16; | |
660 | id_val |= (u32)ior(db, DM9000_PIDH) << 24; | |
661 | ||
662 | if (id_val == DM9000_ID) | |
663 | break; | |
a76836f9 | 664 | dev_err(db->dev, "read wrong id 0x%08x\n", id_val); |
a1365275 SH |
665 | } |
666 | ||
667 | if (id_val != DM9000_ID) { | |
a76836f9 | 668 | dev_err(db->dev, "wrong id: 0x%08x\n", id_val); |
418d6f87 MR |
669 | ret = -ENODEV; |
670 | goto out; | |
a1365275 SH |
671 | } |
672 | ||
6d406b3c BD |
673 | /* Identify what type of DM9000 we are working on */ |
674 | ||
675 | id_val = ior(db, DM9000_CHIPR); | |
676 | dev_dbg(db->dev, "dm9000 revision 0x%02x\n", id_val); | |
677 | ||
678 | switch (id_val) { | |
679 | case CHIPR_DM9000A: | |
680 | db->type = TYPE_DM9000A; | |
681 | break; | |
682 | case CHIPR_DM9000B: | |
683 | db->type = TYPE_DM9000B; | |
684 | break; | |
685 | default: | |
686 | dev_dbg(db->dev, "ID %02x => defaulting to DM9000E\n", id_val); | |
687 | db->type = TYPE_DM9000E; | |
688 | } | |
689 | ||
a1365275 SH |
690 | /* from this point we assume that we have found a DM9000 */ |
691 | ||
692 | /* driver system function */ | |
693 | ether_setup(ndev); | |
694 | ||
695 | ndev->open = &dm9000_open; | |
696 | ndev->hard_start_xmit = &dm9000_start_xmit; | |
697 | ndev->tx_timeout = &dm9000_timeout; | |
698 | ndev->watchdog_timeo = msecs_to_jiffies(watchdog); | |
699 | ndev->stop = &dm9000_stop; | |
a1365275 | 700 | ndev->set_multicast_list = &dm9000_hash_table; |
7da99859 | 701 | ndev->ethtool_ops = &dm9000_ethtool_ops; |
f42d8aea | 702 | ndev->do_ioctl = &dm9000_ioctl; |
7da99859 | 703 | |
2fd0e33f KH |
704 | #ifdef CONFIG_NET_POLL_CONTROLLER |
705 | ndev->poll_controller = &dm9000_poll_controller; | |
706 | #endif | |
a1365275 | 707 | |
a1365275 SH |
708 | db->msg_enable = NETIF_MSG_LINK; |
709 | db->mii.phy_id_mask = 0x1f; | |
710 | db->mii.reg_num_mask = 0x1f; | |
711 | db->mii.force_media = 0; | |
712 | db->mii.full_duplex = 0; | |
713 | db->mii.dev = ndev; | |
714 | db->mii.mdio_read = dm9000_phy_read; | |
715 | db->mii.mdio_write = dm9000_phy_write; | |
716 | ||
179c743f BD |
717 | mac_src = "eeprom"; |
718 | ||
86c62fab BD |
719 | /* try reading the node address from the attached EEPROM */ |
720 | for (i = 0; i < 6; i += 2) | |
721 | dm9000_read_eeprom(db, i / 2, ndev->dev_addr+i); | |
a1365275 | 722 | |
5b55dda6 BD |
723 | if (!is_valid_ether_addr(ndev->dev_addr)) { |
724 | /* try reading from mac */ | |
7d2e3cb7 | 725 | |
179c743f | 726 | mac_src = "chip"; |
5b55dda6 BD |
727 | for (i = 0; i < 6; i++) |
728 | ndev->dev_addr[i] = ior(db, i+DM9000_PAR); | |
729 | } | |
730 | ||
a1365275 | 731 | if (!is_valid_ether_addr(ndev->dev_addr)) |
a76836f9 BD |
732 | dev_warn(db->dev, "%s: Invalid ethernet MAC address. Please " |
733 | "set using ifconfig\n", ndev->name); | |
a1365275 | 734 | |
3ae5eaec | 735 | platform_set_drvdata(pdev, ndev); |
a1365275 SH |
736 | ret = register_netdev(ndev); |
737 | ||
738 | if (ret == 0) { | |
0795af57 | 739 | DECLARE_MAC_BUF(mac); |
6d406b3c BD |
740 | printk(KERN_INFO "%s: dm9000%c at %p,%p IRQ %d MAC: %s (%s)\n", |
741 | ndev->name, dm9000_type_to_char(db->type), | |
742 | db->io_addr, db->io_data, ndev->irq, | |
179c743f | 743 | print_mac(mac, ndev->dev_addr), mac_src); |
a1365275 SH |
744 | } |
745 | return 0; | |
746 | ||
418d6f87 | 747 | out: |
a76836f9 | 748 | dev_err(db->dev, "not found (%d).\n", ret); |
a1365275 SH |
749 | |
750 | dm9000_release_board(pdev, db); | |
9fd9f9b6 | 751 | free_netdev(ndev); |
a1365275 SH |
752 | |
753 | return ret; | |
754 | } | |
755 | ||
756 | /* | |
757 | * Open the interface. | |
758 | * The interface is opened whenever "ifconfig" actives it. | |
759 | */ | |
760 | static int | |
761 | dm9000_open(struct net_device *dev) | |
762 | { | |
59eae1fa | 763 | board_info_t *db = dev->priv; |
1a5f1c4f | 764 | unsigned long irqflags = db->irq_res->flags & IRQF_TRIGGER_MASK; |
a1365275 | 765 | |
c991d168 BD |
766 | if (netif_msg_ifup(db)) |
767 | dev_dbg(db->dev, "enabling %s\n", dev->name); | |
a1365275 | 768 | |
1a5f1c4f BD |
769 | /* If there is no IRQ type specified, default to something that |
770 | * may work, and tell the user that this is a problem */ | |
771 | ||
772 | if (irqflags == IRQF_TRIGGER_NONE) { | |
773 | dev_warn(db->dev, "WARNING: no IRQ resource flags set.\n"); | |
774 | irqflags = DEFAULT_TRIGGER; | |
775 | } | |
7d2e3cb7 | 776 | |
1a5f1c4f BD |
777 | irqflags |= IRQF_SHARED; |
778 | ||
779 | if (request_irq(dev->irq, &dm9000_interrupt, irqflags, dev->name, dev)) | |
a1365275 SH |
780 | return -EAGAIN; |
781 | ||
782 | /* Initialize DM9000 board */ | |
783 | dm9000_reset(db); | |
784 | dm9000_init_dm9000(dev); | |
785 | ||
786 | /* Init driver variable */ | |
787 | db->dbug_cnt = 0; | |
788 | ||
a1365275 SH |
789 | mii_check_media(&db->mii, netif_msg_link(db), 1); |
790 | netif_start_queue(dev); | |
8f5bf5f2 BD |
791 | |
792 | dm9000_schedule_poll(db); | |
a1365275 SH |
793 | |
794 | return 0; | |
795 | } | |
796 | ||
797 | /* | |
798 | * Initilize dm9000 board | |
799 | */ | |
800 | static void | |
801 | dm9000_init_dm9000(struct net_device *dev) | |
802 | { | |
59eae1fa | 803 | board_info_t *db = dev->priv; |
6d406b3c | 804 | unsigned int imr; |
a1365275 | 805 | |
5b2b4ff0 | 806 | dm9000_dbg(db, 1, "entering %s\n", __func__); |
a1365275 SH |
807 | |
808 | /* I/O mode */ | |
809 | db->io_mode = ior(db, DM9000_ISR) >> 6; /* ISR bit7:6 keeps I/O mode */ | |
810 | ||
811 | /* GPIO0 on pre-activate PHY */ | |
812 | iow(db, DM9000_GPR, 0); /* REG_1F bit0 activate phyxcer */ | |
813 | iow(db, DM9000_GPCR, GPCR_GEP_CNTL); /* Let GPIO0 output */ | |
814 | iow(db, DM9000_GPR, 0); /* Enable PHY */ | |
815 | ||
33ba5091 BD |
816 | if (db->flags & DM9000_PLATF_EXT_PHY) |
817 | iow(db, DM9000_NCR, NCR_EXT_PHY); | |
818 | ||
a1365275 SH |
819 | /* Program operating register */ |
820 | iow(db, DM9000_TCR, 0); /* TX Polling clear */ | |
821 | iow(db, DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */ | |
822 | iow(db, DM9000_FCR, 0xff); /* Flow Control */ | |
823 | iow(db, DM9000_SMCR, 0); /* Special Mode */ | |
824 | /* clear TX status */ | |
825 | iow(db, DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); | |
826 | iow(db, DM9000_ISR, ISR_CLR_STATUS); /* Clear interrupt status */ | |
827 | ||
828 | /* Set address filter table */ | |
829 | dm9000_hash_table(dev); | |
830 | ||
6d406b3c BD |
831 | imr = IMR_PAR | IMR_PTM | IMR_PRM; |
832 | if (db->type != TYPE_DM9000E) | |
833 | imr |= IMR_LNKCHNG; | |
834 | ||
835 | db->imr_all = imr; | |
836 | ||
a1365275 | 837 | /* Enable TX/RX interrupt mask */ |
6d406b3c | 838 | iow(db, DM9000_IMR, imr); |
a1365275 SH |
839 | |
840 | /* Init Driver variable */ | |
841 | db->tx_pkt_cnt = 0; | |
842 | db->queue_pkt_len = 0; | |
843 | dev->trans_start = 0; | |
a1365275 SH |
844 | } |
845 | ||
846 | /* | |
847 | * Hardware start transmission. | |
848 | * Send a packet to media from the upper layer. | |
849 | */ | |
850 | static int | |
851 | dm9000_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
852 | { | |
c46ac946 | 853 | unsigned long flags; |
59eae1fa | 854 | board_info_t *db = dev->priv; |
a1365275 | 855 | |
5b2b4ff0 | 856 | dm9000_dbg(db, 3, "%s:\n", __func__); |
a1365275 SH |
857 | |
858 | if (db->tx_pkt_cnt > 1) | |
859 | return 1; | |
860 | ||
c46ac946 | 861 | spin_lock_irqsave(&db->lock, flags); |
a1365275 SH |
862 | |
863 | /* Move data to DM9000 TX RAM */ | |
864 | writeb(DM9000_MWCMD, db->io_addr); | |
865 | ||
866 | (db->outblk)(db->io_data, skb->data, skb->len); | |
09f75cd7 | 867 | dev->stats.tx_bytes += skb->len; |
a1365275 | 868 | |
c46ac946 | 869 | db->tx_pkt_cnt++; |
a1365275 | 870 | /* TX control: First packet immediately send, second packet queue */ |
c46ac946 | 871 | if (db->tx_pkt_cnt == 1) { |
a1365275 | 872 | /* Set TX length to DM9000 */ |
073d3f46 BD |
873 | iow(db, DM9000_TXPLL, skb->len); |
874 | iow(db, DM9000_TXPLH, skb->len >> 8); | |
a1365275 SH |
875 | |
876 | /* Issue TX polling command */ | |
877 | iow(db, DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */ | |
878 | ||
879 | dev->trans_start = jiffies; /* save the time stamp */ | |
a1365275 SH |
880 | } else { |
881 | /* Second packet */ | |
a1365275 | 882 | db->queue_pkt_len = skb->len; |
c46ac946 | 883 | netif_stop_queue(dev); |
a1365275 SH |
884 | } |
885 | ||
c46ac946 FW |
886 | spin_unlock_irqrestore(&db->lock, flags); |
887 | ||
a1365275 SH |
888 | /* free this SKB */ |
889 | dev_kfree_skb(skb); | |
890 | ||
a1365275 SH |
891 | return 0; |
892 | } | |
893 | ||
894 | static void | |
895 | dm9000_shutdown(struct net_device *dev) | |
896 | { | |
59eae1fa | 897 | board_info_t *db = dev->priv; |
a1365275 SH |
898 | |
899 | /* RESET device */ | |
900 | dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET); /* PHY RESET */ | |
901 | iow(db, DM9000_GPR, 0x01); /* Power-Down PHY */ | |
902 | iow(db, DM9000_IMR, IMR_PAR); /* Disable all interrupt */ | |
903 | iow(db, DM9000_RCR, 0x00); /* Disable RX */ | |
904 | } | |
905 | ||
906 | /* | |
907 | * Stop the interface. | |
908 | * The interface is stopped when it is brought. | |
909 | */ | |
910 | static int | |
911 | dm9000_stop(struct net_device *ndev) | |
912 | { | |
59eae1fa | 913 | board_info_t *db = ndev->priv; |
a1365275 | 914 | |
c991d168 BD |
915 | if (netif_msg_ifdown(db)) |
916 | dev_dbg(db->dev, "shutting down %s\n", ndev->name); | |
a1365275 | 917 | |
5bceeda3 | 918 | cancel_delayed_work_sync(&db->phy_poll); |
8f5bf5f2 | 919 | |
a1365275 SH |
920 | netif_stop_queue(ndev); |
921 | netif_carrier_off(ndev); | |
922 | ||
923 | /* free interrupt */ | |
924 | free_irq(ndev->irq, ndev); | |
925 | ||
926 | dm9000_shutdown(ndev); | |
927 | ||
928 | return 0; | |
929 | } | |
930 | ||
931 | /* | |
932 | * DM9000 interrupt handler | |
933 | * receive the packet to upper layer, free the transmitted packet | |
934 | */ | |
935 | ||
5d22a312 | 936 | static void |
a1365275 SH |
937 | dm9000_tx_done(struct net_device *dev, board_info_t * db) |
938 | { | |
939 | int tx_status = ior(db, DM9000_NSR); /* Got TX status */ | |
940 | ||
941 | if (tx_status & (NSR_TX2END | NSR_TX1END)) { | |
942 | /* One packet sent complete */ | |
943 | db->tx_pkt_cnt--; | |
09f75cd7 | 944 | dev->stats.tx_packets++; |
a1365275 | 945 | |
c991d168 BD |
946 | if (netif_msg_tx_done(db)) |
947 | dev_dbg(db->dev, "tx done, NSR %02x\n", tx_status); | |
948 | ||
a1365275 SH |
949 | /* Queue packet check & send */ |
950 | if (db->tx_pkt_cnt > 0) { | |
073d3f46 BD |
951 | iow(db, DM9000_TXPLL, db->queue_pkt_len); |
952 | iow(db, DM9000_TXPLH, db->queue_pkt_len >> 8); | |
a1365275 SH |
953 | iow(db, DM9000_TCR, TCR_TXREQ); |
954 | dev->trans_start = jiffies; | |
955 | } | |
956 | netif_wake_queue(dev); | |
957 | } | |
958 | } | |
959 | ||
960 | static irqreturn_t | |
7d12e780 | 961 | dm9000_interrupt(int irq, void *dev_id) |
a1365275 SH |
962 | { |
963 | struct net_device *dev = dev_id; | |
59eae1fa | 964 | board_info_t *db = dev->priv; |
a1365275 SH |
965 | int int_status; |
966 | u8 reg_save; | |
967 | ||
5b2b4ff0 | 968 | dm9000_dbg(db, 3, "entering %s\n", __func__); |
a1365275 SH |
969 | |
970 | /* A real interrupt coming */ | |
5b2b4ff0 | 971 | |
a1365275 SH |
972 | spin_lock(&db->lock); |
973 | ||
974 | /* Save previous register address */ | |
975 | reg_save = readb(db->io_addr); | |
976 | ||
977 | /* Disable all interrupts */ | |
978 | iow(db, DM9000_IMR, IMR_PAR); | |
979 | ||
980 | /* Got DM9000 interrupt status */ | |
981 | int_status = ior(db, DM9000_ISR); /* Got ISR */ | |
982 | iow(db, DM9000_ISR, int_status); /* Clear ISR status */ | |
983 | ||
c991d168 BD |
984 | if (netif_msg_intr(db)) |
985 | dev_dbg(db->dev, "interrupt status %02x\n", int_status); | |
986 | ||
a1365275 SH |
987 | /* Received the coming packet */ |
988 | if (int_status & ISR_PRS) | |
989 | dm9000_rx(dev); | |
990 | ||
991 | /* Trnasmit Interrupt check */ | |
992 | if (int_status & ISR_PTS) | |
993 | dm9000_tx_done(dev, db); | |
994 | ||
6d406b3c BD |
995 | if (db->type != TYPE_DM9000E) { |
996 | if (int_status & ISR_LNKCHNG) { | |
997 | /* fire a link-change request */ | |
998 | schedule_delayed_work(&db->phy_poll, 1); | |
999 | } | |
1000 | } | |
1001 | ||
a1365275 | 1002 | /* Re-enable interrupt mask */ |
6d406b3c | 1003 | iow(db, DM9000_IMR, db->imr_all); |
a1365275 SH |
1004 | |
1005 | /* Restore previous register address */ | |
1006 | writeb(reg_save, db->io_addr); | |
1007 | ||
1008 | spin_unlock(&db->lock); | |
1009 | ||
1010 | return IRQ_HANDLED; | |
1011 | } | |
1012 | ||
a1365275 | 1013 | struct dm9000_rxhdr { |
93116573 BD |
1014 | u8 RxPktReady; |
1015 | u8 RxStatus; | |
8b9fc8ae | 1016 | __le16 RxLen; |
a1365275 SH |
1017 | } __attribute__((__packed__)); |
1018 | ||
1019 | /* | |
1020 | * Received a packet and pass to upper layer | |
1021 | */ | |
1022 | static void | |
1023 | dm9000_rx(struct net_device *dev) | |
1024 | { | |
1025 | board_info_t *db = (board_info_t *) dev->priv; | |
1026 | struct dm9000_rxhdr rxhdr; | |
1027 | struct sk_buff *skb; | |
1028 | u8 rxbyte, *rdptr; | |
6478fac6 | 1029 | bool GoodPacket; |
a1365275 SH |
1030 | int RxLen; |
1031 | ||
1032 | /* Check packet ready or not */ | |
1033 | do { | |
1034 | ior(db, DM9000_MRCMDX); /* Dummy read */ | |
1035 | ||
1036 | /* Get most updated data */ | |
1037 | rxbyte = readb(db->io_data); | |
1038 | ||
1039 | /* Status check: this byte must be 0 or 1 */ | |
1040 | if (rxbyte > DM9000_PKT_RDY) { | |
a76836f9 | 1041 | dev_warn(db->dev, "status check fail: %d\n", rxbyte); |
a1365275 SH |
1042 | iow(db, DM9000_RCR, 0x00); /* Stop Device */ |
1043 | iow(db, DM9000_ISR, IMR_PAR); /* Stop INT request */ | |
1044 | return; | |
1045 | } | |
1046 | ||
1047 | if (rxbyte != DM9000_PKT_RDY) | |
1048 | return; | |
1049 | ||
1050 | /* A packet ready now & Get status/length */ | |
6478fac6 | 1051 | GoodPacket = true; |
a1365275 SH |
1052 | writeb(DM9000_MRCMD, db->io_addr); |
1053 | ||
1054 | (db->inblk)(db->io_data, &rxhdr, sizeof(rxhdr)); | |
1055 | ||
93116573 | 1056 | RxLen = le16_to_cpu(rxhdr.RxLen); |
a1365275 | 1057 | |
c991d168 BD |
1058 | if (netif_msg_rx_status(db)) |
1059 | dev_dbg(db->dev, "RX: status %02x, length %04x\n", | |
1060 | rxhdr.RxStatus, RxLen); | |
1061 | ||
a1365275 SH |
1062 | /* Packet Status check */ |
1063 | if (RxLen < 0x40) { | |
6478fac6 | 1064 | GoodPacket = false; |
c991d168 BD |
1065 | if (netif_msg_rx_err(db)) |
1066 | dev_dbg(db->dev, "RX: Bad Packet (runt)\n"); | |
a1365275 SH |
1067 | } |
1068 | ||
1069 | if (RxLen > DM9000_PKT_MAX) { | |
a76836f9 | 1070 | dev_dbg(db->dev, "RST: RX Len:%x\n", RxLen); |
a1365275 SH |
1071 | } |
1072 | ||
93116573 | 1073 | if (rxhdr.RxStatus & 0xbf) { |
6478fac6 | 1074 | GoodPacket = false; |
93116573 | 1075 | if (rxhdr.RxStatus & 0x01) { |
c991d168 BD |
1076 | if (netif_msg_rx_err(db)) |
1077 | dev_dbg(db->dev, "fifo error\n"); | |
09f75cd7 | 1078 | dev->stats.rx_fifo_errors++; |
a1365275 | 1079 | } |
93116573 | 1080 | if (rxhdr.RxStatus & 0x02) { |
c991d168 BD |
1081 | if (netif_msg_rx_err(db)) |
1082 | dev_dbg(db->dev, "crc error\n"); | |
09f75cd7 | 1083 | dev->stats.rx_crc_errors++; |
a1365275 | 1084 | } |
93116573 | 1085 | if (rxhdr.RxStatus & 0x80) { |
c991d168 BD |
1086 | if (netif_msg_rx_err(db)) |
1087 | dev_dbg(db->dev, "length error\n"); | |
09f75cd7 | 1088 | dev->stats.rx_length_errors++; |
a1365275 SH |
1089 | } |
1090 | } | |
1091 | ||
1092 | /* Move data from DM9000 */ | |
1093 | if (GoodPacket | |
1094 | && ((skb = dev_alloc_skb(RxLen + 4)) != NULL)) { | |
a1365275 SH |
1095 | skb_reserve(skb, 2); |
1096 | rdptr = (u8 *) skb_put(skb, RxLen - 4); | |
1097 | ||
1098 | /* Read received packet from RX SRAM */ | |
1099 | ||
1100 | (db->inblk)(db->io_data, rdptr, RxLen); | |
09f75cd7 | 1101 | dev->stats.rx_bytes += RxLen; |
a1365275 SH |
1102 | |
1103 | /* Pass to upper layer */ | |
1104 | skb->protocol = eth_type_trans(skb, dev); | |
1105 | netif_rx(skb); | |
09f75cd7 | 1106 | dev->stats.rx_packets++; |
a1365275 SH |
1107 | |
1108 | } else { | |
1109 | /* need to dump the packet's data */ | |
1110 | ||
1111 | (db->dumpblk)(db->io_data, RxLen); | |
1112 | } | |
1113 | } while (rxbyte == DM9000_PKT_RDY); | |
1114 | } | |
1115 | ||
39c341a8 BD |
1116 | static unsigned int |
1117 | dm9000_read_locked(board_info_t *db, int reg) | |
1118 | { | |
1119 | unsigned long flags; | |
1120 | unsigned int ret; | |
1121 | ||
1122 | spin_lock_irqsave(&db->lock, flags); | |
1123 | ret = ior(db, reg); | |
1124 | spin_unlock_irqrestore(&db->lock, flags); | |
1125 | ||
1126 | return ret; | |
1127 | } | |
1128 | ||
1129 | static int dm9000_wait_eeprom(board_info_t *db) | |
1130 | { | |
1131 | unsigned int status; | |
1132 | int timeout = 8; /* wait max 8msec */ | |
1133 | ||
1134 | /* The DM9000 data sheets say we should be able to | |
1135 | * poll the ERRE bit in EPCR to wait for the EEPROM | |
1136 | * operation. From testing several chips, this bit | |
7d2e3cb7 | 1137 | * does not seem to work. |
39c341a8 BD |
1138 | * |
1139 | * We attempt to use the bit, but fall back to the | |
1140 | * timeout (which is why we do not return an error | |
1141 | * on expiry) to say that the EEPROM operation has | |
1142 | * completed. | |
1143 | */ | |
1144 | ||
1145 | while (1) { | |
1146 | status = dm9000_read_locked(db, DM9000_EPCR); | |
1147 | ||
1148 | if ((status & EPCR_ERRE) == 0) | |
1149 | break; | |
1150 | ||
1151 | if (timeout-- < 0) { | |
1152 | dev_dbg(db->dev, "timeout waiting EEPROM\n"); | |
1153 | break; | |
1154 | } | |
1155 | } | |
1156 | ||
1157 | return 0; | |
1158 | } | |
1159 | ||
a1365275 | 1160 | /* |
86c62fab | 1161 | * Read a word data from EEPROM |
a1365275 | 1162 | */ |
86c62fab | 1163 | static void |
29d52e54 | 1164 | dm9000_read_eeprom(board_info_t *db, int offset, u8 *to) |
a1365275 | 1165 | { |
621ddcb0 BD |
1166 | unsigned long flags; |
1167 | ||
bb44fb70 BD |
1168 | if (db->flags & DM9000_PLATF_NO_EEPROM) { |
1169 | to[0] = 0xff; | |
1170 | to[1] = 0xff; | |
1171 | return; | |
1172 | } | |
1173 | ||
9a2f037c BD |
1174 | mutex_lock(&db->addr_lock); |
1175 | ||
621ddcb0 BD |
1176 | spin_lock_irqsave(&db->lock, flags); |
1177 | ||
a1365275 SH |
1178 | iow(db, DM9000_EPAR, offset); |
1179 | iow(db, DM9000_EPCR, EPCR_ERPRR); | |
621ddcb0 BD |
1180 | |
1181 | spin_unlock_irqrestore(&db->lock, flags); | |
1182 | ||
39c341a8 BD |
1183 | dm9000_wait_eeprom(db); |
1184 | ||
1185 | /* delay for at-least 150uS */ | |
1186 | msleep(1); | |
621ddcb0 BD |
1187 | |
1188 | spin_lock_irqsave(&db->lock, flags); | |
1189 | ||
a1365275 | 1190 | iow(db, DM9000_EPCR, 0x0); |
86c62fab BD |
1191 | |
1192 | to[0] = ior(db, DM9000_EPDRL); | |
1193 | to[1] = ior(db, DM9000_EPDRH); | |
9a2f037c | 1194 | |
621ddcb0 BD |
1195 | spin_unlock_irqrestore(&db->lock, flags); |
1196 | ||
9a2f037c | 1197 | mutex_unlock(&db->addr_lock); |
a1365275 SH |
1198 | } |
1199 | ||
a1365275 SH |
1200 | /* |
1201 | * Write a word data to SROM | |
1202 | */ | |
1203 | static void | |
29d52e54 | 1204 | dm9000_write_eeprom(board_info_t *db, int offset, u8 *data) |
a1365275 | 1205 | { |
621ddcb0 BD |
1206 | unsigned long flags; |
1207 | ||
bb44fb70 BD |
1208 | if (db->flags & DM9000_PLATF_NO_EEPROM) |
1209 | return; | |
1210 | ||
9a2f037c BD |
1211 | mutex_lock(&db->addr_lock); |
1212 | ||
621ddcb0 | 1213 | spin_lock_irqsave(&db->lock, flags); |
a1365275 | 1214 | iow(db, DM9000_EPAR, offset); |
29d52e54 BD |
1215 | iow(db, DM9000_EPDRH, data[1]); |
1216 | iow(db, DM9000_EPDRL, data[0]); | |
a1365275 | 1217 | iow(db, DM9000_EPCR, EPCR_WEP | EPCR_ERPRW); |
621ddcb0 BD |
1218 | spin_unlock_irqrestore(&db->lock, flags); |
1219 | ||
39c341a8 BD |
1220 | dm9000_wait_eeprom(db); |
1221 | ||
1222 | mdelay(1); /* wait at least 150uS to clear */ | |
621ddcb0 BD |
1223 | |
1224 | spin_lock_irqsave(&db->lock, flags); | |
a1365275 | 1225 | iow(db, DM9000_EPCR, 0); |
621ddcb0 | 1226 | spin_unlock_irqrestore(&db->lock, flags); |
9a2f037c BD |
1227 | |
1228 | mutex_unlock(&db->addr_lock); | |
a1365275 SH |
1229 | } |
1230 | ||
a1365275 SH |
1231 | /* |
1232 | * Set DM9000 multicast address | |
1233 | */ | |
1234 | static void | |
1235 | dm9000_hash_table(struct net_device *dev) | |
1236 | { | |
1237 | board_info_t *db = (board_info_t *) dev->priv; | |
1238 | struct dev_mc_list *mcptr = dev->mc_list; | |
1239 | int mc_cnt = dev->mc_count; | |
d39cb786 | 1240 | int i, oft; |
a1365275 | 1241 | u32 hash_val; |
d39cb786 | 1242 | u16 hash_table[4]; |
23d245b6 | 1243 | u8 rcr = RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN; |
a1365275 SH |
1244 | unsigned long flags; |
1245 | ||
5b2b4ff0 | 1246 | dm9000_dbg(db, 1, "entering %s\n", __func__); |
a1365275 | 1247 | |
d39cb786 | 1248 | spin_lock_irqsave(&db->lock, flags); |
a1365275 | 1249 | |
d39cb786 | 1250 | for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++) |
a1365275 SH |
1251 | iow(db, oft, dev->dev_addr[i]); |
1252 | ||
1253 | /* Clear Hash Table */ | |
1254 | for (i = 0; i < 4; i++) | |
1255 | hash_table[i] = 0x0; | |
1256 | ||
1257 | /* broadcast address */ | |
1258 | hash_table[3] = 0x8000; | |
1259 | ||
23d245b6 PK |
1260 | if (dev->flags & IFF_PROMISC) |
1261 | rcr |= RCR_PRMSC; | |
1262 | ||
1263 | if (dev->flags & IFF_ALLMULTI) | |
1264 | rcr |= RCR_ALL; | |
1265 | ||
a1365275 SH |
1266 | /* the multicast address in Hash Table : 64 bits */ |
1267 | for (i = 0; i < mc_cnt; i++, mcptr = mcptr->next) { | |
d39cb786 | 1268 | hash_val = ether_crc_le(6, mcptr->dmi_addr) & 0x3f; |
a1365275 SH |
1269 | hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16); |
1270 | } | |
1271 | ||
1272 | /* Write the hash table to MAC MD table */ | |
d39cb786 BD |
1273 | for (i = 0, oft = DM9000_MAR; i < 4; i++) { |
1274 | iow(db, oft++, hash_table[i]); | |
1275 | iow(db, oft++, hash_table[i] >> 8); | |
a1365275 SH |
1276 | } |
1277 | ||
23d245b6 | 1278 | iow(db, DM9000_RCR, rcr); |
d39cb786 | 1279 | spin_unlock_irqrestore(&db->lock, flags); |
a1365275 SH |
1280 | } |
1281 | ||
1282 | ||
321f69a4 BD |
1283 | /* |
1284 | * Sleep, either by using msleep() or if we are suspending, then | |
1285 | * use mdelay() to sleep. | |
1286 | */ | |
1287 | static void dm9000_msleep(board_info_t *db, unsigned int ms) | |
1288 | { | |
1289 | if (db->in_suspend) | |
1290 | mdelay(ms); | |
1291 | else | |
1292 | msleep(ms); | |
1293 | } | |
1294 | ||
a1365275 SH |
1295 | /* |
1296 | * Read a word from phyxcer | |
1297 | */ | |
1298 | static int | |
1299 | dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg) | |
1300 | { | |
1301 | board_info_t *db = (board_info_t *) dev->priv; | |
1302 | unsigned long flags; | |
9ef9ac51 | 1303 | unsigned int reg_save; |
a1365275 SH |
1304 | int ret; |
1305 | ||
9a2f037c BD |
1306 | mutex_lock(&db->addr_lock); |
1307 | ||
a1365275 | 1308 | spin_lock_irqsave(&db->lock,flags); |
9ef9ac51 BD |
1309 | |
1310 | /* Save previous register address */ | |
1311 | reg_save = readb(db->io_addr); | |
1312 | ||
a1365275 SH |
1313 | /* Fill the phyxcer register into REG_0C */ |
1314 | iow(db, DM9000_EPAR, DM9000_PHY | reg); | |
1315 | ||
1316 | iow(db, DM9000_EPCR, 0xc); /* Issue phyxcer read command */ | |
89c8b0e6 BD |
1317 | |
1318 | writeb(reg_save, db->io_addr); | |
1319 | spin_unlock_irqrestore(&db->lock,flags); | |
1320 | ||
321f69a4 | 1321 | dm9000_msleep(db, 1); /* Wait read complete */ |
89c8b0e6 BD |
1322 | |
1323 | spin_lock_irqsave(&db->lock,flags); | |
1324 | reg_save = readb(db->io_addr); | |
1325 | ||
a1365275 SH |
1326 | iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer read command */ |
1327 | ||
1328 | /* The read data keeps on REG_0D & REG_0E */ | |
1329 | ret = (ior(db, DM9000_EPDRH) << 8) | ior(db, DM9000_EPDRL); | |
1330 | ||
9ef9ac51 BD |
1331 | /* restore the previous address */ |
1332 | writeb(reg_save, db->io_addr); | |
a1365275 SH |
1333 | spin_unlock_irqrestore(&db->lock,flags); |
1334 | ||
9a2f037c | 1335 | mutex_unlock(&db->addr_lock); |
37d5dca6 ES |
1336 | |
1337 | dm9000_dbg(db, 5, "phy_read[%02x] -> %04x\n", reg, ret); | |
a1365275 SH |
1338 | return ret; |
1339 | } | |
1340 | ||
1341 | /* | |
1342 | * Write a word to phyxcer | |
1343 | */ | |
1344 | static void | |
59eae1fa BD |
1345 | dm9000_phy_write(struct net_device *dev, |
1346 | int phyaddr_unused, int reg, int value) | |
a1365275 SH |
1347 | { |
1348 | board_info_t *db = (board_info_t *) dev->priv; | |
1349 | unsigned long flags; | |
9ef9ac51 | 1350 | unsigned long reg_save; |
a1365275 | 1351 | |
37d5dca6 | 1352 | dm9000_dbg(db, 5, "phy_write[%02x] = %04x\n", reg, value); |
9a2f037c BD |
1353 | mutex_lock(&db->addr_lock); |
1354 | ||
a1365275 SH |
1355 | spin_lock_irqsave(&db->lock,flags); |
1356 | ||
9ef9ac51 BD |
1357 | /* Save previous register address */ |
1358 | reg_save = readb(db->io_addr); | |
1359 | ||
a1365275 SH |
1360 | /* Fill the phyxcer register into REG_0C */ |
1361 | iow(db, DM9000_EPAR, DM9000_PHY | reg); | |
1362 | ||
1363 | /* Fill the written data into REG_0D & REG_0E */ | |
073d3f46 BD |
1364 | iow(db, DM9000_EPDRL, value); |
1365 | iow(db, DM9000_EPDRH, value >> 8); | |
a1365275 SH |
1366 | |
1367 | iow(db, DM9000_EPCR, 0xa); /* Issue phyxcer write command */ | |
89c8b0e6 BD |
1368 | |
1369 | writeb(reg_save, db->io_addr); | |
9a2f037c | 1370 | spin_unlock_irqrestore(&db->lock, flags); |
89c8b0e6 | 1371 | |
321f69a4 | 1372 | dm9000_msleep(db, 1); /* Wait write complete */ |
89c8b0e6 BD |
1373 | |
1374 | spin_lock_irqsave(&db->lock,flags); | |
1375 | reg_save = readb(db->io_addr); | |
1376 | ||
a1365275 SH |
1377 | iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer write command */ |
1378 | ||
9ef9ac51 BD |
1379 | /* restore the previous address */ |
1380 | writeb(reg_save, db->io_addr); | |
1381 | ||
9a2f037c BD |
1382 | spin_unlock_irqrestore(&db->lock, flags); |
1383 | mutex_unlock(&db->addr_lock); | |
a1365275 SH |
1384 | } |
1385 | ||
1386 | static int | |
3ae5eaec | 1387 | dm9000_drv_suspend(struct platform_device *dev, pm_message_t state) |
a1365275 | 1388 | { |
3ae5eaec | 1389 | struct net_device *ndev = platform_get_drvdata(dev); |
321f69a4 | 1390 | board_info_t *db; |
a1365275 | 1391 | |
9480e307 | 1392 | if (ndev) { |
321f69a4 BD |
1393 | db = (board_info_t *) ndev->priv; |
1394 | db->in_suspend = 1; | |
1395 | ||
a1365275 SH |
1396 | if (netif_running(ndev)) { |
1397 | netif_device_detach(ndev); | |
1398 | dm9000_shutdown(ndev); | |
1399 | } | |
1400 | } | |
1401 | return 0; | |
1402 | } | |
1403 | ||
1404 | static int | |
3ae5eaec | 1405 | dm9000_drv_resume(struct platform_device *dev) |
a1365275 | 1406 | { |
3ae5eaec | 1407 | struct net_device *ndev = platform_get_drvdata(dev); |
a1365275 SH |
1408 | board_info_t *db = (board_info_t *) ndev->priv; |
1409 | ||
9480e307 | 1410 | if (ndev) { |
a1365275 SH |
1411 | |
1412 | if (netif_running(ndev)) { | |
1413 | dm9000_reset(db); | |
1414 | dm9000_init_dm9000(ndev); | |
1415 | ||
1416 | netif_device_attach(ndev); | |
1417 | } | |
321f69a4 BD |
1418 | |
1419 | db->in_suspend = 0; | |
a1365275 SH |
1420 | } |
1421 | return 0; | |
1422 | } | |
1423 | ||
e21fd4f0 | 1424 | static int __devexit |
3ae5eaec | 1425 | dm9000_drv_remove(struct platform_device *pdev) |
a1365275 | 1426 | { |
3ae5eaec | 1427 | struct net_device *ndev = platform_get_drvdata(pdev); |
a1365275 | 1428 | |
3ae5eaec | 1429 | platform_set_drvdata(pdev, NULL); |
a1365275 SH |
1430 | |
1431 | unregister_netdev(ndev); | |
1432 | dm9000_release_board(pdev, (board_info_t *) ndev->priv); | |
9fd9f9b6 | 1433 | free_netdev(ndev); /* free device structure */ |
a1365275 | 1434 | |
a76836f9 | 1435 | dev_dbg(&pdev->dev, "released and freed device\n"); |
a1365275 SH |
1436 | return 0; |
1437 | } | |
1438 | ||
3ae5eaec | 1439 | static struct platform_driver dm9000_driver = { |
5d22a312 BD |
1440 | .driver = { |
1441 | .name = "dm9000", | |
1442 | .owner = THIS_MODULE, | |
1443 | }, | |
a1365275 | 1444 | .probe = dm9000_probe, |
e21fd4f0 | 1445 | .remove = __devexit_p(dm9000_drv_remove), |
a1365275 SH |
1446 | .suspend = dm9000_drv_suspend, |
1447 | .resume = dm9000_drv_resume, | |
1448 | }; | |
1449 | ||
1450 | static int __init | |
1451 | dm9000_init(void) | |
1452 | { | |
7da99859 | 1453 | printk(KERN_INFO "%s Ethernet Driver, V%s\n", CARDNAME, DRV_VERSION); |
2ae2d77c | 1454 | |
59eae1fa | 1455 | return platform_driver_register(&dm9000_driver); |
a1365275 SH |
1456 | } |
1457 | ||
1458 | static void __exit | |
1459 | dm9000_cleanup(void) | |
1460 | { | |
3ae5eaec | 1461 | platform_driver_unregister(&dm9000_driver); |
a1365275 SH |
1462 | } |
1463 | ||
1464 | module_init(dm9000_init); | |
1465 | module_exit(dm9000_cleanup); | |
1466 | ||
1467 | MODULE_AUTHOR("Sascha Hauer, Ben Dooks"); | |
1468 | MODULE_DESCRIPTION("Davicom DM9000 network driver"); | |
1469 | MODULE_LICENSE("GPL"); | |
72abb461 | 1470 | MODULE_ALIAS("platform:dm9000"); |