[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / chelsio / mv88x201x.c

/*****************************************************************************
 *                                                                           *
 * File: mv88x201x.c                                                         *
 * $Revision: 1.12 $                                                         *
 * $Date: 2005/04/15 19:27:14 $                                              *
 * Description:                                                              *
 *  Marvell PHY (mv88x201x) functionality.                                   *
 *  part of the Chelsio 10Gb Ethernet Driver.                                *
 *                                                                           *
 * This program is free software; you can redistribute it and/or modify      *
 * it under the terms of the GNU General Public License, version 2, as       *
 * published by the Free Software Foundation.                                *
 *                                                                           *
 * You should have received a copy of the GNU General Public License along   *
 * with this program; if not, write to the Free Software Foundation, Inc.,   *
 * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.                 *
 *                                                                           *
 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED    *
 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF      *
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.                     *
 *                                                                           *
 * http://www.chelsio.com                                                    *
 *                                                                           *
 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc.                    *
 * All rights reserved.                                                      *
 *                                                                           *
 * Maintainers: maintainers@chelsio.com                                      *
 *                                                                           *
 * Authors: Dimitrios Michailidis   <dm@chelsio.com>                         *
 *          Tina Yang               <tainay@chelsio.com>                     *
 *          Felix Marti             <felix@chelsio.com>                      *
 *          Scott Bardone           <sbardone@chelsio.com>                   *
 *          Kurt Ottaway            <kottaway@chelsio.com>                   *
 *          Frank DiMambro          <frank@chelsio.com>                      *
 *                                                                           *
 * History:                                                                  *
 *                                                                           *
 ****************************************************************************/

#include "cphy.h"
#include "elmer0.h"

/*
 * The 88x2010 Rev C. requires some link status registers * to be read
 * twice in order to get the right values. Future * revisions will fix
 * this problem and then this macro * can disappear.
 */
#define MV88x2010_LINK_STATUS_BUGS    1

static int led_init(struct cphy *cphy)
{
	/* Setup the LED registers so we can turn on/off.
	 * Writing these bits maps control to another
	 * register. mmd(0x1) addr(0x7)
	 */
	cphy_mdio_write(cphy, MDIO_MMD_PCS, 0x8304, 0xdddd);
	return 0;
}

static int led_link(struct cphy *cphy, u32 do_enable)
{
	u32 led = 0;
#define LINK_ENABLE_BIT 0x1

	cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_CTRL2, &led);

	if (do_enable & LINK_ENABLE_BIT) {
		led |= LINK_ENABLE_BIT;
		cphy_mdio_write(cphy, MDIO_MMD_PMAPMD, MDIO_CTRL2, led);
	} else {
		led &= ~LINK_ENABLE_BIT;
		cphy_mdio_write(cphy, MDIO_MMD_PMAPMD, MDIO_CTRL2, led);
	}
	return 0;
}

/* Port Reset */
static int mv88x201x_reset(struct cphy *cphy, int wait)
{
	/* This can be done through registers.  It is not required since
	 * a full chip reset is used.
	 */
	return 0;
}

static int mv88x201x_interrupt_enable(struct cphy *cphy)
{
	/* Enable PHY LASI interrupts. */
	cphy_mdio_write(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL,
			MDIO_PMA_LASI_LSALARM);

	/* Enable Marvell interrupts through Elmer0. */
	if (t1_is_asic(cphy->adapter)) {
		u32 elmer;

		t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer);
		elmer |= ELMER0_GP_BIT6;
		t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);
	}
	return 0;
}

static int mv88x201x_interrupt_disable(struct cphy *cphy)
{
	/* Disable PHY LASI interrupts. */
	cphy_mdio_write(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL, 0x0);

	/* Disable Marvell interrupts through Elmer0. */
	if (t1_is_asic(cphy->adapter)) {
		u32 elmer;

		t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer);
		elmer &= ~ELMER0_GP_BIT6;
		t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);
	}
	return 0;
}

static int mv88x201x_interrupt_clear(struct cphy *cphy)
{
	u32 elmer;
	u32 val;

#ifdef MV88x2010_LINK_STATUS_BUGS
	/* Required to read twice before clear takes affect. */
	cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_RXSTAT, &val);
	cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_TXSTAT, &val);
	cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_STAT, &val);

	/* Read this register after the others above it else
	 * the register doesn't clear correctly.
	 */
	cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val);
#endif

	/* Clear link status. */
	cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val);
	/* Clear PHY LASI interrupts. */
	cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_STAT, &val);

#ifdef MV88x2010_LINK_STATUS_BUGS
	/* Do it again. */
	cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_RXSTAT, &val);
	cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_TXSTAT, &val);
#endif

	/* Clear Marvell interrupts through Elmer0. */
	if (t1_is_asic(cphy->adapter)) {
		t1_tpi_read(cphy->adapter, A_ELMER0_INT_CAUSE, &elmer);
		elmer |= ELMER0_GP_BIT6;
		t1_tpi_write(cphy->adapter, A_ELMER0_INT_CAUSE, elmer);
	}
	return 0;
}

static int mv88x201x_interrupt_handler(struct cphy *cphy)
{
	/* Clear interrupts */
	mv88x201x_interrupt_clear(cphy);

	/* We have only enabled link change interrupts and so
	 * cphy_cause must be a link change interrupt.
	 */
	return cphy_cause_link_change;
}

static int mv88x201x_set_loopback(struct cphy *cphy, int on)
{
	return 0;
}

static int mv88x201x_get_link_status(struct cphy *cphy, int *link_ok,
				     int *speed, int *duplex, int *fc)
{
	u32 val = 0;

	if (link_ok) {
		/* Read link status. */
		cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val);
		val &= MDIO_STAT1_LSTATUS;
		*link_ok = (val == MDIO_STAT1_LSTATUS);
		/* Turn on/off Link LED */
		led_link(cphy, *link_ok);
	}
	if (speed)
		*speed = SPEED_10000;
	if (duplex)
		*duplex = DUPLEX_FULL;
	if (fc)
		*fc = PAUSE_RX | PAUSE_TX;
	return 0;
}

static void mv88x201x_destroy(struct cphy *cphy)
{
	kfree(cphy);
}

static struct cphy_ops mv88x201x_ops = {
	.destroy           = mv88x201x_destroy,
	.reset             = mv88x201x_reset,
	.interrupt_enable  = mv88x201x_interrupt_enable,
	.interrupt_disable = mv88x201x_interrupt_disable,
	.interrupt_clear   = mv88x201x_interrupt_clear,
	.interrupt_handler = mv88x201x_interrupt_handler,
	.get_link_status   = mv88x201x_get_link_status,
	.set_loopback      = mv88x201x_set_loopback,
	.mmds              = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS |
			      MDIO_DEVS_PHYXS | MDIO_DEVS_WIS),
};

static struct cphy *mv88x201x_phy_create(struct net_device *dev, int phy_addr,
					 const struct mdio_ops *mdio_ops)
{
	u32 val;
	struct cphy *cphy = kzalloc(sizeof(*cphy), GFP_KERNEL);

	if (!cphy)
		return NULL;

	cphy_init(cphy, dev, phy_addr, &mv88x201x_ops, mdio_ops);

	/* Commands the PHY to enable XFP's clock. */
	cphy_mdio_read(cphy, MDIO_MMD_PCS, 0x8300, &val);
	cphy_mdio_write(cphy, MDIO_MMD_PCS, 0x8300, val | 1);

	/* Clear link status. Required because of a bug in the PHY.  */
	cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT2, &val);
	cphy_mdio_read(cphy, MDIO_MMD_PCS, MDIO_STAT2, &val);

	/* Allows for Link,Ack LED turn on/off */
	led_init(cphy);
	return cphy;
}

/* Chip Reset */
static int mv88x201x_phy_reset(adapter_t *adapter)
{
	u32 val;

	t1_tpi_read(adapter, A_ELMER0_GPO, &val);
	val &= ~4;
	t1_tpi_write(adapter, A_ELMER0_GPO, val);
	msleep(100);

	t1_tpi_write(adapter, A_ELMER0_GPO, val | 4);
	msleep(1000);

	/* Now lets enable the Laser. Delay 100us */
	t1_tpi_read(adapter, A_ELMER0_GPO, &val);
	val |= 0x8000;
	t1_tpi_write(adapter, A_ELMER0_GPO, val);
	udelay(100);
	return 0;
}

const struct gphy t1_mv88x201x_ops = {
	.create = mv88x201x_phy_create,
	.reset = mv88x201x_phy_reset
};
Commit	Line	Data
8199d3a7 CL	1	/*****************************************************************************
	2	* *
	3	* File: mv88x201x.c *
559fb51b SB	4	* $Revision: 1.12 $ *
559fb51b SB	5	* $Date: 2005/04/15 19:27:14 $ *
8199d3a7 CL	6	* Description: *
	7	* Marvell PHY (mv88x201x) functionality. *
	8	* part of the Chelsio 10Gb Ethernet Driver. *
	9	* *
	10	* This program is free software; you can redistribute it and/or modify *
	11	* it under the terms of the GNU General Public License, version 2, as *
	12	* published by the Free Software Foundation. *
	13	* *
	14	* You should have received a copy of the GNU General Public License along *
	15	* with this program; if not, write to the Free Software Foundation, Inc., *
	16	* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
	17	* *
	18	* THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
	19	* WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
	20	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
	21	* *
	22	* http://www.chelsio.com *
	23	* *
	24	* Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
	25	* All rights reserved. *
	26	* *
	27	* Maintainers: maintainers@chelsio.com *
	28	* *
	29	* Authors: Dimitrios Michailidis <dm@chelsio.com> *
	30	* Tina Yang <tainay@chelsio.com> *
	31	* Felix Marti <felix@chelsio.com> *
	32	* Scott Bardone <sbardone@chelsio.com> *
	33	* Kurt Ottaway <kottaway@chelsio.com> *
	34	* Frank DiMambro <frank@chelsio.com> *
	35	* *
	36	* History: *
	37	* *
	38	****************************************************************************/
	39
	40	#include "cphy.h"
	41	#include "elmer0.h"
	42
	43	/*
	44	* The 88x2010 Rev C. requires some link status registers * to be read
	45	* twice in order to get the right values. Future * revisions will fix
	46	* this problem and then this macro * can disappear.
	47	*/
	48	#define MV88x2010_LINK_STATUS_BUGS 1
	49
	50	static int led_init(struct cphy *cphy)
	51	{
	52	/* Setup the LED registers so we can turn on/off.
	53	* Writing these bits maps control to another
	54	* register. mmd(0x1) addr(0x7)
	55	*/
23c3320c	56	cphy_mdio_write(cphy, MDIO_MMD_PCS, 0x8304, 0xdddd);
8199d3a7 CL	57	return 0;
	58	}
	59
	60	static int led_link(struct cphy *cphy, u32 do_enable)
	61	{
	62	u32 led = 0;
	63	#define LINK_ENABLE_BIT 0x1
	64
23c3320c	65	cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_CTRL2, &led);
8199d3a7 CL	66
	67	if (do_enable & LINK_ENABLE_BIT) {
	68	led \|= LINK_ENABLE_BIT;
23c3320c	69	cphy_mdio_write(cphy, MDIO_MMD_PMAPMD, MDIO_CTRL2, led);
8199d3a7 CL	70	} else {
8199d3a7 CL	71	led &= ~LINK_ENABLE_BIT;
23c3320c	72	cphy_mdio_write(cphy, MDIO_MMD_PMAPMD, MDIO_CTRL2, led);
8199d3a7 CL	73	}
	74	return 0;
	75	}
	76
	77	/* Port Reset */
	78	static int mv88x201x_reset(struct cphy *cphy, int wait)
	79	{
	80	/* This can be done through registers. It is not required since
	81	* a full chip reset is used.
	82	*/
	83	return 0;
	84	}
	85
	86	static int mv88x201x_interrupt_enable(struct cphy *cphy)
	87	{
	88	/* Enable PHY LASI interrupts. */
aa22437e BH	89	cphy_mdio_write(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL,
aa22437e BH	90	MDIO_PMA_LASI_LSALARM);
8199d3a7 CL	91
8199d3a7 CL	92	/* Enable Marvell interrupts through Elmer0. */
f1d3d38a SH	93	if (t1_is_asic(cphy->adapter)) {
	94	u32 elmer;
	95
	96	t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer);
	97	elmer \|= ELMER0_GP_BIT6;
	98	t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);
	99	}
8199d3a7 CL	100	return 0;
	101	}
	102
	103	static int mv88x201x_interrupt_disable(struct cphy *cphy)
	104	{
	105	/* Disable PHY LASI interrupts. */
aa22437e	106	cphy_mdio_write(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL, 0x0);
8199d3a7 CL	107
8199d3a7 CL	108	/* Disable Marvell interrupts through Elmer0. */
f1d3d38a SH	109	if (t1_is_asic(cphy->adapter)) {
	110	u32 elmer;
	111
	112	t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer);
	113	elmer &= ~ELMER0_GP_BIT6;
	114	t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);
	115	}
8199d3a7 CL	116	return 0;
	117	}
	118
	119	static int mv88x201x_interrupt_clear(struct cphy *cphy)
	120	{
	121	u32 elmer;
	122	u32 val;
	123
	124	#ifdef MV88x2010_LINK_STATUS_BUGS
	125	/* Required to read twice before clear takes affect. */
aa22437e BH	126	cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_RXSTAT, &val);
	127	cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_TXSTAT, &val);
	128	cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_STAT, &val);
8199d3a7 CL	129
	130	/* Read this register after the others above it else
	131	* the register doesn't clear correctly.
	132	*/
23c3320c	133	cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val);
8199d3a7 CL	134	#endif
	135
	136	/* Clear link status. */
23c3320c	137	cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val);
8199d3a7	138	/* Clear PHY LASI interrupts. */
aa22437e	139	cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_STAT, &val);
8199d3a7 CL	140
	141	#ifdef MV88x2010_LINK_STATUS_BUGS
	142	/* Do it again. */
aa22437e BH	143	cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_RXSTAT, &val);
aa22437e BH	144	cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_TXSTAT, &val);
8199d3a7 CL	145	#endif
	146
	147	/* Clear Marvell interrupts through Elmer0. */
f1d3d38a SH	148	if (t1_is_asic(cphy->adapter)) {
	149	t1_tpi_read(cphy->adapter, A_ELMER0_INT_CAUSE, &elmer);
	150	elmer \|= ELMER0_GP_BIT6;
	151	t1_tpi_write(cphy->adapter, A_ELMER0_INT_CAUSE, elmer);
	152	}
8199d3a7 CL	153	return 0;
	154	}
	155
	156	static int mv88x201x_interrupt_handler(struct cphy *cphy)
	157	{
	158	/* Clear interrupts */
	159	mv88x201x_interrupt_clear(cphy);
	160
	161	/* We have only enabled link change interrupts and so
	162	* cphy_cause must be a link change interrupt.
	163	*/
	164	return cphy_cause_link_change;
	165	}
	166
	167	static int mv88x201x_set_loopback(struct cphy *cphy, int on)
	168	{
	169	return 0;
	170	}
	171
	172	static int mv88x201x_get_link_status(struct cphy cphy, int link_ok,
	173	int speed, int duplex, int *fc)
	174	{
	175	u32 val = 0;
8199d3a7 CL	176
	177	if (link_ok) {
	178	/* Read link status. */
23c3320c BH	179	cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val);
	180	val &= MDIO_STAT1_LSTATUS;
	181	*link_ok = (val == MDIO_STAT1_LSTATUS);
8199d3a7 CL	182	/* Turn on/off Link LED */
	183	led_link(cphy, *link_ok);
	184	}
	185	if (speed)
	186	*speed = SPEED_10000;
	187	if (duplex)
	188	*duplex = DUPLEX_FULL;
	189	if (fc)
	190	*fc = PAUSE_RX \| PAUSE_TX;
	191	return 0;
	192	}
	193
	194	static void mv88x201x_destroy(struct cphy *cphy)
	195	{
	196	kfree(cphy);
	197	}
	198
	199	static struct cphy_ops mv88x201x_ops = {
	200	.destroy = mv88x201x_destroy,
	201	.reset = mv88x201x_reset,
	202	.interrupt_enable = mv88x201x_interrupt_enable,
	203	.interrupt_disable = mv88x201x_interrupt_disable,
	204	.interrupt_clear = mv88x201x_interrupt_clear,
	205	.interrupt_handler = mv88x201x_interrupt_handler,
	206	.get_link_status = mv88x201x_get_link_status,
	207	.set_loopback = mv88x201x_set_loopback,
23c3320c BH	208	.mmds = (MDIO_DEVS_PMAPMD \| MDIO_DEVS_PCS \|
23c3320c BH	209	MDIO_DEVS_PHYXS \| MDIO_DEVS_WIS),
8199d3a7 CL	210	};
8199d3a7 CL	211
703cebab	212	static struct cphy mv88x201x_phy_create(struct net_device dev, int phy_addr,
459e536b	213	const struct mdio_ops *mdio_ops)
8199d3a7 CL	214	{
8199d3a7 CL	215	u32 val;
1270266c	216	struct cphy cphy = kzalloc(sizeof(cphy), GFP_KERNEL);
8199d3a7 CL	217
	218	if (!cphy)
	219	return NULL;
1270266c	220
703cebab	221	cphy_init(cphy, dev, phy_addr, &mv88x201x_ops, mdio_ops);
8199d3a7 CL	222
8199d3a7 CL	223	/* Commands the PHY to enable XFP's clock. */
23c3320c BH	224	cphy_mdio_read(cphy, MDIO_MMD_PCS, 0x8300, &val);
23c3320c BH	225	cphy_mdio_write(cphy, MDIO_MMD_PCS, 0x8300, val \| 1);
8199d3a7 CL	226
8199d3a7 CL	227	/* Clear link status. Required because of a bug in the PHY. */
23c3320c BH	228	cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT2, &val);
23c3320c BH	229	cphy_mdio_read(cphy, MDIO_MMD_PCS, MDIO_STAT2, &val);
8199d3a7 CL	230
	231	/* Allows for Link,Ack LED turn on/off */
	232	led_init(cphy);
	233	return cphy;
	234	}
	235
	236	/* Chip Reset */
	237	static int mv88x201x_phy_reset(adapter_t *adapter)
	238	{
	239	u32 val;
	240
	241	t1_tpi_read(adapter, A_ELMER0_GPO, &val);
	242	val &= ~4;
	243	t1_tpi_write(adapter, A_ELMER0_GPO, val);
	244	msleep(100);
	245
	246	t1_tpi_write(adapter, A_ELMER0_GPO, val \| 4);
	247	msleep(1000);
	248
	249	/* Now lets enable the Laser. Delay 100us */
	250	t1_tpi_read(adapter, A_ELMER0_GPO, &val);
	251	val \|= 0x8000;
	252	t1_tpi_write(adapter, A_ELMER0_GPO, val);
	253	udelay(100);
	254	return 0;
	255	}
	256
459e536b SH	257	const struct gphy t1_mv88x201x_ops = {
	258	.create = mv88x201x_phy_create,
	259	.reset = mv88x201x_phy_reset
8199d3a7	260	};