[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / chelsio / common.h

/*****************************************************************************
 *                                                                           *
 * File: common.h                                                            *
 * $Revision: 1.21 $                                                         *
 * $Date: 2005/06/22 00:43:25 $                                              *
 * Description:                                                              *
 *  part of the Chelsio 10Gb Ethernet Driver.                                *
 *                                                                           *
 * This program is free software; you can redistribute it and/or modify      *
 * it under the terms of the GNU General Public License, version 2, as       *
 * published by the Free Software Foundation.                                *
 *                                                                           *
 * You should have received a copy of the GNU General Public License along   *
 * with this program; if not, write to the Free Software Foundation, Inc.,   *
 * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.                 *
 *                                                                           *
 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED    *
 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF      *
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.                     *
 *                                                                           *
 * http://www.chelsio.com                                                    *
 *                                                                           *
 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc.                    *
 * All rights reserved.                                                      *
 *                                                                           *
 * Maintainers: maintainers@chelsio.com                                      *
 *                                                                           *
 * Authors: Dimitrios Michailidis   <dm@chelsio.com>                         *
 *          Tina Yang               <tainay@chelsio.com>                     *
 *          Felix Marti             <felix@chelsio.com>                      *
 *          Scott Bardone           <sbardone@chelsio.com>                   *
 *          Kurt Ottaway            <kottaway@chelsio.com>                   *
 *          Frank DiMambro          <frank@chelsio.com>                      *
 *                                                                           *
 * History:                                                                  *
 *                                                                           *
 ****************************************************************************/

#define pr_fmt(fmt) "cxgb: " fmt

#ifndef _CXGB_COMMON_H_
#define _CXGB_COMMON_H_

#include <linux/module.h>
#include <linux/netdevice.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/ethtool.h>
#include <linux/if_vlan.h>
#include <linux/mdio.h>
#include <linux/crc32.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <asm/io.h>
#include <linux/pci_ids.h>

#define DRV_DESCRIPTION "Chelsio 10Gb Ethernet Driver"
#define DRV_NAME "cxgb"
#define DRV_VERSION "2.2"

#define CH_DEVICE(devid, ssid, idx) \
	{ PCI_VENDOR_ID_CHELSIO, devid, PCI_ANY_ID, ssid, 0, 0, idx }

#define SUPPORTED_PAUSE       (1 << 13)
#define SUPPORTED_LOOPBACK    (1 << 15)

#define ADVERTISED_PAUSE      (1 << 13)
#define ADVERTISED_ASYM_PAUSE (1 << 14)

typedef struct adapter adapter_t;

struct t1_rx_mode {
       struct net_device *dev;
};

#define t1_rx_mode_promisc(rm)	(rm->dev->flags & IFF_PROMISC)
#define t1_rx_mode_allmulti(rm)	(rm->dev->flags & IFF_ALLMULTI)
#define t1_rx_mode_mc_cnt(rm)	(netdev_mc_count(rm->dev))
#define t1_get_netdev(rm)	(rm->dev)

#define	MAX_NPORTS 4
#define PORT_MASK ((1 << MAX_NPORTS) - 1)
#define NMTUS      8
#define TCB_SIZE   128

#define SPEED_INVALID 0xffff
#define DUPLEX_INVALID 0xff

enum {
	CHBT_BOARD_N110,
	CHBT_BOARD_N210,
	CHBT_BOARD_7500,
	CHBT_BOARD_8000,
	CHBT_BOARD_CHT101,
	CHBT_BOARD_CHT110,
	CHBT_BOARD_CHT210,
	CHBT_BOARD_CHT204,
	CHBT_BOARD_CHT204V,
	CHBT_BOARD_CHT204E,
	CHBT_BOARD_CHN204,
	CHBT_BOARD_COUGAR,
	CHBT_BOARD_6800,
	CHBT_BOARD_SIMUL,
};

enum {
	CHBT_TERM_FPGA,
	CHBT_TERM_T1,
	CHBT_TERM_T2,
	CHBT_TERM_T3
};

enum {
	CHBT_MAC_CHELSIO_A,
	CHBT_MAC_IXF1010,
	CHBT_MAC_PM3393,
	CHBT_MAC_VSC7321,
	CHBT_MAC_DUMMY
};

enum {
	CHBT_PHY_88E1041,
	CHBT_PHY_88E1111,
	CHBT_PHY_88X2010,
	CHBT_PHY_XPAK,
	CHBT_PHY_MY3126,
	CHBT_PHY_8244,
	CHBT_PHY_DUMMY
};

enum {
	PAUSE_RX      = 1 << 0,
	PAUSE_TX      = 1 << 1,
	PAUSE_AUTONEG = 1 << 2
};

/* Revisions of T1 chip */
enum {
	TERM_T1A   = 0,
	TERM_T1B   = 1,
	TERM_T2    = 3
};

struct sge_params {
	unsigned int cmdQ_size[2];
	unsigned int freelQ_size[2];
	unsigned int large_buf_capacity;
	unsigned int rx_coalesce_usecs;
	unsigned int last_rx_coalesce_raw;
	unsigned int default_rx_coalesce_usecs;
	unsigned int sample_interval_usecs;
	unsigned int coalesce_enable;
	unsigned int polling;
};

struct chelsio_pci_params {
	unsigned short speed;
	unsigned char  width;
	unsigned char  is_pcix;
};

struct tp_params {
	unsigned int pm_size;
	unsigned int cm_size;
	unsigned int pm_rx_base;
	unsigned int pm_tx_base;
	unsigned int pm_rx_pg_size;
	unsigned int pm_tx_pg_size;
	unsigned int pm_rx_num_pgs;
	unsigned int pm_tx_num_pgs;
	unsigned int rx_coalescing_size;
	unsigned int use_5tuple_mode;
};

struct mc5_params {
	unsigned int mode;       /* selects MC5 width */
	unsigned int nservers;   /* size of server region */
	unsigned int nroutes;    /* size of routing region */
};

/* Default MC5 region sizes */
#define DEFAULT_SERVER_REGION_LEN 256
#define DEFAULT_RT_REGION_LEN 1024

struct adapter_params {
	struct sge_params sge;
	struct mc5_params mc5;
	struct tp_params  tp;
	struct chelsio_pci_params pci;

	const struct board_info *brd_info;

	unsigned short mtus[NMTUS];
	unsigned int   nports;          /* # of ethernet ports */
	unsigned int   stats_update_period;
	unsigned short chip_revision;
	unsigned char  chip_version;
	unsigned char  is_asic;
	unsigned char  has_msi;
};

struct link_config {
	unsigned int   supported;        /* link capabilities */
	unsigned int   advertising;      /* advertised capabilities */
	unsigned short requested_speed;  /* speed user has requested */
	unsigned short speed;            /* actual link speed */
	unsigned char  requested_duplex; /* duplex user has requested */
	unsigned char  duplex;           /* actual link duplex */
	unsigned char  requested_fc;     /* flow control user has requested */
	unsigned char  fc;               /* actual link flow control */
	unsigned char  autoneg;          /* autonegotiating? */
};

struct cmac;
struct cphy;

struct port_info {
	struct net_device *dev;
	struct cmac *mac;
	struct cphy *phy;
	struct link_config link_config;
	struct net_device_stats netstats;
};

struct sge;
struct peespi;

struct adapter {
	u8 __iomem *regs;
	struct pci_dev *pdev;
	unsigned long registered_device_map;
	unsigned long open_device_map;
	unsigned long flags;

	const char *name;
	int msg_enable;
	u32 mmio_len;

	struct work_struct ext_intr_handler_task;
	struct adapter_params params;

	struct vlan_group *vlan_grp;

	/* Terminator modules. */
	struct sge    *sge;
	struct peespi *espi;
	struct petp   *tp;

	struct napi_struct napi;
	struct port_info port[MAX_NPORTS];
	struct delayed_work stats_update_task;
	struct timer_list stats_update_timer;

	spinlock_t tpi_lock;
	spinlock_t work_lock;
	spinlock_t mac_lock;

	/* guards async operations */
	spinlock_t async_lock ____cacheline_aligned;
	u32 slow_intr_mask;
	int t1powersave;
};

enum {                                           /* adapter flags */
	FULL_INIT_DONE        = 1 << 0,
	TSO_CAPABLE           = 1 << 2,
	TCP_CSUM_CAPABLE      = 1 << 3,
	UDP_CSUM_CAPABLE      = 1 << 4,
	VLAN_ACCEL_CAPABLE    = 1 << 5,
	RX_CSUM_ENABLED       = 1 << 6,
};

struct mdio_ops;
struct gmac;
struct gphy;

struct board_info {
	unsigned char           board;
	unsigned char           port_number;
	unsigned long           caps;
	unsigned char           chip_term;
	unsigned char           chip_mac;
	unsigned char           chip_phy;
	unsigned int            clock_core;
	unsigned int            clock_mc3;
	unsigned int            clock_mc4;
	unsigned int            espi_nports;
	unsigned int            clock_cspi;
	unsigned int            clock_elmer0;
	unsigned char           mdio_mdien;
	unsigned char           mdio_mdiinv;
	unsigned char           mdio_mdc;
	unsigned char           mdio_phybaseaddr;
	const struct gmac      *gmac;
	const struct gphy      *gphy;
	const struct mdio_ops  *mdio_ops;
	const char             *desc;
};

static inline int t1_is_asic(const adapter_t *adapter)
{
	return adapter->params.is_asic;
}

extern const struct pci_device_id t1_pci_tbl[];

static inline int adapter_matches_type(const adapter_t *adapter,
				       int version, int revision)
{
	return adapter->params.chip_version == version &&
	       adapter->params.chip_revision == revision;
}

#define t1_is_T1B(adap) adapter_matches_type(adap, CHBT_TERM_T1, TERM_T1B)
#define is_T2(adap)     adapter_matches_type(adap, CHBT_TERM_T2, TERM_T2)

/* Returns true if an adapter supports VLAN acceleration and TSO */
static inline int vlan_tso_capable(const adapter_t *adapter)
{
	return !t1_is_T1B(adapter);
}

#define for_each_port(adapter, iter) \
	for (iter = 0; iter < (adapter)->params.nports; ++iter)

#define board_info(adapter) ((adapter)->params.brd_info)
#define is_10G(adapter) (board_info(adapter)->caps & SUPPORTED_10000baseT_Full)

static inline unsigned int core_ticks_per_usec(const adapter_t *adap)
{
	return board_info(adap)->clock_core / 1000000;
}

extern int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp);
extern int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value);
extern int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value);
extern int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *value);

extern void t1_interrupts_enable(adapter_t *adapter);
extern void t1_interrupts_disable(adapter_t *adapter);
extern void t1_interrupts_clear(adapter_t *adapter);
extern int t1_elmer0_ext_intr_handler(adapter_t *adapter);
extern void t1_elmer0_ext_intr(adapter_t *adapter);
extern int t1_slow_intr_handler(adapter_t *adapter);

extern int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
extern const struct board_info *t1_get_board_info(unsigned int board_id);
extern const struct board_info *t1_get_board_info_from_ids(unsigned int devid,
						    unsigned short ssid);
extern int t1_seeprom_read(adapter_t *adapter, u32 addr, __le32 *data);
extern int t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,
		     struct adapter_params *p);
extern int t1_init_hw_modules(adapter_t *adapter);
extern int t1_init_sw_modules(adapter_t *adapter, const struct board_info *bi);
extern void t1_free_sw_modules(adapter_t *adapter);
extern void t1_fatal_err(adapter_t *adapter);
extern void t1_link_changed(adapter_t *adapter, int port_id);
extern void t1_link_negotiated(adapter_t *adapter, int port_id, int link_stat,
			    int speed, int duplex, int pause);
#endif /* _CXGB_COMMON_H_ */
Commit	Line	Data
8199d3a7 CL	1	/*****************************************************************************
	2	* *
	3	* File: common.h *
559fb51b SB	4	* $Revision: 1.21 $ *
559fb51b SB	5	* $Date: 2005/06/22 00:43:25 $ *
8199d3a7 CL	6	* Description: *
	7	* part of the Chelsio 10Gb Ethernet Driver. *
	8	* *
	9	* This program is free software; you can redistribute it and/or modify *
	10	* it under the terms of the GNU General Public License, version 2, as *
	11	* published by the Free Software Foundation. *
	12	* *
	13	* You should have received a copy of the GNU General Public License along *
	14	* with this program; if not, write to the Free Software Foundation, Inc., *
	15	* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
	16	* *
	17	* THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
	18	* WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
	19	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
	20	* *
	21	* http://www.chelsio.com *
	22	* *
	23	* Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
	24	* All rights reserved. *
	25	* *
	26	* Maintainers: maintainers@chelsio.com *
	27	* *
	28	* Authors: Dimitrios Michailidis <dm@chelsio.com> *
	29	* Tina Yang <tainay@chelsio.com> *
	30	* Felix Marti <felix@chelsio.com> *
	31	* Scott Bardone <sbardone@chelsio.com> *
	32	* Kurt Ottaway <kottaway@chelsio.com> *
	33	* Frank DiMambro <frank@chelsio.com> *
	34	* *
	35	* History: *
	36	* *
	37	****************************************************************************/
	38
c1f51212 JP	39	#define pr_fmt(fmt) "cxgb: " fmt
c1f51212 JP	40
559fb51b SB	41	#ifndef _CXGB_COMMON_H_
	42	#define _CXGB_COMMON_H_
	43
559fb51b SB	44	#include <linux/module.h>
	45	#include <linux/netdevice.h>
	46	#include <linux/types.h>
	47	#include <linux/delay.h>
	48	#include <linux/pci.h>
	49	#include <linux/ethtool.h>
f1d3d38a	50	#include <linux/if_vlan.h>
23c3320c	51	#include <linux/mdio.h>
559fb51b SB	52	#include <linux/crc32.h>
559fb51b SB	53	#include <linux/init.h>
5a0e3ad6	54	#include <linux/slab.h>
559fb51b SB	55	#include <asm/io.h>
	56	#include <linux/pci_ids.h>
	57
	58	#define DRV_DESCRIPTION "Chelsio 10Gb Ethernet Driver"
	59	#define DRV_NAME "cxgb"
f1d3d38a	60	#define DRV_VERSION "2.2"
f1d3d38a	61
559fb51b SB	62	#define CH_DEVICE(devid, ssid, idx) \
	63	{ PCI_VENDOR_ID_CHELSIO, devid, PCI_ANY_ID, ssid, 0, 0, idx }
	64
	65	#define SUPPORTED_PAUSE (1 << 13)
	66	#define SUPPORTED_LOOPBACK (1 << 15)
	67
	68	#define ADVERTISED_PAUSE (1 << 13)
	69	#define ADVERTISED_ASYM_PAUSE (1 << 14)
	70
	71	typedef struct adapter adapter_t;
	72
559fb51b	73	struct t1_rx_mode {
305b0160	74	struct net_device *dev;
559fb51b SB	75	};
	76
	77	#define t1_rx_mode_promisc(rm) (rm->dev->flags & IFF_PROMISC)
	78	#define t1_rx_mode_allmulti(rm) (rm->dev->flags & IFF_ALLMULTI)
4cd24eaf	79	#define t1_rx_mode_mc_cnt(rm) (netdev_mc_count(rm->dev))
305b0160	80	#define t1_get_netdev(rm) (rm->dev)
559fb51b SB	81
559fb51b SB	82	#define MAX_NPORTS 4
f1d3d38a SH	83	#define PORT_MASK ((1 << MAX_NPORTS) - 1)
	84	#define NMTUS 8
	85	#define TCB_SIZE 128
8199d3a7	86
559fb51b SB	87	#define SPEED_INVALID 0xffff
559fb51b SB	88	#define DUPLEX_INVALID 0xff
8199d3a7 CL	89
8199d3a7 CL	90	enum {
8199d3a7	91	CHBT_BOARD_N110,
f1d3d38a SH	92	CHBT_BOARD_N210,
	93	CHBT_BOARD_7500,
	94	CHBT_BOARD_8000,
	95	CHBT_BOARD_CHT101,
	96	CHBT_BOARD_CHT110,
	97	CHBT_BOARD_CHT210,
	98	CHBT_BOARD_CHT204,
	99	CHBT_BOARD_CHT204V,
	100	CHBT_BOARD_CHT204E,
	101	CHBT_BOARD_CHN204,
	102	CHBT_BOARD_COUGAR,
	103	CHBT_BOARD_6800,
	104	CHBT_BOARD_SIMUL,
8199d3a7 CL	105	};
	106
	107	enum {
f1d3d38a	108	CHBT_TERM_FPGA,
8199d3a7	109	CHBT_TERM_T1,
f1d3d38a SH	110	CHBT_TERM_T2,
f1d3d38a SH	111	CHBT_TERM_T3
8199d3a7 CL	112	};
	113
	114	enum {
f1d3d38a SH	115	CHBT_MAC_CHELSIO_A,
f1d3d38a SH	116	CHBT_MAC_IXF1010,
8199d3a7	117	CHBT_MAC_PM3393,
f1d3d38a SH	118	CHBT_MAC_VSC7321,
f1d3d38a SH	119	CHBT_MAC_DUMMY
8199d3a7 CL	120	};
	121
	122	enum {
f1d3d38a SH	123	CHBT_PHY_88E1041,
f1d3d38a SH	124	CHBT_PHY_88E1111,
8199d3a7	125	CHBT_PHY_88X2010,
f1d3d38a SH	126	CHBT_PHY_XPAK,
	127	CHBT_PHY_MY3126,
	128	CHBT_PHY_8244,
	129	CHBT_PHY_DUMMY
8199d3a7 CL	130	};
	131
	132	enum {
559fb51b SB	133	PAUSE_RX = 1 << 0,
	134	PAUSE_TX = 1 << 1,
	135	PAUSE_AUTONEG = 1 << 2
8199d3a7 CL	136	};
	137
	138	/* Revisions of T1 chip */
559fb51b SB	139	enum {
	140	TERM_T1A = 0,
	141	TERM_T1B = 1,
	142	TERM_T2 = 3
8199d3a7 CL	143	};
	144
	145	struct sge_params {
	146	unsigned int cmdQ_size[2];
	147	unsigned int freelQ_size[2];
	148	unsigned int large_buf_capacity;
	149	unsigned int rx_coalesce_usecs;
	150	unsigned int last_rx_coalesce_raw;
	151	unsigned int default_rx_coalesce_usecs;
	152	unsigned int sample_interval_usecs;
	153	unsigned int coalesce_enable;
	154	unsigned int polling;
	155	};
	156
559fb51b	157	struct chelsio_pci_params {
8199d3a7 CL	158	unsigned short speed;
	159	unsigned char width;
	160	unsigned char is_pcix;
	161	};
	162
f1d3d38a SH	163	struct tp_params {
	164	unsigned int pm_size;
	165	unsigned int cm_size;
	166	unsigned int pm_rx_base;
	167	unsigned int pm_tx_base;
	168	unsigned int pm_rx_pg_size;
	169	unsigned int pm_tx_pg_size;
	170	unsigned int pm_rx_num_pgs;
	171	unsigned int pm_tx_num_pgs;
	172	unsigned int rx_coalescing_size;
	173	unsigned int use_5tuple_mode;
	174	};
	175
	176	struct mc5_params {
	177	unsigned int mode; /* selects MC5 width */
	178	unsigned int nservers; /* size of server region */
	179	unsigned int nroutes; /* size of routing region */
	180	};
	181
	182	/* Default MC5 region sizes */
	183	#define DEFAULT_SERVER_REGION_LEN 256
	184	#define DEFAULT_RT_REGION_LEN 1024
	185
8199d3a7 CL	186	struct adapter_params {
8199d3a7 CL	187	struct sge_params sge;
f1d3d38a SH	188	struct mc5_params mc5;
f1d3d38a SH	189	struct tp_params tp;
559fb51b	190	struct chelsio_pci_params pci;
8199d3a7 CL	191
	192	const struct board_info *brd_info;
	193
f1d3d38a	194	unsigned short mtus[NMTUS];
559fb51b	195	unsigned int nports; /* # of ethernet ports */
8199d3a7 CL	196	unsigned int stats_update_period;
	197	unsigned short chip_revision;
	198	unsigned char chip_version;
f1d3d38a	199	unsigned char is_asic;
325dde48	200	unsigned char has_msi;
8199d3a7 CL	201	};
	202
	203	struct link_config {
	204	unsigned int supported; /* link capabilities */
	205	unsigned int advertising; /* advertised capabilities */
	206	unsigned short requested_speed; /* speed user has requested */
	207	unsigned short speed; /* actual link speed */
	208	unsigned char requested_duplex; /* duplex user has requested */
	209	unsigned char duplex; /* actual link duplex */
	210	unsigned char requested_fc; /* flow control user has requested */
	211	unsigned char fc; /* actual link flow control */
	212	unsigned char autoneg; /* autonegotiating? */
	213	};
	214
559fb51b SB	215	struct cmac;
	216	struct cphy;
	217
	218	struct port_info {
	219	struct net_device *dev;
	220	struct cmac *mac;
	221	struct cphy *phy;
	222	struct link_config link_config;
	223	struct net_device_stats netstats;
	224	};
	225
	226	struct sge;
	227	struct peespi;
	228
	229	struct adapter {
91fb4c96	230	u8 __iomem *regs;
559fb51b SB	231	struct pci_dev *pdev;
	232	unsigned long registered_device_map;
	233	unsigned long open_device_map;
	234	unsigned long flags;
	235
	236	const char *name;
	237	int msg_enable;
	238	u32 mmio_len;
	239
	240	struct work_struct ext_intr_handler_task;
	241	struct adapter_params params;
	242
	243	struct vlan_group *vlan_grp;
	244
	245	/* Terminator modules. */
	246	struct sge *sge;
	247	struct peespi *espi;
f1d3d38a	248	struct petp *tp;
559fb51b	249
bea3348e	250	struct napi_struct napi;
559fb51b	251	struct port_info port[MAX_NPORTS];
c4028958	252	struct delayed_work stats_update_task;
559fb51b SB	253	struct timer_list stats_update_timer;
559fb51b SB	254
559fb51b SB	255	spinlock_t tpi_lock;
559fb51b SB	256	spinlock_t work_lock;
352c417d SH	257	spinlock_t mac_lock;
352c417d SH	258
559fb51b SB	259	/* guards async operations */
	260	spinlock_t async_lock ____cacheline_aligned;
	261	u32 slow_intr_mask;
f1d3d38a	262	int t1powersave;
559fb51b SB	263	};
	264
	265	enum { /* adapter flags */
	266	FULL_INIT_DONE = 1 << 0,
	267	TSO_CAPABLE = 1 << 2,
	268	TCP_CSUM_CAPABLE = 1 << 3,
	269	UDP_CSUM_CAPABLE = 1 << 4,
	270	VLAN_ACCEL_CAPABLE = 1 << 5,
	271	RX_CSUM_ENABLED = 1 << 6,
	272	};
8199d3a7 CL	273
	274	struct mdio_ops;
	275	struct gmac;
	276	struct gphy;
	277
	278	struct board_info {
	279	unsigned char board;
	280	unsigned char port_number;
	281	unsigned long caps;
	282	unsigned char chip_term;
	283	unsigned char chip_mac;
	284	unsigned char chip_phy;
	285	unsigned int clock_core;
	286	unsigned int clock_mc3;
	287	unsigned int clock_mc4;
	288	unsigned int espi_nports;
	289	unsigned int clock_cspi;
	290	unsigned int clock_elmer0;
	291	unsigned char mdio_mdien;
	292	unsigned char mdio_mdiinv;
	293	unsigned char mdio_mdc;
	294	unsigned char mdio_phybaseaddr;
459e536b SH	295	const struct gmac *gmac;
	296	const struct gphy *gphy;
	297	const struct mdio_ops *mdio_ops;
8199d3a7 CL	298	const char *desc;
	299	};
	300
f1d3d38a SH	301	static inline int t1_is_asic(const adapter_t *adapter)
	302	{
	303	return adapter->params.is_asic;
	304	}
	305
a3aa1884	306	extern const struct pci_device_id t1_pci_tbl[];
8199d3a7	307
8199d3a7 CL	308	static inline int adapter_matches_type(const adapter_t *adapter,
	309	int version, int revision)
	310	{
	311	return adapter->params.chip_version == version &&
	312	adapter->params.chip_revision == revision;
	313	}
	314
	315	#define t1_is_T1B(adap) adapter_matches_type(adap, CHBT_TERM_T1, TERM_T1B)
	316	#define is_T2(adap) adapter_matches_type(adap, CHBT_TERM_T2, TERM_T2)
	317
	318	/* Returns true if an adapter supports VLAN acceleration and TSO */
	319	static inline int vlan_tso_capable(const adapter_t *adapter)
	320	{
	321	return !t1_is_T1B(adapter);
	322	}
	323
	324	#define for_each_port(adapter, iter) \
	325	for (iter = 0; iter < (adapter)->params.nports; ++iter)
	326
	327	#define board_info(adapter) ((adapter)->params.brd_info)
	328	#define is_10G(adapter) (board_info(adapter)->caps & SUPPORTED_10000baseT_Full)
	329
	330	static inline unsigned int core_ticks_per_usec(const adapter_t *adap)
	331	{
	332	return board_info(adap)->clock_core / 1000000;
	333	}
	334
f1d3d38a SH	335	extern int __t1_tpi_read(adapter_t adapter, u32 addr, u32 valp);
f1d3d38a SH	336	extern int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value);
559fb51b SB	337	extern int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value);
559fb51b SB	338	extern int t1_tpi_read(adapter_t adapter, u32 addr, u32 value);
8199d3a7	339
559fb51b SB	340	extern void t1_interrupts_enable(adapter_t *adapter);
	341	extern void t1_interrupts_disable(adapter_t *adapter);
	342	extern void t1_interrupts_clear(adapter_t *adapter);
f1d3d38a	343	extern int t1_elmer0_ext_intr_handler(adapter_t *adapter);
33a85aa1	344	extern void t1_elmer0_ext_intr(adapter_t *adapter);
559fb51b	345	extern int t1_slow_intr_handler(adapter_t *adapter);
8199d3a7	346
559fb51b SB	347	extern int t1_link_start(struct cphy phy, struct cmac mac, struct link_config *lc);
	348	extern const struct board_info *t1_get_board_info(unsigned int board_id);
	349	extern const struct board_info *t1_get_board_info_from_ids(unsigned int devid,
8199d3a7	350	unsigned short ssid);
ac390c60	351	extern int t1_seeprom_read(adapter_t adapter, u32 addr, __le32 data);
559fb51b	352	extern int t1_get_board_rev(adapter_t adapter, const struct board_info bi,
8199d3a7	353	struct adapter_params *p);
559fb51b SB	354	extern int t1_init_hw_modules(adapter_t *adapter);
	355	extern int t1_init_sw_modules(adapter_t adapter, const struct board_info bi);
	356	extern void t1_free_sw_modules(adapter_t *adapter);
	357	extern void t1_fatal_err(adapter_t *adapter);
f1d3d38a SH	358	extern void t1_link_changed(adapter_t *adapter, int port_id);
	359	extern void t1_link_negotiated(adapter_t *adapter, int port_id, int link_stat,
	360	int speed, int duplex, int pause);
559fb51b	361	#endif /* _CXGB_COMMON_H_ */