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bnx2x: New microcode part 3/3
[GitHub/LineageOS/android_kernel_samsung_universal7580.git] / drivers / net / bnx2x_reg.h
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ET		 1/* bnx2x_reg.h: Broadcom Everest network driver.
2 *
f1410647 3 * Copyright (c) 2007-2008 Broadcom Corporation
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ET		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * The registers description starts with the regsister Access type followed
10 * by size in bits. For example [RW 32]. The access types are:
11 * R - Read only
12 * RC - Clear on read
13 * RW - Read/Write
14 * ST - Statistics register (clear on read)
15 * W - Write only
16 * WB - Wide bus register - the size is over 32 bits and it should be
17 * read/write in consecutive 32 bits accesses
18 * WR - Write Clear (write 1 to clear the bit)
19 *
20 */
21
22
23/* [R 19] Interrupt register #0 read */
24#define BRB1_REG_BRB1_INT_STS 0x6011c
25/* [RW 4] Parity mask register #0 read/write */
26#define BRB1_REG_BRB1_PRTY_MASK 0x60138
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ET		 27/* [R 4] Parity register #0 read */
28#define BRB1_REG_BRB1_PRTY_STS 0x6012c
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ET		 29/* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
30 address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address
31 BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. */
32#define BRB1_REG_FREE_LIST_PRS_CRDT 0x60200
33/* [RW 23] LL RAM data. */
34#define BRB1_REG_LL_RAM 0x61000
35/* [R 24] The number of full blocks. */
36#define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090
37/* [ST 32] The number of cycles that the write_full signal towards MAC #0
38 was asserted. */
39#define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8
40#define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc
41#define BRB1_REG_NUM_OF_FULL_CYCLES_2 0x600d0
42#define BRB1_REG_NUM_OF_FULL_CYCLES_3 0x600d4
43#define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8
44/* [ST 32] The number of cycles that the pause signal towards MAC #0 was
45 asserted. */
46#define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8
47#define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc
48#define BRB1_REG_NUM_OF_PAUSE_CYCLES_2 0x600c0
49#define BRB1_REG_NUM_OF_PAUSE_CYCLES_3 0x600c4
50/* [RW 10] Write client 0: De-assert pause threshold. */
51#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078
52#define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c
53/* [RW 10] Write client 0: Assert pause threshold. */
54#define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068
55#define BRB1_REG_PAUSE_LOW_THRESHOLD_1 0x6006c
56/* [RW 1] Reset the design by software. */
57#define BRB1_REG_SOFT_RESET 0x600dc
58/* [R 5] Used to read the value of the XX protection CAM occupancy counter. */
59#define CCM_REG_CAM_OCCUP 0xd0188
60/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
61 acknowledge output is deasserted; all other signals are treated as usual;
62 if 1 - normal activity. */
63#define CCM_REG_CCM_CFC_IFEN 0xd003c
64/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
65 disregarded; valid is deasserted; all other signals are treated as usual;
66 if 1 - normal activity. */
67#define CCM_REG_CCM_CQM_IFEN 0xd000c
68/* [RW 1] If set the Q index; received from the QM is inserted to event ID.
69 Otherwise 0 is inserted. */
70#define CCM_REG_CCM_CQM_USE_Q 0xd00c0
71/* [RW 11] Interrupt mask register #0 read/write */
72#define CCM_REG_CCM_INT_MASK 0xd01e4
73/* [R 11] Interrupt register #0 read */
74#define CCM_REG_CCM_INT_STS 0xd01d8
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YR		 75/* [R 27] Parity register #0 read */
76#define CCM_REG_CCM_PRTY_STS 0xd01e8
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ET		 77/* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
78 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
79 Is used to determine the number of the AG context REG-pairs written back;
80 when the input message Reg1WbFlg isn't set. */
81#define CCM_REG_CCM_REG0_SZ 0xd00c4
82/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
83 disregarded; valid is deasserted; all other signals are treated as usual;
84 if 1 - normal activity. */
85#define CCM_REG_CCM_STORM0_IFEN 0xd0004
86/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
87 disregarded; valid is deasserted; all other signals are treated as usual;
88 if 1 - normal activity. */
89#define CCM_REG_CCM_STORM1_IFEN 0xd0008
90/* [RW 1] CDU AG read Interface enable. If 0 - the request input is
91 disregarded; valid output is deasserted; all other signals are treated as
92 usual; if 1 - normal activity. */
93#define CCM_REG_CDU_AG_RD_IFEN 0xd0030
94/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
95 are disregarded; all other signals are treated as usual; if 1 - normal
96 activity. */
97#define CCM_REG_CDU_AG_WR_IFEN 0xd002c
98/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
99 disregarded; valid output is deasserted; all other signals are treated as
100 usual; if 1 - normal activity. */
101#define CCM_REG_CDU_SM_RD_IFEN 0xd0038
102/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
103 input is disregarded; all other signals are treated as usual; if 1 -
104 normal activity. */
105#define CCM_REG_CDU_SM_WR_IFEN 0xd0034
106/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
107 the initial credit value; read returns the current value of the credit
108 counter. Must be initialized to 1 at start-up. */
109#define CCM_REG_CFC_INIT_CRD 0xd0204
110/* [RW 2] Auxillary counter flag Q number 1. */
111#define CCM_REG_CNT_AUX1_Q 0xd00c8
112/* [RW 2] Auxillary counter flag Q number 2. */
113#define CCM_REG_CNT_AUX2_Q 0xd00cc
114/* [RW 28] The CM header value for QM request (primary). */
115#define CCM_REG_CQM_CCM_HDR_P 0xd008c
116/* [RW 28] The CM header value for QM request (secondary). */
117#define CCM_REG_CQM_CCM_HDR_S 0xd0090
118/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
119 acknowledge output is deasserted; all other signals are treated as usual;
120 if 1 - normal activity. */
121#define CCM_REG_CQM_CCM_IFEN 0xd0014
122/* [RW 6] QM output initial credit. Max credit available - 32. Write writes
123 the initial credit value; read returns the current value of the credit
124 counter. Must be initialized to 32 at start-up. */
125#define CCM_REG_CQM_INIT_CRD 0xd020c
126/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
127 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
128 prioritised); 2 stands for weight 2; tc. */
129#define CCM_REG_CQM_P_WEIGHT 0xd00b8
130/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
131 acknowledge output is deasserted; all other signals are treated as usual;
132 if 1 - normal activity. */
133#define CCM_REG_CSDM_IFEN 0xd0018
134/* [RC 1] Set when the message length mismatch (relative to last indication)
135 at the SDM interface is detected. */
136#define CCM_REG_CSDM_LENGTH_MIS 0xd0170
137/* [RW 28] The CM header for QM formatting in case of an error in the QM
138 inputs. */
139#define CCM_REG_ERR_CCM_HDR 0xd0094
140/* [RW 8] The Event ID in case the input message ErrorFlg is set. */
141#define CCM_REG_ERR_EVNT_ID 0xd0098
142/* [RW 8] FIC0 output initial credit. Max credit available - 255. Write
143 writes the initial credit value; read returns the current value of the
144 credit counter. Must be initialized to 64 at start-up. */
145#define CCM_REG_FIC0_INIT_CRD 0xd0210
146/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
147 writes the initial credit value; read returns the current value of the
148 credit counter. Must be initialized to 64 at start-up. */
149#define CCM_REG_FIC1_INIT_CRD 0xd0214
150/* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
151 - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr;
152 ~ccm_registers_gr_ld0_pr.gr_ld0_pr and
153 ~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and
154 outputs to STORM: aggregation; load FIC0; load FIC1 and store. */
155#define CCM_REG_GR_ARB_TYPE 0xd015c
156/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
157 highest priority is 3. It is supposed; that the Store channel priority is
158 the compliment to 4 of the rest priorities - Aggregation channel; Load
159 (FIC0) channel and Load (FIC1). */
160#define CCM_REG_GR_LD0_PR 0xd0164
161/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
162 highest priority is 3. It is supposed; that the Store channel priority is
163 the compliment to 4 of the rest priorities - Aggregation channel; Load
164 (FIC0) channel and Load (FIC1). */
165#define CCM_REG_GR_LD1_PR 0xd0168
166/* [RW 2] General flags index. */
167#define CCM_REG_INV_DONE_Q 0xd0108
168/* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM
169 context and sent to STORM; for a specific connection type. The double
170 REG-pairs are used in order to align to STORM context row size of 128
171 bits. The offset of these data in the STORM context is always 0. Index
172 _(0..15) stands for the connection type (one of 16). */
173#define CCM_REG_N_SM_CTX_LD_0 0xd004c
174#define CCM_REG_N_SM_CTX_LD_1 0xd0050
175#define CCM_REG_N_SM_CTX_LD_10 0xd0074
176#define CCM_REG_N_SM_CTX_LD_11 0xd0078
177#define CCM_REG_N_SM_CTX_LD_12 0xd007c
178#define CCM_REG_N_SM_CTX_LD_13 0xd0080
179#define CCM_REG_N_SM_CTX_LD_14 0xd0084
180#define CCM_REG_N_SM_CTX_LD_15 0xd0088
181#define CCM_REG_N_SM_CTX_LD_2 0xd0054
182#define CCM_REG_N_SM_CTX_LD_3 0xd0058
183#define CCM_REG_N_SM_CTX_LD_4 0xd005c
184/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
185 acknowledge output is deasserted; all other signals are treated as usual;
186 if 1 - normal activity. */
187#define CCM_REG_PBF_IFEN 0xd0028
188/* [RC 1] Set when the message length mismatch (relative to last indication)
189 at the pbf interface is detected. */
190#define CCM_REG_PBF_LENGTH_MIS 0xd0180
191/* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
192 weight 8 (the most prioritised); 1 stands for weight 1(least
193 prioritised); 2 stands for weight 2; tc. */
194#define CCM_REG_PBF_WEIGHT 0xd00ac
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ET		 195#define CCM_REG_PHYS_QNUM1_0 0xd0134
196#define CCM_REG_PHYS_QNUM1_1 0xd0138
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ET		 197#define CCM_REG_PHYS_QNUM2_0 0xd013c
198#define CCM_REG_PHYS_QNUM2_1 0xd0140
a2fbb9ea 199#define CCM_REG_PHYS_QNUM3_0 0xd0144
c18487ee 200#define CCM_REG_PHYS_QNUM3_1 0xd0148
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ET		 201#define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114
202#define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118
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ET		 203#define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c
204#define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120
a2fbb9ea 205#define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124
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YR		 206#define CCM_REG_QOS_PHYS_QNUM2_1 0xd0128
207#define CCM_REG_QOS_PHYS_QNUM3_0 0xd012c
208#define CCM_REG_QOS_PHYS_QNUM3_1 0xd0130
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ET		 209/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
210 disregarded; acknowledge output is deasserted; all other signals are
211 treated as usual; if 1 - normal activity. */
212#define CCM_REG_STORM_CCM_IFEN 0xd0010
213/* [RC 1] Set when the message length mismatch (relative to last indication)
214 at the STORM interface is detected. */
215#define CCM_REG_STORM_LENGTH_MIS 0xd016c
216/* [RW 1] Input tsem Interface enable. If 0 - the valid input is
217 disregarded; acknowledge output is deasserted; all other signals are
218 treated as usual; if 1 - normal activity. */
219#define CCM_REG_TSEM_IFEN 0xd001c
220/* [RC 1] Set when the message length mismatch (relative to last indication)
221 at the tsem interface is detected. */
222#define CCM_REG_TSEM_LENGTH_MIS 0xd0174
223/* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
224 weight 8 (the most prioritised); 1 stands for weight 1(least
225 prioritised); 2 stands for weight 2; tc. */
226#define CCM_REG_TSEM_WEIGHT 0xd00a0
227/* [RW 1] Input usem Interface enable. If 0 - the valid input is
228 disregarded; acknowledge output is deasserted; all other signals are
229 treated as usual; if 1 - normal activity. */
230#define CCM_REG_USEM_IFEN 0xd0024
231/* [RC 1] Set when message length mismatch (relative to last indication) at
232 the usem interface is detected. */
233#define CCM_REG_USEM_LENGTH_MIS 0xd017c
234/* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
235 weight 8 (the most prioritised); 1 stands for weight 1(least
236 prioritised); 2 stands for weight 2; tc. */
237#define CCM_REG_USEM_WEIGHT 0xd00a8
238/* [RW 1] Input xsem Interface enable. If 0 - the valid input is
239 disregarded; acknowledge output is deasserted; all other signals are
240 treated as usual; if 1 - normal activity. */
241#define CCM_REG_XSEM_IFEN 0xd0020
242/* [RC 1] Set when the message length mismatch (relative to last indication)
243 at the xsem interface is detected. */
244#define CCM_REG_XSEM_LENGTH_MIS 0xd0178
245/* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
246 weight 8 (the most prioritised); 1 stands for weight 1(least
247 prioritised); 2 stands for weight 2; tc. */
248#define CCM_REG_XSEM_WEIGHT 0xd00a4
249/* [RW 19] Indirect access to the descriptor table of the XX protection
250 mechanism. The fields are: [5:0] - message length; [12:6] - message
251 pointer; 18:13] - next pointer. */
252#define CCM_REG_XX_DESCR_TABLE 0xd0300
c18487ee 253#define CCM_REG_XX_DESCR_TABLE_SIZE 36
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ET		 254/* [R 7] Used to read the value of XX protection Free counter. */
255#define CCM_REG_XX_FREE 0xd0184
256/* [RW 6] Initial value for the credit counter; responsible for fulfilling
257 of the Input Stage XX protection buffer by the XX protection pending
258 messages. Max credit available - 127. Write writes the initial credit
259 value; read returns the current value of the credit counter. Must be
260 initialized to maximum XX protected message size - 2 at start-up. */
261#define CCM_REG_XX_INIT_CRD 0xd0220
262/* [RW 7] The maximum number of pending messages; which may be stored in XX
263 protection. At read the ~ccm_registers_xx_free.xx_free counter is read.
264 At write comprises the start value of the ~ccm_registers_xx_free.xx_free
265 counter. */
266#define CCM_REG_XX_MSG_NUM 0xd0224
267/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
268#define CCM_REG_XX_OVFL_EVNT_ID 0xd0044
269/* [RW 18] Indirect access to the XX table of the XX protection mechanism.
270 The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] -
271 header pointer. */
272#define CCM_REG_XX_TABLE 0xd0280
273#define CDU_REG_CDU_CHK_MASK0 0x101000
274#define CDU_REG_CDU_CHK_MASK1 0x101004
275#define CDU_REG_CDU_CONTROL0 0x101008
276#define CDU_REG_CDU_DEBUG 0x101010
277#define CDU_REG_CDU_GLOBAL_PARAMS 0x101020
278/* [RW 7] Interrupt mask register #0 read/write */
279#define CDU_REG_CDU_INT_MASK 0x10103c
280/* [R 7] Interrupt register #0 read */
281#define CDU_REG_CDU_INT_STS 0x101030
282/* [RW 5] Parity mask register #0 read/write */
283#define CDU_REG_CDU_PRTY_MASK 0x10104c
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ET		 284/* [R 5] Parity register #0 read */
285#define CDU_REG_CDU_PRTY_STS 0x101040
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ET		 286/* [RC 32] logging of error data in case of a CDU load error:
287 {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error;
288 ype_error; ctual_active; ctual_compressed_context}; */
289#define CDU_REG_ERROR_DATA 0x101014
290/* [WB 216] L1TT ram access. each entry has the following format :
291 {mrege_regions[7:0]; ffset12[5:0]...offset0[5:0];
292 ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */
293#define CDU_REG_L1TT 0x101800
294/* [WB 24] MATT ram access. each entry has the following
295 format:{RegionLength[11:0]; egionOffset[11:0]} */
296#define CDU_REG_MATT 0x101100
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YR		 297/* [RW 1] when this bit is set the CDU operates in e1hmf mode */
298#define CDU_REG_MF_MODE 0x101050
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ET		 299/* [R 1] indication the initializing the activity counter by the hardware
300 was done. */
301#define CFC_REG_AC_INIT_DONE 0x104078
302/* [RW 13] activity counter ram access */
303#define CFC_REG_ACTIVITY_COUNTER 0x104400
304#define CFC_REG_ACTIVITY_COUNTER_SIZE 256
305/* [R 1] indication the initializing the cams by the hardware was done. */
306#define CFC_REG_CAM_INIT_DONE 0x10407c
307/* [RW 2] Interrupt mask register #0 read/write */
308#define CFC_REG_CFC_INT_MASK 0x104108
309/* [R 2] Interrupt register #0 read */
310#define CFC_REG_CFC_INT_STS 0x1040fc
311/* [RC 2] Interrupt register #0 read clear */
312#define CFC_REG_CFC_INT_STS_CLR 0x104100
313/* [RW 4] Parity mask register #0 read/write */
314#define CFC_REG_CFC_PRTY_MASK 0x104118
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ET		 315/* [R 4] Parity register #0 read */
316#define CFC_REG_CFC_PRTY_STS 0x10410c
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ET		 317/* [RW 21] CID cam access (21:1 - Data; alid - 0) */
318#define CFC_REG_CID_CAM 0x104800
319#define CFC_REG_CONTROL0 0x104028
320#define CFC_REG_DEBUG0 0x104050
321/* [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error
322 vector) whether the cfc should be disabled upon it */
323#define CFC_REG_DISABLE_ON_ERROR 0x104044
324/* [RC 14] CFC error vector. when the CFC detects an internal error it will
325 set one of these bits. the bit description can be found in CFC
326 specifications */
327#define CFC_REG_ERROR_VECTOR 0x10403c
328#define CFC_REG_INIT_REG 0x10404c
329/* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this
330 field allows changing the priorities of the weighted-round-robin arbiter
331 which selects which CFC load client should be served next */
332#define CFC_REG_LCREQ_WEIGHTS 0x104084
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YR		 333/* [RW 16] Link List ram access; data = {prev_lcid; ext_lcid} */
334#define CFC_REG_LINK_LIST 0x104c00
335#define CFC_REG_LINK_LIST_SIZE 256
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ET		 336/* [R 1] indication the initializing the link list by the hardware was done. */
337#define CFC_REG_LL_INIT_DONE 0x104074
338/* [R 9] Number of allocated LCIDs which are at empty state */
339#define CFC_REG_NUM_LCIDS_ALLOC 0x104020
340/* [R 9] Number of Arriving LCIDs in Link List Block */
341#define CFC_REG_NUM_LCIDS_ARRIVING 0x104004
342/* [R 9] Number of Inside LCIDs in Link List Block */
343#define CFC_REG_NUM_LCIDS_INSIDE 0x104008
344/* [R 9] Number of Leaving LCIDs in Link List Block */
345#define CFC_REG_NUM_LCIDS_LEAVING 0x104018
346/* [RW 8] The event id for aggregated interrupt 0 */
347#define CSDM_REG_AGG_INT_EVENT_0 0xc2038
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YR		 348#define CSDM_REG_AGG_INT_EVENT_1 0xc203c
349#define CSDM_REG_AGG_INT_EVENT_10 0xc2060
350#define CSDM_REG_AGG_INT_EVENT_11 0xc2064
351#define CSDM_REG_AGG_INT_EVENT_12 0xc2068
352#define CSDM_REG_AGG_INT_EVENT_13 0xc206c
353#define CSDM_REG_AGG_INT_EVENT_14 0xc2070
354#define CSDM_REG_AGG_INT_EVENT_15 0xc2074
355#define CSDM_REG_AGG_INT_EVENT_16 0xc2078
356#define CSDM_REG_AGG_INT_EVENT_17 0xc207c
357#define CSDM_REG_AGG_INT_EVENT_18 0xc2080
358#define CSDM_REG_AGG_INT_EVENT_19 0xc2084
359#define CSDM_REG_AGG_INT_EVENT_2 0xc2040
360#define CSDM_REG_AGG_INT_EVENT_20 0xc2088
361#define CSDM_REG_AGG_INT_EVENT_21 0xc208c
362#define CSDM_REG_AGG_INT_EVENT_22 0xc2090
363#define CSDM_REG_AGG_INT_EVENT_23 0xc2094
364#define CSDM_REG_AGG_INT_EVENT_24 0xc2098
365#define CSDM_REG_AGG_INT_EVENT_25 0xc209c
366#define CSDM_REG_AGG_INT_EVENT_26 0xc20a0
367#define CSDM_REG_AGG_INT_EVENT_27 0xc20a4
368#define CSDM_REG_AGG_INT_EVENT_28 0xc20a8
369#define CSDM_REG_AGG_INT_EVENT_29 0xc20ac
370#define CSDM_REG_AGG_INT_EVENT_3 0xc2044
371#define CSDM_REG_AGG_INT_EVENT_30 0xc20b0
372#define CSDM_REG_AGG_INT_EVENT_31 0xc20b4
373#define CSDM_REG_AGG_INT_EVENT_4 0xc2048
374/* [RW 1] The T bit for aggregated interrupt 0 */
375#define CSDM_REG_AGG_INT_T_0 0xc20b8
376#define CSDM_REG_AGG_INT_T_1 0xc20bc
377#define CSDM_REG_AGG_INT_T_10 0xc20e0
378#define CSDM_REG_AGG_INT_T_11 0xc20e4
379#define CSDM_REG_AGG_INT_T_12 0xc20e8
380#define CSDM_REG_AGG_INT_T_13 0xc20ec
381#define CSDM_REG_AGG_INT_T_14 0xc20f0
382#define CSDM_REG_AGG_INT_T_15 0xc20f4
383#define CSDM_REG_AGG_INT_T_16 0xc20f8
384#define CSDM_REG_AGG_INT_T_17 0xc20fc
385#define CSDM_REG_AGG_INT_T_18 0xc2100
386#define CSDM_REG_AGG_INT_T_19 0xc2104
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ET		 387/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
388#define CSDM_REG_CFC_RSP_START_ADDR 0xc2008
389/* [RW 16] The maximum value of the competion counter #0 */
390#define CSDM_REG_CMP_COUNTER_MAX0 0xc201c
391/* [RW 16] The maximum value of the competion counter #1 */
392#define CSDM_REG_CMP_COUNTER_MAX1 0xc2020
393/* [RW 16] The maximum value of the competion counter #2 */
394#define CSDM_REG_CMP_COUNTER_MAX2 0xc2024
395/* [RW 16] The maximum value of the competion counter #3 */
396#define CSDM_REG_CMP_COUNTER_MAX3 0xc2028
397/* [RW 13] The start address in the internal RAM for the completion
398 counters. */
399#define CSDM_REG_CMP_COUNTER_START_ADDR 0xc200c
400/* [RW 32] Interrupt mask register #0 read/write */
401#define CSDM_REG_CSDM_INT_MASK_0 0xc229c
402#define CSDM_REG_CSDM_INT_MASK_1 0xc22ac
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YR		 403/* [R 32] Interrupt register #0 read */
404#define CSDM_REG_CSDM_INT_STS_0 0xc2290
405#define CSDM_REG_CSDM_INT_STS_1 0xc22a0
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ET		 406/* [RW 11] Parity mask register #0 read/write */
407#define CSDM_REG_CSDM_PRTY_MASK 0xc22bc
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ET		 408/* [R 11] Parity register #0 read */
409#define CSDM_REG_CSDM_PRTY_STS 0xc22b0
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ET		 410#define CSDM_REG_ENABLE_IN1 0xc2238
411#define CSDM_REG_ENABLE_IN2 0xc223c
412#define CSDM_REG_ENABLE_OUT1 0xc2240
413#define CSDM_REG_ENABLE_OUT2 0xc2244
414/* [RW 4] The initial number of messages that can be sent to the pxp control
415 interface without receiving any ACK. */
416#define CSDM_REG_INIT_CREDIT_PXP_CTRL 0xc24bc
417/* [ST 32] The number of ACK after placement messages received */
418#define CSDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc227c
419/* [ST 32] The number of packet end messages received from the parser */
420#define CSDM_REG_NUM_OF_PKT_END_MSG 0xc2274
421/* [ST 32] The number of requests received from the pxp async if */
422#define CSDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc2278
423/* [ST 32] The number of commands received in queue 0 */
424#define CSDM_REG_NUM_OF_Q0_CMD 0xc2248
425/* [ST 32] The number of commands received in queue 10 */
426#define CSDM_REG_NUM_OF_Q10_CMD 0xc226c
427/* [ST 32] The number of commands received in queue 11 */
428#define CSDM_REG_NUM_OF_Q11_CMD 0xc2270
429/* [ST 32] The number of commands received in queue 1 */
430#define CSDM_REG_NUM_OF_Q1_CMD 0xc224c
431/* [ST 32] The number of commands received in queue 3 */
432#define CSDM_REG_NUM_OF_Q3_CMD 0xc2250
433/* [ST 32] The number of commands received in queue 4 */
434#define CSDM_REG_NUM_OF_Q4_CMD 0xc2254
435/* [ST 32] The number of commands received in queue 5 */
436#define CSDM_REG_NUM_OF_Q5_CMD 0xc2258
437/* [ST 32] The number of commands received in queue 6 */
438#define CSDM_REG_NUM_OF_Q6_CMD 0xc225c
439/* [ST 32] The number of commands received in queue 7 */
440#define CSDM_REG_NUM_OF_Q7_CMD 0xc2260
441/* [ST 32] The number of commands received in queue 8 */
442#define CSDM_REG_NUM_OF_Q8_CMD 0xc2264
443/* [ST 32] The number of commands received in queue 9 */
444#define CSDM_REG_NUM_OF_Q9_CMD 0xc2268
445/* [RW 13] The start address in the internal RAM for queue counters */
446#define CSDM_REG_Q_COUNTER_START_ADDR 0xc2010
447/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
448#define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548
449/* [R 1] parser fifo empty in sdm_sync block */
450#define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550
451/* [R 1] parser serial fifo empty in sdm_sync block */
452#define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558
453/* [RW 32] Tick for timer counter. Applicable only when
454 ~csdm_registers_timer_tick_enable.timer_tick_enable =1 */
455#define CSDM_REG_TIMER_TICK 0xc2000
456/* [RW 5] The number of time_slots in the arbitration cycle */
457#define CSEM_REG_ARB_CYCLE_SIZE 0x200034
458/* [RW 3] The source that is associated with arbitration element 0. Source
459 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
460 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
461#define CSEM_REG_ARB_ELEMENT0 0x200020
462/* [RW 3] The source that is associated with arbitration element 1. Source
463 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
464 sleeping thread with priority 1; 4- sleeping thread with priority 2.
465 Could not be equal to register ~csem_registers_arb_element0.arb_element0 */
466#define CSEM_REG_ARB_ELEMENT1 0x200024
467/* [RW 3] The source that is associated with arbitration element 2. Source
468 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
469 sleeping thread with priority 1; 4- sleeping thread with priority 2.
470 Could not be equal to register ~csem_registers_arb_element0.arb_element0
471 and ~csem_registers_arb_element1.arb_element1 */
472#define CSEM_REG_ARB_ELEMENT2 0x200028
473/* [RW 3] The source that is associated with arbitration element 3. Source
474 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
475 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
476 not be equal to register ~csem_registers_arb_element0.arb_element0 and
477 ~csem_registers_arb_element1.arb_element1 and
478 ~csem_registers_arb_element2.arb_element2 */
479#define CSEM_REG_ARB_ELEMENT3 0x20002c
480/* [RW 3] The source that is associated with arbitration element 4. Source
481 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
482 sleeping thread with priority 1; 4- sleeping thread with priority 2.
483 Could not be equal to register ~csem_registers_arb_element0.arb_element0
484 and ~csem_registers_arb_element1.arb_element1 and
485 ~csem_registers_arb_element2.arb_element2 and
486 ~csem_registers_arb_element3.arb_element3 */
487#define CSEM_REG_ARB_ELEMENT4 0x200030
488/* [RW 32] Interrupt mask register #0 read/write */
489#define CSEM_REG_CSEM_INT_MASK_0 0x200110
490#define CSEM_REG_CSEM_INT_MASK_1 0x200120
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YR		 491/* [R 32] Interrupt register #0 read */
492#define CSEM_REG_CSEM_INT_STS_0 0x200104
493#define CSEM_REG_CSEM_INT_STS_1 0x200114
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ET		 494/* [RW 32] Parity mask register #0 read/write */
495#define CSEM_REG_CSEM_PRTY_MASK_0 0x200130
496#define CSEM_REG_CSEM_PRTY_MASK_1 0x200140
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ET		 497/* [R 32] Parity register #0 read */
498#define CSEM_REG_CSEM_PRTY_STS_0 0x200124
499#define CSEM_REG_CSEM_PRTY_STS_1 0x200134
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ET		 500#define CSEM_REG_ENABLE_IN 0x2000a4
501#define CSEM_REG_ENABLE_OUT 0x2000a8
502/* [RW 32] This address space contains all registers and memories that are
503 placed in SEM_FAST block. The SEM_FAST registers are described in
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YR		 504 appendix B. In order to access the sem_fast registers the base address
505 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
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ET		 506#define CSEM_REG_FAST_MEMORY 0x220000
507/* [RW 1] Disables input messages from FIC0 May be updated during run_time
508 by the microcode */
509#define CSEM_REG_FIC0_DISABLE 0x200224
510/* [RW 1] Disables input messages from FIC1 May be updated during run_time
511 by the microcode */
512#define CSEM_REG_FIC1_DISABLE 0x200234
513/* [RW 15] Interrupt table Read and write access to it is not possible in
514 the middle of the work */
515#define CSEM_REG_INT_TABLE 0x200400
c18487ee 516#define CSEM_REG_INT_TABLE_SIZE 256
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ET		 517/* [ST 24] Statistics register. The number of messages that entered through
518 FIC0 */
519#define CSEM_REG_MSG_NUM_FIC0 0x200000
520/* [ST 24] Statistics register. The number of messages that entered through
521 FIC1 */
522#define CSEM_REG_MSG_NUM_FIC1 0x200004
523/* [ST 24] Statistics register. The number of messages that were sent to
524 FOC0 */
525#define CSEM_REG_MSG_NUM_FOC0 0x200008
526/* [ST 24] Statistics register. The number of messages that were sent to
527 FOC1 */
528#define CSEM_REG_MSG_NUM_FOC1 0x20000c
529/* [ST 24] Statistics register. The number of messages that were sent to
530 FOC2 */
531#define CSEM_REG_MSG_NUM_FOC2 0x200010
532/* [ST 24] Statistics register. The number of messages that were sent to
533 FOC3 */
534#define CSEM_REG_MSG_NUM_FOC3 0x200014
535/* [RW 1] Disables input messages from the passive buffer May be updated
536 during run_time by the microcode */
537#define CSEM_REG_PAS_DISABLE 0x20024c
538/* [WB 128] Debug only. Passive buffer memory */
539#define CSEM_REG_PASSIVE_BUFFER 0x202000
540/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
541#define CSEM_REG_PRAM 0x240000
542/* [R 16] Valid sleeping threads indication have bit per thread */
543#define CSEM_REG_SLEEP_THREADS_VALID 0x20026c
544/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
545#define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0
546/* [RW 16] List of free threads . There is a bit per thread. */
547#define CSEM_REG_THREADS_LIST 0x2002e4
548/* [RW 3] The arbitration scheme of time_slot 0 */
549#define CSEM_REG_TS_0_AS 0x200038
550/* [RW 3] The arbitration scheme of time_slot 10 */
551#define CSEM_REG_TS_10_AS 0x200060
552/* [RW 3] The arbitration scheme of time_slot 11 */
553#define CSEM_REG_TS_11_AS 0x200064
554/* [RW 3] The arbitration scheme of time_slot 12 */
555#define CSEM_REG_TS_12_AS 0x200068
556/* [RW 3] The arbitration scheme of time_slot 13 */
557#define CSEM_REG_TS_13_AS 0x20006c
558/* [RW 3] The arbitration scheme of time_slot 14 */
559#define CSEM_REG_TS_14_AS 0x200070
560/* [RW 3] The arbitration scheme of time_slot 15 */
561#define CSEM_REG_TS_15_AS 0x200074
562/* [RW 3] The arbitration scheme of time_slot 16 */
563#define CSEM_REG_TS_16_AS 0x200078
564/* [RW 3] The arbitration scheme of time_slot 17 */
565#define CSEM_REG_TS_17_AS 0x20007c
566/* [RW 3] The arbitration scheme of time_slot 18 */
567#define CSEM_REG_TS_18_AS 0x200080
568/* [RW 3] The arbitration scheme of time_slot 1 */
569#define CSEM_REG_TS_1_AS 0x20003c
570/* [RW 3] The arbitration scheme of time_slot 2 */
571#define CSEM_REG_TS_2_AS 0x200040
572/* [RW 3] The arbitration scheme of time_slot 3 */
573#define CSEM_REG_TS_3_AS 0x200044
574/* [RW 3] The arbitration scheme of time_slot 4 */
575#define CSEM_REG_TS_4_AS 0x200048
576/* [RW 3] The arbitration scheme of time_slot 5 */
577#define CSEM_REG_TS_5_AS 0x20004c
578/* [RW 3] The arbitration scheme of time_slot 6 */
579#define CSEM_REG_TS_6_AS 0x200050
580/* [RW 3] The arbitration scheme of time_slot 7 */
581#define CSEM_REG_TS_7_AS 0x200054
582/* [RW 3] The arbitration scheme of time_slot 8 */
583#define CSEM_REG_TS_8_AS 0x200058
584/* [RW 3] The arbitration scheme of time_slot 9 */
585#define CSEM_REG_TS_9_AS 0x20005c
586/* [RW 1] Parity mask register #0 read/write */
587#define DBG_REG_DBG_PRTY_MASK 0xc0a8
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ET		 588/* [R 1] Parity register #0 read */
589#define DBG_REG_DBG_PRTY_STS 0xc09c
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ET		 590/* [RW 2] debug only: These bits indicate the credit for PCI request type 4
591 interface; MUST be configured AFTER pci_ext_buffer_strt_addr_lsb/msb are
592 configured */
593#define DBG_REG_PCI_REQ_CREDIT 0xc120
594/* [RW 32] Commands memory. The address to command X; row Y is to calculated
595 as 14*X+Y. */
596#define DMAE_REG_CMD_MEM 0x102400
597/* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c
598 initial value is all ones. */
599#define DMAE_REG_CRC16C_INIT 0x10201c
600/* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the
601 CRC-16 T10 initial value is all ones. */
602#define DMAE_REG_CRC16T10_INIT 0x102020
603/* [RW 2] Interrupt mask register #0 read/write */
604#define DMAE_REG_DMAE_INT_MASK 0x102054
605/* [RW 4] Parity mask register #0 read/write */
606#define DMAE_REG_DMAE_PRTY_MASK 0x102064
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ET		 607/* [R 4] Parity register #0 read */
608#define DMAE_REG_DMAE_PRTY_STS 0x102058
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ET		 609/* [RW 1] Command 0 go. */
610#define DMAE_REG_GO_C0 0x102080
611/* [RW 1] Command 1 go. */
612#define DMAE_REG_GO_C1 0x102084
613/* [RW 1] Command 10 go. */
614#define DMAE_REG_GO_C10 0x102088
615#define DMAE_REG_GO_C10_SIZE 1
616/* [RW 1] Command 11 go. */
617#define DMAE_REG_GO_C11 0x10208c
618#define DMAE_REG_GO_C11_SIZE 1
619/* [RW 1] Command 12 go. */
620#define DMAE_REG_GO_C12 0x102090
621#define DMAE_REG_GO_C12_SIZE 1
622/* [RW 1] Command 13 go. */
623#define DMAE_REG_GO_C13 0x102094
624#define DMAE_REG_GO_C13_SIZE 1
625/* [RW 1] Command 14 go. */
626#define DMAE_REG_GO_C14 0x102098
627#define DMAE_REG_GO_C14_SIZE 1
628/* [RW 1] Command 15 go. */
629#define DMAE_REG_GO_C15 0x10209c
630#define DMAE_REG_GO_C15_SIZE 1
631/* [RW 1] Command 10 go. */
632#define DMAE_REG_GO_C10 0x102088
633/* [RW 1] Command 11 go. */
634#define DMAE_REG_GO_C11 0x10208c
635/* [RW 1] Command 12 go. */
636#define DMAE_REG_GO_C12 0x102090
637/* [RW 1] Command 13 go. */
638#define DMAE_REG_GO_C13 0x102094
639/* [RW 1] Command 14 go. */
640#define DMAE_REG_GO_C14 0x102098
641/* [RW 1] Command 15 go. */
642#define DMAE_REG_GO_C15 0x10209c
643/* [RW 1] Command 2 go. */
644#define DMAE_REG_GO_C2 0x1020a0
645/* [RW 1] Command 3 go. */
646#define DMAE_REG_GO_C3 0x1020a4
647/* [RW 1] Command 4 go. */
648#define DMAE_REG_GO_C4 0x1020a8
649/* [RW 1] Command 5 go. */
650#define DMAE_REG_GO_C5 0x1020ac
651/* [RW 1] Command 6 go. */
652#define DMAE_REG_GO_C6 0x1020b0
653/* [RW 1] Command 7 go. */
654#define DMAE_REG_GO_C7 0x1020b4
655/* [RW 1] Command 8 go. */
656#define DMAE_REG_GO_C8 0x1020b8
657/* [RW 1] Command 9 go. */
658#define DMAE_REG_GO_C9 0x1020bc
659/* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge
660 input is disregarded; valid is deasserted; all other signals are treated
661 as usual; if 1 - normal activity. */
662#define DMAE_REG_GRC_IFEN 0x102008
663/* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the
664 acknowledge input is disregarded; valid is deasserted; full is asserted;
665 all other signals are treated as usual; if 1 - normal activity. */
666#define DMAE_REG_PCI_IFEN 0x102004
667/* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the
668 initial value to the credit counter; related to the address. Read returns
669 the current value of the counter. */
670#define DMAE_REG_PXP_REQ_INIT_CRD 0x1020c0
671/* [RW 8] Aggregation command. */
672#define DORQ_REG_AGG_CMD0 0x170060
673/* [RW 8] Aggregation command. */
674#define DORQ_REG_AGG_CMD1 0x170064
675/* [RW 8] Aggregation command. */
676#define DORQ_REG_AGG_CMD2 0x170068
677/* [RW 8] Aggregation command. */
678#define DORQ_REG_AGG_CMD3 0x17006c
679/* [RW 28] UCM Header. */
680#define DORQ_REG_CMHEAD_RX 0x170050
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YR		 681/* [RW 32] Doorbell address for RBC doorbells (function 0). */
682#define DORQ_REG_DB_ADDR0 0x17008c
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ET		 683/* [RW 5] Interrupt mask register #0 read/write */
684#define DORQ_REG_DORQ_INT_MASK 0x170180
685/* [R 5] Interrupt register #0 read */
686#define DORQ_REG_DORQ_INT_STS 0x170174
687/* [RC 5] Interrupt register #0 read clear */
688#define DORQ_REG_DORQ_INT_STS_CLR 0x170178
689/* [RW 2] Parity mask register #0 read/write */
690#define DORQ_REG_DORQ_PRTY_MASK 0x170190
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ET		 691/* [R 2] Parity register #0 read */
692#define DORQ_REG_DORQ_PRTY_STS 0x170184
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ET		 693/* [RW 8] The address to write the DPM CID to STORM. */
694#define DORQ_REG_DPM_CID_ADDR 0x170044
695/* [RW 5] The DPM mode CID extraction offset. */
696#define DORQ_REG_DPM_CID_OFST 0x170030
697/* [RW 12] The threshold of the DQ FIFO to send the almost full interrupt. */
698#define DORQ_REG_DQ_FIFO_AFULL_TH 0x17007c
699/* [RW 12] The threshold of the DQ FIFO to send the full interrupt. */
700#define DORQ_REG_DQ_FIFO_FULL_TH 0x170078
701/* [R 13] Current value of the DQ FIFO fill level according to following
702 pointer. The range is 0 - 256 FIFO rows; where each row stands for the
703 doorbell. */
704#define DORQ_REG_DQ_FILL_LVLF 0x1700a4
705/* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or
706 equal to full threshold; reset on full clear. */
707#define DORQ_REG_DQ_FULL_ST 0x1700c0
708/* [RW 28] The value sent to CM header in the case of CFC load error. */
709#define DORQ_REG_ERR_CMHEAD 0x170058
710#define DORQ_REG_IF_EN 0x170004
711#define DORQ_REG_MODE_ACT 0x170008
712/* [RW 5] The normal mode CID extraction offset. */
713#define DORQ_REG_NORM_CID_OFST 0x17002c
714/* [RW 28] TCM Header when only TCP context is loaded. */
715#define DORQ_REG_NORM_CMHEAD_TX 0x17004c
716/* [RW 3] The number of simultaneous outstanding requests to Context Fetch
717 Interface. */
718#define DORQ_REG_OUTST_REQ 0x17003c
719#define DORQ_REG_REGN 0x170038
720/* [R 4] Current value of response A counter credit. Initial credit is
721 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
722 register. */
723#define DORQ_REG_RSPA_CRD_CNT 0x1700ac
724/* [R 4] Current value of response B counter credit. Initial credit is
725 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
726 register. */
727#define DORQ_REG_RSPB_CRD_CNT 0x1700b0
728/* [RW 4] The initial credit at the Doorbell Response Interface. The write
729 writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The
730 read reads this written value. */
731#define DORQ_REG_RSP_INIT_CRD 0x170048
732/* [RW 4] Initial activity counter value on the load request; when the
733 shortcut is done. */
734#define DORQ_REG_SHRT_ACT_CNT 0x170070
735/* [RW 28] TCM Header when both ULP and TCP context is loaded. */
736#define DORQ_REG_SHRT_CMHEAD 0x170054
737#define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4)
738#define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3)
739#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2)
740#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1)
741#define HC_REG_AGG_INT_0 0x108050
742#define HC_REG_AGG_INT_1 0x108054
a2fbb9ea 743#define HC_REG_ATTN_BIT 0x108120
a2fbb9ea 744#define HC_REG_ATTN_IDX 0x108100
a2fbb9ea 745#define HC_REG_ATTN_MSG0_ADDR_L 0x108018
a2fbb9ea 746#define HC_REG_ATTN_MSG1_ADDR_L 0x108020
a2fbb9ea 747#define HC_REG_ATTN_NUM_P0 0x108038
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ET		 748#define HC_REG_ATTN_NUM_P1 0x10803c
749#define HC_REG_CONFIG_0 0x108000
750#define HC_REG_CONFIG_1 0x108004
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YR		 751#define HC_REG_FUNC_NUM_P0 0x1080ac
752#define HC_REG_FUNC_NUM_P1 0x1080b0
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ET		 753/* [RW 3] Parity mask register #0 read/write */
754#define HC_REG_HC_PRTY_MASK 0x1080a0
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ET		 755/* [R 3] Parity register #0 read */
756#define HC_REG_HC_PRTY_STS 0x108094
a2fbb9ea 757#define HC_REG_INT_MASK 0x108108
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ET		 758#define HC_REG_LEADING_EDGE_0 0x108040
759#define HC_REG_LEADING_EDGE_1 0x108048
a2fbb9ea 760#define HC_REG_P0_PROD_CONS 0x108200
a2fbb9ea 761#define HC_REG_P1_PROD_CONS 0x108400
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ET		 762#define HC_REG_PBA_COMMAND 0x108140
763#define HC_REG_PCI_CONFIG_0 0x108010
764#define HC_REG_PCI_CONFIG_1 0x108014
a2fbb9ea 765#define HC_REG_STATISTIC_COUNTERS 0x109000
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ET		 766#define HC_REG_TRAILING_EDGE_0 0x108044
767#define HC_REG_TRAILING_EDGE_1 0x10804c
768#define HC_REG_UC_RAM_ADDR_0 0x108028
769#define HC_REG_UC_RAM_ADDR_1 0x108030
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ET		 770#define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068
771#define HC_REG_VQID_0 0x108008
772#define HC_REG_VQID_1 0x10800c
773#define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x86424
774#define MCP_REG_MCPR_NVM_ADDR 0x8640c
775#define MCP_REG_MCPR_NVM_CFG4 0x8642c
776#define MCP_REG_MCPR_NVM_COMMAND 0x86400
777#define MCP_REG_MCPR_NVM_READ 0x86410
778#define MCP_REG_MCPR_NVM_SW_ARB 0x86420
779#define MCP_REG_MCPR_NVM_WRITE 0x86408
780#define MCP_REG_MCPR_NVM_WRITE1 0x86428
781#define MCP_REG_MCPR_SCRATCH 0xa0000
782/* [R 32] read first 32 bit after inversion of function 0. mapped as
783 follows: [0] NIG attention for function0; [1] NIG attention for
784 function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp;
785 [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9]
786 GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE
787 glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0;
788 [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16]
789 MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB
790 Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw
791 interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity
792 error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw
793 interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF
794 Parity error; [31] PBF Hw interrupt; */
795#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 0xa42c
796#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 0xa430
797/* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0]
798 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
799 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
800 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
801 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
802 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
803 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
804 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
805 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
806 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
807 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
808 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
809 interrupt; */
810#define MISC_REG_AEU_AFTER_INVERT_1_MCP 0xa434
811/* [R 32] read second 32 bit after inversion of function 0. mapped as
812 follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
813 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
814 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
815 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
816 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
817 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
818 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
819 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
820 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
821 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
822 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
823 interrupt; */
824#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 0xa438
825#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 0xa43c
826/* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0]
827 PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error;
828 [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt;
829 [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9]
830 XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
831 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
832 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
833 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
834 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
835 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
836 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
837 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
838#define MISC_REG_AEU_AFTER_INVERT_2_MCP 0xa440
839/* [R 32] read third 32 bit after inversion of function 0. mapped as
840 follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity
841 error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5]
842 PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
843 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
844 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
845 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
846 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
847 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
848 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
849 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
850 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
851 attn1; */
852#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 0xa444
853#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 0xa448
854/* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0]
855 CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP
856 Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient
857 Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity
858 error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw
859 interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14]
860 MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17]
861 Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW
862 timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3
863 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1
864 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW
865 timers attn_4 func1; [30] General attn0; [31] General attn1; */
866#define MISC_REG_AEU_AFTER_INVERT_3_MCP 0xa44c
867/* [R 32] read fourth 32 bit after inversion of function 0. mapped as
868 follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
869 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
870 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
871 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
872 [14] General attn16; [15] General attn17; [16] General attn18; [17]
873 General attn19; [18] General attn20; [19] General attn21; [20] Main power
874 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
875 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
876 Latched timeout attention; [27] GRC Latched reserved access attention;
877 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
878 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
879#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 0xa450
880#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 0xa454
881/* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0]
882 General attn2; [1] General attn3; [2] General attn4; [3] General attn5;
883 [4] General attn6; [5] General attn7; [6] General attn8; [7] General
884 attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11]
885 General attn13; [12] General attn14; [13] General attn15; [14] General
886 attn16; [15] General attn17; [16] General attn18; [17] General attn19;
887 [18] General attn20; [19] General attn21; [20] Main power interrupt; [21]
888 RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24]
889 RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout
890 attention; [27] GRC Latched reserved access attention; [28] MCP Latched
891 rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched
892 ump_tx_parity; [31] MCP Latched scpad_parity; */
893#define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458
c18487ee 894/* [W 14] write to this register results with the clear of the latched
a2fbb9ea
ET		 895 signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in
896 d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP
897 latch; one in d5 clears GRC Latched timeout attention; one in d6 clears
898 GRC Latched reserved access attention; one in d7 clears Latched
899 rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears
c18487ee
YR		 900 Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both
901 ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears
902 pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read
903 from this register return zero */
a2fbb9ea
ET		 904#define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c
905/* [RW 32] first 32b for enabling the output for function 0 output0. mapped
906 as follows: [0] NIG attention for function0; [1] NIG attention for
907 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
908 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
909 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
910 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
911 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
912 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
913 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
914 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
915 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
916 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
917 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
918#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c
919#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c
c18487ee 920#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 0xa08c
a2fbb9ea 921#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 0xa09c
c18487ee
YR		 922#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5 0xa0bc
923#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6 0xa0cc
924#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7 0xa0dc
a2fbb9ea
ET		 925/* [RW 32] first 32b for enabling the output for function 1 output0. mapped
926 as follows: [0] NIG attention for function0; [1] NIG attention for
927 function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function
928 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
929 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
930 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
931 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
932 SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X
933 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
934 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
935 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
936 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
937 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
938#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c
939#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c
c18487ee 940#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 0xa12c
a2fbb9ea 941#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 0xa13c
c18487ee
YR		 942#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5 0xa15c
943#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6 0xa16c
944#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7 0xa17c
945/* [RW 32] first 32b for enabling the output for close the gate nig. mapped
946 as follows: [0] NIG attention for function0; [1] NIG attention for
a2fbb9ea
ET		 947 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
948 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
949 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
950 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
951 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
952 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
953 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
954 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
955 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
956 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
957 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
958#define MISC_REG_AEU_ENABLE1_NIG_0 0xa0ec
959#define MISC_REG_AEU_ENABLE1_NIG_1 0xa18c
c18487ee
YR		 960/* [RW 32] first 32b for enabling the output for close the gate pxp. mapped
961 as follows: [0] NIG attention for function0; [1] NIG attention for
a2fbb9ea
ET		 962 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
963 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
964 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
965 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
966 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
967 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
968 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
969 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
970 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
971 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
972 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
973#define MISC_REG_AEU_ENABLE1_PXP_0 0xa0fc
974#define MISC_REG_AEU_ENABLE1_PXP_1 0xa19c
975/* [RW 32] second 32b for enabling the output for function 0 output0. mapped
976 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
977 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
978 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
979 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
980 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
981 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
982 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
983 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
984 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
985 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
986 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
987 interrupt; */
988#define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0 0xa070
989#define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1 0xa080
990/* [RW 32] second 32b for enabling the output for function 1 output0. mapped
991 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
992 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
993 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
994 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
995 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
996 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
997 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
998 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
999 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1000 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1001 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1002 interrupt; */
1003#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 0xa110
1004#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 0xa120
c18487ee
YR		 1005/* [RW 32] second 32b for enabling the output for close the gate nig. mapped
1006 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1007 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1008 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1009 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1010 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1011 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1012 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1013 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1014 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1015 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1016 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1017 interrupt; */
a2fbb9ea
ET		 1018#define MISC_REG_AEU_ENABLE2_NIG_0 0xa0f0
1019#define MISC_REG_AEU_ENABLE2_NIG_1 0xa190
c18487ee
YR		 1020/* [RW 32] second 32b for enabling the output for close the gate pxp. mapped
1021 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1022 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1023 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1024 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1025 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1026 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1027 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1028 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1029 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1030 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1031 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1032 interrupt; */
a2fbb9ea
ET		 1033#define MISC_REG_AEU_ENABLE2_PXP_0 0xa100
1034#define MISC_REG_AEU_ENABLE2_PXP_1 0xa1a0
1035/* [RW 32] third 32b for enabling the output for function 0 output0. mapped
1036 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1037 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1038 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1039 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1040 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1041 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1042 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1043 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1044 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1045 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1046 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1047 attn1; */
1048#define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0 0xa074
1049#define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1 0xa084
1050/* [RW 32] third 32b for enabling the output for function 1 output0. mapped
1051 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1052 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1053 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1054 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1055 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1056 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1057 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1058 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1059 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1060 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1061 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1062 attn1; */
1063#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 0xa114
1064#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 0xa124
c18487ee
YR		 1065/* [RW 32] third 32b for enabling the output for close the gate nig. mapped
1066 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1067 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1068 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1069 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1070 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1071 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1072 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1073 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1074 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1075 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1076 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1077 attn1; */
a2fbb9ea
ET		 1078#define MISC_REG_AEU_ENABLE3_NIG_0 0xa0f4
1079#define MISC_REG_AEU_ENABLE3_NIG_1 0xa194
c18487ee
YR		 1080/* [RW 32] third 32b for enabling the output for close the gate pxp. mapped
1081 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1082 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1083 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1084 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1085 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1086 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1087 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1088 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1089 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1090 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1091 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1092 attn1; */
a2fbb9ea
ET		 1093#define MISC_REG_AEU_ENABLE3_PXP_0 0xa104
1094#define MISC_REG_AEU_ENABLE3_PXP_1 0xa1a4
1095/* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped
1096 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1097 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1098 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1099 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1100 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1101 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1102 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1103 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1104 Latched timeout attention; [27] GRC Latched reserved access attention;
1105 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1106 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1107#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078
1108#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 0xa098
c18487ee
YR		 1109#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4 0xa0b8
1110#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5 0xa0c8
1111#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6 0xa0d8
1112#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7 0xa0e8
a2fbb9ea
ET		 1113/* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped
1114 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1115 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1116 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1117 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1118 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1119 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1120 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1121 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1122 Latched timeout attention; [27] GRC Latched reserved access attention;
1123 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1124 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1125#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118
1126#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 0xa138
c18487ee
YR		 1127#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4 0xa158
1128#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5 0xa168
1129#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6 0xa178
1130#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7 0xa188
1131/* [RW 32] fourth 32b for enabling the output for close the gate nig.mapped
1132 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1133 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1134 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1135 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1136 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1137 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1138 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1139 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1140 Latched timeout attention; [27] GRC Latched reserved access attention;
1141 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1142 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
a2fbb9ea
ET		 1143#define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8
1144#define MISC_REG_AEU_ENABLE4_NIG_1 0xa198
c18487ee
YR		 1145/* [RW 32] fourth 32b for enabling the output for close the gate pxp.mapped
1146 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1147 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1148 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1149 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1150 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1151 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1152 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1153 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1154 Latched timeout attention; [27] GRC Latched reserved access attention;
1155 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1156 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
a2fbb9ea
ET		 1157#define MISC_REG_AEU_ENABLE4_PXP_0 0xa108
1158#define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8
1159/* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu
1160 128 bit vector */
1161#define MISC_REG_AEU_GENERAL_ATTN_0 0xa000
1162#define MISC_REG_AEU_GENERAL_ATTN_1 0xa004
1163#define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
1164#define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
1165#define MISC_REG_AEU_GENERAL_ATTN_12 0xa030
1166#define MISC_REG_AEU_GENERAL_ATTN_13 0xa034
1167#define MISC_REG_AEU_GENERAL_ATTN_14 0xa038
1168#define MISC_REG_AEU_GENERAL_ATTN_15 0xa03c
1169#define MISC_REG_AEU_GENERAL_ATTN_16 0xa040
1170#define MISC_REG_AEU_GENERAL_ATTN_17 0xa044
1171#define MISC_REG_AEU_GENERAL_ATTN_18 0xa048
1172#define MISC_REG_AEU_GENERAL_ATTN_19 0xa04c
f1410647 1173#define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
a2fbb9ea 1174#define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
c18487ee 1175#define MISC_REG_AEU_GENERAL_ATTN_12 0xa030
a2fbb9ea
ET		 1176#define MISC_REG_AEU_GENERAL_ATTN_2 0xa008
1177#define MISC_REG_AEU_GENERAL_ATTN_20 0xa050
1178#define MISC_REG_AEU_GENERAL_ATTN_21 0xa054
1179#define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c
1180#define MISC_REG_AEU_GENERAL_ATTN_4 0xa010
1181#define MISC_REG_AEU_GENERAL_ATTN_5 0xa014
1182#define MISC_REG_AEU_GENERAL_ATTN_6 0xa018
f1410647
ET		 1183#define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c
1184#define MISC_REG_AEU_GENERAL_ATTN_8 0xa020
1185#define MISC_REG_AEU_GENERAL_ATTN_9 0xa024
c18487ee 1186#define MISC_REG_AEU_GENERAL_MASK 0xa61c
a2fbb9ea
ET		 1187/* [RW 32] first 32b for inverting the input for function 0; for each bit:
1188 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for
1189 function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp;
1190 [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1;
1191 [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1192 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1193 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1194 SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication
1195 for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS
1196 Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw
1197 interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM
1198 Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI
1199 Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1200#define MISC_REG_AEU_INVERTER_1_FUNC_0 0xa22c
1201#define MISC_REG_AEU_INVERTER_1_FUNC_1 0xa23c
1202/* [RW 32] second 32b for inverting the input for function 0; for each bit:
1203 0= do not invert; 1= invert. mapped as follows: [0] PBClient Parity
1204 error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw
1205 interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM
1206 Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw
1207 interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
1208 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
1209 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
1210 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
1211 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
1212 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
1213 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
1214 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
1215#define MISC_REG_AEU_INVERTER_2_FUNC_0 0xa230
1216#define MISC_REG_AEU_INVERTER_2_FUNC_1 0xa240
1217/* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0;
c18487ee 1218 [9:8] = raserved. Zero = mask; one = unmask */
a2fbb9ea
ET		 1219#define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060
1220#define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064
c18487ee
YR		 1221/* [RW 1] If set a system kill occurred */
1222#define MISC_REG_AEU_SYS_KILL_OCCURRED 0xa610
1223/* [RW 32] Represent the status of the input vector to the AEU when a system
1224 kill occurred. The register is reset in por reset. Mapped as follows: [0]
1225 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
1226 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
1227 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
1228 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
1229 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
1230 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
1231 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
1232 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
1233 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
1234 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
1235 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
1236 interrupt; */
1237#define MISC_REG_AEU_SYS_KILL_STATUS_0 0xa600
1238#define MISC_REG_AEU_SYS_KILL_STATUS_1 0xa604
1239#define MISC_REG_AEU_SYS_KILL_STATUS_2 0xa608
1240#define MISC_REG_AEU_SYS_KILL_STATUS_3 0xa60c
a2fbb9ea
ET		 1241/* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1
1242 Port. */
1243#define MISC_REG_BOND_ID 0xa400
1244/* [R 8] These bits indicate the metal revision of the chip. This value
1245 starts at 0x00 for each all-layer tape-out and increments by one for each
1246 tape-out. */
1247#define MISC_REG_CHIP_METAL 0xa404
1248/* [R 16] These bits indicate the part number for the chip. */
1249#define MISC_REG_CHIP_NUM 0xa408
1250/* [R 4] These bits indicate the base revision of the chip. This value
1251 starts at 0x0 for the A0 tape-out and increments by one for each
1252 all-layer tape-out. */
1253#define MISC_REG_CHIP_REV 0xa40c
c18487ee
YR		 1254/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1255 32 clients. Each client can be controlled by one driver only. One in each
1256 bit represent that this driver control the appropriate client (Ex: bit 5
1257 is set means this driver control client number 5). addr1 = set; addr0 =
1258 clear; read from both addresses will give the same result = status. write
1259 to address 1 will set a request to control all the clients that their
1260 appropriate bit (in the write command) is set. if the client is free (the
1261 appropriate bit in all the other drivers is clear) one will be written to
1262 that driver register; if the client isn't free the bit will remain zero.
1263 if the appropriate bit is set (the driver request to gain control on a
1264 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1265 interrupt will be asserted). write to address 0 will set a request to
1266 free all the clients that their appropriate bit (in the write command) is
1267 set. if the appropriate bit is clear (the driver request to free a client
1268 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1269 be asserted). */
1270#define MISC_REG_DRIVER_CONTROL_10 0xa3e0
1271#define MISC_REG_DRIVER_CONTROL_10_SIZE 2
1272/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1273 32 clients. Each client can be controlled by one driver only. One in each
1274 bit represent that this driver control the appropriate client (Ex: bit 5
1275 is set means this driver control client number 5). addr1 = set; addr0 =
1276 clear; read from both addresses will give the same result = status. write
1277 to address 1 will set a request to control all the clients that their
1278 appropriate bit (in the write command) is set. if the client is free (the
1279 appropriate bit in all the other drivers is clear) one will be written to
1280 that driver register; if the client isn't free the bit will remain zero.
1281 if the appropriate bit is set (the driver request to gain control on a
1282 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1283 interrupt will be asserted). write to address 0 will set a request to
1284 free all the clients that their appropriate bit (in the write command) is
1285 set. if the appropriate bit is clear (the driver request to free a client
1286 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1287 be asserted). */
1288#define MISC_REG_DRIVER_CONTROL_11 0xa3e8
1289#define MISC_REG_DRIVER_CONTROL_11_SIZE 2
1290/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1291 32 clients. Each client can be controlled by one driver only. One in each
1292 bit represent that this driver control the appropriate client (Ex: bit 5
1293 is set means this driver control client number 5). addr1 = set; addr0 =
1294 clear; read from both addresses will give the same result = status. write
1295 to address 1 will set a request to control all the clients that their
1296 appropriate bit (in the write command) is set. if the client is free (the
1297 appropriate bit in all the other drivers is clear) one will be written to
1298 that driver register; if the client isn't free the bit will remain zero.
1299 if the appropriate bit is set (the driver request to gain control on a
1300 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1301 interrupt will be asserted). write to address 0 will set a request to
1302 free all the clients that their appropriate bit (in the write command) is
1303 set. if the appropriate bit is clear (the driver request to free a client
1304 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1305 be asserted). */
1306#define MISC_REG_DRIVER_CONTROL_12 0xa3f0
1307#define MISC_REG_DRIVER_CONTROL_12_SIZE 2
1308/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1309 32 clients. Each client can be controlled by one driver only. One in each
1310 bit represent that this driver control the appropriate client (Ex: bit 5
1311 is set means this driver control client number 5). addr1 = set; addr0 =
1312 clear; read from both addresses will give the same result = status. write
1313 to address 1 will set a request to control all the clients that their
1314 appropriate bit (in the write command) is set. if the client is free (the
1315 appropriate bit in all the other drivers is clear) one will be written to
1316 that driver register; if the client isn't free the bit will remain zero.
1317 if the appropriate bit is set (the driver request to gain control on a
1318 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1319 interrupt will be asserted). write to address 0 will set a request to
1320 free all the clients that their appropriate bit (in the write command) is
1321 set. if the appropriate bit is clear (the driver request to free a client
1322 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1323 be asserted). */
1324#define MISC_REG_DRIVER_CONTROL_13 0xa3f8
1325#define MISC_REG_DRIVER_CONTROL_13_SIZE 2
1326/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1327 32 clients. Each client can be controlled by one driver only. One in each
f1410647
ET		 1328 bit represent that this driver control the appropriate client (Ex: bit 5
1329 is set means this driver control client number 5). addr1 = set; addr0 =
1330 clear; read from both addresses will give the same result = status. write
1331 to address 1 will set a request to control all the clients that their
1332 appropriate bit (in the write command) is set. if the client is free (the
1333 appropriate bit in all the other drivers is clear) one will be written to
1334 that driver register; if the client isn't free the bit will remain zero.
1335 if the appropriate bit is set (the driver request to gain control on a
1336 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1337 interrupt will be asserted). write to address 0 will set a request to
1338 free all the clients that their appropriate bit (in the write command) is
1339 set. if the appropriate bit is clear (the driver request to free a client
1340 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1341 be asserted). */
1342#define MISC_REG_DRIVER_CONTROL_1 0xa510
c18487ee
YR		 1343#define MISC_REG_DRIVER_CONTROL_14 0xa5e0
1344#define MISC_REG_DRIVER_CONTROL_14_SIZE 2
1345/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1346 32 clients. Each client can be controlled by one driver only. One in each
1347 bit represent that this driver control the appropriate client (Ex: bit 5
1348 is set means this driver control client number 5). addr1 = set; addr0 =
1349 clear; read from both addresses will give the same result = status. write
1350 to address 1 will set a request to control all the clients that their
1351 appropriate bit (in the write command) is set. if the client is free (the
1352 appropriate bit in all the other drivers is clear) one will be written to
1353 that driver register; if the client isn't free the bit will remain zero.
1354 if the appropriate bit is set (the driver request to gain control on a
1355 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1356 interrupt will be asserted). write to address 0 will set a request to
1357 free all the clients that their appropriate bit (in the write command) is
1358 set. if the appropriate bit is clear (the driver request to free a client
1359 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1360 be asserted). */
1361#define MISC_REG_DRIVER_CONTROL_15 0xa5e8
1362#define MISC_REG_DRIVER_CONTROL_15_SIZE 2
1363/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1364 32 clients. Each client can be controlled by one driver only. One in each
1365 bit represent that this driver control the appropriate client (Ex: bit 5
1366 is set means this driver control client number 5). addr1 = set; addr0 =
1367 clear; read from both addresses will give the same result = status. write
1368 to address 1 will set a request to control all the clients that their
1369 appropriate bit (in the write command) is set. if the client is free (the
1370 appropriate bit in all the other drivers is clear) one will be written to
1371 that driver register; if the client isn't free the bit will remain zero.
1372 if the appropriate bit is set (the driver request to gain control on a
1373 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1374 interrupt will be asserted). write to address 0 will set a request to
1375 free all the clients that their appropriate bit (in the write command) is
1376 set. if the appropriate bit is clear (the driver request to free a client
1377 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1378 be asserted). */
1379#define MISC_REG_DRIVER_CONTROL_16 0xa5f0
1380#define MISC_REG_DRIVER_CONTROL_16_SIZE 2
1381/* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0
1382 only. */
1383#define MISC_REG_E1HMF_MODE 0xa5f8
f1410647
ET		 1384/* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of
1385 these bits is written as a '1'; the corresponding SPIO bit will turn off
1386 it's drivers and become an input. This is the reset state of all GPIO
1387 pins. The read value of these bits will be a '1' if that last command
1388 (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff).
1389 [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written
1390 as a '1'; the corresponding GPIO bit will drive low. The read value of
1391 these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for
1392 this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0;
1393 SET When any of these bits is written as a '1'; the corresponding GPIO
1394 bit will drive high (if it has that capability). The read value of these
1395 bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this
1396 bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0;
1397 RO; These bits indicate the read value of each of the eight GPIO pins.
1398 This is the result value of the pin; not the drive value. Writing these
1399 bits will have not effect. */
1400#define MISC_REG_GPIO 0xa490
c18487ee
YR		 1401/* [R 28] this field hold the last information that caused reserved
1402 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1403 [27:24] the master thatcaused the attention - according to the following
1404 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1405 dbu; 8 = dmae */
1406#define MISC_REG_GRC_RSV_ATTN 0xa3c0
1407/* [R 28] this field hold the last information that caused timeout
1408 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1409 [27:24] the master thatcaused the attention - according to the following
1410 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1411 dbu; 8 = dmae */
1412#define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4
a2fbb9ea
ET		 1413/* [RW 1] Setting this bit enables a timer in the GRC block to timeout any
1414 access that does not finish within
1415 ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is
1416 cleared; this timeout is disabled. If this timeout occurs; the GRC shall
1417 assert it attention output. */
1418#define MISC_REG_GRC_TIMEOUT_EN 0xa280
1419/* [RW 28] 28 LSB of LCPLL first register; reset val = 521. inside order of
1420 the bits is: [2:0] OAC reset value 001) CML output buffer bias control;
1421 111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl
1422 (reset value 001) Charge pump current control; 111 for 720u; 011 for
1423 600u; 001 for 480u and 000 for 360u. [7:6] Bias_ctrl (reset value 00)
1424 Global bias control; When bit 7 is high bias current will be 10 0gh; When
1425 bit 6 is high bias will be 100w; Valid values are 00; 10; 01. [10:8]
1426 Pll_observe (reset value 010) Bits to control observability. bit 10 is
1427 for test bias; bit 9 is for test CK; bit 8 is test Vc. [12:11] Vth_ctrl
1428 (reset value 00) Comparator threshold control. 00 for 0.6V; 01 for 0.54V
1429 and 10 for 0.66V. [13] pllSeqStart (reset value 0) Enables VCO tuning
1430 sequencer: 1= sequencer disabled; 0= sequencer enabled (inverted
1431 internally). [14] reserved (reset value 0) Reset for VCO sequencer is
1432 connected to RESET input directly. [15] capRetry_en (reset value 0)
1433 enable retry on cap search failure (inverted). [16] freqMonitor_e (reset
1434 value 0) bit to continuously monitor vco freq (inverted). [17]
1435 freqDetRestart_en (reset value 0) bit to enable restart when not freq
1436 locked (inverted). [18] freqDetRetry_en (reset value 0) bit to enable
1437 retry on freq det failure(inverted). [19] pllForceFdone_en (reset value
1438 0) bit to enable pllForceFdone & pllForceFpass into pllSeq. [20]
1439 pllForceFdone (reset value 0) bit to force freqDone. [21] pllForceFpass
1440 (reset value 0) bit to force freqPass. [22] pllForceDone_en (reset value
1441 0) bit to enable pllForceCapDone. [23] pllForceCapDone (reset value 0)
1442 bit to force capDone. [24] pllForceCapPass_en (reset value 0) bit to
1443 enable pllForceCapPass. [25] pllForceCapPass (reset value 0) bit to force
1444 capPass. [26] capRestart (reset value 0) bit to force cap sequencer to
1445 restart. [27] capSelectM_en (reset value 0) bit to enable cap select
1446 register bits. */
1447#define MISC_REG_LCPLL_CTRL_1 0xa2a4
1448#define MISC_REG_LCPLL_CTRL_REG_2 0xa2a8
1449/* [RW 4] Interrupt mask register #0 read/write */
1450#define MISC_REG_MISC_INT_MASK 0xa388
1451/* [RW 1] Parity mask register #0 read/write */
1452#define MISC_REG_MISC_PRTY_MASK 0xa398
f1410647
ET		 1453/* [R 1] Parity register #0 read */
1454#define MISC_REG_MISC_PRTY_STS 0xa38c
c18487ee
YR		 1455#define MISC_REG_NIG_WOL_P0 0xa270
1456#define MISC_REG_NIG_WOL_P1 0xa274
1457/* [R 1] If set indicate that the pcie_rst_b was asserted without perst
1458 assertion */
1459#define MISC_REG_PCIE_HOT_RESET 0xa618
a2fbb9ea
ET		 1460/* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911.
1461 inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1
1462 divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1
1463 divider[3] (reset value 0); [4] P2 divider[0] (reset value 1); [5] P2
1464 divider[1] (reset value 0); [6] P2 divider[2] (reset value 0); [7] P2
1465 divider[3] (reset value 0); [8] ph_det_dis (reset value 1); [9]
1466 freq_det_dis (reset value 0); [10] Icpx[0] (reset value 0); [11] Icpx[1]
1467 (reset value 1); [12] Icpx[2] (reset value 0); [13] Icpx[3] (reset value
1468 1); [14] Icpx[4] (reset value 0); [15] Icpx[5] (reset value 0); [16]
1469 Rx[0] (reset value 1); [17] Rx[1] (reset value 0); [18] vc_en (reset
1470 value 1); [19] vco_rng[0] (reset value 1); [20] vco_rng[1] (reset value
1471 1); [21] Kvco_xf[0] (reset value 0); [22] Kvco_xf[1] (reset value 0);
1472 [23] Kvco_xf[2] (reset value 0); [24] Kvco_xs[0] (reset value 1); [25]
1473 Kvco_xs[1] (reset value 1); [26] Kvco_xs[2] (reset value 1); [27]
1474 testd_en (reset value 0); [28] testd_sel[0] (reset value 0); [29]
1475 testd_sel[1] (reset value 0); [30] testd_sel[2] (reset value 0); [31]
1476 testa_en (reset value 0); */
1477#define MISC_REG_PLL_STORM_CTRL_1 0xa294
1478#define MISC_REG_PLL_STORM_CTRL_2 0xa298
1479#define MISC_REG_PLL_STORM_CTRL_3 0xa29c
1480#define MISC_REG_PLL_STORM_CTRL_4 0xa2a0
c18487ee 1481/* [RW 32] reset reg#2; rite/read one = the specific block is out of reset;
a2fbb9ea
ET		 1482 write/read zero = the specific block is in reset; addr 0-wr- the write
1483 value will be written to the register; addr 1-set - one will be written
1484 to all the bits that have the value of one in the data written (bits that
1485 have the value of zero will not be change) ; addr 2-clear - zero will be
1486 written to all the bits that have the value of one in the data written
1487 (bits that have the value of zero will not be change); addr 3-ignore;
1488 read ignore from all addr except addr 00; inside order of the bits is:
c18487ee
YR		 1489 [0] rst_bmac0; [1] rst_bmac1; [2] rst_emac0; [3] rst_emac1; [4] rst_grc;
1490 [5] rst_mcp_n_reset_reg_hard_core; [6] rst_ mcp_n_hard_core_rst_b; [7]
1491 rst_ mcp_n_reset_cmn_cpu; [8] rst_ mcp_n_reset_cmn_core; [9] rst_rbcn;
1492 [10] rst_dbg; [11] rst_misc_core; [12] rst_dbue (UART); [13]
1493 Pci_resetmdio_n; [14] rst_emac0_hard_core; [15] rst_emac1_hard_core; 16]
1494 rst_pxp_rq_rd_wr; 31:17] reserved */
a2fbb9ea
ET		 1495#define MISC_REG_RESET_REG_2 0xa590
1496/* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is
1497 shared with the driver resides */
1498#define MISC_REG_SHARED_MEM_ADDR 0xa2b4
f1410647
ET		 1499/* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1';
1500 the corresponding SPIO bit will turn off it's drivers and become an
1501 input. This is the reset state of all SPIO pins. The read value of these
1502 bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this
1503 bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits
1504 is written as a '1'; the corresponding SPIO bit will drive low. The read
1505 value of these bits will be a '1' if that last command (#SET; #CLR; or
1506#FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of
1507 these bits is written as a '1'; the corresponding SPIO bit will drive
1508 high (if it has that capability). The read value of these bits will be a
1509 '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET.
1510 (reset value 0). [7-0] VALUE RO; These bits indicate the read value of
1511 each of the eight SPIO pins. This is the result value of the pin; not the
1512 drive value. Writing these bits will have not effect. Each 8 bits field
1513 is divided as follows: [0] VAUX Enable; when pulsed low; enables supply
1514 from VAUX. (This is an output pin only; the FLOAT field is not applicable
1515 for this pin); [1] VAUX Disable; when pulsed low; disables supply form
1516 VAUX. (This is an output pin only; FLOAT field is not applicable for this
1517 pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to
1518 select VAUX supply. (This is an output pin only; it is not controlled by
1519 the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT
1520 field is not applicable for this pin; only the VALUE fields is relevant -
c18487ee 1521 it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6]
f1410647
ET		 1522 Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP
1523 device ID select; read by UMP firmware. */
1524#define MISC_REG_SPIO 0xa4fc
1525/* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC.
1526 according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5;
1527 [7:0] reserved */
1528#define MISC_REG_SPIO_EVENT_EN 0xa2b8
1529/* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the
1530 corresponding bit in the #OLD_VALUE register. This will acknowledge an
1531 interrupt on the falling edge of corresponding SPIO input (reset value
1532 0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit
1533 in the #OLD_VALUE register. This will acknowledge an interrupt on the
1534 rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE
1535 RO; These bits indicate the old value of the SPIO input value. When the
1536 ~INT_STATE bit is set; this bit indicates the OLD value of the pin such
1537 that if ~INT_STATE is set and this bit is '0'; then the interrupt is due
1538 to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the
1539 interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE
1540 RO; These bits indicate the current SPIO interrupt state for each SPIO
1541 pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR
1542 command bit is written. This bit is set when the SPIO input does not
1543 match the current value in #OLD_VALUE (reset value 0). */
1544#define MISC_REG_SPIO_INT 0xa500
1545/* [RW 1] Set by the MCP to remember if one or more of the drivers is/are
1546 loaded; 0-prepare; -unprepare */
1547#define MISC_REG_UNPREPARED 0xa424
a2fbb9ea
ET		 1548#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0)
1549#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9)
1550#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15)
1551#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS (0xf<<18)
1552/* [RW 1] Input enable for RX_BMAC0 IF */
1553#define NIG_REG_BMAC0_IN_EN 0x100ac
1554/* [RW 1] output enable for TX_BMAC0 IF */
1555#define NIG_REG_BMAC0_OUT_EN 0x100e0
1556/* [RW 1] output enable for TX BMAC pause port 0 IF */
1557#define NIG_REG_BMAC0_PAUSE_OUT_EN 0x10110
1558/* [RW 1] output enable for RX_BMAC0_REGS IF */
1559#define NIG_REG_BMAC0_REGS_OUT_EN 0x100e8
1560/* [RW 1] output enable for RX BRB1 port0 IF */
1561#define NIG_REG_BRB0_OUT_EN 0x100f8
1562/* [RW 1] Input enable for TX BRB1 pause port 0 IF */
1563#define NIG_REG_BRB0_PAUSE_IN_EN 0x100c4
1564/* [RW 1] output enable for RX BRB1 port1 IF */
1565#define NIG_REG_BRB1_OUT_EN 0x100fc
1566/* [RW 1] Input enable for TX BRB1 pause port 1 IF */
1567#define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8
1568/* [RW 1] output enable for RX BRB1 LP IF */
1569#define NIG_REG_BRB_LB_OUT_EN 0x10100
c18487ee
YR		 1570/* [WB_W 82] Debug packet to LP from RBC; Data spelling:[63:0] data; 64]
1571 error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush;
1572 72:73]-vnic_num; 81:74]-sideband_info */
a2fbb9ea
ET		 1573#define NIG_REG_DEBUG_PACKET_LB 0x10800
1574/* [RW 1] Input enable for TX Debug packet */
1575#define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dc
1576/* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all
1577 packets from PBFare not forwarded to the MAC and just deleted from FIFO.
1578 First packet may be deleted from the middle. And last packet will be
1579 always deleted till the end. */
1580#define NIG_REG_EGRESS_DRAIN0_MODE 0x10060
1581/* [RW 1] Output enable to EMAC0 */
1582#define NIG_REG_EGRESS_EMAC0_OUT_EN 0x10120
1583/* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs
1584 to emac for port0; other way to bmac for port0 */
1585#define NIG_REG_EGRESS_EMAC0_PORT 0x10058
c18487ee
YR		 1586/* [RW 32] TX_MNG_FIFO in NIG_TX_PORT0; data[31:0] written in FIFO order. */
1587#define NIG_REG_EGRESS_MNG0_FIFO 0x1045c
a2fbb9ea
ET		 1588/* [RW 1] Input enable for TX PBF user packet port0 IF */
1589#define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc
1590/* [RW 1] Input enable for TX PBF user packet port1 IF */
1591#define NIG_REG_EGRESS_PBF1_IN_EN 0x100d0
1592/* [RW 1] Input enable for RX_EMAC0 IF */
1593#define NIG_REG_EMAC0_IN_EN 0x100a4
1594/* [RW 1] output enable for TX EMAC pause port 0 IF */
1595#define NIG_REG_EMAC0_PAUSE_OUT_EN 0x10118
1596/* [R 1] status from emac0. This bit is set when MDINT from either the
1597 EXT_MDINT pin or from the Copper PHY is driven low. This condition must
1598 be cleared in the attached PHY device that is driving the MINT pin. */
1599#define NIG_REG_EMAC0_STATUS_MISC_MI_INT 0x10494
1600/* [WB 48] This address space contains BMAC0 registers. The BMAC registers
1601 are described in appendix A. In order to access the BMAC0 registers; the
1602 base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be
1603 added to each BMAC register offset */
1604#define NIG_REG_INGRESS_BMAC0_MEM 0x10c00
1605/* [WB 48] This address space contains BMAC1 registers. The BMAC registers
1606 are described in appendix A. In order to access the BMAC0 registers; the
1607 base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be
1608 added to each BMAC register offset */
1609#define NIG_REG_INGRESS_BMAC1_MEM 0x11000
1610/* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */
1611#define NIG_REG_INGRESS_EOP_LB_EMPTY 0x104e0
1612/* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data
1613 packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */
1614#define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4
1615/* [RW 1] led 10g for port 0 */
1616#define NIG_REG_LED_10G_P0 0x10320
c18487ee
YR		 1617/* [RW 1] led 10g for port 1 */
1618#define NIG_REG_LED_10G_P1 0x10324
a2fbb9ea
ET		 1619/* [RW 1] Port0: This bit is set to enable the use of the
1620 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field
1621 defined below. If this bit is cleared; then the blink rate will be about
1622 8Hz. */
1623#define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 0x10318
1624/* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for
1625 Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field
1626 is reset to 0x080; giving a default blink period of approximately 8Hz. */
1627#define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310
1628/* [RW 1] Port0: If set along with the
1629 nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0
1630 bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED
1631 bit; the Traffic LED will blink with the blink rate specified in
1632 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
1633 ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
1634 fields. */
1635#define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 0x10308
1636/* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The
1637 Traffic LED will then be controlled via bit ~nig_registers_
1638 led_control_traffic_p0.led_control_traffic_p0 and bit
1639 ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 */
1640#define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x102f8
1641/* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit;
1642 turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also
1643 set; the LED will blink with blink rate specified in
1644 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
1645 ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
1646 fields. */
1647#define NIG_REG_LED_CONTROL_TRAFFIC_P0 0x10300
1648/* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3;
1649 9-11PHY7; 12 MAC4; 13-15 PHY10; */
1650#define NIG_REG_LED_MODE_P0 0x102f0
c18487ee
YR		 1651#define NIG_REG_LLH0_ACPI_PAT_0_CRC 0x1015c
1652#define NIG_REG_LLH0_ACPI_PAT_6_LEN 0x10154
a2fbb9ea 1653#define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244
c18487ee 1654#define NIG_REG_LLH0_BRB1_DRV_MASK_MF 0x16048
a2fbb9ea
ET		 1655/* [RW 1] send to BRB1 if no match on any of RMP rules. */
1656#define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c
c18487ee
YR		 1657/* [RW 2] Determine the classification participants. 0: no classification.1:
1658 classification upon VLAN id. 2: classification upon MAC address. 3:
1659 classification upon both VLAN id & MAC addr. */
1660#define NIG_REG_LLH0_CLS_TYPE 0x16080
a2fbb9ea
ET		 1661/* [RW 32] cm header for llh0 */
1662#define NIG_REG_LLH0_CM_HEADER 0x1007c
c18487ee
YR		 1663#define NIG_REG_LLH0_DEST_IP_0_1 0x101dc
1664#define NIG_REG_LLH0_DEST_MAC_0_0 0x101c0
1665/* [RW 16] destination TCP address 1. The LLH will look for this address in
1666 all incoming packets. */
1667#define NIG_REG_LLH0_DEST_TCP_0 0x10220
1668/* [RW 16] destination UDP address 1 The LLH will look for this address in
1669 all incoming packets. */
1670#define NIG_REG_LLH0_DEST_UDP_0 0x10214
a2fbb9ea
ET		 1671#define NIG_REG_LLH0_ERROR_MASK 0x1008c
1672/* [RW 8] event id for llh0 */
1673#define NIG_REG_LLH0_EVENT_ID 0x10084
c18487ee
YR		 1674#define NIG_REG_LLH0_FUNC_EN 0x160fc
1675#define NIG_REG_LLH0_FUNC_VLAN_ID 0x16100
1676/* [RW 1] Determine the IP version to look for in
1677 ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 */
1678#define NIG_REG_LLH0_IPV4_IPV6_0 0x10208
1679/* [RW 1] t bit for llh0 */
1680#define NIG_REG_LLH0_T_BIT 0x10074
1681/* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */
1682#define NIG_REG_LLH0_VLAN_ID_0 0x1022c
a2fbb9ea
ET		 1683/* [RW 8] init credit counter for port0 in LLH */
1684#define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554
1685#define NIG_REG_LLH0_XCM_MASK 0x10130
1686/* [RW 1] send to BRB1 if no match on any of RMP rules. */
1687#define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc
c18487ee
YR		 1688/* [RW 2] Determine the classification participants. 0: no classification.1:
1689 classification upon VLAN id. 2: classification upon MAC address. 3:
1690 classification upon both VLAN id & MAC addr. */
1691#define NIG_REG_LLH1_CLS_TYPE 0x16084
a2fbb9ea
ET		 1692/* [RW 32] cm header for llh1 */
1693#define NIG_REG_LLH1_CM_HEADER 0x10080
1694#define NIG_REG_LLH1_ERROR_MASK 0x10090
1695/* [RW 8] event id for llh1 */
1696#define NIG_REG_LLH1_EVENT_ID 0x10088
1697/* [RW 8] init credit counter for port1 in LLH */
1698#define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564
1699#define NIG_REG_LLH1_XCM_MASK 0x10134
c18487ee
YR		 1700/* [RW 1] When this bit is set; the LLH will expect all packets to be with
1701 e1hov */
1702#define NIG_REG_LLH_E1HOV_MODE 0x160d8
1703/* [RW 1] When this bit is set; the LLH will classify the packet before
1704 sending it to the BRB or calculating WoL on it. */
1705#define NIG_REG_LLH_MF_MODE 0x16024
a2fbb9ea
ET		 1706#define NIG_REG_MASK_INTERRUPT_PORT0 0x10330
1707#define NIG_REG_MASK_INTERRUPT_PORT1 0x10334
1708/* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */
1709#define NIG_REG_NIG_EMAC0_EN 0x1003c
c18487ee
YR		 1710/* [RW 1] Output signal from NIG to EMAC1. When set enables the EMAC1 block. */
1711#define NIG_REG_NIG_EMAC1_EN 0x10040
a2fbb9ea
ET		 1712/* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the
1713 EMAC0 to strip the CRC from the ingress packets. */
1714#define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044
c18487ee
YR		 1715/* [R 32] Interrupt register #0 read */
1716#define NIG_REG_NIG_INT_STS_0 0x103b0
1717#define NIG_REG_NIG_INT_STS_1 0x103c0
1718/* [R 32] Parity register #0 read */
1719#define NIG_REG_NIG_PRTY_STS 0x103d0
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ET		 1720/* [RW 1] Input enable for RX PBF LP IF */
1721#define NIG_REG_PBF_LB_IN_EN 0x100b4
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ET		 1722/* [RW 1] Value of this register will be transmitted to port swap when
1723 ~nig_registers_strap_override.strap_override =1 */
1724#define NIG_REG_PORT_SWAP 0x10394
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ET		 1725/* [RW 1] output enable for RX parser descriptor IF */
1726#define NIG_REG_PRS_EOP_OUT_EN 0x10104
1727/* [RW 1] Input enable for RX parser request IF */
1728#define NIG_REG_PRS_REQ_IN_EN 0x100b8
1729/* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */
1730#define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374
1731/* [R 1] status from serdes0 that inputs to interrupt logic of link status */
1732#define NIG_REG_SERDES0_STATUS_LINK_STATUS 0x10578
1733/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
1734 for port0 */
1735#define NIG_REG_STAT0_BRB_DISCARD 0x105f0
1736/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
1737 for port1 */
1738#define NIG_REG_STAT1_BRB_DISCARD 0x10628
1739/* [WB_R 64] Rx statistics : User octets received for LP */
1740#define NIG_REG_STAT2_BRB_OCTET 0x107e0
1741#define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328
1742#define NIG_REG_STATUS_INTERRUPT_PORT1 0x1032c
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ET		 1743/* [RW 1] port swap mux selection. If this register equal to 0 then port
1744 swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then
1745 ort swap is equal to ~nig_registers_port_swap.port_swap */
1746#define NIG_REG_STRAP_OVERRIDE 0x10398
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ET		 1747/* [RW 1] output enable for RX_XCM0 IF */
1748#define NIG_REG_XCM0_OUT_EN 0x100f0
1749/* [RW 1] output enable for RX_XCM1 IF */
1750#define NIG_REG_XCM1_OUT_EN 0x100f4
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YR		 1751/* [RW 1] control to xgxs - remote PHY in-band MDIO */
1752#define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST 0x10348
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ET		 1753/* [RW 5] control to xgxs - CL45 DEVAD */
1754#define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c
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YR		 1755/* [RW 1] control to xgxs; 0 - clause 45; 1 - clause 22 */
1756#define NIG_REG_XGXS0_CTRL_MD_ST 0x10338
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ET		 1757/* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */
1758#define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340
1759/* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */
1760#define NIG_REG_XGXS0_STATUS_LINK10G 0x10680
1761/* [R 4] status from xgxs0 that inputs to interrupt logic of link status */
1762#define NIG_REG_XGXS0_STATUS_LINK_STATUS 0x10684
1763/* [RW 2] selection for XGXS lane of port 0 in NIG_MUX block */
1764#define NIG_REG_XGXS_LANE_SEL_P0 0x102e8
1765/* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */
1766#define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0
1767#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9)
1768#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1<<15)
1769#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf<<18)
1770#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18
1771/* [RW 1] Disable processing further tasks from port 0 (after ending the
1772 current task in process). */
1773#define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005c
1774/* [RW 1] Disable processing further tasks from port 1 (after ending the
1775 current task in process). */
1776#define PBF_REG_DISABLE_NEW_TASK_PROC_P1 0x140060
1777/* [RW 1] Disable processing further tasks from port 4 (after ending the
1778 current task in process). */
1779#define PBF_REG_DISABLE_NEW_TASK_PROC_P4 0x14006c
1780#define PBF_REG_IF_ENABLE_REG 0x140044
1781/* [RW 1] Init bit. When set the initial credits are copied to the credit
1782 registers (except the port credits). Should be set and then reset after
1783 the configuration of the block has ended. */
1784#define PBF_REG_INIT 0x140000
1785/* [RW 1] Init bit for port 0. When set the initial credit of port 0 is
1786 copied to the credit register. Should be set and then reset after the
1787 configuration of the port has ended. */
1788#define PBF_REG_INIT_P0 0x140004
1789/* [RW 1] Init bit for port 1. When set the initial credit of port 1 is
1790 copied to the credit register. Should be set and then reset after the
1791 configuration of the port has ended. */
1792#define PBF_REG_INIT_P1 0x140008
1793/* [RW 1] Init bit for port 4. When set the initial credit of port 4 is
1794 copied to the credit register. Should be set and then reset after the
1795 configuration of the port has ended. */
1796#define PBF_REG_INIT_P4 0x14000c
1797/* [RW 1] Enable for mac interface 0. */
1798#define PBF_REG_MAC_IF0_ENABLE 0x140030
1799/* [RW 1] Enable for mac interface 1. */
1800#define PBF_REG_MAC_IF1_ENABLE 0x140034
1801/* [RW 1] Enable for the loopback interface. */
1802#define PBF_REG_MAC_LB_ENABLE 0x140040
1803/* [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when pause
1804 not suppoterd. */
1805#define PBF_REG_P0_ARB_THRSH 0x1400e4
1806/* [R 11] Current credit for port 0 in the tx port buffers in 16 byte lines. */
1807#define PBF_REG_P0_CREDIT 0x140200
1808/* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte
1809 lines. */
1810#define PBF_REG_P0_INIT_CRD 0x1400d0
1811/* [RW 1] Indication that pause is enabled for port 0. */
1812#define PBF_REG_P0_PAUSE_ENABLE 0x140014
1813/* [R 8] Number of tasks in port 0 task queue. */
1814#define PBF_REG_P0_TASK_CNT 0x140204
1815/* [R 11] Current credit for port 1 in the tx port buffers in 16 byte lines. */
1816#define PBF_REG_P1_CREDIT 0x140208
1817/* [RW 11] Initial credit for port 1 in the tx port buffers in 16 byte
1818 lines. */
1819#define PBF_REG_P1_INIT_CRD 0x1400d4
1820/* [R 8] Number of tasks in port 1 task queue. */
1821#define PBF_REG_P1_TASK_CNT 0x14020c
1822/* [R 11] Current credit for port 4 in the tx port buffers in 16 byte lines. */
1823#define PBF_REG_P4_CREDIT 0x140210
1824/* [RW 11] Initial credit for port 4 in the tx port buffers in 16 byte
1825 lines. */
1826#define PBF_REG_P4_INIT_CRD 0x1400e0
1827/* [R 8] Number of tasks in port 4 task queue. */
1828#define PBF_REG_P4_TASK_CNT 0x140214
1829/* [RW 5] Interrupt mask register #0 read/write */
1830#define PBF_REG_PBF_INT_MASK 0x1401d4
1831/* [R 5] Interrupt register #0 read */
1832#define PBF_REG_PBF_INT_STS 0x1401c8
1833#define PB_REG_CONTROL 0
1834/* [RW 2] Interrupt mask register #0 read/write */
1835#define PB_REG_PB_INT_MASK 0x28
1836/* [R 2] Interrupt register #0 read */
1837#define PB_REG_PB_INT_STS 0x1c
1838/* [RW 4] Parity mask register #0 read/write */
1839#define PB_REG_PB_PRTY_MASK 0x38
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ET		 1840/* [R 4] Parity register #0 read */
1841#define PB_REG_PB_PRTY_STS 0x2c
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ET		 1842#define PRS_REG_A_PRSU_20 0x40134
1843/* [R 8] debug only: CFC load request current credit. Transaction based. */
1844#define PRS_REG_CFC_LD_CURRENT_CREDIT 0x40164
1845/* [R 8] debug only: CFC search request current credit. Transaction based. */
1846#define PRS_REG_CFC_SEARCH_CURRENT_CREDIT 0x40168
1847/* [RW 6] The initial credit for the search message to the CFC interface.
1848 Credit is transaction based. */
1849#define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c
1850/* [RW 24] CID for port 0 if no match */
1851#define PRS_REG_CID_PORT_0 0x400fc
1852#define PRS_REG_CID_PORT_1 0x40100
1853/* [RW 32] The CM header for flush message where 'load existed' bit in CFC
1854 load response is reset and packet type is 0. Used in packet start message
1855 to TCM. */
1856#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0 0x400dc
1857#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1 0x400e0
1858#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2 0x400e4
1859#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3 0x400e8
1860#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4 0x400ec
1861/* [RW 32] The CM header for flush message where 'load existed' bit in CFC
1862 load response is set and packet type is 0. Used in packet start message
1863 to TCM. */
1864#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0 0x400bc
1865#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1 0x400c0
1866#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0x400c4
1867#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0x400c8
1868#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0x400cc
1869/* [RW 32] The CM header for a match and packet type 1 for loopback port.
1870 Used in packet start message to TCM. */
1871#define PRS_REG_CM_HDR_LOOPBACK_TYPE_1 0x4009c
1872#define PRS_REG_CM_HDR_LOOPBACK_TYPE_2 0x400a0
1873#define PRS_REG_CM_HDR_LOOPBACK_TYPE_3 0x400a4
1874#define PRS_REG_CM_HDR_LOOPBACK_TYPE_4 0x400a8
1875/* [RW 32] The CM header for a match and packet type 0. Used in packet start
1876 message to TCM. */
1877#define PRS_REG_CM_HDR_TYPE_0 0x40078
1878#define PRS_REG_CM_HDR_TYPE_1 0x4007c
1879#define PRS_REG_CM_HDR_TYPE_2 0x40080
1880#define PRS_REG_CM_HDR_TYPE_3 0x40084
1881#define PRS_REG_CM_HDR_TYPE_4 0x40088
1882/* [RW 32] The CM header in case there was not a match on the connection */
1883#define PRS_REG_CM_NO_MATCH_HDR 0x400b8
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YR		 1884/* [RW 1] Indicates if in e1hov mode. 0=non-e1hov mode; 1=e1hov mode. */
1885#define PRS_REG_E1HOV_MODE 0x401c8
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ET		 1886/* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet
1887 start message to TCM. */
1888#define PRS_REG_EVENT_ID_1 0x40054
1889#define PRS_REG_EVENT_ID_2 0x40058
1890#define PRS_REG_EVENT_ID_3 0x4005c
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YR		 1891/* [RW 16] The Ethernet type value for FCoE */
1892#define PRS_REG_FCOE_TYPE 0x401d0
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ET		 1893/* [RW 8] Context region for flush packet with packet type 0. Used in CFC
1894 load request message. */
1895#define PRS_REG_FLUSH_REGIONS_TYPE_0 0x40004
1896#define PRS_REG_FLUSH_REGIONS_TYPE_1 0x40008
1897#define PRS_REG_FLUSH_REGIONS_TYPE_2 0x4000c
1898#define PRS_REG_FLUSH_REGIONS_TYPE_3 0x40010
1899#define PRS_REG_FLUSH_REGIONS_TYPE_4 0x40014
1900#define PRS_REG_FLUSH_REGIONS_TYPE_5 0x40018
1901#define PRS_REG_FLUSH_REGIONS_TYPE_6 0x4001c
1902#define PRS_REG_FLUSH_REGIONS_TYPE_7 0x40020
1903/* [RW 4] The increment value to send in the CFC load request message */
1904#define PRS_REG_INC_VALUE 0x40048
1905/* [RW 1] If set indicates not to send messages to CFC on received packets */
1906#define PRS_REG_NIC_MODE 0x40138
1907/* [RW 8] The 8-bit event ID for cases where there is no match on the
1908 connection. Used in packet start message to TCM. */
1909#define PRS_REG_NO_MATCH_EVENT_ID 0x40070
1910/* [ST 24] The number of input CFC flush packets */
1911#define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES 0x40128
1912/* [ST 32] The number of cycles the Parser halted its operation since it
1913 could not allocate the next serial number */
1914#define PRS_REG_NUM_OF_DEAD_CYCLES 0x40130
1915/* [ST 24] The number of input packets */
1916#define PRS_REG_NUM_OF_PACKETS 0x40124
1917/* [ST 24] The number of input transparent flush packets */
1918#define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES 0x4012c
1919/* [RW 8] Context region for received Ethernet packet with a match and
1920 packet type 0. Used in CFC load request message */
1921#define PRS_REG_PACKET_REGIONS_TYPE_0 0x40028
1922#define PRS_REG_PACKET_REGIONS_TYPE_1 0x4002c
1923#define PRS_REG_PACKET_REGIONS_TYPE_2 0x40030
1924#define PRS_REG_PACKET_REGIONS_TYPE_3 0x40034
1925#define PRS_REG_PACKET_REGIONS_TYPE_4 0x40038
1926#define PRS_REG_PACKET_REGIONS_TYPE_5 0x4003c
1927#define PRS_REG_PACKET_REGIONS_TYPE_6 0x40040
1928#define PRS_REG_PACKET_REGIONS_TYPE_7 0x40044
1929/* [R 2] debug only: Number of pending requests for CAC on port 0. */
1930#define PRS_REG_PENDING_BRB_CAC0_RQ 0x40174
1931/* [R 2] debug only: Number of pending requests for header parsing. */
1932#define PRS_REG_PENDING_BRB_PRS_RQ 0x40170
1933/* [R 1] Interrupt register #0 read */
1934#define PRS_REG_PRS_INT_STS 0x40188
1935/* [RW 8] Parity mask register #0 read/write */
1936#define PRS_REG_PRS_PRTY_MASK 0x401a4
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ET		 1937/* [R 8] Parity register #0 read */
1938#define PRS_REG_PRS_PRTY_STS 0x40198
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ET		 1939/* [RW 8] Context region for pure acknowledge packets. Used in CFC load
1940 request message */
1941#define PRS_REG_PURE_REGIONS 0x40024
1942/* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this
1943 serail number was released by SDM but cannot be used because a previous
1944 serial number was not released. */
1945#define PRS_REG_SERIAL_NUM_STATUS_LSB 0x40154
1946/* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this
1947 serail number was released by SDM but cannot be used because a previous
1948 serial number was not released. */
1949#define PRS_REG_SERIAL_NUM_STATUS_MSB 0x40158
1950/* [R 4] debug only: SRC current credit. Transaction based. */
1951#define PRS_REG_SRC_CURRENT_CREDIT 0x4016c
1952/* [R 8] debug only: TCM current credit. Cycle based. */
1953#define PRS_REG_TCM_CURRENT_CREDIT 0x40160
1954/* [R 8] debug only: TSDM current credit. Transaction based. */
1955#define PRS_REG_TSDM_CURRENT_CREDIT 0x4015c
1956/* [R 6] Debug only: Number of used entries in the data FIFO */
1957#define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c
1958/* [R 7] Debug only: Number of used entries in the header FIFO */
1959#define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478
1960#define PXP2_REG_PGL_CONTROL0 0x120490
1961#define PXP2_REG_PGL_CONTROL1 0x120514
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YR		 1962/* [RW 32] third dword data of expansion rom request. this register is
1963 special. reading from it provides a vector outstanding read requests. if
1964 a bit is zero it means that a read request on the corresponding tag did
1965 not finish yet (not all completions have arrived for it) */
1966#define PXP2_REG_PGL_EXP_ROM2 0x120808
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ET		 1967/* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask;
1968 its[15:0]-address */
1969#define PXP2_REG_PGL_INT_CSDM_0 0x1204f4
1970#define PXP2_REG_PGL_INT_CSDM_1 0x1204f8
1971#define PXP2_REG_PGL_INT_CSDM_2 0x1204fc
1972#define PXP2_REG_PGL_INT_CSDM_3 0x120500
1973#define PXP2_REG_PGL_INT_CSDM_4 0x120504
1974#define PXP2_REG_PGL_INT_CSDM_5 0x120508
1975#define PXP2_REG_PGL_INT_CSDM_6 0x12050c
1976#define PXP2_REG_PGL_INT_CSDM_7 0x120510
1977/* [RW 32] Inbound interrupt table for TSDM: bits[31:16]-mask;
1978 its[15:0]-address */
1979#define PXP2_REG_PGL_INT_TSDM_0 0x120494
1980#define PXP2_REG_PGL_INT_TSDM_1 0x120498
1981#define PXP2_REG_PGL_INT_TSDM_2 0x12049c
1982#define PXP2_REG_PGL_INT_TSDM_3 0x1204a0
1983#define PXP2_REG_PGL_INT_TSDM_4 0x1204a4
1984#define PXP2_REG_PGL_INT_TSDM_5 0x1204a8
1985#define PXP2_REG_PGL_INT_TSDM_6 0x1204ac
1986#define PXP2_REG_PGL_INT_TSDM_7 0x1204b0
1987/* [RW 32] Inbound interrupt table for USDM: bits[31:16]-mask;
1988 its[15:0]-address */
1989#define PXP2_REG_PGL_INT_USDM_0 0x1204b4
1990#define PXP2_REG_PGL_INT_USDM_1 0x1204b8
1991#define PXP2_REG_PGL_INT_USDM_2 0x1204bc
1992#define PXP2_REG_PGL_INT_USDM_3 0x1204c0
1993#define PXP2_REG_PGL_INT_USDM_4 0x1204c4
1994#define PXP2_REG_PGL_INT_USDM_5 0x1204c8
1995#define PXP2_REG_PGL_INT_USDM_6 0x1204cc
1996#define PXP2_REG_PGL_INT_USDM_7 0x1204d0
1997/* [RW 32] Inbound interrupt table for XSDM: bits[31:16]-mask;
1998 its[15:0]-address */
1999#define PXP2_REG_PGL_INT_XSDM_0 0x1204d4
2000#define PXP2_REG_PGL_INT_XSDM_1 0x1204d8
2001#define PXP2_REG_PGL_INT_XSDM_2 0x1204dc
2002#define PXP2_REG_PGL_INT_XSDM_3 0x1204e0
2003#define PXP2_REG_PGL_INT_XSDM_4 0x1204e4
2004#define PXP2_REG_PGL_INT_XSDM_5 0x1204e8
2005#define PXP2_REG_PGL_INT_XSDM_6 0x1204ec
2006#define PXP2_REG_PGL_INT_XSDM_7 0x1204f0
2007/* [R 1] this bit indicates that a read request was blocked because of
2008 bus_master_en was deasserted */
2009#define PXP2_REG_PGL_READ_BLOCKED 0x120568
c18487ee 2010#define PXP2_REG_PGL_TAGS_LIMIT 0x1205a8
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ET		 2011/* [R 18] debug only */
2012#define PXP2_REG_PGL_TXW_CDTS 0x12052c
2013/* [R 1] this bit indicates that a write request was blocked because of
2014 bus_master_en was deasserted */
2015#define PXP2_REG_PGL_WRITE_BLOCKED 0x120564
2016#define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0
2017#define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
2018#define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
2019#define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
2020#define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
2021#define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4
2022#define PXP2_REG_PSWRQ_BW_ADD28 0x120228
2023#define PXP2_REG_PSWRQ_BW_ADD28 0x120228
2024#define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8
2025#define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4
2026#define PXP2_REG_PSWRQ_BW_ADD7 0x1201d8
2027#define PXP2_REG_PSWRQ_BW_ADD8 0x1201dc
2028#define PXP2_REG_PSWRQ_BW_ADD9 0x1201e0
2029#define PXP2_REG_PSWRQ_BW_CREDIT 0x12032c
2030#define PXP2_REG_PSWRQ_BW_L1 0x1202b0
2031#define PXP2_REG_PSWRQ_BW_L10 0x1202d4
2032#define PXP2_REG_PSWRQ_BW_L11 0x1202d8
2033#define PXP2_REG_PSWRQ_BW_L10 0x1202d4
2034#define PXP2_REG_PSWRQ_BW_L11 0x1202d8
2035#define PXP2_REG_PSWRQ_BW_L2 0x1202b4
2036#define PXP2_REG_PSWRQ_BW_L28 0x120318
2037#define PXP2_REG_PSWRQ_BW_L28 0x120318
2038#define PXP2_REG_PSWRQ_BW_L3 0x1202b8
2039#define PXP2_REG_PSWRQ_BW_L6 0x1202c4
2040#define PXP2_REG_PSWRQ_BW_L7 0x1202c8
2041#define PXP2_REG_PSWRQ_BW_L8 0x1202cc
2042#define PXP2_REG_PSWRQ_BW_L9 0x1202d0
2043#define PXP2_REG_PSWRQ_BW_RD 0x120324
2044#define PXP2_REG_PSWRQ_BW_UB1 0x120238
2045#define PXP2_REG_PSWRQ_BW_UB10 0x12025c
2046#define PXP2_REG_PSWRQ_BW_UB11 0x120260
2047#define PXP2_REG_PSWRQ_BW_UB10 0x12025c
2048#define PXP2_REG_PSWRQ_BW_UB11 0x120260
2049#define PXP2_REG_PSWRQ_BW_UB2 0x12023c
2050#define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
2051#define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
2052#define PXP2_REG_PSWRQ_BW_UB3 0x120240
2053#define PXP2_REG_PSWRQ_BW_UB6 0x12024c
2054#define PXP2_REG_PSWRQ_BW_UB7 0x120250
2055#define PXP2_REG_PSWRQ_BW_UB8 0x120254
2056#define PXP2_REG_PSWRQ_BW_UB9 0x120258
2057#define PXP2_REG_PSWRQ_BW_WR 0x120328
2058#define PXP2_REG_PSWRQ_CDU0_L2P 0x120000
2059#define PXP2_REG_PSWRQ_QM0_L2P 0x120038
2060#define PXP2_REG_PSWRQ_SRC0_L2P 0x120054
2061#define PXP2_REG_PSWRQ_TM0_L2P 0x12001c
c18487ee 2062#define PXP2_REG_PSWRQ_TSDM0_L2P 0x1200e0
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ET		 2063/* [RW 25] Interrupt mask register #0 read/write */
2064#define PXP2_REG_PXP2_INT_MASK 0x120578
2065/* [R 25] Interrupt register #0 read */
2066#define PXP2_REG_PXP2_INT_STS 0x12056c
2067/* [RC 25] Interrupt register #0 read clear */
2068#define PXP2_REG_PXP2_INT_STS_CLR 0x120570
2069/* [RW 32] Parity mask register #0 read/write */
2070#define PXP2_REG_PXP2_PRTY_MASK_0 0x120588
2071#define PXP2_REG_PXP2_PRTY_MASK_1 0x120598
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ET		 2072/* [R 32] Parity register #0 read */
2073#define PXP2_REG_PXP2_PRTY_STS_0 0x12057c
2074#define PXP2_REG_PXP2_PRTY_STS_1 0x12058c
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ET		 2075/* [R 1] Debug only: The 'almost full' indication from each fifo (gives
2076 indication about backpressure) */
2077#define PXP2_REG_RD_ALMOST_FULL_0 0x120424
2078/* [R 8] Debug only: The blocks counter - number of unused block ids */
2079#define PXP2_REG_RD_BLK_CNT 0x120418
2080/* [RW 8] Debug only: Total number of available blocks in Tetris Buffer.
2081 Must be bigger than 6. Normally should not be changed. */
2082#define PXP2_REG_RD_BLK_NUM_CFG 0x12040c
2083/* [RW 2] CDU byte swapping mode configuration for master read requests */
2084#define PXP2_REG_RD_CDURD_SWAP_MODE 0x120404
2085/* [RW 1] When '1'; inputs to the PSWRD block are ignored */
2086#define PXP2_REG_RD_DISABLE_INPUTS 0x120374
2087/* [R 1] PSWRD internal memories initialization is done */
2088#define PXP2_REG_RD_INIT_DONE 0x120370
2089/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2090 allocated for vq10 */
2091#define PXP2_REG_RD_MAX_BLKS_VQ10 0x1203a0
2092/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2093 allocated for vq11 */
2094#define PXP2_REG_RD_MAX_BLKS_VQ11 0x1203a4
2095/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2096 allocated for vq17 */
2097#define PXP2_REG_RD_MAX_BLKS_VQ17 0x1203bc
2098/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2099 allocated for vq18 */
2100#define PXP2_REG_RD_MAX_BLKS_VQ18 0x1203c0
2101/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2102 allocated for vq19 */
2103#define PXP2_REG_RD_MAX_BLKS_VQ19 0x1203c4
2104/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2105 allocated for vq22 */
2106#define PXP2_REG_RD_MAX_BLKS_VQ22 0x1203d0
2107/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2108 allocated for vq6 */
2109#define PXP2_REG_RD_MAX_BLKS_VQ6 0x120390
2110/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2111 allocated for vq9 */
2112#define PXP2_REG_RD_MAX_BLKS_VQ9 0x12039c
2113/* [RW 2] PBF byte swapping mode configuration for master read requests */
2114#define PXP2_REG_RD_PBF_SWAP_MODE 0x1203f4
2115/* [R 1] Debug only: Indication if delivery ports are idle */
2116#define PXP2_REG_RD_PORT_IS_IDLE_0 0x12041c
2117#define PXP2_REG_RD_PORT_IS_IDLE_1 0x120420
2118/* [RW 2] QM byte swapping mode configuration for master read requests */
2119#define PXP2_REG_RD_QM_SWAP_MODE 0x1203f8
2120/* [R 7] Debug only: The SR counter - number of unused sub request ids */
2121#define PXP2_REG_RD_SR_CNT 0x120414
2122/* [RW 2] SRC byte swapping mode configuration for master read requests */
2123#define PXP2_REG_RD_SRC_SWAP_MODE 0x120400
2124/* [RW 7] Debug only: Total number of available PCI read sub-requests. Must
2125 be bigger than 1. Normally should not be changed. */
2126#define PXP2_REG_RD_SR_NUM_CFG 0x120408
2127/* [RW 1] Signals the PSWRD block to start initializing internal memories */
2128#define PXP2_REG_RD_START_INIT 0x12036c
2129/* [RW 2] TM byte swapping mode configuration for master read requests */
2130#define PXP2_REG_RD_TM_SWAP_MODE 0x1203fc
2131/* [RW 10] Bandwidth addition to VQ0 write requests */
2132#define PXP2_REG_RQ_BW_RD_ADD0 0x1201bc
2133/* [RW 10] Bandwidth addition to VQ12 read requests */
2134#define PXP2_REG_RQ_BW_RD_ADD12 0x1201ec
2135/* [RW 10] Bandwidth addition to VQ13 read requests */
2136#define PXP2_REG_RQ_BW_RD_ADD13 0x1201f0
2137/* [RW 10] Bandwidth addition to VQ14 read requests */
2138#define PXP2_REG_RQ_BW_RD_ADD14 0x1201f4
2139/* [RW 10] Bandwidth addition to VQ15 read requests */
2140#define PXP2_REG_RQ_BW_RD_ADD15 0x1201f8
2141/* [RW 10] Bandwidth addition to VQ16 read requests */
2142#define PXP2_REG_RQ_BW_RD_ADD16 0x1201fc
2143/* [RW 10] Bandwidth addition to VQ17 read requests */
2144#define PXP2_REG_RQ_BW_RD_ADD17 0x120200
2145/* [RW 10] Bandwidth addition to VQ18 read requests */
2146#define PXP2_REG_RQ_BW_RD_ADD18 0x120204
2147/* [RW 10] Bandwidth addition to VQ19 read requests */
2148#define PXP2_REG_RQ_BW_RD_ADD19 0x120208
2149/* [RW 10] Bandwidth addition to VQ20 read requests */
2150#define PXP2_REG_RQ_BW_RD_ADD20 0x12020c
2151/* [RW 10] Bandwidth addition to VQ22 read requests */
2152#define PXP2_REG_RQ_BW_RD_ADD22 0x120210
2153/* [RW 10] Bandwidth addition to VQ23 read requests */
2154#define PXP2_REG_RQ_BW_RD_ADD23 0x120214
2155/* [RW 10] Bandwidth addition to VQ24 read requests */
2156#define PXP2_REG_RQ_BW_RD_ADD24 0x120218
2157/* [RW 10] Bandwidth addition to VQ25 read requests */
2158#define PXP2_REG_RQ_BW_RD_ADD25 0x12021c
2159/* [RW 10] Bandwidth addition to VQ26 read requests */
2160#define PXP2_REG_RQ_BW_RD_ADD26 0x120220
2161/* [RW 10] Bandwidth addition to VQ27 read requests */
2162#define PXP2_REG_RQ_BW_RD_ADD27 0x120224
2163/* [RW 10] Bandwidth addition to VQ4 read requests */
2164#define PXP2_REG_RQ_BW_RD_ADD4 0x1201cc
2165/* [RW 10] Bandwidth addition to VQ5 read requests */
2166#define PXP2_REG_RQ_BW_RD_ADD5 0x1201d0
2167/* [RW 10] Bandwidth Typical L for VQ0 Read requests */
2168#define PXP2_REG_RQ_BW_RD_L0 0x1202ac
2169/* [RW 10] Bandwidth Typical L for VQ12 Read requests */
2170#define PXP2_REG_RQ_BW_RD_L12 0x1202dc
2171/* [RW 10] Bandwidth Typical L for VQ13 Read requests */
2172#define PXP2_REG_RQ_BW_RD_L13 0x1202e0
2173/* [RW 10] Bandwidth Typical L for VQ14 Read requests */
2174#define PXP2_REG_RQ_BW_RD_L14 0x1202e4
2175/* [RW 10] Bandwidth Typical L for VQ15 Read requests */
2176#define PXP2_REG_RQ_BW_RD_L15 0x1202e8
2177/* [RW 10] Bandwidth Typical L for VQ16 Read requests */
2178#define PXP2_REG_RQ_BW_RD_L16 0x1202ec
2179/* [RW 10] Bandwidth Typical L for VQ17 Read requests */
2180#define PXP2_REG_RQ_BW_RD_L17 0x1202f0
2181/* [RW 10] Bandwidth Typical L for VQ18 Read requests */
2182#define PXP2_REG_RQ_BW_RD_L18 0x1202f4
2183/* [RW 10] Bandwidth Typical L for VQ19 Read requests */
2184#define PXP2_REG_RQ_BW_RD_L19 0x1202f8
2185/* [RW 10] Bandwidth Typical L for VQ20 Read requests */
2186#define PXP2_REG_RQ_BW_RD_L20 0x1202fc
2187/* [RW 10] Bandwidth Typical L for VQ22 Read requests */
2188#define PXP2_REG_RQ_BW_RD_L22 0x120300
2189/* [RW 10] Bandwidth Typical L for VQ23 Read requests */
2190#define PXP2_REG_RQ_BW_RD_L23 0x120304
2191/* [RW 10] Bandwidth Typical L for VQ24 Read requests */
2192#define PXP2_REG_RQ_BW_RD_L24 0x120308
2193/* [RW 10] Bandwidth Typical L for VQ25 Read requests */
2194#define PXP2_REG_RQ_BW_RD_L25 0x12030c
2195/* [RW 10] Bandwidth Typical L for VQ26 Read requests */
2196#define PXP2_REG_RQ_BW_RD_L26 0x120310
2197/* [RW 10] Bandwidth Typical L for VQ27 Read requests */
2198#define PXP2_REG_RQ_BW_RD_L27 0x120314
2199/* [RW 10] Bandwidth Typical L for VQ4 Read requests */
2200#define PXP2_REG_RQ_BW_RD_L4 0x1202bc
2201/* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */
2202#define PXP2_REG_RQ_BW_RD_L5 0x1202c0
2203/* [RW 7] Bandwidth upper bound for VQ0 read requests */
2204#define PXP2_REG_RQ_BW_RD_UBOUND0 0x120234
2205/* [RW 7] Bandwidth upper bound for VQ12 read requests */
2206#define PXP2_REG_RQ_BW_RD_UBOUND12 0x120264
2207/* [RW 7] Bandwidth upper bound for VQ13 read requests */
2208#define PXP2_REG_RQ_BW_RD_UBOUND13 0x120268
2209/* [RW 7] Bandwidth upper bound for VQ14 read requests */
2210#define PXP2_REG_RQ_BW_RD_UBOUND14 0x12026c
2211/* [RW 7] Bandwidth upper bound for VQ15 read requests */
2212#define PXP2_REG_RQ_BW_RD_UBOUND15 0x120270
2213/* [RW 7] Bandwidth upper bound for VQ16 read requests */
2214#define PXP2_REG_RQ_BW_RD_UBOUND16 0x120274
2215/* [RW 7] Bandwidth upper bound for VQ17 read requests */
2216#define PXP2_REG_RQ_BW_RD_UBOUND17 0x120278
2217/* [RW 7] Bandwidth upper bound for VQ18 read requests */
2218#define PXP2_REG_RQ_BW_RD_UBOUND18 0x12027c
2219/* [RW 7] Bandwidth upper bound for VQ19 read requests */
2220#define PXP2_REG_RQ_BW_RD_UBOUND19 0x120280
2221/* [RW 7] Bandwidth upper bound for VQ20 read requests */
2222#define PXP2_REG_RQ_BW_RD_UBOUND20 0x120284
2223/* [RW 7] Bandwidth upper bound for VQ22 read requests */
2224#define PXP2_REG_RQ_BW_RD_UBOUND22 0x120288
2225/* [RW 7] Bandwidth upper bound for VQ23 read requests */
2226#define PXP2_REG_RQ_BW_RD_UBOUND23 0x12028c
2227/* [RW 7] Bandwidth upper bound for VQ24 read requests */
2228#define PXP2_REG_RQ_BW_RD_UBOUND24 0x120290
2229/* [RW 7] Bandwidth upper bound for VQ25 read requests */
2230#define PXP2_REG_RQ_BW_RD_UBOUND25 0x120294
2231/* [RW 7] Bandwidth upper bound for VQ26 read requests */
2232#define PXP2_REG_RQ_BW_RD_UBOUND26 0x120298
2233/* [RW 7] Bandwidth upper bound for VQ27 read requests */
2234#define PXP2_REG_RQ_BW_RD_UBOUND27 0x12029c
2235/* [RW 7] Bandwidth upper bound for VQ4 read requests */
2236#define PXP2_REG_RQ_BW_RD_UBOUND4 0x120244
2237/* [RW 7] Bandwidth upper bound for VQ5 read requests */
2238#define PXP2_REG_RQ_BW_RD_UBOUND5 0x120248
2239/* [RW 10] Bandwidth addition to VQ29 write requests */
2240#define PXP2_REG_RQ_BW_WR_ADD29 0x12022c
2241/* [RW 10] Bandwidth addition to VQ30 write requests */
2242#define PXP2_REG_RQ_BW_WR_ADD30 0x120230
2243/* [RW 10] Bandwidth Typical L for VQ29 Write requests */
2244#define PXP2_REG_RQ_BW_WR_L29 0x12031c
2245/* [RW 10] Bandwidth Typical L for VQ30 Write requests */
2246#define PXP2_REG_RQ_BW_WR_L30 0x120320
2247/* [RW 7] Bandwidth upper bound for VQ29 */
2248#define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4
2249/* [RW 7] Bandwidth upper bound for VQ30 */
2250#define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8
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YR		 2251/* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */
2252#define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR 0x120008
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ET		 2253/* [RW 2] Endian mode for cdu */
2254#define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0
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YR		 2255#define PXP2_REG_RQ_CDU_FIRST_ILT 0x12061c
2256#define PXP2_REG_RQ_CDU_LAST_ILT 0x120620
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ET		 2257/* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k;
2258 -128k */
2259#define PXP2_REG_RQ_CDU_P_SIZE 0x120018
2260/* [R 1] 1' indicates that the requester has finished its internal
2261 configuration */
2262#define PXP2_REG_RQ_CFG_DONE 0x1201b4
2263/* [RW 2] Endian mode for debug */
2264#define PXP2_REG_RQ_DBG_ENDIAN_M 0x1201a4
2265/* [RW 1] When '1'; requests will enter input buffers but wont get out
2266 towards the glue */
2267#define PXP2_REG_RQ_DISABLE_INPUTS 0x120330
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YR		 2268/* [RW 1] 1 - SR will be aligned by 64B; 0 - SR will be aligned by 8B */
2269#define PXP2_REG_RQ_DRAM_ALIGN 0x1205b0
2270/* [RW 1] If 1 ILT failiue will not result in ELT access; An interrupt will
2271 be asserted */
2272#define PXP2_REG_RQ_ELT_DISABLE 0x12066c
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ET		 2273/* [RW 2] Endian mode for hc */
2274#define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8
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YR		 2275/* [RW 1] when '0' ILT logic will work as in A0; otherwise B0; for back
2276 compatibility needs; Note that different registers are used per mode */
2277#define PXP2_REG_RQ_ILT_MODE 0x1205b4
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ET		 2278/* [WB 53] Onchip address table */
2279#define PXP2_REG_RQ_ONCHIP_AT 0x122000
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YR		 2280/* [WB 53] Onchip address table - B0 */
2281#define PXP2_REG_RQ_ONCHIP_AT_B0 0x128000
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ET		 2282/* [RW 13] Pending read limiter threshold; in Dwords */
2283#define PXP2_REG_RQ_PDR_LIMIT 0x12033c
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ET		 2284/* [RW 2] Endian mode for qm */
2285#define PXP2_REG_RQ_QM_ENDIAN_M 0x120194
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YR		 2286#define PXP2_REG_RQ_QM_FIRST_ILT 0x120634
2287#define PXP2_REG_RQ_QM_LAST_ILT 0x120638
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ET		 2288/* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k;
2289 -128k */
2290#define PXP2_REG_RQ_QM_P_SIZE 0x120050
2291/* [RW 1] 1' indicates that the RBC has finished configurating the PSWRQ */
2292#define PXP2_REG_RQ_RBC_DONE 0x1201b0
2293/* [RW 3] Max burst size filed for read requests port 0; 000 - 128B;
2294 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
2295#define PXP2_REG_RQ_RD_MBS0 0x120160
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ET		 2296/* [RW 3] Max burst size filed for read requests port 1; 000 - 128B;
2297 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
2298#define PXP2_REG_RQ_RD_MBS1 0x120168
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ET		 2299/* [RW 2] Endian mode for src */
2300#define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c
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YR		 2301#define PXP2_REG_RQ_SRC_FIRST_ILT 0x12063c
2302#define PXP2_REG_RQ_SRC_LAST_ILT 0x120640
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ET		 2303/* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k;
2304 -128k */
2305#define PXP2_REG_RQ_SRC_P_SIZE 0x12006c
2306/* [RW 2] Endian mode for tm */
2307#define PXP2_REG_RQ_TM_ENDIAN_M 0x120198
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YR		 2308#define PXP2_REG_RQ_TM_FIRST_ILT 0x120644
2309#define PXP2_REG_RQ_TM_LAST_ILT 0x120648
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ET		 2310/* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k;
2311 -128k */
2312#define PXP2_REG_RQ_TM_P_SIZE 0x120034
2313/* [R 5] Number of entries in the ufifo; his fifo has l2p completions */
2314#define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c
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YR		 2315/* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */
2316#define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR 0x120094
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ET		 2317/* [R 8] Number of entries occupied by vq 0 in pswrq memory */
2318#define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810
2319/* [R 8] Number of entries occupied by vq 10 in pswrq memory */
2320#define PXP2_REG_RQ_VQ10_ENTRY_CNT 0x120818
2321/* [R 8] Number of entries occupied by vq 11 in pswrq memory */
2322#define PXP2_REG_RQ_VQ11_ENTRY_CNT 0x120820
2323/* [R 8] Number of entries occupied by vq 12 in pswrq memory */
2324#define PXP2_REG_RQ_VQ12_ENTRY_CNT 0x120828
2325/* [R 8] Number of entries occupied by vq 13 in pswrq memory */
2326#define PXP2_REG_RQ_VQ13_ENTRY_CNT 0x120830
2327/* [R 8] Number of entries occupied by vq 14 in pswrq memory */
2328#define PXP2_REG_RQ_VQ14_ENTRY_CNT 0x120838
2329/* [R 8] Number of entries occupied by vq 15 in pswrq memory */
2330#define PXP2_REG_RQ_VQ15_ENTRY_CNT 0x120840
2331/* [R 8] Number of entries occupied by vq 16 in pswrq memory */
2332#define PXP2_REG_RQ_VQ16_ENTRY_CNT 0x120848
2333/* [R 8] Number of entries occupied by vq 17 in pswrq memory */
2334#define PXP2_REG_RQ_VQ17_ENTRY_CNT 0x120850
2335/* [R 8] Number of entries occupied by vq 18 in pswrq memory */
2336#define PXP2_REG_RQ_VQ18_ENTRY_CNT 0x120858
2337/* [R 8] Number of entries occupied by vq 19 in pswrq memory */
2338#define PXP2_REG_RQ_VQ19_ENTRY_CNT 0x120860
2339/* [R 8] Number of entries occupied by vq 1 in pswrq memory */
2340#define PXP2_REG_RQ_VQ1_ENTRY_CNT 0x120868
2341/* [R 8] Number of entries occupied by vq 20 in pswrq memory */
2342#define PXP2_REG_RQ_VQ20_ENTRY_CNT 0x120870
2343/* [R 8] Number of entries occupied by vq 21 in pswrq memory */
2344#define PXP2_REG_RQ_VQ21_ENTRY_CNT 0x120878
2345/* [R 8] Number of entries occupied by vq 22 in pswrq memory */
2346#define PXP2_REG_RQ_VQ22_ENTRY_CNT 0x120880
2347/* [R 8] Number of entries occupied by vq 23 in pswrq memory */
2348#define PXP2_REG_RQ_VQ23_ENTRY_CNT 0x120888
2349/* [R 8] Number of entries occupied by vq 24 in pswrq memory */
2350#define PXP2_REG_RQ_VQ24_ENTRY_CNT 0x120890
2351/* [R 8] Number of entries occupied by vq 25 in pswrq memory */
2352#define PXP2_REG_RQ_VQ25_ENTRY_CNT 0x120898
2353/* [R 8] Number of entries occupied by vq 26 in pswrq memory */
2354#define PXP2_REG_RQ_VQ26_ENTRY_CNT 0x1208a0
2355/* [R 8] Number of entries occupied by vq 27 in pswrq memory */
2356#define PXP2_REG_RQ_VQ27_ENTRY_CNT 0x1208a8
2357/* [R 8] Number of entries occupied by vq 28 in pswrq memory */
2358#define PXP2_REG_RQ_VQ28_ENTRY_CNT 0x1208b0
2359/* [R 8] Number of entries occupied by vq 29 in pswrq memory */
2360#define PXP2_REG_RQ_VQ29_ENTRY_CNT 0x1208b8
2361/* [R 8] Number of entries occupied by vq 2 in pswrq memory */
2362#define PXP2_REG_RQ_VQ2_ENTRY_CNT 0x1208c0
2363/* [R 8] Number of entries occupied by vq 30 in pswrq memory */
2364#define PXP2_REG_RQ_VQ30_ENTRY_CNT 0x1208c8
2365/* [R 8] Number of entries occupied by vq 31 in pswrq memory */
2366#define PXP2_REG_RQ_VQ31_ENTRY_CNT 0x1208d0
2367/* [R 8] Number of entries occupied by vq 3 in pswrq memory */
2368#define PXP2_REG_RQ_VQ3_ENTRY_CNT 0x1208d8
2369/* [R 8] Number of entries occupied by vq 4 in pswrq memory */
2370#define PXP2_REG_RQ_VQ4_ENTRY_CNT 0x1208e0
2371/* [R 8] Number of entries occupied by vq 5 in pswrq memory */
2372#define PXP2_REG_RQ_VQ5_ENTRY_CNT 0x1208e8
2373/* [R 8] Number of entries occupied by vq 6 in pswrq memory */
2374#define PXP2_REG_RQ_VQ6_ENTRY_CNT 0x1208f0
2375/* [R 8] Number of entries occupied by vq 7 in pswrq memory */
2376#define PXP2_REG_RQ_VQ7_ENTRY_CNT 0x1208f8
2377/* [R 8] Number of entries occupied by vq 8 in pswrq memory */
2378#define PXP2_REG_RQ_VQ8_ENTRY_CNT 0x120900
2379/* [R 8] Number of entries occupied by vq 9 in pswrq memory */
2380#define PXP2_REG_RQ_VQ9_ENTRY_CNT 0x120908
2381/* [RW 3] Max burst size filed for write requests port 0; 000 - 128B;
2382 001:256B; 010: 512B; */
2383#define PXP2_REG_RQ_WR_MBS0 0x12015c
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ET		 2384/* [RW 3] Max burst size filed for write requests port 1; 000 - 128B;
2385 001:256B; 010: 512B; */
2386#define PXP2_REG_RQ_WR_MBS1 0x120164
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YR		 2387/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2388 buffer reaches this number has_payload will be asserted */
2389#define PXP2_REG_WR_CDU_MPS 0x1205f0
2390/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2391 buffer reaches this number has_payload will be asserted */
2392#define PXP2_REG_WR_CSDM_MPS 0x1205d0
2393/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2394 buffer reaches this number has_payload will be asserted */
2395#define PXP2_REG_WR_DBG_MPS 0x1205e8
2396/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2397 buffer reaches this number has_payload will be asserted */
2398#define PXP2_REG_WR_DMAE_MPS 0x1205ec
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ET		 2399/* [RW 10] if Number of entries in dmae fifo will be higer than this
2400 threshold then has_payload indication will be asserted; the default value
2401 should be equal to &gt; write MBS size! */
2402#define PXP2_REG_WR_DMAE_TH 0x120368
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YR		 2403/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2404 buffer reaches this number has_payload will be asserted */
2405#define PXP2_REG_WR_HC_MPS 0x1205c8
2406/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2407 buffer reaches this number has_payload will be asserted */
2408#define PXP2_REG_WR_QM_MPS 0x1205dc
2409/* [RW 1] 0 - working in A0 mode; - working in B0 mode */
2410#define PXP2_REG_WR_REV_MODE 0x120670
2411/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2412 buffer reaches this number has_payload will be asserted */
2413#define PXP2_REG_WR_SRC_MPS 0x1205e4
2414/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2415 buffer reaches this number has_payload will be asserted */
2416#define PXP2_REG_WR_TM_MPS 0x1205e0
2417/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2418 buffer reaches this number has_payload will be asserted */
2419#define PXP2_REG_WR_TSDM_MPS 0x1205d4
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ET		 2420/* [RW 10] if Number of entries in usdmdp fifo will be higer than this
2421 threshold then has_payload indication will be asserted; the default value
2422 should be equal to &gt; write MBS size! */
2423#define PXP2_REG_WR_USDMDP_TH 0x120348
c18487ee
YR		 2424/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2425 buffer reaches this number has_payload will be asserted */
2426#define PXP2_REG_WR_USDM_MPS 0x1205cc
2427/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2428 buffer reaches this number has_payload will be asserted */
2429#define PXP2_REG_WR_XSDM_MPS 0x1205d8
a2fbb9ea
ET		 2430/* [R 1] debug only: Indication if PSWHST arbiter is idle */
2431#define PXP_REG_HST_ARB_IS_IDLE 0x103004
2432/* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means
2433 this client is waiting for the arbiter. */
2434#define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008
c18487ee
YR		 2435/* [R 1] debug only: '1' means this PSWHST is discarding doorbells. This bit
2436 should update accoring to 'hst_discard_doorbells' register when the state
2437 machine is idle */
2438#define PXP_REG_HST_DISCARD_DOORBELLS_STATUS 0x1030a0
2439/* [R 6] debug only: A bit mask for all PSWHST internal write clients. '1'
2440 means this PSWHST is discarding inputs from this client. Each bit should
2441 update accoring to 'hst_discard_internal_writes' register when the state
2442 machine is idle. */
2443#define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS 0x10309c
a2fbb9ea
ET		 2444/* [WB 160] Used for initialization of the inbound interrupts memory */
2445#define PXP_REG_HST_INBOUND_INT 0x103800
2446/* [RW 32] Interrupt mask register #0 read/write */
2447#define PXP_REG_PXP_INT_MASK_0 0x103074
2448#define PXP_REG_PXP_INT_MASK_1 0x103084
2449/* [R 32] Interrupt register #0 read */
2450#define PXP_REG_PXP_INT_STS_0 0x103068
2451#define PXP_REG_PXP_INT_STS_1 0x103078
2452/* [RC 32] Interrupt register #0 read clear */
2453#define PXP_REG_PXP_INT_STS_CLR_0 0x10306c
2454/* [RW 26] Parity mask register #0 read/write */
2455#define PXP_REG_PXP_PRTY_MASK 0x103094
f1410647
ET		 2456/* [R 26] Parity register #0 read */
2457#define PXP_REG_PXP_PRTY_STS 0x103088
a2fbb9ea
ET		 2458/* [RW 4] The activity counter initial increment value sent in the load
2459 request */
2460#define QM_REG_ACTCTRINITVAL_0 0x168040
2461#define QM_REG_ACTCTRINITVAL_1 0x168044
2462#define QM_REG_ACTCTRINITVAL_2 0x168048
2463#define QM_REG_ACTCTRINITVAL_3 0x16804c
2464/* [RW 32] The base logical address (in bytes) of each physical queue. The
2465 index I represents the physical queue number. The 12 lsbs are ignore and
c18487ee
YR		 2466 considered zero so practically there are only 20 bits in this register;
2467 queues 63-0 */
a2fbb9ea
ET		 2468#define QM_REG_BASEADDR 0x168900
2469/* [RW 16] The byte credit cost for each task. This value is for both ports */
2470#define QM_REG_BYTECRDCOST 0x168234
2471/* [RW 16] The initial byte credit value for both ports. */
2472#define QM_REG_BYTECRDINITVAL 0x168238
2473/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
c18487ee 2474 queue uses port 0 else it uses port 1; queues 31-0 */
a2fbb9ea
ET		 2475#define QM_REG_BYTECRDPORT_LSB 0x168228
2476/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
c18487ee
YR		 2477 queue uses port 0 else it uses port 1; queues 95-64 */
2478#define QM_REG_BYTECRDPORT_LSB_EXT_A 0x16e520
2479/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
2480 queue uses port 0 else it uses port 1; queues 63-32 */
a2fbb9ea 2481#define QM_REG_BYTECRDPORT_MSB 0x168224
c18487ee
YR		 2482/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
2483 queue uses port 0 else it uses port 1; queues 127-96 */
2484#define QM_REG_BYTECRDPORT_MSB_EXT_A 0x16e51c
a2fbb9ea
ET		 2485/* [RW 16] The byte credit value that if above the QM is considered almost
2486 full */
2487#define QM_REG_BYTECREDITAFULLTHR 0x168094
2488/* [RW 4] The initial credit for interface */
2489#define QM_REG_CMINITCRD_0 0x1680cc
2490#define QM_REG_CMINITCRD_1 0x1680d0
2491#define QM_REG_CMINITCRD_2 0x1680d4
2492#define QM_REG_CMINITCRD_3 0x1680d8
2493#define QM_REG_CMINITCRD_4 0x1680dc
2494#define QM_REG_CMINITCRD_5 0x1680e0
2495#define QM_REG_CMINITCRD_6 0x1680e4
2496#define QM_REG_CMINITCRD_7 0x1680e8
2497/* [RW 8] A mask bit per CM interface. If this bit is 0 then this interface
2498 is masked */
2499#define QM_REG_CMINTEN 0x1680ec
2500/* [RW 12] A bit vector which indicates which one of the queues are tied to
2501 interface 0 */
2502#define QM_REG_CMINTVOQMASK_0 0x1681f4
2503#define QM_REG_CMINTVOQMASK_1 0x1681f8
2504#define QM_REG_CMINTVOQMASK_2 0x1681fc
2505#define QM_REG_CMINTVOQMASK_3 0x168200
2506#define QM_REG_CMINTVOQMASK_4 0x168204
2507#define QM_REG_CMINTVOQMASK_5 0x168208
2508#define QM_REG_CMINTVOQMASK_6 0x16820c
2509#define QM_REG_CMINTVOQMASK_7 0x168210
2510/* [RW 20] The number of connections divided by 16 which dictates the size
c18487ee 2511 of each queue which belongs to even function number. */
a2fbb9ea
ET		 2512#define QM_REG_CONNNUM_0 0x168020
2513/* [R 6] Keep the fill level of the fifo from write client 4 */
2514#define QM_REG_CQM_WRC_FIFOLVL 0x168018
2515/* [RW 8] The context regions sent in the CFC load request */
2516#define QM_REG_CTXREG_0 0x168030
2517#define QM_REG_CTXREG_1 0x168034
2518#define QM_REG_CTXREG_2 0x168038
2519#define QM_REG_CTXREG_3 0x16803c
2520/* [RW 12] The VOQ mask used to select the VOQs which needs to be full for
2521 bypass enable */
2522#define QM_REG_ENBYPVOQMASK 0x16823c
2523/* [RW 32] A bit mask per each physical queue. If a bit is set then the
c18487ee 2524 physical queue uses the byte credit; queues 31-0 */
a2fbb9ea
ET		 2525#define QM_REG_ENBYTECRD_LSB 0x168220
2526/* [RW 32] A bit mask per each physical queue. If a bit is set then the
c18487ee
YR		 2527 physical queue uses the byte credit; queues 95-64 */
2528#define QM_REG_ENBYTECRD_LSB_EXT_A 0x16e518
2529/* [RW 32] A bit mask per each physical queue. If a bit is set then the
2530 physical queue uses the byte credit; queues 63-32 */
a2fbb9ea 2531#define QM_REG_ENBYTECRD_MSB 0x16821c
c18487ee
YR		 2532/* [RW 32] A bit mask per each physical queue. If a bit is set then the
2533 physical queue uses the byte credit; queues 127-96 */
2534#define QM_REG_ENBYTECRD_MSB_EXT_A 0x16e514
a2fbb9ea
ET		 2535/* [RW 4] If cleared then the secondary interface will not be served by the
2536 RR arbiter */
2537#define QM_REG_ENSEC 0x1680f0
c18487ee 2538/* [RW 32] NA */
a2fbb9ea 2539#define QM_REG_FUNCNUMSEL_LSB 0x168230
c18487ee 2540/* [RW 32] NA */
a2fbb9ea
ET		 2541#define QM_REG_FUNCNUMSEL_MSB 0x16822c
2542/* [RW 32] A mask register to mask the Almost empty signals which will not
c18487ee 2543 be use for the almost empty indication to the HW block; queues 31:0 */
a2fbb9ea
ET		 2544#define QM_REG_HWAEMPTYMASK_LSB 0x168218
2545/* [RW 32] A mask register to mask the Almost empty signals which will not
c18487ee
YR		 2546 be use for the almost empty indication to the HW block; queues 95-64 */
2547#define QM_REG_HWAEMPTYMASK_LSB_EXT_A 0x16e510
2548/* [RW 32] A mask register to mask the Almost empty signals which will not
2549 be use for the almost empty indication to the HW block; queues 63:32 */
a2fbb9ea 2550#define QM_REG_HWAEMPTYMASK_MSB 0x168214
c18487ee
YR		 2551/* [RW 32] A mask register to mask the Almost empty signals which will not
2552 be use for the almost empty indication to the HW block; queues 127-96 */
2553#define QM_REG_HWAEMPTYMASK_MSB_EXT_A 0x16e50c
a2fbb9ea
ET		 2554/* [RW 4] The number of outstanding request to CFC */
2555#define QM_REG_OUTLDREQ 0x168804
2556/* [RC 1] A flag to indicate that overflow error occurred in one of the
2557 queues. */
2558#define QM_REG_OVFERROR 0x16805c
c18487ee 2559/* [RC 7] the Q were the qverflow occurs */
a2fbb9ea 2560#define QM_REG_OVFQNUM 0x168058
c18487ee 2561/* [R 16] Pause state for physical queues 15-0 */
a2fbb9ea 2562#define QM_REG_PAUSESTATE0 0x168410
c18487ee 2563/* [R 16] Pause state for physical queues 31-16 */
a2fbb9ea 2564#define QM_REG_PAUSESTATE1 0x168414
c18487ee
YR		 2565/* [R 16] Pause state for physical queues 47-32 */
2566#define QM_REG_PAUSESTATE2 0x16e684
2567/* [R 16] Pause state for physical queues 63-48 */
2568#define QM_REG_PAUSESTATE3 0x16e688
2569/* [R 16] Pause state for physical queues 79-64 */
2570#define QM_REG_PAUSESTATE4 0x16e68c
2571/* [R 16] Pause state for physical queues 95-80 */
2572#define QM_REG_PAUSESTATE5 0x16e690
2573/* [R 16] Pause state for physical queues 111-96 */
2574#define QM_REG_PAUSESTATE6 0x16e694
2575/* [R 16] Pause state for physical queues 127-112 */
2576#define QM_REG_PAUSESTATE7 0x16e698
a2fbb9ea
ET		 2577/* [RW 2] The PCI attributes field used in the PCI request. */
2578#define QM_REG_PCIREQAT 0x168054
2579/* [R 16] The byte credit of port 0 */
2580#define QM_REG_PORT0BYTECRD 0x168300
2581/* [R 16] The byte credit of port 1 */
2582#define QM_REG_PORT1BYTECRD 0x168304
c18487ee
YR		 2583/* [RW 3] pci function number of queues 15-0 */
2584#define QM_REG_PQ2PCIFUNC_0 0x16e6bc
2585#define QM_REG_PQ2PCIFUNC_1 0x16e6c0
2586#define QM_REG_PQ2PCIFUNC_2 0x16e6c4
2587#define QM_REG_PQ2PCIFUNC_3 0x16e6c8
2588#define QM_REG_PQ2PCIFUNC_4 0x16e6cc
2589#define QM_REG_PQ2PCIFUNC_5 0x16e6d0
2590#define QM_REG_PQ2PCIFUNC_6 0x16e6d4
2591#define QM_REG_PQ2PCIFUNC_7 0x16e6d8
2592/* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow:
2593 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
2594 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
a2fbb9ea 2595#define QM_REG_PTRTBL 0x168a00
c18487ee
YR		 2596/* [WB 54] Pointer Table Memory for queues 127-64; The mapping is as follow:
2597 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
2598 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
2599#define QM_REG_PTRTBL_EXT_A 0x16e200
a2fbb9ea
ET		 2600/* [RW 2] Interrupt mask register #0 read/write */
2601#define QM_REG_QM_INT_MASK 0x168444
2602/* [R 2] Interrupt register #0 read */
2603#define QM_REG_QM_INT_STS 0x168438
c18487ee 2604/* [RW 12] Parity mask register #0 read/write */
a2fbb9ea 2605#define QM_REG_QM_PRTY_MASK 0x168454
c18487ee 2606/* [R 12] Parity register #0 read */
f1410647 2607#define QM_REG_QM_PRTY_STS 0x168448
a2fbb9ea
ET		 2608/* [R 32] Current queues in pipeline: Queues from 32 to 63 */
2609#define QM_REG_QSTATUS_HIGH 0x16802c
c18487ee
YR		 2610/* [R 32] Current queues in pipeline: Queues from 96 to 127 */
2611#define QM_REG_QSTATUS_HIGH_EXT_A 0x16e408
a2fbb9ea
ET		 2612/* [R 32] Current queues in pipeline: Queues from 0 to 31 */
2613#define QM_REG_QSTATUS_LOW 0x168028
c18487ee
YR		 2614/* [R 32] Current queues in pipeline: Queues from 64 to 95 */
2615#define QM_REG_QSTATUS_LOW_EXT_A 0x16e404
2616/* [R 24] The number of tasks queued for each queue; queues 63-0 */
a2fbb9ea 2617#define QM_REG_QTASKCTR_0 0x168308
c18487ee
YR		 2618/* [R 24] The number of tasks queued for each queue; queues 127-64 */
2619#define QM_REG_QTASKCTR_EXT_A_0 0x16e584
a2fbb9ea
ET		 2620/* [RW 4] Queue tied to VOQ */
2621#define QM_REG_QVOQIDX_0 0x1680f4
2622#define QM_REG_QVOQIDX_10 0x16811c
c18487ee
YR		 2623#define QM_REG_QVOQIDX_100 0x16e49c
2624#define QM_REG_QVOQIDX_101 0x16e4a0
2625#define QM_REG_QVOQIDX_102 0x16e4a4
2626#define QM_REG_QVOQIDX_103 0x16e4a8
2627#define QM_REG_QVOQIDX_104 0x16e4ac
2628#define QM_REG_QVOQIDX_105 0x16e4b0
2629#define QM_REG_QVOQIDX_106 0x16e4b4
2630#define QM_REG_QVOQIDX_107 0x16e4b8
2631#define QM_REG_QVOQIDX_108 0x16e4bc
2632#define QM_REG_QVOQIDX_109 0x16e4c0
2633#define QM_REG_QVOQIDX_100 0x16e49c
2634#define QM_REG_QVOQIDX_101 0x16e4a0
2635#define QM_REG_QVOQIDX_102 0x16e4a4
2636#define QM_REG_QVOQIDX_103 0x16e4a8
2637#define QM_REG_QVOQIDX_104 0x16e4ac
2638#define QM_REG_QVOQIDX_105 0x16e4b0
2639#define QM_REG_QVOQIDX_106 0x16e4b4
2640#define QM_REG_QVOQIDX_107 0x16e4b8
2641#define QM_REG_QVOQIDX_108 0x16e4bc
2642#define QM_REG_QVOQIDX_109 0x16e4c0
a2fbb9ea 2643#define QM_REG_QVOQIDX_11 0x168120
c18487ee
YR		 2644#define QM_REG_QVOQIDX_110 0x16e4c4
2645#define QM_REG_QVOQIDX_111 0x16e4c8
2646#define QM_REG_QVOQIDX_112 0x16e4cc
2647#define QM_REG_QVOQIDX_113 0x16e4d0
2648#define QM_REG_QVOQIDX_114 0x16e4d4
2649#define QM_REG_QVOQIDX_115 0x16e4d8
2650#define QM_REG_QVOQIDX_116 0x16e4dc
2651#define QM_REG_QVOQIDX_117 0x16e4e0
2652#define QM_REG_QVOQIDX_118 0x16e4e4
2653#define QM_REG_QVOQIDX_119 0x16e4e8
2654#define QM_REG_QVOQIDX_110 0x16e4c4
2655#define QM_REG_QVOQIDX_111 0x16e4c8
2656#define QM_REG_QVOQIDX_112 0x16e4cc
2657#define QM_REG_QVOQIDX_113 0x16e4d0
2658#define QM_REG_QVOQIDX_114 0x16e4d4
2659#define QM_REG_QVOQIDX_115 0x16e4d8
2660#define QM_REG_QVOQIDX_116 0x16e4dc
2661#define QM_REG_QVOQIDX_117 0x16e4e0
2662#define QM_REG_QVOQIDX_118 0x16e4e4
2663#define QM_REG_QVOQIDX_119 0x16e4e8
a2fbb9ea 2664#define QM_REG_QVOQIDX_12 0x168124
c18487ee
YR		 2665#define QM_REG_QVOQIDX_120 0x16e4ec
2666#define QM_REG_QVOQIDX_121 0x16e4f0
2667#define QM_REG_QVOQIDX_122 0x16e4f4
2668#define QM_REG_QVOQIDX_123 0x16e4f8
2669#define QM_REG_QVOQIDX_124 0x16e4fc
2670#define QM_REG_QVOQIDX_125 0x16e500
2671#define QM_REG_QVOQIDX_126 0x16e504
2672#define QM_REG_QVOQIDX_127 0x16e508
2673#define QM_REG_QVOQIDX_120 0x16e4ec
2674#define QM_REG_QVOQIDX_121 0x16e4f0
2675#define QM_REG_QVOQIDX_122 0x16e4f4
2676#define QM_REG_QVOQIDX_123 0x16e4f8
2677#define QM_REG_QVOQIDX_124 0x16e4fc
2678#define QM_REG_QVOQIDX_125 0x16e500
2679#define QM_REG_QVOQIDX_126 0x16e504
2680#define QM_REG_QVOQIDX_127 0x16e508
a2fbb9ea
ET		 2681#define QM_REG_QVOQIDX_13 0x168128
2682#define QM_REG_QVOQIDX_14 0x16812c
2683#define QM_REG_QVOQIDX_15 0x168130
2684#define QM_REG_QVOQIDX_16 0x168134
2685#define QM_REG_QVOQIDX_17 0x168138
2686#define QM_REG_QVOQIDX_21 0x168148
c18487ee
YR		 2687#define QM_REG_QVOQIDX_22 0x16814c
2688#define QM_REG_QVOQIDX_23 0x168150
2689#define QM_REG_QVOQIDX_24 0x168154
a2fbb9ea 2690#define QM_REG_QVOQIDX_25 0x168158
c18487ee
YR		 2691#define QM_REG_QVOQIDX_26 0x16815c
2692#define QM_REG_QVOQIDX_27 0x168160
2693#define QM_REG_QVOQIDX_28 0x168164
a2fbb9ea 2694#define QM_REG_QVOQIDX_29 0x168168
c18487ee
YR		 2695#define QM_REG_QVOQIDX_30 0x16816c
2696#define QM_REG_QVOQIDX_31 0x168170
a2fbb9ea
ET		 2697#define QM_REG_QVOQIDX_32 0x168174
2698#define QM_REG_QVOQIDX_33 0x168178
2699#define QM_REG_QVOQIDX_34 0x16817c
2700#define QM_REG_QVOQIDX_35 0x168180
2701#define QM_REG_QVOQIDX_36 0x168184
2702#define QM_REG_QVOQIDX_37 0x168188
2703#define QM_REG_QVOQIDX_38 0x16818c
2704#define QM_REG_QVOQIDX_39 0x168190
2705#define QM_REG_QVOQIDX_40 0x168194
2706#define QM_REG_QVOQIDX_41 0x168198
2707#define QM_REG_QVOQIDX_42 0x16819c
2708#define QM_REG_QVOQIDX_43 0x1681a0
2709#define QM_REG_QVOQIDX_44 0x1681a4
2710#define QM_REG_QVOQIDX_45 0x1681a8
2711#define QM_REG_QVOQIDX_46 0x1681ac
2712#define QM_REG_QVOQIDX_47 0x1681b0
2713#define QM_REG_QVOQIDX_48 0x1681b4
2714#define QM_REG_QVOQIDX_49 0x1681b8
2715#define QM_REG_QVOQIDX_5 0x168108
2716#define QM_REG_QVOQIDX_50 0x1681bc
2717#define QM_REG_QVOQIDX_51 0x1681c0
2718#define QM_REG_QVOQIDX_52 0x1681c4
2719#define QM_REG_QVOQIDX_53 0x1681c8
2720#define QM_REG_QVOQIDX_54 0x1681cc
2721#define QM_REG_QVOQIDX_55 0x1681d0
2722#define QM_REG_QVOQIDX_56 0x1681d4
2723#define QM_REG_QVOQIDX_57 0x1681d8
2724#define QM_REG_QVOQIDX_58 0x1681dc
2725#define QM_REG_QVOQIDX_59 0x1681e0
2726#define QM_REG_QVOQIDX_50 0x1681bc
2727#define QM_REG_QVOQIDX_51 0x1681c0
2728#define QM_REG_QVOQIDX_52 0x1681c4
2729#define QM_REG_QVOQIDX_53 0x1681c8
2730#define QM_REG_QVOQIDX_54 0x1681cc
2731#define QM_REG_QVOQIDX_55 0x1681d0
2732#define QM_REG_QVOQIDX_56 0x1681d4
2733#define QM_REG_QVOQIDX_57 0x1681d8
2734#define QM_REG_QVOQIDX_58 0x1681dc
2735#define QM_REG_QVOQIDX_59 0x1681e0
2736#define QM_REG_QVOQIDX_6 0x16810c
2737#define QM_REG_QVOQIDX_60 0x1681e4
2738#define QM_REG_QVOQIDX_61 0x1681e8
2739#define QM_REG_QVOQIDX_62 0x1681ec
2740#define QM_REG_QVOQIDX_63 0x1681f0
c18487ee
YR		 2741#define QM_REG_QVOQIDX_64 0x16e40c
2742#define QM_REG_QVOQIDX_65 0x16e410
2743#define QM_REG_QVOQIDX_66 0x16e414
2744#define QM_REG_QVOQIDX_67 0x16e418
2745#define QM_REG_QVOQIDX_68 0x16e41c
2746#define QM_REG_QVOQIDX_69 0x16e420
a2fbb9ea
ET		 2747#define QM_REG_QVOQIDX_60 0x1681e4
2748#define QM_REG_QVOQIDX_61 0x1681e8
2749#define QM_REG_QVOQIDX_62 0x1681ec
2750#define QM_REG_QVOQIDX_63 0x1681f0
c18487ee
YR		 2751#define QM_REG_QVOQIDX_64 0x16e40c
2752#define QM_REG_QVOQIDX_65 0x16e410
2753#define QM_REG_QVOQIDX_69 0x16e420
a2fbb9ea 2754#define QM_REG_QVOQIDX_7 0x168110
c18487ee
YR		 2755#define QM_REG_QVOQIDX_70 0x16e424
2756#define QM_REG_QVOQIDX_71 0x16e428
2757#define QM_REG_QVOQIDX_72 0x16e42c
2758#define QM_REG_QVOQIDX_73 0x16e430
2759#define QM_REG_QVOQIDX_74 0x16e434
2760#define QM_REG_QVOQIDX_75 0x16e438
2761#define QM_REG_QVOQIDX_76 0x16e43c
2762#define QM_REG_QVOQIDX_77 0x16e440
2763#define QM_REG_QVOQIDX_78 0x16e444
2764#define QM_REG_QVOQIDX_79 0x16e448
2765#define QM_REG_QVOQIDX_70 0x16e424
2766#define QM_REG_QVOQIDX_71 0x16e428
2767#define QM_REG_QVOQIDX_72 0x16e42c
2768#define QM_REG_QVOQIDX_73 0x16e430
2769#define QM_REG_QVOQIDX_74 0x16e434
2770#define QM_REG_QVOQIDX_75 0x16e438
2771#define QM_REG_QVOQIDX_76 0x16e43c
2772#define QM_REG_QVOQIDX_77 0x16e440
2773#define QM_REG_QVOQIDX_78 0x16e444
2774#define QM_REG_QVOQIDX_79 0x16e448
a2fbb9ea 2775#define QM_REG_QVOQIDX_8 0x168114
c18487ee
YR		 2776#define QM_REG_QVOQIDX_80 0x16e44c
2777#define QM_REG_QVOQIDX_81 0x16e450
2778#define QM_REG_QVOQIDX_82 0x16e454
2779#define QM_REG_QVOQIDX_83 0x16e458
2780#define QM_REG_QVOQIDX_84 0x16e45c
2781#define QM_REG_QVOQIDX_85 0x16e460
2782#define QM_REG_QVOQIDX_86 0x16e464
2783#define QM_REG_QVOQIDX_87 0x16e468
2784#define QM_REG_QVOQIDX_88 0x16e46c
2785#define QM_REG_QVOQIDX_89 0x16e470
2786#define QM_REG_QVOQIDX_80 0x16e44c
2787#define QM_REG_QVOQIDX_81 0x16e450
2788#define QM_REG_QVOQIDX_85 0x16e460
2789#define QM_REG_QVOQIDX_86 0x16e464
2790#define QM_REG_QVOQIDX_87 0x16e468
2791#define QM_REG_QVOQIDX_88 0x16e46c
2792#define QM_REG_QVOQIDX_89 0x16e470
a2fbb9ea 2793#define QM_REG_QVOQIDX_9 0x168118
c18487ee
YR		 2794#define QM_REG_QVOQIDX_90 0x16e474
2795#define QM_REG_QVOQIDX_91 0x16e478
2796#define QM_REG_QVOQIDX_92 0x16e47c
2797#define QM_REG_QVOQIDX_93 0x16e480
2798#define QM_REG_QVOQIDX_94 0x16e484
2799#define QM_REG_QVOQIDX_95 0x16e488
2800#define QM_REG_QVOQIDX_96 0x16e48c
2801#define QM_REG_QVOQIDX_97 0x16e490
2802#define QM_REG_QVOQIDX_98 0x16e494
2803#define QM_REG_QVOQIDX_99 0x16e498
2804#define QM_REG_QVOQIDX_90 0x16e474
2805#define QM_REG_QVOQIDX_91 0x16e478
2806#define QM_REG_QVOQIDX_92 0x16e47c
2807#define QM_REG_QVOQIDX_93 0x16e480
2808#define QM_REG_QVOQIDX_94 0x16e484
2809#define QM_REG_QVOQIDX_95 0x16e488
2810#define QM_REG_QVOQIDX_96 0x16e48c
2811#define QM_REG_QVOQIDX_97 0x16e490
2812#define QM_REG_QVOQIDX_98 0x16e494
2813#define QM_REG_QVOQIDX_99 0x16e498
2814/* [R 24] Remaining pause timeout for queues 15-0 */
a2fbb9ea 2815#define QM_REG_REMAINPAUSETM0 0x168418
c18487ee 2816/* [R 24] Remaining pause timeout for queues 31-16 */
a2fbb9ea 2817#define QM_REG_REMAINPAUSETM1 0x16841c
c18487ee
YR		 2818/* [R 24] Remaining pause timeout for queues 47-32 */
2819#define QM_REG_REMAINPAUSETM2 0x16e69c
2820/* [R 24] Remaining pause timeout for queues 63-48 */
2821#define QM_REG_REMAINPAUSETM3 0x16e6a0
2822/* [R 24] Remaining pause timeout for queues 79-64 */
2823#define QM_REG_REMAINPAUSETM4 0x16e6a4
2824/* [R 24] Remaining pause timeout for queues 95-80 */
2825#define QM_REG_REMAINPAUSETM5 0x16e6a8
2826/* [R 24] Remaining pause timeout for queues 111-96 */
2827#define QM_REG_REMAINPAUSETM6 0x16e6ac
2828/* [R 24] Remaining pause timeout for queues 127-112 */
2829#define QM_REG_REMAINPAUSETM7 0x16e6b0
a2fbb9ea
ET		 2830/* [RW 1] Initialization bit command */
2831#define QM_REG_SOFT_RESET 0x168428
2832/* [RW 8] The credit cost per every task in the QM. A value per each VOQ */
2833#define QM_REG_TASKCRDCOST_0 0x16809c
2834#define QM_REG_TASKCRDCOST_1 0x1680a0
2835#define QM_REG_TASKCRDCOST_10 0x1680c4
2836#define QM_REG_TASKCRDCOST_11 0x1680c8
2837#define QM_REG_TASKCRDCOST_2 0x1680a4
2838#define QM_REG_TASKCRDCOST_4 0x1680ac
2839#define QM_REG_TASKCRDCOST_5 0x1680b0
2840/* [R 6] Keep the fill level of the fifo from write client 3 */
2841#define QM_REG_TQM_WRC_FIFOLVL 0x168010
2842/* [R 6] Keep the fill level of the fifo from write client 2 */
2843#define QM_REG_UQM_WRC_FIFOLVL 0x168008
2844/* [RC 32] Credit update error register */
2845#define QM_REG_VOQCRDERRREG 0x168408
2846/* [R 16] The credit value for each VOQ */
2847#define QM_REG_VOQCREDIT_0 0x1682d0
2848#define QM_REG_VOQCREDIT_1 0x1682d4
2849#define QM_REG_VOQCREDIT_10 0x1682f8
2850#define QM_REG_VOQCREDIT_11 0x1682fc
2851#define QM_REG_VOQCREDIT_4 0x1682e0
2852/* [RW 16] The credit value that if above the QM is considered almost full */
2853#define QM_REG_VOQCREDITAFULLTHR 0x168090
2854/* [RW 16] The init and maximum credit for each VoQ */
2855#define QM_REG_VOQINITCREDIT_0 0x168060
2856#define QM_REG_VOQINITCREDIT_1 0x168064
2857#define QM_REG_VOQINITCREDIT_10 0x168088
2858#define QM_REG_VOQINITCREDIT_11 0x16808c
2859#define QM_REG_VOQINITCREDIT_2 0x168068
2860#define QM_REG_VOQINITCREDIT_4 0x168070
2861#define QM_REG_VOQINITCREDIT_5 0x168074
2862/* [RW 1] The port of which VOQ belongs */
c18487ee 2863#define QM_REG_VOQPORT_0 0x1682a0
a2fbb9ea
ET		 2864#define QM_REG_VOQPORT_1 0x1682a4
2865#define QM_REG_VOQPORT_10 0x1682c8
2866#define QM_REG_VOQPORT_11 0x1682cc
2867#define QM_REG_VOQPORT_2 0x1682a8
c18487ee 2868/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
a2fbb9ea 2869#define QM_REG_VOQQMASK_0_LSB 0x168240
c18487ee
YR		 2870/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2871#define QM_REG_VOQQMASK_0_LSB_EXT_A 0x16e524
2872/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
a2fbb9ea 2873#define QM_REG_VOQQMASK_0_MSB 0x168244
c18487ee
YR		 2874/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2875#define QM_REG_VOQQMASK_0_MSB_EXT_A 0x16e528
2876/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2877#define QM_REG_VOQQMASK_10_LSB 0x168290
2878/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2879#define QM_REG_VOQQMASK_10_LSB_EXT_A 0x16e574
2880/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2881#define QM_REG_VOQQMASK_10_MSB 0x168294
2882/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2883#define QM_REG_VOQQMASK_10_MSB_EXT_A 0x16e578
2884/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2885#define QM_REG_VOQQMASK_11_LSB 0x168298
2886/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2887#define QM_REG_VOQQMASK_11_LSB_EXT_A 0x16e57c
2888/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2889#define QM_REG_VOQQMASK_11_MSB 0x16829c
2890/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2891#define QM_REG_VOQQMASK_11_MSB_EXT_A 0x16e580
2892/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2893#define QM_REG_VOQQMASK_1_LSB 0x168248
2894/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2895#define QM_REG_VOQQMASK_1_LSB_EXT_A 0x16e52c
2896/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
a2fbb9ea 2897#define QM_REG_VOQQMASK_1_MSB 0x16824c
c18487ee
YR		 2898/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2899#define QM_REG_VOQQMASK_1_MSB_EXT_A 0x16e530
2900/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
a2fbb9ea 2901#define QM_REG_VOQQMASK_2_LSB 0x168250
c18487ee
YR		 2902/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2903#define QM_REG_VOQQMASK_2_LSB_EXT_A 0x16e534
2904/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
a2fbb9ea 2905#define QM_REG_VOQQMASK_2_MSB 0x168254
c18487ee
YR		 2906/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2907#define QM_REG_VOQQMASK_2_MSB_EXT_A 0x16e538
2908/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
a2fbb9ea 2909#define QM_REG_VOQQMASK_3_LSB 0x168258
c18487ee
YR		 2910/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2911#define QM_REG_VOQQMASK_3_LSB_EXT_A 0x16e53c
2912/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2913#define QM_REG_VOQQMASK_3_MSB_EXT_A 0x16e540
2914/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
a2fbb9ea 2915#define QM_REG_VOQQMASK_4_LSB 0x168260
c18487ee
YR		 2916/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2917#define QM_REG_VOQQMASK_4_LSB_EXT_A 0x16e544
2918/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
a2fbb9ea 2919#define QM_REG_VOQQMASK_4_MSB 0x168264
c18487ee
YR		 2920/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2921#define QM_REG_VOQQMASK_4_MSB_EXT_A 0x16e548
2922/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
a2fbb9ea 2923#define QM_REG_VOQQMASK_5_LSB 0x168268
c18487ee
YR		 2924/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2925#define QM_REG_VOQQMASK_5_LSB_EXT_A 0x16e54c
2926/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
a2fbb9ea 2927#define QM_REG_VOQQMASK_5_MSB 0x16826c
c18487ee
YR		 2928/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2929#define QM_REG_VOQQMASK_5_MSB_EXT_A 0x16e550
2930/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
a2fbb9ea 2931#define QM_REG_VOQQMASK_6_LSB 0x168270
c18487ee
YR		 2932/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2933#define QM_REG_VOQQMASK_6_LSB_EXT_A 0x16e554
2934/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
a2fbb9ea 2935#define QM_REG_VOQQMASK_6_MSB 0x168274
c18487ee
YR		 2936/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2937#define QM_REG_VOQQMASK_6_MSB_EXT_A 0x16e558
2938/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
a2fbb9ea 2939#define QM_REG_VOQQMASK_7_LSB 0x168278
c18487ee
YR		 2940/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2941#define QM_REG_VOQQMASK_7_LSB_EXT_A 0x16e55c
2942/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
a2fbb9ea 2943#define QM_REG_VOQQMASK_7_MSB 0x16827c
c18487ee
YR		 2944/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2945#define QM_REG_VOQQMASK_7_MSB_EXT_A 0x16e560
2946/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
a2fbb9ea 2947#define QM_REG_VOQQMASK_8_LSB 0x168280
c18487ee
YR		 2948/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2949#define QM_REG_VOQQMASK_8_LSB_EXT_A 0x16e564
2950/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
a2fbb9ea 2951#define QM_REG_VOQQMASK_8_MSB 0x168284
c18487ee
YR		 2952/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2953#define QM_REG_VOQQMASK_8_MSB_EXT_A 0x16e568
2954/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
a2fbb9ea 2955#define QM_REG_VOQQMASK_9_LSB 0x168288
c18487ee
YR		 2956/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2957#define QM_REG_VOQQMASK_9_LSB_EXT_A 0x16e56c
2958/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2959#define QM_REG_VOQQMASK_9_MSB_EXT_A 0x16e570
a2fbb9ea
ET		 2960/* [RW 32] Wrr weights */
2961#define QM_REG_WRRWEIGHTS_0 0x16880c
2962#define QM_REG_WRRWEIGHTS_1 0x168810
2963#define QM_REG_WRRWEIGHTS_10 0x168814
2964#define QM_REG_WRRWEIGHTS_10_SIZE 1
2965/* [RW 32] Wrr weights */
2966#define QM_REG_WRRWEIGHTS_11 0x168818
2967#define QM_REG_WRRWEIGHTS_11_SIZE 1
2968/* [RW 32] Wrr weights */
2969#define QM_REG_WRRWEIGHTS_12 0x16881c
2970#define QM_REG_WRRWEIGHTS_12_SIZE 1
2971/* [RW 32] Wrr weights */
2972#define QM_REG_WRRWEIGHTS_13 0x168820
2973#define QM_REG_WRRWEIGHTS_13_SIZE 1
2974/* [RW 32] Wrr weights */
2975#define QM_REG_WRRWEIGHTS_14 0x168824
2976#define QM_REG_WRRWEIGHTS_14_SIZE 1
2977/* [RW 32] Wrr weights */
2978#define QM_REG_WRRWEIGHTS_15 0x168828
2979#define QM_REG_WRRWEIGHTS_15_SIZE 1
2980/* [RW 32] Wrr weights */
c18487ee
YR		 2981#define QM_REG_WRRWEIGHTS_16 0x16e000
2982#define QM_REG_WRRWEIGHTS_16_SIZE 1
2983/* [RW 32] Wrr weights */
2984#define QM_REG_WRRWEIGHTS_17 0x16e004
2985#define QM_REG_WRRWEIGHTS_17_SIZE 1
2986/* [RW 32] Wrr weights */
2987#define QM_REG_WRRWEIGHTS_18 0x16e008
2988#define QM_REG_WRRWEIGHTS_18_SIZE 1
2989/* [RW 32] Wrr weights */
2990#define QM_REG_WRRWEIGHTS_19 0x16e00c
2991#define QM_REG_WRRWEIGHTS_19_SIZE 1
2992/* [RW 32] Wrr weights */
a2fbb9ea
ET		 2993#define QM_REG_WRRWEIGHTS_10 0x168814
2994#define QM_REG_WRRWEIGHTS_11 0x168818
2995#define QM_REG_WRRWEIGHTS_12 0x16881c
2996#define QM_REG_WRRWEIGHTS_13 0x168820
2997#define QM_REG_WRRWEIGHTS_14 0x168824
2998#define QM_REG_WRRWEIGHTS_15 0x168828
c18487ee
YR		 2999#define QM_REG_WRRWEIGHTS_16 0x16e000
3000#define QM_REG_WRRWEIGHTS_17 0x16e004
3001#define QM_REG_WRRWEIGHTS_18 0x16e008
3002#define QM_REG_WRRWEIGHTS_19 0x16e00c
a2fbb9ea 3003#define QM_REG_WRRWEIGHTS_2 0x16882c
c18487ee
YR		 3004#define QM_REG_WRRWEIGHTS_20 0x16e010
3005#define QM_REG_WRRWEIGHTS_20_SIZE 1
3006/* [RW 32] Wrr weights */
3007#define QM_REG_WRRWEIGHTS_21 0x16e014
3008#define QM_REG_WRRWEIGHTS_21_SIZE 1
3009/* [RW 32] Wrr weights */
3010#define QM_REG_WRRWEIGHTS_22 0x16e018
3011#define QM_REG_WRRWEIGHTS_22_SIZE 1
3012/* [RW 32] Wrr weights */
3013#define QM_REG_WRRWEIGHTS_23 0x16e01c
3014#define QM_REG_WRRWEIGHTS_23_SIZE 1
3015/* [RW 32] Wrr weights */
3016#define QM_REG_WRRWEIGHTS_24 0x16e020
3017#define QM_REG_WRRWEIGHTS_24_SIZE 1
3018/* [RW 32] Wrr weights */
3019#define QM_REG_WRRWEIGHTS_25 0x16e024
3020#define QM_REG_WRRWEIGHTS_25_SIZE 1
3021/* [RW 32] Wrr weights */
3022#define QM_REG_WRRWEIGHTS_26 0x16e028
3023#define QM_REG_WRRWEIGHTS_26_SIZE 1
3024/* [RW 32] Wrr weights */
3025#define QM_REG_WRRWEIGHTS_27 0x16e02c
3026#define QM_REG_WRRWEIGHTS_27_SIZE 1
3027/* [RW 32] Wrr weights */
3028#define QM_REG_WRRWEIGHTS_28 0x16e030
3029#define QM_REG_WRRWEIGHTS_28_SIZE 1
3030/* [RW 32] Wrr weights */
3031#define QM_REG_WRRWEIGHTS_29 0x16e034
3032#define QM_REG_WRRWEIGHTS_29_SIZE 1
3033/* [RW 32] Wrr weights */
3034#define QM_REG_WRRWEIGHTS_20 0x16e010
3035#define QM_REG_WRRWEIGHTS_21 0x16e014
3036#define QM_REG_WRRWEIGHTS_22 0x16e018
3037#define QM_REG_WRRWEIGHTS_23 0x16e01c
3038#define QM_REG_WRRWEIGHTS_24 0x16e020
3039#define QM_REG_WRRWEIGHTS_25 0x16e024
3040#define QM_REG_WRRWEIGHTS_26 0x16e028
3041#define QM_REG_WRRWEIGHTS_27 0x16e02c
3042#define QM_REG_WRRWEIGHTS_28 0x16e030
3043#define QM_REG_WRRWEIGHTS_29 0x16e034
a2fbb9ea 3044#define QM_REG_WRRWEIGHTS_3 0x168830
c18487ee
YR		 3045#define QM_REG_WRRWEIGHTS_30 0x16e038
3046#define QM_REG_WRRWEIGHTS_30_SIZE 1
3047/* [RW 32] Wrr weights */
3048#define QM_REG_WRRWEIGHTS_31 0x16e03c
3049#define QM_REG_WRRWEIGHTS_31_SIZE 1
3050/* [RW 32] Wrr weights */
3051#define QM_REG_WRRWEIGHTS_30 0x16e038
3052#define QM_REG_WRRWEIGHTS_31 0x16e03c
a2fbb9ea
ET		 3053#define QM_REG_WRRWEIGHTS_4 0x168834
3054#define QM_REG_WRRWEIGHTS_5 0x168838
3055#define QM_REG_WRRWEIGHTS_6 0x16883c
3056#define QM_REG_WRRWEIGHTS_7 0x168840
3057#define QM_REG_WRRWEIGHTS_8 0x168844
3058#define QM_REG_WRRWEIGHTS_9 0x168848
3059/* [R 6] Keep the fill level of the fifo from write client 1 */
3060#define QM_REG_XQM_WRC_FIFOLVL 0x168000
c18487ee
YR		 3061#define BRB1_BRB1_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3062#define BRB1_BRB1_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3063#define BRB1_BRB1_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3064#define BRB1_BRB1_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3065#define BRB1_BRB1_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3066#define BRB1_BRB1_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3067#define BRB1_BRB1_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3068#define BRB1_BRB1_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3069#define CCM_CCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3070#define CCM_CCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3071#define CCM_CCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3072#define CCM_CCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3073#define CCM_CCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3074#define CCM_CCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3075#define CCM_CCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3076#define CCM_CCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3077#define CDU_CDU_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3078#define CDU_CDU_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3079#define CDU_CDU_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3080#define CDU_CDU_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3081#define CDU_CDU_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3082#define CDU_CDU_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3083#define CDU_CDU_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3084#define CDU_CDU_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3085#define CFC_CFC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3086#define CFC_CFC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3087#define CFC_CFC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3088#define CFC_CFC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3089#define CFC_CFC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3090#define CFC_CFC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3091#define CFC_CFC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3092#define CFC_CFC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3093#define CSDM_CSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3094#define CSDM_CSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3095#define CSDM_CSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3096#define CSDM_CSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3097#define CSDM_CSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3098#define CSDM_CSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3099#define CSDM_CSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3100#define CSDM_CSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3101#define CSEM_CSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3102#define CSEM_CSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3103#define CSEM_CSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3104#define CSEM_CSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3105#define CSEM_CSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3106#define CSEM_CSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3107#define CSEM_CSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3108#define CSEM_CSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3109#define DBG_DBG_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3110#define DBG_DBG_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3111#define DBG_DBG_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3112#define DBG_DBG_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3113#define DBG_DBG_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3114#define DBG_DBG_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3115#define DBG_DBG_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3116#define DBG_DBG_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3117#define DMAE_DMAE_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3118#define DMAE_DMAE_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3119#define DMAE_DMAE_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3120#define DMAE_DMAE_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3121#define DMAE_DMAE_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3122#define DMAE_DMAE_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3123#define DMAE_DMAE_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3124#define DMAE_DMAE_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
a2fbb9ea
ET		 3125#define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3126#define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3127#define DORQ_DORQ_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3128#define DORQ_DORQ_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3129#define DORQ_DORQ_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3130#define DORQ_DORQ_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3131#define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3132#define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
c18487ee
YR		 3133#define HC_HC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3134#define HC_HC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3135#define HC_HC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3136#define HC_HC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3137#define HC_HC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3138#define HC_HC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3139#define HC_HC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3140#define HC_HC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3141#define MISC_MISC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3142#define MISC_MISC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3143#define MISC_MISC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3144#define MISC_MISC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3145#define MISC_MISC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3146#define MISC_MISC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3147#define MISC_MISC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3148#define MISC_MISC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
a2fbb9ea
ET		 3149#define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3150#define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3151#define NIG_NIG_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3152#define NIG_NIG_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3153#define NIG_NIG_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3154#define NIG_NIG_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3155#define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3156#define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
c18487ee
YR		 3157#define PBF_PBF_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3158#define PBF_PBF_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3159#define PBF_PBF_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3160#define PBF_PBF_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3161#define PBF_PBF_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3162#define PBF_PBF_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3163#define PBF_PBF_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3164#define PBF_PBF_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3165#define PB_PB_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3166#define PB_PB_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3167#define PB_PB_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3168#define PB_PB_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3169#define PB_PB_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3170#define PB_PB_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3171#define PB_PB_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3172#define PB_PB_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3173#define PRS_PRS_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3174#define PRS_PRS_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3175#define PRS_PRS_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3176#define PRS_PRS_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3177#define PRS_PRS_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3178#define PRS_PRS_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3179#define PRS_PRS_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3180#define PRS_PRS_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3181#define PXP2_PXP2_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3182#define PXP2_PXP2_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3183#define PXP2_PXP2_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3184#define PXP2_PXP2_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3185#define PXP2_PXP2_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3186#define PXP2_PXP2_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3187#define PXP2_PXP2_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3188#define PXP2_PXP2_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3189#define PXP_PXP_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3190#define PXP_PXP_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3191#define PXP_PXP_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3192#define PXP_PXP_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3193#define PXP_PXP_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3194#define PXP_PXP_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3195#define PXP_PXP_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3196#define PXP_PXP_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3197#define QM_QM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3198#define QM_QM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3199#define QM_QM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3200#define QM_QM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3201#define QM_QM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3202#define QM_QM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3203#define QM_QM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3204#define QM_QM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3205#define SEM_FAST_SEM_FAST_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3206#define SEM_FAST_SEM_FAST_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3207#define SEM_FAST_SEM_FAST_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3208#define SEM_FAST_SEM_FAST_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3209#define SEM_FAST_SEM_FAST_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3210#define SEM_FAST_SEM_FAST_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3211#define SEM_FAST_SEM_FAST_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3212#define SEM_FAST_SEM_FAST_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3213#define SRC_SRC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3214#define SRC_SRC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3215#define SRC_SRC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3216#define SRC_SRC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3217#define SRC_SRC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3218#define SRC_SRC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3219#define SRC_SRC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3220#define SRC_SRC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
a2fbb9ea
ET		 3221#define TCM_TCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3222#define TCM_TCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3223#define TCM_TCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3224#define TCM_TCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3225#define TCM_TCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3226#define TCM_TCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3227#define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3228#define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
c18487ee
YR		 3229#define TM_TM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3230#define TM_TM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3231#define TM_TM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3232#define TM_TM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3233#define TM_TM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3234#define TM_TM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3235#define TM_TM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3236#define TM_TM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3237#define TSDM_TSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3238#define TSDM_TSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3239#define TSDM_TSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3240#define TSDM_TSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3241#define TSDM_TSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3242#define TSDM_TSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3243#define TSDM_TSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3244#define TSDM_TSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3245#define TSEM_TSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3246#define TSEM_TSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3247#define TSEM_TSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3248#define TSEM_TSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3249#define TSEM_TSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3250#define TSEM_TSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3251#define TSEM_TSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3252#define TSEM_TSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3253#define UCM_UCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3254#define UCM_UCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3255#define UCM_UCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3256#define UCM_UCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3257#define UCM_UCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3258#define UCM_UCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3259#define UCM_UCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3260#define UCM_UCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3261#define USDM_USDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3262#define USDM_USDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3263#define USDM_USDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3264#define USDM_USDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3265#define USDM_USDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3266#define USDM_USDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3267#define USDM_USDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3268#define USDM_USDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3269#define USEM_USEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3270#define USEM_USEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3271#define USEM_USEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3272#define USEM_USEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3273#define USEM_USEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3274#define USEM_USEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3275#define USEM_USEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3276#define USEM_USEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3277#define XCM_XCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3278#define XCM_XCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3279#define XCM_XCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3280#define XCM_XCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3281#define XCM_XCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3282#define XCM_XCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3283#define XCM_XCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3284#define XCM_XCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3285#define XSDM_XSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3286#define XSDM_XSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3287#define XSDM_XSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3288#define XSDM_XSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3289#define XSDM_XSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3290#define XSDM_XSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3291#define XSDM_XSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3292#define XSDM_XSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3293#define XSEM_XSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3294#define XSEM_XSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3295#define XSEM_XSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3296#define XSEM_XSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3297#define XSEM_XSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3298#define XSEM_XSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3299#define XSEM_XSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3300#define XSEM_XSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
a2fbb9ea
ET		 3301#define CFC_DEBUG1_REG_WRITE_AC (0x1<<4)
3302#define CFC_DEBUG1_REG_WRITE_AC_SIZE 4
3303/* [R 1] debug only: This bit indicates wheter indicates that external
3304 buffer was wrapped (oldest data was thrown); Relevant only when
3305 ~dbg_registers_debug_target=2 (PCI) & ~dbg_registers_full_mode=1 (wrap); */
3306#define DBG_REG_WRAP_ON_EXT_BUFFER 0xc124
3307#define DBG_REG_WRAP_ON_EXT_BUFFER_SIZE 1
3308/* [R 1] debug only: This bit indicates wheter the internal buffer was
3309 wrapped (oldest data was thrown) Relevant only when
3310 ~dbg_registers_debug_target=0 (internal buffer) */
3311#define DBG_REG_WRAP_ON_INT_BUFFER 0xc128
3312#define DBG_REG_WRAP_ON_INT_BUFFER_SIZE 1
c18487ee
YR		 3313#define QM_QM_PRTY_STS_REG_WRBUFF (0x1<<8)
3314#define QM_QM_PRTY_STS_REG_WRBUFF_SIZE 8
3315#define QM_QM_PRTY_STS_CLR_REG_WRBUFF (0x1<<8)
3316#define QM_QM_PRTY_STS_CLR_REG_WRBUFF_SIZE 8
3317#define QM_QM_PRTY_STS_WR_REG_WRBUFF (0x1<<8)
3318#define QM_QM_PRTY_STS_WR_REG_WRBUFF_SIZE 8
3319#define QM_QM_PRTY_MASK_REG_WRBUFF (0x1<<8)
3320#define QM_QM_PRTY_MASK_REG_WRBUFF_SIZE 8
a2fbb9ea
ET		 3321/* [RW 32] Wrr weights */
3322#define QM_REG_WRRWEIGHTS_0 0x16880c
3323#define QM_REG_WRRWEIGHTS_0_SIZE 1
3324/* [RW 32] Wrr weights */
3325#define QM_REG_WRRWEIGHTS_1 0x168810
3326#define QM_REG_WRRWEIGHTS_1_SIZE 1
3327/* [RW 32] Wrr weights */
3328#define QM_REG_WRRWEIGHTS_10 0x168814
3329#define QM_REG_WRRWEIGHTS_10_SIZE 1
3330/* [RW 32] Wrr weights */
3331#define QM_REG_WRRWEIGHTS_11 0x168818
3332#define QM_REG_WRRWEIGHTS_11_SIZE 1
3333/* [RW 32] Wrr weights */
3334#define QM_REG_WRRWEIGHTS_12 0x16881c
3335#define QM_REG_WRRWEIGHTS_12_SIZE 1
3336/* [RW 32] Wrr weights */
3337#define QM_REG_WRRWEIGHTS_13 0x168820
3338#define QM_REG_WRRWEIGHTS_13_SIZE 1
3339/* [RW 32] Wrr weights */
3340#define QM_REG_WRRWEIGHTS_14 0x168824
3341#define QM_REG_WRRWEIGHTS_14_SIZE 1
3342/* [RW 32] Wrr weights */
3343#define QM_REG_WRRWEIGHTS_15 0x168828
3344#define QM_REG_WRRWEIGHTS_15_SIZE 1
3345/* [RW 32] Wrr weights */
3346#define QM_REG_WRRWEIGHTS_2 0x16882c
3347#define QM_REG_WRRWEIGHTS_2_SIZE 1
3348/* [RW 32] Wrr weights */
3349#define QM_REG_WRRWEIGHTS_3 0x168830
3350#define QM_REG_WRRWEIGHTS_3_SIZE 1
3351/* [RW 32] Wrr weights */
3352#define QM_REG_WRRWEIGHTS_4 0x168834
3353#define QM_REG_WRRWEIGHTS_4_SIZE 1
3354/* [RW 32] Wrr weights */
3355#define QM_REG_WRRWEIGHTS_5 0x168838
3356#define QM_REG_WRRWEIGHTS_5_SIZE 1
3357/* [RW 32] Wrr weights */
3358#define QM_REG_WRRWEIGHTS_6 0x16883c
3359#define QM_REG_WRRWEIGHTS_6_SIZE 1
3360/* [RW 32] Wrr weights */
3361#define QM_REG_WRRWEIGHTS_7 0x168840
3362#define QM_REG_WRRWEIGHTS_7_SIZE 1
3363/* [RW 32] Wrr weights */
3364#define QM_REG_WRRWEIGHTS_8 0x168844
3365#define QM_REG_WRRWEIGHTS_8_SIZE 1
3366/* [RW 32] Wrr weights */
3367#define QM_REG_WRRWEIGHTS_9 0x168848
3368#define QM_REG_WRRWEIGHTS_9_SIZE 1
c18487ee
YR		 3369/* [RW 32] Wrr weights */
3370#define QM_REG_WRRWEIGHTS_16 0x16e000
3371#define QM_REG_WRRWEIGHTS_16_SIZE 1
3372/* [RW 32] Wrr weights */
3373#define QM_REG_WRRWEIGHTS_17 0x16e004
3374#define QM_REG_WRRWEIGHTS_17_SIZE 1
3375/* [RW 32] Wrr weights */
3376#define QM_REG_WRRWEIGHTS_18 0x16e008
3377#define QM_REG_WRRWEIGHTS_18_SIZE 1
3378/* [RW 32] Wrr weights */
3379#define QM_REG_WRRWEIGHTS_19 0x16e00c
3380#define QM_REG_WRRWEIGHTS_19_SIZE 1
3381/* [RW 32] Wrr weights */
3382#define QM_REG_WRRWEIGHTS_20 0x16e010
3383#define QM_REG_WRRWEIGHTS_20_SIZE 1
3384/* [RW 32] Wrr weights */
3385#define QM_REG_WRRWEIGHTS_21 0x16e014
3386#define QM_REG_WRRWEIGHTS_21_SIZE 1
3387/* [RW 32] Wrr weights */
3388#define QM_REG_WRRWEIGHTS_22 0x16e018
3389#define QM_REG_WRRWEIGHTS_22_SIZE 1
3390/* [RW 32] Wrr weights */
3391#define QM_REG_WRRWEIGHTS_23 0x16e01c
3392#define QM_REG_WRRWEIGHTS_23_SIZE 1
3393/* [RW 32] Wrr weights */
3394#define QM_REG_WRRWEIGHTS_24 0x16e020
3395#define QM_REG_WRRWEIGHTS_24_SIZE 1
3396/* [RW 32] Wrr weights */
3397#define QM_REG_WRRWEIGHTS_25 0x16e024
3398#define QM_REG_WRRWEIGHTS_25_SIZE 1
3399/* [RW 32] Wrr weights */
3400#define QM_REG_WRRWEIGHTS_26 0x16e028
3401#define QM_REG_WRRWEIGHTS_26_SIZE 1
3402/* [RW 32] Wrr weights */
3403#define QM_REG_WRRWEIGHTS_27 0x16e02c
3404#define QM_REG_WRRWEIGHTS_27_SIZE 1
3405/* [RW 32] Wrr weights */
3406#define QM_REG_WRRWEIGHTS_28 0x16e030
3407#define QM_REG_WRRWEIGHTS_28_SIZE 1
3408/* [RW 32] Wrr weights */
3409#define QM_REG_WRRWEIGHTS_29 0x16e034
3410#define QM_REG_WRRWEIGHTS_29_SIZE 1
3411/* [RW 32] Wrr weights */
3412#define QM_REG_WRRWEIGHTS_30 0x16e038
3413#define QM_REG_WRRWEIGHTS_30_SIZE 1
3414/* [RW 32] Wrr weights */
3415#define QM_REG_WRRWEIGHTS_31 0x16e03c
3416#define QM_REG_WRRWEIGHTS_31_SIZE 1
a2fbb9ea 3417#define SRC_REG_COUNTFREE0 0x40500
c18487ee
YR		 3418/* [RW 1] If clr the searcher is compatible to E1 A0 - support only two
3419 ports. If set the searcher support 8 functions. */
3420#define SRC_REG_E1HMF_ENABLE 0x404cc
a2fbb9ea
ET		 3421#define SRC_REG_FIRSTFREE0 0x40510
3422#define SRC_REG_KEYRSS0_0 0x40408
c18487ee 3423#define SRC_REG_KEYRSS0_7 0x40424
a2fbb9ea 3424#define SRC_REG_KEYRSS1_9 0x40454
a2fbb9ea 3425#define SRC_REG_LASTFREE0 0x40530
a2fbb9ea
ET		 3426#define SRC_REG_NUMBER_HASH_BITS0 0x40400
3427/* [RW 1] Reset internal state machines. */
3428#define SRC_REG_SOFT_RST 0x4049c
c18487ee 3429/* [R 3] Interrupt register #0 read */
a2fbb9ea
ET		 3430#define SRC_REG_SRC_INT_STS 0x404ac
3431/* [RW 3] Parity mask register #0 read/write */
3432#define SRC_REG_SRC_PRTY_MASK 0x404c8
f1410647
ET		 3433/* [R 3] Parity register #0 read */
3434#define SRC_REG_SRC_PRTY_STS 0x404bc
a2fbb9ea
ET		 3435/* [R 4] Used to read the value of the XX protection CAM occupancy counter. */
3436#define TCM_REG_CAM_OCCUP 0x5017c
3437/* [RW 1] CDU AG read Interface enable. If 0 - the request input is
3438 disregarded; valid output is deasserted; all other signals are treated as
3439 usual; if 1 - normal activity. */
3440#define TCM_REG_CDU_AG_RD_IFEN 0x50034
3441/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
3442 are disregarded; all other signals are treated as usual; if 1 - normal
3443 activity. */
3444#define TCM_REG_CDU_AG_WR_IFEN 0x50030
3445/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
3446 disregarded; valid output is deasserted; all other signals are treated as
3447 usual; if 1 - normal activity. */
3448#define TCM_REG_CDU_SM_RD_IFEN 0x5003c
3449/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
3450 input is disregarded; all other signals are treated as usual; if 1 -
3451 normal activity. */
3452#define TCM_REG_CDU_SM_WR_IFEN 0x50038
3453/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
3454 the initial credit value; read returns the current value of the credit
3455 counter. Must be initialized to 1 at start-up. */
3456#define TCM_REG_CFC_INIT_CRD 0x50204
3457/* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
3458 weight 8 (the most prioritised); 1 stands for weight 1(least
3459 prioritised); 2 stands for weight 2; tc. */
3460#define TCM_REG_CP_WEIGHT 0x500c0
3461/* [RW 1] Input csem Interface enable. If 0 - the valid input is
3462 disregarded; acknowledge output is deasserted; all other signals are
3463 treated as usual; if 1 - normal activity. */
3464#define TCM_REG_CSEM_IFEN 0x5002c
3465/* [RC 1] Message length mismatch (relative to last indication) at the In#9
3466 interface. */
3467#define TCM_REG_CSEM_LENGTH_MIS 0x50174
3468/* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */
3469#define TCM_REG_ERR_EVNT_ID 0x500a0
3470/* [RW 28] The CM erroneous header for QM and Timers formatting. */
3471#define TCM_REG_ERR_TCM_HDR 0x5009c
3472/* [RW 8] The Event ID for Timers expiration. */
3473#define TCM_REG_EXPR_EVNT_ID 0x500a4
3474/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
3475 writes the initial credit value; read returns the current value of the
3476 credit counter. Must be initialized to 64 at start-up. */
3477#define TCM_REG_FIC0_INIT_CRD 0x5020c
3478/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
3479 writes the initial credit value; read returns the current value of the
3480 credit counter. Must be initialized to 64 at start-up. */
3481#define TCM_REG_FIC1_INIT_CRD 0x50210
3482/* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
3483 - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr;
3484 ~tcm_registers_gr_ld0_pr.gr_ld0_pr and
3485 ~tcm_registers_gr_ld1_pr.gr_ld1_pr. */
3486#define TCM_REG_GR_ARB_TYPE 0x50114
3487/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
3488 highest priority is 3. It is supposed that the Store channel is the
3489 compliment of the other 3 groups. */
3490#define TCM_REG_GR_LD0_PR 0x5011c
3491/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
3492 highest priority is 3. It is supposed that the Store channel is the
3493 compliment of the other 3 groups. */
3494#define TCM_REG_GR_LD1_PR 0x50120
3495/* [RW 4] The number of double REG-pairs; loaded from the STORM context and
3496 sent to STORM; for a specific connection type. The double REG-pairs are
3497 used to align to STORM context row size of 128 bits. The offset of these
3498 data in the STORM context is always 0. Index _i stands for the connection
3499 type (one of 16). */
3500#define TCM_REG_N_SM_CTX_LD_0 0x50050
3501#define TCM_REG_N_SM_CTX_LD_1 0x50054
3502#define TCM_REG_N_SM_CTX_LD_10 0x50078
3503#define TCM_REG_N_SM_CTX_LD_11 0x5007c
3504#define TCM_REG_N_SM_CTX_LD_12 0x50080
3505#define TCM_REG_N_SM_CTX_LD_13 0x50084
3506#define TCM_REG_N_SM_CTX_LD_14 0x50088
3507#define TCM_REG_N_SM_CTX_LD_15 0x5008c
3508#define TCM_REG_N_SM_CTX_LD_2 0x50058
3509#define TCM_REG_N_SM_CTX_LD_3 0x5005c
3510#define TCM_REG_N_SM_CTX_LD_4 0x50060
3511/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
3512 acknowledge output is deasserted; all other signals are treated as usual;
3513 if 1 - normal activity. */
3514#define TCM_REG_PBF_IFEN 0x50024
3515/* [RC 1] Message length mismatch (relative to last indication) at the In#7
3516 interface. */
3517#define TCM_REG_PBF_LENGTH_MIS 0x5016c
3518/* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
3519 weight 8 (the most prioritised); 1 stands for weight 1(least
3520 prioritised); 2 stands for weight 2; tc. */
3521#define TCM_REG_PBF_WEIGHT 0x500b4
a2fbb9ea
ET		 3522#define TCM_REG_PHYS_QNUM0_0 0x500e0
3523#define TCM_REG_PHYS_QNUM0_1 0x500e4
a2fbb9ea 3524#define TCM_REG_PHYS_QNUM1_0 0x500e8
c18487ee
YR		 3525#define TCM_REG_PHYS_QNUM1_1 0x500ec
3526#define TCM_REG_PHYS_QNUM2_0 0x500f0
3527#define TCM_REG_PHYS_QNUM2_1 0x500f4
3528#define TCM_REG_PHYS_QNUM3_0 0x500f8
3529#define TCM_REG_PHYS_QNUM3_1 0x500fc
a2fbb9ea
ET		 3530/* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded;
3531 acknowledge output is deasserted; all other signals are treated as usual;
3532 if 1 - normal activity. */
3533#define TCM_REG_PRS_IFEN 0x50020
3534/* [RC 1] Message length mismatch (relative to last indication) at the In#6
3535 interface. */
3536#define TCM_REG_PRS_LENGTH_MIS 0x50168
3537/* [RW 3] The weight of the input prs in the WRR mechanism. 0 stands for
3538 weight 8 (the most prioritised); 1 stands for weight 1(least
3539 prioritised); 2 stands for weight 2; tc. */
3540#define TCM_REG_PRS_WEIGHT 0x500b0
3541/* [RW 8] The Event ID for Timers formatting in case of stop done. */
3542#define TCM_REG_STOP_EVNT_ID 0x500a8
3543/* [RC 1] Message length mismatch (relative to last indication) at the STORM
3544 interface. */
3545#define TCM_REG_STORM_LENGTH_MIS 0x50160
3546/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
3547 disregarded; acknowledge output is deasserted; all other signals are
3548 treated as usual; if 1 - normal activity. */
3549#define TCM_REG_STORM_TCM_IFEN 0x50010
3550/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
3551 acknowledge output is deasserted; all other signals are treated as usual;
3552 if 1 - normal activity. */
3553#define TCM_REG_TCM_CFC_IFEN 0x50040
3554/* [RW 11] Interrupt mask register #0 read/write */
3555#define TCM_REG_TCM_INT_MASK 0x501dc
3556/* [R 11] Interrupt register #0 read */
3557#define TCM_REG_TCM_INT_STS 0x501d0
c18487ee
YR		 3558/* [R 27] Parity register #0 read */
3559#define TCM_REG_TCM_PRTY_STS 0x501e0
a2fbb9ea
ET		 3560/* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
3561 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
3562 Is used to determine the number of the AG context REG-pairs written back;
3563 when the input message Reg1WbFlg isn't set. */
3564#define TCM_REG_TCM_REG0_SZ 0x500d8
3565/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
3566 disregarded; valid is deasserted; all other signals are treated as usual;
3567 if 1 - normal activity. */
3568#define TCM_REG_TCM_STORM0_IFEN 0x50004
3569/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
3570 disregarded; valid is deasserted; all other signals are treated as usual;
3571 if 1 - normal activity. */
3572#define TCM_REG_TCM_STORM1_IFEN 0x50008
3573/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
3574 disregarded; valid is deasserted; all other signals are treated as usual;
3575 if 1 - normal activity. */
3576#define TCM_REG_TCM_TQM_IFEN 0x5000c
3577/* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
3578#define TCM_REG_TCM_TQM_USE_Q 0x500d4
3579/* [RW 28] The CM header for Timers expiration command. */
3580#define TCM_REG_TM_TCM_HDR 0x50098
3581/* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
3582 disregarded; acknowledge output is deasserted; all other signals are
3583 treated as usual; if 1 - normal activity. */
3584#define TCM_REG_TM_TCM_IFEN 0x5001c
3585/* [RW 6] QM output initial credit. Max credit available - 32.Write writes
3586 the initial credit value; read returns the current value of the credit
3587 counter. Must be initialized to 32 at start-up. */
3588#define TCM_REG_TQM_INIT_CRD 0x5021c
3589/* [RW 28] The CM header value for QM request (primary). */
3590#define TCM_REG_TQM_TCM_HDR_P 0x50090
3591/* [RW 28] The CM header value for QM request (secondary). */
3592#define TCM_REG_TQM_TCM_HDR_S 0x50094
3593/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
3594 acknowledge output is deasserted; all other signals are treated as usual;
3595 if 1 - normal activity. */
3596#define TCM_REG_TQM_TCM_IFEN 0x50014
3597/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
3598 acknowledge output is deasserted; all other signals are treated as usual;
3599 if 1 - normal activity. */
3600#define TCM_REG_TSDM_IFEN 0x50018
3601/* [RC 1] Message length mismatch (relative to last indication) at the SDM
3602 interface. */
3603#define TCM_REG_TSDM_LENGTH_MIS 0x50164
3604/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
3605 weight 8 (the most prioritised); 1 stands for weight 1(least
3606 prioritised); 2 stands for weight 2; tc. */
3607#define TCM_REG_TSDM_WEIGHT 0x500c4
3608/* [RW 1] Input usem Interface enable. If 0 - the valid input is
3609 disregarded; acknowledge output is deasserted; all other signals are
3610 treated as usual; if 1 - normal activity. */
3611#define TCM_REG_USEM_IFEN 0x50028
3612/* [RC 1] Message length mismatch (relative to last indication) at the In#8
3613 interface. */
3614#define TCM_REG_USEM_LENGTH_MIS 0x50170
3615/* [RW 21] Indirect access to the descriptor table of the XX protection
3616 mechanism. The fields are: [5:0] - length of the message; 15:6] - message
3617 pointer; 20:16] - next pointer. */
3618#define TCM_REG_XX_DESCR_TABLE 0x50280
c18487ee 3619#define TCM_REG_XX_DESCR_TABLE_SIZE 32
a2fbb9ea
ET		 3620/* [R 6] Use to read the value of XX protection Free counter. */
3621#define TCM_REG_XX_FREE 0x50178
3622/* [RW 6] Initial value for the credit counter; responsible for fulfilling
3623 of the Input Stage XX protection buffer by the XX protection pending
3624 messages. Max credit available - 127.Write writes the initial credit
3625 value; read returns the current value of the credit counter. Must be
3626 initialized to 19 at start-up. */
3627#define TCM_REG_XX_INIT_CRD 0x50220
3628/* [RW 6] Maximum link list size (messages locked) per connection in the XX
3629 protection. */
3630#define TCM_REG_XX_MAX_LL_SZ 0x50044
3631/* [RW 6] The maximum number of pending messages; which may be stored in XX
3632 protection. ~tcm_registers_xx_free.xx_free is read on read. */
3633#define TCM_REG_XX_MSG_NUM 0x50224
3634/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
3635#define TCM_REG_XX_OVFL_EVNT_ID 0x50048
3636/* [RW 16] Indirect access to the XX table of the XX protection mechanism.
3637 The fields are:[4:0] - tail pointer; [10:5] - Link List size; 15:11] -
3638 header pointer. */
3639#define TCM_REG_XX_TABLE 0x50240
3640/* [RW 4] Load value for for cfc ac credit cnt. */
3641#define TM_REG_CFC_AC_CRDCNT_VAL 0x164208
3642/* [RW 4] Load value for cfc cld credit cnt. */
3643#define TM_REG_CFC_CLD_CRDCNT_VAL 0x164210
3644/* [RW 8] Client0 context region. */
3645#define TM_REG_CL0_CONT_REGION 0x164030
3646/* [RW 8] Client1 context region. */
3647#define TM_REG_CL1_CONT_REGION 0x164034
3648/* [RW 8] Client2 context region. */
3649#define TM_REG_CL2_CONT_REGION 0x164038
3650/* [RW 2] Client in High priority client number. */
3651#define TM_REG_CLIN_PRIOR0_CLIENT 0x164024
3652/* [RW 4] Load value for clout0 cred cnt. */
3653#define TM_REG_CLOUT_CRDCNT0_VAL 0x164220
3654/* [RW 4] Load value for clout1 cred cnt. */
3655#define TM_REG_CLOUT_CRDCNT1_VAL 0x164228
3656/* [RW 4] Load value for clout2 cred cnt. */
3657#define TM_REG_CLOUT_CRDCNT2_VAL 0x164230
3658/* [RW 1] Enable client0 input. */
3659#define TM_REG_EN_CL0_INPUT 0x164008
3660/* [RW 1] Enable client1 input. */
3661#define TM_REG_EN_CL1_INPUT 0x16400c
3662/* [RW 1] Enable client2 input. */
3663#define TM_REG_EN_CL2_INPUT 0x164010
3664/* [RW 1] Enable real time counter. */
3665#define TM_REG_EN_REAL_TIME_CNT 0x1640d8
3666/* [RW 1] Enable for Timers state machines. */
3667#define TM_REG_EN_TIMERS 0x164000
3668/* [RW 4] Load value for expiration credit cnt. CFC max number of
3669 outstanding load requests for timers (expiration) context loading. */
3670#define TM_REG_EXP_CRDCNT_VAL 0x164238
c18487ee 3671/* [RW 18] Linear0 Max active cid (in banks of 32 entries). */
a2fbb9ea
ET		 3672#define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048
3673/* [WB 64] Linear0 phy address. */
3674#define TM_REG_LIN0_PHY_ADDR 0x164270
3675/* [RW 24] Linear0 array scan timeout. */
3676#define TM_REG_LIN0_SCAN_TIME 0x16403c
3677/* [WB 64] Linear1 phy address. */
3678#define TM_REG_LIN1_PHY_ADDR 0x164280
3679/* [RW 6] Linear timer set_clear fifo threshold. */
3680#define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR 0x164070
3681/* [RW 2] Load value for pci arbiter credit cnt. */
3682#define TM_REG_PCIARB_CRDCNT_VAL 0x164260
3683/* [RW 1] Timer software reset - active high. */
3684#define TM_REG_TIMER_SOFT_RST 0x164004
3685/* [RW 20] The amount of hardware cycles for each timer tick. */
3686#define TM_REG_TIMER_TICK_SIZE 0x16401c
3687/* [RW 8] Timers Context region. */
3688#define TM_REG_TM_CONTEXT_REGION 0x164044
3689/* [RW 1] Interrupt mask register #0 read/write */
3690#define TM_REG_TM_INT_MASK 0x1640fc
3691/* [R 1] Interrupt register #0 read */
3692#define TM_REG_TM_INT_STS 0x1640f0
3693/* [RW 8] The event id for aggregated interrupt 0 */
3694#define TSDM_REG_AGG_INT_EVENT_0 0x42038
c18487ee
YR		 3695#define TSDM_REG_AGG_INT_EVENT_2 0x42040
3696#define TSDM_REG_AGG_INT_EVENT_20 0x42088
3697#define TSDM_REG_AGG_INT_EVENT_21 0x4208c
3698#define TSDM_REG_AGG_INT_EVENT_22 0x42090
3699#define TSDM_REG_AGG_INT_EVENT_23 0x42094
3700#define TSDM_REG_AGG_INT_EVENT_24 0x42098
3701#define TSDM_REG_AGG_INT_EVENT_25 0x4209c
3702#define TSDM_REG_AGG_INT_EVENT_26 0x420a0
3703#define TSDM_REG_AGG_INT_EVENT_27 0x420a4
3704#define TSDM_REG_AGG_INT_EVENT_28 0x420a8
3705#define TSDM_REG_AGG_INT_EVENT_29 0x420ac
3706#define TSDM_REG_AGG_INT_EVENT_3 0x42044
3707#define TSDM_REG_AGG_INT_EVENT_30 0x420b0
3708#define TSDM_REG_AGG_INT_EVENT_31 0x420b4
3709#define TSDM_REG_AGG_INT_EVENT_4 0x42048
a2fbb9ea
ET		 3710/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
3711#define TSDM_REG_CFC_RSP_START_ADDR 0x42008
3712/* [RW 16] The maximum value of the competion counter #0 */
3713#define TSDM_REG_CMP_COUNTER_MAX0 0x4201c
3714/* [RW 16] The maximum value of the competion counter #1 */
3715#define TSDM_REG_CMP_COUNTER_MAX1 0x42020
3716/* [RW 16] The maximum value of the competion counter #2 */
3717#define TSDM_REG_CMP_COUNTER_MAX2 0x42024
3718/* [RW 16] The maximum value of the competion counter #3 */
3719#define TSDM_REG_CMP_COUNTER_MAX3 0x42028
3720/* [RW 13] The start address in the internal RAM for the completion
3721 counters. */
3722#define TSDM_REG_CMP_COUNTER_START_ADDR 0x4200c
3723#define TSDM_REG_ENABLE_IN1 0x42238
3724#define TSDM_REG_ENABLE_IN2 0x4223c
3725#define TSDM_REG_ENABLE_OUT1 0x42240
3726#define TSDM_REG_ENABLE_OUT2 0x42244
3727/* [RW 4] The initial number of messages that can be sent to the pxp control
3728 interface without receiving any ACK. */
3729#define TSDM_REG_INIT_CREDIT_PXP_CTRL 0x424bc
3730/* [ST 32] The number of ACK after placement messages received */
3731#define TSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x4227c
3732/* [ST 32] The number of packet end messages received from the parser */
3733#define TSDM_REG_NUM_OF_PKT_END_MSG 0x42274
3734/* [ST 32] The number of requests received from the pxp async if */
3735#define TSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x42278
3736/* [ST 32] The number of commands received in queue 0 */
3737#define TSDM_REG_NUM_OF_Q0_CMD 0x42248
3738/* [ST 32] The number of commands received in queue 10 */
3739#define TSDM_REG_NUM_OF_Q10_CMD 0x4226c
3740/* [ST 32] The number of commands received in queue 11 */
3741#define TSDM_REG_NUM_OF_Q11_CMD 0x42270
3742/* [ST 32] The number of commands received in queue 1 */
3743#define TSDM_REG_NUM_OF_Q1_CMD 0x4224c
3744/* [ST 32] The number of commands received in queue 3 */
3745#define TSDM_REG_NUM_OF_Q3_CMD 0x42250
3746/* [ST 32] The number of commands received in queue 4 */
3747#define TSDM_REG_NUM_OF_Q4_CMD 0x42254
3748/* [ST 32] The number of commands received in queue 5 */
3749#define TSDM_REG_NUM_OF_Q5_CMD 0x42258
3750/* [ST 32] The number of commands received in queue 6 */
3751#define TSDM_REG_NUM_OF_Q6_CMD 0x4225c
3752/* [ST 32] The number of commands received in queue 7 */
3753#define TSDM_REG_NUM_OF_Q7_CMD 0x42260
3754/* [ST 32] The number of commands received in queue 8 */
3755#define TSDM_REG_NUM_OF_Q8_CMD 0x42264
3756/* [ST 32] The number of commands received in queue 9 */
3757#define TSDM_REG_NUM_OF_Q9_CMD 0x42268
3758/* [RW 13] The start address in the internal RAM for the packet end message */
3759#define TSDM_REG_PCK_END_MSG_START_ADDR 0x42014
3760/* [RW 13] The start address in the internal RAM for queue counters */
3761#define TSDM_REG_Q_COUNTER_START_ADDR 0x42010
3762/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
3763#define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x42548
3764/* [R 1] parser fifo empty in sdm_sync block */
3765#define TSDM_REG_SYNC_PARSER_EMPTY 0x42550
3766/* [R 1] parser serial fifo empty in sdm_sync block */
3767#define TSDM_REG_SYNC_SYNC_EMPTY 0x42558
3768/* [RW 32] Tick for timer counter. Applicable only when
3769 ~tsdm_registers_timer_tick_enable.timer_tick_enable =1 */
3770#define TSDM_REG_TIMER_TICK 0x42000
3771/* [RW 32] Interrupt mask register #0 read/write */
3772#define TSDM_REG_TSDM_INT_MASK_0 0x4229c
3773#define TSDM_REG_TSDM_INT_MASK_1 0x422ac
c18487ee
YR		 3774/* [R 32] Interrupt register #0 read */
3775#define TSDM_REG_TSDM_INT_STS_0 0x42290
3776#define TSDM_REG_TSDM_INT_STS_1 0x422a0
a2fbb9ea
ET		 3777/* [RW 11] Parity mask register #0 read/write */
3778#define TSDM_REG_TSDM_PRTY_MASK 0x422bc
f1410647
ET		 3779/* [R 11] Parity register #0 read */
3780#define TSDM_REG_TSDM_PRTY_STS 0x422b0
a2fbb9ea
ET		 3781/* [RW 5] The number of time_slots in the arbitration cycle */
3782#define TSEM_REG_ARB_CYCLE_SIZE 0x180034
3783/* [RW 3] The source that is associated with arbitration element 0. Source
3784 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3785 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
3786#define TSEM_REG_ARB_ELEMENT0 0x180020
3787/* [RW 3] The source that is associated with arbitration element 1. Source
3788 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3789 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3790 Could not be equal to register ~tsem_registers_arb_element0.arb_element0 */
3791#define TSEM_REG_ARB_ELEMENT1 0x180024
3792/* [RW 3] The source that is associated with arbitration element 2. Source
3793 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3794 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3795 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
3796 and ~tsem_registers_arb_element1.arb_element1 */
3797#define TSEM_REG_ARB_ELEMENT2 0x180028
3798/* [RW 3] The source that is associated with arbitration element 3. Source
3799 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3800 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
3801 not be equal to register ~tsem_registers_arb_element0.arb_element0 and
3802 ~tsem_registers_arb_element1.arb_element1 and
3803 ~tsem_registers_arb_element2.arb_element2 */
3804#define TSEM_REG_ARB_ELEMENT3 0x18002c
3805/* [RW 3] The source that is associated with arbitration element 4. Source
3806 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3807 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3808 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
3809 and ~tsem_registers_arb_element1.arb_element1 and
3810 ~tsem_registers_arb_element2.arb_element2 and
3811 ~tsem_registers_arb_element3.arb_element3 */
3812#define TSEM_REG_ARB_ELEMENT4 0x180030
3813#define TSEM_REG_ENABLE_IN 0x1800a4
3814#define TSEM_REG_ENABLE_OUT 0x1800a8
3815/* [RW 32] This address space contains all registers and memories that are
3816 placed in SEM_FAST block. The SEM_FAST registers are described in
c18487ee
YR		 3817 appendix B. In order to access the sem_fast registers the base address
3818 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
a2fbb9ea
ET		 3819#define TSEM_REG_FAST_MEMORY 0x1a0000
3820/* [RW 1] Disables input messages from FIC0 May be updated during run_time
3821 by the microcode */
3822#define TSEM_REG_FIC0_DISABLE 0x180224
3823/* [RW 1] Disables input messages from FIC1 May be updated during run_time
3824 by the microcode */
3825#define TSEM_REG_FIC1_DISABLE 0x180234
3826/* [RW 15] Interrupt table Read and write access to it is not possible in
3827 the middle of the work */
3828#define TSEM_REG_INT_TABLE 0x180400
c18487ee 3829#define TSEM_REG_INT_TABLE_SIZE 256
a2fbb9ea
ET		 3830/* [ST 24] Statistics register. The number of messages that entered through
3831 FIC0 */
3832#define TSEM_REG_MSG_NUM_FIC0 0x180000
3833/* [ST 24] Statistics register. The number of messages that entered through
3834 FIC1 */
3835#define TSEM_REG_MSG_NUM_FIC1 0x180004
3836/* [ST 24] Statistics register. The number of messages that were sent to
3837 FOC0 */
3838#define TSEM_REG_MSG_NUM_FOC0 0x180008
3839/* [ST 24] Statistics register. The number of messages that were sent to
3840 FOC1 */
3841#define TSEM_REG_MSG_NUM_FOC1 0x18000c
3842/* [ST 24] Statistics register. The number of messages that were sent to
3843 FOC2 */
3844#define TSEM_REG_MSG_NUM_FOC2 0x180010
3845/* [ST 24] Statistics register. The number of messages that were sent to
3846 FOC3 */
3847#define TSEM_REG_MSG_NUM_FOC3 0x180014
3848/* [RW 1] Disables input messages from the passive buffer May be updated
3849 during run_time by the microcode */
3850#define TSEM_REG_PAS_DISABLE 0x18024c
3851/* [WB 128] Debug only. Passive buffer memory */
3852#define TSEM_REG_PASSIVE_BUFFER 0x181000
3853/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
3854#define TSEM_REG_PRAM 0x1c0000
3855/* [R 8] Valid sleeping threads indication have bit per thread */
3856#define TSEM_REG_SLEEP_THREADS_VALID 0x18026c
3857/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
3858#define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1802a0
3859/* [RW 8] List of free threads . There is a bit per thread. */
3860#define TSEM_REG_THREADS_LIST 0x1802e4
3861/* [RW 3] The arbitration scheme of time_slot 0 */
3862#define TSEM_REG_TS_0_AS 0x180038
3863/* [RW 3] The arbitration scheme of time_slot 10 */
3864#define TSEM_REG_TS_10_AS 0x180060
3865/* [RW 3] The arbitration scheme of time_slot 11 */
3866#define TSEM_REG_TS_11_AS 0x180064
3867/* [RW 3] The arbitration scheme of time_slot 12 */
3868#define TSEM_REG_TS_12_AS 0x180068
3869/* [RW 3] The arbitration scheme of time_slot 13 */
3870#define TSEM_REG_TS_13_AS 0x18006c
3871/* [RW 3] The arbitration scheme of time_slot 14 */
3872#define TSEM_REG_TS_14_AS 0x180070
3873/* [RW 3] The arbitration scheme of time_slot 15 */
3874#define TSEM_REG_TS_15_AS 0x180074
3875/* [RW 3] The arbitration scheme of time_slot 16 */
3876#define TSEM_REG_TS_16_AS 0x180078
3877/* [RW 3] The arbitration scheme of time_slot 17 */
3878#define TSEM_REG_TS_17_AS 0x18007c
3879/* [RW 3] The arbitration scheme of time_slot 18 */
3880#define TSEM_REG_TS_18_AS 0x180080
3881/* [RW 3] The arbitration scheme of time_slot 1 */
3882#define TSEM_REG_TS_1_AS 0x18003c
3883/* [RW 3] The arbitration scheme of time_slot 2 */
3884#define TSEM_REG_TS_2_AS 0x180040
3885/* [RW 3] The arbitration scheme of time_slot 3 */
3886#define TSEM_REG_TS_3_AS 0x180044
3887/* [RW 3] The arbitration scheme of time_slot 4 */
3888#define TSEM_REG_TS_4_AS 0x180048
3889/* [RW 3] The arbitration scheme of time_slot 5 */
3890#define TSEM_REG_TS_5_AS 0x18004c
3891/* [RW 3] The arbitration scheme of time_slot 6 */
3892#define TSEM_REG_TS_6_AS 0x180050
3893/* [RW 3] The arbitration scheme of time_slot 7 */
3894#define TSEM_REG_TS_7_AS 0x180054
3895/* [RW 3] The arbitration scheme of time_slot 8 */
3896#define TSEM_REG_TS_8_AS 0x180058
3897/* [RW 3] The arbitration scheme of time_slot 9 */
3898#define TSEM_REG_TS_9_AS 0x18005c
3899/* [RW 32] Interrupt mask register #0 read/write */
3900#define TSEM_REG_TSEM_INT_MASK_0 0x180100
3901#define TSEM_REG_TSEM_INT_MASK_1 0x180110
c18487ee
YR		 3902/* [R 32] Interrupt register #0 read */
3903#define TSEM_REG_TSEM_INT_STS_0 0x1800f4
3904#define TSEM_REG_TSEM_INT_STS_1 0x180104
a2fbb9ea
ET		 3905/* [RW 32] Parity mask register #0 read/write */
3906#define TSEM_REG_TSEM_PRTY_MASK_0 0x180120
3907#define TSEM_REG_TSEM_PRTY_MASK_1 0x180130
f1410647
ET		 3908/* [R 32] Parity register #0 read */
3909#define TSEM_REG_TSEM_PRTY_STS_0 0x180114
3910#define TSEM_REG_TSEM_PRTY_STS_1 0x180124
a2fbb9ea
ET		 3911/* [R 5] Used to read the XX protection CAM occupancy counter. */
3912#define UCM_REG_CAM_OCCUP 0xe0170
3913/* [RW 1] CDU AG read Interface enable. If 0 - the request input is
3914 disregarded; valid output is deasserted; all other signals are treated as
3915 usual; if 1 - normal activity. */
3916#define UCM_REG_CDU_AG_RD_IFEN 0xe0038
3917/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
3918 are disregarded; all other signals are treated as usual; if 1 - normal
3919 activity. */
3920#define UCM_REG_CDU_AG_WR_IFEN 0xe0034
3921/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
3922 disregarded; valid output is deasserted; all other signals are treated as
3923 usual; if 1 - normal activity. */
3924#define UCM_REG_CDU_SM_RD_IFEN 0xe0040
3925/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
3926 input is disregarded; all other signals are treated as usual; if 1 -
3927 normal activity. */
3928#define UCM_REG_CDU_SM_WR_IFEN 0xe003c
3929/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
3930 the initial credit value; read returns the current value of the credit
3931 counter. Must be initialized to 1 at start-up. */
3932#define UCM_REG_CFC_INIT_CRD 0xe0204
3933/* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
3934 weight 8 (the most prioritised); 1 stands for weight 1(least
3935 prioritised); 2 stands for weight 2; tc. */
3936#define UCM_REG_CP_WEIGHT 0xe00c4
3937/* [RW 1] Input csem Interface enable. If 0 - the valid input is
3938 disregarded; acknowledge output is deasserted; all other signals are
3939 treated as usual; if 1 - normal activity. */
3940#define UCM_REG_CSEM_IFEN 0xe0028
3941/* [RC 1] Set when the message length mismatch (relative to last indication)
3942 at the csem interface is detected. */
3943#define UCM_REG_CSEM_LENGTH_MIS 0xe0160
3944/* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
3945 weight 8 (the most prioritised); 1 stands for weight 1(least
3946 prioritised); 2 stands for weight 2; tc. */
3947#define UCM_REG_CSEM_WEIGHT 0xe00b8
3948/* [RW 1] Input dorq Interface enable. If 0 - the valid input is
3949 disregarded; acknowledge output is deasserted; all other signals are
3950 treated as usual; if 1 - normal activity. */
3951#define UCM_REG_DORQ_IFEN 0xe0030
3952/* [RC 1] Set when the message length mismatch (relative to last indication)
3953 at the dorq interface is detected. */
3954#define UCM_REG_DORQ_LENGTH_MIS 0xe0168
3955/* [RW 8] The Event ID in case ErrorFlg input message bit is set. */
3956#define UCM_REG_ERR_EVNT_ID 0xe00a4
3957/* [RW 28] The CM erroneous header for QM and Timers formatting. */
3958#define UCM_REG_ERR_UCM_HDR 0xe00a0
3959/* [RW 8] The Event ID for Timers expiration. */
3960#define UCM_REG_EXPR_EVNT_ID 0xe00a8
3961/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
3962 writes the initial credit value; read returns the current value of the
3963 credit counter. Must be initialized to 64 at start-up. */
3964#define UCM_REG_FIC0_INIT_CRD 0xe020c
3965/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
3966 writes the initial credit value; read returns the current value of the
3967 credit counter. Must be initialized to 64 at start-up. */
3968#define UCM_REG_FIC1_INIT_CRD 0xe0210
3969/* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
3970 - strict priority defined by ~ucm_registers_gr_ag_pr.gr_ag_pr;
3971 ~ucm_registers_gr_ld0_pr.gr_ld0_pr and
3972 ~ucm_registers_gr_ld1_pr.gr_ld1_pr. */
3973#define UCM_REG_GR_ARB_TYPE 0xe0144
3974/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
3975 highest priority is 3. It is supposed that the Store channel group is
3976 compliment to the others. */
3977#define UCM_REG_GR_LD0_PR 0xe014c
3978/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
3979 highest priority is 3. It is supposed that the Store channel group is
3980 compliment to the others. */
3981#define UCM_REG_GR_LD1_PR 0xe0150
3982/* [RW 2] The queue index for invalidate counter flag decision. */
3983#define UCM_REG_INV_CFLG_Q 0xe00e4
3984/* [RW 5] The number of double REG-pairs; loaded from the STORM context and
3985 sent to STORM; for a specific connection type. the double REG-pairs are
3986 used in order to align to STORM context row size of 128 bits. The offset
3987 of these data in the STORM context is always 0. Index _i stands for the
3988 connection type (one of 16). */
3989#define UCM_REG_N_SM_CTX_LD_0 0xe0054
3990#define UCM_REG_N_SM_CTX_LD_1 0xe0058
3991#define UCM_REG_N_SM_CTX_LD_10 0xe007c
3992#define UCM_REG_N_SM_CTX_LD_11 0xe0080
3993#define UCM_REG_N_SM_CTX_LD_12 0xe0084
3994#define UCM_REG_N_SM_CTX_LD_13 0xe0088
3995#define UCM_REG_N_SM_CTX_LD_14 0xe008c
3996#define UCM_REG_N_SM_CTX_LD_15 0xe0090
3997#define UCM_REG_N_SM_CTX_LD_2 0xe005c
3998#define UCM_REG_N_SM_CTX_LD_3 0xe0060
3999#define UCM_REG_N_SM_CTX_LD_4 0xe0064
c18487ee 4000#define UCM_REG_N_SM_CTX_LD_5 0xe0068
a2fbb9ea
ET		 4001#define UCM_REG_PHYS_QNUM0_0 0xe0110
4002#define UCM_REG_PHYS_QNUM0_1 0xe0114
a2fbb9ea
ET		 4003#define UCM_REG_PHYS_QNUM1_0 0xe0118
4004#define UCM_REG_PHYS_QNUM1_1 0xe011c
c18487ee
YR		 4005#define UCM_REG_PHYS_QNUM2_0 0xe0120
4006#define UCM_REG_PHYS_QNUM2_1 0xe0124
4007#define UCM_REG_PHYS_QNUM3_0 0xe0128
4008#define UCM_REG_PHYS_QNUM3_1 0xe012c
a2fbb9ea
ET		 4009/* [RW 8] The Event ID for Timers formatting in case of stop done. */
4010#define UCM_REG_STOP_EVNT_ID 0xe00ac
4011/* [RC 1] Set when the message length mismatch (relative to last indication)
4012 at the STORM interface is detected. */
4013#define UCM_REG_STORM_LENGTH_MIS 0xe0154
4014/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
4015 disregarded; acknowledge output is deasserted; all other signals are
4016 treated as usual; if 1 - normal activity. */
4017#define UCM_REG_STORM_UCM_IFEN 0xe0010
4018/* [RW 4] Timers output initial credit. Max credit available - 15.Write
4019 writes the initial credit value; read returns the current value of the
4020 credit counter. Must be initialized to 4 at start-up. */
4021#define UCM_REG_TM_INIT_CRD 0xe021c
4022/* [RW 28] The CM header for Timers expiration command. */
4023#define UCM_REG_TM_UCM_HDR 0xe009c
4024/* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
4025 disregarded; acknowledge output is deasserted; all other signals are
4026 treated as usual; if 1 - normal activity. */
4027#define UCM_REG_TM_UCM_IFEN 0xe001c
4028/* [RW 1] Input tsem Interface enable. If 0 - the valid input is
4029 disregarded; acknowledge output is deasserted; all other signals are
4030 treated as usual; if 1 - normal activity. */
4031#define UCM_REG_TSEM_IFEN 0xe0024
4032/* [RC 1] Set when the message length mismatch (relative to last indication)
4033 at the tsem interface is detected. */
4034#define UCM_REG_TSEM_LENGTH_MIS 0xe015c
4035/* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
4036 weight 8 (the most prioritised); 1 stands for weight 1(least
4037 prioritised); 2 stands for weight 2; tc. */
4038#define UCM_REG_TSEM_WEIGHT 0xe00b4
4039/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
4040 acknowledge output is deasserted; all other signals are treated as usual;
4041 if 1 - normal activity. */
4042#define UCM_REG_UCM_CFC_IFEN 0xe0044
4043/* [RW 11] Interrupt mask register #0 read/write */
4044#define UCM_REG_UCM_INT_MASK 0xe01d4
4045/* [R 11] Interrupt register #0 read */
4046#define UCM_REG_UCM_INT_STS 0xe01c8
c18487ee
YR		 4047/* [R 27] Parity register #0 read */
4048#define UCM_REG_UCM_PRTY_STS 0xe01d8
a2fbb9ea
ET		 4049/* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS
4050 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
4051 Is used to determine the number of the AG context REG-pairs written back;
4052 when the Reg1WbFlg isn't set. */
4053#define UCM_REG_UCM_REG0_SZ 0xe00dc
4054/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
4055 disregarded; valid is deasserted; all other signals are treated as usual;
4056 if 1 - normal activity. */
4057#define UCM_REG_UCM_STORM0_IFEN 0xe0004
4058/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
4059 disregarded; valid is deasserted; all other signals are treated as usual;
4060 if 1 - normal activity. */
4061#define UCM_REG_UCM_STORM1_IFEN 0xe0008
4062/* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
4063 disregarded; acknowledge output is deasserted; all other signals are
4064 treated as usual; if 1 - normal activity. */
4065#define UCM_REG_UCM_TM_IFEN 0xe0020
4066/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
4067 disregarded; valid is deasserted; all other signals are treated as usual;
4068 if 1 - normal activity. */
4069#define UCM_REG_UCM_UQM_IFEN 0xe000c
4070/* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
4071#define UCM_REG_UCM_UQM_USE_Q 0xe00d8
4072/* [RW 6] QM output initial credit. Max credit available - 32.Write writes
4073 the initial credit value; read returns the current value of the credit
4074 counter. Must be initialized to 32 at start-up. */
4075#define UCM_REG_UQM_INIT_CRD 0xe0220
4076/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
4077 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4078 prioritised); 2 stands for weight 2; tc. */
4079#define UCM_REG_UQM_P_WEIGHT 0xe00cc
4080/* [RW 28] The CM header value for QM request (primary). */
4081#define UCM_REG_UQM_UCM_HDR_P 0xe0094
4082/* [RW 28] The CM header value for QM request (secondary). */
4083#define UCM_REG_UQM_UCM_HDR_S 0xe0098
4084/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
4085 acknowledge output is deasserted; all other signals are treated as usual;
4086 if 1 - normal activity. */
4087#define UCM_REG_UQM_UCM_IFEN 0xe0014
4088/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
4089 acknowledge output is deasserted; all other signals are treated as usual;
4090 if 1 - normal activity. */
4091#define UCM_REG_USDM_IFEN 0xe0018
4092/* [RC 1] Set when the message length mismatch (relative to last indication)
4093 at the SDM interface is detected. */
4094#define UCM_REG_USDM_LENGTH_MIS 0xe0158
4095/* [RW 1] Input xsem Interface enable. If 0 - the valid input is
4096 disregarded; acknowledge output is deasserted; all other signals are
4097 treated as usual; if 1 - normal activity. */
4098#define UCM_REG_XSEM_IFEN 0xe002c
4099/* [RC 1] Set when the message length mismatch (relative to last indication)
4100 at the xsem interface isdetected. */
4101#define UCM_REG_XSEM_LENGTH_MIS 0xe0164
4102/* [RW 20] Indirect access to the descriptor table of the XX protection
4103 mechanism. The fields are:[5:0] - message length; 14:6] - message
4104 pointer; 19:15] - next pointer. */
4105#define UCM_REG_XX_DESCR_TABLE 0xe0280
c18487ee 4106#define UCM_REG_XX_DESCR_TABLE_SIZE 32
a2fbb9ea
ET		 4107/* [R 6] Use to read the XX protection Free counter. */
4108#define UCM_REG_XX_FREE 0xe016c
4109/* [RW 6] Initial value for the credit counter; responsible for fulfilling
4110 of the Input Stage XX protection buffer by the XX protection pending
4111 messages. Write writes the initial credit value; read returns the current
4112 value of the credit counter. Must be initialized to 12 at start-up. */
4113#define UCM_REG_XX_INIT_CRD 0xe0224
4114/* [RW 6] The maximum number of pending messages; which may be stored in XX
4115 protection. ~ucm_registers_xx_free.xx_free read on read. */
4116#define UCM_REG_XX_MSG_NUM 0xe0228
4117/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
4118#define UCM_REG_XX_OVFL_EVNT_ID 0xe004c
4119/* [RW 16] Indirect access to the XX table of the XX protection mechanism.
4120 The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] -
4121 header pointer. */
4122#define UCM_REG_XX_TABLE 0xe0300
4123/* [RW 8] The event id for aggregated interrupt 0 */
4124#define USDM_REG_AGG_INT_EVENT_0 0xc4038
4125#define USDM_REG_AGG_INT_EVENT_1 0xc403c
4126#define USDM_REG_AGG_INT_EVENT_10 0xc4060
4127#define USDM_REG_AGG_INT_EVENT_11 0xc4064
4128#define USDM_REG_AGG_INT_EVENT_12 0xc4068
4129#define USDM_REG_AGG_INT_EVENT_13 0xc406c
4130#define USDM_REG_AGG_INT_EVENT_14 0xc4070
4131#define USDM_REG_AGG_INT_EVENT_15 0xc4074
4132#define USDM_REG_AGG_INT_EVENT_16 0xc4078
4133#define USDM_REG_AGG_INT_EVENT_17 0xc407c
4134#define USDM_REG_AGG_INT_EVENT_18 0xc4080
4135#define USDM_REG_AGG_INT_EVENT_19 0xc4084
c18487ee
YR		 4136#define USDM_REG_AGG_INT_EVENT_2 0xc4040
4137#define USDM_REG_AGG_INT_EVENT_20 0xc4088
4138#define USDM_REG_AGG_INT_EVENT_21 0xc408c
4139#define USDM_REG_AGG_INT_EVENT_22 0xc4090
4140#define USDM_REG_AGG_INT_EVENT_23 0xc4094
4141#define USDM_REG_AGG_INT_EVENT_24 0xc4098
4142#define USDM_REG_AGG_INT_EVENT_25 0xc409c
4143#define USDM_REG_AGG_INT_EVENT_26 0xc40a0
4144#define USDM_REG_AGG_INT_EVENT_27 0xc40a4
4145#define USDM_REG_AGG_INT_EVENT_28 0xc40a8
4146#define USDM_REG_AGG_INT_EVENT_29 0xc40ac
4147#define USDM_REG_AGG_INT_EVENT_3 0xc4044
4148#define USDM_REG_AGG_INT_EVENT_30 0xc40b0
4149#define USDM_REG_AGG_INT_EVENT_31 0xc40b4
4150#define USDM_REG_AGG_INT_EVENT_4 0xc4048
a2fbb9ea
ET		 4151/* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
4152 or auto-mask-mode (1) */
4153#define USDM_REG_AGG_INT_MODE_0 0xc41b8
4154#define USDM_REG_AGG_INT_MODE_1 0xc41bc
4155#define USDM_REG_AGG_INT_MODE_10 0xc41e0
4156#define USDM_REG_AGG_INT_MODE_11 0xc41e4
4157#define USDM_REG_AGG_INT_MODE_12 0xc41e8
4158#define USDM_REG_AGG_INT_MODE_13 0xc41ec
4159#define USDM_REG_AGG_INT_MODE_14 0xc41f0
4160#define USDM_REG_AGG_INT_MODE_15 0xc41f4
4161#define USDM_REG_AGG_INT_MODE_16 0xc41f8
4162#define USDM_REG_AGG_INT_MODE_17 0xc41fc
4163#define USDM_REG_AGG_INT_MODE_18 0xc4200
4164#define USDM_REG_AGG_INT_MODE_19 0xc4204
4165/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
4166#define USDM_REG_CFC_RSP_START_ADDR 0xc4008
4167/* [RW 16] The maximum value of the competion counter #0 */
4168#define USDM_REG_CMP_COUNTER_MAX0 0xc401c
4169/* [RW 16] The maximum value of the competion counter #1 */
4170#define USDM_REG_CMP_COUNTER_MAX1 0xc4020
4171/* [RW 16] The maximum value of the competion counter #2 */
4172#define USDM_REG_CMP_COUNTER_MAX2 0xc4024
4173/* [RW 16] The maximum value of the competion counter #3 */
4174#define USDM_REG_CMP_COUNTER_MAX3 0xc4028
4175/* [RW 13] The start address in the internal RAM for the completion
4176 counters. */
4177#define USDM_REG_CMP_COUNTER_START_ADDR 0xc400c
4178#define USDM_REG_ENABLE_IN1 0xc4238
4179#define USDM_REG_ENABLE_IN2 0xc423c
4180#define USDM_REG_ENABLE_OUT1 0xc4240
4181#define USDM_REG_ENABLE_OUT2 0xc4244
4182/* [RW 4] The initial number of messages that can be sent to the pxp control
4183 interface without receiving any ACK. */
4184#define USDM_REG_INIT_CREDIT_PXP_CTRL 0xc44c0
4185/* [ST 32] The number of ACK after placement messages received */
4186#define USDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc4280
4187/* [ST 32] The number of packet end messages received from the parser */
4188#define USDM_REG_NUM_OF_PKT_END_MSG 0xc4278
4189/* [ST 32] The number of requests received from the pxp async if */
4190#define USDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc427c
4191/* [ST 32] The number of commands received in queue 0 */
4192#define USDM_REG_NUM_OF_Q0_CMD 0xc4248
4193/* [ST 32] The number of commands received in queue 10 */
4194#define USDM_REG_NUM_OF_Q10_CMD 0xc4270
4195/* [ST 32] The number of commands received in queue 11 */
4196#define USDM_REG_NUM_OF_Q11_CMD 0xc4274
4197/* [ST 32] The number of commands received in queue 1 */
4198#define USDM_REG_NUM_OF_Q1_CMD 0xc424c
4199/* [ST 32] The number of commands received in queue 2 */
4200#define USDM_REG_NUM_OF_Q2_CMD 0xc4250
4201/* [ST 32] The number of commands received in queue 3 */
4202#define USDM_REG_NUM_OF_Q3_CMD 0xc4254
4203/* [ST 32] The number of commands received in queue 4 */
4204#define USDM_REG_NUM_OF_Q4_CMD 0xc4258
4205/* [ST 32] The number of commands received in queue 5 */
4206#define USDM_REG_NUM_OF_Q5_CMD 0xc425c
4207/* [ST 32] The number of commands received in queue 6 */
4208#define USDM_REG_NUM_OF_Q6_CMD 0xc4260
4209/* [ST 32] The number of commands received in queue 7 */
4210#define USDM_REG_NUM_OF_Q7_CMD 0xc4264
4211/* [ST 32] The number of commands received in queue 8 */
4212#define USDM_REG_NUM_OF_Q8_CMD 0xc4268
4213/* [ST 32] The number of commands received in queue 9 */
4214#define USDM_REG_NUM_OF_Q9_CMD 0xc426c
4215/* [RW 13] The start address in the internal RAM for the packet end message */
4216#define USDM_REG_PCK_END_MSG_START_ADDR 0xc4014
4217/* [RW 13] The start address in the internal RAM for queue counters */
4218#define USDM_REG_Q_COUNTER_START_ADDR 0xc4010
4219/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
4220#define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc4550
4221/* [R 1] parser fifo empty in sdm_sync block */
4222#define USDM_REG_SYNC_PARSER_EMPTY 0xc4558
4223/* [R 1] parser serial fifo empty in sdm_sync block */
4224#define USDM_REG_SYNC_SYNC_EMPTY 0xc4560
4225/* [RW 32] Tick for timer counter. Applicable only when
4226 ~usdm_registers_timer_tick_enable.timer_tick_enable =1 */
4227#define USDM_REG_TIMER_TICK 0xc4000
4228/* [RW 32] Interrupt mask register #0 read/write */
4229#define USDM_REG_USDM_INT_MASK_0 0xc42a0
4230#define USDM_REG_USDM_INT_MASK_1 0xc42b0
c18487ee
YR		 4231/* [R 32] Interrupt register #0 read */
4232#define USDM_REG_USDM_INT_STS_0 0xc4294
4233#define USDM_REG_USDM_INT_STS_1 0xc42a4
a2fbb9ea
ET		 4234/* [RW 11] Parity mask register #0 read/write */
4235#define USDM_REG_USDM_PRTY_MASK 0xc42c0
f1410647
ET		 4236/* [R 11] Parity register #0 read */
4237#define USDM_REG_USDM_PRTY_STS 0xc42b4
a2fbb9ea
ET		 4238/* [RW 5] The number of time_slots in the arbitration cycle */
4239#define USEM_REG_ARB_CYCLE_SIZE 0x300034
4240/* [RW 3] The source that is associated with arbitration element 0. Source
4241 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4242 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
4243#define USEM_REG_ARB_ELEMENT0 0x300020
4244/* [RW 3] The source that is associated with arbitration element 1. Source
4245 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4246 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4247 Could not be equal to register ~usem_registers_arb_element0.arb_element0 */
4248#define USEM_REG_ARB_ELEMENT1 0x300024
4249/* [RW 3] The source that is associated with arbitration element 2. Source
4250 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4251 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4252 Could not be equal to register ~usem_registers_arb_element0.arb_element0
4253 and ~usem_registers_arb_element1.arb_element1 */
4254#define USEM_REG_ARB_ELEMENT2 0x300028
4255/* [RW 3] The source that is associated with arbitration element 3. Source
4256 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4257 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
4258 not be equal to register ~usem_registers_arb_element0.arb_element0 and
4259 ~usem_registers_arb_element1.arb_element1 and
4260 ~usem_registers_arb_element2.arb_element2 */
4261#define USEM_REG_ARB_ELEMENT3 0x30002c
4262/* [RW 3] The source that is associated with arbitration element 4. Source
4263 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4264 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4265 Could not be equal to register ~usem_registers_arb_element0.arb_element0
4266 and ~usem_registers_arb_element1.arb_element1 and
4267 ~usem_registers_arb_element2.arb_element2 and
4268 ~usem_registers_arb_element3.arb_element3 */
4269#define USEM_REG_ARB_ELEMENT4 0x300030
4270#define USEM_REG_ENABLE_IN 0x3000a4
4271#define USEM_REG_ENABLE_OUT 0x3000a8
4272/* [RW 32] This address space contains all registers and memories that are
4273 placed in SEM_FAST block. The SEM_FAST registers are described in
c18487ee
YR		 4274 appendix B. In order to access the sem_fast registers the base address
4275 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
a2fbb9ea
ET		 4276#define USEM_REG_FAST_MEMORY 0x320000
4277/* [RW 1] Disables input messages from FIC0 May be updated during run_time
4278 by the microcode */
4279#define USEM_REG_FIC0_DISABLE 0x300224
4280/* [RW 1] Disables input messages from FIC1 May be updated during run_time
4281 by the microcode */
4282#define USEM_REG_FIC1_DISABLE 0x300234
4283/* [RW 15] Interrupt table Read and write access to it is not possible in
4284 the middle of the work */
4285#define USEM_REG_INT_TABLE 0x300400
c18487ee 4286#define USEM_REG_INT_TABLE_SIZE 256
a2fbb9ea
ET		 4287/* [ST 24] Statistics register. The number of messages that entered through
4288 FIC0 */
4289#define USEM_REG_MSG_NUM_FIC0 0x300000
4290/* [ST 24] Statistics register. The number of messages that entered through
4291 FIC1 */
4292#define USEM_REG_MSG_NUM_FIC1 0x300004
4293/* [ST 24] Statistics register. The number of messages that were sent to
4294 FOC0 */
4295#define USEM_REG_MSG_NUM_FOC0 0x300008
4296/* [ST 24] Statistics register. The number of messages that were sent to
4297 FOC1 */
4298#define USEM_REG_MSG_NUM_FOC1 0x30000c
4299/* [ST 24] Statistics register. The number of messages that were sent to
4300 FOC2 */
4301#define USEM_REG_MSG_NUM_FOC2 0x300010
4302/* [ST 24] Statistics register. The number of messages that were sent to
4303 FOC3 */
4304#define USEM_REG_MSG_NUM_FOC3 0x300014
4305/* [RW 1] Disables input messages from the passive buffer May be updated
4306 during run_time by the microcode */
4307#define USEM_REG_PAS_DISABLE 0x30024c
4308/* [WB 128] Debug only. Passive buffer memory */
4309#define USEM_REG_PASSIVE_BUFFER 0x302000
4310/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
4311#define USEM_REG_PRAM 0x340000
4312/* [R 16] Valid sleeping threads indication have bit per thread */
4313#define USEM_REG_SLEEP_THREADS_VALID 0x30026c
4314/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
4315#define USEM_REG_SLOW_EXT_STORE_EMPTY 0x3002a0
4316/* [RW 16] List of free threads . There is a bit per thread. */
4317#define USEM_REG_THREADS_LIST 0x3002e4
4318/* [RW 3] The arbitration scheme of time_slot 0 */
4319#define USEM_REG_TS_0_AS 0x300038
4320/* [RW 3] The arbitration scheme of time_slot 10 */
4321#define USEM_REG_TS_10_AS 0x300060
4322/* [RW 3] The arbitration scheme of time_slot 11 */
4323#define USEM_REG_TS_11_AS 0x300064
4324/* [RW 3] The arbitration scheme of time_slot 12 */
4325#define USEM_REG_TS_12_AS 0x300068
4326/* [RW 3] The arbitration scheme of time_slot 13 */
4327#define USEM_REG_TS_13_AS 0x30006c
4328/* [RW 3] The arbitration scheme of time_slot 14 */
4329#define USEM_REG_TS_14_AS 0x300070
4330/* [RW 3] The arbitration scheme of time_slot 15 */
4331#define USEM_REG_TS_15_AS 0x300074
4332/* [RW 3] The arbitration scheme of time_slot 16 */
4333#define USEM_REG_TS_16_AS 0x300078
4334/* [RW 3] The arbitration scheme of time_slot 17 */
4335#define USEM_REG_TS_17_AS 0x30007c
4336/* [RW 3] The arbitration scheme of time_slot 18 */
4337#define USEM_REG_TS_18_AS 0x300080
4338/* [RW 3] The arbitration scheme of time_slot 1 */
4339#define USEM_REG_TS_1_AS 0x30003c
4340/* [RW 3] The arbitration scheme of time_slot 2 */
4341#define USEM_REG_TS_2_AS 0x300040
4342/* [RW 3] The arbitration scheme of time_slot 3 */
4343#define USEM_REG_TS_3_AS 0x300044
4344/* [RW 3] The arbitration scheme of time_slot 4 */
4345#define USEM_REG_TS_4_AS 0x300048
4346/* [RW 3] The arbitration scheme of time_slot 5 */
4347#define USEM_REG_TS_5_AS 0x30004c
4348/* [RW 3] The arbitration scheme of time_slot 6 */
4349#define USEM_REG_TS_6_AS 0x300050
4350/* [RW 3] The arbitration scheme of time_slot 7 */
4351#define USEM_REG_TS_7_AS 0x300054
4352/* [RW 3] The arbitration scheme of time_slot 8 */
4353#define USEM_REG_TS_8_AS 0x300058
4354/* [RW 3] The arbitration scheme of time_slot 9 */
4355#define USEM_REG_TS_9_AS 0x30005c
4356/* [RW 32] Interrupt mask register #0 read/write */
4357#define USEM_REG_USEM_INT_MASK_0 0x300110
4358#define USEM_REG_USEM_INT_MASK_1 0x300120
c18487ee
YR		 4359/* [R 32] Interrupt register #0 read */
4360#define USEM_REG_USEM_INT_STS_0 0x300104
4361#define USEM_REG_USEM_INT_STS_1 0x300114
a2fbb9ea
ET		 4362/* [RW 32] Parity mask register #0 read/write */
4363#define USEM_REG_USEM_PRTY_MASK_0 0x300130
4364#define USEM_REG_USEM_PRTY_MASK_1 0x300140
f1410647
ET		 4365/* [R 32] Parity register #0 read */
4366#define USEM_REG_USEM_PRTY_STS_0 0x300124
4367#define USEM_REG_USEM_PRTY_STS_1 0x300134
a2fbb9ea
ET		 4368/* [RW 2] The queue index for registration on Aux1 counter flag. */
4369#define XCM_REG_AUX1_Q 0x20134
4370/* [RW 2] Per each decision rule the queue index to register to. */
4371#define XCM_REG_AUX_CNT_FLG_Q_19 0x201b0
4372/* [R 5] Used to read the XX protection CAM occupancy counter. */
4373#define XCM_REG_CAM_OCCUP 0x20244
4374/* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4375 disregarded; valid output is deasserted; all other signals are treated as
4376 usual; if 1 - normal activity. */
4377#define XCM_REG_CDU_AG_RD_IFEN 0x20044
4378/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4379 are disregarded; all other signals are treated as usual; if 1 - normal
4380 activity. */
4381#define XCM_REG_CDU_AG_WR_IFEN 0x20040
4382/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4383 disregarded; valid output is deasserted; all other signals are treated as
4384 usual; if 1 - normal activity. */
4385#define XCM_REG_CDU_SM_RD_IFEN 0x2004c
4386/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4387 input is disregarded; all other signals are treated as usual; if 1 -
4388 normal activity. */
4389#define XCM_REG_CDU_SM_WR_IFEN 0x20048
4390/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4391 the initial credit value; read returns the current value of the credit
4392 counter. Must be initialized to 1 at start-up. */
4393#define XCM_REG_CFC_INIT_CRD 0x20404
4394/* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4395 weight 8 (the most prioritised); 1 stands for weight 1(least
4396 prioritised); 2 stands for weight 2; tc. */
4397#define XCM_REG_CP_WEIGHT 0x200dc
4398/* [RW 1] Input csem Interface enable. If 0 - the valid input is
4399 disregarded; acknowledge output is deasserted; all other signals are
4400 treated as usual; if 1 - normal activity. */
4401#define XCM_REG_CSEM_IFEN 0x20028
4402/* [RC 1] Set at message length mismatch (relative to last indication) at
4403 the csem interface. */
4404#define XCM_REG_CSEM_LENGTH_MIS 0x20228
4405/* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4406 weight 8 (the most prioritised); 1 stands for weight 1(least
4407 prioritised); 2 stands for weight 2; tc. */
4408#define XCM_REG_CSEM_WEIGHT 0x200c4
4409/* [RW 1] Input dorq Interface enable. If 0 - the valid input is
4410 disregarded; acknowledge output is deasserted; all other signals are
4411 treated as usual; if 1 - normal activity. */
4412#define XCM_REG_DORQ_IFEN 0x20030
4413/* [RC 1] Set at message length mismatch (relative to last indication) at
4414 the dorq interface. */
4415#define XCM_REG_DORQ_LENGTH_MIS 0x20230
4416/* [RW 8] The Event ID in case the ErrorFlg input message bit is set. */
4417#define XCM_REG_ERR_EVNT_ID 0x200b0
4418/* [RW 28] The CM erroneous header for QM and Timers formatting. */
4419#define XCM_REG_ERR_XCM_HDR 0x200ac
4420/* [RW 8] The Event ID for Timers expiration. */
4421#define XCM_REG_EXPR_EVNT_ID 0x200b4
4422/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
4423 writes the initial credit value; read returns the current value of the
4424 credit counter. Must be initialized to 64 at start-up. */
4425#define XCM_REG_FIC0_INIT_CRD 0x2040c
4426/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
4427 writes the initial credit value; read returns the current value of the
4428 credit counter. Must be initialized to 64 at start-up. */
4429#define XCM_REG_FIC1_INIT_CRD 0x20410
a2fbb9ea
ET		 4430#define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x20118
4431#define XCM_REG_GLB_DEL_ACK_MAX_CNT_1 0x2011c
a2fbb9ea
ET		 4432#define XCM_REG_GLB_DEL_ACK_TMR_VAL_0 0x20108
4433#define XCM_REG_GLB_DEL_ACK_TMR_VAL_1 0x2010c
4434/* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1
4435 - strict priority defined by ~xcm_registers_gr_ag_pr.gr_ag_pr;
4436 ~xcm_registers_gr_ld0_pr.gr_ld0_pr and
4437 ~xcm_registers_gr_ld1_pr.gr_ld1_pr. */
4438#define XCM_REG_GR_ARB_TYPE 0x2020c
4439/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
4440 highest priority is 3. It is supposed that the Channel group is the
4441 compliment of the other 3 groups. */
4442#define XCM_REG_GR_LD0_PR 0x20214
4443/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
4444 highest priority is 3. It is supposed that the Channel group is the
4445 compliment of the other 3 groups. */
4446#define XCM_REG_GR_LD1_PR 0x20218
4447/* [RW 1] Input nig0 Interface enable. If 0 - the valid input is
4448 disregarded; acknowledge output is deasserted; all other signals are
4449 treated as usual; if 1 - normal activity. */
4450#define XCM_REG_NIG0_IFEN 0x20038
4451/* [RC 1] Set at message length mismatch (relative to last indication) at
4452 the nig0 interface. */
4453#define XCM_REG_NIG0_LENGTH_MIS 0x20238
4454/* [RW 1] Input nig1 Interface enable. If 0 - the valid input is
4455 disregarded; acknowledge output is deasserted; all other signals are
4456 treated as usual; if 1 - normal activity. */
4457#define XCM_REG_NIG1_IFEN 0x2003c
4458/* [RC 1] Set at message length mismatch (relative to last indication) at
4459 the nig1 interface. */
4460#define XCM_REG_NIG1_LENGTH_MIS 0x2023c
4461/* [RW 3] The weight of the input nig1 in the WRR mechanism. 0 stands for
4462 weight 8 (the most prioritised); 1 stands for weight 1(least
4463 prioritised); 2 stands for weight 2; tc. */
4464#define XCM_REG_NIG1_WEIGHT 0x200d8
4465/* [RW 5] The number of double REG-pairs; loaded from the STORM context and
4466 sent to STORM; for a specific connection type. The double REG-pairs are
4467 used in order to align to STORM context row size of 128 bits. The offset
4468 of these data in the STORM context is always 0. Index _i stands for the
4469 connection type (one of 16). */
4470#define XCM_REG_N_SM_CTX_LD_0 0x20060
4471#define XCM_REG_N_SM_CTX_LD_1 0x20064
4472#define XCM_REG_N_SM_CTX_LD_10 0x20088
4473#define XCM_REG_N_SM_CTX_LD_11 0x2008c
4474#define XCM_REG_N_SM_CTX_LD_12 0x20090
4475#define XCM_REG_N_SM_CTX_LD_13 0x20094
4476#define XCM_REG_N_SM_CTX_LD_14 0x20098
4477#define XCM_REG_N_SM_CTX_LD_15 0x2009c
4478#define XCM_REG_N_SM_CTX_LD_2 0x20068
4479#define XCM_REG_N_SM_CTX_LD_3 0x2006c
4480#define XCM_REG_N_SM_CTX_LD_4 0x20070
c18487ee 4481#define XCM_REG_N_SM_CTX_LD_5 0x20074
a2fbb9ea
ET		 4482/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
4483 acknowledge output is deasserted; all other signals are treated as usual;
4484 if 1 - normal activity. */
4485#define XCM_REG_PBF_IFEN 0x20034
4486/* [RC 1] Set at message length mismatch (relative to last indication) at
4487 the pbf interface. */
4488#define XCM_REG_PBF_LENGTH_MIS 0x20234
4489/* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
4490 weight 8 (the most prioritised); 1 stands for weight 1(least
4491 prioritised); 2 stands for weight 2; tc. */
4492#define XCM_REG_PBF_WEIGHT 0x200d0
c18487ee
YR		 4493#define XCM_REG_PHYS_QNUM3_0 0x20100
4494#define XCM_REG_PHYS_QNUM3_1 0x20104
a2fbb9ea
ET		 4495/* [RW 8] The Event ID for Timers formatting in case of stop done. */
4496#define XCM_REG_STOP_EVNT_ID 0x200b8
4497/* [RC 1] Set at message length mismatch (relative to last indication) at
4498 the STORM interface. */
4499#define XCM_REG_STORM_LENGTH_MIS 0x2021c
4500/* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
4501 weight 8 (the most prioritised); 1 stands for weight 1(least
4502 prioritised); 2 stands for weight 2; tc. */
4503#define XCM_REG_STORM_WEIGHT 0x200bc
4504/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
4505 disregarded; acknowledge output is deasserted; all other signals are
4506 treated as usual; if 1 - normal activity. */
4507#define XCM_REG_STORM_XCM_IFEN 0x20010
4508/* [RW 4] Timers output initial credit. Max credit available - 15.Write
4509 writes the initial credit value; read returns the current value of the
4510 credit counter. Must be initialized to 4 at start-up. */
4511#define XCM_REG_TM_INIT_CRD 0x2041c
4512/* [RW 28] The CM header for Timers expiration command. */
4513#define XCM_REG_TM_XCM_HDR 0x200a8
4514/* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
4515 disregarded; acknowledge output is deasserted; all other signals are
4516 treated as usual; if 1 - normal activity. */
4517#define XCM_REG_TM_XCM_IFEN 0x2001c
4518/* [RW 1] Input tsem Interface enable. If 0 - the valid input is
4519 disregarded; acknowledge output is deasserted; all other signals are
4520 treated as usual; if 1 - normal activity. */
4521#define XCM_REG_TSEM_IFEN 0x20024
4522/* [RC 1] Set at message length mismatch (relative to last indication) at
4523 the tsem interface. */
4524#define XCM_REG_TSEM_LENGTH_MIS 0x20224
4525/* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
4526 weight 8 (the most prioritised); 1 stands for weight 1(least
4527 prioritised); 2 stands for weight 2; tc. */
4528#define XCM_REG_TSEM_WEIGHT 0x200c0
4529/* [RW 2] The queue index for registration on UNA greater NXT decision rule. */
4530#define XCM_REG_UNA_GT_NXT_Q 0x20120
4531/* [RW 1] Input usem Interface enable. If 0 - the valid input is
4532 disregarded; acknowledge output is deasserted; all other signals are
4533 treated as usual; if 1 - normal activity. */
4534#define XCM_REG_USEM_IFEN 0x2002c
4535/* [RC 1] Message length mismatch (relative to last indication) at the usem
4536 interface. */
4537#define XCM_REG_USEM_LENGTH_MIS 0x2022c
4538/* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
4539 weight 8 (the most prioritised); 1 stands for weight 1(least
4540 prioritised); 2 stands for weight 2; tc. */
4541#define XCM_REG_USEM_WEIGHT 0x200c8
a2fbb9ea 4542#define XCM_REG_WU_DA_CNT_CMD00 0x201d4
a2fbb9ea 4543#define XCM_REG_WU_DA_CNT_CMD01 0x201d8
a2fbb9ea 4544#define XCM_REG_WU_DA_CNT_CMD10 0x201dc
a2fbb9ea 4545#define XCM_REG_WU_DA_CNT_CMD11 0x201e0
a2fbb9ea 4546#define XCM_REG_WU_DA_CNT_UPD_VAL00 0x201e4
a2fbb9ea 4547#define XCM_REG_WU_DA_CNT_UPD_VAL01 0x201e8
a2fbb9ea 4548#define XCM_REG_WU_DA_CNT_UPD_VAL10 0x201ec
a2fbb9ea 4549#define XCM_REG_WU_DA_CNT_UPD_VAL11 0x201f0
a2fbb9ea 4550#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4
a2fbb9ea 4551#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01 0x201c8
a2fbb9ea 4552#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10 0x201cc
a2fbb9ea
ET		 4553#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11 0x201d0
4554/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
4555 acknowledge output is deasserted; all other signals are treated as usual;
4556 if 1 - normal activity. */
4557#define XCM_REG_XCM_CFC_IFEN 0x20050
4558/* [RW 14] Interrupt mask register #0 read/write */
4559#define XCM_REG_XCM_INT_MASK 0x202b4
4560/* [R 14] Interrupt register #0 read */
4561#define XCM_REG_XCM_INT_STS 0x202a8
c18487ee
YR		 4562/* [R 30] Parity register #0 read */
4563#define XCM_REG_XCM_PRTY_STS 0x202b8
a2fbb9ea
ET		 4564/* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS
4565 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
4566 Is used to determine the number of the AG context REG-pairs written back;
4567 when the Reg1WbFlg isn't set. */
4568#define XCM_REG_XCM_REG0_SZ 0x200f4
4569/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
4570 disregarded; valid is deasserted; all other signals are treated as usual;
4571 if 1 - normal activity. */
4572#define XCM_REG_XCM_STORM0_IFEN 0x20004
4573/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
4574 disregarded; valid is deasserted; all other signals are treated as usual;
4575 if 1 - normal activity. */
4576#define XCM_REG_XCM_STORM1_IFEN 0x20008
4577/* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
4578 disregarded; acknowledge output is deasserted; all other signals are
4579 treated as usual; if 1 - normal activity. */
4580#define XCM_REG_XCM_TM_IFEN 0x20020
4581/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
4582 disregarded; valid is deasserted; all other signals are treated as usual;
4583 if 1 - normal activity. */
4584#define XCM_REG_XCM_XQM_IFEN 0x2000c
4585/* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
4586#define XCM_REG_XCM_XQM_USE_Q 0x200f0
4587/* [RW 4] The value by which CFC updates the activity counter at QM bypass. */
4588#define XCM_REG_XQM_BYP_ACT_UPD 0x200fc
4589/* [RW 6] QM output initial credit. Max credit available - 32.Write writes
4590 the initial credit value; read returns the current value of the credit
4591 counter. Must be initialized to 32 at start-up. */
4592#define XCM_REG_XQM_INIT_CRD 0x20420
4593/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
4594 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4595 prioritised); 2 stands for weight 2; tc. */
4596#define XCM_REG_XQM_P_WEIGHT 0x200e4
4597/* [RW 28] The CM header value for QM request (primary). */
4598#define XCM_REG_XQM_XCM_HDR_P 0x200a0
4599/* [RW 28] The CM header value for QM request (secondary). */
4600#define XCM_REG_XQM_XCM_HDR_S 0x200a4
4601/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
4602 acknowledge output is deasserted; all other signals are treated as usual;
4603 if 1 - normal activity. */
4604#define XCM_REG_XQM_XCM_IFEN 0x20014
4605/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
4606 acknowledge output is deasserted; all other signals are treated as usual;
4607 if 1 - normal activity. */
4608#define XCM_REG_XSDM_IFEN 0x20018
4609/* [RC 1] Set at message length mismatch (relative to last indication) at
4610 the SDM interface. */
4611#define XCM_REG_XSDM_LENGTH_MIS 0x20220
4612/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
4613 weight 8 (the most prioritised); 1 stands for weight 1(least
4614 prioritised); 2 stands for weight 2; tc. */
4615#define XCM_REG_XSDM_WEIGHT 0x200e0
4616/* [RW 17] Indirect access to the descriptor table of the XX protection
4617 mechanism. The fields are: [5:0] - message length; 11:6] - message
4618 pointer; 16:12] - next pointer. */
4619#define XCM_REG_XX_DESCR_TABLE 0x20480
c18487ee 4620#define XCM_REG_XX_DESCR_TABLE_SIZE 32
a2fbb9ea
ET		 4621/* [R 6] Used to read the XX protection Free counter. */
4622#define XCM_REG_XX_FREE 0x20240
4623/* [RW 6] Initial value for the credit counter; responsible for fulfilling
4624 of the Input Stage XX protection buffer by the XX protection pending
4625 messages. Max credit available - 3.Write writes the initial credit value;
4626 read returns the current value of the credit counter. Must be initialized
4627 to 2 at start-up. */
4628#define XCM_REG_XX_INIT_CRD 0x20424
4629/* [RW 6] The maximum number of pending messages; which may be stored in XX
4630 protection. ~xcm_registers_xx_free.xx_free read on read. */
4631#define XCM_REG_XX_MSG_NUM 0x20428
4632/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
4633#define XCM_REG_XX_OVFL_EVNT_ID 0x20058
c18487ee 4634/* [RW 16] Indirect access to the XX table of the XX protection mechanism.
a2fbb9ea
ET		 4635 The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] -
4636 header pointer. */
4637#define XCM_REG_XX_TABLE 0x20500
4638/* [RW 8] The event id for aggregated interrupt 0 */
4639#define XSDM_REG_AGG_INT_EVENT_0 0x166038
4640#define XSDM_REG_AGG_INT_EVENT_1 0x16603c
4641#define XSDM_REG_AGG_INT_EVENT_10 0x166060
4642#define XSDM_REG_AGG_INT_EVENT_11 0x166064
4643#define XSDM_REG_AGG_INT_EVENT_12 0x166068
4644#define XSDM_REG_AGG_INT_EVENT_13 0x16606c
4645#define XSDM_REG_AGG_INT_EVENT_14 0x166070
4646#define XSDM_REG_AGG_INT_EVENT_15 0x166074
4647#define XSDM_REG_AGG_INT_EVENT_16 0x166078
4648#define XSDM_REG_AGG_INT_EVENT_17 0x16607c
4649#define XSDM_REG_AGG_INT_EVENT_18 0x166080
4650#define XSDM_REG_AGG_INT_EVENT_19 0x166084
c18487ee
YR		 4651#define XSDM_REG_AGG_INT_EVENT_10 0x166060
4652#define XSDM_REG_AGG_INT_EVENT_11 0x166064
4653#define XSDM_REG_AGG_INT_EVENT_12 0x166068
a2fbb9ea
ET		 4654#define XSDM_REG_AGG_INT_EVENT_2 0x166040
4655#define XSDM_REG_AGG_INT_EVENT_20 0x166088
4656#define XSDM_REG_AGG_INT_EVENT_21 0x16608c
4657#define XSDM_REG_AGG_INT_EVENT_22 0x166090
4658#define XSDM_REG_AGG_INT_EVENT_23 0x166094
4659#define XSDM_REG_AGG_INT_EVENT_24 0x166098
4660#define XSDM_REG_AGG_INT_EVENT_25 0x16609c
4661#define XSDM_REG_AGG_INT_EVENT_26 0x1660a0
4662#define XSDM_REG_AGG_INT_EVENT_27 0x1660a4
4663#define XSDM_REG_AGG_INT_EVENT_28 0x1660a8
4664#define XSDM_REG_AGG_INT_EVENT_29 0x1660ac
c18487ee
YR		 4665#define XSDM_REG_AGG_INT_EVENT_3 0x166044
4666#define XSDM_REG_AGG_INT_EVENT_30 0x1660b0
4667#define XSDM_REG_AGG_INT_EVENT_31 0x1660b4
4668#define XSDM_REG_AGG_INT_EVENT_4 0x166048
4669#define XSDM_REG_AGG_INT_EVENT_5 0x16604c
4670#define XSDM_REG_AGG_INT_EVENT_6 0x166050
4671#define XSDM_REG_AGG_INT_EVENT_7 0x166054
4672#define XSDM_REG_AGG_INT_EVENT_8 0x166058
4673#define XSDM_REG_AGG_INT_EVENT_9 0x16605c
a2fbb9ea
ET		 4674/* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
4675 or auto-mask-mode (1) */
4676#define XSDM_REG_AGG_INT_MODE_0 0x1661b8
4677#define XSDM_REG_AGG_INT_MODE_1 0x1661bc
4678#define XSDM_REG_AGG_INT_MODE_10 0x1661e0
4679#define XSDM_REG_AGG_INT_MODE_11 0x1661e4
4680#define XSDM_REG_AGG_INT_MODE_12 0x1661e8
4681#define XSDM_REG_AGG_INT_MODE_13 0x1661ec
4682#define XSDM_REG_AGG_INT_MODE_14 0x1661f0
4683#define XSDM_REG_AGG_INT_MODE_15 0x1661f4
4684#define XSDM_REG_AGG_INT_MODE_16 0x1661f8
4685#define XSDM_REG_AGG_INT_MODE_17 0x1661fc
4686#define XSDM_REG_AGG_INT_MODE_18 0x166200
4687#define XSDM_REG_AGG_INT_MODE_19 0x166204
4688/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
4689#define XSDM_REG_CFC_RSP_START_ADDR 0x166008
4690/* [RW 16] The maximum value of the competion counter #0 */
4691#define XSDM_REG_CMP_COUNTER_MAX0 0x16601c
4692/* [RW 16] The maximum value of the competion counter #1 */
4693#define XSDM_REG_CMP_COUNTER_MAX1 0x166020
4694/* [RW 16] The maximum value of the competion counter #2 */
4695#define XSDM_REG_CMP_COUNTER_MAX2 0x166024
4696/* [RW 16] The maximum value of the competion counter #3 */
4697#define XSDM_REG_CMP_COUNTER_MAX3 0x166028
4698/* [RW 13] The start address in the internal RAM for the completion
4699 counters. */
4700#define XSDM_REG_CMP_COUNTER_START_ADDR 0x16600c
4701#define XSDM_REG_ENABLE_IN1 0x166238
4702#define XSDM_REG_ENABLE_IN2 0x16623c
4703#define XSDM_REG_ENABLE_OUT1 0x166240
4704#define XSDM_REG_ENABLE_OUT2 0x166244
4705/* [RW 4] The initial number of messages that can be sent to the pxp control
4706 interface without receiving any ACK. */
4707#define XSDM_REG_INIT_CREDIT_PXP_CTRL 0x1664bc
4708/* [ST 32] The number of ACK after placement messages received */
4709#define XSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x16627c
4710/* [ST 32] The number of packet end messages received from the parser */
4711#define XSDM_REG_NUM_OF_PKT_END_MSG 0x166274
4712/* [ST 32] The number of requests received from the pxp async if */
4713#define XSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x166278
4714/* [ST 32] The number of commands received in queue 0 */
4715#define XSDM_REG_NUM_OF_Q0_CMD 0x166248
4716/* [ST 32] The number of commands received in queue 10 */
4717#define XSDM_REG_NUM_OF_Q10_CMD 0x16626c
4718/* [ST 32] The number of commands received in queue 11 */
4719#define XSDM_REG_NUM_OF_Q11_CMD 0x166270
4720/* [ST 32] The number of commands received in queue 1 */
4721#define XSDM_REG_NUM_OF_Q1_CMD 0x16624c
4722/* [ST 32] The number of commands received in queue 3 */
4723#define XSDM_REG_NUM_OF_Q3_CMD 0x166250
4724/* [ST 32] The number of commands received in queue 4 */
4725#define XSDM_REG_NUM_OF_Q4_CMD 0x166254
4726/* [ST 32] The number of commands received in queue 5 */
4727#define XSDM_REG_NUM_OF_Q5_CMD 0x166258
4728/* [ST 32] The number of commands received in queue 6 */
4729#define XSDM_REG_NUM_OF_Q6_CMD 0x16625c
4730/* [ST 32] The number of commands received in queue 7 */
4731#define XSDM_REG_NUM_OF_Q7_CMD 0x166260
4732/* [ST 32] The number of commands received in queue 8 */
4733#define XSDM_REG_NUM_OF_Q8_CMD 0x166264
4734/* [ST 32] The number of commands received in queue 9 */
4735#define XSDM_REG_NUM_OF_Q9_CMD 0x166268
4736/* [RW 13] The start address in the internal RAM for queue counters */
4737#define XSDM_REG_Q_COUNTER_START_ADDR 0x166010
4738/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
4739#define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x166548
4740/* [R 1] parser fifo empty in sdm_sync block */
4741#define XSDM_REG_SYNC_PARSER_EMPTY 0x166550
4742/* [R 1] parser serial fifo empty in sdm_sync block */
4743#define XSDM_REG_SYNC_SYNC_EMPTY 0x166558
4744/* [RW 32] Tick for timer counter. Applicable only when
4745 ~xsdm_registers_timer_tick_enable.timer_tick_enable =1 */
4746#define XSDM_REG_TIMER_TICK 0x166000
4747/* [RW 32] Interrupt mask register #0 read/write */
4748#define XSDM_REG_XSDM_INT_MASK_0 0x16629c
4749#define XSDM_REG_XSDM_INT_MASK_1 0x1662ac
c18487ee
YR		 4750/* [R 32] Interrupt register #0 read */
4751#define XSDM_REG_XSDM_INT_STS_0 0x166290
4752#define XSDM_REG_XSDM_INT_STS_1 0x1662a0
a2fbb9ea
ET		 4753/* [RW 11] Parity mask register #0 read/write */
4754#define XSDM_REG_XSDM_PRTY_MASK 0x1662bc
f1410647
ET		 4755/* [R 11] Parity register #0 read */
4756#define XSDM_REG_XSDM_PRTY_STS 0x1662b0
a2fbb9ea
ET		 4757/* [RW 5] The number of time_slots in the arbitration cycle */
4758#define XSEM_REG_ARB_CYCLE_SIZE 0x280034
4759/* [RW 3] The source that is associated with arbitration element 0. Source
4760 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4761 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
4762#define XSEM_REG_ARB_ELEMENT0 0x280020
4763/* [RW 3] The source that is associated with arbitration element 1. Source
4764 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4765 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4766 Could not be equal to register ~xsem_registers_arb_element0.arb_element0 */
4767#define XSEM_REG_ARB_ELEMENT1 0x280024
4768/* [RW 3] The source that is associated with arbitration element 2. Source
4769 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4770 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4771 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
4772 and ~xsem_registers_arb_element1.arb_element1 */
4773#define XSEM_REG_ARB_ELEMENT2 0x280028
4774/* [RW 3] The source that is associated with arbitration element 3. Source
4775 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4776 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
4777 not be equal to register ~xsem_registers_arb_element0.arb_element0 and
4778 ~xsem_registers_arb_element1.arb_element1 and
4779 ~xsem_registers_arb_element2.arb_element2 */
4780#define XSEM_REG_ARB_ELEMENT3 0x28002c
4781/* [RW 3] The source that is associated with arbitration element 4. Source
4782 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4783 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4784 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
4785 and ~xsem_registers_arb_element1.arb_element1 and
4786 ~xsem_registers_arb_element2.arb_element2 and
4787 ~xsem_registers_arb_element3.arb_element3 */
4788#define XSEM_REG_ARB_ELEMENT4 0x280030
4789#define XSEM_REG_ENABLE_IN 0x2800a4
4790#define XSEM_REG_ENABLE_OUT 0x2800a8
4791/* [RW 32] This address space contains all registers and memories that are
4792 placed in SEM_FAST block. The SEM_FAST registers are described in
c18487ee
YR		 4793 appendix B. In order to access the sem_fast registers the base address
4794 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
a2fbb9ea
ET		 4795#define XSEM_REG_FAST_MEMORY 0x2a0000
4796/* [RW 1] Disables input messages from FIC0 May be updated during run_time
4797 by the microcode */
4798#define XSEM_REG_FIC0_DISABLE 0x280224
4799/* [RW 1] Disables input messages from FIC1 May be updated during run_time
4800 by the microcode */
4801#define XSEM_REG_FIC1_DISABLE 0x280234
4802/* [RW 15] Interrupt table Read and write access to it is not possible in
4803 the middle of the work */
4804#define XSEM_REG_INT_TABLE 0x280400
c18487ee 4805#define XSEM_REG_INT_TABLE_SIZE 256
a2fbb9ea
ET		 4806/* [ST 24] Statistics register. The number of messages that entered through
4807 FIC0 */
4808#define XSEM_REG_MSG_NUM_FIC0 0x280000
4809/* [ST 24] Statistics register. The number of messages that entered through
4810 FIC1 */
4811#define XSEM_REG_MSG_NUM_FIC1 0x280004
4812/* [ST 24] Statistics register. The number of messages that were sent to
4813 FOC0 */
4814#define XSEM_REG_MSG_NUM_FOC0 0x280008
4815/* [ST 24] Statistics register. The number of messages that were sent to
4816 FOC1 */
4817#define XSEM_REG_MSG_NUM_FOC1 0x28000c
4818/* [ST 24] Statistics register. The number of messages that were sent to
4819 FOC2 */
4820#define XSEM_REG_MSG_NUM_FOC2 0x280010
4821/* [ST 24] Statistics register. The number of messages that were sent to
4822 FOC3 */
4823#define XSEM_REG_MSG_NUM_FOC3 0x280014
4824/* [RW 1] Disables input messages from the passive buffer May be updated
4825 during run_time by the microcode */
4826#define XSEM_REG_PAS_DISABLE 0x28024c
4827/* [WB 128] Debug only. Passive buffer memory */
4828#define XSEM_REG_PASSIVE_BUFFER 0x282000
4829/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
4830#define XSEM_REG_PRAM 0x2c0000
4831/* [R 16] Valid sleeping threads indication have bit per thread */
4832#define XSEM_REG_SLEEP_THREADS_VALID 0x28026c
4833/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
4834#define XSEM_REG_SLOW_EXT_STORE_EMPTY 0x2802a0
4835/* [RW 16] List of free threads . There is a bit per thread. */
4836#define XSEM_REG_THREADS_LIST 0x2802e4
4837/* [RW 3] The arbitration scheme of time_slot 0 */
4838#define XSEM_REG_TS_0_AS 0x280038
4839/* [RW 3] The arbitration scheme of time_slot 10 */
4840#define XSEM_REG_TS_10_AS 0x280060
4841/* [RW 3] The arbitration scheme of time_slot 11 */
4842#define XSEM_REG_TS_11_AS 0x280064
4843/* [RW 3] The arbitration scheme of time_slot 12 */
4844#define XSEM_REG_TS_12_AS 0x280068
4845/* [RW 3] The arbitration scheme of time_slot 13 */
4846#define XSEM_REG_TS_13_AS 0x28006c
4847/* [RW 3] The arbitration scheme of time_slot 14 */
4848#define XSEM_REG_TS_14_AS 0x280070
4849/* [RW 3] The arbitration scheme of time_slot 15 */
4850#define XSEM_REG_TS_15_AS 0x280074
4851/* [RW 3] The arbitration scheme of time_slot 16 */
4852#define XSEM_REG_TS_16_AS 0x280078
4853/* [RW 3] The arbitration scheme of time_slot 17 */
4854#define XSEM_REG_TS_17_AS 0x28007c
4855/* [RW 3] The arbitration scheme of time_slot 18 */
4856#define XSEM_REG_TS_18_AS 0x280080
4857/* [RW 3] The arbitration scheme of time_slot 1 */
4858#define XSEM_REG_TS_1_AS 0x28003c
4859/* [RW 3] The arbitration scheme of time_slot 2 */
4860#define XSEM_REG_TS_2_AS 0x280040
4861/* [RW 3] The arbitration scheme of time_slot 3 */
4862#define XSEM_REG_TS_3_AS 0x280044
4863/* [RW 3] The arbitration scheme of time_slot 4 */
4864#define XSEM_REG_TS_4_AS 0x280048
4865/* [RW 3] The arbitration scheme of time_slot 5 */
4866#define XSEM_REG_TS_5_AS 0x28004c
4867/* [RW 3] The arbitration scheme of time_slot 6 */
4868#define XSEM_REG_TS_6_AS 0x280050
4869/* [RW 3] The arbitration scheme of time_slot 7 */
4870#define XSEM_REG_TS_7_AS 0x280054
4871/* [RW 3] The arbitration scheme of time_slot 8 */
4872#define XSEM_REG_TS_8_AS 0x280058
4873/* [RW 3] The arbitration scheme of time_slot 9 */
4874#define XSEM_REG_TS_9_AS 0x28005c
4875/* [RW 32] Interrupt mask register #0 read/write */
4876#define XSEM_REG_XSEM_INT_MASK_0 0x280110
4877#define XSEM_REG_XSEM_INT_MASK_1 0x280120
c18487ee
YR		 4878/* [R 32] Interrupt register #0 read */
4879#define XSEM_REG_XSEM_INT_STS_0 0x280104
4880#define XSEM_REG_XSEM_INT_STS_1 0x280114
a2fbb9ea
ET		 4881/* [RW 32] Parity mask register #0 read/write */
4882#define XSEM_REG_XSEM_PRTY_MASK_0 0x280130
4883#define XSEM_REG_XSEM_PRTY_MASK_1 0x280140
f1410647
ET		 4884/* [R 32] Parity register #0 read */
4885#define XSEM_REG_XSEM_PRTY_STS_0 0x280124
4886#define XSEM_REG_XSEM_PRTY_STS_1 0x280134
a2fbb9ea
ET		 4887#define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0)
4888#define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
4889#define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
4890#define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0)
4891#define MCPR_NVM_COMMAND_DOIT (1L<<4)
4892#define MCPR_NVM_COMMAND_DONE (1L<<3)
4893#define MCPR_NVM_COMMAND_FIRST (1L<<7)
4894#define MCPR_NVM_COMMAND_LAST (1L<<8)
4895#define MCPR_NVM_COMMAND_WR (1L<<5)
4896#define MCPR_NVM_COMMAND_WREN (1L<<16)
4897#define MCPR_NVM_COMMAND_WREN_BITSHIFT 16
4898#define MCPR_NVM_COMMAND_WRDI (1L<<17)
4899#define MCPR_NVM_COMMAND_WRDI_BITSHIFT 17
4900#define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9)
4901#define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
4902#define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
4903#define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3)
4904#define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
4905#define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3)
4906#define BIGMAC_REGISTER_RX_CONTROL (0x21<<3)
4907#define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3)
4908#define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3)
4909#define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3)
4910#define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3)
4911#define BIGMAC_REGISTER_TX_CONTROL (0x07<<3)
4912#define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3)
4913#define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3)
4914#define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3)
4915#define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3)
4916#define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3)
c18487ee
YR		 4917#define EMAC_LED_1000MB_OVERRIDE (1L<<1)
4918#define EMAC_LED_100MB_OVERRIDE (1L<<2)
4919#define EMAC_LED_10MB_OVERRIDE (1L<<3)
4920#define EMAC_LED_2500MB_OVERRIDE (1L<<12)
4921#define EMAC_LED_OVERRIDE (1L<<0)
4922#define EMAC_LED_TRAFFIC (1L<<6)
a2fbb9ea 4923#define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
a2fbb9ea 4924#define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
a2fbb9ea
ET		 4925#define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26)
4926#define EMAC_MDIO_COMM_DATA (0xffffL<<0)
4927#define EMAC_MDIO_COMM_START_BUSY (1L<<29)
4928#define EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
4929#define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31)
f1410647
ET		 4930#define EMAC_MDIO_MODE_CLOCK_CNT (0x3fL<<16)
4931#define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16
a2fbb9ea
ET		 4932#define EMAC_MODE_25G_MODE (1L<<5)
4933#define EMAC_MODE_ACPI_RCVD (1L<<20)
4934#define EMAC_MODE_HALF_DUPLEX (1L<<1)
4935#define EMAC_MODE_MPKT (1L<<18)
4936#define EMAC_MODE_MPKT_RCVD (1L<<19)
4937#define EMAC_MODE_PORT_GMII (2L<<2)
4938#define EMAC_MODE_PORT_MII (1L<<2)
4939#define EMAC_MODE_PORT_MII_10M (3L<<2)
4940#define EMAC_MODE_RESET (1L<<0)
c18487ee 4941#define EMAC_REG_EMAC_LED 0xc
a2fbb9ea
ET		 4942#define EMAC_REG_EMAC_MAC_MATCH 0x10
4943#define EMAC_REG_EMAC_MDIO_COMM 0xac
4944#define EMAC_REG_EMAC_MDIO_MODE 0xb4
4945#define EMAC_REG_EMAC_MODE 0x0
4946#define EMAC_REG_EMAC_RX_MODE 0xc8
4947#define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c
4948#define EMAC_REG_EMAC_RX_STAT_AC 0x180
4949#define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4
4950#define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23
4951#define EMAC_REG_EMAC_TX_MODE 0xbc
4952#define EMAC_REG_EMAC_TX_STAT_AC 0x280
4953#define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22
4954#define EMAC_RX_MODE_FLOW_EN (1L<<2)
4955#define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
4956#define EMAC_RX_MODE_PROMISCUOUS (1L<<8)
4957#define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
4958#define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
c18487ee 4959#define MISC_REGISTERS_GPIO_0 0
f1410647
ET		 4960#define MISC_REGISTERS_GPIO_1 1
4961#define MISC_REGISTERS_GPIO_2 2
4962#define MISC_REGISTERS_GPIO_3 3
4963#define MISC_REGISTERS_GPIO_CLR_POS 16
4964#define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24)
4965#define MISC_REGISTERS_GPIO_FLOAT_POS 24
c18487ee 4966#define MISC_REGISTERS_GPIO_HIGH 1
f1410647 4967#define MISC_REGISTERS_GPIO_INPUT_HI_Z 2
c18487ee 4968#define MISC_REGISTERS_GPIO_LOW 0
f1410647
ET		 4969#define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1
4970#define MISC_REGISTERS_GPIO_OUTPUT_LOW 0
4971#define MISC_REGISTERS_GPIO_PORT_SHIFT 4
4972#define MISC_REGISTERS_GPIO_SET_POS 8
a2fbb9ea
ET		 4973#define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588
4974#define MISC_REGISTERS_RESET_REG_1_SET 0x584
4975#define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598
4976#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
4977#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14)
4978#define MISC_REGISTERS_RESET_REG_2_SET 0x594
4979#define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8
4980#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1)
4981#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2)
4982#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
4983#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0)
4984#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5)
4985#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6)
4986#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7)
4987#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4)
4988#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8)
4989#define MISC_REGISTERS_RESET_REG_3_SET 0x5a4
f1410647
ET		 4990#define MISC_REGISTERS_SPIO_4 4
4991#define MISC_REGISTERS_SPIO_5 5
4992#define MISC_REGISTERS_SPIO_7 7
4993#define MISC_REGISTERS_SPIO_CLR_POS 16
4994#define MISC_REGISTERS_SPIO_FLOAT (0xffL<<24)
4995#define GRC_MISC_REGISTERS_SPIO_FLOAT7 0x80000000
4996#define GRC_MISC_REGISTERS_SPIO_FLOAT6 0x40000000
4997#define GRC_MISC_REGISTERS_SPIO_FLOAT5 0x20000000
4998#define GRC_MISC_REGISTERS_SPIO_FLOAT4 0x10000000
4999#define MISC_REGISTERS_SPIO_FLOAT_POS 24
5000#define MISC_REGISTERS_SPIO_INPUT_HI_Z 2
5001#define MISC_REGISTERS_SPIO_INT_OLD_SET_POS 16
5002#define MISC_REGISTERS_SPIO_OUTPUT_HIGH 1
5003#define MISC_REGISTERS_SPIO_OUTPUT_LOW 0
5004#define MISC_REGISTERS_SPIO_SET_POS 8
5005#define HW_LOCK_MAX_RESOURCE_VALUE 31
5006#define HW_LOCK_RESOURCE_8072_MDIO 0
5007#define HW_LOCK_RESOURCE_GPIO 1
5008#define HW_LOCK_RESOURCE_SPIO 2
a2fbb9ea
ET		 5009#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (1<<18)
5010#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (1<<31)
5011#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (1<<9)
5012#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (1<<8)
5013#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (1<<7)
5014#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (1<<6)
5015#define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (1<<29)
5016#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (1<<28)
5017#define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (1<<1)
5018#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (1<<0)
5019#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (1<<18)
5020#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (1<<11)
5021#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (1<<13)
5022#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (1<<12)
5023#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (1<<12)
5024#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (1<<15)
5025#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (1<<14)
5026#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (1<<20)
5027#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (1<<0)
5028#define AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT (1<<31)
5029#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (1<<3)
5030#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (1<<2)
5031#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (1<<5)
5032#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (1<<4)
5033#define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (1<<3)
5034#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (1<<2)
5035#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (1<<22)
f1410647 5036#define AEU_INPUTS_ATTN_BITS_SPIO5 (1<<15)
a2fbb9ea
ET		 5037#define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (1<<27)
5038#define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (1<<5)
5039#define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (1<<25)
5040#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (1<<24)
5041#define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (1<<29)
5042#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (1<<28)
5043#define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (1<<23)
5044#define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (1<<27)
5045#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (1<<26)
5046#define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (1<<21)
5047#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (1<<20)
5048#define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (1<<25)
5049#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (1<<24)
5050#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (1<<16)
5051#define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (1<<9)
5052#define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (1<<7)
5053#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (1<<6)
5054#define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (1<<11)
5055#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (1<<10)
5056#define RESERVED_GENERAL_ATTENTION_BIT_0 0
5057
c18487ee 5058#define EVEREST_GEN_ATTN_IN_USE_MASK 0x3ffe0
a2fbb9ea
ET		 5059#define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000
5060
5061#define RESERVED_GENERAL_ATTENTION_BIT_6 6
5062#define RESERVED_GENERAL_ATTENTION_BIT_7 7
5063#define RESERVED_GENERAL_ATTENTION_BIT_8 8
5064#define RESERVED_GENERAL_ATTENTION_BIT_9 9
5065#define RESERVED_GENERAL_ATTENTION_BIT_10 10
5066#define RESERVED_GENERAL_ATTENTION_BIT_11 11
5067#define RESERVED_GENERAL_ATTENTION_BIT_12 12
5068#define RESERVED_GENERAL_ATTENTION_BIT_13 13
5069#define RESERVED_GENERAL_ATTENTION_BIT_14 14
5070#define RESERVED_GENERAL_ATTENTION_BIT_15 15
5071#define RESERVED_GENERAL_ATTENTION_BIT_16 16
5072#define RESERVED_GENERAL_ATTENTION_BIT_17 17
5073#define RESERVED_GENERAL_ATTENTION_BIT_18 18
5074#define RESERVED_GENERAL_ATTENTION_BIT_19 19
5075#define RESERVED_GENERAL_ATTENTION_BIT_20 20
5076#define RESERVED_GENERAL_ATTENTION_BIT_21 21
5077
5078/* storm asserts attention bits */
5079#define TSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_7
5080#define USTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_8
5081#define CSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_9
5082#define XSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_10
5083
5084/* mcp error attention bit */
5085#define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11
5086
c18487ee
YR		 5087/*E1H NIG status sync attention mapped to group 4-7*/
5088#define LINK_SYNC_ATTENTION_BIT_FUNC_0 RESERVED_GENERAL_ATTENTION_BIT_12
5089#define LINK_SYNC_ATTENTION_BIT_FUNC_1 RESERVED_GENERAL_ATTENTION_BIT_13
5090#define LINK_SYNC_ATTENTION_BIT_FUNC_2 RESERVED_GENERAL_ATTENTION_BIT_14
5091#define LINK_SYNC_ATTENTION_BIT_FUNC_3 RESERVED_GENERAL_ATTENTION_BIT_15
5092#define LINK_SYNC_ATTENTION_BIT_FUNC_4 RESERVED_GENERAL_ATTENTION_BIT_16
5093#define LINK_SYNC_ATTENTION_BIT_FUNC_5 RESERVED_GENERAL_ATTENTION_BIT_17
5094#define LINK_SYNC_ATTENTION_BIT_FUNC_6 RESERVED_GENERAL_ATTENTION_BIT_18
5095#define LINK_SYNC_ATTENTION_BIT_FUNC_7 RESERVED_GENERAL_ATTENTION_BIT_19
5096
5097
a2fbb9ea
ET		 5098#define LATCHED_ATTN_RBCR 23
5099#define LATCHED_ATTN_RBCT 24
5100#define LATCHED_ATTN_RBCN 25
5101#define LATCHED_ATTN_RBCU 26
5102#define LATCHED_ATTN_RBCP 27
5103#define LATCHED_ATTN_TIMEOUT_GRC 28
5104#define LATCHED_ATTN_RSVD_GRC 29
5105#define LATCHED_ATTN_ROM_PARITY_MCP 30
5106#define LATCHED_ATTN_UM_RX_PARITY_MCP 31
5107#define LATCHED_ATTN_UM_TX_PARITY_MCP 32
5108#define LATCHED_ATTN_SCPAD_PARITY_MCP 33
5109
5110#define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32)
5111#define GENERAL_ATTEN_OFFSET(atten_name) (1 << ((94 + atten_name) % 32))
5112/*
5113 * This file defines GRC base address for every block.
5114 * This file is included by chipsim, asm microcode and cpp microcode.
5115 * These values are used in Design.xml on regBase attribute
5116 * Use the base with the generated offsets of specific registers.
5117 */
5118
5119#define GRCBASE_PXPCS 0x000000
5120#define GRCBASE_PCICONFIG 0x002000
5121#define GRCBASE_PCIREG 0x002400
5122#define GRCBASE_EMAC0 0x008000
5123#define GRCBASE_EMAC1 0x008400
5124#define GRCBASE_DBU 0x008800
5125#define GRCBASE_MISC 0x00A000
5126#define GRCBASE_DBG 0x00C000
5127#define GRCBASE_NIG 0x010000
5128#define GRCBASE_XCM 0x020000
5129#define GRCBASE_PRS 0x040000
5130#define GRCBASE_SRCH 0x040400
5131#define GRCBASE_TSDM 0x042000
5132#define GRCBASE_TCM 0x050000
5133#define GRCBASE_BRB1 0x060000
5134#define GRCBASE_MCP 0x080000
5135#define GRCBASE_UPB 0x0C1000
5136#define GRCBASE_CSDM 0x0C2000
5137#define GRCBASE_USDM 0x0C4000
5138#define GRCBASE_CCM 0x0D0000
5139#define GRCBASE_UCM 0x0E0000
5140#define GRCBASE_CDU 0x101000
5141#define GRCBASE_DMAE 0x102000
5142#define GRCBASE_PXP 0x103000
5143#define GRCBASE_CFC 0x104000
5144#define GRCBASE_HC 0x108000
5145#define GRCBASE_PXP2 0x120000
5146#define GRCBASE_PBF 0x140000
5147#define GRCBASE_XPB 0x161000
5148#define GRCBASE_TIMERS 0x164000
5149#define GRCBASE_XSDM 0x166000
5150#define GRCBASE_QM 0x168000
5151#define GRCBASE_DQ 0x170000
5152#define GRCBASE_TSEM 0x180000
5153#define GRCBASE_CSEM 0x200000
5154#define GRCBASE_XSEM 0x280000
5155#define GRCBASE_USEM 0x300000
5156#define GRCBASE_MISC_AEU GRCBASE_MISC
5157
5158
5159/*the offset of the configuration space in the pci core register*/
5160#define PCICFG_OFFSET 0x2000
5161#define PCICFG_VENDOR_ID_OFFSET 0x00
5162#define PCICFG_DEVICE_ID_OFFSET 0x02
c18487ee
YR		 5163#define PCICFG_COMMAND_OFFSET 0x04
5164#define PCICFG_STATUS_OFFSET 0x06
5165#define PCICFG_REVESION_ID 0x08
a2fbb9ea
ET		 5166#define PCICFG_CACHE_LINE_SIZE 0x0c
5167#define PCICFG_LATENCY_TIMER 0x0d
c18487ee
YR		 5168#define PCICFG_BAR_1_LOW 0x10
5169#define PCICFG_BAR_1_HIGH 0x14
5170#define PCICFG_BAR_2_LOW 0x18
5171#define PCICFG_BAR_2_HIGH 0x1c
5172#define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c
5173#define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e
5174#define PCICFG_INT_LINE 0x3c
5175#define PCICFG_INT_PIN 0x3d
5176#define PCICFG_PM_CSR_OFFSET 0x4c
5177#define PCICFG_GRC_ADDRESS 0x78
5178#define PCICFG_GRC_DATA 0x80
a2fbb9ea
ET		 5179#define PCICFG_DEVICE_CONTROL 0xb4
5180#define PCICFG_LINK_CONTROL 0xbc
5181
c18487ee
YR		 5182#define PCICFG_COMMAND_IO_SPACE (1<<0)
5183#define PCICFG_COMMAND_MEM_SPACE (1<<1)
5184#define PCICFG_COMMAND_BUS_MASTER (1<<2)
5185#define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3)
5186#define PCICFG_COMMAND_MWI_CYCLES (1<<4)
5187#define PCICFG_COMMAND_VGA_SNOOP (1<<5)
5188#define PCICFG_COMMAND_PERR_ENA (1<<6)
5189#define PCICFG_COMMAND_STEPPING (1<<7)
5190#define PCICFG_COMMAND_SERR_ENA (1<<8)
5191#define PCICFG_COMMAND_FAST_B2B (1<<9)
5192#define PCICFG_COMMAND_INT_DISABLE (1<<10)
5193#define PCICFG_COMMAND_RESERVED (0x1f<<11)
5194
5195#define PCICFG_PM_CSR_STATE (0x3<<0)
5196#define PCICFG_PM_CSR_PME_STATUS (1<<15)
5197
a2fbb9ea
ET		 5198#define BAR_USTRORM_INTMEM 0x400000
5199#define BAR_CSTRORM_INTMEM 0x410000
5200#define BAR_XSTRORM_INTMEM 0x420000
5201#define BAR_TSTRORM_INTMEM 0x430000
5202
5203#define BAR_IGU_INTMEM 0x440000
5204
5205#define BAR_DOORBELL_OFFSET 0x800000
5206
5207#define BAR_ME_REGISTER 0x450000
5208
5209
5210#define GRC_CONFIG_2_SIZE_REG 0x408 /* config_2 offset */
5211#define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
5212#define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
5213#define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
5214#define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
5215#define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
5216#define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
5217#define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
5218#define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
5219#define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
5220#define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
5221#define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
5222#define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
5223#define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
5224#define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
5225#define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
5226#define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
5227#define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
5228#define PCI_CONFIG_2_BAR1_64ENA (1L<<4)
5229#define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
5230#define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
5231#define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
5232#define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
5233#define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
5234#define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8)
5235#define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8)
5236#define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8)
5237#define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8)
5238#define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8)
5239#define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8)
5240#define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8)
5241#define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8)
5242#define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8)
5243#define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8)
5244#define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8)
5245#define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8)
5246#define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8)
5247#define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8)
5248#define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8)
5249#define PCI_CONFIG_2_BAR_PREFETCH (1L<<16)
5250#define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17)
5251
5252/* config_3 offset */
5253#define GRC_CONFIG_3_SIZE_REG (0x40c)
5254#define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
5255#define PCI_CONFIG_3_FORCE_PME (1L<<24)
5256#define PCI_CONFIG_3_PME_STATUS (1L<<25)
5257#define PCI_CONFIG_3_PME_ENABLE (1L<<26)
5258#define PCI_CONFIG_3_PM_STATE (0x3L<<27)
5259#define PCI_CONFIG_3_VAUX_PRESET (1L<<30)
5260#define PCI_CONFIG_3_PCI_POWER (1L<<31)
5261
5262/* config_2 offset */
5263#define GRC_CONFIG_2_SIZE_REG 0x408
5264
5265#define GRC_BAR2_CONFIG 0x4e0
5266#define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0)
5267#define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0)
5268#define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0)
5269#define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0)
5270#define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0)
5271#define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0)
5272#define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0)
5273#define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0)
5274#define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0)
5275#define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0)
5276#define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0)
5277#define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0)
5278#define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0)
5279#define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0)
5280#define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0)
5281#define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0)
5282#define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0)
5283#define PCI_CONFIG_2_BAR2_64ENA (1L<<4)
5284
5285#define PCI_PM_DATA_A (0x410)
5286#define PCI_PM_DATA_B (0x414)
5287#define PCI_ID_VAL1 (0x434)
5288#define PCI_ID_VAL2 (0x438)
5289
5290#define MDIO_REG_BANK_CL73_IEEEB0 0x0
5291#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
5292#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
5293#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
5294#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
5295
5296#define MDIO_REG_BANK_CL73_IEEEB1 0x10
c18487ee 5297#define MDIO_CL73_IEEEB1_AN_ADV2 0x01
a2fbb9ea
ET		 5298#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
5299#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
5300#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
5301#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
5302
5303#define MDIO_REG_BANK_RX0 0x80b0
5304#define MDIO_RX0_RX_EQ_BOOST 0x1c
5305#define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5306#define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
5307
5308#define MDIO_REG_BANK_RX1 0x80c0
5309#define MDIO_RX1_RX_EQ_BOOST 0x1c
5310#define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5311#define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
5312
5313#define MDIO_REG_BANK_RX2 0x80d0
5314#define MDIO_RX2_RX_EQ_BOOST 0x1c
5315#define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5316#define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
5317
5318#define MDIO_REG_BANK_RX3 0x80e0
5319#define MDIO_RX3_RX_EQ_BOOST 0x1c
5320#define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5321#define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
5322
5323#define MDIO_REG_BANK_RX_ALL 0x80f0
5324#define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
5325#define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
c18487ee 5326#define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
a2fbb9ea
ET		 5327
5328#define MDIO_REG_BANK_TX0 0x8060
5329#define MDIO_TX0_TX_DRIVER 0x17
5330#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
5331#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
5332#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
5333#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
5334#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
5335#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
5336#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
5337#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
5338#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
5339
5340#define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
5341#define MDIO_BLOCK0_XGXS_CONTROL 0x10
5342
5343#define MDIO_REG_BANK_XGXS_BLOCK1 0x8010
5344#define MDIO_BLOCK1_LANE_CTRL0 0x15
5345#define MDIO_BLOCK1_LANE_CTRL1 0x16
5346#define MDIO_BLOCK1_LANE_CTRL2 0x17
5347#define MDIO_BLOCK1_LANE_PRBS 0x19
5348
5349#define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
5350#define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
5351#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
5352#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
c18487ee 5353#define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
a2fbb9ea 5354#define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
c18487ee 5355#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
f1410647
ET		 5356#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
5357#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
c18487ee 5358#define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
a2fbb9ea
ET		 5359
5360#define MDIO_REG_BANK_GP_STATUS 0x8120
c18487ee
YR		 5361#define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
5362#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
5363#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
5364#define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
5365#define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
5366#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
5367#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
5368#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
5369#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
5370#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
5371#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
5372#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
5373#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
5374#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
5375#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
5376#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
5377#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
5378#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
5379#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
5380#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
5381#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
5382#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
5383#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
5384#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
5385#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
a2fbb9ea
ET		 5386
5387
5388#define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
c18487ee
YR		 5389#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
5390#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
5391#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
5392#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
a2fbb9ea
ET		 5393
5394#define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
c18487ee
YR		 5395#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
5396#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
5397#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
5398#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
5399#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
5400#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
5401#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
5402#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
5403#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
5404#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
5405#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
5406#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
5407#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
5408#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
5409#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
5410#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
5411#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
5412#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
5413#define MDIO_SERDES_DIGITAL_MISC1 0x18
5414#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
5415#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
5416#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
5417#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
5418#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
5419#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
5420#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
5421#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
5422#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
5423#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
5424#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
5425#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
5426#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
5427#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
5428#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
5429#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
5430#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
5431#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
a2fbb9ea
ET		 5432
5433#define MDIO_REG_BANK_OVER_1G 0x8320
c18487ee
YR		 5434#define MDIO_OVER_1G_DIGCTL_3_4 0x14
5435#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
5436#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
5437#define MDIO_OVER_1G_UP1 0x19
5438#define MDIO_OVER_1G_UP1_2_5G 0x0001
5439#define MDIO_OVER_1G_UP1_5G 0x0002
5440#define MDIO_OVER_1G_UP1_6G 0x0004
5441#define MDIO_OVER_1G_UP1_10G 0x0010
5442#define MDIO_OVER_1G_UP1_10GH 0x0008
5443#define MDIO_OVER_1G_UP1_12G 0x0020
5444#define MDIO_OVER_1G_UP1_12_5G 0x0040
5445#define MDIO_OVER_1G_UP1_13G 0x0080
5446#define MDIO_OVER_1G_UP1_15G 0x0100
5447#define MDIO_OVER_1G_UP1_16G 0x0200
5448#define MDIO_OVER_1G_UP2 0x1A
5449#define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
5450#define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
5451#define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
5452#define MDIO_OVER_1G_UP3 0x1B
5453#define MDIO_OVER_1G_UP3_HIGIG2 0x0001
5454#define MDIO_OVER_1G_LP_UP1 0x1C
5455#define MDIO_OVER_1G_LP_UP2 0x1D
5456#define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
5457#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
5458#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
5459#define MDIO_OVER_1G_LP_UP3 0x1E
a2fbb9ea
ET		 5460
5461#define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
c18487ee
YR		 5462#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
5463#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
5464#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
5465
5466#define MDIO_REG_BANK_CL73_USERB0 0x8370
5467#define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
5468#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
5469#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
5470#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
5471#define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
5472#define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
5473
5474#define MDIO_REG_BANK_AER_BLOCK 0xFFD0
5475#define MDIO_AER_BLOCK_AER_REG 0x1E
5476
5477#define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
5478#define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
5479#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
5480#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
5481#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
5482#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
5483#define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
5484#define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
5485#define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
5486#define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
5487#define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
5488#define MDIO_COMBO_IEEE0_MII_STATUS 0x11
5489#define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
5490#define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
5491#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
5492#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
5493#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
5494#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
5495#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
5496#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
5497#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
5498#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
5499#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
5500#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
5501#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
5502#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
5503#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
5504#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000
5505#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180
5506#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
5507#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
5508/*WhenthelinkpartnerisinSGMIImode(bit0=1),then
5509bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge.
5510Theotherbitsarereservedandshouldbezero*/
5511#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
5512
5513
5514#define MDIO_PMA_DEVAD 0x1
5515/*ieee*/
5516#define MDIO_PMA_REG_CTRL 0x0
5517#define MDIO_PMA_REG_STATUS 0x1
5518#define MDIO_PMA_REG_10G_CTRL2 0x7
5519#define MDIO_PMA_REG_RX_SD 0xa
5520/*bcm*/
5521#define MDIO_PMA_REG_BCM_CTRL 0x0096
5522#define MDIO_PMA_REG_FEC_CTRL 0x00ab
5523#define MDIO_PMA_REG_RX_ALARM_CTRL 0x9000
5524#define MDIO_PMA_REG_LASI_CTRL 0x9002
5525#define MDIO_PMA_REG_RX_ALARM 0x9003
5526#define MDIO_PMA_REG_TX_ALARM 0x9004
5527#define MDIO_PMA_REG_LASI_STATUS 0x9005
5528#define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800
5529#define MDIO_PMA_REG_DIGITAL_CTRL 0xc808
5530#define MDIO_PMA_REG_DIGITAL_STATUS 0xc809
5531#define MDIO_PMA_REG_TX_POWER_DOWN 0xca02
5532#define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09
5533#define MDIO_PMA_REG_MISC_CTRL 0xca0a
5534#define MDIO_PMA_REG_GEN_CTRL 0xca10
5535#define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
5536#define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
5537#define MDIO_PMA_REG_ROM_VER1 0xca19
5538#define MDIO_PMA_REG_ROM_VER2 0xca1a
5539#define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
5540#define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d
5541#define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46
5542#define MDIO_PMA_REG_MISC_CTRL1 0xca85
5543
5544#define MDIO_PMA_REG_7101_RESET 0xc000
5545#define MDIO_PMA_REG_7107_LED_CNTL 0xc007
5546#define MDIO_PMA_REG_7101_VER1 0xc026
5547#define MDIO_PMA_REG_7101_VER2 0xc027
5548
5549
5550#define MDIO_WIS_DEVAD 0x2
5551/*bcm*/
5552#define MDIO_WIS_REG_LASI_CNTL 0x9002
5553#define MDIO_WIS_REG_LASI_STATUS 0x9005
5554
5555#define MDIO_PCS_DEVAD 0x3
5556#define MDIO_PCS_REG_STATUS 0x0020
5557#define MDIO_PCS_REG_LASI_STATUS 0x9005
5558#define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000
5559#define MDIO_PCS_REG_7101_SPI_MUX 0xD008
5560#define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
5561#define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
5562#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
5563#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
5564#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
5565#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
5566#define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
5567
a2fbb9ea 5568
c18487ee
YR		 5569#define MDIO_XS_DEVAD 0x4
5570#define MDIO_XS_PLL_SEQUENCER 0x8000
5571#define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a
a2fbb9ea 5572
c18487ee
YR		 5573#define MDIO_AN_DEVAD 0x7
5574/*ieee*/
5575#define MDIO_AN_REG_CTRL 0x0000
5576#define MDIO_AN_REG_STATUS 0x0001
5577#define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
5578#define MDIO_AN_REG_ADV_PAUSE 0x0010
5579#define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400
5580#define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
5581#define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00
5582#define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00
5583#define MDIO_AN_REG_ADV 0x0011
5584#define MDIO_AN_REG_ADV2 0x0012
5585#define MDIO_AN_REG_LP_AUTO_NEG 0x0013
5586#define MDIO_AN_REG_MASTER_STATUS 0x0021
5587/*bcm*/
5588#define MDIO_AN_REG_LINK_STATUS 0x8304
5589#define MDIO_AN_REG_CL37_CL73 0x8370
5590#define MDIO_AN_REG_CL37_AN 0xffe0
5591#define MDIO_AN_REG_CL37_FD 0xffe4
a2fbb9ea 5592
a2fbb9ea 5593
c18487ee 5594#define IGU_FUNC_BASE 0x0400
a2fbb9ea 5595
c18487ee
YR		 5596#define IGU_ADDR_MSIX 0x0000
5597#define IGU_ADDR_INT_ACK 0x0200
5598#define IGU_ADDR_PROD_UPD 0x0201
5599#define IGU_ADDR_ATTN_BITS_UPD 0x0202
5600#define IGU_ADDR_ATTN_BITS_SET 0x0203
5601#define IGU_ADDR_ATTN_BITS_CLR 0x0204
5602#define IGU_ADDR_COALESCE_NOW 0x0205
5603#define IGU_ADDR_SIMD_MASK 0x0206
5604#define IGU_ADDR_SIMD_NOMASK 0x0207
5605#define IGU_ADDR_MSI_CTL 0x0210
5606#define IGU_ADDR_MSI_ADDR_LO 0x0211
5607#define IGU_ADDR_MSI_ADDR_HI 0x0212
5608#define IGU_ADDR_MSI_DATA 0x0213
a2fbb9ea 5609
c18487ee
YR		 5610#define IGU_INT_ENABLE 0
5611#define IGU_INT_DISABLE 1
5612#define IGU_INT_NOP 2
5613#define IGU_INT_NOP2 3
f1410647 5614
a2fbb9ea 5615