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bnx2x: Removing redundant device parameters
[GitHub/LineageOS/android_kernel_samsung_universal7580.git] / drivers / net / bnx2x_reg.h
CommitLineData
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ET		 1/* bnx2x_reg.h: Broadcom Everest network driver.
2 *
d05c26ce 3 * Copyright (c) 2007-2009 Broadcom Corporation
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ET		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
33471629 9 * The registers description starts with the register Access type followed
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ET		 10 * by size in bits. For example [RW 32]. The access types are:
11 * R - Read only
12 * RC - Clear on read
13 * RW - Read/Write
14 * ST - Statistics register (clear on read)
15 * W - Write only
16 * WB - Wide bus register - the size is over 32 bits and it should be
17 * read/write in consecutive 32 bits accesses
18 * WR - Write Clear (write 1 to clear the bit)
19 *
20 */
21
22
23/* [R 19] Interrupt register #0 read */
24#define BRB1_REG_BRB1_INT_STS 0x6011c
25/* [RW 4] Parity mask register #0 read/write */
26#define BRB1_REG_BRB1_PRTY_MASK 0x60138
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ET		 27/* [R 4] Parity register #0 read */
28#define BRB1_REG_BRB1_PRTY_STS 0x6012c
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ET		 29/* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
30 address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address
31 BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. */
32#define BRB1_REG_FREE_LIST_PRS_CRDT 0x60200
1c06328c
EG		 33/* [RW 10] The number of free blocks above which the High_llfc signal to
34 interface #n is de-asserted. */
35#define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0 0x6014c
36/* [RW 10] The number of free blocks below which the High_llfc signal to
37 interface #n is asserted. */
38#define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0 0x6013c
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ET		 39/* [RW 23] LL RAM data. */
40#define BRB1_REG_LL_RAM 0x61000
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EG		 41/* [RW 10] The number of free blocks above which the Low_llfc signal to
42 interface #n is de-asserted. */
43#define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0 0x6016c
44/* [RW 10] The number of free blocks below which the Low_llfc signal to
45 interface #n is asserted. */
46#define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0 0x6015c
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ET		 47/* [R 24] The number of full blocks. */
48#define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090
49/* [ST 32] The number of cycles that the write_full signal towards MAC #0
50 was asserted. */
51#define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8
52#define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc
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ET		 53#define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8
54/* [ST 32] The number of cycles that the pause signal towards MAC #0 was
55 asserted. */
56#define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8
57#define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc
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ET		 58/* [RW 10] Write client 0: De-assert pause threshold. */
59#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078
60#define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c
61/* [RW 10] Write client 0: Assert pause threshold. */
62#define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068
63#define BRB1_REG_PAUSE_LOW_THRESHOLD_1 0x6006c
33471629 64/* [R 24] The number of full blocks occupied by port. */
34f80b04 65#define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094
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ET		 66/* [RW 1] Reset the design by software. */
67#define BRB1_REG_SOFT_RESET 0x600dc
68/* [R 5] Used to read the value of the XX protection CAM occupancy counter. */
69#define CCM_REG_CAM_OCCUP 0xd0188
70/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
71 acknowledge output is deasserted; all other signals are treated as usual;
72 if 1 - normal activity. */
73#define CCM_REG_CCM_CFC_IFEN 0xd003c
74/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
75 disregarded; valid is deasserted; all other signals are treated as usual;
76 if 1 - normal activity. */
77#define CCM_REG_CCM_CQM_IFEN 0xd000c
78/* [RW 1] If set the Q index; received from the QM is inserted to event ID.
79 Otherwise 0 is inserted. */
80#define CCM_REG_CCM_CQM_USE_Q 0xd00c0
81/* [RW 11] Interrupt mask register #0 read/write */
82#define CCM_REG_CCM_INT_MASK 0xd01e4
83/* [R 11] Interrupt register #0 read */
84#define CCM_REG_CCM_INT_STS 0xd01d8
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YR		 85/* [R 27] Parity register #0 read */
86#define CCM_REG_CCM_PRTY_STS 0xd01e8
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ET		 87/* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
88 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
89 Is used to determine the number of the AG context REG-pairs written back;
90 when the input message Reg1WbFlg isn't set. */
91#define CCM_REG_CCM_REG0_SZ 0xd00c4
92/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
93 disregarded; valid is deasserted; all other signals are treated as usual;
94 if 1 - normal activity. */
95#define CCM_REG_CCM_STORM0_IFEN 0xd0004
96/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
97 disregarded; valid is deasserted; all other signals are treated as usual;
98 if 1 - normal activity. */
99#define CCM_REG_CCM_STORM1_IFEN 0xd0008
100/* [RW 1] CDU AG read Interface enable. If 0 - the request input is
101 disregarded; valid output is deasserted; all other signals are treated as
102 usual; if 1 - normal activity. */
103#define CCM_REG_CDU_AG_RD_IFEN 0xd0030
104/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
105 are disregarded; all other signals are treated as usual; if 1 - normal
106 activity. */
107#define CCM_REG_CDU_AG_WR_IFEN 0xd002c
108/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
109 disregarded; valid output is deasserted; all other signals are treated as
110 usual; if 1 - normal activity. */
111#define CCM_REG_CDU_SM_RD_IFEN 0xd0038
112/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
113 input is disregarded; all other signals are treated as usual; if 1 -
114 normal activity. */
115#define CCM_REG_CDU_SM_WR_IFEN 0xd0034
116/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
117 the initial credit value; read returns the current value of the credit
118 counter. Must be initialized to 1 at start-up. */
119#define CCM_REG_CFC_INIT_CRD 0xd0204
120/* [RW 2] Auxillary counter flag Q number 1. */
121#define CCM_REG_CNT_AUX1_Q 0xd00c8
122/* [RW 2] Auxillary counter flag Q number 2. */
123#define CCM_REG_CNT_AUX2_Q 0xd00cc
124/* [RW 28] The CM header value for QM request (primary). */
125#define CCM_REG_CQM_CCM_HDR_P 0xd008c
126/* [RW 28] The CM header value for QM request (secondary). */
127#define CCM_REG_CQM_CCM_HDR_S 0xd0090
128/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
129 acknowledge output is deasserted; all other signals are treated as usual;
130 if 1 - normal activity. */
131#define CCM_REG_CQM_CCM_IFEN 0xd0014
132/* [RW 6] QM output initial credit. Max credit available - 32. Write writes
133 the initial credit value; read returns the current value of the credit
134 counter. Must be initialized to 32 at start-up. */
135#define CCM_REG_CQM_INIT_CRD 0xd020c
136/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
137 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
138 prioritised); 2 stands for weight 2; tc. */
139#define CCM_REG_CQM_P_WEIGHT 0xd00b8
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EG		 140/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
141 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
142 prioritised); 2 stands for weight 2; tc. */
143#define CCM_REG_CQM_S_WEIGHT 0xd00bc
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ET		 144/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
145 acknowledge output is deasserted; all other signals are treated as usual;
146 if 1 - normal activity. */
147#define CCM_REG_CSDM_IFEN 0xd0018
148/* [RC 1] Set when the message length mismatch (relative to last indication)
149 at the SDM interface is detected. */
150#define CCM_REG_CSDM_LENGTH_MIS 0xd0170
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EG		 151/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
152 weight 8 (the most prioritised); 1 stands for weight 1(least
153 prioritised); 2 stands for weight 2; tc. */
154#define CCM_REG_CSDM_WEIGHT 0xd00b4
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ET		 155/* [RW 28] The CM header for QM formatting in case of an error in the QM
156 inputs. */
157#define CCM_REG_ERR_CCM_HDR 0xd0094
158/* [RW 8] The Event ID in case the input message ErrorFlg is set. */
159#define CCM_REG_ERR_EVNT_ID 0xd0098
160/* [RW 8] FIC0 output initial credit. Max credit available - 255. Write
161 writes the initial credit value; read returns the current value of the
162 credit counter. Must be initialized to 64 at start-up. */
163#define CCM_REG_FIC0_INIT_CRD 0xd0210
164/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
165 writes the initial credit value; read returns the current value of the
166 credit counter. Must be initialized to 64 at start-up. */
167#define CCM_REG_FIC1_INIT_CRD 0xd0214
168/* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
169 - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr;
170 ~ccm_registers_gr_ld0_pr.gr_ld0_pr and
171 ~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and
172 outputs to STORM: aggregation; load FIC0; load FIC1 and store. */
173#define CCM_REG_GR_ARB_TYPE 0xd015c
174/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
175 highest priority is 3. It is supposed; that the Store channel priority is
176 the compliment to 4 of the rest priorities - Aggregation channel; Load
177 (FIC0) channel and Load (FIC1). */
178#define CCM_REG_GR_LD0_PR 0xd0164
179/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
180 highest priority is 3. It is supposed; that the Store channel priority is
181 the compliment to 4 of the rest priorities - Aggregation channel; Load
182 (FIC0) channel and Load (FIC1). */
183#define CCM_REG_GR_LD1_PR 0xd0168
184/* [RW 2] General flags index. */
185#define CCM_REG_INV_DONE_Q 0xd0108
186/* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM
187 context and sent to STORM; for a specific connection type. The double
188 REG-pairs are used in order to align to STORM context row size of 128
189 bits. The offset of these data in the STORM context is always 0. Index
190 _(0..15) stands for the connection type (one of 16). */
191#define CCM_REG_N_SM_CTX_LD_0 0xd004c
192#define CCM_REG_N_SM_CTX_LD_1 0xd0050
193#define CCM_REG_N_SM_CTX_LD_10 0xd0074
194#define CCM_REG_N_SM_CTX_LD_11 0xd0078
195#define CCM_REG_N_SM_CTX_LD_12 0xd007c
196#define CCM_REG_N_SM_CTX_LD_13 0xd0080
197#define CCM_REG_N_SM_CTX_LD_14 0xd0084
198#define CCM_REG_N_SM_CTX_LD_15 0xd0088
199#define CCM_REG_N_SM_CTX_LD_2 0xd0054
200#define CCM_REG_N_SM_CTX_LD_3 0xd0058
201#define CCM_REG_N_SM_CTX_LD_4 0xd005c
202/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
203 acknowledge output is deasserted; all other signals are treated as usual;
204 if 1 - normal activity. */
205#define CCM_REG_PBF_IFEN 0xd0028
206/* [RC 1] Set when the message length mismatch (relative to last indication)
207 at the pbf interface is detected. */
208#define CCM_REG_PBF_LENGTH_MIS 0xd0180
209/* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
210 weight 8 (the most prioritised); 1 stands for weight 1(least
211 prioritised); 2 stands for weight 2; tc. */
212#define CCM_REG_PBF_WEIGHT 0xd00ac
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ET		 213#define CCM_REG_PHYS_QNUM1_0 0xd0134
214#define CCM_REG_PHYS_QNUM1_1 0xd0138
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ET		 215#define CCM_REG_PHYS_QNUM2_0 0xd013c
216#define CCM_REG_PHYS_QNUM2_1 0xd0140
a2fbb9ea 217#define CCM_REG_PHYS_QNUM3_0 0xd0144
c18487ee 218#define CCM_REG_PHYS_QNUM3_1 0xd0148
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ET		 219#define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114
220#define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118
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ET		 221#define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c
222#define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120
a2fbb9ea 223#define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124
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YR		 224#define CCM_REG_QOS_PHYS_QNUM2_1 0xd0128
225#define CCM_REG_QOS_PHYS_QNUM3_0 0xd012c
226#define CCM_REG_QOS_PHYS_QNUM3_1 0xd0130
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ET		 227/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
228 disregarded; acknowledge output is deasserted; all other signals are
229 treated as usual; if 1 - normal activity. */
230#define CCM_REG_STORM_CCM_IFEN 0xd0010
231/* [RC 1] Set when the message length mismatch (relative to last indication)
232 at the STORM interface is detected. */
233#define CCM_REG_STORM_LENGTH_MIS 0xd016c
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EG		 234/* [RW 3] The weight of the STORM input in the WRR (Weighted Round robin)
235 mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for
236 weight 1(least prioritised); 2 stands for weight 2 (more prioritised);
237 tc. */
238#define CCM_REG_STORM_WEIGHT 0xd009c
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ET		 239/* [RW 1] Input tsem Interface enable. If 0 - the valid input is
240 disregarded; acknowledge output is deasserted; all other signals are
241 treated as usual; if 1 - normal activity. */
242#define CCM_REG_TSEM_IFEN 0xd001c
243/* [RC 1] Set when the message length mismatch (relative to last indication)
244 at the tsem interface is detected. */
245#define CCM_REG_TSEM_LENGTH_MIS 0xd0174
246/* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
247 weight 8 (the most prioritised); 1 stands for weight 1(least
248 prioritised); 2 stands for weight 2; tc. */
249#define CCM_REG_TSEM_WEIGHT 0xd00a0
250/* [RW 1] Input usem Interface enable. If 0 - the valid input is
251 disregarded; acknowledge output is deasserted; all other signals are
252 treated as usual; if 1 - normal activity. */
253#define CCM_REG_USEM_IFEN 0xd0024
254/* [RC 1] Set when message length mismatch (relative to last indication) at
255 the usem interface is detected. */
256#define CCM_REG_USEM_LENGTH_MIS 0xd017c
257/* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
258 weight 8 (the most prioritised); 1 stands for weight 1(least
259 prioritised); 2 stands for weight 2; tc. */
260#define CCM_REG_USEM_WEIGHT 0xd00a8
261/* [RW 1] Input xsem Interface enable. If 0 - the valid input is
262 disregarded; acknowledge output is deasserted; all other signals are
263 treated as usual; if 1 - normal activity. */
264#define CCM_REG_XSEM_IFEN 0xd0020
265/* [RC 1] Set when the message length mismatch (relative to last indication)
266 at the xsem interface is detected. */
267#define CCM_REG_XSEM_LENGTH_MIS 0xd0178
268/* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
269 weight 8 (the most prioritised); 1 stands for weight 1(least
270 prioritised); 2 stands for weight 2; tc. */
271#define CCM_REG_XSEM_WEIGHT 0xd00a4
272/* [RW 19] Indirect access to the descriptor table of the XX protection
273 mechanism. The fields are: [5:0] - message length; [12:6] - message
274 pointer; 18:13] - next pointer. */
275#define CCM_REG_XX_DESCR_TABLE 0xd0300
c18487ee 276#define CCM_REG_XX_DESCR_TABLE_SIZE 36
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ET		 277/* [R 7] Used to read the value of XX protection Free counter. */
278#define CCM_REG_XX_FREE 0xd0184
279/* [RW 6] Initial value for the credit counter; responsible for fulfilling
280 of the Input Stage XX protection buffer by the XX protection pending
281 messages. Max credit available - 127. Write writes the initial credit
282 value; read returns the current value of the credit counter. Must be
283 initialized to maximum XX protected message size - 2 at start-up. */
284#define CCM_REG_XX_INIT_CRD 0xd0220
285/* [RW 7] The maximum number of pending messages; which may be stored in XX
286 protection. At read the ~ccm_registers_xx_free.xx_free counter is read.
287 At write comprises the start value of the ~ccm_registers_xx_free.xx_free
288 counter. */
289#define CCM_REG_XX_MSG_NUM 0xd0224
290/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
291#define CCM_REG_XX_OVFL_EVNT_ID 0xd0044
292/* [RW 18] Indirect access to the XX table of the XX protection mechanism.
293 The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] -
294 header pointer. */
295#define CCM_REG_XX_TABLE 0xd0280
296#define CDU_REG_CDU_CHK_MASK0 0x101000
297#define CDU_REG_CDU_CHK_MASK1 0x101004
298#define CDU_REG_CDU_CONTROL0 0x101008
299#define CDU_REG_CDU_DEBUG 0x101010
300#define CDU_REG_CDU_GLOBAL_PARAMS 0x101020
301/* [RW 7] Interrupt mask register #0 read/write */
302#define CDU_REG_CDU_INT_MASK 0x10103c
303/* [R 7] Interrupt register #0 read */
304#define CDU_REG_CDU_INT_STS 0x101030
305/* [RW 5] Parity mask register #0 read/write */
306#define CDU_REG_CDU_PRTY_MASK 0x10104c
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ET		 307/* [R 5] Parity register #0 read */
308#define CDU_REG_CDU_PRTY_STS 0x101040
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ET		 309/* [RC 32] logging of error data in case of a CDU load error:
310 {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error;
311 ype_error; ctual_active; ctual_compressed_context}; */
312#define CDU_REG_ERROR_DATA 0x101014
313/* [WB 216] L1TT ram access. each entry has the following format :
314 {mrege_regions[7:0]; ffset12[5:0]...offset0[5:0];
315 ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */
316#define CDU_REG_L1TT 0x101800
317/* [WB 24] MATT ram access. each entry has the following
318 format:{RegionLength[11:0]; egionOffset[11:0]} */
319#define CDU_REG_MATT 0x101100
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YR		 320/* [RW 1] when this bit is set the CDU operates in e1hmf mode */
321#define CDU_REG_MF_MODE 0x101050
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ET		 322/* [R 1] indication the initializing the activity counter by the hardware
323 was done. */
324#define CFC_REG_AC_INIT_DONE 0x104078
325/* [RW 13] activity counter ram access */
326#define CFC_REG_ACTIVITY_COUNTER 0x104400
327#define CFC_REG_ACTIVITY_COUNTER_SIZE 256
328/* [R 1] indication the initializing the cams by the hardware was done. */
329#define CFC_REG_CAM_INIT_DONE 0x10407c
330/* [RW 2] Interrupt mask register #0 read/write */
331#define CFC_REG_CFC_INT_MASK 0x104108
332/* [R 2] Interrupt register #0 read */
333#define CFC_REG_CFC_INT_STS 0x1040fc
334/* [RC 2] Interrupt register #0 read clear */
335#define CFC_REG_CFC_INT_STS_CLR 0x104100
336/* [RW 4] Parity mask register #0 read/write */
337#define CFC_REG_CFC_PRTY_MASK 0x104118
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ET		 338/* [R 4] Parity register #0 read */
339#define CFC_REG_CFC_PRTY_STS 0x10410c
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ET		 340/* [RW 21] CID cam access (21:1 - Data; alid - 0) */
341#define CFC_REG_CID_CAM 0x104800
342#define CFC_REG_CONTROL0 0x104028
343#define CFC_REG_DEBUG0 0x104050
344/* [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error
345 vector) whether the cfc should be disabled upon it */
346#define CFC_REG_DISABLE_ON_ERROR 0x104044
347/* [RC 14] CFC error vector. when the CFC detects an internal error it will
348 set one of these bits. the bit description can be found in CFC
349 specifications */
350#define CFC_REG_ERROR_VECTOR 0x10403c
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EG		 351/* [WB 93] LCID info ram access */
352#define CFC_REG_INFO_RAM 0x105000
353#define CFC_REG_INFO_RAM_SIZE 1024
a2fbb9ea 354#define CFC_REG_INIT_REG 0x10404c
8d9c5f34 355#define CFC_REG_INTERFACES 0x104058
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ET		 356/* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this
357 field allows changing the priorities of the weighted-round-robin arbiter
358 which selects which CFC load client should be served next */
359#define CFC_REG_LCREQ_WEIGHTS 0x104084
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YR		 360/* [RW 16] Link List ram access; data = {prev_lcid; ext_lcid} */
361#define CFC_REG_LINK_LIST 0x104c00
362#define CFC_REG_LINK_LIST_SIZE 256
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ET		 363/* [R 1] indication the initializing the link list by the hardware was done. */
364#define CFC_REG_LL_INIT_DONE 0x104074
365/* [R 9] Number of allocated LCIDs which are at empty state */
366#define CFC_REG_NUM_LCIDS_ALLOC 0x104020
367/* [R 9] Number of Arriving LCIDs in Link List Block */
368#define CFC_REG_NUM_LCIDS_ARRIVING 0x104004
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ET		 369/* [R 9] Number of Leaving LCIDs in Link List Block */
370#define CFC_REG_NUM_LCIDS_LEAVING 0x104018
371/* [RW 8] The event id for aggregated interrupt 0 */
372#define CSDM_REG_AGG_INT_EVENT_0 0xc2038
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YR		 373#define CSDM_REG_AGG_INT_EVENT_1 0xc203c
374#define CSDM_REG_AGG_INT_EVENT_10 0xc2060
375#define CSDM_REG_AGG_INT_EVENT_11 0xc2064
376#define CSDM_REG_AGG_INT_EVENT_12 0xc2068
377#define CSDM_REG_AGG_INT_EVENT_13 0xc206c
378#define CSDM_REG_AGG_INT_EVENT_14 0xc2070
379#define CSDM_REG_AGG_INT_EVENT_15 0xc2074
380#define CSDM_REG_AGG_INT_EVENT_16 0xc2078
381#define CSDM_REG_AGG_INT_EVENT_17 0xc207c
382#define CSDM_REG_AGG_INT_EVENT_18 0xc2080
383#define CSDM_REG_AGG_INT_EVENT_19 0xc2084
384#define CSDM_REG_AGG_INT_EVENT_2 0xc2040
385#define CSDM_REG_AGG_INT_EVENT_20 0xc2088
386#define CSDM_REG_AGG_INT_EVENT_21 0xc208c
387#define CSDM_REG_AGG_INT_EVENT_22 0xc2090
388#define CSDM_REG_AGG_INT_EVENT_23 0xc2094
389#define CSDM_REG_AGG_INT_EVENT_24 0xc2098
390#define CSDM_REG_AGG_INT_EVENT_25 0xc209c
391#define CSDM_REG_AGG_INT_EVENT_26 0xc20a0
392#define CSDM_REG_AGG_INT_EVENT_27 0xc20a4
393#define CSDM_REG_AGG_INT_EVENT_28 0xc20a8
394#define CSDM_REG_AGG_INT_EVENT_29 0xc20ac
395#define CSDM_REG_AGG_INT_EVENT_3 0xc2044
396#define CSDM_REG_AGG_INT_EVENT_30 0xc20b0
397#define CSDM_REG_AGG_INT_EVENT_31 0xc20b4
398#define CSDM_REG_AGG_INT_EVENT_4 0xc2048
399/* [RW 1] The T bit for aggregated interrupt 0 */
400#define CSDM_REG_AGG_INT_T_0 0xc20b8
401#define CSDM_REG_AGG_INT_T_1 0xc20bc
402#define CSDM_REG_AGG_INT_T_10 0xc20e0
403#define CSDM_REG_AGG_INT_T_11 0xc20e4
404#define CSDM_REG_AGG_INT_T_12 0xc20e8
405#define CSDM_REG_AGG_INT_T_13 0xc20ec
406#define CSDM_REG_AGG_INT_T_14 0xc20f0
407#define CSDM_REG_AGG_INT_T_15 0xc20f4
408#define CSDM_REG_AGG_INT_T_16 0xc20f8
409#define CSDM_REG_AGG_INT_T_17 0xc20fc
410#define CSDM_REG_AGG_INT_T_18 0xc2100
411#define CSDM_REG_AGG_INT_T_19 0xc2104
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ET		 412/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
413#define CSDM_REG_CFC_RSP_START_ADDR 0xc2008
414/* [RW 16] The maximum value of the competion counter #0 */
415#define CSDM_REG_CMP_COUNTER_MAX0 0xc201c
416/* [RW 16] The maximum value of the competion counter #1 */
417#define CSDM_REG_CMP_COUNTER_MAX1 0xc2020
418/* [RW 16] The maximum value of the competion counter #2 */
419#define CSDM_REG_CMP_COUNTER_MAX2 0xc2024
420/* [RW 16] The maximum value of the competion counter #3 */
421#define CSDM_REG_CMP_COUNTER_MAX3 0xc2028
422/* [RW 13] The start address in the internal RAM for the completion
423 counters. */
424#define CSDM_REG_CMP_COUNTER_START_ADDR 0xc200c
425/* [RW 32] Interrupt mask register #0 read/write */
426#define CSDM_REG_CSDM_INT_MASK_0 0xc229c
427#define CSDM_REG_CSDM_INT_MASK_1 0xc22ac
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YR		 428/* [R 32] Interrupt register #0 read */
429#define CSDM_REG_CSDM_INT_STS_0 0xc2290
430#define CSDM_REG_CSDM_INT_STS_1 0xc22a0
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ET		 431/* [RW 11] Parity mask register #0 read/write */
432#define CSDM_REG_CSDM_PRTY_MASK 0xc22bc
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ET		 433/* [R 11] Parity register #0 read */
434#define CSDM_REG_CSDM_PRTY_STS 0xc22b0
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ET		 435#define CSDM_REG_ENABLE_IN1 0xc2238
436#define CSDM_REG_ENABLE_IN2 0xc223c
437#define CSDM_REG_ENABLE_OUT1 0xc2240
438#define CSDM_REG_ENABLE_OUT2 0xc2244
439/* [RW 4] The initial number of messages that can be sent to the pxp control
440 interface without receiving any ACK. */
441#define CSDM_REG_INIT_CREDIT_PXP_CTRL 0xc24bc
442/* [ST 32] The number of ACK after placement messages received */
443#define CSDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc227c
444/* [ST 32] The number of packet end messages received from the parser */
445#define CSDM_REG_NUM_OF_PKT_END_MSG 0xc2274
446/* [ST 32] The number of requests received from the pxp async if */
447#define CSDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc2278
448/* [ST 32] The number of commands received in queue 0 */
449#define CSDM_REG_NUM_OF_Q0_CMD 0xc2248
450/* [ST 32] The number of commands received in queue 10 */
451#define CSDM_REG_NUM_OF_Q10_CMD 0xc226c
452/* [ST 32] The number of commands received in queue 11 */
453#define CSDM_REG_NUM_OF_Q11_CMD 0xc2270
454/* [ST 32] The number of commands received in queue 1 */
455#define CSDM_REG_NUM_OF_Q1_CMD 0xc224c
456/* [ST 32] The number of commands received in queue 3 */
457#define CSDM_REG_NUM_OF_Q3_CMD 0xc2250
458/* [ST 32] The number of commands received in queue 4 */
459#define CSDM_REG_NUM_OF_Q4_CMD 0xc2254
460/* [ST 32] The number of commands received in queue 5 */
461#define CSDM_REG_NUM_OF_Q5_CMD 0xc2258
462/* [ST 32] The number of commands received in queue 6 */
463#define CSDM_REG_NUM_OF_Q6_CMD 0xc225c
464/* [ST 32] The number of commands received in queue 7 */
465#define CSDM_REG_NUM_OF_Q7_CMD 0xc2260
466/* [ST 32] The number of commands received in queue 8 */
467#define CSDM_REG_NUM_OF_Q8_CMD 0xc2264
468/* [ST 32] The number of commands received in queue 9 */
469#define CSDM_REG_NUM_OF_Q9_CMD 0xc2268
470/* [RW 13] The start address in the internal RAM for queue counters */
471#define CSDM_REG_Q_COUNTER_START_ADDR 0xc2010
472/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
473#define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548
474/* [R 1] parser fifo empty in sdm_sync block */
475#define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550
476/* [R 1] parser serial fifo empty in sdm_sync block */
477#define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558
478/* [RW 32] Tick for timer counter. Applicable only when
479 ~csdm_registers_timer_tick_enable.timer_tick_enable =1 */
480#define CSDM_REG_TIMER_TICK 0xc2000
481/* [RW 5] The number of time_slots in the arbitration cycle */
482#define CSEM_REG_ARB_CYCLE_SIZE 0x200034
483/* [RW 3] The source that is associated with arbitration element 0. Source
484 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
485 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
486#define CSEM_REG_ARB_ELEMENT0 0x200020
487/* [RW 3] The source that is associated with arbitration element 1. Source
488 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
489 sleeping thread with priority 1; 4- sleeping thread with priority 2.
490 Could not be equal to register ~csem_registers_arb_element0.arb_element0 */
491#define CSEM_REG_ARB_ELEMENT1 0x200024
492/* [RW 3] The source that is associated with arbitration element 2. Source
493 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
494 sleeping thread with priority 1; 4- sleeping thread with priority 2.
495 Could not be equal to register ~csem_registers_arb_element0.arb_element0
496 and ~csem_registers_arb_element1.arb_element1 */
497#define CSEM_REG_ARB_ELEMENT2 0x200028
498/* [RW 3] The source that is associated with arbitration element 3. Source
499 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
500 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
501 not be equal to register ~csem_registers_arb_element0.arb_element0 and
502 ~csem_registers_arb_element1.arb_element1 and
503 ~csem_registers_arb_element2.arb_element2 */
504#define CSEM_REG_ARB_ELEMENT3 0x20002c
505/* [RW 3] The source that is associated with arbitration element 4. Source
506 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
507 sleeping thread with priority 1; 4- sleeping thread with priority 2.
508 Could not be equal to register ~csem_registers_arb_element0.arb_element0
509 and ~csem_registers_arb_element1.arb_element1 and
510 ~csem_registers_arb_element2.arb_element2 and
511 ~csem_registers_arb_element3.arb_element3 */
512#define CSEM_REG_ARB_ELEMENT4 0x200030
513/* [RW 32] Interrupt mask register #0 read/write */
514#define CSEM_REG_CSEM_INT_MASK_0 0x200110
515#define CSEM_REG_CSEM_INT_MASK_1 0x200120
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YR		 516/* [R 32] Interrupt register #0 read */
517#define CSEM_REG_CSEM_INT_STS_0 0x200104
518#define CSEM_REG_CSEM_INT_STS_1 0x200114
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ET		 519/* [RW 32] Parity mask register #0 read/write */
520#define CSEM_REG_CSEM_PRTY_MASK_0 0x200130
521#define CSEM_REG_CSEM_PRTY_MASK_1 0x200140
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ET		 522/* [R 32] Parity register #0 read */
523#define CSEM_REG_CSEM_PRTY_STS_0 0x200124
524#define CSEM_REG_CSEM_PRTY_STS_1 0x200134
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ET		 525#define CSEM_REG_ENABLE_IN 0x2000a4
526#define CSEM_REG_ENABLE_OUT 0x2000a8
527/* [RW 32] This address space contains all registers and memories that are
528 placed in SEM_FAST block. The SEM_FAST registers are described in
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YR		 529 appendix B. In order to access the sem_fast registers the base address
530 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
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ET		 531#define CSEM_REG_FAST_MEMORY 0x220000
532/* [RW 1] Disables input messages from FIC0 May be updated during run_time
533 by the microcode */
534#define CSEM_REG_FIC0_DISABLE 0x200224
535/* [RW 1] Disables input messages from FIC1 May be updated during run_time
536 by the microcode */
537#define CSEM_REG_FIC1_DISABLE 0x200234
538/* [RW 15] Interrupt table Read and write access to it is not possible in
539 the middle of the work */
540#define CSEM_REG_INT_TABLE 0x200400
541/* [ST 24] Statistics register. The number of messages that entered through
542 FIC0 */
543#define CSEM_REG_MSG_NUM_FIC0 0x200000
544/* [ST 24] Statistics register. The number of messages that entered through
545 FIC1 */
546#define CSEM_REG_MSG_NUM_FIC1 0x200004
547/* [ST 24] Statistics register. The number of messages that were sent to
548 FOC0 */
549#define CSEM_REG_MSG_NUM_FOC0 0x200008
550/* [ST 24] Statistics register. The number of messages that were sent to
551 FOC1 */
552#define CSEM_REG_MSG_NUM_FOC1 0x20000c
553/* [ST 24] Statistics register. The number of messages that were sent to
554 FOC2 */
555#define CSEM_REG_MSG_NUM_FOC2 0x200010
556/* [ST 24] Statistics register. The number of messages that were sent to
557 FOC3 */
558#define CSEM_REG_MSG_NUM_FOC3 0x200014
559/* [RW 1] Disables input messages from the passive buffer May be updated
560 during run_time by the microcode */
561#define CSEM_REG_PAS_DISABLE 0x20024c
562/* [WB 128] Debug only. Passive buffer memory */
563#define CSEM_REG_PASSIVE_BUFFER 0x202000
564/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
565#define CSEM_REG_PRAM 0x240000
566/* [R 16] Valid sleeping threads indication have bit per thread */
567#define CSEM_REG_SLEEP_THREADS_VALID 0x20026c
568/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
569#define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0
570/* [RW 16] List of free threads . There is a bit per thread. */
571#define CSEM_REG_THREADS_LIST 0x2002e4
572/* [RW 3] The arbitration scheme of time_slot 0 */
573#define CSEM_REG_TS_0_AS 0x200038
574/* [RW 3] The arbitration scheme of time_slot 10 */
575#define CSEM_REG_TS_10_AS 0x200060
576/* [RW 3] The arbitration scheme of time_slot 11 */
577#define CSEM_REG_TS_11_AS 0x200064
578/* [RW 3] The arbitration scheme of time_slot 12 */
579#define CSEM_REG_TS_12_AS 0x200068
580/* [RW 3] The arbitration scheme of time_slot 13 */
581#define CSEM_REG_TS_13_AS 0x20006c
582/* [RW 3] The arbitration scheme of time_slot 14 */
583#define CSEM_REG_TS_14_AS 0x200070
584/* [RW 3] The arbitration scheme of time_slot 15 */
585#define CSEM_REG_TS_15_AS 0x200074
586/* [RW 3] The arbitration scheme of time_slot 16 */
587#define CSEM_REG_TS_16_AS 0x200078
588/* [RW 3] The arbitration scheme of time_slot 17 */
589#define CSEM_REG_TS_17_AS 0x20007c
590/* [RW 3] The arbitration scheme of time_slot 18 */
591#define CSEM_REG_TS_18_AS 0x200080
592/* [RW 3] The arbitration scheme of time_slot 1 */
593#define CSEM_REG_TS_1_AS 0x20003c
594/* [RW 3] The arbitration scheme of time_slot 2 */
595#define CSEM_REG_TS_2_AS 0x200040
596/* [RW 3] The arbitration scheme of time_slot 3 */
597#define CSEM_REG_TS_3_AS 0x200044
598/* [RW 3] The arbitration scheme of time_slot 4 */
599#define CSEM_REG_TS_4_AS 0x200048
600/* [RW 3] The arbitration scheme of time_slot 5 */
601#define CSEM_REG_TS_5_AS 0x20004c
602/* [RW 3] The arbitration scheme of time_slot 6 */
603#define CSEM_REG_TS_6_AS 0x200050
604/* [RW 3] The arbitration scheme of time_slot 7 */
605#define CSEM_REG_TS_7_AS 0x200054
606/* [RW 3] The arbitration scheme of time_slot 8 */
607#define CSEM_REG_TS_8_AS 0x200058
608/* [RW 3] The arbitration scheme of time_slot 9 */
609#define CSEM_REG_TS_9_AS 0x20005c
610/* [RW 1] Parity mask register #0 read/write */
611#define DBG_REG_DBG_PRTY_MASK 0xc0a8
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ET		 612/* [R 1] Parity register #0 read */
613#define DBG_REG_DBG_PRTY_STS 0xc09c
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ET		 614/* [RW 32] Commands memory. The address to command X; row Y is to calculated
615 as 14*X+Y. */
616#define DMAE_REG_CMD_MEM 0x102400
34f80b04 617#define DMAE_REG_CMD_MEM_SIZE 224
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ET		 618/* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c
619 initial value is all ones. */
620#define DMAE_REG_CRC16C_INIT 0x10201c
621/* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the
622 CRC-16 T10 initial value is all ones. */
623#define DMAE_REG_CRC16T10_INIT 0x102020
624/* [RW 2] Interrupt mask register #0 read/write */
625#define DMAE_REG_DMAE_INT_MASK 0x102054
626/* [RW 4] Parity mask register #0 read/write */
627#define DMAE_REG_DMAE_PRTY_MASK 0x102064
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ET		 628/* [R 4] Parity register #0 read */
629#define DMAE_REG_DMAE_PRTY_STS 0x102058
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ET		 630/* [RW 1] Command 0 go. */
631#define DMAE_REG_GO_C0 0x102080
632/* [RW 1] Command 1 go. */
633#define DMAE_REG_GO_C1 0x102084
634/* [RW 1] Command 10 go. */
635#define DMAE_REG_GO_C10 0x102088
636#define DMAE_REG_GO_C10_SIZE 1
637/* [RW 1] Command 11 go. */
638#define DMAE_REG_GO_C11 0x10208c
639#define DMAE_REG_GO_C11_SIZE 1
640/* [RW 1] Command 12 go. */
641#define DMAE_REG_GO_C12 0x102090
642#define DMAE_REG_GO_C12_SIZE 1
643/* [RW 1] Command 13 go. */
644#define DMAE_REG_GO_C13 0x102094
645#define DMAE_REG_GO_C13_SIZE 1
646/* [RW 1] Command 14 go. */
647#define DMAE_REG_GO_C14 0x102098
648#define DMAE_REG_GO_C14_SIZE 1
649/* [RW 1] Command 15 go. */
650#define DMAE_REG_GO_C15 0x10209c
651#define DMAE_REG_GO_C15_SIZE 1
652/* [RW 1] Command 10 go. */
653#define DMAE_REG_GO_C10 0x102088
654/* [RW 1] Command 11 go. */
655#define DMAE_REG_GO_C11 0x10208c
656/* [RW 1] Command 12 go. */
657#define DMAE_REG_GO_C12 0x102090
658/* [RW 1] Command 13 go. */
659#define DMAE_REG_GO_C13 0x102094
660/* [RW 1] Command 14 go. */
661#define DMAE_REG_GO_C14 0x102098
662/* [RW 1] Command 15 go. */
663#define DMAE_REG_GO_C15 0x10209c
664/* [RW 1] Command 2 go. */
665#define DMAE_REG_GO_C2 0x1020a0
666/* [RW 1] Command 3 go. */
667#define DMAE_REG_GO_C3 0x1020a4
668/* [RW 1] Command 4 go. */
669#define DMAE_REG_GO_C4 0x1020a8
670/* [RW 1] Command 5 go. */
671#define DMAE_REG_GO_C5 0x1020ac
672/* [RW 1] Command 6 go. */
673#define DMAE_REG_GO_C6 0x1020b0
674/* [RW 1] Command 7 go. */
675#define DMAE_REG_GO_C7 0x1020b4
676/* [RW 1] Command 8 go. */
677#define DMAE_REG_GO_C8 0x1020b8
678/* [RW 1] Command 9 go. */
679#define DMAE_REG_GO_C9 0x1020bc
680/* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge
681 input is disregarded; valid is deasserted; all other signals are treated
682 as usual; if 1 - normal activity. */
683#define DMAE_REG_GRC_IFEN 0x102008
684/* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the
685 acknowledge input is disregarded; valid is deasserted; full is asserted;
686 all other signals are treated as usual; if 1 - normal activity. */
687#define DMAE_REG_PCI_IFEN 0x102004
688/* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the
689 initial value to the credit counter; related to the address. Read returns
690 the current value of the counter. */
691#define DMAE_REG_PXP_REQ_INIT_CRD 0x1020c0
692/* [RW 8] Aggregation command. */
693#define DORQ_REG_AGG_CMD0 0x170060
694/* [RW 8] Aggregation command. */
695#define DORQ_REG_AGG_CMD1 0x170064
696/* [RW 8] Aggregation command. */
697#define DORQ_REG_AGG_CMD2 0x170068
698/* [RW 8] Aggregation command. */
699#define DORQ_REG_AGG_CMD3 0x17006c
700/* [RW 28] UCM Header. */
701#define DORQ_REG_CMHEAD_RX 0x170050
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YR		 702/* [RW 32] Doorbell address for RBC doorbells (function 0). */
703#define DORQ_REG_DB_ADDR0 0x17008c
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ET		 704/* [RW 5] Interrupt mask register #0 read/write */
705#define DORQ_REG_DORQ_INT_MASK 0x170180
706/* [R 5] Interrupt register #0 read */
707#define DORQ_REG_DORQ_INT_STS 0x170174
708/* [RC 5] Interrupt register #0 read clear */
709#define DORQ_REG_DORQ_INT_STS_CLR 0x170178
710/* [RW 2] Parity mask register #0 read/write */
711#define DORQ_REG_DORQ_PRTY_MASK 0x170190
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ET		 712/* [R 2] Parity register #0 read */
713#define DORQ_REG_DORQ_PRTY_STS 0x170184
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ET		 714/* [RW 8] The address to write the DPM CID to STORM. */
715#define DORQ_REG_DPM_CID_ADDR 0x170044
716/* [RW 5] The DPM mode CID extraction offset. */
717#define DORQ_REG_DPM_CID_OFST 0x170030
718/* [RW 12] The threshold of the DQ FIFO to send the almost full interrupt. */
719#define DORQ_REG_DQ_FIFO_AFULL_TH 0x17007c
720/* [RW 12] The threshold of the DQ FIFO to send the full interrupt. */
721#define DORQ_REG_DQ_FIFO_FULL_TH 0x170078
722/* [R 13] Current value of the DQ FIFO fill level according to following
723 pointer. The range is 0 - 256 FIFO rows; where each row stands for the
724 doorbell. */
725#define DORQ_REG_DQ_FILL_LVLF 0x1700a4
726/* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or
727 equal to full threshold; reset on full clear. */
728#define DORQ_REG_DQ_FULL_ST 0x1700c0
729/* [RW 28] The value sent to CM header in the case of CFC load error. */
730#define DORQ_REG_ERR_CMHEAD 0x170058
731#define DORQ_REG_IF_EN 0x170004
732#define DORQ_REG_MODE_ACT 0x170008
733/* [RW 5] The normal mode CID extraction offset. */
734#define DORQ_REG_NORM_CID_OFST 0x17002c
735/* [RW 28] TCM Header when only TCP context is loaded. */
736#define DORQ_REG_NORM_CMHEAD_TX 0x17004c
737/* [RW 3] The number of simultaneous outstanding requests to Context Fetch
738 Interface. */
739#define DORQ_REG_OUTST_REQ 0x17003c
740#define DORQ_REG_REGN 0x170038
741/* [R 4] Current value of response A counter credit. Initial credit is
742 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
743 register. */
744#define DORQ_REG_RSPA_CRD_CNT 0x1700ac
745/* [R 4] Current value of response B counter credit. Initial credit is
746 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
747 register. */
748#define DORQ_REG_RSPB_CRD_CNT 0x1700b0
749/* [RW 4] The initial credit at the Doorbell Response Interface. The write
750 writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The
751 read reads this written value. */
752#define DORQ_REG_RSP_INIT_CRD 0x170048
753/* [RW 4] Initial activity counter value on the load request; when the
754 shortcut is done. */
755#define DORQ_REG_SHRT_ACT_CNT 0x170070
756/* [RW 28] TCM Header when both ULP and TCP context is loaded. */
757#define DORQ_REG_SHRT_CMHEAD 0x170054
758#define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4)
759#define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3)
8badd27a 760#define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1<<7)
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ET		 761#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2)
762#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1)
763#define HC_REG_AGG_INT_0 0x108050
764#define HC_REG_AGG_INT_1 0x108054
a2fbb9ea 765#define HC_REG_ATTN_BIT 0x108120
a2fbb9ea 766#define HC_REG_ATTN_IDX 0x108100
a2fbb9ea 767#define HC_REG_ATTN_MSG0_ADDR_L 0x108018
a2fbb9ea 768#define HC_REG_ATTN_MSG1_ADDR_L 0x108020
a2fbb9ea 769#define HC_REG_ATTN_NUM_P0 0x108038
a2fbb9ea 770#define HC_REG_ATTN_NUM_P1 0x10803c
5c862848 771#define HC_REG_COMMAND_REG 0x108180
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ET		 772#define HC_REG_CONFIG_0 0x108000
773#define HC_REG_CONFIG_1 0x108004
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YR		 774#define HC_REG_FUNC_NUM_P0 0x1080ac
775#define HC_REG_FUNC_NUM_P1 0x1080b0
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ET		 776/* [RW 3] Parity mask register #0 read/write */
777#define HC_REG_HC_PRTY_MASK 0x1080a0
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ET		 778/* [R 3] Parity register #0 read */
779#define HC_REG_HC_PRTY_STS 0x108094
a2fbb9ea 780#define HC_REG_INT_MASK 0x108108
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ET		 781#define HC_REG_LEADING_EDGE_0 0x108040
782#define HC_REG_LEADING_EDGE_1 0x108048
a2fbb9ea 783#define HC_REG_P0_PROD_CONS 0x108200
a2fbb9ea 784#define HC_REG_P1_PROD_CONS 0x108400
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ET		 785#define HC_REG_PBA_COMMAND 0x108140
786#define HC_REG_PCI_CONFIG_0 0x108010
787#define HC_REG_PCI_CONFIG_1 0x108014
a2fbb9ea 788#define HC_REG_STATISTIC_COUNTERS 0x109000
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ET		 789#define HC_REG_TRAILING_EDGE_0 0x108044
790#define HC_REG_TRAILING_EDGE_1 0x10804c
791#define HC_REG_UC_RAM_ADDR_0 0x108028
792#define HC_REG_UC_RAM_ADDR_1 0x108030
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ET		 793#define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068
794#define HC_REG_VQID_0 0x108008
795#define HC_REG_VQID_1 0x10800c
796#define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x86424
797#define MCP_REG_MCPR_NVM_ADDR 0x8640c
798#define MCP_REG_MCPR_NVM_CFG4 0x8642c
799#define MCP_REG_MCPR_NVM_COMMAND 0x86400
800#define MCP_REG_MCPR_NVM_READ 0x86410
801#define MCP_REG_MCPR_NVM_SW_ARB 0x86420
802#define MCP_REG_MCPR_NVM_WRITE 0x86408
803#define MCP_REG_MCPR_NVM_WRITE1 0x86428
804#define MCP_REG_MCPR_SCRATCH 0xa0000
805/* [R 32] read first 32 bit after inversion of function 0. mapped as
806 follows: [0] NIG attention for function0; [1] NIG attention for
807 function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp;
808 [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9]
809 GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE
810 glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0;
811 [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16]
812 MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB
813 Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw
814 interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity
815 error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw
816 interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF
817 Parity error; [31] PBF Hw interrupt; */
818#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 0xa42c
819#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 0xa430
820/* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0]
821 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
822 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
823 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
824 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
825 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
826 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
827 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
828 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
829 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
830 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
831 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
832 interrupt; */
833#define MISC_REG_AEU_AFTER_INVERT_1_MCP 0xa434
834/* [R 32] read second 32 bit after inversion of function 0. mapped as
835 follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
836 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
837 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
838 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
839 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
840 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
841 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
842 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
843 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
844 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
845 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
846 interrupt; */
847#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 0xa438
848#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 0xa43c
849/* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0]
850 PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error;
851 [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt;
852 [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9]
853 XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
854 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
855 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
856 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
857 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
858 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
859 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
860 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
861#define MISC_REG_AEU_AFTER_INVERT_2_MCP 0xa440
862/* [R 32] read third 32 bit after inversion of function 0. mapped as
863 follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity
864 error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5]
865 PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
866 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
867 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
868 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
869 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
870 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
871 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
872 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
873 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
874 attn1; */
875#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 0xa444
876#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 0xa448
877/* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0]
878 CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP
879 Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient
880 Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity
881 error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw
882 interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14]
883 MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17]
884 Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW
885 timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3
886 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1
887 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW
888 timers attn_4 func1; [30] General attn0; [31] General attn1; */
889#define MISC_REG_AEU_AFTER_INVERT_3_MCP 0xa44c
890/* [R 32] read fourth 32 bit after inversion of function 0. mapped as
891 follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
892 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
893 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
894 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
895 [14] General attn16; [15] General attn17; [16] General attn18; [17]
896 General attn19; [18] General attn20; [19] General attn21; [20] Main power
897 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
898 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
899 Latched timeout attention; [27] GRC Latched reserved access attention;
900 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
901 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
902#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 0xa450
903#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 0xa454
904/* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0]
905 General attn2; [1] General attn3; [2] General attn4; [3] General attn5;
906 [4] General attn6; [5] General attn7; [6] General attn8; [7] General
907 attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11]
908 General attn13; [12] General attn14; [13] General attn15; [14] General
909 attn16; [15] General attn17; [16] General attn18; [17] General attn19;
910 [18] General attn20; [19] General attn21; [20] Main power interrupt; [21]
911 RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24]
912 RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout
913 attention; [27] GRC Latched reserved access attention; [28] MCP Latched
914 rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched
915 ump_tx_parity; [31] MCP Latched scpad_parity; */
916#define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458
c18487ee 917/* [W 14] write to this register results with the clear of the latched
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ET		 918 signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in
919 d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP
920 latch; one in d5 clears GRC Latched timeout attention; one in d6 clears
921 GRC Latched reserved access attention; one in d7 clears Latched
922 rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears
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YR		 923 Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both
924 ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears
925 pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read
926 from this register return zero */
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ET		 927#define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c
928/* [RW 32] first 32b for enabling the output for function 0 output0. mapped
929 as follows: [0] NIG attention for function0; [1] NIG attention for
930 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
931 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
932 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
933 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
934 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
935 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
936 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
937 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
938 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
939 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
940 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
941#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c
942#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c
c18487ee 943#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 0xa08c
a2fbb9ea 944#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 0xa09c
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YR		 945#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5 0xa0bc
946#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6 0xa0cc
947#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7 0xa0dc
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ET		 948/* [RW 32] first 32b for enabling the output for function 1 output0. mapped
949 as follows: [0] NIG attention for function0; [1] NIG attention for
950 function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function
951 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
952 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
953 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
954 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
955 SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X
956 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
957 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
958 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
959 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
960 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
961#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c
962#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c
c18487ee 963#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 0xa12c
a2fbb9ea 964#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 0xa13c
c18487ee
YR		 965#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5 0xa15c
966#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6 0xa16c
967#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7 0xa17c
968/* [RW 32] first 32b for enabling the output for close the gate nig. mapped
969 as follows: [0] NIG attention for function0; [1] NIG attention for
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ET		 970 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
971 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
972 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
973 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
974 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
975 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
976 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
977 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
978 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
979 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
980 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
981#define MISC_REG_AEU_ENABLE1_NIG_0 0xa0ec
982#define MISC_REG_AEU_ENABLE1_NIG_1 0xa18c
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YR		 983/* [RW 32] first 32b for enabling the output for close the gate pxp. mapped
984 as follows: [0] NIG attention for function0; [1] NIG attention for
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ET		 985 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
986 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
987 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
988 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
989 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
990 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
991 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
992 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
993 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
994 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
995 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
996#define MISC_REG_AEU_ENABLE1_PXP_0 0xa0fc
997#define MISC_REG_AEU_ENABLE1_PXP_1 0xa19c
998/* [RW 32] second 32b for enabling the output for function 0 output0. mapped
999 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1000 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1001 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1002 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1003 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1004 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1005 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1006 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1007 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1008 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1009 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1010 interrupt; */
1011#define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0 0xa070
1012#define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1 0xa080
1013/* [RW 32] second 32b for enabling the output for function 1 output0. mapped
1014 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1015 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1016 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1017 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1018 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1019 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1020 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1021 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1022 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1023 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1024 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1025 interrupt; */
1026#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 0xa110
1027#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 0xa120
c18487ee
YR		 1028/* [RW 32] second 32b for enabling the output for close the gate nig. mapped
1029 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1030 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1031 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1032 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1033 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1034 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1035 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1036 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1037 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1038 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1039 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1040 interrupt; */
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ET		 1041#define MISC_REG_AEU_ENABLE2_NIG_0 0xa0f0
1042#define MISC_REG_AEU_ENABLE2_NIG_1 0xa190
c18487ee
YR		 1043/* [RW 32] second 32b for enabling the output for close the gate pxp. mapped
1044 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1045 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1046 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1047 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1048 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1049 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1050 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1051 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1052 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1053 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1054 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1055 interrupt; */
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ET		 1056#define MISC_REG_AEU_ENABLE2_PXP_0 0xa100
1057#define MISC_REG_AEU_ENABLE2_PXP_1 0xa1a0
1058/* [RW 32] third 32b for enabling the output for function 0 output0. mapped
1059 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1060 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1061 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1062 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1063 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1064 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1065 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1066 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1067 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1068 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1069 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1070 attn1; */
1071#define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0 0xa074
1072#define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1 0xa084
1073/* [RW 32] third 32b for enabling the output for function 1 output0. mapped
1074 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1075 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1076 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1077 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1078 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1079 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1080 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1081 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1082 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1083 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1084 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1085 attn1; */
1086#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 0xa114
1087#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 0xa124
c18487ee
YR		 1088/* [RW 32] third 32b for enabling the output for close the gate nig. mapped
1089 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1090 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1091 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1092 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1093 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1094 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1095 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1096 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1097 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1098 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1099 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1100 attn1; */
a2fbb9ea
ET		 1101#define MISC_REG_AEU_ENABLE3_NIG_0 0xa0f4
1102#define MISC_REG_AEU_ENABLE3_NIG_1 0xa194
c18487ee
YR		 1103/* [RW 32] third 32b for enabling the output for close the gate pxp. mapped
1104 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1105 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1106 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1107 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1108 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1109 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1110 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1111 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1112 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1113 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1114 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1115 attn1; */
a2fbb9ea
ET		 1116#define MISC_REG_AEU_ENABLE3_PXP_0 0xa104
1117#define MISC_REG_AEU_ENABLE3_PXP_1 0xa1a4
1118/* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped
1119 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1120 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1121 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1122 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1123 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1124 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1125 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1126 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1127 Latched timeout attention; [27] GRC Latched reserved access attention;
1128 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1129 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1130#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078
1131#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 0xa098
c18487ee
YR		 1132#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4 0xa0b8
1133#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5 0xa0c8
1134#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6 0xa0d8
1135#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7 0xa0e8
a2fbb9ea
ET		 1136/* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped
1137 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1138 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1139 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1140 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1141 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1142 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1143 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1144 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1145 Latched timeout attention; [27] GRC Latched reserved access attention;
1146 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1147 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1148#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118
1149#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 0xa138
c18487ee
YR		 1150#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4 0xa158
1151#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5 0xa168
1152#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6 0xa178
1153#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7 0xa188
1154/* [RW 32] fourth 32b for enabling the output for close the gate nig.mapped
1155 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1156 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1157 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1158 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1159 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1160 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1161 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1162 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1163 Latched timeout attention; [27] GRC Latched reserved access attention;
1164 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1165 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
a2fbb9ea
ET		 1166#define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8
1167#define MISC_REG_AEU_ENABLE4_NIG_1 0xa198
c18487ee
YR		 1168/* [RW 32] fourth 32b for enabling the output for close the gate pxp.mapped
1169 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1170 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1171 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1172 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1173 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1174 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1175 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1176 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1177 Latched timeout attention; [27] GRC Latched reserved access attention;
1178 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1179 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
a2fbb9ea
ET		 1180#define MISC_REG_AEU_ENABLE4_PXP_0 0xa108
1181#define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8
1182/* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu
1183 128 bit vector */
1184#define MISC_REG_AEU_GENERAL_ATTN_0 0xa000
1185#define MISC_REG_AEU_GENERAL_ATTN_1 0xa004
1186#define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
1187#define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
1188#define MISC_REG_AEU_GENERAL_ATTN_12 0xa030
1189#define MISC_REG_AEU_GENERAL_ATTN_13 0xa034
1190#define MISC_REG_AEU_GENERAL_ATTN_14 0xa038
1191#define MISC_REG_AEU_GENERAL_ATTN_15 0xa03c
1192#define MISC_REG_AEU_GENERAL_ATTN_16 0xa040
1193#define MISC_REG_AEU_GENERAL_ATTN_17 0xa044
1194#define MISC_REG_AEU_GENERAL_ATTN_18 0xa048
1195#define MISC_REG_AEU_GENERAL_ATTN_19 0xa04c
f1410647 1196#define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
a2fbb9ea 1197#define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
c18487ee 1198#define MISC_REG_AEU_GENERAL_ATTN_12 0xa030
a2fbb9ea
ET		 1199#define MISC_REG_AEU_GENERAL_ATTN_2 0xa008
1200#define MISC_REG_AEU_GENERAL_ATTN_20 0xa050
1201#define MISC_REG_AEU_GENERAL_ATTN_21 0xa054
1202#define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c
1203#define MISC_REG_AEU_GENERAL_ATTN_4 0xa010
1204#define MISC_REG_AEU_GENERAL_ATTN_5 0xa014
1205#define MISC_REG_AEU_GENERAL_ATTN_6 0xa018
f1410647
ET		 1206#define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c
1207#define MISC_REG_AEU_GENERAL_ATTN_8 0xa020
1208#define MISC_REG_AEU_GENERAL_ATTN_9 0xa024
c18487ee 1209#define MISC_REG_AEU_GENERAL_MASK 0xa61c
a2fbb9ea
ET		 1210/* [RW 32] first 32b for inverting the input for function 0; for each bit:
1211 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for
1212 function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp;
1213 [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1;
1214 [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1215 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1216 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1217 SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication
1218 for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS
1219 Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw
1220 interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM
1221 Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI
1222 Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1223#define MISC_REG_AEU_INVERTER_1_FUNC_0 0xa22c
1224#define MISC_REG_AEU_INVERTER_1_FUNC_1 0xa23c
1225/* [RW 32] second 32b for inverting the input for function 0; for each bit:
1226 0= do not invert; 1= invert. mapped as follows: [0] PBClient Parity
1227 error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw
1228 interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM
1229 Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw
1230 interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
1231 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
1232 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
1233 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
1234 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
1235 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
1236 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
1237 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
1238#define MISC_REG_AEU_INVERTER_2_FUNC_0 0xa230
1239#define MISC_REG_AEU_INVERTER_2_FUNC_1 0xa240
1240/* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0;
c18487ee 1241 [9:8] = raserved. Zero = mask; one = unmask */
a2fbb9ea
ET		 1242#define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060
1243#define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064
c18487ee
YR		 1244/* [RW 1] If set a system kill occurred */
1245#define MISC_REG_AEU_SYS_KILL_OCCURRED 0xa610
1246/* [RW 32] Represent the status of the input vector to the AEU when a system
1247 kill occurred. The register is reset in por reset. Mapped as follows: [0]
1248 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
1249 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
1250 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
1251 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
1252 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
1253 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
1254 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
1255 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
1256 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
1257 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
1258 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
1259 interrupt; */
1260#define MISC_REG_AEU_SYS_KILL_STATUS_0 0xa600
1261#define MISC_REG_AEU_SYS_KILL_STATUS_1 0xa604
1262#define MISC_REG_AEU_SYS_KILL_STATUS_2 0xa608
1263#define MISC_REG_AEU_SYS_KILL_STATUS_3 0xa60c
a2fbb9ea
ET		 1264/* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1
1265 Port. */
1266#define MISC_REG_BOND_ID 0xa400
1267/* [R 8] These bits indicate the metal revision of the chip. This value
1268 starts at 0x00 for each all-layer tape-out and increments by one for each
1269 tape-out. */
1270#define MISC_REG_CHIP_METAL 0xa404
1271/* [R 16] These bits indicate the part number for the chip. */
1272#define MISC_REG_CHIP_NUM 0xa408
1273/* [R 4] These bits indicate the base revision of the chip. This value
1274 starts at 0x0 for the A0 tape-out and increments by one for each
1275 all-layer tape-out. */
1276#define MISC_REG_CHIP_REV 0xa40c
c18487ee
YR		 1277/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1278 32 clients. Each client can be controlled by one driver only. One in each
1279 bit represent that this driver control the appropriate client (Ex: bit 5
1280 is set means this driver control client number 5). addr1 = set; addr0 =
1281 clear; read from both addresses will give the same result = status. write
1282 to address 1 will set a request to control all the clients that their
1283 appropriate bit (in the write command) is set. if the client is free (the
1284 appropriate bit in all the other drivers is clear) one will be written to
1285 that driver register; if the client isn't free the bit will remain zero.
1286 if the appropriate bit is set (the driver request to gain control on a
1287 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1288 interrupt will be asserted). write to address 0 will set a request to
1289 free all the clients that their appropriate bit (in the write command) is
1290 set. if the appropriate bit is clear (the driver request to free a client
1291 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1292 be asserted). */
1293#define MISC_REG_DRIVER_CONTROL_10 0xa3e0
1294#define MISC_REG_DRIVER_CONTROL_10_SIZE 2
1295/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1296 32 clients. Each client can be controlled by one driver only. One in each
1297 bit represent that this driver control the appropriate client (Ex: bit 5
1298 is set means this driver control client number 5). addr1 = set; addr0 =
1299 clear; read from both addresses will give the same result = status. write
1300 to address 1 will set a request to control all the clients that their
1301 appropriate bit (in the write command) is set. if the client is free (the
1302 appropriate bit in all the other drivers is clear) one will be written to
1303 that driver register; if the client isn't free the bit will remain zero.
1304 if the appropriate bit is set (the driver request to gain control on a
1305 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1306 interrupt will be asserted). write to address 0 will set a request to
1307 free all the clients that their appropriate bit (in the write command) is
1308 set. if the appropriate bit is clear (the driver request to free a client
1309 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1310 be asserted). */
1311#define MISC_REG_DRIVER_CONTROL_11 0xa3e8
1312#define MISC_REG_DRIVER_CONTROL_11_SIZE 2
1313/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1314 32 clients. Each client can be controlled by one driver only. One in each
1315 bit represent that this driver control the appropriate client (Ex: bit 5
1316 is set means this driver control client number 5). addr1 = set; addr0 =
1317 clear; read from both addresses will give the same result = status. write
1318 to address 1 will set a request to control all the clients that their
1319 appropriate bit (in the write command) is set. if the client is free (the
1320 appropriate bit in all the other drivers is clear) one will be written to
1321 that driver register; if the client isn't free the bit will remain zero.
1322 if the appropriate bit is set (the driver request to gain control on a
1323 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1324 interrupt will be asserted). write to address 0 will set a request to
1325 free all the clients that their appropriate bit (in the write command) is
1326 set. if the appropriate bit is clear (the driver request to free a client
1327 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1328 be asserted). */
1329#define MISC_REG_DRIVER_CONTROL_12 0xa3f0
1330#define MISC_REG_DRIVER_CONTROL_12_SIZE 2
1331/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1332 32 clients. Each client can be controlled by one driver only. One in each
1333 bit represent that this driver control the appropriate client (Ex: bit 5
1334 is set means this driver control client number 5). addr1 = set; addr0 =
1335 clear; read from both addresses will give the same result = status. write
1336 to address 1 will set a request to control all the clients that their
1337 appropriate bit (in the write command) is set. if the client is free (the
1338 appropriate bit in all the other drivers is clear) one will be written to
1339 that driver register; if the client isn't free the bit will remain zero.
1340 if the appropriate bit is set (the driver request to gain control on a
1341 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1342 interrupt will be asserted). write to address 0 will set a request to
1343 free all the clients that their appropriate bit (in the write command) is
1344 set. if the appropriate bit is clear (the driver request to free a client
1345 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1346 be asserted). */
1347#define MISC_REG_DRIVER_CONTROL_13 0xa3f8
1348#define MISC_REG_DRIVER_CONTROL_13_SIZE 2
1349/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1350 32 clients. Each client can be controlled by one driver only. One in each
f1410647
ET		 1351 bit represent that this driver control the appropriate client (Ex: bit 5
1352 is set means this driver control client number 5). addr1 = set; addr0 =
1353 clear; read from both addresses will give the same result = status. write
1354 to address 1 will set a request to control all the clients that their
1355 appropriate bit (in the write command) is set. if the client is free (the
1356 appropriate bit in all the other drivers is clear) one will be written to
1357 that driver register; if the client isn't free the bit will remain zero.
1358 if the appropriate bit is set (the driver request to gain control on a
1359 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1360 interrupt will be asserted). write to address 0 will set a request to
1361 free all the clients that their appropriate bit (in the write command) is
1362 set. if the appropriate bit is clear (the driver request to free a client
1363 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1364 be asserted). */
1365#define MISC_REG_DRIVER_CONTROL_1 0xa510
c18487ee
YR		 1366#define MISC_REG_DRIVER_CONTROL_14 0xa5e0
1367#define MISC_REG_DRIVER_CONTROL_14_SIZE 2
1368/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1369 32 clients. Each client can be controlled by one driver only. One in each
1370 bit represent that this driver control the appropriate client (Ex: bit 5
1371 is set means this driver control client number 5). addr1 = set; addr0 =
1372 clear; read from both addresses will give the same result = status. write
1373 to address 1 will set a request to control all the clients that their
1374 appropriate bit (in the write command) is set. if the client is free (the
1375 appropriate bit in all the other drivers is clear) one will be written to
1376 that driver register; if the client isn't free the bit will remain zero.
1377 if the appropriate bit is set (the driver request to gain control on a
1378 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1379 interrupt will be asserted). write to address 0 will set a request to
1380 free all the clients that their appropriate bit (in the write command) is
1381 set. if the appropriate bit is clear (the driver request to free a client
1382 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1383 be asserted). */
1384#define MISC_REG_DRIVER_CONTROL_15 0xa5e8
1385#define MISC_REG_DRIVER_CONTROL_15_SIZE 2
1386/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1387 32 clients. Each client can be controlled by one driver only. One in each
1388 bit represent that this driver control the appropriate client (Ex: bit 5
1389 is set means this driver control client number 5). addr1 = set; addr0 =
1390 clear; read from both addresses will give the same result = status. write
1391 to address 1 will set a request to control all the clients that their
1392 appropriate bit (in the write command) is set. if the client is free (the
1393 appropriate bit in all the other drivers is clear) one will be written to
1394 that driver register; if the client isn't free the bit will remain zero.
1395 if the appropriate bit is set (the driver request to gain control on a
1396 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1397 interrupt will be asserted). write to address 0 will set a request to
1398 free all the clients that their appropriate bit (in the write command) is
1399 set. if the appropriate bit is clear (the driver request to free a client
1400 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1401 be asserted). */
1402#define MISC_REG_DRIVER_CONTROL_16 0xa5f0
1403#define MISC_REG_DRIVER_CONTROL_16_SIZE 2
4a37fb66
YG		 1404/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1405 32 clients. Each client can be controlled by one driver only. One in each
1406 bit represent that this driver control the appropriate client (Ex: bit 5
1407 is set means this driver control client number 5). addr1 = set; addr0 =
1408 clear; read from both addresses will give the same result = status. write
1409 to address 1 will set a request to control all the clients that their
1410 appropriate bit (in the write command) is set. if the client is free (the
1411 appropriate bit in all the other drivers is clear) one will be written to
1412 that driver register; if the client isn't free the bit will remain zero.
1413 if the appropriate bit is set (the driver request to gain control on a
1414 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1415 interrupt will be asserted). write to address 0 will set a request to
1416 free all the clients that their appropriate bit (in the write command) is
1417 set. if the appropriate bit is clear (the driver request to free a client
1418 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1419 be asserted). */
1420#define MISC_REG_DRIVER_CONTROL_7 0xa3c8
c18487ee
YR		 1421/* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0
1422 only. */
1423#define MISC_REG_E1HMF_MODE 0xa5f8
f1410647
ET		 1424/* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of
1425 these bits is written as a '1'; the corresponding SPIO bit will turn off
1426 it's drivers and become an input. This is the reset state of all GPIO
1427 pins. The read value of these bits will be a '1' if that last command
1428 (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff).
1429 [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written
1430 as a '1'; the corresponding GPIO bit will drive low. The read value of
1431 these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for
1432 this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0;
1433 SET When any of these bits is written as a '1'; the corresponding GPIO
1434 bit will drive high (if it has that capability). The read value of these
1435 bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this
1436 bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0;
1437 RO; These bits indicate the read value of each of the eight GPIO pins.
1438 This is the result value of the pin; not the drive value. Writing these
1439 bits will have not effect. */
1440#define MISC_REG_GPIO 0xa490
c18487ee
YR		 1441/* [R 28] this field hold the last information that caused reserved
1442 attention. bits [19:0] - address; [22:20] function; [23] reserved;
33471629 1443 [27:24] the master that caused the attention - according to the following
c18487ee
YR		 1444 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1445 dbu; 8 = dmae */
1446#define MISC_REG_GRC_RSV_ATTN 0xa3c0
1447/* [R 28] this field hold the last information that caused timeout
1448 attention. bits [19:0] - address; [22:20] function; [23] reserved;
33471629 1449 [27:24] the master that caused the attention - according to the following
c18487ee
YR		 1450 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1451 dbu; 8 = dmae */
1452#define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4
a2fbb9ea
ET		 1453/* [RW 1] Setting this bit enables a timer in the GRC block to timeout any
1454 access that does not finish within
1455 ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is
1456 cleared; this timeout is disabled. If this timeout occurs; the GRC shall
1457 assert it attention output. */
1458#define MISC_REG_GRC_TIMEOUT_EN 0xa280
1459/* [RW 28] 28 LSB of LCPLL first register; reset val = 521. inside order of
1460 the bits is: [2:0] OAC reset value 001) CML output buffer bias control;
1461 111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl
1462 (reset value 001) Charge pump current control; 111 for 720u; 011 for
1463 600u; 001 for 480u and 000 for 360u. [7:6] Bias_ctrl (reset value 00)
1464 Global bias control; When bit 7 is high bias current will be 10 0gh; When
1465 bit 6 is high bias will be 100w; Valid values are 00; 10; 01. [10:8]
1466 Pll_observe (reset value 010) Bits to control observability. bit 10 is
1467 for test bias; bit 9 is for test CK; bit 8 is test Vc. [12:11] Vth_ctrl
1468 (reset value 00) Comparator threshold control. 00 for 0.6V; 01 for 0.54V
1469 and 10 for 0.66V. [13] pllSeqStart (reset value 0) Enables VCO tuning
1470 sequencer: 1= sequencer disabled; 0= sequencer enabled (inverted
1471 internally). [14] reserved (reset value 0) Reset for VCO sequencer is
1472 connected to RESET input directly. [15] capRetry_en (reset value 0)
1473 enable retry on cap search failure (inverted). [16] freqMonitor_e (reset
1474 value 0) bit to continuously monitor vco freq (inverted). [17]
1475 freqDetRestart_en (reset value 0) bit to enable restart when not freq
1476 locked (inverted). [18] freqDetRetry_en (reset value 0) bit to enable
1477 retry on freq det failure(inverted). [19] pllForceFdone_en (reset value
1478 0) bit to enable pllForceFdone & pllForceFpass into pllSeq. [20]
1479 pllForceFdone (reset value 0) bit to force freqDone. [21] pllForceFpass
1480 (reset value 0) bit to force freqPass. [22] pllForceDone_en (reset value
1481 0) bit to enable pllForceCapDone. [23] pllForceCapDone (reset value 0)
1482 bit to force capDone. [24] pllForceCapPass_en (reset value 0) bit to
1483 enable pllForceCapPass. [25] pllForceCapPass (reset value 0) bit to force
1484 capPass. [26] capRestart (reset value 0) bit to force cap sequencer to
1485 restart. [27] capSelectM_en (reset value 0) bit to enable cap select
1486 register bits. */
1487#define MISC_REG_LCPLL_CTRL_1 0xa2a4
1488#define MISC_REG_LCPLL_CTRL_REG_2 0xa2a8
1489/* [RW 4] Interrupt mask register #0 read/write */
1490#define MISC_REG_MISC_INT_MASK 0xa388
1491/* [RW 1] Parity mask register #0 read/write */
1492#define MISC_REG_MISC_PRTY_MASK 0xa398
f1410647
ET		 1493/* [R 1] Parity register #0 read */
1494#define MISC_REG_MISC_PRTY_STS 0xa38c
c18487ee
YR		 1495#define MISC_REG_NIG_WOL_P0 0xa270
1496#define MISC_REG_NIG_WOL_P1 0xa274
1497/* [R 1] If set indicate that the pcie_rst_b was asserted without perst
1498 assertion */
1499#define MISC_REG_PCIE_HOT_RESET 0xa618
a2fbb9ea
ET		 1500/* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911.
1501 inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1
1502 divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1
1503 divider[3] (reset value 0); [4] P2 divider[0] (reset value 1); [5] P2
1504 divider[1] (reset value 0); [6] P2 divider[2] (reset value 0); [7] P2
1505 divider[3] (reset value 0); [8] ph_det_dis (reset value 1); [9]
1506 freq_det_dis (reset value 0); [10] Icpx[0] (reset value 0); [11] Icpx[1]
1507 (reset value 1); [12] Icpx[2] (reset value 0); [13] Icpx[3] (reset value
1508 1); [14] Icpx[4] (reset value 0); [15] Icpx[5] (reset value 0); [16]
1509 Rx[0] (reset value 1); [17] Rx[1] (reset value 0); [18] vc_en (reset
1510 value 1); [19] vco_rng[0] (reset value 1); [20] vco_rng[1] (reset value
1511 1); [21] Kvco_xf[0] (reset value 0); [22] Kvco_xf[1] (reset value 0);
1512 [23] Kvco_xf[2] (reset value 0); [24] Kvco_xs[0] (reset value 1); [25]
1513 Kvco_xs[1] (reset value 1); [26] Kvco_xs[2] (reset value 1); [27]
1514 testd_en (reset value 0); [28] testd_sel[0] (reset value 0); [29]
1515 testd_sel[1] (reset value 0); [30] testd_sel[2] (reset value 0); [31]
1516 testa_en (reset value 0); */
1517#define MISC_REG_PLL_STORM_CTRL_1 0xa294
1518#define MISC_REG_PLL_STORM_CTRL_2 0xa298
1519#define MISC_REG_PLL_STORM_CTRL_3 0xa29c
1520#define MISC_REG_PLL_STORM_CTRL_4 0xa2a0
c18487ee 1521/* [RW 32] reset reg#2; rite/read one = the specific block is out of reset;
a2fbb9ea
ET		 1522 write/read zero = the specific block is in reset; addr 0-wr- the write
1523 value will be written to the register; addr 1-set - one will be written
1524 to all the bits that have the value of one in the data written (bits that
1525 have the value of zero will not be change) ; addr 2-clear - zero will be
1526 written to all the bits that have the value of one in the data written
1527 (bits that have the value of zero will not be change); addr 3-ignore;
1528 read ignore from all addr except addr 00; inside order of the bits is:
c18487ee
YR		 1529 [0] rst_bmac0; [1] rst_bmac1; [2] rst_emac0; [3] rst_emac1; [4] rst_grc;
1530 [5] rst_mcp_n_reset_reg_hard_core; [6] rst_ mcp_n_hard_core_rst_b; [7]
1531 rst_ mcp_n_reset_cmn_cpu; [8] rst_ mcp_n_reset_cmn_core; [9] rst_rbcn;
1532 [10] rst_dbg; [11] rst_misc_core; [12] rst_dbue (UART); [13]
1533 Pci_resetmdio_n; [14] rst_emac0_hard_core; [15] rst_emac1_hard_core; 16]
1534 rst_pxp_rq_rd_wr; 31:17] reserved */
a2fbb9ea
ET		 1535#define MISC_REG_RESET_REG_2 0xa590
1536/* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is
1537 shared with the driver resides */
1538#define MISC_REG_SHARED_MEM_ADDR 0xa2b4
f1410647
ET		 1539/* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1';
1540 the corresponding SPIO bit will turn off it's drivers and become an
1541 input. This is the reset state of all SPIO pins. The read value of these
1542 bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this
1543 bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits
1544 is written as a '1'; the corresponding SPIO bit will drive low. The read
1545 value of these bits will be a '1' if that last command (#SET; #CLR; or
1546#FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of
1547 these bits is written as a '1'; the corresponding SPIO bit will drive
1548 high (if it has that capability). The read value of these bits will be a
1549 '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET.
1550 (reset value 0). [7-0] VALUE RO; These bits indicate the read value of
1551 each of the eight SPIO pins. This is the result value of the pin; not the
1552 drive value. Writing these bits will have not effect. Each 8 bits field
1553 is divided as follows: [0] VAUX Enable; when pulsed low; enables supply
1554 from VAUX. (This is an output pin only; the FLOAT field is not applicable
1555 for this pin); [1] VAUX Disable; when pulsed low; disables supply form
1556 VAUX. (This is an output pin only; FLOAT field is not applicable for this
1557 pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to
1558 select VAUX supply. (This is an output pin only; it is not controlled by
1559 the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT
1560 field is not applicable for this pin; only the VALUE fields is relevant -
c18487ee 1561 it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6]
f1410647
ET		 1562 Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP
1563 device ID select; read by UMP firmware. */
1564#define MISC_REG_SPIO 0xa4fc
1565/* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC.
1566 according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5;
1567 [7:0] reserved */
1568#define MISC_REG_SPIO_EVENT_EN 0xa2b8
1569/* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the
1570 corresponding bit in the #OLD_VALUE register. This will acknowledge an
1571 interrupt on the falling edge of corresponding SPIO input (reset value
1572 0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit
1573 in the #OLD_VALUE register. This will acknowledge an interrupt on the
1574 rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE
1575 RO; These bits indicate the old value of the SPIO input value. When the
1576 ~INT_STATE bit is set; this bit indicates the OLD value of the pin such
1577 that if ~INT_STATE is set and this bit is '0'; then the interrupt is due
1578 to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the
1579 interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE
1580 RO; These bits indicate the current SPIO interrupt state for each SPIO
1581 pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR
1582 command bit is written. This bit is set when the SPIO input does not
1583 match the current value in #OLD_VALUE (reset value 0). */
1584#define MISC_REG_SPIO_INT 0xa500
8d9c5f34
EG		 1585/* [RW 32] reload value for counter 4 if reload; the value will be reload if
1586 the counter reached zero and the reload bit
1587 (~misc_registers_sw_timer_cfg_4.sw_timer_cfg_4[1] ) is set */
1588#define MISC_REG_SW_TIMER_RELOAD_VAL_4 0xa2fc
1589/* [RW 32] the value of the counter for sw timers1-8. there are 8 addresses
1590 in this register. addres 0 - timer 1; address - timer 2�address 7 -
1591 timer 8 */
1592#define MISC_REG_SW_TIMER_VAL 0xa5c0
f1410647
ET		 1593/* [RW 1] Set by the MCP to remember if one or more of the drivers is/are
1594 loaded; 0-prepare; -unprepare */
1595#define MISC_REG_UNPREPARED 0xa424
a2fbb9ea
ET		 1596#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0)
1597#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9)
1598#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15)
1599#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS (0xf<<18)
1600/* [RW 1] Input enable for RX_BMAC0 IF */
1601#define NIG_REG_BMAC0_IN_EN 0x100ac
1602/* [RW 1] output enable for TX_BMAC0 IF */
1603#define NIG_REG_BMAC0_OUT_EN 0x100e0
1604/* [RW 1] output enable for TX BMAC pause port 0 IF */
1605#define NIG_REG_BMAC0_PAUSE_OUT_EN 0x10110
1606/* [RW 1] output enable for RX_BMAC0_REGS IF */
1607#define NIG_REG_BMAC0_REGS_OUT_EN 0x100e8
1608/* [RW 1] output enable for RX BRB1 port0 IF */
1609#define NIG_REG_BRB0_OUT_EN 0x100f8
1610/* [RW 1] Input enable for TX BRB1 pause port 0 IF */
1611#define NIG_REG_BRB0_PAUSE_IN_EN 0x100c4
1612/* [RW 1] output enable for RX BRB1 port1 IF */
1613#define NIG_REG_BRB1_OUT_EN 0x100fc
1614/* [RW 1] Input enable for TX BRB1 pause port 1 IF */
1615#define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8
1616/* [RW 1] output enable for RX BRB1 LP IF */
1617#define NIG_REG_BRB_LB_OUT_EN 0x10100
c18487ee
YR		 1618/* [WB_W 82] Debug packet to LP from RBC; Data spelling:[63:0] data; 64]
1619 error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush;
1620 72:73]-vnic_num; 81:74]-sideband_info */
a2fbb9ea
ET		 1621#define NIG_REG_DEBUG_PACKET_LB 0x10800
1622/* [RW 1] Input enable for TX Debug packet */
1623#define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dc
1624/* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all
1625 packets from PBFare not forwarded to the MAC and just deleted from FIFO.
1626 First packet may be deleted from the middle. And last packet will be
1627 always deleted till the end. */
1628#define NIG_REG_EGRESS_DRAIN0_MODE 0x10060
1629/* [RW 1] Output enable to EMAC0 */
1630#define NIG_REG_EGRESS_EMAC0_OUT_EN 0x10120
1631/* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs
1632 to emac for port0; other way to bmac for port0 */
1633#define NIG_REG_EGRESS_EMAC0_PORT 0x10058
c18487ee
YR		 1634/* [RW 32] TX_MNG_FIFO in NIG_TX_PORT0; data[31:0] written in FIFO order. */
1635#define NIG_REG_EGRESS_MNG0_FIFO 0x1045c
a2fbb9ea
ET		 1636/* [RW 1] Input enable for TX PBF user packet port0 IF */
1637#define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc
1638/* [RW 1] Input enable for TX PBF user packet port1 IF */
1639#define NIG_REG_EGRESS_PBF1_IN_EN 0x100d0
1640/* [RW 1] Input enable for RX_EMAC0 IF */
1641#define NIG_REG_EMAC0_IN_EN 0x100a4
1642/* [RW 1] output enable for TX EMAC pause port 0 IF */
1643#define NIG_REG_EMAC0_PAUSE_OUT_EN 0x10118
1644/* [R 1] status from emac0. This bit is set when MDINT from either the
1645 EXT_MDINT pin or from the Copper PHY is driven low. This condition must
1646 be cleared in the attached PHY device that is driving the MINT pin. */
1647#define NIG_REG_EMAC0_STATUS_MISC_MI_INT 0x10494
1648/* [WB 48] This address space contains BMAC0 registers. The BMAC registers
1649 are described in appendix A. In order to access the BMAC0 registers; the
1650 base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be
1651 added to each BMAC register offset */
1652#define NIG_REG_INGRESS_BMAC0_MEM 0x10c00
1653/* [WB 48] This address space contains BMAC1 registers. The BMAC registers
1654 are described in appendix A. In order to access the BMAC0 registers; the
1655 base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be
1656 added to each BMAC register offset */
1657#define NIG_REG_INGRESS_BMAC1_MEM 0x11000
1658/* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */
1659#define NIG_REG_INGRESS_EOP_LB_EMPTY 0x104e0
1660/* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data
1661 packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */
1662#define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4
1663/* [RW 1] led 10g for port 0 */
1664#define NIG_REG_LED_10G_P0 0x10320
c18487ee
YR		 1665/* [RW 1] led 10g for port 1 */
1666#define NIG_REG_LED_10G_P1 0x10324
a2fbb9ea
ET		 1667/* [RW 1] Port0: This bit is set to enable the use of the
1668 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field
1669 defined below. If this bit is cleared; then the blink rate will be about
1670 8Hz. */
1671#define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 0x10318
1672/* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for
1673 Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field
1674 is reset to 0x080; giving a default blink period of approximately 8Hz. */
1675#define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310
1676/* [RW 1] Port0: If set along with the
34f80b04 1677 ~nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0
a2fbb9ea
ET		 1678 bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED
1679 bit; the Traffic LED will blink with the blink rate specified in
1680 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
1681 ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
1682 fields. */
1683#define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 0x10308
1684/* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The
1685 Traffic LED will then be controlled via bit ~nig_registers_
1686 led_control_traffic_p0.led_control_traffic_p0 and bit
1687 ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 */
1688#define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x102f8
1689/* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit;
1690 turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also
1691 set; the LED will blink with blink rate specified in
1692 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
1693 ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
1694 fields. */
1695#define NIG_REG_LED_CONTROL_TRAFFIC_P0 0x10300
1696/* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3;
1697 9-11PHY7; 12 MAC4; 13-15 PHY10; */
1698#define NIG_REG_LED_MODE_P0 0x102f0
1c06328c
EG		 1699/* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1-
1700 tsdm enable; b2- usdm enable */
1701#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 0x16070
1702/* [RW 1] SAFC enable for port0. This register may get 1 only when
1703 ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same
1704 port */
1705#define NIG_REG_LLFC_ENABLE_0 0x16208
1706/* [RW 16] classes are high-priority for port0 */
1707#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 0x16058
1708/* [RW 16] classes are low-priority for port0 */
1709#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 0x16060
1710/* [RW 1] Output enable of message to LLFC BMAC IF for port0 */
1711#define NIG_REG_LLFC_OUT_EN_0 0x160c8
c18487ee
YR		 1712#define NIG_REG_LLH0_ACPI_PAT_0_CRC 0x1015c
1713#define NIG_REG_LLH0_ACPI_PAT_6_LEN 0x10154
a2fbb9ea 1714#define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244
c18487ee 1715#define NIG_REG_LLH0_BRB1_DRV_MASK_MF 0x16048
a2fbb9ea
ET		 1716/* [RW 1] send to BRB1 if no match on any of RMP rules. */
1717#define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c
c18487ee
YR		 1718/* [RW 2] Determine the classification participants. 0: no classification.1:
1719 classification upon VLAN id. 2: classification upon MAC address. 3:
1720 classification upon both VLAN id & MAC addr. */
1721#define NIG_REG_LLH0_CLS_TYPE 0x16080
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ET		 1722/* [RW 32] cm header for llh0 */
1723#define NIG_REG_LLH0_CM_HEADER 0x1007c
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YR		 1724#define NIG_REG_LLH0_DEST_IP_0_1 0x101dc
1725#define NIG_REG_LLH0_DEST_MAC_0_0 0x101c0
1726/* [RW 16] destination TCP address 1. The LLH will look for this address in
1727 all incoming packets. */
1728#define NIG_REG_LLH0_DEST_TCP_0 0x10220
1729/* [RW 16] destination UDP address 1 The LLH will look for this address in
1730 all incoming packets. */
1731#define NIG_REG_LLH0_DEST_UDP_0 0x10214
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ET		 1732#define NIG_REG_LLH0_ERROR_MASK 0x1008c
1733/* [RW 8] event id for llh0 */
1734#define NIG_REG_LLH0_EVENT_ID 0x10084
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YR		 1735#define NIG_REG_LLH0_FUNC_EN 0x160fc
1736#define NIG_REG_LLH0_FUNC_VLAN_ID 0x16100
1737/* [RW 1] Determine the IP version to look for in
1738 ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 */
1739#define NIG_REG_LLH0_IPV4_IPV6_0 0x10208
1740/* [RW 1] t bit for llh0 */
1741#define NIG_REG_LLH0_T_BIT 0x10074
1742/* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */
1743#define NIG_REG_LLH0_VLAN_ID_0 0x1022c
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ET		 1744/* [RW 8] init credit counter for port0 in LLH */
1745#define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554
1746#define NIG_REG_LLH0_XCM_MASK 0x10130
da5a662a 1747#define NIG_REG_LLH1_BRB1_DRV_MASK 0x10248
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ET		 1748/* [RW 1] send to BRB1 if no match on any of RMP rules. */
1749#define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc
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YR		 1750/* [RW 2] Determine the classification participants. 0: no classification.1:
1751 classification upon VLAN id. 2: classification upon MAC address. 3:
1752 classification upon both VLAN id & MAC addr. */
1753#define NIG_REG_LLH1_CLS_TYPE 0x16084
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ET		 1754/* [RW 32] cm header for llh1 */
1755#define NIG_REG_LLH1_CM_HEADER 0x10080
1756#define NIG_REG_LLH1_ERROR_MASK 0x10090
1757/* [RW 8] event id for llh1 */
1758#define NIG_REG_LLH1_EVENT_ID 0x10088
1759/* [RW 8] init credit counter for port1 in LLH */
1760#define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564
1761#define NIG_REG_LLH1_XCM_MASK 0x10134
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YR		 1762/* [RW 1] When this bit is set; the LLH will expect all packets to be with
1763 e1hov */
1764#define NIG_REG_LLH_E1HOV_MODE 0x160d8
1765/* [RW 1] When this bit is set; the LLH will classify the packet before
1766 sending it to the BRB or calculating WoL on it. */
1767#define NIG_REG_LLH_MF_MODE 0x16024
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ET		 1768#define NIG_REG_MASK_INTERRUPT_PORT0 0x10330
1769#define NIG_REG_MASK_INTERRUPT_PORT1 0x10334
1770/* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */
1771#define NIG_REG_NIG_EMAC0_EN 0x1003c
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YR		 1772/* [RW 1] Output signal from NIG to EMAC1. When set enables the EMAC1 block. */
1773#define NIG_REG_NIG_EMAC1_EN 0x10040
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ET		 1774/* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the
1775 EMAC0 to strip the CRC from the ingress packets. */
1776#define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044
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YR		 1777/* [R 32] Interrupt register #0 read */
1778#define NIG_REG_NIG_INT_STS_0 0x103b0
1779#define NIG_REG_NIG_INT_STS_1 0x103c0
1780/* [R 32] Parity register #0 read */
1781#define NIG_REG_NIG_PRTY_STS 0x103d0
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EG		 1782/* [RW 1] Pause enable for port0. This register may get 1 only when
1783 ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same
1784 port */
1785#define NIG_REG_PAUSE_ENABLE_0 0x160c0
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ET		 1786/* [RW 1] Input enable for RX PBF LP IF */
1787#define NIG_REG_PBF_LB_IN_EN 0x100b4
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ET		 1788/* [RW 1] Value of this register will be transmitted to port swap when
1789 ~nig_registers_strap_override.strap_override =1 */
1790#define NIG_REG_PORT_SWAP 0x10394
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ET		 1791/* [RW 1] output enable for RX parser descriptor IF */
1792#define NIG_REG_PRS_EOP_OUT_EN 0x10104
1793/* [RW 1] Input enable for RX parser request IF */
1794#define NIG_REG_PRS_REQ_IN_EN 0x100b8
1795/* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */
1796#define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374
1797/* [R 1] status from serdes0 that inputs to interrupt logic of link status */
1798#define NIG_REG_SERDES0_STATUS_LINK_STATUS 0x10578
1799/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
1800 for port0 */
1801#define NIG_REG_STAT0_BRB_DISCARD 0x105f0
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YG		 1802/* [R 32] Rx statistics : In user packets truncated due to BRB backpressure
1803 for port0 */
1804#define NIG_REG_STAT0_BRB_TRUNCATE 0x105f8
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EG		 1805/* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
1806 between 1024 and 1522 bytes for port0 */
1807#define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750
1808/* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
1809 between 1523 bytes and above for port0 */
1810#define NIG_REG_STAT0_EGRESS_MAC_PKT1 0x10760
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ET		 1811/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
1812 for port1 */
1813#define NIG_REG_STAT1_BRB_DISCARD 0x10628
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EG		 1814/* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
1815 between 1024 and 1522 bytes for port1 */
1816#define NIG_REG_STAT1_EGRESS_MAC_PKT0 0x107a0
1817/* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
1818 between 1523 bytes and above for port1 */
1819#define NIG_REG_STAT1_EGRESS_MAC_PKT1 0x107b0
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ET		 1820/* [WB_R 64] Rx statistics : User octets received for LP */
1821#define NIG_REG_STAT2_BRB_OCTET 0x107e0
1822#define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328
1823#define NIG_REG_STATUS_INTERRUPT_PORT1 0x1032c
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ET		 1824/* [RW 1] port swap mux selection. If this register equal to 0 then port
1825 swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then
1826 ort swap is equal to ~nig_registers_port_swap.port_swap */
1827#define NIG_REG_STRAP_OVERRIDE 0x10398
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ET		 1828/* [RW 1] output enable for RX_XCM0 IF */
1829#define NIG_REG_XCM0_OUT_EN 0x100f0
1830/* [RW 1] output enable for RX_XCM1 IF */
1831#define NIG_REG_XCM1_OUT_EN 0x100f4
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YR		 1832/* [RW 1] control to xgxs - remote PHY in-band MDIO */
1833#define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST 0x10348
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ET		 1834/* [RW 5] control to xgxs - CL45 DEVAD */
1835#define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c
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YR		 1836/* [RW 1] control to xgxs; 0 - clause 45; 1 - clause 22 */
1837#define NIG_REG_XGXS0_CTRL_MD_ST 0x10338
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ET		 1838/* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */
1839#define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340
1840/* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */
1841#define NIG_REG_XGXS0_STATUS_LINK10G 0x10680
1842/* [R 4] status from xgxs0 that inputs to interrupt logic of link status */
1843#define NIG_REG_XGXS0_STATUS_LINK_STATUS 0x10684
1844/* [RW 2] selection for XGXS lane of port 0 in NIG_MUX block */
1845#define NIG_REG_XGXS_LANE_SEL_P0 0x102e8
1846/* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */
1847#define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0
1848#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9)
1849#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1<<15)
1850#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf<<18)
1851#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18
1852/* [RW 1] Disable processing further tasks from port 0 (after ending the
1853 current task in process). */
1854#define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005c
1855/* [RW 1] Disable processing further tasks from port 1 (after ending the
1856 current task in process). */
1857#define PBF_REG_DISABLE_NEW_TASK_PROC_P1 0x140060
1858/* [RW 1] Disable processing further tasks from port 4 (after ending the
1859 current task in process). */
1860#define PBF_REG_DISABLE_NEW_TASK_PROC_P4 0x14006c
1861#define PBF_REG_IF_ENABLE_REG 0x140044
1862/* [RW 1] Init bit. When set the initial credits are copied to the credit
1863 registers (except the port credits). Should be set and then reset after
1864 the configuration of the block has ended. */
1865#define PBF_REG_INIT 0x140000
1866/* [RW 1] Init bit for port 0. When set the initial credit of port 0 is
1867 copied to the credit register. Should be set and then reset after the
1868 configuration of the port has ended. */
1869#define PBF_REG_INIT_P0 0x140004
1870/* [RW 1] Init bit for port 1. When set the initial credit of port 1 is
1871 copied to the credit register. Should be set and then reset after the
1872 configuration of the port has ended. */
1873#define PBF_REG_INIT_P1 0x140008
1874/* [RW 1] Init bit for port 4. When set the initial credit of port 4 is
1875 copied to the credit register. Should be set and then reset after the
1876 configuration of the port has ended. */
1877#define PBF_REG_INIT_P4 0x14000c
1878/* [RW 1] Enable for mac interface 0. */
1879#define PBF_REG_MAC_IF0_ENABLE 0x140030
1880/* [RW 1] Enable for mac interface 1. */
1881#define PBF_REG_MAC_IF1_ENABLE 0x140034
1882/* [RW 1] Enable for the loopback interface. */
1883#define PBF_REG_MAC_LB_ENABLE 0x140040
1884/* [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when pause
1885 not suppoterd. */
1886#define PBF_REG_P0_ARB_THRSH 0x1400e4
1887/* [R 11] Current credit for port 0 in the tx port buffers in 16 byte lines. */
1888#define PBF_REG_P0_CREDIT 0x140200
1889/* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte
1890 lines. */
1891#define PBF_REG_P0_INIT_CRD 0x1400d0
1892/* [RW 1] Indication that pause is enabled for port 0. */
1893#define PBF_REG_P0_PAUSE_ENABLE 0x140014
1894/* [R 8] Number of tasks in port 0 task queue. */
1895#define PBF_REG_P0_TASK_CNT 0x140204
1896/* [R 11] Current credit for port 1 in the tx port buffers in 16 byte lines. */
1897#define PBF_REG_P1_CREDIT 0x140208
1898/* [RW 11] Initial credit for port 1 in the tx port buffers in 16 byte
1899 lines. */
1900#define PBF_REG_P1_INIT_CRD 0x1400d4
1901/* [R 8] Number of tasks in port 1 task queue. */
1902#define PBF_REG_P1_TASK_CNT 0x14020c
1903/* [R 11] Current credit for port 4 in the tx port buffers in 16 byte lines. */
1904#define PBF_REG_P4_CREDIT 0x140210
1905/* [RW 11] Initial credit for port 4 in the tx port buffers in 16 byte
1906 lines. */
1907#define PBF_REG_P4_INIT_CRD 0x1400e0
1908/* [R 8] Number of tasks in port 4 task queue. */
1909#define PBF_REG_P4_TASK_CNT 0x140214
1910/* [RW 5] Interrupt mask register #0 read/write */
1911#define PBF_REG_PBF_INT_MASK 0x1401d4
1912/* [R 5] Interrupt register #0 read */
1913#define PBF_REG_PBF_INT_STS 0x1401c8
1914#define PB_REG_CONTROL 0
1915/* [RW 2] Interrupt mask register #0 read/write */
1916#define PB_REG_PB_INT_MASK 0x28
1917/* [R 2] Interrupt register #0 read */
1918#define PB_REG_PB_INT_STS 0x1c
1919/* [RW 4] Parity mask register #0 read/write */
1920#define PB_REG_PB_PRTY_MASK 0x38
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ET		 1921/* [R 4] Parity register #0 read */
1922#define PB_REG_PB_PRTY_STS 0x2c
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ET		 1923#define PRS_REG_A_PRSU_20 0x40134
1924/* [R 8] debug only: CFC load request current credit. Transaction based. */
1925#define PRS_REG_CFC_LD_CURRENT_CREDIT 0x40164
1926/* [R 8] debug only: CFC search request current credit. Transaction based. */
1927#define PRS_REG_CFC_SEARCH_CURRENT_CREDIT 0x40168
1928/* [RW 6] The initial credit for the search message to the CFC interface.
1929 Credit is transaction based. */
1930#define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c
1931/* [RW 24] CID for port 0 if no match */
1932#define PRS_REG_CID_PORT_0 0x400fc
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ET		 1933/* [RW 32] The CM header for flush message where 'load existed' bit in CFC
1934 load response is reset and packet type is 0. Used in packet start message
1935 to TCM. */
1936#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0 0x400dc
1937#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1 0x400e0
1938#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2 0x400e4
1939#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3 0x400e8
1940#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4 0x400ec
8d9c5f34 1941#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5 0x400f0
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ET		 1942/* [RW 32] The CM header for flush message where 'load existed' bit in CFC
1943 load response is set and packet type is 0. Used in packet start message
1944 to TCM. */
1945#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0 0x400bc
1946#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1 0x400c0
1947#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0x400c4
1948#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0x400c8
1949#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0x400cc
8d9c5f34 1950#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5 0x400d0
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ET		 1951/* [RW 32] The CM header for a match and packet type 1 for loopback port.
1952 Used in packet start message to TCM. */
1953#define PRS_REG_CM_HDR_LOOPBACK_TYPE_1 0x4009c
1954#define PRS_REG_CM_HDR_LOOPBACK_TYPE_2 0x400a0
1955#define PRS_REG_CM_HDR_LOOPBACK_TYPE_3 0x400a4
1956#define PRS_REG_CM_HDR_LOOPBACK_TYPE_4 0x400a8
1957/* [RW 32] The CM header for a match and packet type 0. Used in packet start
1958 message to TCM. */
1959#define PRS_REG_CM_HDR_TYPE_0 0x40078
1960#define PRS_REG_CM_HDR_TYPE_1 0x4007c
1961#define PRS_REG_CM_HDR_TYPE_2 0x40080
1962#define PRS_REG_CM_HDR_TYPE_3 0x40084
1963#define PRS_REG_CM_HDR_TYPE_4 0x40088
1964/* [RW 32] The CM header in case there was not a match on the connection */
1965#define PRS_REG_CM_NO_MATCH_HDR 0x400b8
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YR		 1966/* [RW 1] Indicates if in e1hov mode. 0=non-e1hov mode; 1=e1hov mode. */
1967#define PRS_REG_E1HOV_MODE 0x401c8
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ET		 1968/* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet
1969 start message to TCM. */
1970#define PRS_REG_EVENT_ID_1 0x40054
1971#define PRS_REG_EVENT_ID_2 0x40058
1972#define PRS_REG_EVENT_ID_3 0x4005c
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YR		 1973/* [RW 16] The Ethernet type value for FCoE */
1974#define PRS_REG_FCOE_TYPE 0x401d0
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ET		 1975/* [RW 8] Context region for flush packet with packet type 0. Used in CFC
1976 load request message. */
1977#define PRS_REG_FLUSH_REGIONS_TYPE_0 0x40004
1978#define PRS_REG_FLUSH_REGIONS_TYPE_1 0x40008
1979#define PRS_REG_FLUSH_REGIONS_TYPE_2 0x4000c
1980#define PRS_REG_FLUSH_REGIONS_TYPE_3 0x40010
1981#define PRS_REG_FLUSH_REGIONS_TYPE_4 0x40014
1982#define PRS_REG_FLUSH_REGIONS_TYPE_5 0x40018
1983#define PRS_REG_FLUSH_REGIONS_TYPE_6 0x4001c
1984#define PRS_REG_FLUSH_REGIONS_TYPE_7 0x40020
1985/* [RW 4] The increment value to send in the CFC load request message */
1986#define PRS_REG_INC_VALUE 0x40048
1987/* [RW 1] If set indicates not to send messages to CFC on received packets */
1988#define PRS_REG_NIC_MODE 0x40138
1989/* [RW 8] The 8-bit event ID for cases where there is no match on the
1990 connection. Used in packet start message to TCM. */
1991#define PRS_REG_NO_MATCH_EVENT_ID 0x40070
1992/* [ST 24] The number of input CFC flush packets */
1993#define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES 0x40128
1994/* [ST 32] The number of cycles the Parser halted its operation since it
1995 could not allocate the next serial number */
1996#define PRS_REG_NUM_OF_DEAD_CYCLES 0x40130
1997/* [ST 24] The number of input packets */
1998#define PRS_REG_NUM_OF_PACKETS 0x40124
1999/* [ST 24] The number of input transparent flush packets */
2000#define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES 0x4012c
2001/* [RW 8] Context region for received Ethernet packet with a match and
2002 packet type 0. Used in CFC load request message */
2003#define PRS_REG_PACKET_REGIONS_TYPE_0 0x40028
2004#define PRS_REG_PACKET_REGIONS_TYPE_1 0x4002c
2005#define PRS_REG_PACKET_REGIONS_TYPE_2 0x40030
2006#define PRS_REG_PACKET_REGIONS_TYPE_3 0x40034
2007#define PRS_REG_PACKET_REGIONS_TYPE_4 0x40038
2008#define PRS_REG_PACKET_REGIONS_TYPE_5 0x4003c
2009#define PRS_REG_PACKET_REGIONS_TYPE_6 0x40040
2010#define PRS_REG_PACKET_REGIONS_TYPE_7 0x40044
2011/* [R 2] debug only: Number of pending requests for CAC on port 0. */
2012#define PRS_REG_PENDING_BRB_CAC0_RQ 0x40174
2013/* [R 2] debug only: Number of pending requests for header parsing. */
2014#define PRS_REG_PENDING_BRB_PRS_RQ 0x40170
2015/* [R 1] Interrupt register #0 read */
2016#define PRS_REG_PRS_INT_STS 0x40188
2017/* [RW 8] Parity mask register #0 read/write */
2018#define PRS_REG_PRS_PRTY_MASK 0x401a4
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ET		 2019/* [R 8] Parity register #0 read */
2020#define PRS_REG_PRS_PRTY_STS 0x40198
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ET		 2021/* [RW 8] Context region for pure acknowledge packets. Used in CFC load
2022 request message */
2023#define PRS_REG_PURE_REGIONS 0x40024
2024/* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this
2025 serail number was released by SDM but cannot be used because a previous
2026 serial number was not released. */
2027#define PRS_REG_SERIAL_NUM_STATUS_LSB 0x40154
2028/* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this
2029 serail number was released by SDM but cannot be used because a previous
2030 serial number was not released. */
2031#define PRS_REG_SERIAL_NUM_STATUS_MSB 0x40158
2032/* [R 4] debug only: SRC current credit. Transaction based. */
2033#define PRS_REG_SRC_CURRENT_CREDIT 0x4016c
2034/* [R 8] debug only: TCM current credit. Cycle based. */
2035#define PRS_REG_TCM_CURRENT_CREDIT 0x40160
2036/* [R 8] debug only: TSDM current credit. Transaction based. */
2037#define PRS_REG_TSDM_CURRENT_CREDIT 0x4015c
2038/* [R 6] Debug only: Number of used entries in the data FIFO */
2039#define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c
2040/* [R 7] Debug only: Number of used entries in the header FIFO */
2041#define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478
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EG		 2042#define PXP2_REG_PGL_ADDR_88_F0 0x120534
2043#define PXP2_REG_PGL_ADDR_8C_F0 0x120538
2044#define PXP2_REG_PGL_ADDR_90_F0 0x12053c
2045#define PXP2_REG_PGL_ADDR_94_F0 0x120540
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ET		 2046#define PXP2_REG_PGL_CONTROL0 0x120490
2047#define PXP2_REG_PGL_CONTROL1 0x120514
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YR		 2048/* [RW 32] third dword data of expansion rom request. this register is
2049 special. reading from it provides a vector outstanding read requests. if
2050 a bit is zero it means that a read request on the corresponding tag did
2051 not finish yet (not all completions have arrived for it) */
2052#define PXP2_REG_PGL_EXP_ROM2 0x120808
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ET		 2053/* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask;
2054 its[15:0]-address */
2055#define PXP2_REG_PGL_INT_CSDM_0 0x1204f4
2056#define PXP2_REG_PGL_INT_CSDM_1 0x1204f8
2057#define PXP2_REG_PGL_INT_CSDM_2 0x1204fc
2058#define PXP2_REG_PGL_INT_CSDM_3 0x120500
2059#define PXP2_REG_PGL_INT_CSDM_4 0x120504
2060#define PXP2_REG_PGL_INT_CSDM_5 0x120508
2061#define PXP2_REG_PGL_INT_CSDM_6 0x12050c
2062#define PXP2_REG_PGL_INT_CSDM_7 0x120510
2063/* [RW 32] Inbound interrupt table for TSDM: bits[31:16]-mask;
2064 its[15:0]-address */
2065#define PXP2_REG_PGL_INT_TSDM_0 0x120494
2066#define PXP2_REG_PGL_INT_TSDM_1 0x120498
2067#define PXP2_REG_PGL_INT_TSDM_2 0x12049c
2068#define PXP2_REG_PGL_INT_TSDM_3 0x1204a0
2069#define PXP2_REG_PGL_INT_TSDM_4 0x1204a4
2070#define PXP2_REG_PGL_INT_TSDM_5 0x1204a8
2071#define PXP2_REG_PGL_INT_TSDM_6 0x1204ac
2072#define PXP2_REG_PGL_INT_TSDM_7 0x1204b0
2073/* [RW 32] Inbound interrupt table for USDM: bits[31:16]-mask;
2074 its[15:0]-address */
2075#define PXP2_REG_PGL_INT_USDM_0 0x1204b4
2076#define PXP2_REG_PGL_INT_USDM_1 0x1204b8
2077#define PXP2_REG_PGL_INT_USDM_2 0x1204bc
2078#define PXP2_REG_PGL_INT_USDM_3 0x1204c0
2079#define PXP2_REG_PGL_INT_USDM_4 0x1204c4
2080#define PXP2_REG_PGL_INT_USDM_5 0x1204c8
2081#define PXP2_REG_PGL_INT_USDM_6 0x1204cc
2082#define PXP2_REG_PGL_INT_USDM_7 0x1204d0
2083/* [RW 32] Inbound interrupt table for XSDM: bits[31:16]-mask;
2084 its[15:0]-address */
2085#define PXP2_REG_PGL_INT_XSDM_0 0x1204d4
2086#define PXP2_REG_PGL_INT_XSDM_1 0x1204d8
2087#define PXP2_REG_PGL_INT_XSDM_2 0x1204dc
2088#define PXP2_REG_PGL_INT_XSDM_3 0x1204e0
2089#define PXP2_REG_PGL_INT_XSDM_4 0x1204e4
2090#define PXP2_REG_PGL_INT_XSDM_5 0x1204e8
2091#define PXP2_REG_PGL_INT_XSDM_6 0x1204ec
2092#define PXP2_REG_PGL_INT_XSDM_7 0x1204f0
f1ef27ef
EG		 2093/* [RW 3] this field allows one function to pretend being another function
2094 when accessing any BAR mapped resource within the device. the value of
2095 the field is the number of the function that will be accessed
2096 effectively. after software write to this bit it must read it in order to
2097 know that the new value is updated */
2098#define PXP2_REG_PGL_PRETEND_FUNC_F0 0x120674
2099#define PXP2_REG_PGL_PRETEND_FUNC_F1 0x120678
2100#define PXP2_REG_PGL_PRETEND_FUNC_F2 0x12067c
2101#define PXP2_REG_PGL_PRETEND_FUNC_F3 0x120680
2102#define PXP2_REG_PGL_PRETEND_FUNC_F4 0x120684
2103#define PXP2_REG_PGL_PRETEND_FUNC_F5 0x120688
2104#define PXP2_REG_PGL_PRETEND_FUNC_F6 0x12068c
2105#define PXP2_REG_PGL_PRETEND_FUNC_F7 0x120690
a2fbb9ea
ET		 2106/* [R 1] this bit indicates that a read request was blocked because of
2107 bus_master_en was deasserted */
2108#define PXP2_REG_PGL_READ_BLOCKED 0x120568
c18487ee 2109#define PXP2_REG_PGL_TAGS_LIMIT 0x1205a8
a2fbb9ea
ET		 2110/* [R 18] debug only */
2111#define PXP2_REG_PGL_TXW_CDTS 0x12052c
2112/* [R 1] this bit indicates that a write request was blocked because of
2113 bus_master_en was deasserted */
2114#define PXP2_REG_PGL_WRITE_BLOCKED 0x120564
2115#define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0
2116#define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
2117#define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
2118#define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
2119#define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
2120#define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4
2121#define PXP2_REG_PSWRQ_BW_ADD28 0x120228
2122#define PXP2_REG_PSWRQ_BW_ADD28 0x120228
2123#define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8
2124#define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4
2125#define PXP2_REG_PSWRQ_BW_ADD7 0x1201d8
2126#define PXP2_REG_PSWRQ_BW_ADD8 0x1201dc
2127#define PXP2_REG_PSWRQ_BW_ADD9 0x1201e0
2128#define PXP2_REG_PSWRQ_BW_CREDIT 0x12032c
2129#define PXP2_REG_PSWRQ_BW_L1 0x1202b0
2130#define PXP2_REG_PSWRQ_BW_L10 0x1202d4
2131#define PXP2_REG_PSWRQ_BW_L11 0x1202d8
2132#define PXP2_REG_PSWRQ_BW_L10 0x1202d4
2133#define PXP2_REG_PSWRQ_BW_L11 0x1202d8
2134#define PXP2_REG_PSWRQ_BW_L2 0x1202b4
2135#define PXP2_REG_PSWRQ_BW_L28 0x120318
2136#define PXP2_REG_PSWRQ_BW_L28 0x120318
2137#define PXP2_REG_PSWRQ_BW_L3 0x1202b8
2138#define PXP2_REG_PSWRQ_BW_L6 0x1202c4
2139#define PXP2_REG_PSWRQ_BW_L7 0x1202c8
2140#define PXP2_REG_PSWRQ_BW_L8 0x1202cc
2141#define PXP2_REG_PSWRQ_BW_L9 0x1202d0
2142#define PXP2_REG_PSWRQ_BW_RD 0x120324
2143#define PXP2_REG_PSWRQ_BW_UB1 0x120238
2144#define PXP2_REG_PSWRQ_BW_UB10 0x12025c
2145#define PXP2_REG_PSWRQ_BW_UB11 0x120260
2146#define PXP2_REG_PSWRQ_BW_UB10 0x12025c
2147#define PXP2_REG_PSWRQ_BW_UB11 0x120260
2148#define PXP2_REG_PSWRQ_BW_UB2 0x12023c
2149#define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
2150#define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
2151#define PXP2_REG_PSWRQ_BW_UB3 0x120240
2152#define PXP2_REG_PSWRQ_BW_UB6 0x12024c
2153#define PXP2_REG_PSWRQ_BW_UB7 0x120250
2154#define PXP2_REG_PSWRQ_BW_UB8 0x120254
2155#define PXP2_REG_PSWRQ_BW_UB9 0x120258
2156#define PXP2_REG_PSWRQ_BW_WR 0x120328
2157#define PXP2_REG_PSWRQ_CDU0_L2P 0x120000
2158#define PXP2_REG_PSWRQ_QM0_L2P 0x120038
2159#define PXP2_REG_PSWRQ_SRC0_L2P 0x120054
2160#define PXP2_REG_PSWRQ_TM0_L2P 0x12001c
c18487ee 2161#define PXP2_REG_PSWRQ_TSDM0_L2P 0x1200e0
34f80b04
EG		 2162/* [RW 32] Interrupt mask register #0 read/write */
2163#define PXP2_REG_PXP2_INT_MASK_0 0x120578
2164/* [R 32] Interrupt register #0 read */
2165#define PXP2_REG_PXP2_INT_STS_0 0x12056c
2166#define PXP2_REG_PXP2_INT_STS_1 0x120608
2167/* [RC 32] Interrupt register #0 read clear */
2168#define PXP2_REG_PXP2_INT_STS_CLR_0 0x120570
a2fbb9ea
ET		 2169/* [RW 32] Parity mask register #0 read/write */
2170#define PXP2_REG_PXP2_PRTY_MASK_0 0x120588
2171#define PXP2_REG_PXP2_PRTY_MASK_1 0x120598
f1410647
ET		 2172/* [R 32] Parity register #0 read */
2173#define PXP2_REG_PXP2_PRTY_STS_0 0x12057c
2174#define PXP2_REG_PXP2_PRTY_STS_1 0x12058c
a2fbb9ea
ET		 2175/* [R 1] Debug only: The 'almost full' indication from each fifo (gives
2176 indication about backpressure) */
2177#define PXP2_REG_RD_ALMOST_FULL_0 0x120424
2178/* [R 8] Debug only: The blocks counter - number of unused block ids */
2179#define PXP2_REG_RD_BLK_CNT 0x120418
2180/* [RW 8] Debug only: Total number of available blocks in Tetris Buffer.
2181 Must be bigger than 6. Normally should not be changed. */
2182#define PXP2_REG_RD_BLK_NUM_CFG 0x12040c
2183/* [RW 2] CDU byte swapping mode configuration for master read requests */
2184#define PXP2_REG_RD_CDURD_SWAP_MODE 0x120404
2185/* [RW 1] When '1'; inputs to the PSWRD block are ignored */
2186#define PXP2_REG_RD_DISABLE_INPUTS 0x120374
2187/* [R 1] PSWRD internal memories initialization is done */
2188#define PXP2_REG_RD_INIT_DONE 0x120370
2189/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2190 allocated for vq10 */
2191#define PXP2_REG_RD_MAX_BLKS_VQ10 0x1203a0
2192/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2193 allocated for vq11 */
2194#define PXP2_REG_RD_MAX_BLKS_VQ11 0x1203a4
2195/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2196 allocated for vq17 */
2197#define PXP2_REG_RD_MAX_BLKS_VQ17 0x1203bc
2198/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2199 allocated for vq18 */
2200#define PXP2_REG_RD_MAX_BLKS_VQ18 0x1203c0
2201/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2202 allocated for vq19 */
2203#define PXP2_REG_RD_MAX_BLKS_VQ19 0x1203c4
2204/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2205 allocated for vq22 */
2206#define PXP2_REG_RD_MAX_BLKS_VQ22 0x1203d0
2207/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2208 allocated for vq6 */
2209#define PXP2_REG_RD_MAX_BLKS_VQ6 0x120390
2210/* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2211 allocated for vq9 */
2212#define PXP2_REG_RD_MAX_BLKS_VQ9 0x12039c
2213/* [RW 2] PBF byte swapping mode configuration for master read requests */
2214#define PXP2_REG_RD_PBF_SWAP_MODE 0x1203f4
2215/* [R 1] Debug only: Indication if delivery ports are idle */
2216#define PXP2_REG_RD_PORT_IS_IDLE_0 0x12041c
2217#define PXP2_REG_RD_PORT_IS_IDLE_1 0x120420
2218/* [RW 2] QM byte swapping mode configuration for master read requests */
2219#define PXP2_REG_RD_QM_SWAP_MODE 0x1203f8
2220/* [R 7] Debug only: The SR counter - number of unused sub request ids */
2221#define PXP2_REG_RD_SR_CNT 0x120414
2222/* [RW 2] SRC byte swapping mode configuration for master read requests */
2223#define PXP2_REG_RD_SRC_SWAP_MODE 0x120400
2224/* [RW 7] Debug only: Total number of available PCI read sub-requests. Must
2225 be bigger than 1. Normally should not be changed. */
2226#define PXP2_REG_RD_SR_NUM_CFG 0x120408
2227/* [RW 1] Signals the PSWRD block to start initializing internal memories */
2228#define PXP2_REG_RD_START_INIT 0x12036c
2229/* [RW 2] TM byte swapping mode configuration for master read requests */
2230#define PXP2_REG_RD_TM_SWAP_MODE 0x1203fc
2231/* [RW 10] Bandwidth addition to VQ0 write requests */
2232#define PXP2_REG_RQ_BW_RD_ADD0 0x1201bc
2233/* [RW 10] Bandwidth addition to VQ12 read requests */
2234#define PXP2_REG_RQ_BW_RD_ADD12 0x1201ec
2235/* [RW 10] Bandwidth addition to VQ13 read requests */
2236#define PXP2_REG_RQ_BW_RD_ADD13 0x1201f0
2237/* [RW 10] Bandwidth addition to VQ14 read requests */
2238#define PXP2_REG_RQ_BW_RD_ADD14 0x1201f4
2239/* [RW 10] Bandwidth addition to VQ15 read requests */
2240#define PXP2_REG_RQ_BW_RD_ADD15 0x1201f8
2241/* [RW 10] Bandwidth addition to VQ16 read requests */
2242#define PXP2_REG_RQ_BW_RD_ADD16 0x1201fc
2243/* [RW 10] Bandwidth addition to VQ17 read requests */
2244#define PXP2_REG_RQ_BW_RD_ADD17 0x120200
2245/* [RW 10] Bandwidth addition to VQ18 read requests */
2246#define PXP2_REG_RQ_BW_RD_ADD18 0x120204
2247/* [RW 10] Bandwidth addition to VQ19 read requests */
2248#define PXP2_REG_RQ_BW_RD_ADD19 0x120208
2249/* [RW 10] Bandwidth addition to VQ20 read requests */
2250#define PXP2_REG_RQ_BW_RD_ADD20 0x12020c
2251/* [RW 10] Bandwidth addition to VQ22 read requests */
2252#define PXP2_REG_RQ_BW_RD_ADD22 0x120210
2253/* [RW 10] Bandwidth addition to VQ23 read requests */
2254#define PXP2_REG_RQ_BW_RD_ADD23 0x120214
2255/* [RW 10] Bandwidth addition to VQ24 read requests */
2256#define PXP2_REG_RQ_BW_RD_ADD24 0x120218
2257/* [RW 10] Bandwidth addition to VQ25 read requests */
2258#define PXP2_REG_RQ_BW_RD_ADD25 0x12021c
2259/* [RW 10] Bandwidth addition to VQ26 read requests */
2260#define PXP2_REG_RQ_BW_RD_ADD26 0x120220
2261/* [RW 10] Bandwidth addition to VQ27 read requests */
2262#define PXP2_REG_RQ_BW_RD_ADD27 0x120224
2263/* [RW 10] Bandwidth addition to VQ4 read requests */
2264#define PXP2_REG_RQ_BW_RD_ADD4 0x1201cc
2265/* [RW 10] Bandwidth addition to VQ5 read requests */
2266#define PXP2_REG_RQ_BW_RD_ADD5 0x1201d0
2267/* [RW 10] Bandwidth Typical L for VQ0 Read requests */
2268#define PXP2_REG_RQ_BW_RD_L0 0x1202ac
2269/* [RW 10] Bandwidth Typical L for VQ12 Read requests */
2270#define PXP2_REG_RQ_BW_RD_L12 0x1202dc
2271/* [RW 10] Bandwidth Typical L for VQ13 Read requests */
2272#define PXP2_REG_RQ_BW_RD_L13 0x1202e0
2273/* [RW 10] Bandwidth Typical L for VQ14 Read requests */
2274#define PXP2_REG_RQ_BW_RD_L14 0x1202e4
2275/* [RW 10] Bandwidth Typical L for VQ15 Read requests */
2276#define PXP2_REG_RQ_BW_RD_L15 0x1202e8
2277/* [RW 10] Bandwidth Typical L for VQ16 Read requests */
2278#define PXP2_REG_RQ_BW_RD_L16 0x1202ec
2279/* [RW 10] Bandwidth Typical L for VQ17 Read requests */
2280#define PXP2_REG_RQ_BW_RD_L17 0x1202f0
2281/* [RW 10] Bandwidth Typical L for VQ18 Read requests */
2282#define PXP2_REG_RQ_BW_RD_L18 0x1202f4
2283/* [RW 10] Bandwidth Typical L for VQ19 Read requests */
2284#define PXP2_REG_RQ_BW_RD_L19 0x1202f8
2285/* [RW 10] Bandwidth Typical L for VQ20 Read requests */
2286#define PXP2_REG_RQ_BW_RD_L20 0x1202fc
2287/* [RW 10] Bandwidth Typical L for VQ22 Read requests */
2288#define PXP2_REG_RQ_BW_RD_L22 0x120300
2289/* [RW 10] Bandwidth Typical L for VQ23 Read requests */
2290#define PXP2_REG_RQ_BW_RD_L23 0x120304
2291/* [RW 10] Bandwidth Typical L for VQ24 Read requests */
2292#define PXP2_REG_RQ_BW_RD_L24 0x120308
2293/* [RW 10] Bandwidth Typical L for VQ25 Read requests */
2294#define PXP2_REG_RQ_BW_RD_L25 0x12030c
2295/* [RW 10] Bandwidth Typical L for VQ26 Read requests */
2296#define PXP2_REG_RQ_BW_RD_L26 0x120310
2297/* [RW 10] Bandwidth Typical L for VQ27 Read requests */
2298#define PXP2_REG_RQ_BW_RD_L27 0x120314
2299/* [RW 10] Bandwidth Typical L for VQ4 Read requests */
2300#define PXP2_REG_RQ_BW_RD_L4 0x1202bc
2301/* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */
2302#define PXP2_REG_RQ_BW_RD_L5 0x1202c0
2303/* [RW 7] Bandwidth upper bound for VQ0 read requests */
2304#define PXP2_REG_RQ_BW_RD_UBOUND0 0x120234
2305/* [RW 7] Bandwidth upper bound for VQ12 read requests */
2306#define PXP2_REG_RQ_BW_RD_UBOUND12 0x120264
2307/* [RW 7] Bandwidth upper bound for VQ13 read requests */
2308#define PXP2_REG_RQ_BW_RD_UBOUND13 0x120268
2309/* [RW 7] Bandwidth upper bound for VQ14 read requests */
2310#define PXP2_REG_RQ_BW_RD_UBOUND14 0x12026c
2311/* [RW 7] Bandwidth upper bound for VQ15 read requests */
2312#define PXP2_REG_RQ_BW_RD_UBOUND15 0x120270
2313/* [RW 7] Bandwidth upper bound for VQ16 read requests */
2314#define PXP2_REG_RQ_BW_RD_UBOUND16 0x120274
2315/* [RW 7] Bandwidth upper bound for VQ17 read requests */
2316#define PXP2_REG_RQ_BW_RD_UBOUND17 0x120278
2317/* [RW 7] Bandwidth upper bound for VQ18 read requests */
2318#define PXP2_REG_RQ_BW_RD_UBOUND18 0x12027c
2319/* [RW 7] Bandwidth upper bound for VQ19 read requests */
2320#define PXP2_REG_RQ_BW_RD_UBOUND19 0x120280
2321/* [RW 7] Bandwidth upper bound for VQ20 read requests */
2322#define PXP2_REG_RQ_BW_RD_UBOUND20 0x120284
2323/* [RW 7] Bandwidth upper bound for VQ22 read requests */
2324#define PXP2_REG_RQ_BW_RD_UBOUND22 0x120288
2325/* [RW 7] Bandwidth upper bound for VQ23 read requests */
2326#define PXP2_REG_RQ_BW_RD_UBOUND23 0x12028c
2327/* [RW 7] Bandwidth upper bound for VQ24 read requests */
2328#define PXP2_REG_RQ_BW_RD_UBOUND24 0x120290
2329/* [RW 7] Bandwidth upper bound for VQ25 read requests */
2330#define PXP2_REG_RQ_BW_RD_UBOUND25 0x120294
2331/* [RW 7] Bandwidth upper bound for VQ26 read requests */
2332#define PXP2_REG_RQ_BW_RD_UBOUND26 0x120298
2333/* [RW 7] Bandwidth upper bound for VQ27 read requests */
2334#define PXP2_REG_RQ_BW_RD_UBOUND27 0x12029c
2335/* [RW 7] Bandwidth upper bound for VQ4 read requests */
2336#define PXP2_REG_RQ_BW_RD_UBOUND4 0x120244
2337/* [RW 7] Bandwidth upper bound for VQ5 read requests */
2338#define PXP2_REG_RQ_BW_RD_UBOUND5 0x120248
2339/* [RW 10] Bandwidth addition to VQ29 write requests */
2340#define PXP2_REG_RQ_BW_WR_ADD29 0x12022c
2341/* [RW 10] Bandwidth addition to VQ30 write requests */
2342#define PXP2_REG_RQ_BW_WR_ADD30 0x120230
2343/* [RW 10] Bandwidth Typical L for VQ29 Write requests */
2344#define PXP2_REG_RQ_BW_WR_L29 0x12031c
2345/* [RW 10] Bandwidth Typical L for VQ30 Write requests */
2346#define PXP2_REG_RQ_BW_WR_L30 0x120320
2347/* [RW 7] Bandwidth upper bound for VQ29 */
2348#define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4
2349/* [RW 7] Bandwidth upper bound for VQ30 */
2350#define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8
c18487ee
YR		 2351/* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */
2352#define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR 0x120008
a2fbb9ea
ET		 2353/* [RW 2] Endian mode for cdu */
2354#define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0
c18487ee
YR		 2355#define PXP2_REG_RQ_CDU_FIRST_ILT 0x12061c
2356#define PXP2_REG_RQ_CDU_LAST_ILT 0x120620
a2fbb9ea
ET		 2357/* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k;
2358 -128k */
2359#define PXP2_REG_RQ_CDU_P_SIZE 0x120018
2360/* [R 1] 1' indicates that the requester has finished its internal
2361 configuration */
2362#define PXP2_REG_RQ_CFG_DONE 0x1201b4
2363/* [RW 2] Endian mode for debug */
2364#define PXP2_REG_RQ_DBG_ENDIAN_M 0x1201a4
2365/* [RW 1] When '1'; requests will enter input buffers but wont get out
2366 towards the glue */
2367#define PXP2_REG_RQ_DISABLE_INPUTS 0x120330
c18487ee
YR		 2368/* [RW 1] 1 - SR will be aligned by 64B; 0 - SR will be aligned by 8B */
2369#define PXP2_REG_RQ_DRAM_ALIGN 0x1205b0
2370/* [RW 1] If 1 ILT failiue will not result in ELT access; An interrupt will
2371 be asserted */
2372#define PXP2_REG_RQ_ELT_DISABLE 0x12066c
a2fbb9ea
ET		 2373/* [RW 2] Endian mode for hc */
2374#define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8
c18487ee
YR		 2375/* [RW 1] when '0' ILT logic will work as in A0; otherwise B0; for back
2376 compatibility needs; Note that different registers are used per mode */
2377#define PXP2_REG_RQ_ILT_MODE 0x1205b4
a2fbb9ea
ET		 2378/* [WB 53] Onchip address table */
2379#define PXP2_REG_RQ_ONCHIP_AT 0x122000
c18487ee
YR		 2380/* [WB 53] Onchip address table - B0 */
2381#define PXP2_REG_RQ_ONCHIP_AT_B0 0x128000
f1410647
ET		 2382/* [RW 13] Pending read limiter threshold; in Dwords */
2383#define PXP2_REG_RQ_PDR_LIMIT 0x12033c
a2fbb9ea
ET		 2384/* [RW 2] Endian mode for qm */
2385#define PXP2_REG_RQ_QM_ENDIAN_M 0x120194
c18487ee
YR		 2386#define PXP2_REG_RQ_QM_FIRST_ILT 0x120634
2387#define PXP2_REG_RQ_QM_LAST_ILT 0x120638
a2fbb9ea
ET		 2388/* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k;
2389 -128k */
2390#define PXP2_REG_RQ_QM_P_SIZE 0x120050
33471629 2391/* [RW 1] 1' indicates that the RBC has finished configuring the PSWRQ */
a2fbb9ea
ET		 2392#define PXP2_REG_RQ_RBC_DONE 0x1201b0
2393/* [RW 3] Max burst size filed for read requests port 0; 000 - 128B;
2394 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
2395#define PXP2_REG_RQ_RD_MBS0 0x120160
f1410647
ET		 2396/* [RW 3] Max burst size filed for read requests port 1; 000 - 128B;
2397 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
2398#define PXP2_REG_RQ_RD_MBS1 0x120168
a2fbb9ea
ET		 2399/* [RW 2] Endian mode for src */
2400#define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c
c18487ee
YR		 2401#define PXP2_REG_RQ_SRC_FIRST_ILT 0x12063c
2402#define PXP2_REG_RQ_SRC_LAST_ILT 0x120640
a2fbb9ea
ET		 2403/* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k;
2404 -128k */
2405#define PXP2_REG_RQ_SRC_P_SIZE 0x12006c
2406/* [RW 2] Endian mode for tm */
2407#define PXP2_REG_RQ_TM_ENDIAN_M 0x120198
c18487ee
YR		 2408#define PXP2_REG_RQ_TM_FIRST_ILT 0x120644
2409#define PXP2_REG_RQ_TM_LAST_ILT 0x120648
a2fbb9ea
ET		 2410/* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k;
2411 -128k */
2412#define PXP2_REG_RQ_TM_P_SIZE 0x120034
2413/* [R 5] Number of entries in the ufifo; his fifo has l2p completions */
2414#define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c
c18487ee
YR		 2415/* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */
2416#define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR 0x120094
a2fbb9ea
ET		 2417/* [R 8] Number of entries occupied by vq 0 in pswrq memory */
2418#define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810
2419/* [R 8] Number of entries occupied by vq 10 in pswrq memory */
2420#define PXP2_REG_RQ_VQ10_ENTRY_CNT 0x120818
2421/* [R 8] Number of entries occupied by vq 11 in pswrq memory */
2422#define PXP2_REG_RQ_VQ11_ENTRY_CNT 0x120820
2423/* [R 8] Number of entries occupied by vq 12 in pswrq memory */
2424#define PXP2_REG_RQ_VQ12_ENTRY_CNT 0x120828
2425/* [R 8] Number of entries occupied by vq 13 in pswrq memory */
2426#define PXP2_REG_RQ_VQ13_ENTRY_CNT 0x120830
2427/* [R 8] Number of entries occupied by vq 14 in pswrq memory */
2428#define PXP2_REG_RQ_VQ14_ENTRY_CNT 0x120838
2429/* [R 8] Number of entries occupied by vq 15 in pswrq memory */
2430#define PXP2_REG_RQ_VQ15_ENTRY_CNT 0x120840
2431/* [R 8] Number of entries occupied by vq 16 in pswrq memory */
2432#define PXP2_REG_RQ_VQ16_ENTRY_CNT 0x120848
2433/* [R 8] Number of entries occupied by vq 17 in pswrq memory */
2434#define PXP2_REG_RQ_VQ17_ENTRY_CNT 0x120850
2435/* [R 8] Number of entries occupied by vq 18 in pswrq memory */
2436#define PXP2_REG_RQ_VQ18_ENTRY_CNT 0x120858
2437/* [R 8] Number of entries occupied by vq 19 in pswrq memory */
2438#define PXP2_REG_RQ_VQ19_ENTRY_CNT 0x120860
2439/* [R 8] Number of entries occupied by vq 1 in pswrq memory */
2440#define PXP2_REG_RQ_VQ1_ENTRY_CNT 0x120868
2441/* [R 8] Number of entries occupied by vq 20 in pswrq memory */
2442#define PXP2_REG_RQ_VQ20_ENTRY_CNT 0x120870
2443/* [R 8] Number of entries occupied by vq 21 in pswrq memory */
2444#define PXP2_REG_RQ_VQ21_ENTRY_CNT 0x120878
2445/* [R 8] Number of entries occupied by vq 22 in pswrq memory */
2446#define PXP2_REG_RQ_VQ22_ENTRY_CNT 0x120880
2447/* [R 8] Number of entries occupied by vq 23 in pswrq memory */
2448#define PXP2_REG_RQ_VQ23_ENTRY_CNT 0x120888
2449/* [R 8] Number of entries occupied by vq 24 in pswrq memory */
2450#define PXP2_REG_RQ_VQ24_ENTRY_CNT 0x120890
2451/* [R 8] Number of entries occupied by vq 25 in pswrq memory */
2452#define PXP2_REG_RQ_VQ25_ENTRY_CNT 0x120898
2453/* [R 8] Number of entries occupied by vq 26 in pswrq memory */
2454#define PXP2_REG_RQ_VQ26_ENTRY_CNT 0x1208a0
2455/* [R 8] Number of entries occupied by vq 27 in pswrq memory */
2456#define PXP2_REG_RQ_VQ27_ENTRY_CNT 0x1208a8
2457/* [R 8] Number of entries occupied by vq 28 in pswrq memory */
2458#define PXP2_REG_RQ_VQ28_ENTRY_CNT 0x1208b0
2459/* [R 8] Number of entries occupied by vq 29 in pswrq memory */
2460#define PXP2_REG_RQ_VQ29_ENTRY_CNT 0x1208b8
2461/* [R 8] Number of entries occupied by vq 2 in pswrq memory */
2462#define PXP2_REG_RQ_VQ2_ENTRY_CNT 0x1208c0
2463/* [R 8] Number of entries occupied by vq 30 in pswrq memory */
2464#define PXP2_REG_RQ_VQ30_ENTRY_CNT 0x1208c8
2465/* [R 8] Number of entries occupied by vq 31 in pswrq memory */
2466#define PXP2_REG_RQ_VQ31_ENTRY_CNT 0x1208d0
2467/* [R 8] Number of entries occupied by vq 3 in pswrq memory */
2468#define PXP2_REG_RQ_VQ3_ENTRY_CNT 0x1208d8
2469/* [R 8] Number of entries occupied by vq 4 in pswrq memory */
2470#define PXP2_REG_RQ_VQ4_ENTRY_CNT 0x1208e0
2471/* [R 8] Number of entries occupied by vq 5 in pswrq memory */
2472#define PXP2_REG_RQ_VQ5_ENTRY_CNT 0x1208e8
2473/* [R 8] Number of entries occupied by vq 6 in pswrq memory */
2474#define PXP2_REG_RQ_VQ6_ENTRY_CNT 0x1208f0
2475/* [R 8] Number of entries occupied by vq 7 in pswrq memory */
2476#define PXP2_REG_RQ_VQ7_ENTRY_CNT 0x1208f8
2477/* [R 8] Number of entries occupied by vq 8 in pswrq memory */
2478#define PXP2_REG_RQ_VQ8_ENTRY_CNT 0x120900
2479/* [R 8] Number of entries occupied by vq 9 in pswrq memory */
2480#define PXP2_REG_RQ_VQ9_ENTRY_CNT 0x120908
2481/* [RW 3] Max burst size filed for write requests port 0; 000 - 128B;
2482 001:256B; 010: 512B; */
2483#define PXP2_REG_RQ_WR_MBS0 0x12015c
f1410647
ET		 2484/* [RW 3] Max burst size filed for write requests port 1; 000 - 128B;
2485 001:256B; 010: 512B; */
2486#define PXP2_REG_RQ_WR_MBS1 0x120164
c18487ee
YR		 2487/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2488 buffer reaches this number has_payload will be asserted */
2489#define PXP2_REG_WR_CDU_MPS 0x1205f0
2490/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2491 buffer reaches this number has_payload will be asserted */
2492#define PXP2_REG_WR_CSDM_MPS 0x1205d0
2493/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2494 buffer reaches this number has_payload will be asserted */
2495#define PXP2_REG_WR_DBG_MPS 0x1205e8
2496/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2497 buffer reaches this number has_payload will be asserted */
2498#define PXP2_REG_WR_DMAE_MPS 0x1205ec
33471629 2499/* [RW 10] if Number of entries in dmae fifo will be higher than this
a2fbb9ea
ET		 2500 threshold then has_payload indication will be asserted; the default value
2501 should be equal to &gt; write MBS size! */
2502#define PXP2_REG_WR_DMAE_TH 0x120368
c18487ee
YR		 2503/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2504 buffer reaches this number has_payload will be asserted */
2505#define PXP2_REG_WR_HC_MPS 0x1205c8
2506/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2507 buffer reaches this number has_payload will be asserted */
2508#define PXP2_REG_WR_QM_MPS 0x1205dc
2509/* [RW 1] 0 - working in A0 mode; - working in B0 mode */
2510#define PXP2_REG_WR_REV_MODE 0x120670
2511/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2512 buffer reaches this number has_payload will be asserted */
2513#define PXP2_REG_WR_SRC_MPS 0x1205e4
2514/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2515 buffer reaches this number has_payload will be asserted */
2516#define PXP2_REG_WR_TM_MPS 0x1205e0
2517/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2518 buffer reaches this number has_payload will be asserted */
2519#define PXP2_REG_WR_TSDM_MPS 0x1205d4
33471629 2520/* [RW 10] if Number of entries in usdmdp fifo will be higher than this
f1410647
ET		 2521 threshold then has_payload indication will be asserted; the default value
2522 should be equal to &gt; write MBS size! */
2523#define PXP2_REG_WR_USDMDP_TH 0x120348
c18487ee
YR		 2524/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2525 buffer reaches this number has_payload will be asserted */
2526#define PXP2_REG_WR_USDM_MPS 0x1205cc
2527/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2528 buffer reaches this number has_payload will be asserted */
2529#define PXP2_REG_WR_XSDM_MPS 0x1205d8
a2fbb9ea
ET		 2530/* [R 1] debug only: Indication if PSWHST arbiter is idle */
2531#define PXP_REG_HST_ARB_IS_IDLE 0x103004
2532/* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means
2533 this client is waiting for the arbiter. */
2534#define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008
c18487ee
YR		 2535/* [R 1] debug only: '1' means this PSWHST is discarding doorbells. This bit
2536 should update accoring to 'hst_discard_doorbells' register when the state
2537 machine is idle */
2538#define PXP_REG_HST_DISCARD_DOORBELLS_STATUS 0x1030a0
2539/* [R 6] debug only: A bit mask for all PSWHST internal write clients. '1'
2540 means this PSWHST is discarding inputs from this client. Each bit should
2541 update accoring to 'hst_discard_internal_writes' register when the state
2542 machine is idle. */
2543#define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS 0x10309c
a2fbb9ea
ET		 2544/* [WB 160] Used for initialization of the inbound interrupts memory */
2545#define PXP_REG_HST_INBOUND_INT 0x103800
2546/* [RW 32] Interrupt mask register #0 read/write */
2547#define PXP_REG_PXP_INT_MASK_0 0x103074
2548#define PXP_REG_PXP_INT_MASK_1 0x103084
2549/* [R 32] Interrupt register #0 read */
2550#define PXP_REG_PXP_INT_STS_0 0x103068
2551#define PXP_REG_PXP_INT_STS_1 0x103078
2552/* [RC 32] Interrupt register #0 read clear */
2553#define PXP_REG_PXP_INT_STS_CLR_0 0x10306c
2554/* [RW 26] Parity mask register #0 read/write */
2555#define PXP_REG_PXP_PRTY_MASK 0x103094
f1410647
ET		 2556/* [R 26] Parity register #0 read */
2557#define PXP_REG_PXP_PRTY_STS 0x103088
a2fbb9ea
ET		 2558/* [RW 4] The activity counter initial increment value sent in the load
2559 request */
2560#define QM_REG_ACTCTRINITVAL_0 0x168040
2561#define QM_REG_ACTCTRINITVAL_1 0x168044
2562#define QM_REG_ACTCTRINITVAL_2 0x168048
2563#define QM_REG_ACTCTRINITVAL_3 0x16804c
2564/* [RW 32] The base logical address (in bytes) of each physical queue. The
2565 index I represents the physical queue number. The 12 lsbs are ignore and
c18487ee
YR		 2566 considered zero so practically there are only 20 bits in this register;
2567 queues 63-0 */
a2fbb9ea 2568#define QM_REG_BASEADDR 0x168900
8d9c5f34
EG		 2569/* [RW 32] The base logical address (in bytes) of each physical queue. The
2570 index I represents the physical queue number. The 12 lsbs are ignore and
2571 considered zero so practically there are only 20 bits in this register;
2572 queues 127-64 */
2573#define QM_REG_BASEADDR_EXT_A 0x16e100
a2fbb9ea
ET		 2574/* [RW 16] The byte credit cost for each task. This value is for both ports */
2575#define QM_REG_BYTECRDCOST 0x168234
2576/* [RW 16] The initial byte credit value for both ports. */
2577#define QM_REG_BYTECRDINITVAL 0x168238
2578/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
c18487ee 2579 queue uses port 0 else it uses port 1; queues 31-0 */
a2fbb9ea
ET		 2580#define QM_REG_BYTECRDPORT_LSB 0x168228
2581/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
c18487ee
YR		 2582 queue uses port 0 else it uses port 1; queues 95-64 */
2583#define QM_REG_BYTECRDPORT_LSB_EXT_A 0x16e520
2584/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
2585 queue uses port 0 else it uses port 1; queues 63-32 */
a2fbb9ea 2586#define QM_REG_BYTECRDPORT_MSB 0x168224
c18487ee
YR		 2587/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
2588 queue uses port 0 else it uses port 1; queues 127-96 */
2589#define QM_REG_BYTECRDPORT_MSB_EXT_A 0x16e51c
a2fbb9ea
ET		 2590/* [RW 16] The byte credit value that if above the QM is considered almost
2591 full */
2592#define QM_REG_BYTECREDITAFULLTHR 0x168094
2593/* [RW 4] The initial credit for interface */
2594#define QM_REG_CMINITCRD_0 0x1680cc
2595#define QM_REG_CMINITCRD_1 0x1680d0
2596#define QM_REG_CMINITCRD_2 0x1680d4
2597#define QM_REG_CMINITCRD_3 0x1680d8
2598#define QM_REG_CMINITCRD_4 0x1680dc
2599#define QM_REG_CMINITCRD_5 0x1680e0
2600#define QM_REG_CMINITCRD_6 0x1680e4
2601#define QM_REG_CMINITCRD_7 0x1680e8
2602/* [RW 8] A mask bit per CM interface. If this bit is 0 then this interface
2603 is masked */
2604#define QM_REG_CMINTEN 0x1680ec
2605/* [RW 12] A bit vector which indicates which one of the queues are tied to
2606 interface 0 */
2607#define QM_REG_CMINTVOQMASK_0 0x1681f4
2608#define QM_REG_CMINTVOQMASK_1 0x1681f8
2609#define QM_REG_CMINTVOQMASK_2 0x1681fc
2610#define QM_REG_CMINTVOQMASK_3 0x168200
2611#define QM_REG_CMINTVOQMASK_4 0x168204
2612#define QM_REG_CMINTVOQMASK_5 0x168208
2613#define QM_REG_CMINTVOQMASK_6 0x16820c
2614#define QM_REG_CMINTVOQMASK_7 0x168210
2615/* [RW 20] The number of connections divided by 16 which dictates the size
c18487ee 2616 of each queue which belongs to even function number. */
a2fbb9ea
ET		 2617#define QM_REG_CONNNUM_0 0x168020
2618/* [R 6] Keep the fill level of the fifo from write client 4 */
2619#define QM_REG_CQM_WRC_FIFOLVL 0x168018
2620/* [RW 8] The context regions sent in the CFC load request */
2621#define QM_REG_CTXREG_0 0x168030
2622#define QM_REG_CTXREG_1 0x168034
2623#define QM_REG_CTXREG_2 0x168038
2624#define QM_REG_CTXREG_3 0x16803c
2625/* [RW 12] The VOQ mask used to select the VOQs which needs to be full for
2626 bypass enable */
2627#define QM_REG_ENBYPVOQMASK 0x16823c
2628/* [RW 32] A bit mask per each physical queue. If a bit is set then the
c18487ee 2629 physical queue uses the byte credit; queues 31-0 */
a2fbb9ea
ET		 2630#define QM_REG_ENBYTECRD_LSB 0x168220
2631/* [RW 32] A bit mask per each physical queue. If a bit is set then the
c18487ee
YR		 2632 physical queue uses the byte credit; queues 95-64 */
2633#define QM_REG_ENBYTECRD_LSB_EXT_A 0x16e518
2634/* [RW 32] A bit mask per each physical queue. If a bit is set then the
2635 physical queue uses the byte credit; queues 63-32 */
a2fbb9ea 2636#define QM_REG_ENBYTECRD_MSB 0x16821c
c18487ee
YR		 2637/* [RW 32] A bit mask per each physical queue. If a bit is set then the
2638 physical queue uses the byte credit; queues 127-96 */
2639#define QM_REG_ENBYTECRD_MSB_EXT_A 0x16e514
a2fbb9ea
ET		 2640/* [RW 4] If cleared then the secondary interface will not be served by the
2641 RR arbiter */
2642#define QM_REG_ENSEC 0x1680f0
c18487ee 2643/* [RW 32] NA */
a2fbb9ea 2644#define QM_REG_FUNCNUMSEL_LSB 0x168230
c18487ee 2645/* [RW 32] NA */
a2fbb9ea
ET		 2646#define QM_REG_FUNCNUMSEL_MSB 0x16822c
2647/* [RW 32] A mask register to mask the Almost empty signals which will not
c18487ee 2648 be use for the almost empty indication to the HW block; queues 31:0 */
a2fbb9ea
ET		 2649#define QM_REG_HWAEMPTYMASK_LSB 0x168218
2650/* [RW 32] A mask register to mask the Almost empty signals which will not
c18487ee
YR		 2651 be use for the almost empty indication to the HW block; queues 95-64 */
2652#define QM_REG_HWAEMPTYMASK_LSB_EXT_A 0x16e510
2653/* [RW 32] A mask register to mask the Almost empty signals which will not
2654 be use for the almost empty indication to the HW block; queues 63:32 */
a2fbb9ea 2655#define QM_REG_HWAEMPTYMASK_MSB 0x168214
c18487ee
YR		 2656/* [RW 32] A mask register to mask the Almost empty signals which will not
2657 be use for the almost empty indication to the HW block; queues 127-96 */
2658#define QM_REG_HWAEMPTYMASK_MSB_EXT_A 0x16e50c
a2fbb9ea
ET		 2659/* [RW 4] The number of outstanding request to CFC */
2660#define QM_REG_OUTLDREQ 0x168804
2661/* [RC 1] A flag to indicate that overflow error occurred in one of the
2662 queues. */
2663#define QM_REG_OVFERROR 0x16805c
c18487ee 2664/* [RC 7] the Q were the qverflow occurs */
a2fbb9ea 2665#define QM_REG_OVFQNUM 0x168058
c18487ee 2666/* [R 16] Pause state for physical queues 15-0 */
a2fbb9ea 2667#define QM_REG_PAUSESTATE0 0x168410
c18487ee 2668/* [R 16] Pause state for physical queues 31-16 */
a2fbb9ea 2669#define QM_REG_PAUSESTATE1 0x168414
c18487ee
YR		 2670/* [R 16] Pause state for physical queues 47-32 */
2671#define QM_REG_PAUSESTATE2 0x16e684
2672/* [R 16] Pause state for physical queues 63-48 */
2673#define QM_REG_PAUSESTATE3 0x16e688
2674/* [R 16] Pause state for physical queues 79-64 */
2675#define QM_REG_PAUSESTATE4 0x16e68c
2676/* [R 16] Pause state for physical queues 95-80 */
2677#define QM_REG_PAUSESTATE5 0x16e690
2678/* [R 16] Pause state for physical queues 111-96 */
2679#define QM_REG_PAUSESTATE6 0x16e694
2680/* [R 16] Pause state for physical queues 127-112 */
2681#define QM_REG_PAUSESTATE7 0x16e698
a2fbb9ea
ET		 2682/* [RW 2] The PCI attributes field used in the PCI request. */
2683#define QM_REG_PCIREQAT 0x168054
2684/* [R 16] The byte credit of port 0 */
2685#define QM_REG_PORT0BYTECRD 0x168300
2686/* [R 16] The byte credit of port 1 */
2687#define QM_REG_PORT1BYTECRD 0x168304
c18487ee
YR		 2688/* [RW 3] pci function number of queues 15-0 */
2689#define QM_REG_PQ2PCIFUNC_0 0x16e6bc
2690#define QM_REG_PQ2PCIFUNC_1 0x16e6c0
2691#define QM_REG_PQ2PCIFUNC_2 0x16e6c4
2692#define QM_REG_PQ2PCIFUNC_3 0x16e6c8
2693#define QM_REG_PQ2PCIFUNC_4 0x16e6cc
2694#define QM_REG_PQ2PCIFUNC_5 0x16e6d0
2695#define QM_REG_PQ2PCIFUNC_6 0x16e6d4
2696#define QM_REG_PQ2PCIFUNC_7 0x16e6d8
2697/* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow:
2698 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
2699 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
a2fbb9ea 2700#define QM_REG_PTRTBL 0x168a00
c18487ee
YR		 2701/* [WB 54] Pointer Table Memory for queues 127-64; The mapping is as follow:
2702 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
2703 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
2704#define QM_REG_PTRTBL_EXT_A 0x16e200
a2fbb9ea
ET		 2705/* [RW 2] Interrupt mask register #0 read/write */
2706#define QM_REG_QM_INT_MASK 0x168444
2707/* [R 2] Interrupt register #0 read */
2708#define QM_REG_QM_INT_STS 0x168438
c18487ee 2709/* [RW 12] Parity mask register #0 read/write */
a2fbb9ea 2710#define QM_REG_QM_PRTY_MASK 0x168454
c18487ee 2711/* [R 12] Parity register #0 read */
f1410647 2712#define QM_REG_QM_PRTY_STS 0x168448
a2fbb9ea
ET		 2713/* [R 32] Current queues in pipeline: Queues from 32 to 63 */
2714#define QM_REG_QSTATUS_HIGH 0x16802c
c18487ee
YR		 2715/* [R 32] Current queues in pipeline: Queues from 96 to 127 */
2716#define QM_REG_QSTATUS_HIGH_EXT_A 0x16e408
a2fbb9ea
ET		 2717/* [R 32] Current queues in pipeline: Queues from 0 to 31 */
2718#define QM_REG_QSTATUS_LOW 0x168028
c18487ee
YR		 2719/* [R 32] Current queues in pipeline: Queues from 64 to 95 */
2720#define QM_REG_QSTATUS_LOW_EXT_A 0x16e404
2721/* [R 24] The number of tasks queued for each queue; queues 63-0 */
a2fbb9ea 2722#define QM_REG_QTASKCTR_0 0x168308
c18487ee
YR		 2723/* [R 24] The number of tasks queued for each queue; queues 127-64 */
2724#define QM_REG_QTASKCTR_EXT_A_0 0x16e584
a2fbb9ea
ET		 2725/* [RW 4] Queue tied to VOQ */
2726#define QM_REG_QVOQIDX_0 0x1680f4
2727#define QM_REG_QVOQIDX_10 0x16811c
c18487ee
YR		 2728#define QM_REG_QVOQIDX_100 0x16e49c
2729#define QM_REG_QVOQIDX_101 0x16e4a0
2730#define QM_REG_QVOQIDX_102 0x16e4a4
2731#define QM_REG_QVOQIDX_103 0x16e4a8
2732#define QM_REG_QVOQIDX_104 0x16e4ac
2733#define QM_REG_QVOQIDX_105 0x16e4b0
2734#define QM_REG_QVOQIDX_106 0x16e4b4
2735#define QM_REG_QVOQIDX_107 0x16e4b8
2736#define QM_REG_QVOQIDX_108 0x16e4bc
2737#define QM_REG_QVOQIDX_109 0x16e4c0
2738#define QM_REG_QVOQIDX_100 0x16e49c
2739#define QM_REG_QVOQIDX_101 0x16e4a0
2740#define QM_REG_QVOQIDX_102 0x16e4a4
2741#define QM_REG_QVOQIDX_103 0x16e4a8
2742#define QM_REG_QVOQIDX_104 0x16e4ac
2743#define QM_REG_QVOQIDX_105 0x16e4b0
2744#define QM_REG_QVOQIDX_106 0x16e4b4
2745#define QM_REG_QVOQIDX_107 0x16e4b8
2746#define QM_REG_QVOQIDX_108 0x16e4bc
2747#define QM_REG_QVOQIDX_109 0x16e4c0
a2fbb9ea 2748#define QM_REG_QVOQIDX_11 0x168120
c18487ee
YR		 2749#define QM_REG_QVOQIDX_110 0x16e4c4
2750#define QM_REG_QVOQIDX_111 0x16e4c8
2751#define QM_REG_QVOQIDX_112 0x16e4cc
2752#define QM_REG_QVOQIDX_113 0x16e4d0
2753#define QM_REG_QVOQIDX_114 0x16e4d4
2754#define QM_REG_QVOQIDX_115 0x16e4d8
2755#define QM_REG_QVOQIDX_116 0x16e4dc
2756#define QM_REG_QVOQIDX_117 0x16e4e0
2757#define QM_REG_QVOQIDX_118 0x16e4e4
2758#define QM_REG_QVOQIDX_119 0x16e4e8
2759#define QM_REG_QVOQIDX_110 0x16e4c4
2760#define QM_REG_QVOQIDX_111 0x16e4c8
2761#define QM_REG_QVOQIDX_112 0x16e4cc
2762#define QM_REG_QVOQIDX_113 0x16e4d0
2763#define QM_REG_QVOQIDX_114 0x16e4d4
2764#define QM_REG_QVOQIDX_115 0x16e4d8
2765#define QM_REG_QVOQIDX_116 0x16e4dc
2766#define QM_REG_QVOQIDX_117 0x16e4e0
2767#define QM_REG_QVOQIDX_118 0x16e4e4
2768#define QM_REG_QVOQIDX_119 0x16e4e8
a2fbb9ea 2769#define QM_REG_QVOQIDX_12 0x168124
c18487ee
YR		 2770#define QM_REG_QVOQIDX_120 0x16e4ec
2771#define QM_REG_QVOQIDX_121 0x16e4f0
2772#define QM_REG_QVOQIDX_122 0x16e4f4
2773#define QM_REG_QVOQIDX_123 0x16e4f8
2774#define QM_REG_QVOQIDX_124 0x16e4fc
2775#define QM_REG_QVOQIDX_125 0x16e500
2776#define QM_REG_QVOQIDX_126 0x16e504
2777#define QM_REG_QVOQIDX_127 0x16e508
2778#define QM_REG_QVOQIDX_120 0x16e4ec
2779#define QM_REG_QVOQIDX_121 0x16e4f0
2780#define QM_REG_QVOQIDX_122 0x16e4f4
2781#define QM_REG_QVOQIDX_123 0x16e4f8
2782#define QM_REG_QVOQIDX_124 0x16e4fc
2783#define QM_REG_QVOQIDX_125 0x16e500
2784#define QM_REG_QVOQIDX_126 0x16e504
2785#define QM_REG_QVOQIDX_127 0x16e508
a2fbb9ea
ET		 2786#define QM_REG_QVOQIDX_13 0x168128
2787#define QM_REG_QVOQIDX_14 0x16812c
2788#define QM_REG_QVOQIDX_15 0x168130
2789#define QM_REG_QVOQIDX_16 0x168134
2790#define QM_REG_QVOQIDX_17 0x168138
2791#define QM_REG_QVOQIDX_21 0x168148
c18487ee
YR		 2792#define QM_REG_QVOQIDX_22 0x16814c
2793#define QM_REG_QVOQIDX_23 0x168150
2794#define QM_REG_QVOQIDX_24 0x168154
a2fbb9ea 2795#define QM_REG_QVOQIDX_25 0x168158
c18487ee
YR		 2796#define QM_REG_QVOQIDX_26 0x16815c
2797#define QM_REG_QVOQIDX_27 0x168160
2798#define QM_REG_QVOQIDX_28 0x168164
a2fbb9ea 2799#define QM_REG_QVOQIDX_29 0x168168
c18487ee
YR		 2800#define QM_REG_QVOQIDX_30 0x16816c
2801#define QM_REG_QVOQIDX_31 0x168170
a2fbb9ea
ET		 2802#define QM_REG_QVOQIDX_32 0x168174
2803#define QM_REG_QVOQIDX_33 0x168178
2804#define QM_REG_QVOQIDX_34 0x16817c
2805#define QM_REG_QVOQIDX_35 0x168180
2806#define QM_REG_QVOQIDX_36 0x168184
2807#define QM_REG_QVOQIDX_37 0x168188
2808#define QM_REG_QVOQIDX_38 0x16818c
2809#define QM_REG_QVOQIDX_39 0x168190
2810#define QM_REG_QVOQIDX_40 0x168194
2811#define QM_REG_QVOQIDX_41 0x168198
2812#define QM_REG_QVOQIDX_42 0x16819c
2813#define QM_REG_QVOQIDX_43 0x1681a0
2814#define QM_REG_QVOQIDX_44 0x1681a4
2815#define QM_REG_QVOQIDX_45 0x1681a8
2816#define QM_REG_QVOQIDX_46 0x1681ac
2817#define QM_REG_QVOQIDX_47 0x1681b0
2818#define QM_REG_QVOQIDX_48 0x1681b4
2819#define QM_REG_QVOQIDX_49 0x1681b8
2820#define QM_REG_QVOQIDX_5 0x168108
2821#define QM_REG_QVOQIDX_50 0x1681bc
2822#define QM_REG_QVOQIDX_51 0x1681c0
2823#define QM_REG_QVOQIDX_52 0x1681c4
2824#define QM_REG_QVOQIDX_53 0x1681c8
2825#define QM_REG_QVOQIDX_54 0x1681cc
2826#define QM_REG_QVOQIDX_55 0x1681d0
2827#define QM_REG_QVOQIDX_56 0x1681d4
2828#define QM_REG_QVOQIDX_57 0x1681d8
2829#define QM_REG_QVOQIDX_58 0x1681dc
2830#define QM_REG_QVOQIDX_59 0x1681e0
2831#define QM_REG_QVOQIDX_50 0x1681bc
2832#define QM_REG_QVOQIDX_51 0x1681c0
2833#define QM_REG_QVOQIDX_52 0x1681c4
2834#define QM_REG_QVOQIDX_53 0x1681c8
2835#define QM_REG_QVOQIDX_54 0x1681cc
2836#define QM_REG_QVOQIDX_55 0x1681d0
2837#define QM_REG_QVOQIDX_56 0x1681d4
2838#define QM_REG_QVOQIDX_57 0x1681d8
2839#define QM_REG_QVOQIDX_58 0x1681dc
2840#define QM_REG_QVOQIDX_59 0x1681e0
2841#define QM_REG_QVOQIDX_6 0x16810c
2842#define QM_REG_QVOQIDX_60 0x1681e4
2843#define QM_REG_QVOQIDX_61 0x1681e8
2844#define QM_REG_QVOQIDX_62 0x1681ec
2845#define QM_REG_QVOQIDX_63 0x1681f0
c18487ee
YR		 2846#define QM_REG_QVOQIDX_64 0x16e40c
2847#define QM_REG_QVOQIDX_65 0x16e410
2848#define QM_REG_QVOQIDX_66 0x16e414
2849#define QM_REG_QVOQIDX_67 0x16e418
2850#define QM_REG_QVOQIDX_68 0x16e41c
2851#define QM_REG_QVOQIDX_69 0x16e420
a2fbb9ea
ET		 2852#define QM_REG_QVOQIDX_60 0x1681e4
2853#define QM_REG_QVOQIDX_61 0x1681e8
2854#define QM_REG_QVOQIDX_62 0x1681ec
2855#define QM_REG_QVOQIDX_63 0x1681f0
c18487ee
YR		 2856#define QM_REG_QVOQIDX_64 0x16e40c
2857#define QM_REG_QVOQIDX_65 0x16e410
2858#define QM_REG_QVOQIDX_69 0x16e420
a2fbb9ea 2859#define QM_REG_QVOQIDX_7 0x168110
c18487ee
YR		 2860#define QM_REG_QVOQIDX_70 0x16e424
2861#define QM_REG_QVOQIDX_71 0x16e428
2862#define QM_REG_QVOQIDX_72 0x16e42c
2863#define QM_REG_QVOQIDX_73 0x16e430
2864#define QM_REG_QVOQIDX_74 0x16e434
2865#define QM_REG_QVOQIDX_75 0x16e438
2866#define QM_REG_QVOQIDX_76 0x16e43c
2867#define QM_REG_QVOQIDX_77 0x16e440
2868#define QM_REG_QVOQIDX_78 0x16e444
2869#define QM_REG_QVOQIDX_79 0x16e448
2870#define QM_REG_QVOQIDX_70 0x16e424
2871#define QM_REG_QVOQIDX_71 0x16e428
2872#define QM_REG_QVOQIDX_72 0x16e42c
2873#define QM_REG_QVOQIDX_73 0x16e430
2874#define QM_REG_QVOQIDX_74 0x16e434
2875#define QM_REG_QVOQIDX_75 0x16e438
2876#define QM_REG_QVOQIDX_76 0x16e43c
2877#define QM_REG_QVOQIDX_77 0x16e440
2878#define QM_REG_QVOQIDX_78 0x16e444
2879#define QM_REG_QVOQIDX_79 0x16e448
a2fbb9ea 2880#define QM_REG_QVOQIDX_8 0x168114
c18487ee
YR		 2881#define QM_REG_QVOQIDX_80 0x16e44c
2882#define QM_REG_QVOQIDX_81 0x16e450
2883#define QM_REG_QVOQIDX_82 0x16e454
2884#define QM_REG_QVOQIDX_83 0x16e458
2885#define QM_REG_QVOQIDX_84 0x16e45c
2886#define QM_REG_QVOQIDX_85 0x16e460
2887#define QM_REG_QVOQIDX_86 0x16e464
2888#define QM_REG_QVOQIDX_87 0x16e468
2889#define QM_REG_QVOQIDX_88 0x16e46c
2890#define QM_REG_QVOQIDX_89 0x16e470
2891#define QM_REG_QVOQIDX_80 0x16e44c
2892#define QM_REG_QVOQIDX_81 0x16e450
2893#define QM_REG_QVOQIDX_85 0x16e460
2894#define QM_REG_QVOQIDX_86 0x16e464
2895#define QM_REG_QVOQIDX_87 0x16e468
2896#define QM_REG_QVOQIDX_88 0x16e46c
2897#define QM_REG_QVOQIDX_89 0x16e470
a2fbb9ea 2898#define QM_REG_QVOQIDX_9 0x168118
c18487ee
YR		 2899#define QM_REG_QVOQIDX_90 0x16e474
2900#define QM_REG_QVOQIDX_91 0x16e478
2901#define QM_REG_QVOQIDX_92 0x16e47c
2902#define QM_REG_QVOQIDX_93 0x16e480
2903#define QM_REG_QVOQIDX_94 0x16e484
2904#define QM_REG_QVOQIDX_95 0x16e488
2905#define QM_REG_QVOQIDX_96 0x16e48c
2906#define QM_REG_QVOQIDX_97 0x16e490
2907#define QM_REG_QVOQIDX_98 0x16e494
2908#define QM_REG_QVOQIDX_99 0x16e498
2909#define QM_REG_QVOQIDX_90 0x16e474
2910#define QM_REG_QVOQIDX_91 0x16e478
2911#define QM_REG_QVOQIDX_92 0x16e47c
2912#define QM_REG_QVOQIDX_93 0x16e480
2913#define QM_REG_QVOQIDX_94 0x16e484
2914#define QM_REG_QVOQIDX_95 0x16e488
2915#define QM_REG_QVOQIDX_96 0x16e48c
2916#define QM_REG_QVOQIDX_97 0x16e490
2917#define QM_REG_QVOQIDX_98 0x16e494
2918#define QM_REG_QVOQIDX_99 0x16e498
a2fbb9ea
ET		 2919/* [RW 1] Initialization bit command */
2920#define QM_REG_SOFT_RESET 0x168428
2921/* [RW 8] The credit cost per every task in the QM. A value per each VOQ */
2922#define QM_REG_TASKCRDCOST_0 0x16809c
2923#define QM_REG_TASKCRDCOST_1 0x1680a0
2924#define QM_REG_TASKCRDCOST_10 0x1680c4
2925#define QM_REG_TASKCRDCOST_11 0x1680c8
2926#define QM_REG_TASKCRDCOST_2 0x1680a4
2927#define QM_REG_TASKCRDCOST_4 0x1680ac
2928#define QM_REG_TASKCRDCOST_5 0x1680b0
2929/* [R 6] Keep the fill level of the fifo from write client 3 */
2930#define QM_REG_TQM_WRC_FIFOLVL 0x168010
2931/* [R 6] Keep the fill level of the fifo from write client 2 */
2932#define QM_REG_UQM_WRC_FIFOLVL 0x168008
2933/* [RC 32] Credit update error register */
2934#define QM_REG_VOQCRDERRREG 0x168408
2935/* [R 16] The credit value for each VOQ */
2936#define QM_REG_VOQCREDIT_0 0x1682d0
2937#define QM_REG_VOQCREDIT_1 0x1682d4
2938#define QM_REG_VOQCREDIT_10 0x1682f8
2939#define QM_REG_VOQCREDIT_11 0x1682fc
2940#define QM_REG_VOQCREDIT_4 0x1682e0
2941/* [RW 16] The credit value that if above the QM is considered almost full */
2942#define QM_REG_VOQCREDITAFULLTHR 0x168090
2943/* [RW 16] The init and maximum credit for each VoQ */
2944#define QM_REG_VOQINITCREDIT_0 0x168060
2945#define QM_REG_VOQINITCREDIT_1 0x168064
2946#define QM_REG_VOQINITCREDIT_10 0x168088
2947#define QM_REG_VOQINITCREDIT_11 0x16808c
2948#define QM_REG_VOQINITCREDIT_2 0x168068
2949#define QM_REG_VOQINITCREDIT_4 0x168070
2950#define QM_REG_VOQINITCREDIT_5 0x168074
2951/* [RW 1] The port of which VOQ belongs */
c18487ee 2952#define QM_REG_VOQPORT_0 0x1682a0
a2fbb9ea
ET		 2953#define QM_REG_VOQPORT_1 0x1682a4
2954#define QM_REG_VOQPORT_10 0x1682c8
2955#define QM_REG_VOQPORT_11 0x1682cc
2956#define QM_REG_VOQPORT_2 0x1682a8
c18487ee 2957/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
a2fbb9ea 2958#define QM_REG_VOQQMASK_0_LSB 0x168240
c18487ee
YR		 2959/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2960#define QM_REG_VOQQMASK_0_LSB_EXT_A 0x16e524
2961/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
a2fbb9ea 2962#define QM_REG_VOQQMASK_0_MSB 0x168244
c18487ee
YR		 2963/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2964#define QM_REG_VOQQMASK_0_MSB_EXT_A 0x16e528
2965/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2966#define QM_REG_VOQQMASK_10_LSB 0x168290
2967/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2968#define QM_REG_VOQQMASK_10_LSB_EXT_A 0x16e574
2969/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2970#define QM_REG_VOQQMASK_10_MSB 0x168294
2971/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2972#define QM_REG_VOQQMASK_10_MSB_EXT_A 0x16e578
2973/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2974#define QM_REG_VOQQMASK_11_LSB 0x168298
2975/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2976#define QM_REG_VOQQMASK_11_LSB_EXT_A 0x16e57c
2977/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2978#define QM_REG_VOQQMASK_11_MSB 0x16829c
2979/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2980#define QM_REG_VOQQMASK_11_MSB_EXT_A 0x16e580
2981/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2982#define QM_REG_VOQQMASK_1_LSB 0x168248
2983/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2984#define QM_REG_VOQQMASK_1_LSB_EXT_A 0x16e52c
2985/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
a2fbb9ea 2986#define QM_REG_VOQQMASK_1_MSB 0x16824c
c18487ee
YR		 2987/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2988#define QM_REG_VOQQMASK_1_MSB_EXT_A 0x16e530
2989/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
a2fbb9ea 2990#define QM_REG_VOQQMASK_2_LSB 0x168250
c18487ee
YR		 2991/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2992#define QM_REG_VOQQMASK_2_LSB_EXT_A 0x16e534
2993/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
a2fbb9ea 2994#define QM_REG_VOQQMASK_2_MSB 0x168254
c18487ee
YR		 2995/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2996#define QM_REG_VOQQMASK_2_MSB_EXT_A 0x16e538
2997/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
a2fbb9ea 2998#define QM_REG_VOQQMASK_3_LSB 0x168258
c18487ee
YR		 2999/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3000#define QM_REG_VOQQMASK_3_LSB_EXT_A 0x16e53c
3001/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3002#define QM_REG_VOQQMASK_3_MSB_EXT_A 0x16e540
3003/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
a2fbb9ea 3004#define QM_REG_VOQQMASK_4_LSB 0x168260
c18487ee
YR		 3005/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3006#define QM_REG_VOQQMASK_4_LSB_EXT_A 0x16e544
3007/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
a2fbb9ea 3008#define QM_REG_VOQQMASK_4_MSB 0x168264
c18487ee
YR		 3009/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3010#define QM_REG_VOQQMASK_4_MSB_EXT_A 0x16e548
3011/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
a2fbb9ea 3012#define QM_REG_VOQQMASK_5_LSB 0x168268
c18487ee
YR		 3013/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3014#define QM_REG_VOQQMASK_5_LSB_EXT_A 0x16e54c
3015/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
a2fbb9ea 3016#define QM_REG_VOQQMASK_5_MSB 0x16826c
c18487ee
YR		 3017/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3018#define QM_REG_VOQQMASK_5_MSB_EXT_A 0x16e550
3019/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
a2fbb9ea 3020#define QM_REG_VOQQMASK_6_LSB 0x168270
c18487ee
YR		 3021/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3022#define QM_REG_VOQQMASK_6_LSB_EXT_A 0x16e554
3023/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
a2fbb9ea 3024#define QM_REG_VOQQMASK_6_MSB 0x168274
c18487ee
YR		 3025/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3026#define QM_REG_VOQQMASK_6_MSB_EXT_A 0x16e558
3027/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
a2fbb9ea 3028#define QM_REG_VOQQMASK_7_LSB 0x168278
c18487ee
YR		 3029/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3030#define QM_REG_VOQQMASK_7_LSB_EXT_A 0x16e55c
3031/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
a2fbb9ea 3032#define QM_REG_VOQQMASK_7_MSB 0x16827c
c18487ee
YR		 3033/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3034#define QM_REG_VOQQMASK_7_MSB_EXT_A 0x16e560
3035/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
a2fbb9ea 3036#define QM_REG_VOQQMASK_8_LSB 0x168280
c18487ee
YR		 3037/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3038#define QM_REG_VOQQMASK_8_LSB_EXT_A 0x16e564
3039/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
a2fbb9ea 3040#define QM_REG_VOQQMASK_8_MSB 0x168284
c18487ee
YR		 3041/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3042#define QM_REG_VOQQMASK_8_MSB_EXT_A 0x16e568
3043/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
a2fbb9ea 3044#define QM_REG_VOQQMASK_9_LSB 0x168288
c18487ee
YR		 3045/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3046#define QM_REG_VOQQMASK_9_LSB_EXT_A 0x16e56c
3047/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3048#define QM_REG_VOQQMASK_9_MSB_EXT_A 0x16e570
a2fbb9ea
ET		 3049/* [RW 32] Wrr weights */
3050#define QM_REG_WRRWEIGHTS_0 0x16880c
3051#define QM_REG_WRRWEIGHTS_1 0x168810
3052#define QM_REG_WRRWEIGHTS_10 0x168814
3053#define QM_REG_WRRWEIGHTS_10_SIZE 1
3054/* [RW 32] Wrr weights */
3055#define QM_REG_WRRWEIGHTS_11 0x168818
3056#define QM_REG_WRRWEIGHTS_11_SIZE 1
3057/* [RW 32] Wrr weights */
3058#define QM_REG_WRRWEIGHTS_12 0x16881c
3059#define QM_REG_WRRWEIGHTS_12_SIZE 1
3060/* [RW 32] Wrr weights */
3061#define QM_REG_WRRWEIGHTS_13 0x168820
3062#define QM_REG_WRRWEIGHTS_13_SIZE 1
3063/* [RW 32] Wrr weights */
3064#define QM_REG_WRRWEIGHTS_14 0x168824
3065#define QM_REG_WRRWEIGHTS_14_SIZE 1
3066/* [RW 32] Wrr weights */
3067#define QM_REG_WRRWEIGHTS_15 0x168828
3068#define QM_REG_WRRWEIGHTS_15_SIZE 1
3069/* [RW 32] Wrr weights */
c18487ee
YR		 3070#define QM_REG_WRRWEIGHTS_16 0x16e000
3071#define QM_REG_WRRWEIGHTS_16_SIZE 1
3072/* [RW 32] Wrr weights */
3073#define QM_REG_WRRWEIGHTS_17 0x16e004
3074#define QM_REG_WRRWEIGHTS_17_SIZE 1
3075/* [RW 32] Wrr weights */
3076#define QM_REG_WRRWEIGHTS_18 0x16e008
3077#define QM_REG_WRRWEIGHTS_18_SIZE 1
3078/* [RW 32] Wrr weights */
3079#define QM_REG_WRRWEIGHTS_19 0x16e00c
3080#define QM_REG_WRRWEIGHTS_19_SIZE 1
3081/* [RW 32] Wrr weights */
a2fbb9ea
ET		 3082#define QM_REG_WRRWEIGHTS_10 0x168814
3083#define QM_REG_WRRWEIGHTS_11 0x168818
3084#define QM_REG_WRRWEIGHTS_12 0x16881c
3085#define QM_REG_WRRWEIGHTS_13 0x168820
3086#define QM_REG_WRRWEIGHTS_14 0x168824
3087#define QM_REG_WRRWEIGHTS_15 0x168828
c18487ee
YR		 3088#define QM_REG_WRRWEIGHTS_16 0x16e000
3089#define QM_REG_WRRWEIGHTS_17 0x16e004
3090#define QM_REG_WRRWEIGHTS_18 0x16e008
3091#define QM_REG_WRRWEIGHTS_19 0x16e00c
a2fbb9ea 3092#define QM_REG_WRRWEIGHTS_2 0x16882c
c18487ee
YR		 3093#define QM_REG_WRRWEIGHTS_20 0x16e010
3094#define QM_REG_WRRWEIGHTS_20_SIZE 1
3095/* [RW 32] Wrr weights */
3096#define QM_REG_WRRWEIGHTS_21 0x16e014
3097#define QM_REG_WRRWEIGHTS_21_SIZE 1
3098/* [RW 32] Wrr weights */
3099#define QM_REG_WRRWEIGHTS_22 0x16e018
3100#define QM_REG_WRRWEIGHTS_22_SIZE 1
3101/* [RW 32] Wrr weights */
3102#define QM_REG_WRRWEIGHTS_23 0x16e01c
3103#define QM_REG_WRRWEIGHTS_23_SIZE 1
3104/* [RW 32] Wrr weights */
3105#define QM_REG_WRRWEIGHTS_24 0x16e020
3106#define QM_REG_WRRWEIGHTS_24_SIZE 1
3107/* [RW 32] Wrr weights */
3108#define QM_REG_WRRWEIGHTS_25 0x16e024
3109#define QM_REG_WRRWEIGHTS_25_SIZE 1
3110/* [RW 32] Wrr weights */
3111#define QM_REG_WRRWEIGHTS_26 0x16e028
3112#define QM_REG_WRRWEIGHTS_26_SIZE 1
3113/* [RW 32] Wrr weights */
3114#define QM_REG_WRRWEIGHTS_27 0x16e02c
3115#define QM_REG_WRRWEIGHTS_27_SIZE 1
3116/* [RW 32] Wrr weights */
3117#define QM_REG_WRRWEIGHTS_28 0x16e030
3118#define QM_REG_WRRWEIGHTS_28_SIZE 1
3119/* [RW 32] Wrr weights */
3120#define QM_REG_WRRWEIGHTS_29 0x16e034
3121#define QM_REG_WRRWEIGHTS_29_SIZE 1
3122/* [RW 32] Wrr weights */
3123#define QM_REG_WRRWEIGHTS_20 0x16e010
3124#define QM_REG_WRRWEIGHTS_21 0x16e014
3125#define QM_REG_WRRWEIGHTS_22 0x16e018
3126#define QM_REG_WRRWEIGHTS_23 0x16e01c
3127#define QM_REG_WRRWEIGHTS_24 0x16e020
3128#define QM_REG_WRRWEIGHTS_25 0x16e024
3129#define QM_REG_WRRWEIGHTS_26 0x16e028
3130#define QM_REG_WRRWEIGHTS_27 0x16e02c
3131#define QM_REG_WRRWEIGHTS_28 0x16e030
3132#define QM_REG_WRRWEIGHTS_29 0x16e034
a2fbb9ea 3133#define QM_REG_WRRWEIGHTS_3 0x168830
c18487ee
YR		 3134#define QM_REG_WRRWEIGHTS_30 0x16e038
3135#define QM_REG_WRRWEIGHTS_30_SIZE 1
3136/* [RW 32] Wrr weights */
3137#define QM_REG_WRRWEIGHTS_31 0x16e03c
3138#define QM_REG_WRRWEIGHTS_31_SIZE 1
3139/* [RW 32] Wrr weights */
3140#define QM_REG_WRRWEIGHTS_30 0x16e038
3141#define QM_REG_WRRWEIGHTS_31 0x16e03c
a2fbb9ea
ET		 3142#define QM_REG_WRRWEIGHTS_4 0x168834
3143#define QM_REG_WRRWEIGHTS_5 0x168838
3144#define QM_REG_WRRWEIGHTS_6 0x16883c
3145#define QM_REG_WRRWEIGHTS_7 0x168840
3146#define QM_REG_WRRWEIGHTS_8 0x168844
3147#define QM_REG_WRRWEIGHTS_9 0x168848
3148/* [R 6] Keep the fill level of the fifo from write client 1 */
3149#define QM_REG_XQM_WRC_FIFOLVL 0x168000
c18487ee
YR		 3150#define BRB1_BRB1_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3151#define BRB1_BRB1_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3152#define BRB1_BRB1_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3153#define BRB1_BRB1_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3154#define BRB1_BRB1_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3155#define BRB1_BRB1_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3156#define BRB1_BRB1_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3157#define BRB1_BRB1_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3158#define CCM_CCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3159#define CCM_CCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3160#define CCM_CCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3161#define CCM_CCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3162#define CCM_CCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3163#define CCM_CCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3164#define CCM_CCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3165#define CCM_CCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3166#define CDU_CDU_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3167#define CDU_CDU_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3168#define CDU_CDU_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3169#define CDU_CDU_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3170#define CDU_CDU_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3171#define CDU_CDU_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3172#define CDU_CDU_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3173#define CDU_CDU_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3174#define CFC_CFC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3175#define CFC_CFC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3176#define CFC_CFC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3177#define CFC_CFC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3178#define CFC_CFC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3179#define CFC_CFC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3180#define CFC_CFC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3181#define CFC_CFC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3182#define CSDM_CSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3183#define CSDM_CSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3184#define CSDM_CSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3185#define CSDM_CSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3186#define CSDM_CSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3187#define CSDM_CSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3188#define CSDM_CSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3189#define CSDM_CSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3190#define CSEM_CSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3191#define CSEM_CSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3192#define CSEM_CSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3193#define CSEM_CSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3194#define CSEM_CSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3195#define CSEM_CSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3196#define CSEM_CSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3197#define CSEM_CSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3198#define DBG_DBG_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3199#define DBG_DBG_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3200#define DBG_DBG_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3201#define DBG_DBG_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3202#define DBG_DBG_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3203#define DBG_DBG_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3204#define DBG_DBG_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3205#define DBG_DBG_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3206#define DMAE_DMAE_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3207#define DMAE_DMAE_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3208#define DMAE_DMAE_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3209#define DMAE_DMAE_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3210#define DMAE_DMAE_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3211#define DMAE_DMAE_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3212#define DMAE_DMAE_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3213#define DMAE_DMAE_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
a2fbb9ea
ET		 3214#define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3215#define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3216#define DORQ_DORQ_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3217#define DORQ_DORQ_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3218#define DORQ_DORQ_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3219#define DORQ_DORQ_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3220#define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3221#define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
c18487ee
YR		 3222#define HC_HC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3223#define HC_HC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3224#define HC_HC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3225#define HC_HC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3226#define HC_HC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3227#define HC_HC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3228#define HC_HC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3229#define HC_HC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3230#define MISC_MISC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3231#define MISC_MISC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3232#define MISC_MISC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3233#define MISC_MISC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3234#define MISC_MISC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3235#define MISC_MISC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3236#define MISC_MISC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3237#define MISC_MISC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
a2fbb9ea
ET		 3238#define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3239#define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3240#define NIG_NIG_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3241#define NIG_NIG_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3242#define NIG_NIG_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3243#define NIG_NIG_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3244#define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3245#define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
c18487ee
YR		 3246#define PBF_PBF_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3247#define PBF_PBF_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3248#define PBF_PBF_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3249#define PBF_PBF_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3250#define PBF_PBF_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3251#define PBF_PBF_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3252#define PBF_PBF_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3253#define PBF_PBF_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3254#define PB_PB_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3255#define PB_PB_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3256#define PB_PB_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3257#define PB_PB_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3258#define PB_PB_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3259#define PB_PB_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3260#define PB_PB_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3261#define PB_PB_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3262#define PRS_PRS_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3263#define PRS_PRS_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3264#define PRS_PRS_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3265#define PRS_PRS_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3266#define PRS_PRS_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3267#define PRS_PRS_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3268#define PRS_PRS_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3269#define PRS_PRS_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3270#define PXP2_PXP2_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3271#define PXP2_PXP2_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3272#define PXP2_PXP2_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3273#define PXP2_PXP2_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3274#define PXP2_PXP2_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3275#define PXP2_PXP2_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3276#define PXP2_PXP2_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3277#define PXP2_PXP2_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3278#define PXP_PXP_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3279#define PXP_PXP_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3280#define PXP_PXP_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3281#define PXP_PXP_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3282#define PXP_PXP_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3283#define PXP_PXP_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3284#define PXP_PXP_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3285#define PXP_PXP_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3286#define QM_QM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3287#define QM_QM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3288#define QM_QM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3289#define QM_QM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3290#define QM_QM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3291#define QM_QM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3292#define QM_QM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3293#define QM_QM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3294#define SEM_FAST_SEM_FAST_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3295#define SEM_FAST_SEM_FAST_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3296#define SEM_FAST_SEM_FAST_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3297#define SEM_FAST_SEM_FAST_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3298#define SEM_FAST_SEM_FAST_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3299#define SEM_FAST_SEM_FAST_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3300#define SEM_FAST_SEM_FAST_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3301#define SEM_FAST_SEM_FAST_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3302#define SRC_SRC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3303#define SRC_SRC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3304#define SRC_SRC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3305#define SRC_SRC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3306#define SRC_SRC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3307#define SRC_SRC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3308#define SRC_SRC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3309#define SRC_SRC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
a2fbb9ea
ET		 3310#define TCM_TCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3311#define TCM_TCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3312#define TCM_TCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3313#define TCM_TCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3314#define TCM_TCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3315#define TCM_TCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3316#define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3317#define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
c18487ee
YR		 3318#define TM_TM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3319#define TM_TM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3320#define TM_TM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3321#define TM_TM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3322#define TM_TM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3323#define TM_TM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3324#define TM_TM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3325#define TM_TM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3326#define TSDM_TSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3327#define TSDM_TSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3328#define TSDM_TSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3329#define TSDM_TSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3330#define TSDM_TSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3331#define TSDM_TSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3332#define TSDM_TSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3333#define TSDM_TSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3334#define TSEM_TSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3335#define TSEM_TSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3336#define TSEM_TSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3337#define TSEM_TSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3338#define TSEM_TSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3339#define TSEM_TSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3340#define TSEM_TSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3341#define TSEM_TSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3342#define UCM_UCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3343#define UCM_UCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3344#define UCM_UCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3345#define UCM_UCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3346#define UCM_UCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3347#define UCM_UCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3348#define UCM_UCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3349#define UCM_UCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3350#define USDM_USDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3351#define USDM_USDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3352#define USDM_USDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3353#define USDM_USDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3354#define USDM_USDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3355#define USDM_USDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3356#define USDM_USDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3357#define USDM_USDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3358#define USEM_USEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3359#define USEM_USEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3360#define USEM_USEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3361#define USEM_USEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3362#define USEM_USEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3363#define USEM_USEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3364#define USEM_USEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3365#define USEM_USEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3366#define XCM_XCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3367#define XCM_XCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3368#define XCM_XCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3369#define XCM_XCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3370#define XCM_XCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3371#define XCM_XCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3372#define XCM_XCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3373#define XCM_XCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3374#define XSDM_XSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3375#define XSDM_XSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3376#define XSDM_XSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3377#define XSDM_XSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3378#define XSDM_XSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3379#define XSDM_XSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3380#define XSDM_XSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3381#define XSDM_XSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3382#define XSEM_XSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3383#define XSEM_XSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3384#define XSEM_XSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3385#define XSEM_XSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3386#define XSEM_XSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3387#define XSEM_XSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3388#define XSEM_XSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3389#define XSEM_XSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
a2fbb9ea
ET		 3390#define CFC_DEBUG1_REG_WRITE_AC (0x1<<4)
3391#define CFC_DEBUG1_REG_WRITE_AC_SIZE 4
33471629 3392/* [R 1] debug only: This bit indicates whether indicates that external
a2fbb9ea
ET		 3393 buffer was wrapped (oldest data was thrown); Relevant only when
3394 ~dbg_registers_debug_target=2 (PCI) & ~dbg_registers_full_mode=1 (wrap); */
3395#define DBG_REG_WRAP_ON_EXT_BUFFER 0xc124
3396#define DBG_REG_WRAP_ON_EXT_BUFFER_SIZE 1
33471629 3397/* [R 1] debug only: This bit indicates whether the internal buffer was
a2fbb9ea
ET		 3398 wrapped (oldest data was thrown) Relevant only when
3399 ~dbg_registers_debug_target=0 (internal buffer) */
3400#define DBG_REG_WRAP_ON_INT_BUFFER 0xc128
3401#define DBG_REG_WRAP_ON_INT_BUFFER_SIZE 1
c18487ee
YR		 3402#define QM_QM_PRTY_STS_REG_WRBUFF (0x1<<8)
3403#define QM_QM_PRTY_STS_REG_WRBUFF_SIZE 8
3404#define QM_QM_PRTY_STS_CLR_REG_WRBUFF (0x1<<8)
3405#define QM_QM_PRTY_STS_CLR_REG_WRBUFF_SIZE 8
3406#define QM_QM_PRTY_STS_WR_REG_WRBUFF (0x1<<8)
3407#define QM_QM_PRTY_STS_WR_REG_WRBUFF_SIZE 8
3408#define QM_QM_PRTY_MASK_REG_WRBUFF (0x1<<8)
3409#define QM_QM_PRTY_MASK_REG_WRBUFF_SIZE 8
a2fbb9ea
ET		 3410/* [RW 32] Wrr weights */
3411#define QM_REG_WRRWEIGHTS_0 0x16880c
3412#define QM_REG_WRRWEIGHTS_0_SIZE 1
3413/* [RW 32] Wrr weights */
3414#define QM_REG_WRRWEIGHTS_1 0x168810
3415#define QM_REG_WRRWEIGHTS_1_SIZE 1
3416/* [RW 32] Wrr weights */
3417#define QM_REG_WRRWEIGHTS_10 0x168814
3418#define QM_REG_WRRWEIGHTS_10_SIZE 1
3419/* [RW 32] Wrr weights */
3420#define QM_REG_WRRWEIGHTS_11 0x168818
3421#define QM_REG_WRRWEIGHTS_11_SIZE 1
3422/* [RW 32] Wrr weights */
3423#define QM_REG_WRRWEIGHTS_12 0x16881c
3424#define QM_REG_WRRWEIGHTS_12_SIZE 1
3425/* [RW 32] Wrr weights */
3426#define QM_REG_WRRWEIGHTS_13 0x168820
3427#define QM_REG_WRRWEIGHTS_13_SIZE 1
3428/* [RW 32] Wrr weights */
3429#define QM_REG_WRRWEIGHTS_14 0x168824
3430#define QM_REG_WRRWEIGHTS_14_SIZE 1
3431/* [RW 32] Wrr weights */
3432#define QM_REG_WRRWEIGHTS_15 0x168828
3433#define QM_REG_WRRWEIGHTS_15_SIZE 1
3434/* [RW 32] Wrr weights */
3435#define QM_REG_WRRWEIGHTS_2 0x16882c
3436#define QM_REG_WRRWEIGHTS_2_SIZE 1
3437/* [RW 32] Wrr weights */
3438#define QM_REG_WRRWEIGHTS_3 0x168830
3439#define QM_REG_WRRWEIGHTS_3_SIZE 1
3440/* [RW 32] Wrr weights */
3441#define QM_REG_WRRWEIGHTS_4 0x168834
3442#define QM_REG_WRRWEIGHTS_4_SIZE 1
3443/* [RW 32] Wrr weights */
3444#define QM_REG_WRRWEIGHTS_5 0x168838
3445#define QM_REG_WRRWEIGHTS_5_SIZE 1
3446/* [RW 32] Wrr weights */
3447#define QM_REG_WRRWEIGHTS_6 0x16883c
3448#define QM_REG_WRRWEIGHTS_6_SIZE 1
3449/* [RW 32] Wrr weights */
3450#define QM_REG_WRRWEIGHTS_7 0x168840
3451#define QM_REG_WRRWEIGHTS_7_SIZE 1
3452/* [RW 32] Wrr weights */
3453#define QM_REG_WRRWEIGHTS_8 0x168844
3454#define QM_REG_WRRWEIGHTS_8_SIZE 1
3455/* [RW 32] Wrr weights */
3456#define QM_REG_WRRWEIGHTS_9 0x168848
3457#define QM_REG_WRRWEIGHTS_9_SIZE 1
c18487ee
YR		 3458/* [RW 32] Wrr weights */
3459#define QM_REG_WRRWEIGHTS_16 0x16e000
3460#define QM_REG_WRRWEIGHTS_16_SIZE 1
3461/* [RW 32] Wrr weights */
3462#define QM_REG_WRRWEIGHTS_17 0x16e004
3463#define QM_REG_WRRWEIGHTS_17_SIZE 1
3464/* [RW 32] Wrr weights */
3465#define QM_REG_WRRWEIGHTS_18 0x16e008
3466#define QM_REG_WRRWEIGHTS_18_SIZE 1
3467/* [RW 32] Wrr weights */
3468#define QM_REG_WRRWEIGHTS_19 0x16e00c
3469#define QM_REG_WRRWEIGHTS_19_SIZE 1
3470/* [RW 32] Wrr weights */
3471#define QM_REG_WRRWEIGHTS_20 0x16e010
3472#define QM_REG_WRRWEIGHTS_20_SIZE 1
3473/* [RW 32] Wrr weights */
3474#define QM_REG_WRRWEIGHTS_21 0x16e014
3475#define QM_REG_WRRWEIGHTS_21_SIZE 1
3476/* [RW 32] Wrr weights */
3477#define QM_REG_WRRWEIGHTS_22 0x16e018
3478#define QM_REG_WRRWEIGHTS_22_SIZE 1
3479/* [RW 32] Wrr weights */
3480#define QM_REG_WRRWEIGHTS_23 0x16e01c
3481#define QM_REG_WRRWEIGHTS_23_SIZE 1
3482/* [RW 32] Wrr weights */
3483#define QM_REG_WRRWEIGHTS_24 0x16e020
3484#define QM_REG_WRRWEIGHTS_24_SIZE 1
3485/* [RW 32] Wrr weights */
3486#define QM_REG_WRRWEIGHTS_25 0x16e024
3487#define QM_REG_WRRWEIGHTS_25_SIZE 1
3488/* [RW 32] Wrr weights */
3489#define QM_REG_WRRWEIGHTS_26 0x16e028
3490#define QM_REG_WRRWEIGHTS_26_SIZE 1
3491/* [RW 32] Wrr weights */
3492#define QM_REG_WRRWEIGHTS_27 0x16e02c
3493#define QM_REG_WRRWEIGHTS_27_SIZE 1
3494/* [RW 32] Wrr weights */
3495#define QM_REG_WRRWEIGHTS_28 0x16e030
3496#define QM_REG_WRRWEIGHTS_28_SIZE 1
3497/* [RW 32] Wrr weights */
3498#define QM_REG_WRRWEIGHTS_29 0x16e034
3499#define QM_REG_WRRWEIGHTS_29_SIZE 1
3500/* [RW 32] Wrr weights */
3501#define QM_REG_WRRWEIGHTS_30 0x16e038
3502#define QM_REG_WRRWEIGHTS_30_SIZE 1
3503/* [RW 32] Wrr weights */
3504#define QM_REG_WRRWEIGHTS_31 0x16e03c
3505#define QM_REG_WRRWEIGHTS_31_SIZE 1
a2fbb9ea 3506#define SRC_REG_COUNTFREE0 0x40500
c18487ee
YR		 3507/* [RW 1] If clr the searcher is compatible to E1 A0 - support only two
3508 ports. If set the searcher support 8 functions. */
3509#define SRC_REG_E1HMF_ENABLE 0x404cc
a2fbb9ea
ET		 3510#define SRC_REG_FIRSTFREE0 0x40510
3511#define SRC_REG_KEYRSS0_0 0x40408
c18487ee 3512#define SRC_REG_KEYRSS0_7 0x40424
a2fbb9ea 3513#define SRC_REG_KEYRSS1_9 0x40454
8d9c5f34
EG		 3514#define SRC_REG_KEYSEARCH_0 0x40458
3515#define SRC_REG_KEYSEARCH_1 0x4045c
3516#define SRC_REG_KEYSEARCH_2 0x40460
3517#define SRC_REG_KEYSEARCH_3 0x40464
3518#define SRC_REG_KEYSEARCH_4 0x40468
3519#define SRC_REG_KEYSEARCH_5 0x4046c
3520#define SRC_REG_KEYSEARCH_6 0x40470
3521#define SRC_REG_KEYSEARCH_7 0x40474
3522#define SRC_REG_KEYSEARCH_8 0x40478
3523#define SRC_REG_KEYSEARCH_9 0x4047c
a2fbb9ea 3524#define SRC_REG_LASTFREE0 0x40530
a2fbb9ea
ET		 3525#define SRC_REG_NUMBER_HASH_BITS0 0x40400
3526/* [RW 1] Reset internal state machines. */
3527#define SRC_REG_SOFT_RST 0x4049c
c18487ee 3528/* [R 3] Interrupt register #0 read */
a2fbb9ea
ET		 3529#define SRC_REG_SRC_INT_STS 0x404ac
3530/* [RW 3] Parity mask register #0 read/write */
3531#define SRC_REG_SRC_PRTY_MASK 0x404c8
f1410647
ET		 3532/* [R 3] Parity register #0 read */
3533#define SRC_REG_SRC_PRTY_STS 0x404bc
a2fbb9ea
ET		 3534/* [R 4] Used to read the value of the XX protection CAM occupancy counter. */
3535#define TCM_REG_CAM_OCCUP 0x5017c
3536/* [RW 1] CDU AG read Interface enable. If 0 - the request input is
3537 disregarded; valid output is deasserted; all other signals are treated as
3538 usual; if 1 - normal activity. */
3539#define TCM_REG_CDU_AG_RD_IFEN 0x50034
3540/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
3541 are disregarded; all other signals are treated as usual; if 1 - normal
3542 activity. */
3543#define TCM_REG_CDU_AG_WR_IFEN 0x50030
3544/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
3545 disregarded; valid output is deasserted; all other signals are treated as
3546 usual; if 1 - normal activity. */
3547#define TCM_REG_CDU_SM_RD_IFEN 0x5003c
3548/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
3549 input is disregarded; all other signals are treated as usual; if 1 -
3550 normal activity. */
3551#define TCM_REG_CDU_SM_WR_IFEN 0x50038
3552/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
3553 the initial credit value; read returns the current value of the credit
3554 counter. Must be initialized to 1 at start-up. */
3555#define TCM_REG_CFC_INIT_CRD 0x50204
3556/* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
3557 weight 8 (the most prioritised); 1 stands for weight 1(least
3558 prioritised); 2 stands for weight 2; tc. */
3559#define TCM_REG_CP_WEIGHT 0x500c0
3560/* [RW 1] Input csem Interface enable. If 0 - the valid input is
3561 disregarded; acknowledge output is deasserted; all other signals are
3562 treated as usual; if 1 - normal activity. */
3563#define TCM_REG_CSEM_IFEN 0x5002c
3564/* [RC 1] Message length mismatch (relative to last indication) at the In#9
3565 interface. */
3566#define TCM_REG_CSEM_LENGTH_MIS 0x50174
8d9c5f34
EG		 3567/* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
3568 weight 8 (the most prioritised); 1 stands for weight 1(least
3569 prioritised); 2 stands for weight 2; tc. */
3570#define TCM_REG_CSEM_WEIGHT 0x500bc
a2fbb9ea
ET		 3571/* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */
3572#define TCM_REG_ERR_EVNT_ID 0x500a0
3573/* [RW 28] The CM erroneous header for QM and Timers formatting. */
3574#define TCM_REG_ERR_TCM_HDR 0x5009c
3575/* [RW 8] The Event ID for Timers expiration. */
3576#define TCM_REG_EXPR_EVNT_ID 0x500a4
3577/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
3578 writes the initial credit value; read returns the current value of the
3579 credit counter. Must be initialized to 64 at start-up. */
3580#define TCM_REG_FIC0_INIT_CRD 0x5020c
3581/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
3582 writes the initial credit value; read returns the current value of the
3583 credit counter. Must be initialized to 64 at start-up. */
3584#define TCM_REG_FIC1_INIT_CRD 0x50210
3585/* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
3586 - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr;
3587 ~tcm_registers_gr_ld0_pr.gr_ld0_pr and
3588 ~tcm_registers_gr_ld1_pr.gr_ld1_pr. */
3589#define TCM_REG_GR_ARB_TYPE 0x50114
3590/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
3591 highest priority is 3. It is supposed that the Store channel is the
3592 compliment of the other 3 groups. */
3593#define TCM_REG_GR_LD0_PR 0x5011c
3594/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
3595 highest priority is 3. It is supposed that the Store channel is the
3596 compliment of the other 3 groups. */
3597#define TCM_REG_GR_LD1_PR 0x50120
3598/* [RW 4] The number of double REG-pairs; loaded from the STORM context and
3599 sent to STORM; for a specific connection type. The double REG-pairs are
3600 used to align to STORM context row size of 128 bits. The offset of these
3601 data in the STORM context is always 0. Index _i stands for the connection
3602 type (one of 16). */
3603#define TCM_REG_N_SM_CTX_LD_0 0x50050
3604#define TCM_REG_N_SM_CTX_LD_1 0x50054
3605#define TCM_REG_N_SM_CTX_LD_10 0x50078
3606#define TCM_REG_N_SM_CTX_LD_11 0x5007c
3607#define TCM_REG_N_SM_CTX_LD_12 0x50080
3608#define TCM_REG_N_SM_CTX_LD_13 0x50084
3609#define TCM_REG_N_SM_CTX_LD_14 0x50088
3610#define TCM_REG_N_SM_CTX_LD_15 0x5008c
3611#define TCM_REG_N_SM_CTX_LD_2 0x50058
3612#define TCM_REG_N_SM_CTX_LD_3 0x5005c
3613#define TCM_REG_N_SM_CTX_LD_4 0x50060
8d9c5f34 3614#define TCM_REG_N_SM_CTX_LD_5 0x50064
a2fbb9ea
ET		 3615/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
3616 acknowledge output is deasserted; all other signals are treated as usual;
3617 if 1 - normal activity. */
3618#define TCM_REG_PBF_IFEN 0x50024
3619/* [RC 1] Message length mismatch (relative to last indication) at the In#7
3620 interface. */
3621#define TCM_REG_PBF_LENGTH_MIS 0x5016c
3622/* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
3623 weight 8 (the most prioritised); 1 stands for weight 1(least
3624 prioritised); 2 stands for weight 2; tc. */
3625#define TCM_REG_PBF_WEIGHT 0x500b4
a2fbb9ea
ET		 3626#define TCM_REG_PHYS_QNUM0_0 0x500e0
3627#define TCM_REG_PHYS_QNUM0_1 0x500e4
a2fbb9ea 3628#define TCM_REG_PHYS_QNUM1_0 0x500e8
c18487ee
YR		 3629#define TCM_REG_PHYS_QNUM1_1 0x500ec
3630#define TCM_REG_PHYS_QNUM2_0 0x500f0
3631#define TCM_REG_PHYS_QNUM2_1 0x500f4
3632#define TCM_REG_PHYS_QNUM3_0 0x500f8
3633#define TCM_REG_PHYS_QNUM3_1 0x500fc
a2fbb9ea
ET		 3634/* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded;
3635 acknowledge output is deasserted; all other signals are treated as usual;
3636 if 1 - normal activity. */
3637#define TCM_REG_PRS_IFEN 0x50020
3638/* [RC 1] Message length mismatch (relative to last indication) at the In#6
3639 interface. */
3640#define TCM_REG_PRS_LENGTH_MIS 0x50168
3641/* [RW 3] The weight of the input prs in the WRR mechanism. 0 stands for
3642 weight 8 (the most prioritised); 1 stands for weight 1(least
3643 prioritised); 2 stands for weight 2; tc. */
3644#define TCM_REG_PRS_WEIGHT 0x500b0
3645/* [RW 8] The Event ID for Timers formatting in case of stop done. */
3646#define TCM_REG_STOP_EVNT_ID 0x500a8
3647/* [RC 1] Message length mismatch (relative to last indication) at the STORM
3648 interface. */
3649#define TCM_REG_STORM_LENGTH_MIS 0x50160
3650/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
3651 disregarded; acknowledge output is deasserted; all other signals are
3652 treated as usual; if 1 - normal activity. */
3653#define TCM_REG_STORM_TCM_IFEN 0x50010
8d9c5f34
EG		 3654/* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
3655 weight 8 (the most prioritised); 1 stands for weight 1(least
3656 prioritised); 2 stands for weight 2; tc. */
3657#define TCM_REG_STORM_WEIGHT 0x500ac
a2fbb9ea
ET		 3658/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
3659 acknowledge output is deasserted; all other signals are treated as usual;
3660 if 1 - normal activity. */
3661#define TCM_REG_TCM_CFC_IFEN 0x50040
3662/* [RW 11] Interrupt mask register #0 read/write */
3663#define TCM_REG_TCM_INT_MASK 0x501dc
3664/* [R 11] Interrupt register #0 read */
3665#define TCM_REG_TCM_INT_STS 0x501d0
c18487ee
YR		 3666/* [R 27] Parity register #0 read */
3667#define TCM_REG_TCM_PRTY_STS 0x501e0
a2fbb9ea
ET		 3668/* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
3669 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
3670 Is used to determine the number of the AG context REG-pairs written back;
3671 when the input message Reg1WbFlg isn't set. */
3672#define TCM_REG_TCM_REG0_SZ 0x500d8
3673/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
3674 disregarded; valid is deasserted; all other signals are treated as usual;
3675 if 1 - normal activity. */
3676#define TCM_REG_TCM_STORM0_IFEN 0x50004
3677/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
3678 disregarded; valid is deasserted; all other signals are treated as usual;
3679 if 1 - normal activity. */
3680#define TCM_REG_TCM_STORM1_IFEN 0x50008
3681/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
3682 disregarded; valid is deasserted; all other signals are treated as usual;
3683 if 1 - normal activity. */
3684#define TCM_REG_TCM_TQM_IFEN 0x5000c
3685/* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
3686#define TCM_REG_TCM_TQM_USE_Q 0x500d4
3687/* [RW 28] The CM header for Timers expiration command. */
3688#define TCM_REG_TM_TCM_HDR 0x50098
3689/* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
3690 disregarded; acknowledge output is deasserted; all other signals are
3691 treated as usual; if 1 - normal activity. */
3692#define TCM_REG_TM_TCM_IFEN 0x5001c
8d9c5f34
EG		 3693/* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
3694 weight 8 (the most prioritised); 1 stands for weight 1(least
3695 prioritised); 2 stands for weight 2; tc. */
3696#define TCM_REG_TM_WEIGHT 0x500d0
a2fbb9ea
ET		 3697/* [RW 6] QM output initial credit. Max credit available - 32.Write writes
3698 the initial credit value; read returns the current value of the credit
3699 counter. Must be initialized to 32 at start-up. */
3700#define TCM_REG_TQM_INIT_CRD 0x5021c
8d9c5f34
EG		 3701/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
3702 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
3703 prioritised); 2 stands for weight 2; tc. */
3704#define TCM_REG_TQM_P_WEIGHT 0x500c8
3705/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
3706 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
3707 prioritised); 2 stands for weight 2; tc. */
3708#define TCM_REG_TQM_S_WEIGHT 0x500cc
a2fbb9ea
ET		 3709/* [RW 28] The CM header value for QM request (primary). */
3710#define TCM_REG_TQM_TCM_HDR_P 0x50090
3711/* [RW 28] The CM header value for QM request (secondary). */
3712#define TCM_REG_TQM_TCM_HDR_S 0x50094
3713/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
3714 acknowledge output is deasserted; all other signals are treated as usual;
3715 if 1 - normal activity. */
3716#define TCM_REG_TQM_TCM_IFEN 0x50014
3717/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
3718 acknowledge output is deasserted; all other signals are treated as usual;
3719 if 1 - normal activity. */
3720#define TCM_REG_TSDM_IFEN 0x50018
3721/* [RC 1] Message length mismatch (relative to last indication) at the SDM
3722 interface. */
3723#define TCM_REG_TSDM_LENGTH_MIS 0x50164
3724/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
3725 weight 8 (the most prioritised); 1 stands for weight 1(least
3726 prioritised); 2 stands for weight 2; tc. */
3727#define TCM_REG_TSDM_WEIGHT 0x500c4
3728/* [RW 1] Input usem Interface enable. If 0 - the valid input is
3729 disregarded; acknowledge output is deasserted; all other signals are
3730 treated as usual; if 1 - normal activity. */
3731#define TCM_REG_USEM_IFEN 0x50028
3732/* [RC 1] Message length mismatch (relative to last indication) at the In#8
3733 interface. */
3734#define TCM_REG_USEM_LENGTH_MIS 0x50170
8d9c5f34
EG		 3735/* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
3736 weight 8 (the most prioritised); 1 stands for weight 1(least
3737 prioritised); 2 stands for weight 2; tc. */
3738#define TCM_REG_USEM_WEIGHT 0x500b8
a2fbb9ea
ET		 3739/* [RW 21] Indirect access to the descriptor table of the XX protection
3740 mechanism. The fields are: [5:0] - length of the message; 15:6] - message
3741 pointer; 20:16] - next pointer. */
3742#define TCM_REG_XX_DESCR_TABLE 0x50280
c18487ee 3743#define TCM_REG_XX_DESCR_TABLE_SIZE 32
a2fbb9ea
ET		 3744/* [R 6] Use to read the value of XX protection Free counter. */
3745#define TCM_REG_XX_FREE 0x50178
3746/* [RW 6] Initial value for the credit counter; responsible for fulfilling
3747 of the Input Stage XX protection buffer by the XX protection pending
3748 messages. Max credit available - 127.Write writes the initial credit
3749 value; read returns the current value of the credit counter. Must be
3750 initialized to 19 at start-up. */
3751#define TCM_REG_XX_INIT_CRD 0x50220
3752/* [RW 6] Maximum link list size (messages locked) per connection in the XX
3753 protection. */
3754#define TCM_REG_XX_MAX_LL_SZ 0x50044
3755/* [RW 6] The maximum number of pending messages; which may be stored in XX
3756 protection. ~tcm_registers_xx_free.xx_free is read on read. */
3757#define TCM_REG_XX_MSG_NUM 0x50224
3758/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
3759#define TCM_REG_XX_OVFL_EVNT_ID 0x50048
3760/* [RW 16] Indirect access to the XX table of the XX protection mechanism.
3761 The fields are:[4:0] - tail pointer; [10:5] - Link List size; 15:11] -
3762 header pointer. */
3763#define TCM_REG_XX_TABLE 0x50240
3764/* [RW 4] Load value for for cfc ac credit cnt. */
3765#define TM_REG_CFC_AC_CRDCNT_VAL 0x164208
3766/* [RW 4] Load value for cfc cld credit cnt. */
3767#define TM_REG_CFC_CLD_CRDCNT_VAL 0x164210
3768/* [RW 8] Client0 context region. */
3769#define TM_REG_CL0_CONT_REGION 0x164030
3770/* [RW 8] Client1 context region. */
3771#define TM_REG_CL1_CONT_REGION 0x164034
3772/* [RW 8] Client2 context region. */
3773#define TM_REG_CL2_CONT_REGION 0x164038
3774/* [RW 2] Client in High priority client number. */
3775#define TM_REG_CLIN_PRIOR0_CLIENT 0x164024
3776/* [RW 4] Load value for clout0 cred cnt. */
3777#define TM_REG_CLOUT_CRDCNT0_VAL 0x164220
3778/* [RW 4] Load value for clout1 cred cnt. */
3779#define TM_REG_CLOUT_CRDCNT1_VAL 0x164228
3780/* [RW 4] Load value for clout2 cred cnt. */
3781#define TM_REG_CLOUT_CRDCNT2_VAL 0x164230
3782/* [RW 1] Enable client0 input. */
3783#define TM_REG_EN_CL0_INPUT 0x164008
3784/* [RW 1] Enable client1 input. */
3785#define TM_REG_EN_CL1_INPUT 0x16400c
3786/* [RW 1] Enable client2 input. */
3787#define TM_REG_EN_CL2_INPUT 0x164010
8d9c5f34 3788#define TM_REG_EN_LINEAR0_TIMER 0x164014
a2fbb9ea
ET		 3789/* [RW 1] Enable real time counter. */
3790#define TM_REG_EN_REAL_TIME_CNT 0x1640d8
3791/* [RW 1] Enable for Timers state machines. */
3792#define TM_REG_EN_TIMERS 0x164000
3793/* [RW 4] Load value for expiration credit cnt. CFC max number of
3794 outstanding load requests for timers (expiration) context loading. */
3795#define TM_REG_EXP_CRDCNT_VAL 0x164238
8d9c5f34
EG		 3796/* [RW 32] Linear0 logic address. */
3797#define TM_REG_LIN0_LOGIC_ADDR 0x164240
c18487ee 3798/* [RW 18] Linear0 Max active cid (in banks of 32 entries). */
a2fbb9ea
ET		 3799#define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048
3800/* [WB 64] Linear0 phy address. */
3801#define TM_REG_LIN0_PHY_ADDR 0x164270
8d9c5f34
EG		 3802/* [RW 1] Linear0 physical address valid. */
3803#define TM_REG_LIN0_PHY_ADDR_VALID 0x164248
a2fbb9ea
ET		 3804/* [RW 24] Linear0 array scan timeout. */
3805#define TM_REG_LIN0_SCAN_TIME 0x16403c
8d9c5f34
EG		 3806/* [RW 32] Linear1 logic address. */
3807#define TM_REG_LIN1_LOGIC_ADDR 0x164250
a2fbb9ea
ET		 3808/* [WB 64] Linear1 phy address. */
3809#define TM_REG_LIN1_PHY_ADDR 0x164280
8d9c5f34
EG		 3810/* [RW 1] Linear1 physical address valid. */
3811#define TM_REG_LIN1_PHY_ADDR_VALID 0x164258
a2fbb9ea
ET		 3812/* [RW 6] Linear timer set_clear fifo threshold. */
3813#define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR 0x164070
3814/* [RW 2] Load value for pci arbiter credit cnt. */
3815#define TM_REG_PCIARB_CRDCNT_VAL 0x164260
3816/* [RW 1] Timer software reset - active high. */
3817#define TM_REG_TIMER_SOFT_RST 0x164004
3818/* [RW 20] The amount of hardware cycles for each timer tick. */
3819#define TM_REG_TIMER_TICK_SIZE 0x16401c
3820/* [RW 8] Timers Context region. */
3821#define TM_REG_TM_CONTEXT_REGION 0x164044
3822/* [RW 1] Interrupt mask register #0 read/write */
3823#define TM_REG_TM_INT_MASK 0x1640fc
3824/* [R 1] Interrupt register #0 read */
3825#define TM_REG_TM_INT_STS 0x1640f0
3826/* [RW 8] The event id for aggregated interrupt 0 */
3827#define TSDM_REG_AGG_INT_EVENT_0 0x42038
8d9c5f34
EG		 3828#define TSDM_REG_AGG_INT_EVENT_1 0x4203c
3829#define TSDM_REG_AGG_INT_EVENT_10 0x42060
3830#define TSDM_REG_AGG_INT_EVENT_11 0x42064
3831#define TSDM_REG_AGG_INT_EVENT_12 0x42068
3832#define TSDM_REG_AGG_INT_EVENT_13 0x4206c
3833#define TSDM_REG_AGG_INT_EVENT_14 0x42070
3834#define TSDM_REG_AGG_INT_EVENT_15 0x42074
3835#define TSDM_REG_AGG_INT_EVENT_16 0x42078
3836#define TSDM_REG_AGG_INT_EVENT_17 0x4207c
3837#define TSDM_REG_AGG_INT_EVENT_18 0x42080
3838#define TSDM_REG_AGG_INT_EVENT_19 0x42084
c18487ee
YR		 3839#define TSDM_REG_AGG_INT_EVENT_2 0x42040
3840#define TSDM_REG_AGG_INT_EVENT_20 0x42088
3841#define TSDM_REG_AGG_INT_EVENT_21 0x4208c
3842#define TSDM_REG_AGG_INT_EVENT_22 0x42090
3843#define TSDM_REG_AGG_INT_EVENT_23 0x42094
3844#define TSDM_REG_AGG_INT_EVENT_24 0x42098
3845#define TSDM_REG_AGG_INT_EVENT_25 0x4209c
3846#define TSDM_REG_AGG_INT_EVENT_26 0x420a0
3847#define TSDM_REG_AGG_INT_EVENT_27 0x420a4
3848#define TSDM_REG_AGG_INT_EVENT_28 0x420a8
3849#define TSDM_REG_AGG_INT_EVENT_29 0x420ac
3850#define TSDM_REG_AGG_INT_EVENT_3 0x42044
3851#define TSDM_REG_AGG_INT_EVENT_30 0x420b0
3852#define TSDM_REG_AGG_INT_EVENT_31 0x420b4
3853#define TSDM_REG_AGG_INT_EVENT_4 0x42048
8d9c5f34
EG		 3854/* [RW 1] The T bit for aggregated interrupt 0 */
3855#define TSDM_REG_AGG_INT_T_0 0x420b8
3856#define TSDM_REG_AGG_INT_T_1 0x420bc
3857#define TSDM_REG_AGG_INT_T_10 0x420e0
3858#define TSDM_REG_AGG_INT_T_11 0x420e4
3859#define TSDM_REG_AGG_INT_T_12 0x420e8
3860#define TSDM_REG_AGG_INT_T_13 0x420ec
3861#define TSDM_REG_AGG_INT_T_14 0x420f0
3862#define TSDM_REG_AGG_INT_T_15 0x420f4
3863#define TSDM_REG_AGG_INT_T_16 0x420f8
3864#define TSDM_REG_AGG_INT_T_17 0x420fc
3865#define TSDM_REG_AGG_INT_T_18 0x42100
3866#define TSDM_REG_AGG_INT_T_19 0x42104
a2fbb9ea
ET		 3867/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
3868#define TSDM_REG_CFC_RSP_START_ADDR 0x42008
3869/* [RW 16] The maximum value of the competion counter #0 */
3870#define TSDM_REG_CMP_COUNTER_MAX0 0x4201c
3871/* [RW 16] The maximum value of the competion counter #1 */
3872#define TSDM_REG_CMP_COUNTER_MAX1 0x42020
3873/* [RW 16] The maximum value of the competion counter #2 */
3874#define TSDM_REG_CMP_COUNTER_MAX2 0x42024
3875/* [RW 16] The maximum value of the competion counter #3 */
3876#define TSDM_REG_CMP_COUNTER_MAX3 0x42028
3877/* [RW 13] The start address in the internal RAM for the completion
3878 counters. */
3879#define TSDM_REG_CMP_COUNTER_START_ADDR 0x4200c
3880#define TSDM_REG_ENABLE_IN1 0x42238
3881#define TSDM_REG_ENABLE_IN2 0x4223c
3882#define TSDM_REG_ENABLE_OUT1 0x42240
3883#define TSDM_REG_ENABLE_OUT2 0x42244
3884/* [RW 4] The initial number of messages that can be sent to the pxp control
3885 interface without receiving any ACK. */
3886#define TSDM_REG_INIT_CREDIT_PXP_CTRL 0x424bc
3887/* [ST 32] The number of ACK after placement messages received */
3888#define TSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x4227c
3889/* [ST 32] The number of packet end messages received from the parser */
3890#define TSDM_REG_NUM_OF_PKT_END_MSG 0x42274
3891/* [ST 32] The number of requests received from the pxp async if */
3892#define TSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x42278
3893/* [ST 32] The number of commands received in queue 0 */
3894#define TSDM_REG_NUM_OF_Q0_CMD 0x42248
3895/* [ST 32] The number of commands received in queue 10 */
3896#define TSDM_REG_NUM_OF_Q10_CMD 0x4226c
3897/* [ST 32] The number of commands received in queue 11 */
3898#define TSDM_REG_NUM_OF_Q11_CMD 0x42270
3899/* [ST 32] The number of commands received in queue 1 */
3900#define TSDM_REG_NUM_OF_Q1_CMD 0x4224c
3901/* [ST 32] The number of commands received in queue 3 */
3902#define TSDM_REG_NUM_OF_Q3_CMD 0x42250
3903/* [ST 32] The number of commands received in queue 4 */
3904#define TSDM_REG_NUM_OF_Q4_CMD 0x42254
3905/* [ST 32] The number of commands received in queue 5 */
3906#define TSDM_REG_NUM_OF_Q5_CMD 0x42258
3907/* [ST 32] The number of commands received in queue 6 */
3908#define TSDM_REG_NUM_OF_Q6_CMD 0x4225c
3909/* [ST 32] The number of commands received in queue 7 */
3910#define TSDM_REG_NUM_OF_Q7_CMD 0x42260
3911/* [ST 32] The number of commands received in queue 8 */
3912#define TSDM_REG_NUM_OF_Q8_CMD 0x42264
3913/* [ST 32] The number of commands received in queue 9 */
3914#define TSDM_REG_NUM_OF_Q9_CMD 0x42268
3915/* [RW 13] The start address in the internal RAM for the packet end message */
3916#define TSDM_REG_PCK_END_MSG_START_ADDR 0x42014
3917/* [RW 13] The start address in the internal RAM for queue counters */
3918#define TSDM_REG_Q_COUNTER_START_ADDR 0x42010
3919/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
3920#define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x42548
3921/* [R 1] parser fifo empty in sdm_sync block */
3922#define TSDM_REG_SYNC_PARSER_EMPTY 0x42550
3923/* [R 1] parser serial fifo empty in sdm_sync block */
3924#define TSDM_REG_SYNC_SYNC_EMPTY 0x42558
3925/* [RW 32] Tick for timer counter. Applicable only when
3926 ~tsdm_registers_timer_tick_enable.timer_tick_enable =1 */
3927#define TSDM_REG_TIMER_TICK 0x42000
3928/* [RW 32] Interrupt mask register #0 read/write */
3929#define TSDM_REG_TSDM_INT_MASK_0 0x4229c
3930#define TSDM_REG_TSDM_INT_MASK_1 0x422ac
c18487ee
YR		 3931/* [R 32] Interrupt register #0 read */
3932#define TSDM_REG_TSDM_INT_STS_0 0x42290
3933#define TSDM_REG_TSDM_INT_STS_1 0x422a0
a2fbb9ea
ET		 3934/* [RW 11] Parity mask register #0 read/write */
3935#define TSDM_REG_TSDM_PRTY_MASK 0x422bc
f1410647
ET		 3936/* [R 11] Parity register #0 read */
3937#define TSDM_REG_TSDM_PRTY_STS 0x422b0
a2fbb9ea
ET		 3938/* [RW 5] The number of time_slots in the arbitration cycle */
3939#define TSEM_REG_ARB_CYCLE_SIZE 0x180034
3940/* [RW 3] The source that is associated with arbitration element 0. Source
3941 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3942 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
3943#define TSEM_REG_ARB_ELEMENT0 0x180020
3944/* [RW 3] The source that is associated with arbitration element 1. Source
3945 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3946 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3947 Could not be equal to register ~tsem_registers_arb_element0.arb_element0 */
3948#define TSEM_REG_ARB_ELEMENT1 0x180024
3949/* [RW 3] The source that is associated with arbitration element 2. Source
3950 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3951 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3952 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
3953 and ~tsem_registers_arb_element1.arb_element1 */
3954#define TSEM_REG_ARB_ELEMENT2 0x180028
3955/* [RW 3] The source that is associated with arbitration element 3. Source
3956 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3957 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
3958 not be equal to register ~tsem_registers_arb_element0.arb_element0 and
3959 ~tsem_registers_arb_element1.arb_element1 and
3960 ~tsem_registers_arb_element2.arb_element2 */
3961#define TSEM_REG_ARB_ELEMENT3 0x18002c
3962/* [RW 3] The source that is associated with arbitration element 4. Source
3963 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3964 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3965 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
3966 and ~tsem_registers_arb_element1.arb_element1 and
3967 ~tsem_registers_arb_element2.arb_element2 and
3968 ~tsem_registers_arb_element3.arb_element3 */
3969#define TSEM_REG_ARB_ELEMENT4 0x180030
3970#define TSEM_REG_ENABLE_IN 0x1800a4
3971#define TSEM_REG_ENABLE_OUT 0x1800a8
3972/* [RW 32] This address space contains all registers and memories that are
3973 placed in SEM_FAST block. The SEM_FAST registers are described in
c18487ee
YR		 3974 appendix B. In order to access the sem_fast registers the base address
3975 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
a2fbb9ea
ET		 3976#define TSEM_REG_FAST_MEMORY 0x1a0000
3977/* [RW 1] Disables input messages from FIC0 May be updated during run_time
3978 by the microcode */
3979#define TSEM_REG_FIC0_DISABLE 0x180224
3980/* [RW 1] Disables input messages from FIC1 May be updated during run_time
3981 by the microcode */
3982#define TSEM_REG_FIC1_DISABLE 0x180234
3983/* [RW 15] Interrupt table Read and write access to it is not possible in
3984 the middle of the work */
3985#define TSEM_REG_INT_TABLE 0x180400
3986/* [ST 24] Statistics register. The number of messages that entered through
3987 FIC0 */
3988#define TSEM_REG_MSG_NUM_FIC0 0x180000
3989/* [ST 24] Statistics register. The number of messages that entered through
3990 FIC1 */
3991#define TSEM_REG_MSG_NUM_FIC1 0x180004
3992/* [ST 24] Statistics register. The number of messages that were sent to
3993 FOC0 */
3994#define TSEM_REG_MSG_NUM_FOC0 0x180008
3995/* [ST 24] Statistics register. The number of messages that were sent to
3996 FOC1 */
3997#define TSEM_REG_MSG_NUM_FOC1 0x18000c
3998/* [ST 24] Statistics register. The number of messages that were sent to
3999 FOC2 */
4000#define TSEM_REG_MSG_NUM_FOC2 0x180010
4001/* [ST 24] Statistics register. The number of messages that were sent to
4002 FOC3 */
4003#define TSEM_REG_MSG_NUM_FOC3 0x180014
4004/* [RW 1] Disables input messages from the passive buffer May be updated
4005 during run_time by the microcode */
4006#define TSEM_REG_PAS_DISABLE 0x18024c
4007/* [WB 128] Debug only. Passive buffer memory */
4008#define TSEM_REG_PASSIVE_BUFFER 0x181000
4009/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
4010#define TSEM_REG_PRAM 0x1c0000
4011/* [R 8] Valid sleeping threads indication have bit per thread */
4012#define TSEM_REG_SLEEP_THREADS_VALID 0x18026c
4013/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
4014#define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1802a0
4015/* [RW 8] List of free threads . There is a bit per thread. */
4016#define TSEM_REG_THREADS_LIST 0x1802e4
4017/* [RW 3] The arbitration scheme of time_slot 0 */
4018#define TSEM_REG_TS_0_AS 0x180038
4019/* [RW 3] The arbitration scheme of time_slot 10 */
4020#define TSEM_REG_TS_10_AS 0x180060
4021/* [RW 3] The arbitration scheme of time_slot 11 */
4022#define TSEM_REG_TS_11_AS 0x180064
4023/* [RW 3] The arbitration scheme of time_slot 12 */
4024#define TSEM_REG_TS_12_AS 0x180068
4025/* [RW 3] The arbitration scheme of time_slot 13 */
4026#define TSEM_REG_TS_13_AS 0x18006c
4027/* [RW 3] The arbitration scheme of time_slot 14 */
4028#define TSEM_REG_TS_14_AS 0x180070
4029/* [RW 3] The arbitration scheme of time_slot 15 */
4030#define TSEM_REG_TS_15_AS 0x180074
4031/* [RW 3] The arbitration scheme of time_slot 16 */
4032#define TSEM_REG_TS_16_AS 0x180078
4033/* [RW 3] The arbitration scheme of time_slot 17 */
4034#define TSEM_REG_TS_17_AS 0x18007c
4035/* [RW 3] The arbitration scheme of time_slot 18 */
4036#define TSEM_REG_TS_18_AS 0x180080
4037/* [RW 3] The arbitration scheme of time_slot 1 */
4038#define TSEM_REG_TS_1_AS 0x18003c
4039/* [RW 3] The arbitration scheme of time_slot 2 */
4040#define TSEM_REG_TS_2_AS 0x180040
4041/* [RW 3] The arbitration scheme of time_slot 3 */
4042#define TSEM_REG_TS_3_AS 0x180044
4043/* [RW 3] The arbitration scheme of time_slot 4 */
4044#define TSEM_REG_TS_4_AS 0x180048
4045/* [RW 3] The arbitration scheme of time_slot 5 */
4046#define TSEM_REG_TS_5_AS 0x18004c
4047/* [RW 3] The arbitration scheme of time_slot 6 */
4048#define TSEM_REG_TS_6_AS 0x180050
4049/* [RW 3] The arbitration scheme of time_slot 7 */
4050#define TSEM_REG_TS_7_AS 0x180054
4051/* [RW 3] The arbitration scheme of time_slot 8 */
4052#define TSEM_REG_TS_8_AS 0x180058
4053/* [RW 3] The arbitration scheme of time_slot 9 */
4054#define TSEM_REG_TS_9_AS 0x18005c
4055/* [RW 32] Interrupt mask register #0 read/write */
4056#define TSEM_REG_TSEM_INT_MASK_0 0x180100
4057#define TSEM_REG_TSEM_INT_MASK_1 0x180110
c18487ee
YR		 4058/* [R 32] Interrupt register #0 read */
4059#define TSEM_REG_TSEM_INT_STS_0 0x1800f4
4060#define TSEM_REG_TSEM_INT_STS_1 0x180104
a2fbb9ea
ET		 4061/* [RW 32] Parity mask register #0 read/write */
4062#define TSEM_REG_TSEM_PRTY_MASK_0 0x180120
4063#define TSEM_REG_TSEM_PRTY_MASK_1 0x180130
f1410647
ET		 4064/* [R 32] Parity register #0 read */
4065#define TSEM_REG_TSEM_PRTY_STS_0 0x180114
4066#define TSEM_REG_TSEM_PRTY_STS_1 0x180124
a2fbb9ea
ET		 4067/* [R 5] Used to read the XX protection CAM occupancy counter. */
4068#define UCM_REG_CAM_OCCUP 0xe0170
4069/* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4070 disregarded; valid output is deasserted; all other signals are treated as
4071 usual; if 1 - normal activity. */
4072#define UCM_REG_CDU_AG_RD_IFEN 0xe0038
4073/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4074 are disregarded; all other signals are treated as usual; if 1 - normal
4075 activity. */
4076#define UCM_REG_CDU_AG_WR_IFEN 0xe0034
4077/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4078 disregarded; valid output is deasserted; all other signals are treated as
4079 usual; if 1 - normal activity. */
4080#define UCM_REG_CDU_SM_RD_IFEN 0xe0040
4081/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4082 input is disregarded; all other signals are treated as usual; if 1 -
4083 normal activity. */
4084#define UCM_REG_CDU_SM_WR_IFEN 0xe003c
4085/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4086 the initial credit value; read returns the current value of the credit
4087 counter. Must be initialized to 1 at start-up. */
4088#define UCM_REG_CFC_INIT_CRD 0xe0204
4089/* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4090 weight 8 (the most prioritised); 1 stands for weight 1(least
4091 prioritised); 2 stands for weight 2; tc. */
4092#define UCM_REG_CP_WEIGHT 0xe00c4
4093/* [RW 1] Input csem Interface enable. If 0 - the valid input is
4094 disregarded; acknowledge output is deasserted; all other signals are
4095 treated as usual; if 1 - normal activity. */
4096#define UCM_REG_CSEM_IFEN 0xe0028
4097/* [RC 1] Set when the message length mismatch (relative to last indication)
4098 at the csem interface is detected. */
4099#define UCM_REG_CSEM_LENGTH_MIS 0xe0160
4100/* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4101 weight 8 (the most prioritised); 1 stands for weight 1(least
4102 prioritised); 2 stands for weight 2; tc. */
4103#define UCM_REG_CSEM_WEIGHT 0xe00b8
4104/* [RW 1] Input dorq Interface enable. If 0 - the valid input is
4105 disregarded; acknowledge output is deasserted; all other signals are
4106 treated as usual; if 1 - normal activity. */
4107#define UCM_REG_DORQ_IFEN 0xe0030
4108/* [RC 1] Set when the message length mismatch (relative to last indication)
4109 at the dorq interface is detected. */
4110#define UCM_REG_DORQ_LENGTH_MIS 0xe0168
8d9c5f34
EG		 4111/* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
4112 weight 8 (the most prioritised); 1 stands for weight 1(least
4113 prioritised); 2 stands for weight 2; tc. */
4114#define UCM_REG_DORQ_WEIGHT 0xe00c0
a2fbb9ea
ET		 4115/* [RW 8] The Event ID in case ErrorFlg input message bit is set. */
4116#define UCM_REG_ERR_EVNT_ID 0xe00a4
4117/* [RW 28] The CM erroneous header for QM and Timers formatting. */
4118#define UCM_REG_ERR_UCM_HDR 0xe00a0
4119/* [RW 8] The Event ID for Timers expiration. */
4120#define UCM_REG_EXPR_EVNT_ID 0xe00a8
4121/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
4122 writes the initial credit value; read returns the current value of the
4123 credit counter. Must be initialized to 64 at start-up. */
4124#define UCM_REG_FIC0_INIT_CRD 0xe020c
4125/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
4126 writes the initial credit value; read returns the current value of the
4127 credit counter. Must be initialized to 64 at start-up. */
4128#define UCM_REG_FIC1_INIT_CRD 0xe0210
4129/* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
4130 - strict priority defined by ~ucm_registers_gr_ag_pr.gr_ag_pr;
4131 ~ucm_registers_gr_ld0_pr.gr_ld0_pr and
4132 ~ucm_registers_gr_ld1_pr.gr_ld1_pr. */
4133#define UCM_REG_GR_ARB_TYPE 0xe0144
4134/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
4135 highest priority is 3. It is supposed that the Store channel group is
4136 compliment to the others. */
4137#define UCM_REG_GR_LD0_PR 0xe014c
4138/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
4139 highest priority is 3. It is supposed that the Store channel group is
4140 compliment to the others. */
4141#define UCM_REG_GR_LD1_PR 0xe0150
4142/* [RW 2] The queue index for invalidate counter flag decision. */
4143#define UCM_REG_INV_CFLG_Q 0xe00e4
4144/* [RW 5] The number of double REG-pairs; loaded from the STORM context and
4145 sent to STORM; for a specific connection type. the double REG-pairs are
4146 used in order to align to STORM context row size of 128 bits. The offset
4147 of these data in the STORM context is always 0. Index _i stands for the
4148 connection type (one of 16). */
4149#define UCM_REG_N_SM_CTX_LD_0 0xe0054
4150#define UCM_REG_N_SM_CTX_LD_1 0xe0058
4151#define UCM_REG_N_SM_CTX_LD_10 0xe007c
4152#define UCM_REG_N_SM_CTX_LD_11 0xe0080
4153#define UCM_REG_N_SM_CTX_LD_12 0xe0084
4154#define UCM_REG_N_SM_CTX_LD_13 0xe0088
4155#define UCM_REG_N_SM_CTX_LD_14 0xe008c
4156#define UCM_REG_N_SM_CTX_LD_15 0xe0090
4157#define UCM_REG_N_SM_CTX_LD_2 0xe005c
4158#define UCM_REG_N_SM_CTX_LD_3 0xe0060
4159#define UCM_REG_N_SM_CTX_LD_4 0xe0064
c18487ee 4160#define UCM_REG_N_SM_CTX_LD_5 0xe0068
a2fbb9ea
ET		 4161#define UCM_REG_PHYS_QNUM0_0 0xe0110
4162#define UCM_REG_PHYS_QNUM0_1 0xe0114
a2fbb9ea
ET		 4163#define UCM_REG_PHYS_QNUM1_0 0xe0118
4164#define UCM_REG_PHYS_QNUM1_1 0xe011c
c18487ee
YR		 4165#define UCM_REG_PHYS_QNUM2_0 0xe0120
4166#define UCM_REG_PHYS_QNUM2_1 0xe0124
4167#define UCM_REG_PHYS_QNUM3_0 0xe0128
4168#define UCM_REG_PHYS_QNUM3_1 0xe012c
a2fbb9ea
ET		 4169/* [RW 8] The Event ID for Timers formatting in case of stop done. */
4170#define UCM_REG_STOP_EVNT_ID 0xe00ac
4171/* [RC 1] Set when the message length mismatch (relative to last indication)
4172 at the STORM interface is detected. */
4173#define UCM_REG_STORM_LENGTH_MIS 0xe0154
4174/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
4175 disregarded; acknowledge output is deasserted; all other signals are
4176 treated as usual; if 1 - normal activity. */
4177#define UCM_REG_STORM_UCM_IFEN 0xe0010
8d9c5f34
EG		 4178/* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
4179 weight 8 (the most prioritised); 1 stands for weight 1(least
4180 prioritised); 2 stands for weight 2; tc. */
4181#define UCM_REG_STORM_WEIGHT 0xe00b0
a2fbb9ea
ET		 4182/* [RW 4] Timers output initial credit. Max credit available - 15.Write
4183 writes the initial credit value; read returns the current value of the
4184 credit counter. Must be initialized to 4 at start-up. */
4185#define UCM_REG_TM_INIT_CRD 0xe021c
4186/* [RW 28] The CM header for Timers expiration command. */
4187#define UCM_REG_TM_UCM_HDR 0xe009c
4188/* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
4189 disregarded; acknowledge output is deasserted; all other signals are
4190 treated as usual; if 1 - normal activity. */
4191#define UCM_REG_TM_UCM_IFEN 0xe001c
8d9c5f34
EG		 4192/* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
4193 weight 8 (the most prioritised); 1 stands for weight 1(least
4194 prioritised); 2 stands for weight 2; tc. */
4195#define UCM_REG_TM_WEIGHT 0xe00d4
a2fbb9ea
ET		 4196/* [RW 1] Input tsem Interface enable. If 0 - the valid input is
4197 disregarded; acknowledge output is deasserted; all other signals are
4198 treated as usual; if 1 - normal activity. */
4199#define UCM_REG_TSEM_IFEN 0xe0024
4200/* [RC 1] Set when the message length mismatch (relative to last indication)
4201 at the tsem interface is detected. */
4202#define UCM_REG_TSEM_LENGTH_MIS 0xe015c
4203/* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
4204 weight 8 (the most prioritised); 1 stands for weight 1(least
4205 prioritised); 2 stands for weight 2; tc. */
4206#define UCM_REG_TSEM_WEIGHT 0xe00b4
4207/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
4208 acknowledge output is deasserted; all other signals are treated as usual;
4209 if 1 - normal activity. */
4210#define UCM_REG_UCM_CFC_IFEN 0xe0044
4211/* [RW 11] Interrupt mask register #0 read/write */
4212#define UCM_REG_UCM_INT_MASK 0xe01d4
4213/* [R 11] Interrupt register #0 read */
4214#define UCM_REG_UCM_INT_STS 0xe01c8
c18487ee
YR		 4215/* [R 27] Parity register #0 read */
4216#define UCM_REG_UCM_PRTY_STS 0xe01d8
a2fbb9ea
ET		 4217/* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS
4218 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
4219 Is used to determine the number of the AG context REG-pairs written back;
4220 when the Reg1WbFlg isn't set. */
4221#define UCM_REG_UCM_REG0_SZ 0xe00dc
4222/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
4223 disregarded; valid is deasserted; all other signals are treated as usual;
4224 if 1 - normal activity. */
4225#define UCM_REG_UCM_STORM0_IFEN 0xe0004
4226/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
4227 disregarded; valid is deasserted; all other signals are treated as usual;
4228 if 1 - normal activity. */
4229#define UCM_REG_UCM_STORM1_IFEN 0xe0008
4230/* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
4231 disregarded; acknowledge output is deasserted; all other signals are
4232 treated as usual; if 1 - normal activity. */
4233#define UCM_REG_UCM_TM_IFEN 0xe0020
4234/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
4235 disregarded; valid is deasserted; all other signals are treated as usual;
4236 if 1 - normal activity. */
4237#define UCM_REG_UCM_UQM_IFEN 0xe000c
4238/* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
4239#define UCM_REG_UCM_UQM_USE_Q 0xe00d8
4240/* [RW 6] QM output initial credit. Max credit available - 32.Write writes
4241 the initial credit value; read returns the current value of the credit
4242 counter. Must be initialized to 32 at start-up. */
4243#define UCM_REG_UQM_INIT_CRD 0xe0220
4244/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
4245 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4246 prioritised); 2 stands for weight 2; tc. */
4247#define UCM_REG_UQM_P_WEIGHT 0xe00cc
8d9c5f34
EG		 4248/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
4249 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4250 prioritised); 2 stands for weight 2; tc. */
4251#define UCM_REG_UQM_S_WEIGHT 0xe00d0
a2fbb9ea
ET		 4252/* [RW 28] The CM header value for QM request (primary). */
4253#define UCM_REG_UQM_UCM_HDR_P 0xe0094
4254/* [RW 28] The CM header value for QM request (secondary). */
4255#define UCM_REG_UQM_UCM_HDR_S 0xe0098
4256/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
4257 acknowledge output is deasserted; all other signals are treated as usual;
4258 if 1 - normal activity. */
4259#define UCM_REG_UQM_UCM_IFEN 0xe0014
4260/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
4261 acknowledge output is deasserted; all other signals are treated as usual;
4262 if 1 - normal activity. */
4263#define UCM_REG_USDM_IFEN 0xe0018
4264/* [RC 1] Set when the message length mismatch (relative to last indication)
4265 at the SDM interface is detected. */
4266#define UCM_REG_USDM_LENGTH_MIS 0xe0158
8d9c5f34
EG		 4267/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
4268 weight 8 (the most prioritised); 1 stands for weight 1(least
4269 prioritised); 2 stands for weight 2; tc. */
4270#define UCM_REG_USDM_WEIGHT 0xe00c8
a2fbb9ea
ET		 4271/* [RW 1] Input xsem Interface enable. If 0 - the valid input is
4272 disregarded; acknowledge output is deasserted; all other signals are
4273 treated as usual; if 1 - normal activity. */
4274#define UCM_REG_XSEM_IFEN 0xe002c
4275/* [RC 1] Set when the message length mismatch (relative to last indication)
4276 at the xsem interface isdetected. */
4277#define UCM_REG_XSEM_LENGTH_MIS 0xe0164
8d9c5f34
EG		 4278/* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
4279 weight 8 (the most prioritised); 1 stands for weight 1(least
4280 prioritised); 2 stands for weight 2; tc. */
4281#define UCM_REG_XSEM_WEIGHT 0xe00bc
a2fbb9ea
ET		 4282/* [RW 20] Indirect access to the descriptor table of the XX protection
4283 mechanism. The fields are:[5:0] - message length; 14:6] - message
4284 pointer; 19:15] - next pointer. */
4285#define UCM_REG_XX_DESCR_TABLE 0xe0280
c18487ee 4286#define UCM_REG_XX_DESCR_TABLE_SIZE 32
a2fbb9ea
ET		 4287/* [R 6] Use to read the XX protection Free counter. */
4288#define UCM_REG_XX_FREE 0xe016c
4289/* [RW 6] Initial value for the credit counter; responsible for fulfilling
4290 of the Input Stage XX protection buffer by the XX protection pending
4291 messages. Write writes the initial credit value; read returns the current
4292 value of the credit counter. Must be initialized to 12 at start-up. */
4293#define UCM_REG_XX_INIT_CRD 0xe0224
4294/* [RW 6] The maximum number of pending messages; which may be stored in XX
4295 protection. ~ucm_registers_xx_free.xx_free read on read. */
4296#define UCM_REG_XX_MSG_NUM 0xe0228
4297/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
4298#define UCM_REG_XX_OVFL_EVNT_ID 0xe004c
4299/* [RW 16] Indirect access to the XX table of the XX protection mechanism.
4300 The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] -
4301 header pointer. */
4302#define UCM_REG_XX_TABLE 0xe0300
4303/* [RW 8] The event id for aggregated interrupt 0 */
4304#define USDM_REG_AGG_INT_EVENT_0 0xc4038
4305#define USDM_REG_AGG_INT_EVENT_1 0xc403c
4306#define USDM_REG_AGG_INT_EVENT_10 0xc4060
4307#define USDM_REG_AGG_INT_EVENT_11 0xc4064
4308#define USDM_REG_AGG_INT_EVENT_12 0xc4068
4309#define USDM_REG_AGG_INT_EVENT_13 0xc406c
4310#define USDM_REG_AGG_INT_EVENT_14 0xc4070
4311#define USDM_REG_AGG_INT_EVENT_15 0xc4074
4312#define USDM_REG_AGG_INT_EVENT_16 0xc4078
4313#define USDM_REG_AGG_INT_EVENT_17 0xc407c
4314#define USDM_REG_AGG_INT_EVENT_18 0xc4080
4315#define USDM_REG_AGG_INT_EVENT_19 0xc4084
c18487ee
YR		 4316#define USDM_REG_AGG_INT_EVENT_2 0xc4040
4317#define USDM_REG_AGG_INT_EVENT_20 0xc4088
4318#define USDM_REG_AGG_INT_EVENT_21 0xc408c
4319#define USDM_REG_AGG_INT_EVENT_22 0xc4090
4320#define USDM_REG_AGG_INT_EVENT_23 0xc4094
4321#define USDM_REG_AGG_INT_EVENT_24 0xc4098
4322#define USDM_REG_AGG_INT_EVENT_25 0xc409c
4323#define USDM_REG_AGG_INT_EVENT_26 0xc40a0
4324#define USDM_REG_AGG_INT_EVENT_27 0xc40a4
4325#define USDM_REG_AGG_INT_EVENT_28 0xc40a8
4326#define USDM_REG_AGG_INT_EVENT_29 0xc40ac
4327#define USDM_REG_AGG_INT_EVENT_3 0xc4044
4328#define USDM_REG_AGG_INT_EVENT_30 0xc40b0
4329#define USDM_REG_AGG_INT_EVENT_31 0xc40b4
4330#define USDM_REG_AGG_INT_EVENT_4 0xc4048
8d9c5f34 4331#define USDM_REG_AGG_INT_EVENT_5 0xc404c
a2fbb9ea
ET		 4332/* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
4333 or auto-mask-mode (1) */
4334#define USDM_REG_AGG_INT_MODE_0 0xc41b8
4335#define USDM_REG_AGG_INT_MODE_1 0xc41bc
4336#define USDM_REG_AGG_INT_MODE_10 0xc41e0
4337#define USDM_REG_AGG_INT_MODE_11 0xc41e4
4338#define USDM_REG_AGG_INT_MODE_12 0xc41e8
4339#define USDM_REG_AGG_INT_MODE_13 0xc41ec
4340#define USDM_REG_AGG_INT_MODE_14 0xc41f0
4341#define USDM_REG_AGG_INT_MODE_15 0xc41f4
4342#define USDM_REG_AGG_INT_MODE_16 0xc41f8
4343#define USDM_REG_AGG_INT_MODE_17 0xc41fc
4344#define USDM_REG_AGG_INT_MODE_18 0xc4200
4345#define USDM_REG_AGG_INT_MODE_19 0xc4204
8d9c5f34
EG		 4346#define USDM_REG_AGG_INT_MODE_4 0xc41c8
4347#define USDM_REG_AGG_INT_MODE_5 0xc41cc
a2fbb9ea
ET		 4348/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
4349#define USDM_REG_CFC_RSP_START_ADDR 0xc4008
4350/* [RW 16] The maximum value of the competion counter #0 */
4351#define USDM_REG_CMP_COUNTER_MAX0 0xc401c
4352/* [RW 16] The maximum value of the competion counter #1 */
4353#define USDM_REG_CMP_COUNTER_MAX1 0xc4020
4354/* [RW 16] The maximum value of the competion counter #2 */
4355#define USDM_REG_CMP_COUNTER_MAX2 0xc4024
4356/* [RW 16] The maximum value of the competion counter #3 */
4357#define USDM_REG_CMP_COUNTER_MAX3 0xc4028
4358/* [RW 13] The start address in the internal RAM for the completion
4359 counters. */
4360#define USDM_REG_CMP_COUNTER_START_ADDR 0xc400c
4361#define USDM_REG_ENABLE_IN1 0xc4238
4362#define USDM_REG_ENABLE_IN2 0xc423c
4363#define USDM_REG_ENABLE_OUT1 0xc4240
4364#define USDM_REG_ENABLE_OUT2 0xc4244
4365/* [RW 4] The initial number of messages that can be sent to the pxp control
4366 interface without receiving any ACK. */
4367#define USDM_REG_INIT_CREDIT_PXP_CTRL 0xc44c0
4368/* [ST 32] The number of ACK after placement messages received */
4369#define USDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc4280
4370/* [ST 32] The number of packet end messages received from the parser */
4371#define USDM_REG_NUM_OF_PKT_END_MSG 0xc4278
4372/* [ST 32] The number of requests received from the pxp async if */
4373#define USDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc427c
4374/* [ST 32] The number of commands received in queue 0 */
4375#define USDM_REG_NUM_OF_Q0_CMD 0xc4248
4376/* [ST 32] The number of commands received in queue 10 */
4377#define USDM_REG_NUM_OF_Q10_CMD 0xc4270
4378/* [ST 32] The number of commands received in queue 11 */
4379#define USDM_REG_NUM_OF_Q11_CMD 0xc4274
4380/* [ST 32] The number of commands received in queue 1 */
4381#define USDM_REG_NUM_OF_Q1_CMD 0xc424c
4382/* [ST 32] The number of commands received in queue 2 */
4383#define USDM_REG_NUM_OF_Q2_CMD 0xc4250
4384/* [ST 32] The number of commands received in queue 3 */
4385#define USDM_REG_NUM_OF_Q3_CMD 0xc4254
4386/* [ST 32] The number of commands received in queue 4 */
4387#define USDM_REG_NUM_OF_Q4_CMD 0xc4258
4388/* [ST 32] The number of commands received in queue 5 */
4389#define USDM_REG_NUM_OF_Q5_CMD 0xc425c
4390/* [ST 32] The number of commands received in queue 6 */
4391#define USDM_REG_NUM_OF_Q6_CMD 0xc4260
4392/* [ST 32] The number of commands received in queue 7 */
4393#define USDM_REG_NUM_OF_Q7_CMD 0xc4264
4394/* [ST 32] The number of commands received in queue 8 */
4395#define USDM_REG_NUM_OF_Q8_CMD 0xc4268
4396/* [ST 32] The number of commands received in queue 9 */
4397#define USDM_REG_NUM_OF_Q9_CMD 0xc426c
4398/* [RW 13] The start address in the internal RAM for the packet end message */
4399#define USDM_REG_PCK_END_MSG_START_ADDR 0xc4014
4400/* [RW 13] The start address in the internal RAM for queue counters */
4401#define USDM_REG_Q_COUNTER_START_ADDR 0xc4010
4402/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
4403#define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc4550
4404/* [R 1] parser fifo empty in sdm_sync block */
4405#define USDM_REG_SYNC_PARSER_EMPTY 0xc4558
4406/* [R 1] parser serial fifo empty in sdm_sync block */
4407#define USDM_REG_SYNC_SYNC_EMPTY 0xc4560
4408/* [RW 32] Tick for timer counter. Applicable only when
4409 ~usdm_registers_timer_tick_enable.timer_tick_enable =1 */
4410#define USDM_REG_TIMER_TICK 0xc4000
4411/* [RW 32] Interrupt mask register #0 read/write */
4412#define USDM_REG_USDM_INT_MASK_0 0xc42a0
4413#define USDM_REG_USDM_INT_MASK_1 0xc42b0
c18487ee
YR		 4414/* [R 32] Interrupt register #0 read */
4415#define USDM_REG_USDM_INT_STS_0 0xc4294
4416#define USDM_REG_USDM_INT_STS_1 0xc42a4
a2fbb9ea
ET		 4417/* [RW 11] Parity mask register #0 read/write */
4418#define USDM_REG_USDM_PRTY_MASK 0xc42c0
f1410647
ET		 4419/* [R 11] Parity register #0 read */
4420#define USDM_REG_USDM_PRTY_STS 0xc42b4
a2fbb9ea
ET		 4421/* [RW 5] The number of time_slots in the arbitration cycle */
4422#define USEM_REG_ARB_CYCLE_SIZE 0x300034
4423/* [RW 3] The source that is associated with arbitration element 0. Source
4424 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4425 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
4426#define USEM_REG_ARB_ELEMENT0 0x300020
4427/* [RW 3] The source that is associated with arbitration element 1. Source
4428 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4429 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4430 Could not be equal to register ~usem_registers_arb_element0.arb_element0 */
4431#define USEM_REG_ARB_ELEMENT1 0x300024
4432/* [RW 3] The source that is associated with arbitration element 2. Source
4433 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4434 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4435 Could not be equal to register ~usem_registers_arb_element0.arb_element0
4436 and ~usem_registers_arb_element1.arb_element1 */
4437#define USEM_REG_ARB_ELEMENT2 0x300028
4438/* [RW 3] The source that is associated with arbitration element 3. Source
4439 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4440 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
4441 not be equal to register ~usem_registers_arb_element0.arb_element0 and
4442 ~usem_registers_arb_element1.arb_element1 and
4443 ~usem_registers_arb_element2.arb_element2 */
4444#define USEM_REG_ARB_ELEMENT3 0x30002c
4445/* [RW 3] The source that is associated with arbitration element 4. Source
4446 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4447 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4448 Could not be equal to register ~usem_registers_arb_element0.arb_element0
4449 and ~usem_registers_arb_element1.arb_element1 and
4450 ~usem_registers_arb_element2.arb_element2 and
4451 ~usem_registers_arb_element3.arb_element3 */
4452#define USEM_REG_ARB_ELEMENT4 0x300030
4453#define USEM_REG_ENABLE_IN 0x3000a4
4454#define USEM_REG_ENABLE_OUT 0x3000a8
4455/* [RW 32] This address space contains all registers and memories that are
4456 placed in SEM_FAST block. The SEM_FAST registers are described in
c18487ee
YR		 4457 appendix B. In order to access the sem_fast registers the base address
4458 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
a2fbb9ea
ET		 4459#define USEM_REG_FAST_MEMORY 0x320000
4460/* [RW 1] Disables input messages from FIC0 May be updated during run_time
4461 by the microcode */
4462#define USEM_REG_FIC0_DISABLE 0x300224
4463/* [RW 1] Disables input messages from FIC1 May be updated during run_time
4464 by the microcode */
4465#define USEM_REG_FIC1_DISABLE 0x300234
4466/* [RW 15] Interrupt table Read and write access to it is not possible in
4467 the middle of the work */
4468#define USEM_REG_INT_TABLE 0x300400
4469/* [ST 24] Statistics register. The number of messages that entered through
4470 FIC0 */
4471#define USEM_REG_MSG_NUM_FIC0 0x300000
4472/* [ST 24] Statistics register. The number of messages that entered through
4473 FIC1 */
4474#define USEM_REG_MSG_NUM_FIC1 0x300004
4475/* [ST 24] Statistics register. The number of messages that were sent to
4476 FOC0 */
4477#define USEM_REG_MSG_NUM_FOC0 0x300008
4478/* [ST 24] Statistics register. The number of messages that were sent to
4479 FOC1 */
4480#define USEM_REG_MSG_NUM_FOC1 0x30000c
4481/* [ST 24] Statistics register. The number of messages that were sent to
4482 FOC2 */
4483#define USEM_REG_MSG_NUM_FOC2 0x300010
4484/* [ST 24] Statistics register. The number of messages that were sent to
4485 FOC3 */
4486#define USEM_REG_MSG_NUM_FOC3 0x300014
4487/* [RW 1] Disables input messages from the passive buffer May be updated
4488 during run_time by the microcode */
4489#define USEM_REG_PAS_DISABLE 0x30024c
4490/* [WB 128] Debug only. Passive buffer memory */
4491#define USEM_REG_PASSIVE_BUFFER 0x302000
4492/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
4493#define USEM_REG_PRAM 0x340000
4494/* [R 16] Valid sleeping threads indication have bit per thread */
4495#define USEM_REG_SLEEP_THREADS_VALID 0x30026c
4496/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
4497#define USEM_REG_SLOW_EXT_STORE_EMPTY 0x3002a0
4498/* [RW 16] List of free threads . There is a bit per thread. */
4499#define USEM_REG_THREADS_LIST 0x3002e4
4500/* [RW 3] The arbitration scheme of time_slot 0 */
4501#define USEM_REG_TS_0_AS 0x300038
4502/* [RW 3] The arbitration scheme of time_slot 10 */
4503#define USEM_REG_TS_10_AS 0x300060
4504/* [RW 3] The arbitration scheme of time_slot 11 */
4505#define USEM_REG_TS_11_AS 0x300064
4506/* [RW 3] The arbitration scheme of time_slot 12 */
4507#define USEM_REG_TS_12_AS 0x300068
4508/* [RW 3] The arbitration scheme of time_slot 13 */
4509#define USEM_REG_TS_13_AS 0x30006c
4510/* [RW 3] The arbitration scheme of time_slot 14 */
4511#define USEM_REG_TS_14_AS 0x300070
4512/* [RW 3] The arbitration scheme of time_slot 15 */
4513#define USEM_REG_TS_15_AS 0x300074
4514/* [RW 3] The arbitration scheme of time_slot 16 */
4515#define USEM_REG_TS_16_AS 0x300078
4516/* [RW 3] The arbitration scheme of time_slot 17 */
4517#define USEM_REG_TS_17_AS 0x30007c
4518/* [RW 3] The arbitration scheme of time_slot 18 */
4519#define USEM_REG_TS_18_AS 0x300080
4520/* [RW 3] The arbitration scheme of time_slot 1 */
4521#define USEM_REG_TS_1_AS 0x30003c
4522/* [RW 3] The arbitration scheme of time_slot 2 */
4523#define USEM_REG_TS_2_AS 0x300040
4524/* [RW 3] The arbitration scheme of time_slot 3 */
4525#define USEM_REG_TS_3_AS 0x300044
4526/* [RW 3] The arbitration scheme of time_slot 4 */
4527#define USEM_REG_TS_4_AS 0x300048
4528/* [RW 3] The arbitration scheme of time_slot 5 */
4529#define USEM_REG_TS_5_AS 0x30004c
4530/* [RW 3] The arbitration scheme of time_slot 6 */
4531#define USEM_REG_TS_6_AS 0x300050
4532/* [RW 3] The arbitration scheme of time_slot 7 */
4533#define USEM_REG_TS_7_AS 0x300054
4534/* [RW 3] The arbitration scheme of time_slot 8 */
4535#define USEM_REG_TS_8_AS 0x300058
4536/* [RW 3] The arbitration scheme of time_slot 9 */
4537#define USEM_REG_TS_9_AS 0x30005c
4538/* [RW 32] Interrupt mask register #0 read/write */
4539#define USEM_REG_USEM_INT_MASK_0 0x300110
4540#define USEM_REG_USEM_INT_MASK_1 0x300120
c18487ee
YR		 4541/* [R 32] Interrupt register #0 read */
4542#define USEM_REG_USEM_INT_STS_0 0x300104
4543#define USEM_REG_USEM_INT_STS_1 0x300114
a2fbb9ea
ET		 4544/* [RW 32] Parity mask register #0 read/write */
4545#define USEM_REG_USEM_PRTY_MASK_0 0x300130
4546#define USEM_REG_USEM_PRTY_MASK_1 0x300140
f1410647
ET		 4547/* [R 32] Parity register #0 read */
4548#define USEM_REG_USEM_PRTY_STS_0 0x300124
4549#define USEM_REG_USEM_PRTY_STS_1 0x300134
a2fbb9ea
ET		 4550/* [RW 2] The queue index for registration on Aux1 counter flag. */
4551#define XCM_REG_AUX1_Q 0x20134
4552/* [RW 2] Per each decision rule the queue index to register to. */
4553#define XCM_REG_AUX_CNT_FLG_Q_19 0x201b0
4554/* [R 5] Used to read the XX protection CAM occupancy counter. */
4555#define XCM_REG_CAM_OCCUP 0x20244
4556/* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4557 disregarded; valid output is deasserted; all other signals are treated as
4558 usual; if 1 - normal activity. */
4559#define XCM_REG_CDU_AG_RD_IFEN 0x20044
4560/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4561 are disregarded; all other signals are treated as usual; if 1 - normal
4562 activity. */
4563#define XCM_REG_CDU_AG_WR_IFEN 0x20040
4564/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4565 disregarded; valid output is deasserted; all other signals are treated as
4566 usual; if 1 - normal activity. */
4567#define XCM_REG_CDU_SM_RD_IFEN 0x2004c
4568/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4569 input is disregarded; all other signals are treated as usual; if 1 -
4570 normal activity. */
4571#define XCM_REG_CDU_SM_WR_IFEN 0x20048
4572/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4573 the initial credit value; read returns the current value of the credit
4574 counter. Must be initialized to 1 at start-up. */
4575#define XCM_REG_CFC_INIT_CRD 0x20404
4576/* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4577 weight 8 (the most prioritised); 1 stands for weight 1(least
4578 prioritised); 2 stands for weight 2; tc. */
4579#define XCM_REG_CP_WEIGHT 0x200dc
4580/* [RW 1] Input csem Interface enable. If 0 - the valid input is
4581 disregarded; acknowledge output is deasserted; all other signals are
4582 treated as usual; if 1 - normal activity. */
4583#define XCM_REG_CSEM_IFEN 0x20028
4584/* [RC 1] Set at message length mismatch (relative to last indication) at
4585 the csem interface. */
4586#define XCM_REG_CSEM_LENGTH_MIS 0x20228
4587/* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4588 weight 8 (the most prioritised); 1 stands for weight 1(least
4589 prioritised); 2 stands for weight 2; tc. */
4590#define XCM_REG_CSEM_WEIGHT 0x200c4
4591/* [RW 1] Input dorq Interface enable. If 0 - the valid input is
4592 disregarded; acknowledge output is deasserted; all other signals are
4593 treated as usual; if 1 - normal activity. */
4594#define XCM_REG_DORQ_IFEN 0x20030
4595/* [RC 1] Set at message length mismatch (relative to last indication) at
4596 the dorq interface. */
4597#define XCM_REG_DORQ_LENGTH_MIS 0x20230
8d9c5f34
EG		 4598/* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
4599 weight 8 (the most prioritised); 1 stands for weight 1(least
4600 prioritised); 2 stands for weight 2; tc. */
4601#define XCM_REG_DORQ_WEIGHT 0x200cc
a2fbb9ea
ET		 4602/* [RW 8] The Event ID in case the ErrorFlg input message bit is set. */
4603#define XCM_REG_ERR_EVNT_ID 0x200b0
4604/* [RW 28] The CM erroneous header for QM and Timers formatting. */
4605#define XCM_REG_ERR_XCM_HDR 0x200ac
4606/* [RW 8] The Event ID for Timers expiration. */
4607#define XCM_REG_EXPR_EVNT_ID 0x200b4
4608/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
4609 writes the initial credit value; read returns the current value of the
4610 credit counter. Must be initialized to 64 at start-up. */
4611#define XCM_REG_FIC0_INIT_CRD 0x2040c
4612/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
4613 writes the initial credit value; read returns the current value of the
4614 credit counter. Must be initialized to 64 at start-up. */
4615#define XCM_REG_FIC1_INIT_CRD 0x20410
a2fbb9ea
ET		 4616#define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x20118
4617#define XCM_REG_GLB_DEL_ACK_MAX_CNT_1 0x2011c
a2fbb9ea
ET		 4618#define XCM_REG_GLB_DEL_ACK_TMR_VAL_0 0x20108
4619#define XCM_REG_GLB_DEL_ACK_TMR_VAL_1 0x2010c
4620/* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1
4621 - strict priority defined by ~xcm_registers_gr_ag_pr.gr_ag_pr;
4622 ~xcm_registers_gr_ld0_pr.gr_ld0_pr and
4623 ~xcm_registers_gr_ld1_pr.gr_ld1_pr. */
4624#define XCM_REG_GR_ARB_TYPE 0x2020c
4625/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
4626 highest priority is 3. It is supposed that the Channel group is the
4627 compliment of the other 3 groups. */
4628#define XCM_REG_GR_LD0_PR 0x20214
4629/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
4630 highest priority is 3. It is supposed that the Channel group is the
4631 compliment of the other 3 groups. */
4632#define XCM_REG_GR_LD1_PR 0x20218
4633/* [RW 1] Input nig0 Interface enable. If 0 - the valid input is
4634 disregarded; acknowledge output is deasserted; all other signals are
4635 treated as usual; if 1 - normal activity. */
4636#define XCM_REG_NIG0_IFEN 0x20038
4637/* [RC 1] Set at message length mismatch (relative to last indication) at
4638 the nig0 interface. */
4639#define XCM_REG_NIG0_LENGTH_MIS 0x20238
8d9c5f34
EG		 4640/* [RW 3] The weight of the input nig0 in the WRR mechanism. 0 stands for
4641 weight 8 (the most prioritised); 1 stands for weight 1(least
4642 prioritised); 2 stands for weight 2; tc. */
4643#define XCM_REG_NIG0_WEIGHT 0x200d4
a2fbb9ea
ET		 4644/* [RW 1] Input nig1 Interface enable. If 0 - the valid input is
4645 disregarded; acknowledge output is deasserted; all other signals are
4646 treated as usual; if 1 - normal activity. */
4647#define XCM_REG_NIG1_IFEN 0x2003c
4648/* [RC 1] Set at message length mismatch (relative to last indication) at
4649 the nig1 interface. */
4650#define XCM_REG_NIG1_LENGTH_MIS 0x2023c
4651/* [RW 3] The weight of the input nig1 in the WRR mechanism. 0 stands for
4652 weight 8 (the most prioritised); 1 stands for weight 1(least
4653 prioritised); 2 stands for weight 2; tc. */
4654#define XCM_REG_NIG1_WEIGHT 0x200d8
4655/* [RW 5] The number of double REG-pairs; loaded from the STORM context and
4656 sent to STORM; for a specific connection type. The double REG-pairs are
4657 used in order to align to STORM context row size of 128 bits. The offset
4658 of these data in the STORM context is always 0. Index _i stands for the
4659 connection type (one of 16). */
4660#define XCM_REG_N_SM_CTX_LD_0 0x20060
4661#define XCM_REG_N_SM_CTX_LD_1 0x20064
4662#define XCM_REG_N_SM_CTX_LD_10 0x20088
4663#define XCM_REG_N_SM_CTX_LD_11 0x2008c
4664#define XCM_REG_N_SM_CTX_LD_12 0x20090
4665#define XCM_REG_N_SM_CTX_LD_13 0x20094
4666#define XCM_REG_N_SM_CTX_LD_14 0x20098
4667#define XCM_REG_N_SM_CTX_LD_15 0x2009c
4668#define XCM_REG_N_SM_CTX_LD_2 0x20068
4669#define XCM_REG_N_SM_CTX_LD_3 0x2006c
4670#define XCM_REG_N_SM_CTX_LD_4 0x20070
c18487ee 4671#define XCM_REG_N_SM_CTX_LD_5 0x20074
a2fbb9ea
ET		 4672/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
4673 acknowledge output is deasserted; all other signals are treated as usual;
4674 if 1 - normal activity. */
4675#define XCM_REG_PBF_IFEN 0x20034
4676/* [RC 1] Set at message length mismatch (relative to last indication) at
4677 the pbf interface. */
4678#define XCM_REG_PBF_LENGTH_MIS 0x20234
4679/* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
4680 weight 8 (the most prioritised); 1 stands for weight 1(least
4681 prioritised); 2 stands for weight 2; tc. */
4682#define XCM_REG_PBF_WEIGHT 0x200d0
c18487ee
YR		 4683#define XCM_REG_PHYS_QNUM3_0 0x20100
4684#define XCM_REG_PHYS_QNUM3_1 0x20104
a2fbb9ea
ET		 4685/* [RW 8] The Event ID for Timers formatting in case of stop done. */
4686#define XCM_REG_STOP_EVNT_ID 0x200b8
4687/* [RC 1] Set at message length mismatch (relative to last indication) at
4688 the STORM interface. */
4689#define XCM_REG_STORM_LENGTH_MIS 0x2021c
4690/* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
4691 weight 8 (the most prioritised); 1 stands for weight 1(least
4692 prioritised); 2 stands for weight 2; tc. */
4693#define XCM_REG_STORM_WEIGHT 0x200bc
4694/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
4695 disregarded; acknowledge output is deasserted; all other signals are
4696 treated as usual; if 1 - normal activity. */
4697#define XCM_REG_STORM_XCM_IFEN 0x20010
4698/* [RW 4] Timers output initial credit. Max credit available - 15.Write
4699 writes the initial credit value; read returns the current value of the
4700 credit counter. Must be initialized to 4 at start-up. */
4701#define XCM_REG_TM_INIT_CRD 0x2041c
8d9c5f34
EG		 4702/* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
4703 weight 8 (the most prioritised); 1 stands for weight 1(least
4704 prioritised); 2 stands for weight 2; tc. */
4705#define XCM_REG_TM_WEIGHT 0x200ec
a2fbb9ea
ET		 4706/* [RW 28] The CM header for Timers expiration command. */
4707#define XCM_REG_TM_XCM_HDR 0x200a8
4708/* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
4709 disregarded; acknowledge output is deasserted; all other signals are
4710 treated as usual; if 1 - normal activity. */
4711#define XCM_REG_TM_XCM_IFEN 0x2001c
4712/* [RW 1] Input tsem Interface enable. If 0 - the valid input is
4713 disregarded; acknowledge output is deasserted; all other signals are
4714 treated as usual; if 1 - normal activity. */
4715#define XCM_REG_TSEM_IFEN 0x20024
4716/* [RC 1] Set at message length mismatch (relative to last indication) at
4717 the tsem interface. */
4718#define XCM_REG_TSEM_LENGTH_MIS 0x20224
4719/* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
4720 weight 8 (the most prioritised); 1 stands for weight 1(least
4721 prioritised); 2 stands for weight 2; tc. */
4722#define XCM_REG_TSEM_WEIGHT 0x200c0
4723/* [RW 2] The queue index for registration on UNA greater NXT decision rule. */
4724#define XCM_REG_UNA_GT_NXT_Q 0x20120
4725/* [RW 1] Input usem Interface enable. If 0 - the valid input is
4726 disregarded; acknowledge output is deasserted; all other signals are
4727 treated as usual; if 1 - normal activity. */
4728#define XCM_REG_USEM_IFEN 0x2002c
4729/* [RC 1] Message length mismatch (relative to last indication) at the usem
4730 interface. */
4731#define XCM_REG_USEM_LENGTH_MIS 0x2022c
4732/* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
4733 weight 8 (the most prioritised); 1 stands for weight 1(least
4734 prioritised); 2 stands for weight 2; tc. */
4735#define XCM_REG_USEM_WEIGHT 0x200c8
a2fbb9ea 4736#define XCM_REG_WU_DA_CNT_CMD00 0x201d4
a2fbb9ea 4737#define XCM_REG_WU_DA_CNT_CMD01 0x201d8
a2fbb9ea 4738#define XCM_REG_WU_DA_CNT_CMD10 0x201dc
a2fbb9ea 4739#define XCM_REG_WU_DA_CNT_CMD11 0x201e0
a2fbb9ea 4740#define XCM_REG_WU_DA_CNT_UPD_VAL00 0x201e4
a2fbb9ea 4741#define XCM_REG_WU_DA_CNT_UPD_VAL01 0x201e8
a2fbb9ea 4742#define XCM_REG_WU_DA_CNT_UPD_VAL10 0x201ec
a2fbb9ea 4743#define XCM_REG_WU_DA_CNT_UPD_VAL11 0x201f0
a2fbb9ea 4744#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4
a2fbb9ea 4745#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01 0x201c8
a2fbb9ea 4746#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10 0x201cc
a2fbb9ea
ET		 4747#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11 0x201d0
4748/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
4749 acknowledge output is deasserted; all other signals are treated as usual;
4750 if 1 - normal activity. */
4751#define XCM_REG_XCM_CFC_IFEN 0x20050
4752/* [RW 14] Interrupt mask register #0 read/write */
4753#define XCM_REG_XCM_INT_MASK 0x202b4
4754/* [R 14] Interrupt register #0 read */
4755#define XCM_REG_XCM_INT_STS 0x202a8
c18487ee
YR		 4756/* [R 30] Parity register #0 read */
4757#define XCM_REG_XCM_PRTY_STS 0x202b8
a2fbb9ea
ET		 4758/* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS
4759 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
4760 Is used to determine the number of the AG context REG-pairs written back;
4761 when the Reg1WbFlg isn't set. */
4762#define XCM_REG_XCM_REG0_SZ 0x200f4
4763/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
4764 disregarded; valid is deasserted; all other signals are treated as usual;
4765 if 1 - normal activity. */
4766#define XCM_REG_XCM_STORM0_IFEN 0x20004
4767/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
4768 disregarded; valid is deasserted; all other signals are treated as usual;
4769 if 1 - normal activity. */
4770#define XCM_REG_XCM_STORM1_IFEN 0x20008
4771/* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
4772 disregarded; acknowledge output is deasserted; all other signals are
4773 treated as usual; if 1 - normal activity. */
4774#define XCM_REG_XCM_TM_IFEN 0x20020
4775/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
4776 disregarded; valid is deasserted; all other signals are treated as usual;
4777 if 1 - normal activity. */
4778#define XCM_REG_XCM_XQM_IFEN 0x2000c
4779/* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
4780#define XCM_REG_XCM_XQM_USE_Q 0x200f0
4781/* [RW 4] The value by which CFC updates the activity counter at QM bypass. */
4782#define XCM_REG_XQM_BYP_ACT_UPD 0x200fc
4783/* [RW 6] QM output initial credit. Max credit available - 32.Write writes
4784 the initial credit value; read returns the current value of the credit
4785 counter. Must be initialized to 32 at start-up. */
4786#define XCM_REG_XQM_INIT_CRD 0x20420
4787/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
4788 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4789 prioritised); 2 stands for weight 2; tc. */
4790#define XCM_REG_XQM_P_WEIGHT 0x200e4
8d9c5f34
EG		 4791/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
4792 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4793 prioritised); 2 stands for weight 2; tc. */
4794#define XCM_REG_XQM_S_WEIGHT 0x200e8
a2fbb9ea
ET		 4795/* [RW 28] The CM header value for QM request (primary). */
4796#define XCM_REG_XQM_XCM_HDR_P 0x200a0
4797/* [RW 28] The CM header value for QM request (secondary). */
4798#define XCM_REG_XQM_XCM_HDR_S 0x200a4
4799/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
4800 acknowledge output is deasserted; all other signals are treated as usual;
4801 if 1 - normal activity. */
4802#define XCM_REG_XQM_XCM_IFEN 0x20014
4803/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
4804 acknowledge output is deasserted; all other signals are treated as usual;
4805 if 1 - normal activity. */
4806#define XCM_REG_XSDM_IFEN 0x20018
4807/* [RC 1] Set at message length mismatch (relative to last indication) at
4808 the SDM interface. */
4809#define XCM_REG_XSDM_LENGTH_MIS 0x20220
4810/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
4811 weight 8 (the most prioritised); 1 stands for weight 1(least
4812 prioritised); 2 stands for weight 2; tc. */
4813#define XCM_REG_XSDM_WEIGHT 0x200e0
4814/* [RW 17] Indirect access to the descriptor table of the XX protection
4815 mechanism. The fields are: [5:0] - message length; 11:6] - message
4816 pointer; 16:12] - next pointer. */
4817#define XCM_REG_XX_DESCR_TABLE 0x20480
c18487ee 4818#define XCM_REG_XX_DESCR_TABLE_SIZE 32
a2fbb9ea
ET		 4819/* [R 6] Used to read the XX protection Free counter. */
4820#define XCM_REG_XX_FREE 0x20240
4821/* [RW 6] Initial value for the credit counter; responsible for fulfilling
4822 of the Input Stage XX protection buffer by the XX protection pending
4823 messages. Max credit available - 3.Write writes the initial credit value;
4824 read returns the current value of the credit counter. Must be initialized
4825 to 2 at start-up. */
4826#define XCM_REG_XX_INIT_CRD 0x20424
4827/* [RW 6] The maximum number of pending messages; which may be stored in XX
4828 protection. ~xcm_registers_xx_free.xx_free read on read. */
4829#define XCM_REG_XX_MSG_NUM 0x20428
4830/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
4831#define XCM_REG_XX_OVFL_EVNT_ID 0x20058
c18487ee 4832/* [RW 16] Indirect access to the XX table of the XX protection mechanism.
a2fbb9ea
ET		 4833 The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] -
4834 header pointer. */
4835#define XCM_REG_XX_TABLE 0x20500
4836/* [RW 8] The event id for aggregated interrupt 0 */
4837#define XSDM_REG_AGG_INT_EVENT_0 0x166038
4838#define XSDM_REG_AGG_INT_EVENT_1 0x16603c
4839#define XSDM_REG_AGG_INT_EVENT_10 0x166060
4840#define XSDM_REG_AGG_INT_EVENT_11 0x166064
4841#define XSDM_REG_AGG_INT_EVENT_12 0x166068
4842#define XSDM_REG_AGG_INT_EVENT_13 0x16606c
4843#define XSDM_REG_AGG_INT_EVENT_14 0x166070
4844#define XSDM_REG_AGG_INT_EVENT_15 0x166074
4845#define XSDM_REG_AGG_INT_EVENT_16 0x166078
4846#define XSDM_REG_AGG_INT_EVENT_17 0x16607c
4847#define XSDM_REG_AGG_INT_EVENT_18 0x166080
4848#define XSDM_REG_AGG_INT_EVENT_19 0x166084
c18487ee
YR		 4849#define XSDM_REG_AGG_INT_EVENT_10 0x166060
4850#define XSDM_REG_AGG_INT_EVENT_11 0x166064
4851#define XSDM_REG_AGG_INT_EVENT_12 0x166068
8d9c5f34
EG		 4852#define XSDM_REG_AGG_INT_EVENT_13 0x16606c
4853#define XSDM_REG_AGG_INT_EVENT_14 0x166070
a2fbb9ea
ET		 4854#define XSDM_REG_AGG_INT_EVENT_2 0x166040
4855#define XSDM_REG_AGG_INT_EVENT_20 0x166088
4856#define XSDM_REG_AGG_INT_EVENT_21 0x16608c
4857#define XSDM_REG_AGG_INT_EVENT_22 0x166090
4858#define XSDM_REG_AGG_INT_EVENT_23 0x166094
4859#define XSDM_REG_AGG_INT_EVENT_24 0x166098
4860#define XSDM_REG_AGG_INT_EVENT_25 0x16609c
4861#define XSDM_REG_AGG_INT_EVENT_26 0x1660a0
4862#define XSDM_REG_AGG_INT_EVENT_27 0x1660a4
4863#define XSDM_REG_AGG_INT_EVENT_28 0x1660a8
4864#define XSDM_REG_AGG_INT_EVENT_29 0x1660ac
c18487ee
YR		 4865#define XSDM_REG_AGG_INT_EVENT_3 0x166044
4866#define XSDM_REG_AGG_INT_EVENT_30 0x1660b0
4867#define XSDM_REG_AGG_INT_EVENT_31 0x1660b4
4868#define XSDM_REG_AGG_INT_EVENT_4 0x166048
4869#define XSDM_REG_AGG_INT_EVENT_5 0x16604c
4870#define XSDM_REG_AGG_INT_EVENT_6 0x166050
4871#define XSDM_REG_AGG_INT_EVENT_7 0x166054
4872#define XSDM_REG_AGG_INT_EVENT_8 0x166058
4873#define XSDM_REG_AGG_INT_EVENT_9 0x16605c
a2fbb9ea
ET		 4874/* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
4875 or auto-mask-mode (1) */
4876#define XSDM_REG_AGG_INT_MODE_0 0x1661b8
4877#define XSDM_REG_AGG_INT_MODE_1 0x1661bc
4878#define XSDM_REG_AGG_INT_MODE_10 0x1661e0
4879#define XSDM_REG_AGG_INT_MODE_11 0x1661e4
4880#define XSDM_REG_AGG_INT_MODE_12 0x1661e8
4881#define XSDM_REG_AGG_INT_MODE_13 0x1661ec
4882#define XSDM_REG_AGG_INT_MODE_14 0x1661f0
4883#define XSDM_REG_AGG_INT_MODE_15 0x1661f4
4884#define XSDM_REG_AGG_INT_MODE_16 0x1661f8
4885#define XSDM_REG_AGG_INT_MODE_17 0x1661fc
4886#define XSDM_REG_AGG_INT_MODE_18 0x166200
4887#define XSDM_REG_AGG_INT_MODE_19 0x166204
4888/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
4889#define XSDM_REG_CFC_RSP_START_ADDR 0x166008
4890/* [RW 16] The maximum value of the competion counter #0 */
4891#define XSDM_REG_CMP_COUNTER_MAX0 0x16601c
4892/* [RW 16] The maximum value of the competion counter #1 */
4893#define XSDM_REG_CMP_COUNTER_MAX1 0x166020
4894/* [RW 16] The maximum value of the competion counter #2 */
4895#define XSDM_REG_CMP_COUNTER_MAX2 0x166024
4896/* [RW 16] The maximum value of the competion counter #3 */
4897#define XSDM_REG_CMP_COUNTER_MAX3 0x166028
4898/* [RW 13] The start address in the internal RAM for the completion
4899 counters. */
4900#define XSDM_REG_CMP_COUNTER_START_ADDR 0x16600c
4901#define XSDM_REG_ENABLE_IN1 0x166238
4902#define XSDM_REG_ENABLE_IN2 0x16623c
4903#define XSDM_REG_ENABLE_OUT1 0x166240
4904#define XSDM_REG_ENABLE_OUT2 0x166244
4905/* [RW 4] The initial number of messages that can be sent to the pxp control
4906 interface without receiving any ACK. */
4907#define XSDM_REG_INIT_CREDIT_PXP_CTRL 0x1664bc
4908/* [ST 32] The number of ACK after placement messages received */
4909#define XSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x16627c
4910/* [ST 32] The number of packet end messages received from the parser */
4911#define XSDM_REG_NUM_OF_PKT_END_MSG 0x166274
4912/* [ST 32] The number of requests received from the pxp async if */
4913#define XSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x166278
4914/* [ST 32] The number of commands received in queue 0 */
4915#define XSDM_REG_NUM_OF_Q0_CMD 0x166248
4916/* [ST 32] The number of commands received in queue 10 */
4917#define XSDM_REG_NUM_OF_Q10_CMD 0x16626c
4918/* [ST 32] The number of commands received in queue 11 */
4919#define XSDM_REG_NUM_OF_Q11_CMD 0x166270
4920/* [ST 32] The number of commands received in queue 1 */
4921#define XSDM_REG_NUM_OF_Q1_CMD 0x16624c
4922/* [ST 32] The number of commands received in queue 3 */
4923#define XSDM_REG_NUM_OF_Q3_CMD 0x166250
4924/* [ST 32] The number of commands received in queue 4 */
4925#define XSDM_REG_NUM_OF_Q4_CMD 0x166254
4926/* [ST 32] The number of commands received in queue 5 */
4927#define XSDM_REG_NUM_OF_Q5_CMD 0x166258
4928/* [ST 32] The number of commands received in queue 6 */
4929#define XSDM_REG_NUM_OF_Q6_CMD 0x16625c
4930/* [ST 32] The number of commands received in queue 7 */
4931#define XSDM_REG_NUM_OF_Q7_CMD 0x166260
4932/* [ST 32] The number of commands received in queue 8 */
4933#define XSDM_REG_NUM_OF_Q8_CMD 0x166264
4934/* [ST 32] The number of commands received in queue 9 */
4935#define XSDM_REG_NUM_OF_Q9_CMD 0x166268
4936/* [RW 13] The start address in the internal RAM for queue counters */
4937#define XSDM_REG_Q_COUNTER_START_ADDR 0x166010
4938/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
4939#define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x166548
4940/* [R 1] parser fifo empty in sdm_sync block */
4941#define XSDM_REG_SYNC_PARSER_EMPTY 0x166550
4942/* [R 1] parser serial fifo empty in sdm_sync block */
4943#define XSDM_REG_SYNC_SYNC_EMPTY 0x166558
4944/* [RW 32] Tick for timer counter. Applicable only when
4945 ~xsdm_registers_timer_tick_enable.timer_tick_enable =1 */
4946#define XSDM_REG_TIMER_TICK 0x166000
4947/* [RW 32] Interrupt mask register #0 read/write */
4948#define XSDM_REG_XSDM_INT_MASK_0 0x16629c
4949#define XSDM_REG_XSDM_INT_MASK_1 0x1662ac
c18487ee
YR		 4950/* [R 32] Interrupt register #0 read */
4951#define XSDM_REG_XSDM_INT_STS_0 0x166290
4952#define XSDM_REG_XSDM_INT_STS_1 0x1662a0
a2fbb9ea
ET		 4953/* [RW 11] Parity mask register #0 read/write */
4954#define XSDM_REG_XSDM_PRTY_MASK 0x1662bc
f1410647
ET		 4955/* [R 11] Parity register #0 read */
4956#define XSDM_REG_XSDM_PRTY_STS 0x1662b0
a2fbb9ea
ET		 4957/* [RW 5] The number of time_slots in the arbitration cycle */
4958#define XSEM_REG_ARB_CYCLE_SIZE 0x280034
4959/* [RW 3] The source that is associated with arbitration element 0. Source
4960 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4961 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
4962#define XSEM_REG_ARB_ELEMENT0 0x280020
4963/* [RW 3] The source that is associated with arbitration element 1. Source
4964 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4965 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4966 Could not be equal to register ~xsem_registers_arb_element0.arb_element0 */
4967#define XSEM_REG_ARB_ELEMENT1 0x280024
4968/* [RW 3] The source that is associated with arbitration element 2. Source
4969 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4970 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4971 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
4972 and ~xsem_registers_arb_element1.arb_element1 */
4973#define XSEM_REG_ARB_ELEMENT2 0x280028
4974/* [RW 3] The source that is associated with arbitration element 3. Source
4975 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4976 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
4977 not be equal to register ~xsem_registers_arb_element0.arb_element0 and
4978 ~xsem_registers_arb_element1.arb_element1 and
4979 ~xsem_registers_arb_element2.arb_element2 */
4980#define XSEM_REG_ARB_ELEMENT3 0x28002c
4981/* [RW 3] The source that is associated with arbitration element 4. Source
4982 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4983 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4984 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
4985 and ~xsem_registers_arb_element1.arb_element1 and
4986 ~xsem_registers_arb_element2.arb_element2 and
4987 ~xsem_registers_arb_element3.arb_element3 */
4988#define XSEM_REG_ARB_ELEMENT4 0x280030
4989#define XSEM_REG_ENABLE_IN 0x2800a4
4990#define XSEM_REG_ENABLE_OUT 0x2800a8
4991/* [RW 32] This address space contains all registers and memories that are
4992 placed in SEM_FAST block. The SEM_FAST registers are described in
c18487ee
YR		 4993 appendix B. In order to access the sem_fast registers the base address
4994 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
a2fbb9ea
ET		 4995#define XSEM_REG_FAST_MEMORY 0x2a0000
4996/* [RW 1] Disables input messages from FIC0 May be updated during run_time
4997 by the microcode */
4998#define XSEM_REG_FIC0_DISABLE 0x280224
4999/* [RW 1] Disables input messages from FIC1 May be updated during run_time
5000 by the microcode */
5001#define XSEM_REG_FIC1_DISABLE 0x280234
5002/* [RW 15] Interrupt table Read and write access to it is not possible in
5003 the middle of the work */
5004#define XSEM_REG_INT_TABLE 0x280400
5005/* [ST 24] Statistics register. The number of messages that entered through
5006 FIC0 */
5007#define XSEM_REG_MSG_NUM_FIC0 0x280000
5008/* [ST 24] Statistics register. The number of messages that entered through
5009 FIC1 */
5010#define XSEM_REG_MSG_NUM_FIC1 0x280004
5011/* [ST 24] Statistics register. The number of messages that were sent to
5012 FOC0 */
5013#define XSEM_REG_MSG_NUM_FOC0 0x280008
5014/* [ST 24] Statistics register. The number of messages that were sent to
5015 FOC1 */
5016#define XSEM_REG_MSG_NUM_FOC1 0x28000c
5017/* [ST 24] Statistics register. The number of messages that were sent to
5018 FOC2 */
5019#define XSEM_REG_MSG_NUM_FOC2 0x280010
5020/* [ST 24] Statistics register. The number of messages that were sent to
5021 FOC3 */
5022#define XSEM_REG_MSG_NUM_FOC3 0x280014
5023/* [RW 1] Disables input messages from the passive buffer May be updated
5024 during run_time by the microcode */
5025#define XSEM_REG_PAS_DISABLE 0x28024c
5026/* [WB 128] Debug only. Passive buffer memory */
5027#define XSEM_REG_PASSIVE_BUFFER 0x282000
5028/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
5029#define XSEM_REG_PRAM 0x2c0000
5030/* [R 16] Valid sleeping threads indication have bit per thread */
5031#define XSEM_REG_SLEEP_THREADS_VALID 0x28026c
5032/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
5033#define XSEM_REG_SLOW_EXT_STORE_EMPTY 0x2802a0
5034/* [RW 16] List of free threads . There is a bit per thread. */
5035#define XSEM_REG_THREADS_LIST 0x2802e4
5036/* [RW 3] The arbitration scheme of time_slot 0 */
5037#define XSEM_REG_TS_0_AS 0x280038
5038/* [RW 3] The arbitration scheme of time_slot 10 */
5039#define XSEM_REG_TS_10_AS 0x280060
5040/* [RW 3] The arbitration scheme of time_slot 11 */
5041#define XSEM_REG_TS_11_AS 0x280064
5042/* [RW 3] The arbitration scheme of time_slot 12 */
5043#define XSEM_REG_TS_12_AS 0x280068
5044/* [RW 3] The arbitration scheme of time_slot 13 */
5045#define XSEM_REG_TS_13_AS 0x28006c
5046/* [RW 3] The arbitration scheme of time_slot 14 */
5047#define XSEM_REG_TS_14_AS 0x280070
5048/* [RW 3] The arbitration scheme of time_slot 15 */
5049#define XSEM_REG_TS_15_AS 0x280074
5050/* [RW 3] The arbitration scheme of time_slot 16 */
5051#define XSEM_REG_TS_16_AS 0x280078
5052/* [RW 3] The arbitration scheme of time_slot 17 */
5053#define XSEM_REG_TS_17_AS 0x28007c
5054/* [RW 3] The arbitration scheme of time_slot 18 */
5055#define XSEM_REG_TS_18_AS 0x280080
5056/* [RW 3] The arbitration scheme of time_slot 1 */
5057#define XSEM_REG_TS_1_AS 0x28003c
5058/* [RW 3] The arbitration scheme of time_slot 2 */
5059#define XSEM_REG_TS_2_AS 0x280040
5060/* [RW 3] The arbitration scheme of time_slot 3 */
5061#define XSEM_REG_TS_3_AS 0x280044
5062/* [RW 3] The arbitration scheme of time_slot 4 */
5063#define XSEM_REG_TS_4_AS 0x280048
5064/* [RW 3] The arbitration scheme of time_slot 5 */
5065#define XSEM_REG_TS_5_AS 0x28004c
5066/* [RW 3] The arbitration scheme of time_slot 6 */
5067#define XSEM_REG_TS_6_AS 0x280050
5068/* [RW 3] The arbitration scheme of time_slot 7 */
5069#define XSEM_REG_TS_7_AS 0x280054
5070/* [RW 3] The arbitration scheme of time_slot 8 */
5071#define XSEM_REG_TS_8_AS 0x280058
5072/* [RW 3] The arbitration scheme of time_slot 9 */
5073#define XSEM_REG_TS_9_AS 0x28005c
5074/* [RW 32] Interrupt mask register #0 read/write */
5075#define XSEM_REG_XSEM_INT_MASK_0 0x280110
5076#define XSEM_REG_XSEM_INT_MASK_1 0x280120
c18487ee
YR		 5077/* [R 32] Interrupt register #0 read */
5078#define XSEM_REG_XSEM_INT_STS_0 0x280104
5079#define XSEM_REG_XSEM_INT_STS_1 0x280114
a2fbb9ea
ET		 5080/* [RW 32] Parity mask register #0 read/write */
5081#define XSEM_REG_XSEM_PRTY_MASK_0 0x280130
5082#define XSEM_REG_XSEM_PRTY_MASK_1 0x280140
f1410647
ET		 5083/* [R 32] Parity register #0 read */
5084#define XSEM_REG_XSEM_PRTY_STS_0 0x280124
5085#define XSEM_REG_XSEM_PRTY_STS_1 0x280134
a2fbb9ea
ET		 5086#define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0)
5087#define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
5088#define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
5089#define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0)
5090#define MCPR_NVM_COMMAND_DOIT (1L<<4)
5091#define MCPR_NVM_COMMAND_DONE (1L<<3)
5092#define MCPR_NVM_COMMAND_FIRST (1L<<7)
5093#define MCPR_NVM_COMMAND_LAST (1L<<8)
5094#define MCPR_NVM_COMMAND_WR (1L<<5)
5095#define MCPR_NVM_COMMAND_WREN (1L<<16)
5096#define MCPR_NVM_COMMAND_WREN_BITSHIFT 16
5097#define MCPR_NVM_COMMAND_WRDI (1L<<17)
5098#define MCPR_NVM_COMMAND_WRDI_BITSHIFT 17
5099#define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9)
5100#define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
5101#define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
5102#define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3)
5103#define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
5104#define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3)
5105#define BIGMAC_REGISTER_RX_CONTROL (0x21<<3)
5106#define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3)
5107#define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3)
5108#define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3)
5109#define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3)
5110#define BIGMAC_REGISTER_TX_CONTROL (0x07<<3)
5111#define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3)
5112#define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3)
5113#define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3)
5114#define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3)
5115#define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3)
c18487ee
YR		 5116#define EMAC_LED_1000MB_OVERRIDE (1L<<1)
5117#define EMAC_LED_100MB_OVERRIDE (1L<<2)
5118#define EMAC_LED_10MB_OVERRIDE (1L<<3)
5119#define EMAC_LED_2500MB_OVERRIDE (1L<<12)
5120#define EMAC_LED_OVERRIDE (1L<<0)
5121#define EMAC_LED_TRAFFIC (1L<<6)
a2fbb9ea 5122#define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
a2fbb9ea 5123#define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
a2fbb9ea
ET		 5124#define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26)
5125#define EMAC_MDIO_COMM_DATA (0xffffL<<0)
5126#define EMAC_MDIO_COMM_START_BUSY (1L<<29)
5127#define EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
5128#define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31)
f1410647
ET		 5129#define EMAC_MDIO_MODE_CLOCK_CNT (0x3fL<<16)
5130#define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16
a2fbb9ea 5131#define EMAC_MODE_25G_MODE (1L<<5)
a2fbb9ea 5132#define EMAC_MODE_HALF_DUPLEX (1L<<1)
a2fbb9ea
ET		 5133#define EMAC_MODE_PORT_GMII (2L<<2)
5134#define EMAC_MODE_PORT_MII (1L<<2)
5135#define EMAC_MODE_PORT_MII_10M (3L<<2)
5136#define EMAC_MODE_RESET (1L<<0)
c18487ee 5137#define EMAC_REG_EMAC_LED 0xc
a2fbb9ea
ET		 5138#define EMAC_REG_EMAC_MAC_MATCH 0x10
5139#define EMAC_REG_EMAC_MDIO_COMM 0xac
5140#define EMAC_REG_EMAC_MDIO_MODE 0xb4
5141#define EMAC_REG_EMAC_MODE 0x0
5142#define EMAC_REG_EMAC_RX_MODE 0xc8
5143#define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c
5144#define EMAC_REG_EMAC_RX_STAT_AC 0x180
5145#define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4
5146#define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23
5147#define EMAC_REG_EMAC_TX_MODE 0xbc
5148#define EMAC_REG_EMAC_TX_STAT_AC 0x280
5149#define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22
5150#define EMAC_RX_MODE_FLOW_EN (1L<<2)
5151#define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
5152#define EMAC_RX_MODE_PROMISCUOUS (1L<<8)
5153#define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
5154#define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
8c99e7b0 5155#define EMAC_TX_MODE_FLOW_EN (1L<<4)
c18487ee 5156#define MISC_REGISTERS_GPIO_0 0
f1410647
ET		 5157#define MISC_REGISTERS_GPIO_1 1
5158#define MISC_REGISTERS_GPIO_2 2
5159#define MISC_REGISTERS_GPIO_3 3
5160#define MISC_REGISTERS_GPIO_CLR_POS 16
5161#define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24)
5162#define MISC_REGISTERS_GPIO_FLOAT_POS 24
c18487ee 5163#define MISC_REGISTERS_GPIO_HIGH 1
f1410647 5164#define MISC_REGISTERS_GPIO_INPUT_HI_Z 2
c18487ee 5165#define MISC_REGISTERS_GPIO_LOW 0
f1410647
ET		 5166#define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1
5167#define MISC_REGISTERS_GPIO_OUTPUT_LOW 0
5168#define MISC_REGISTERS_GPIO_PORT_SHIFT 4
5169#define MISC_REGISTERS_GPIO_SET_POS 8
a2fbb9ea 5170#define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588
da5a662a 5171#define MISC_REGISTERS_RESET_REG_1_RST_NIG (0x1<<7)
a2fbb9ea
ET		 5172#define MISC_REGISTERS_RESET_REG_1_SET 0x584
5173#define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598
5174#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
5175#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14)
5176#define MISC_REGISTERS_RESET_REG_2_SET 0x594
5177#define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8
5178#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1)
5179#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2)
5180#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
5181#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0)
5182#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5)
5183#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6)
5184#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7)
5185#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4)
5186#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8)
5187#define MISC_REGISTERS_RESET_REG_3_SET 0x5a4
f1410647
ET		 5188#define MISC_REGISTERS_SPIO_4 4
5189#define MISC_REGISTERS_SPIO_5 5
5190#define MISC_REGISTERS_SPIO_7 7
5191#define MISC_REGISTERS_SPIO_CLR_POS 16
5192#define MISC_REGISTERS_SPIO_FLOAT (0xffL<<24)
5193#define GRC_MISC_REGISTERS_SPIO_FLOAT7 0x80000000
5194#define GRC_MISC_REGISTERS_SPIO_FLOAT6 0x40000000
5195#define GRC_MISC_REGISTERS_SPIO_FLOAT5 0x20000000
5196#define GRC_MISC_REGISTERS_SPIO_FLOAT4 0x10000000
5197#define MISC_REGISTERS_SPIO_FLOAT_POS 24
5198#define MISC_REGISTERS_SPIO_INPUT_HI_Z 2
5199#define MISC_REGISTERS_SPIO_INT_OLD_SET_POS 16
5200#define MISC_REGISTERS_SPIO_OUTPUT_HIGH 1
5201#define MISC_REGISTERS_SPIO_OUTPUT_LOW 0
5202#define MISC_REGISTERS_SPIO_SET_POS 8
5203#define HW_LOCK_MAX_RESOURCE_VALUE 31
5204#define HW_LOCK_RESOURCE_8072_MDIO 0
5205#define HW_LOCK_RESOURCE_GPIO 1
3fcaf2e5 5206#define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3
f1410647 5207#define HW_LOCK_RESOURCE_SPIO 2
da5a662a 5208#define HW_LOCK_RESOURCE_UNDI 5
a2fbb9ea
ET		 5209#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (1<<18)
5210#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (1<<31)
5211#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (1<<9)
5212#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (1<<8)
5213#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (1<<7)
5214#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (1<<6)
5215#define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (1<<29)
5216#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (1<<28)
5217#define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (1<<1)
5218#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (1<<0)
5219#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (1<<18)
5220#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (1<<11)
5221#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (1<<13)
5222#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (1<<12)
5223#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (1<<12)
5224#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (1<<15)
5225#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (1<<14)
5226#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (1<<20)
5227#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (1<<0)
5228#define AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT (1<<31)
5229#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (1<<3)
5230#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (1<<2)
5231#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (1<<5)
5232#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (1<<4)
5233#define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (1<<3)
5234#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (1<<2)
5235#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (1<<22)
f1410647 5236#define AEU_INPUTS_ATTN_BITS_SPIO5 (1<<15)
a2fbb9ea
ET		 5237#define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (1<<27)
5238#define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (1<<5)
5239#define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (1<<25)
5240#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (1<<24)
5241#define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (1<<29)
5242#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (1<<28)
5243#define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (1<<23)
5244#define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (1<<27)
5245#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (1<<26)
5246#define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (1<<21)
5247#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (1<<20)
5248#define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (1<<25)
5249#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (1<<24)
5250#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (1<<16)
5251#define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (1<<9)
5252#define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (1<<7)
5253#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (1<<6)
5254#define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (1<<11)
5255#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (1<<10)
5256#define RESERVED_GENERAL_ATTENTION_BIT_0 0
5257
c18487ee 5258#define EVEREST_GEN_ATTN_IN_USE_MASK 0x3ffe0
a2fbb9ea
ET		 5259#define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000
5260
5261#define RESERVED_GENERAL_ATTENTION_BIT_6 6
5262#define RESERVED_GENERAL_ATTENTION_BIT_7 7
5263#define RESERVED_GENERAL_ATTENTION_BIT_8 8
5264#define RESERVED_GENERAL_ATTENTION_BIT_9 9
5265#define RESERVED_GENERAL_ATTENTION_BIT_10 10
5266#define RESERVED_GENERAL_ATTENTION_BIT_11 11
5267#define RESERVED_GENERAL_ATTENTION_BIT_12 12
5268#define RESERVED_GENERAL_ATTENTION_BIT_13 13
5269#define RESERVED_GENERAL_ATTENTION_BIT_14 14
5270#define RESERVED_GENERAL_ATTENTION_BIT_15 15
5271#define RESERVED_GENERAL_ATTENTION_BIT_16 16
5272#define RESERVED_GENERAL_ATTENTION_BIT_17 17
5273#define RESERVED_GENERAL_ATTENTION_BIT_18 18
5274#define RESERVED_GENERAL_ATTENTION_BIT_19 19
5275#define RESERVED_GENERAL_ATTENTION_BIT_20 20
5276#define RESERVED_GENERAL_ATTENTION_BIT_21 21
5277
5278/* storm asserts attention bits */
5279#define TSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_7
5280#define USTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_8
5281#define CSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_9
5282#define XSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_10
5283
5284/* mcp error attention bit */
5285#define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11
5286
c18487ee
YR		 5287/*E1H NIG status sync attention mapped to group 4-7*/
5288#define LINK_SYNC_ATTENTION_BIT_FUNC_0 RESERVED_GENERAL_ATTENTION_BIT_12
5289#define LINK_SYNC_ATTENTION_BIT_FUNC_1 RESERVED_GENERAL_ATTENTION_BIT_13
5290#define LINK_SYNC_ATTENTION_BIT_FUNC_2 RESERVED_GENERAL_ATTENTION_BIT_14
5291#define LINK_SYNC_ATTENTION_BIT_FUNC_3 RESERVED_GENERAL_ATTENTION_BIT_15
5292#define LINK_SYNC_ATTENTION_BIT_FUNC_4 RESERVED_GENERAL_ATTENTION_BIT_16
5293#define LINK_SYNC_ATTENTION_BIT_FUNC_5 RESERVED_GENERAL_ATTENTION_BIT_17
5294#define LINK_SYNC_ATTENTION_BIT_FUNC_6 RESERVED_GENERAL_ATTENTION_BIT_18
5295#define LINK_SYNC_ATTENTION_BIT_FUNC_7 RESERVED_GENERAL_ATTENTION_BIT_19
5296
5297
a2fbb9ea
ET		 5298#define LATCHED_ATTN_RBCR 23
5299#define LATCHED_ATTN_RBCT 24
5300#define LATCHED_ATTN_RBCN 25
5301#define LATCHED_ATTN_RBCU 26
5302#define LATCHED_ATTN_RBCP 27
5303#define LATCHED_ATTN_TIMEOUT_GRC 28
5304#define LATCHED_ATTN_RSVD_GRC 29
5305#define LATCHED_ATTN_ROM_PARITY_MCP 30
5306#define LATCHED_ATTN_UM_RX_PARITY_MCP 31
5307#define LATCHED_ATTN_UM_TX_PARITY_MCP 32
5308#define LATCHED_ATTN_SCPAD_PARITY_MCP 33
5309
5310#define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32)
5311#define GENERAL_ATTEN_OFFSET(atten_name) (1 << ((94 + atten_name) % 32))
5312/*
5313 * This file defines GRC base address for every block.
5314 * This file is included by chipsim, asm microcode and cpp microcode.
5315 * These values are used in Design.xml on regBase attribute
5316 * Use the base with the generated offsets of specific registers.
5317 */
5318
5319#define GRCBASE_PXPCS 0x000000
5320#define GRCBASE_PCICONFIG 0x002000
5321#define GRCBASE_PCIREG 0x002400
5322#define GRCBASE_EMAC0 0x008000
5323#define GRCBASE_EMAC1 0x008400
5324#define GRCBASE_DBU 0x008800
5325#define GRCBASE_MISC 0x00A000
5326#define GRCBASE_DBG 0x00C000
5327#define GRCBASE_NIG 0x010000
5328#define GRCBASE_XCM 0x020000
5329#define GRCBASE_PRS 0x040000
5330#define GRCBASE_SRCH 0x040400
5331#define GRCBASE_TSDM 0x042000
5332#define GRCBASE_TCM 0x050000
5333#define GRCBASE_BRB1 0x060000
5334#define GRCBASE_MCP 0x080000
5335#define GRCBASE_UPB 0x0C1000
5336#define GRCBASE_CSDM 0x0C2000
5337#define GRCBASE_USDM 0x0C4000
5338#define GRCBASE_CCM 0x0D0000
5339#define GRCBASE_UCM 0x0E0000
5340#define GRCBASE_CDU 0x101000
5341#define GRCBASE_DMAE 0x102000
5342#define GRCBASE_PXP 0x103000
5343#define GRCBASE_CFC 0x104000
5344#define GRCBASE_HC 0x108000
5345#define GRCBASE_PXP2 0x120000
5346#define GRCBASE_PBF 0x140000
5347#define GRCBASE_XPB 0x161000
5348#define GRCBASE_TIMERS 0x164000
5349#define GRCBASE_XSDM 0x166000
5350#define GRCBASE_QM 0x168000
5351#define GRCBASE_DQ 0x170000
5352#define GRCBASE_TSEM 0x180000
5353#define GRCBASE_CSEM 0x200000
5354#define GRCBASE_XSEM 0x280000
5355#define GRCBASE_USEM 0x300000
5356#define GRCBASE_MISC_AEU GRCBASE_MISC
5357
5358
5c862848 5359/* offset of configuration space in the pci core register */
a2fbb9ea
ET		 5360#define PCICFG_OFFSET 0x2000
5361#define PCICFG_VENDOR_ID_OFFSET 0x00
5362#define PCICFG_DEVICE_ID_OFFSET 0x02
c18487ee 5363#define PCICFG_COMMAND_OFFSET 0x04
5c862848
EG		 5364#define PCICFG_COMMAND_IO_SPACE (1<<0)
5365#define PCICFG_COMMAND_MEM_SPACE (1<<1)
5366#define PCICFG_COMMAND_BUS_MASTER (1<<2)
5367#define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3)
5368#define PCICFG_COMMAND_MWI_CYCLES (1<<4)
5369#define PCICFG_COMMAND_VGA_SNOOP (1<<5)
5370#define PCICFG_COMMAND_PERR_ENA (1<<6)
5371#define PCICFG_COMMAND_STEPPING (1<<7)
5372#define PCICFG_COMMAND_SERR_ENA (1<<8)
5373#define PCICFG_COMMAND_FAST_B2B (1<<9)
5374#define PCICFG_COMMAND_INT_DISABLE (1<<10)
5375#define PCICFG_COMMAND_RESERVED (0x1f<<11)
c18487ee 5376#define PCICFG_STATUS_OFFSET 0x06
5c862848 5377#define PCICFG_REVESION_ID 0x08
a2fbb9ea
ET		 5378#define PCICFG_CACHE_LINE_SIZE 0x0c
5379#define PCICFG_LATENCY_TIMER 0x0d
5c862848
EG		 5380#define PCICFG_BAR_1_LOW 0x10
5381#define PCICFG_BAR_1_HIGH 0x14
5382#define PCICFG_BAR_2_LOW 0x18
5383#define PCICFG_BAR_2_HIGH 0x1c
5384#define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c
c18487ee 5385#define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e
5c862848
EG		 5386#define PCICFG_INT_LINE 0x3c
5387#define PCICFG_INT_PIN 0x3d
5388#define PCICFG_PM_CAPABILITY 0x48
5389#define PCICFG_PM_CAPABILITY_VERSION (0x3<<16)
5390#define PCICFG_PM_CAPABILITY_CLOCK (1<<19)
5391#define PCICFG_PM_CAPABILITY_RESERVED (1<<20)
5392#define PCICFG_PM_CAPABILITY_DSI (1<<21)
5393#define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22)
5394#define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25)
5395#define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26)
5396#define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27)
5397#define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28)
5398#define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29)
5399#define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30)
5400#define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31)
5401#define PCICFG_PM_CSR_OFFSET 0x4c
5402#define PCICFG_PM_CSR_STATE (0x3<<0)
5403#define PCICFG_PM_CSR_PME_ENABLE (1<<8)
5404#define PCICFG_PM_CSR_PME_STATUS (1<<15)
8badd27a
EG		 5405#define PCICFG_MSI_CAP_ID 0x58
5406#define PCICFG_MSI_CONTROL_ENABLE (0x1<<16)
5407#define PCICFG_MSI_CONTROL_MCAP (0x7<<17)
5408#define PCICFG_MSI_CONTROL_MENA (0x7<<20)
5409#define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (0x1<<23)
5410#define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24)
5c862848
EG		 5411#define PCICFG_GRC_ADDRESS 0x78
5412#define PCICFG_GRC_DATA 0x80
8badd27a
EG		 5413#define PCICFG_MSIX_CAP_ID 0xa0
5414#define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16)
5415#define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27)
5416#define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30)
5417#define PCICFG_MSIX_CONTROL_MSIX_ENABLE (0x1<<31)
5418
a2fbb9ea 5419#define PCICFG_DEVICE_CONTROL 0xb4
8badd27a
EG		 5420#define PCICFG_DEVICE_STATUS 0xb6
5421#define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0)
5422#define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1)
5423#define PCICFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2)
5424#define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3)
5425#define PCICFG_DEVICE_STATUS_AUX_PWR_DET (1<<4)
5426#define PCICFG_DEVICE_STATUS_NO_PEND (1<<5)
a2fbb9ea
ET		 5427#define PCICFG_LINK_CONTROL 0xbc
5428
c18487ee 5429
a2fbb9ea
ET		 5430#define BAR_USTRORM_INTMEM 0x400000
5431#define BAR_CSTRORM_INTMEM 0x410000
5432#define BAR_XSTRORM_INTMEM 0x420000
5433#define BAR_TSTRORM_INTMEM 0x430000
5434
5c862848 5435/* for accessing the IGU in case of status block ACK */
a2fbb9ea
ET		 5436#define BAR_IGU_INTMEM 0x440000
5437
5438#define BAR_DOORBELL_OFFSET 0x800000
5439
5440#define BAR_ME_REGISTER 0x450000
5441
5c862848
EG		 5442/* config_2 offset */
5443#define GRC_CONFIG_2_SIZE_REG 0x408
5444#define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
a2fbb9ea
ET		 5445#define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
5446#define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
5447#define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
5448#define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
5449#define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
5450#define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
5451#define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
5452#define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
5453#define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
5454#define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
5455#define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
5456#define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
5457#define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
5458#define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
5459#define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
5460#define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
5c862848
EG		 5461#define PCI_CONFIG_2_BAR1_64ENA (1L<<4)
5462#define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
5463#define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
5464#define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
5465#define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
a2fbb9ea
ET		 5466#define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
5467#define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8)
5468#define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8)
5469#define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8)
5470#define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8)
5471#define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8)
5472#define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8)
5473#define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8)
5474#define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8)
5475#define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8)
5476#define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8)
5477#define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8)
5478#define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8)
5479#define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8)
5480#define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8)
5481#define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8)
5c862848
EG		 5482#define PCI_CONFIG_2_BAR_PREFETCH (1L<<16)
5483#define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17)
a2fbb9ea
ET		 5484
5485/* config_3 offset */
5c862848
EG		 5486#define GRC_CONFIG_3_SIZE_REG 0x40c
5487#define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
5488#define PCI_CONFIG_3_FORCE_PME (1L<<24)
5489#define PCI_CONFIG_3_PME_STATUS (1L<<25)
5490#define PCI_CONFIG_3_PME_ENABLE (1L<<26)
5491#define PCI_CONFIG_3_PM_STATE (0x3L<<27)
5492#define PCI_CONFIG_3_VAUX_PRESET (1L<<30)
5493#define PCI_CONFIG_3_PCI_POWER (1L<<31)
a2fbb9ea
ET		 5494
5495#define GRC_BAR2_CONFIG 0x4e0
5c862848
EG		 5496#define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0)
5497#define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0)
5498#define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0)
5499#define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0)
5500#define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0)
5501#define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0)
5502#define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0)
5503#define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0)
5504#define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0)
5505#define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0)
5506#define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0)
5507#define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0)
5508#define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0)
5509#define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0)
5510#define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0)
5511#define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0)
5512#define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0)
5513#define PCI_CONFIG_2_BAR2_64ENA (1L<<4)
5514
5515#define PCI_PM_DATA_A 0x410
5516#define PCI_PM_DATA_B 0x414
5517#define PCI_ID_VAL1 0x434
5518#define PCI_ID_VAL2 0x438
a2fbb9ea 5519
a2fbb9ea
ET		 5520
5521#define MDIO_REG_BANK_CL73_IEEEB0 0x0
5522#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
5523#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
5524#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
5525#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
5526
5527#define MDIO_REG_BANK_CL73_IEEEB1 0x10
c18487ee 5528#define MDIO_CL73_IEEEB1_AN_ADV2 0x01
a2fbb9ea
ET		 5529#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
5530#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
5531#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
5532#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
5533
5534#define MDIO_REG_BANK_RX0 0x80b0
5535#define MDIO_RX0_RX_EQ_BOOST 0x1c
5536#define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5537#define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
5538
5539#define MDIO_REG_BANK_RX1 0x80c0
5540#define MDIO_RX1_RX_EQ_BOOST 0x1c
5541#define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5542#define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
5543
5544#define MDIO_REG_BANK_RX2 0x80d0
5545#define MDIO_RX2_RX_EQ_BOOST 0x1c
5546#define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5547#define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
5548
5549#define MDIO_REG_BANK_RX3 0x80e0
5550#define MDIO_RX3_RX_EQ_BOOST 0x1c
5551#define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5552#define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
5553
5554#define MDIO_REG_BANK_RX_ALL 0x80f0
5555#define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
5556#define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
c18487ee 5557#define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
a2fbb9ea
ET		 5558
5559#define MDIO_REG_BANK_TX0 0x8060
5560#define MDIO_TX0_TX_DRIVER 0x17
5561#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
5562#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
5563#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
5564#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
5565#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
5566#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
5567#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
5568#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
5569#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
5570
5571#define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
5572#define MDIO_BLOCK0_XGXS_CONTROL 0x10
5573
5574#define MDIO_REG_BANK_XGXS_BLOCK1 0x8010
5575#define MDIO_BLOCK1_LANE_CTRL0 0x15
5576#define MDIO_BLOCK1_LANE_CTRL1 0x16
5577#define MDIO_BLOCK1_LANE_CTRL2 0x17
5578#define MDIO_BLOCK1_LANE_PRBS 0x19
5579
5580#define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
5581#define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
5582#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
5583#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
c18487ee 5584#define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
a2fbb9ea 5585#define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
c18487ee 5586#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
f1410647
ET		 5587#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
5588#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
c18487ee 5589#define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
a2fbb9ea
ET		 5590
5591#define MDIO_REG_BANK_GP_STATUS 0x8120
c18487ee
YR		 5592#define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
5593#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
5594#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
5595#define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
5596#define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
5597#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
5598#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
5599#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
5600#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
5601#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
5602#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
5603#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
5604#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
5605#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
5606#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
5607#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
5608#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
5609#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
5610#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
5611#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
5612#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
5613#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
5614#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
5615#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
5616#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
a2fbb9ea
ET		 5617
5618
5619#define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
c18487ee
YR		 5620#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
5621#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
5622#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
5623#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
a2fbb9ea
ET		 5624
5625#define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
c18487ee
YR		 5626#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
5627#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
5628#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
5629#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
5630#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
5631#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
5632#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
5633#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
5634#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
5635#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
5636#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
5637#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
5638#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
5639#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
5640#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
5641#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
5642#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
5643#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
5644#define MDIO_SERDES_DIGITAL_MISC1 0x18
5645#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
5646#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
5647#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
5648#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
5649#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
5650#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
5651#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
5652#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
5653#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
5654#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
5655#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
5656#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
5657#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
5658#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
5659#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
5660#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
5661#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
5662#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
a2fbb9ea
ET		 5663
5664#define MDIO_REG_BANK_OVER_1G 0x8320
c18487ee
YR		 5665#define MDIO_OVER_1G_DIGCTL_3_4 0x14
5666#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
5667#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
5668#define MDIO_OVER_1G_UP1 0x19
5669#define MDIO_OVER_1G_UP1_2_5G 0x0001
5670#define MDIO_OVER_1G_UP1_5G 0x0002
5671#define MDIO_OVER_1G_UP1_6G 0x0004
5672#define MDIO_OVER_1G_UP1_10G 0x0010
5673#define MDIO_OVER_1G_UP1_10GH 0x0008
5674#define MDIO_OVER_1G_UP1_12G 0x0020
5675#define MDIO_OVER_1G_UP1_12_5G 0x0040
5676#define MDIO_OVER_1G_UP1_13G 0x0080
5677#define MDIO_OVER_1G_UP1_15G 0x0100
5678#define MDIO_OVER_1G_UP1_16G 0x0200
5679#define MDIO_OVER_1G_UP2 0x1A
5680#define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
5681#define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
5682#define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
5683#define MDIO_OVER_1G_UP3 0x1B
5684#define MDIO_OVER_1G_UP3_HIGIG2 0x0001
5685#define MDIO_OVER_1G_LP_UP1 0x1C
5686#define MDIO_OVER_1G_LP_UP2 0x1D
5687#define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
5688#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
5689#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
5690#define MDIO_OVER_1G_LP_UP3 0x1E
a2fbb9ea
ET		 5691
5692#define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
c18487ee
YR		 5693#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
5694#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
5695#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
5696
5697#define MDIO_REG_BANK_CL73_USERB0 0x8370
5698#define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
5699#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
5700#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
5701#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
5702#define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
5703#define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
5704
5705#define MDIO_REG_BANK_AER_BLOCK 0xFFD0
5706#define MDIO_AER_BLOCK_AER_REG 0x1E
5707
5708#define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
5709#define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
5710#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
5711#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
5712#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
5713#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
5714#define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
5715#define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
5716#define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
5717#define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
5718#define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
5719#define MDIO_COMBO_IEEE0_MII_STATUS 0x11
5720#define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
5721#define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
5722#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
5723#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
5724#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
5725#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
5726#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
5727#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
5728#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
5729#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
5730#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
5731#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
5732#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
5733#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
5734#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
5735#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000
5736#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180
5737#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
5738#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
5739/*WhenthelinkpartnerisinSGMIImode(bit0=1),then
5740bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge.
5741Theotherbitsarereservedandshouldbezero*/
5742#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
5743
5744
5745#define MDIO_PMA_DEVAD 0x1
5746/*ieee*/
5747#define MDIO_PMA_REG_CTRL 0x0
5748#define MDIO_PMA_REG_STATUS 0x1
5749#define MDIO_PMA_REG_10G_CTRL2 0x7
5750#define MDIO_PMA_REG_RX_SD 0xa
5751/*bcm*/
5752#define MDIO_PMA_REG_BCM_CTRL 0x0096
5753#define MDIO_PMA_REG_FEC_CTRL 0x00ab
5754#define MDIO_PMA_REG_RX_ALARM_CTRL 0x9000
5755#define MDIO_PMA_REG_LASI_CTRL 0x9002
5756#define MDIO_PMA_REG_RX_ALARM 0x9003
5757#define MDIO_PMA_REG_TX_ALARM 0x9004
5758#define MDIO_PMA_REG_LASI_STATUS 0x9005
5759#define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800
5760#define MDIO_PMA_REG_DIGITAL_CTRL 0xc808
5761#define MDIO_PMA_REG_DIGITAL_STATUS 0xc809
5762#define MDIO_PMA_REG_TX_POWER_DOWN 0xca02
5763#define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09
5764#define MDIO_PMA_REG_MISC_CTRL 0xca0a
5765#define MDIO_PMA_REG_GEN_CTRL 0xca10
5766#define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
5767#define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
57963ed9
YR		 5768#define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12
5769#define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13
c18487ee
YR		 5770#define MDIO_PMA_REG_ROM_VER1 0xca19
5771#define MDIO_PMA_REG_ROM_VER2 0xca1a
5772#define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
5773#define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d
5774#define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46
5775#define MDIO_PMA_REG_MISC_CTRL1 0xca85
5776
5777#define MDIO_PMA_REG_7101_RESET 0xc000
5778#define MDIO_PMA_REG_7107_LED_CNTL 0xc007
5779#define MDIO_PMA_REG_7101_VER1 0xc026
5780#define MDIO_PMA_REG_7101_VER2 0xc027
5781
5782
5783#define MDIO_WIS_DEVAD 0x2
5784/*bcm*/
5785#define MDIO_WIS_REG_LASI_CNTL 0x9002
5786#define MDIO_WIS_REG_LASI_STATUS 0x9005
5787
5788#define MDIO_PCS_DEVAD 0x3
5789#define MDIO_PCS_REG_STATUS 0x0020
5790#define MDIO_PCS_REG_LASI_STATUS 0x9005
5791#define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000
5792#define MDIO_PCS_REG_7101_SPI_MUX 0xD008
5793#define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
5794#define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
5795#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
5796#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
5797#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
5798#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
5799#define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
5800
a2fbb9ea 5801
c18487ee
YR		 5802#define MDIO_XS_DEVAD 0x4
5803#define MDIO_XS_PLL_SEQUENCER 0x8000
5804#define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a
a2fbb9ea 5805
c18487ee
YR		 5806#define MDIO_AN_DEVAD 0x7
5807/*ieee*/
5808#define MDIO_AN_REG_CTRL 0x0000
5809#define MDIO_AN_REG_STATUS 0x0001
5810#define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
5811#define MDIO_AN_REG_ADV_PAUSE 0x0010
5812#define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400
5813#define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
5814#define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00
5815#define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00
5816#define MDIO_AN_REG_ADV 0x0011
5817#define MDIO_AN_REG_ADV2 0x0012
5818#define MDIO_AN_REG_LP_AUTO_NEG 0x0013
5819#define MDIO_AN_REG_MASTER_STATUS 0x0021
5820/*bcm*/
5821#define MDIO_AN_REG_LINK_STATUS 0x8304
5822#define MDIO_AN_REG_CL37_CL73 0x8370
5823#define MDIO_AN_REG_CL37_AN 0xffe0
8c99e7b0
YR		 5824#define MDIO_AN_REG_CL37_FC_LD 0xffe4
5825#define MDIO_AN_REG_CL37_FC_LP 0xffe5
a2fbb9ea 5826
a2fbb9ea 5827
c18487ee 5828#define IGU_FUNC_BASE 0x0400
a2fbb9ea 5829
c18487ee
YR		 5830#define IGU_ADDR_MSIX 0x0000
5831#define IGU_ADDR_INT_ACK 0x0200
5832#define IGU_ADDR_PROD_UPD 0x0201
5833#define IGU_ADDR_ATTN_BITS_UPD 0x0202
5834#define IGU_ADDR_ATTN_BITS_SET 0x0203
5835#define IGU_ADDR_ATTN_BITS_CLR 0x0204
5836#define IGU_ADDR_COALESCE_NOW 0x0205
5837#define IGU_ADDR_SIMD_MASK 0x0206
5838#define IGU_ADDR_SIMD_NOMASK 0x0207
5839#define IGU_ADDR_MSI_CTL 0x0210
5840#define IGU_ADDR_MSI_ADDR_LO 0x0211
5841#define IGU_ADDR_MSI_ADDR_HI 0x0212
5842#define IGU_ADDR_MSI_DATA 0x0213
a2fbb9ea 5843
c18487ee
YR		 5844#define IGU_INT_ENABLE 0
5845#define IGU_INT_DISABLE 1
5846#define IGU_INT_NOP 2
5847#define IGU_INT_NOP2 3
f1410647 5848
5c862848
EG		 5849#define COMMAND_REG_INT_ACK 0x0
5850#define COMMAND_REG_PROD_UPD 0x4
5851#define COMMAND_REG_ATTN_BITS_UPD 0x8
5852#define COMMAND_REG_ATTN_BITS_SET 0xc
5853#define COMMAND_REG_ATTN_BITS_CLR 0x10
5854#define COMMAND_REG_COALESCE_NOW 0x14
5855#define COMMAND_REG_SIMD_MASK 0x18
5856#define COMMAND_REG_SIMD_NOMASK 0x1c
5857
a2fbb9ea 5858