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a2fbb9ea ET |
1 | /* bnx2x_fw_defs.h: Broadcom Everest network driver. |
2 | * | |
f1410647 | 3 | * Copyright (c) 2007-2008 Broadcom Corporation |
a2fbb9ea ET |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | */ | |
9 | ||
10 | ||
34f80b04 | 11 | #define CSTORM_ASSERT_LIST_INDEX_OFFSET \ |
6378c025 | 12 | (IS_E1H_OFFSET ? 0x7000 : 0x1000) |
34f80b04 | 13 | #define CSTORM_ASSERT_LIST_OFFSET(idx) \ |
6378c025 | 14 | (IS_E1H_OFFSET ? (0x7020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) |
34f80b04 | 15 | #define CSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ |
6378c025 EG |
16 | (IS_E1H_OFFSET ? (0x8522 + ((function>>1) * 0x40) + \ |
17 | ((function&1) * 0x100) + (index * 0x4)) : (0x1922 + (function * \ | |
18 | 0x40) + (index * 0x4))) | |
34f80b04 | 19 | #define CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \ |
6378c025 EG |
20 | (IS_E1H_OFFSET ? (0x8500 + ((function>>1) * 0x40) + \ |
21 | ((function&1) * 0x100)) : (0x1900 + (function * 0x40))) | |
34f80b04 | 22 | #define CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \ |
6378c025 EG |
23 | (IS_E1H_OFFSET ? (0x8508 + ((function>>1) * 0x40) + \ |
24 | ((function&1) * 0x100)) : (0x1908 + (function * 0x40))) | |
34f80b04 | 25 | #define CSTORM_FUNCTION_MODE_OFFSET \ |
6378c025 | 26 | (IS_E1H_OFFSET ? 0x11e8 : 0xffffffff) |
34f80b04 | 27 | #define CSTORM_HC_BTR_OFFSET(port) \ |
6378c025 | 28 | (IS_E1H_OFFSET ? (0x8704 + (port * 0xf0)) : (0x1984 + (port * 0xc0))) |
34f80b04 | 29 | #define CSTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \ |
6378c025 | 30 | (IS_E1H_OFFSET ? (0x801a + (port * 0x280) + (cpu_id * 0x28) + \ |
34f80b04 EG |
31 | (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \ |
32 | (index * 0x4))) | |
33 | #define CSTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \ | |
6378c025 | 34 | (IS_E1H_OFFSET ? (0x8018 + (port * 0x280) + (cpu_id * 0x28) + \ |
34f80b04 EG |
35 | (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \ |
36 | (index * 0x4))) | |
37 | #define CSTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \ | |
6378c025 | 38 | (IS_E1H_OFFSET ? (0x8000 + (port * 0x280) + (cpu_id * 0x28)) : \ |
34f80b04 EG |
39 | (0x1400 + (port * 0x280) + (cpu_id * 0x28))) |
40 | #define CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \ | |
6378c025 | 41 | (IS_E1H_OFFSET ? (0x8008 + (port * 0x280) + (cpu_id * 0x28)) : \ |
34f80b04 EG |
42 | (0x1408 + (port * 0x280) + (cpu_id * 0x28))) |
43 | #define CSTORM_STATS_FLAGS_OFFSET(function) \ | |
6378c025 | 44 | (IS_E1H_OFFSET ? (0x1108 + (function * 0x8)) : (0x5108 + \ |
34f80b04 EG |
45 | (function * 0x8))) |
46 | #define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(function) \ | |
6378c025 | 47 | (IS_E1H_OFFSET ? (0x31c0 + (function * 0x20)) : 0xffffffff) |
34f80b04 | 48 | #define TSTORM_ASSERT_LIST_INDEX_OFFSET \ |
6378c025 | 49 | (IS_E1H_OFFSET ? 0xa000 : 0x1000) |
34f80b04 | 50 | #define TSTORM_ASSERT_LIST_OFFSET(idx) \ |
6378c025 | 51 | (IS_E1H_OFFSET ? (0xa020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) |
34f80b04 | 52 | #define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) \ |
8d9c5f34 EG |
53 | (IS_E1H_OFFSET ? (0x3350 + (port * 0x190) + (client_id * 0x10)) \ |
54 | : (0x9c0 + (port * 0x130) + (client_id * 0x10))) | |
55 | #define TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET \ | |
56 | (IS_E1H_OFFSET ? 0x1ad8 : 0xffffffff) | |
34f80b04 | 57 | #define TSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ |
6378c025 EG |
58 | (IS_E1H_OFFSET ? (0xb01a + ((function>>1) * 0x28) + \ |
59 | ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \ | |
60 | 0x28) + (index * 0x4))) | |
34f80b04 | 61 | #define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \ |
6378c025 EG |
62 | (IS_E1H_OFFSET ? (0xb000 + ((function>>1) * 0x28) + \ |
63 | ((function&1) * 0xa0)) : (0x1400 + (function * 0x28))) | |
34f80b04 | 64 | #define TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \ |
6378c025 EG |
65 | (IS_E1H_OFFSET ? (0xb008 + ((function>>1) * 0x28) + \ |
66 | ((function&1) * 0xa0)) : (0x1408 + (function * 0x28))) | |
34f80b04 | 67 | #define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \ |
6378c025 | 68 | (IS_E1H_OFFSET ? (0x2b80 + (function * 0x8)) : (0x4b68 + \ |
34f80b04 EG |
69 | (function * 0x8))) |
70 | #define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(function) \ | |
6378c025 | 71 | (IS_E1H_OFFSET ? (0x3000 + (function * 0x38)) : (0x1500 + \ |
34f80b04 EG |
72 | (function * 0x38))) |
73 | #define TSTORM_FUNCTION_MODE_OFFSET \ | |
6378c025 | 74 | (IS_E1H_OFFSET ? 0x1ad0 : 0xffffffff) |
34f80b04 | 75 | #define TSTORM_HC_BTR_OFFSET(port) \ |
6378c025 | 76 | (IS_E1H_OFFSET ? (0xb144 + (port * 0x30)) : (0x1454 + (port * 0x18))) |
34f80b04 | 77 | #define TSTORM_INDIRECTION_TABLE_OFFSET(function) \ |
6378c025 | 78 | (IS_E1H_OFFSET ? (0x12c8 + (function * 0x80)) : (0x22c8 + \ |
34f80b04 EG |
79 | (function * 0x80))) |
80 | #define TSTORM_INDIRECTION_TABLE_SIZE 0x80 | |
81 | #define TSTORM_MAC_FILTER_CONFIG_OFFSET(function) \ | |
6378c025 | 82 | (IS_E1H_OFFSET ? (0x3008 + (function * 0x38)) : (0x1508 + \ |
34f80b04 | 83 | (function * 0x38))) |
66e855f3 YG |
84 | #define TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \ |
85 | (IS_E1H_OFFSET ? (0x2010 + (port * 0x5b0) + (stats_counter_id * \ | |
8d9c5f34 | 86 | 0x50)) : (0x4080 + (port * 0x5b0) + (stats_counter_id * 0x50))) |
34f80b04 | 87 | #define TSTORM_STATS_FLAGS_OFFSET(function) \ |
6378c025 | 88 | (IS_E1H_OFFSET ? (0x2c00 + (function * 0x8)) : (0x4b88 + \ |
34f80b04 | 89 | (function * 0x8))) |
8d9c5f34 | 90 | #define TSTORM_TPA_EXIST_OFFSET (IS_E1H_OFFSET ? 0x3680 : 0x1c20) |
6378c025 EG |
91 | #define USTORM_AGG_DATA_OFFSET (IS_E1H_OFFSET ? 0xa040 : 0x2c10) |
92 | #define USTORM_AGG_DATA_SIZE (IS_E1H_OFFSET ? 0x2440 : 0x1200) | |
34f80b04 | 93 | #define USTORM_ASSERT_LIST_INDEX_OFFSET \ |
8d9c5f34 | 94 | (IS_E1H_OFFSET ? 0x8960 : 0x1000) |
34f80b04 | 95 | #define USTORM_ASSERT_LIST_OFFSET(idx) \ |
8d9c5f34 | 96 | (IS_E1H_OFFSET ? (0x8980 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) |
34f80b04 | 97 | #define USTORM_CQE_PAGE_BASE_OFFSET(port, clientId) \ |
8d9c5f34 EG |
98 | (IS_E1H_OFFSET ? (0x8018 + (port * 0x4b0) + (clientId * 0x30)) : \ |
99 | (0x5330 + (port * 0x260) + (clientId * 0x20))) | |
34f80b04 | 100 | #define USTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ |
8d9c5f34 EG |
101 | (IS_E1H_OFFSET ? (0x9522 + ((function>>1) * 0x40) + \ |
102 | ((function&1) * 0x100) + (index * 0x4)) : (0x1922 + (function * \ | |
103 | 0x40) + (index * 0x4))) | |
34f80b04 | 104 | #define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \ |
8d9c5f34 EG |
105 | (IS_E1H_OFFSET ? (0x9500 + ((function>>1) * 0x40) + \ |
106 | ((function&1) * 0x100)) : (0x1900 + (function * 0x40))) | |
34f80b04 | 107 | #define USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \ |
8d9c5f34 EG |
108 | (IS_E1H_OFFSET ? (0x9508 + ((function>>1) * 0x40) + \ |
109 | ((function&1) * 0x100)) : (0x1908 + (function * 0x40))) | |
1c06328c EG |
110 | #define USTORM_ETH_RING_PAUSE_DATA_OFFSET(port, clientId) \ |
111 | (IS_E1H_OFFSET ? (0x8020 + (port * 0x4b0) + (clientId * 0x30)) : \ | |
112 | 0xffffffff) | |
de832a55 EG |
113 | #define USTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \ |
114 | (IS_E1H_OFFSET ? (0x2a50 + (function * 0x8)) : (0x1d98 + \ | |
115 | (function * 0x8))) | |
34f80b04 | 116 | #define USTORM_FUNCTION_MODE_OFFSET \ |
6378c025 | 117 | (IS_E1H_OFFSET ? 0x2448 : 0xffffffff) |
34f80b04 | 118 | #define USTORM_HC_BTR_OFFSET(port) \ |
8d9c5f34 | 119 | (IS_E1H_OFFSET ? (0x9704 + (port * 0xf0)) : (0x1984 + (port * 0xc0))) |
34f80b04 | 120 | #define USTORM_MAX_AGG_SIZE_OFFSET(port, clientId) \ |
8d9c5f34 EG |
121 | (IS_E1H_OFFSET ? (0x8010 + (port * 0x4b0) + (clientId * 0x30)) : \ |
122 | (0x5328 + (port * 0x260) + (clientId * 0x20))) | |
34f80b04 | 123 | #define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(function) \ |
8d9c5f34 | 124 | (IS_E1H_OFFSET ? (0x2408 + (function * 0x8)) : (0x5308 + \ |
34f80b04 | 125 | (function * 0x8))) |
1c06328c EG |
126 | #define USTORM_PAUSE_ENABLED_OFFSET(port) \ |
127 | (IS_E1H_OFFSET ? (0x2ad4 + (port * 0x8)) : 0xffffffff) | |
de832a55 EG |
128 | #define USTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \ |
129 | (IS_E1H_OFFSET ? (0x2450 + (port * 0x2d0) + (stats_counter_id * \ | |
130 | 0x28)) : (0x4740 + (port * 0x2d0) + (stats_counter_id * 0x28))) | |
8d9c5f34 EG |
131 | #define USTORM_RX_PRODS_OFFSET(port, client_id) \ |
132 | (IS_E1H_OFFSET ? (0x8000 + (port * 0x4b0) + (client_id * 0x30)) \ | |
133 | : (0x5318 + (port * 0x260) + (client_id * 0x20))) | |
34f80b04 | 134 | #define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \ |
6378c025 | 135 | (IS_E1H_OFFSET ? (0x901a + (port * 0x280) + (cpu_id * 0x28) + \ |
34f80b04 EG |
136 | (index * 0x4)) : (0x141a + (port * 0x280) + (cpu_id * 0x28) + \ |
137 | (index * 0x4))) | |
138 | #define USTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \ | |
6378c025 | 139 | (IS_E1H_OFFSET ? (0x9018 + (port * 0x280) + (cpu_id * 0x28) + \ |
34f80b04 EG |
140 | (index * 0x4)) : (0x1418 + (port * 0x280) + (cpu_id * 0x28) + \ |
141 | (index * 0x4))) | |
142 | #define USTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \ | |
6378c025 | 143 | (IS_E1H_OFFSET ? (0x9000 + (port * 0x280) + (cpu_id * 0x28)) : \ |
34f80b04 EG |
144 | (0x1400 + (port * 0x280) + (cpu_id * 0x28))) |
145 | #define USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \ | |
6378c025 | 146 | (IS_E1H_OFFSET ? (0x9008 + (port * 0x280) + (cpu_id * 0x28)) : \ |
34f80b04 | 147 | (0x1408 + (port * 0x280) + (cpu_id * 0x28))) |
de832a55 EG |
148 | #define USTORM_STATS_FLAGS_OFFSET(function) \ |
149 | (IS_E1H_OFFSET ? (0x29f0 + (function * 0x8)) : (0x1d80 + \ | |
150 | (function * 0x8))) | |
34f80b04 | 151 | #define XSTORM_ASSERT_LIST_INDEX_OFFSET \ |
6378c025 | 152 | (IS_E1H_OFFSET ? 0x9000 : 0x1000) |
34f80b04 | 153 | #define XSTORM_ASSERT_LIST_OFFSET(idx) \ |
6378c025 | 154 | (IS_E1H_OFFSET ? (0x9020 + (idx * 0x10)) : (0x1020 + (idx * 0x10))) |
34f80b04 | 155 | #define XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) \ |
8d9c5f34 | 156 | (IS_E1H_OFFSET ? (0x24a8 + (port * 0x50)) : (0x3ba0 + (port * 0x50))) |
34f80b04 | 157 | #define XSTORM_DEF_SB_HC_DISABLE_OFFSET(function, index) \ |
6378c025 EG |
158 | (IS_E1H_OFFSET ? (0xa01a + ((function>>1) * 0x28) + \ |
159 | ((function&1) * 0xa0) + (index * 0x4)) : (0x141a + (function * \ | |
160 | 0x28) + (index * 0x4))) | |
34f80b04 | 161 | #define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(function) \ |
6378c025 EG |
162 | (IS_E1H_OFFSET ? (0xa000 + ((function>>1) * 0x28) + \ |
163 | ((function&1) * 0xa0)) : (0x1400 + (function * 0x28))) | |
34f80b04 | 164 | #define XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(function) \ |
6378c025 EG |
165 | (IS_E1H_OFFSET ? (0xa008 + ((function>>1) * 0x28) + \ |
166 | ((function&1) * 0xa0)) : (0x1408 + (function * 0x28))) | |
34f80b04 | 167 | #define XSTORM_E1HOV_OFFSET(function) \ |
8d9c5f34 | 168 | (IS_E1H_OFFSET ? (0x2c10 + (function * 0x2)) : 0xffffffff) |
34f80b04 | 169 | #define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(function) \ |
6378c025 | 170 | (IS_E1H_OFFSET ? (0x2418 + (function * 0x8)) : (0x3b70 + \ |
34f80b04 EG |
171 | (function * 0x8))) |
172 | #define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(function) \ | |
8d9c5f34 EG |
173 | (IS_E1H_OFFSET ? (0x2588 + (function * 0x90)) : (0x3c80 + \ |
174 | (function * 0x90))) | |
34f80b04 | 175 | #define XSTORM_FUNCTION_MODE_OFFSET \ |
8d9c5f34 | 176 | (IS_E1H_OFFSET ? 0x2c20 : 0xffffffff) |
34f80b04 | 177 | #define XSTORM_HC_BTR_OFFSET(port) \ |
6378c025 | 178 | (IS_E1H_OFFSET ? (0xa144 + (port * 0x30)) : (0x1454 + (port * 0x18))) |
66e855f3 YG |
179 | #define XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stats_counter_id) \ |
180 | (IS_E1H_OFFSET ? (0xc000 + (port * 0x3f0) + (stats_counter_id * \ | |
181 | 0x38)) : (0x3378 + (port * 0x3f0) + (stats_counter_id * 0x38))) | |
34f80b04 | 182 | #define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(function) \ |
8d9c5f34 EG |
183 | (IS_E1H_OFFSET ? (0x2548 + (function * 0x90)) : (0x3c40 + \ |
184 | (function * 0x90))) | |
34f80b04 | 185 | #define XSTORM_SPQ_PAGE_BASE_OFFSET(function) \ |
6378c025 | 186 | (IS_E1H_OFFSET ? (0x2000 + (function * 0x10)) : (0x3328 + \ |
34f80b04 EG |
187 | (function * 0x10))) |
188 | #define XSTORM_SPQ_PROD_OFFSET(function) \ | |
6378c025 | 189 | (IS_E1H_OFFSET ? (0x2008 + (function * 0x10)) : (0x3330 + \ |
34f80b04 EG |
190 | (function * 0x10))) |
191 | #define XSTORM_STATS_FLAGS_OFFSET(function) \ | |
6378c025 | 192 | (IS_E1H_OFFSET ? (0x23d8 + (function * 0x8)) : (0x3b60 + \ |
34f80b04 | 193 | (function * 0x8))) |
a2fbb9ea ET |
194 | #define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0 |
195 | ||
196 | /** | |
f5372251 | 197 | * This file defines HSI constants for the ETH flow |
a2fbb9ea | 198 | */ |
34f80b04 EG |
199 | #ifdef _EVEREST_MICROCODE |
200 | #include "microcode_constants.h" | |
201 | #include "eth_rx_bd.h" | |
202 | #include "eth_tx_bd.h" | |
203 | #include "eth_rx_cqe.h" | |
204 | #include "eth_rx_sge.h" | |
205 | #include "eth_rx_cqe_next_page.h" | |
206 | #endif | |
207 | ||
208 | /* RSS hash types */ | |
209 | #define DEFAULT_HASH_TYPE 0 | |
210 | #define IPV4_HASH_TYPE 1 | |
211 | #define TCP_IPV4_HASH_TYPE 2 | |
212 | #define IPV6_HASH_TYPE 3 | |
213 | #define TCP_IPV6_HASH_TYPE 4 | |
214 | ||
f5372251 EG |
215 | |
216 | /* Ethernet Ring parameters */ | |
34f80b04 EG |
217 | #define X_ETH_LOCAL_RING_SIZE 13 |
218 | #define FIRST_BD_IN_PKT 0 | |
219 | #define PARSE_BD_INDEX 1 | |
356e2385 | 220 | #define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8)) |
34f80b04 EG |
221 | |
222 | ||
223 | /* Rx ring params */ | |
356e2385 EG |
224 | #define U_ETH_LOCAL_BD_RING_SIZE 16 |
225 | #define U_ETH_LOCAL_SGE_RING_SIZE 12 | |
226 | #define U_ETH_SGL_SIZE 8 | |
34f80b04 EG |
227 | |
228 | ||
229 | #define U_ETH_BDS_PER_PAGE_MASK \ | |
230 | ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))-1) | |
231 | #define U_ETH_CQE_PER_PAGE_MASK \ | |
232 | ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))-1) | |
233 | #define U_ETH_SGES_PER_PAGE_MASK \ | |
234 | ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))-1) | |
235 | ||
236 | #define U_ETH_SGES_PER_PAGE_INVERSE_MASK \ | |
237 | (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1)) | |
238 | ||
239 | ||
240 | #define TU_ETH_CQES_PER_PAGE \ | |
241 | (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe_next_page)/8)) | |
242 | #define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8)) | |
243 | #define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8)) | |
244 | ||
245 | #define U_ETH_UNDEFINED_Q 0xFF | |
a2fbb9ea ET |
246 | |
247 | /* values of command IDs in the ramrod message */ | |
356e2385 EG |
248 | #define RAMROD_CMD_ID_ETH_PORT_SETUP 80 |
249 | #define RAMROD_CMD_ID_ETH_CLIENT_SETUP 85 | |
250 | #define RAMROD_CMD_ID_ETH_STAT_QUERY 90 | |
251 | #define RAMROD_CMD_ID_ETH_UPDATE 100 | |
252 | #define RAMROD_CMD_ID_ETH_HALT 105 | |
253 | #define RAMROD_CMD_ID_ETH_SET_MAC 110 | |
254 | #define RAMROD_CMD_ID_ETH_CFC_DEL 115 | |
255 | #define RAMROD_CMD_ID_ETH_PORT_DEL 120 | |
256 | #define RAMROD_CMD_ID_ETH_FORWARD_SETUP 125 | |
a2fbb9ea ET |
257 | |
258 | ||
259 | /* command values for set mac command */ | |
34f80b04 EG |
260 | #define T_ETH_MAC_COMMAND_SET 0 |
261 | #define T_ETH_MAC_COMMAND_INVALIDATE 1 | |
262 | ||
263 | #define T_ETH_INDIRECTION_TABLE_SIZE 128 | |
a2fbb9ea | 264 | |
34f80b04 EG |
265 | /*The CRC32 seed, that is used for the hash(reduction) multicast address */ |
266 | #define T_ETH_CRC32_HASH_SEED 0x00000000 | |
a2fbb9ea ET |
267 | |
268 | /* Maximal L2 clients supported */ | |
34f80b04 EG |
269 | #define ETH_MAX_RX_CLIENTS_E1 19 |
270 | #define ETH_MAX_RX_CLIENTS_E1H 25 | |
271 | ||
272 | /* Maximal aggregation queues supported */ | |
356e2385 EG |
273 | #define ETH_MAX_AGGREGATION_QUEUES_E1 32 |
274 | #define ETH_MAX_AGGREGATION_QUEUES_E1H 64 | |
34f80b04 | 275 | |
555f6c78 EG |
276 | /* ETH RSS modes */ |
277 | #define ETH_RSS_MODE_DISABLED 0 | |
278 | #define ETH_RSS_MODE_REGULAR 1 | |
279 | ||
a2fbb9ea ET |
280 | |
281 | /** | |
f5372251 | 282 | * This file defines HSI constants common to all microcode flows |
a2fbb9ea ET |
283 | */ |
284 | ||
285 | /* Connection types */ | |
34f80b04 EG |
286 | #define ETH_CONNECTION_TYPE 0 |
287 | #define TOE_CONNECTION_TYPE 1 | |
288 | #define RDMA_CONNECTION_TYPE 2 | |
289 | #define ISCSI_CONNECTION_TYPE 3 | |
290 | #define FCOE_CONNECTION_TYPE 4 | |
291 | #define RESERVED_CONNECTION_TYPE_0 5 | |
292 | #define RESERVED_CONNECTION_TYPE_1 6 | |
293 | #define RESERVED_CONNECTION_TYPE_2 7 | |
294 | ||
a2fbb9ea | 295 | |
34f80b04 | 296 | #define PROTOCOL_STATE_BIT_OFFSET 6 |
a2fbb9ea | 297 | |
34f80b04 EG |
298 | #define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) |
299 | #define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) | |
300 | #define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) | |
a2fbb9ea ET |
301 | |
302 | /* microcode fixed page page size 4K (chains and ring segments) */ | |
356e2385 | 303 | #define MC_PAGE_SIZE 4096 |
a2fbb9ea | 304 | |
a2fbb9ea | 305 | |
34f80b04 | 306 | /* Host coalescing constants */ |
a2fbb9ea ET |
307 | |
308 | /* index numbers */ | |
8d9c5f34 | 309 | #define HC_USTORM_DEF_SB_NUM_INDICES 8 |
34f80b04 EG |
310 | #define HC_CSTORM_DEF_SB_NUM_INDICES 8 |
311 | #define HC_XSTORM_DEF_SB_NUM_INDICES 4 | |
312 | #define HC_TSTORM_DEF_SB_NUM_INDICES 4 | |
313 | #define HC_USTORM_SB_NUM_INDICES 4 | |
314 | #define HC_CSTORM_SB_NUM_INDICES 4 | |
a2fbb9ea | 315 | |
f5372251 | 316 | /* index values - which counter to update */ |
a2fbb9ea | 317 | |
34f80b04 EG |
318 | #define HC_INDEX_U_TOE_RX_CQ_CONS 0 |
319 | #define HC_INDEX_U_ETH_RX_CQ_CONS 1 | |
320 | #define HC_INDEX_U_ETH_RX_BD_CONS 2 | |
321 | #define HC_INDEX_U_FCOE_EQ_CONS 3 | |
322 | ||
323 | #define HC_INDEX_C_TOE_TX_CQ_CONS 0 | |
324 | #define HC_INDEX_C_ETH_TX_CQ_CONS 1 | |
325 | #define HC_INDEX_C_ISCSI_EQ_CONS 2 | |
326 | ||
327 | #define HC_INDEX_DEF_X_SPQ_CONS 0 | |
a2fbb9ea | 328 | |
34f80b04 EG |
329 | #define HC_INDEX_DEF_C_RDMA_EQ_CONS 0 |
330 | #define HC_INDEX_DEF_C_RDMA_NAL_PROD 1 | |
331 | #define HC_INDEX_DEF_C_ETH_FW_TX_CQ_CONS 2 | |
332 | #define HC_INDEX_DEF_C_ETH_SLOW_PATH 3 | |
333 | #define HC_INDEX_DEF_C_ETH_RDMA_CQ_CONS 4 | |
334 | #define HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS 5 | |
a2fbb9ea | 335 | |
34f80b04 EG |
336 | #define HC_INDEX_DEF_U_ETH_RDMA_RX_CQ_CONS 0 |
337 | #define HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS 1 | |
338 | #define HC_INDEX_DEF_U_ETH_RDMA_RX_BD_CONS 2 | |
339 | #define HC_INDEX_DEF_U_ETH_ISCSI_RX_BD_CONS 3 | |
a2fbb9ea | 340 | |
a2fbb9ea ET |
341 | |
342 | /* used by the driver to get the SB offset */ | |
34f80b04 EG |
343 | #define USTORM_ID 0 |
344 | #define CSTORM_ID 1 | |
345 | #define XSTORM_ID 2 | |
346 | #define TSTORM_ID 3 | |
347 | #define ATTENTION_ID 4 | |
a2fbb9ea ET |
348 | |
349 | /* max number of slow path commands per port */ | |
356e2385 | 350 | #define MAX_RAMRODS_PER_PORT 8 |
a2fbb9ea ET |
351 | |
352 | /* values for RX ETH CQE type field */ | |
356e2385 EG |
353 | #define RX_ETH_CQE_TYPE_ETH_FASTPATH 0 |
354 | #define RX_ETH_CQE_TYPE_ETH_RAMROD 1 | |
34f80b04 EG |
355 | |
356 | ||
357 | /**** DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/ | |
356e2385 EG |
358 | #define EMULATION_FREQUENCY_FACTOR 1600 |
359 | #define FPGA_FREQUENCY_FACTOR 100 | |
34f80b04 EG |
360 | |
361 | #define TIMERS_TICK_SIZE_CHIP (1e-3) | |
362 | #define TIMERS_TICK_SIZE_EMUL \ | |
363 | ((TIMERS_TICK_SIZE_CHIP)/((EMULATION_FREQUENCY_FACTOR))) | |
364 | #define TIMERS_TICK_SIZE_FPGA \ | |
365 | ((TIMERS_TICK_SIZE_CHIP)/((FPGA_FREQUENCY_FACTOR))) | |
366 | ||
367 | #define TSEMI_CLK1_RESUL_CHIP (1e-3) | |
368 | #define TSEMI_CLK1_RESUL_EMUL \ | |
369 | ((TSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR)) | |
370 | #define TSEMI_CLK1_RESUL_FPGA \ | |
371 | ((TSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR)) | |
372 | ||
356e2385 EG |
373 | #define USEMI_CLK1_RESUL_CHIP (TIMERS_TICK_SIZE_CHIP) |
374 | #define USEMI_CLK1_RESUL_EMUL (TIMERS_TICK_SIZE_EMUL) | |
375 | #define USEMI_CLK1_RESUL_FPGA (TIMERS_TICK_SIZE_FPGA) | |
34f80b04 EG |
376 | |
377 | #define XSEMI_CLK1_RESUL_CHIP (1e-3) | |
378 | #define XSEMI_CLK1_RESUL_EMUL \ | |
379 | ((XSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR)) | |
380 | #define XSEMI_CLK1_RESUL_FPGA \ | |
381 | ((XSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR)) | |
382 | ||
383 | #define XSEMI_CLK2_RESUL_CHIP (1e-6) | |
384 | #define XSEMI_CLK2_RESUL_EMUL \ | |
385 | ((XSEMI_CLK2_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR)) | |
386 | #define XSEMI_CLK2_RESUL_FPGA \ | |
387 | ((XSEMI_CLK2_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR)) | |
388 | ||
389 | #define SDM_TIMER_TICK_RESUL_CHIP (4*(1e-6)) | |
390 | #define SDM_TIMER_TICK_RESUL_EMUL \ | |
391 | ((SDM_TIMER_TICK_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR)) | |
392 | #define SDM_TIMER_TICK_RESUL_FPGA \ | |
393 | ((SDM_TIMER_TICK_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR)) | |
394 | ||
395 | ||
396 | /**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/ | |
a2fbb9ea ET |
397 | #define XSTORM_IP_ID_ROLL_HALF 0x8000 |
398 | #define XSTORM_IP_ID_ROLL_ALL 0 | |
399 | ||
356e2385 | 400 | #define FW_LOG_LIST_SIZE 50 |
34f80b04 EG |
401 | |
402 | #define NUM_OF_PROTOCOLS 4 | |
8d9c5f34 EG |
403 | #define NUM_OF_SAFC_BITS 16 |
404 | #define MAX_COS_NUMBER 4 | |
34f80b04 EG |
405 | #define MAX_T_STAT_COUNTER_ID 18 |
406 | #define MAX_X_STAT_COUNTER_ID 18 | |
8d9c5f34 EG |
407 | #define MAX_U_STAT_COUNTER_ID 18 |
408 | ||
a2fbb9ea | 409 | |
34f80b04 EG |
410 | #define UNKNOWN_ADDRESS 0 |
411 | #define UNICAST_ADDRESS 1 | |
412 | #define MULTICAST_ADDRESS 2 | |
413 | #define BROADCAST_ADDRESS 3 | |
a2fbb9ea | 414 | |
34f80b04 EG |
415 | #define SINGLE_FUNCTION 0 |
416 | #define MULTI_FUNCTION 1 | |
a2fbb9ea | 417 | |
34f80b04 EG |
418 | #define IP_V4 0 |
419 | #define IP_V6 1 | |
a2fbb9ea | 420 |