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[BNX2X]: Correct Link management
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / bnx2x.h
CommitLineData
a2fbb9ea
ET		 1/* bnx2x.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Eliezer Tamir <eliezert@broadcom.com>
10 * Based on code from Michael Chan's bnx2 driver
11 */
12
13#ifndef BNX2X_H
14#define BNX2X_H
15
16/* error/debug prints */
17
18#define DRV_MODULE_NAME "bnx2x"
19#define PFX DRV_MODULE_NAME ": "
20
21/* for messages that are currently off */
22#define BNX2X_MSG_OFF 0
23#define BNX2X_MSG_MCP 0x10000 /* was: NETIF_MSG_HW */
24#define BNX2X_MSG_STATS 0x20000 /* was: NETIF_MSG_TIMER */
25#define NETIF_MSG_NVM 0x40000 /* was: NETIF_MSG_HW */
26#define NETIF_MSG_DMAE 0x80000 /* was: NETIF_MSG_HW */
f1410647
ET		 27#define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
28#define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */
a2fbb9ea
ET		 29
30#define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
31
32/* regular debug print */
33#define DP(__mask, __fmt, __args...) do { \
34 if (bp->msglevel & (__mask)) \
35 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __FUNCTION__, \
36 __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \
37 } while (0)
38
39/* for errors (never masked) */
40#define BNX2X_ERR(__fmt, __args...) do { \
41 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __FUNCTION__, \
42 __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \
43 } while (0)
44
f1410647
ET		 45/* for logging (never masked) */
46#define BNX2X_LOG(__fmt, __args...) do { \
47 printk(KERN_NOTICE "[%s:%d(%s)]" __fmt, __FUNCTION__, \
48 __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \
49 } while (0)
50
a2fbb9ea
ET		 51/* before we have a dev->name use dev_info() */
52#define BNX2X_DEV_INFO(__fmt, __args...) do { \
53 if (bp->msglevel & NETIF_MSG_PROBE) \
54 dev_info(&bp->pdev->dev, __fmt, ##__args); \
55 } while (0)
56
57
58#ifdef BNX2X_STOP_ON_ERROR
59#define bnx2x_panic() do { \
60 bp->panic = 1; \
61 BNX2X_ERR("driver assert\n"); \
62 bnx2x_disable_int(bp); \
63 bnx2x_panic_dump(bp); \
64 } while (0)
65#else
66#define bnx2x_panic() do { \
67 BNX2X_ERR("driver assert\n"); \
68 bnx2x_panic_dump(bp); \
69 } while (0)
70#endif
71
72
73#define U64_LO(x) (((u64)x) & 0xffffffff)
74#define U64_HI(x) (((u64)x) >> 32)
75#define HILO_U64(hi, lo) (((u64)hi << 32) + lo)
76
77
78#define REG_ADDR(bp, offset) (bp->regview + offset)
79
80#define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
81#define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
82#define REG_RD64(bp, offset) readq(REG_ADDR(bp, offset))
83
84#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
85#define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
86#define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
87#define REG_WR32(bp, offset, val) REG_WR(bp, offset, val)
88
89#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
90#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
91
92#define REG_WR_DMAE(bp, offset, val, len32) \
93 do { \
94 memcpy(bnx2x_sp(bp, wb_data[0]), val, len32 * 4); \
95 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
96 offset, len32); \
97 } while (0)
98
99#define SHMEM_RD(bp, type) \
100 REG_RD(bp, bp->shmem_base + offsetof(struct shmem_region, type))
101#define SHMEM_WR(bp, type, val) \
102 REG_WR(bp, bp->shmem_base + offsetof(struct shmem_region, type), val)
103
104#define NIG_WR(reg, val) REG_WR(bp, reg, val)
105#define EMAC_WR(reg, val) REG_WR(bp, emac_base + reg, val)
106#define BMAC_WR(reg, val) REG_WR(bp, GRCBASE_NIG + bmac_addr + reg, val)
107
108
109#define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++)
110
111#define for_each_nondefault_queue(bp, var) \
112 for (var = 1; var < bp->num_queues; var++)
113#define is_multi(bp) (bp->num_queues > 1)
114
115
116struct regp {
117 u32 lo;
118 u32 hi;
119};
120
121struct bmac_stats {
122 struct regp tx_gtpkt;
123 struct regp tx_gtxpf;
124 struct regp tx_gtfcs;
125 struct regp tx_gtmca;
126 struct regp tx_gtgca;
127 struct regp tx_gtfrg;
128 struct regp tx_gtovr;
129 struct regp tx_gt64;
130 struct regp tx_gt127;
131 struct regp tx_gt255; /* 10 */
132 struct regp tx_gt511;
133 struct regp tx_gt1023;
134 struct regp tx_gt1518;
135 struct regp tx_gt2047;
136 struct regp tx_gt4095;
137 struct regp tx_gt9216;
138 struct regp tx_gt16383;
139 struct regp tx_gtmax;
140 struct regp tx_gtufl;
141 struct regp tx_gterr; /* 20 */
142 struct regp tx_gtbyt;
143
144 struct regp rx_gr64;
145 struct regp rx_gr127;
146 struct regp rx_gr255;
147 struct regp rx_gr511;
148 struct regp rx_gr1023;
149 struct regp rx_gr1518;
150 struct regp rx_gr2047;
151 struct regp rx_gr4095;
152 struct regp rx_gr9216; /* 30 */
153 struct regp rx_gr16383;
154 struct regp rx_grmax;
155 struct regp rx_grpkt;
156 struct regp rx_grfcs;
157 struct regp rx_grmca;
158 struct regp rx_grbca;
159 struct regp rx_grxcf;
160 struct regp rx_grxpf;
161 struct regp rx_grxuo;
162 struct regp rx_grjbr; /* 40 */
163 struct regp rx_grovr;
164 struct regp rx_grflr;
165 struct regp rx_grmeg;
166 struct regp rx_grmeb;
167 struct regp rx_grbyt;
168 struct regp rx_grund;
169 struct regp rx_grfrg;
170 struct regp rx_grerb;
171 struct regp rx_grfre;
172 struct regp rx_gripj; /* 50 */
173};
174
175struct emac_stats {
176 u32 rx_ifhcinoctets ;
177 u32 rx_ifhcinbadoctets ;
178 u32 rx_etherstatsfragments ;
179 u32 rx_ifhcinucastpkts ;
180 u32 rx_ifhcinmulticastpkts ;
181 u32 rx_ifhcinbroadcastpkts ;
182 u32 rx_dot3statsfcserrors ;
183 u32 rx_dot3statsalignmenterrors ;
184 u32 rx_dot3statscarriersenseerrors ;
185 u32 rx_xonpauseframesreceived ; /* 10 */
186 u32 rx_xoffpauseframesreceived ;
187 u32 rx_maccontrolframesreceived ;
188 u32 rx_xoffstateentered ;
189 u32 rx_dot3statsframestoolong ;
190 u32 rx_etherstatsjabbers ;
191 u32 rx_etherstatsundersizepkts ;
192 u32 rx_etherstatspkts64octets ;
193 u32 rx_etherstatspkts65octetsto127octets ;
194 u32 rx_etherstatspkts128octetsto255octets ;
195 u32 rx_etherstatspkts256octetsto511octets ; /* 20 */
196 u32 rx_etherstatspkts512octetsto1023octets ;
197 u32 rx_etherstatspkts1024octetsto1522octets;
198 u32 rx_etherstatspktsover1522octets ;
199
200 u32 rx_falsecarriererrors ;
201
202 u32 tx_ifhcoutoctets ;
203 u32 tx_ifhcoutbadoctets ;
204 u32 tx_etherstatscollisions ;
205 u32 tx_outxonsent ;
206 u32 tx_outxoffsent ;
207 u32 tx_flowcontroldone ; /* 30 */
208 u32 tx_dot3statssinglecollisionframes ;
209 u32 tx_dot3statsmultiplecollisionframes ;
210 u32 tx_dot3statsdeferredtransmissions ;
211 u32 tx_dot3statsexcessivecollisions ;
212 u32 tx_dot3statslatecollisions ;
213 u32 tx_ifhcoutucastpkts ;
214 u32 tx_ifhcoutmulticastpkts ;
215 u32 tx_ifhcoutbroadcastpkts ;
216 u32 tx_etherstatspkts64octets ;
217 u32 tx_etherstatspkts65octetsto127octets ; /* 40 */
218 u32 tx_etherstatspkts128octetsto255octets ;
219 u32 tx_etherstatspkts256octetsto511octets ;
220 u32 tx_etherstatspkts512octetsto1023octets ;
221 u32 tx_etherstatspkts1024octetsto1522octet ;
222 u32 tx_etherstatspktsover1522octets ;
223 u32 tx_dot3statsinternalmactransmiterrors ; /* 46 */
224};
225
226union mac_stats {
227 struct emac_stats emac;
228 struct bmac_stats bmac;
229};
230
231struct nig_stats {
232 u32 brb_discard;
233 u32 brb_packet;
234 u32 brb_truncate;
235 u32 flow_ctrl_discard;
236 u32 flow_ctrl_octets;
237 u32 flow_ctrl_packet;
238 u32 mng_discard;
239 u32 mng_octet_inp;
240 u32 mng_octet_out;
241 u32 mng_packet_inp;
242 u32 mng_packet_out;
243 u32 pbf_octets;
244 u32 pbf_packet;
245 u32 safc_inp;
246 u32 done;
247 u32 pad;
248};
249
250struct bnx2x_eth_stats {
251 u32 pad; /* to make long counters u64 aligned */
252 u32 mac_stx_start;
253 u32 total_bytes_received_hi;
254 u32 total_bytes_received_lo;
255 u32 total_bytes_transmitted_hi;
256 u32 total_bytes_transmitted_lo;
257 u32 total_unicast_packets_received_hi;
258 u32 total_unicast_packets_received_lo;
259 u32 total_multicast_packets_received_hi;
260 u32 total_multicast_packets_received_lo;
261 u32 total_broadcast_packets_received_hi;
262 u32 total_broadcast_packets_received_lo;
263 u32 total_unicast_packets_transmitted_hi;
264 u32 total_unicast_packets_transmitted_lo;
265 u32 total_multicast_packets_transmitted_hi;
266 u32 total_multicast_packets_transmitted_lo;
267 u32 total_broadcast_packets_transmitted_hi;
268 u32 total_broadcast_packets_transmitted_lo;
269 u32 crc_receive_errors;
270 u32 alignment_errors;
271 u32 false_carrier_detections;
272 u32 runt_packets_received;
273 u32 jabber_packets_received;
274 u32 pause_xon_frames_received;
275 u32 pause_xoff_frames_received;
276 u32 pause_xon_frames_transmitted;
277 u32 pause_xoff_frames_transmitted;
278 u32 single_collision_transmit_frames;
279 u32 multiple_collision_transmit_frames;
280 u32 late_collision_frames;
281 u32 excessive_collision_frames;
282 u32 control_frames_received;
283 u32 frames_received_64_bytes;
284 u32 frames_received_65_127_bytes;
285 u32 frames_received_128_255_bytes;
286 u32 frames_received_256_511_bytes;
287 u32 frames_received_512_1023_bytes;
288 u32 frames_received_1024_1522_bytes;
289 u32 frames_received_1523_9022_bytes;
290 u32 frames_transmitted_64_bytes;
291 u32 frames_transmitted_65_127_bytes;
292 u32 frames_transmitted_128_255_bytes;
293 u32 frames_transmitted_256_511_bytes;
294 u32 frames_transmitted_512_1023_bytes;
295 u32 frames_transmitted_1024_1522_bytes;
296 u32 frames_transmitted_1523_9022_bytes;
297 u32 valid_bytes_received_hi;
298 u32 valid_bytes_received_lo;
299 u32 error_runt_packets_received;
300 u32 error_jabber_packets_received;
301 u32 mac_stx_end;
302
303 u32 pad2;
304 u32 stat_IfHCInBadOctets_hi;
305 u32 stat_IfHCInBadOctets_lo;
306 u32 stat_IfHCOutBadOctets_hi;
307 u32 stat_IfHCOutBadOctets_lo;
308 u32 stat_Dot3statsFramesTooLong;
309 u32 stat_Dot3statsInternalMacTransmitErrors;
310 u32 stat_Dot3StatsCarrierSenseErrors;
311 u32 stat_Dot3StatsDeferredTransmissions;
312 u32 stat_FlowControlDone;
313 u32 stat_XoffStateEntered;
314
315 u32 x_total_sent_bytes_hi;
316 u32 x_total_sent_bytes_lo;
317 u32 x_total_sent_pkts;
318
319 u32 t_rcv_unicast_bytes_hi;
320 u32 t_rcv_unicast_bytes_lo;
321 u32 t_rcv_broadcast_bytes_hi;
322 u32 t_rcv_broadcast_bytes_lo;
323 u32 t_rcv_multicast_bytes_hi;
324 u32 t_rcv_multicast_bytes_lo;
325 u32 t_total_rcv_pkt;
326
327 u32 checksum_discard;
328 u32 packets_too_big_discard;
329 u32 no_buff_discard;
330 u32 ttl0_discard;
331 u32 mac_discard;
332 u32 mac_filter_discard;
333 u32 xxoverflow_discard;
334 u32 brb_truncate_discard;
335
336 u32 brb_discard;
337 u32 brb_packet;
338 u32 brb_truncate;
339 u32 flow_ctrl_discard;
340 u32 flow_ctrl_octets;
341 u32 flow_ctrl_packet;
342 u32 mng_discard;
343 u32 mng_octet_inp;
344 u32 mng_octet_out;
345 u32 mng_packet_inp;
346 u32 mng_packet_out;
347 u32 pbf_octets;
348 u32 pbf_packet;
349 u32 safc_inp;
350 u32 driver_xoff;
351 u32 number_of_bugs_found_in_stats_spec; /* just kidding */
352};
353
354#define MAC_STX_NA 0xffffffff
355
356#ifdef BNX2X_MULTI
357#define MAX_CONTEXT 16
358#else
359#define MAX_CONTEXT 1
360#endif
361
362union cdu_context {
363 struct eth_context eth;
364 char pad[1024];
365};
366
367#define MAX_DMAE_C 5
368
369/* DMA memory not used in fastpath */
370struct bnx2x_slowpath {
371 union cdu_context context[MAX_CONTEXT];
372 struct eth_stats_query fw_stats;
373 struct mac_configuration_cmd mac_config;
374 struct mac_configuration_cmd mcast_config;
375
376 /* used by dmae command executer */
377 struct dmae_command dmae[MAX_DMAE_C];
378
379 union mac_stats mac_stats;
380 struct nig_stats nig;
381 struct bnx2x_eth_stats eth_stats;
382
383 u32 wb_comp;
384#define BNX2X_WB_COMP_VAL 0xe0d0d0ae
385 u32 wb_data[4];
386};
387
388#define bnx2x_sp(bp, var) (&bp->slowpath->var)
389#define bnx2x_sp_check(bp, var) ((bp->slowpath) ? (&bp->slowpath->var) : NULL)
390#define bnx2x_sp_mapping(bp, var) \
391 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
392
393
394struct sw_rx_bd {
395 struct sk_buff *skb;
396 DECLARE_PCI_UNMAP_ADDR(mapping)
397};
398
399struct sw_tx_bd {
400 struct sk_buff *skb;
401 u16 first_bd;
402};
403
404struct bnx2x_fastpath {
405
406 struct napi_struct napi;
407
408 struct host_status_block *status_blk;
409 dma_addr_t status_blk_mapping;
410
411 struct eth_tx_db_data *hw_tx_prods;
412 dma_addr_t tx_prods_mapping;
413
414 struct sw_tx_bd *tx_buf_ring;
415
416 struct eth_tx_bd *tx_desc_ring;
417 dma_addr_t tx_desc_mapping;
418
419 struct sw_rx_bd *rx_buf_ring;
420
421 struct eth_rx_bd *rx_desc_ring;
422 dma_addr_t rx_desc_mapping;
423
424 union eth_rx_cqe *rx_comp_ring;
425 dma_addr_t rx_comp_mapping;
426
427 int state;
428#define BNX2X_FP_STATE_CLOSED 0
429#define BNX2X_FP_STATE_IRQ 0x80000
430#define BNX2X_FP_STATE_OPENING 0x90000
431#define BNX2X_FP_STATE_OPEN 0xa0000
432#define BNX2X_FP_STATE_HALTING 0xb0000
433#define BNX2X_FP_STATE_HALTED 0xc0000
434#define BNX2X_FP_STATE_DELETED 0xd0000
435#define BNX2X_FP_STATE_CLOSE_IRQ 0xe0000
436
437 int index;
438
439 u16 tx_pkt_prod;
440 u16 tx_pkt_cons;
441 u16 tx_bd_prod;
442 u16 tx_bd_cons;
443 u16 *tx_cons_sb;
444
445 u16 fp_c_idx;
446 u16 fp_u_idx;
447
448 u16 rx_bd_prod;
449 u16 rx_bd_cons;
450 u16 rx_comp_prod;
451 u16 rx_comp_cons;
452 u16 *rx_cons_sb;
453
454 unsigned long tx_pkt,
455 rx_pkt,
456 rx_calls;
457
458 struct bnx2x *bp; /* parent */
459};
460
461#define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
462
463
464/* attn group wiring */
465#define MAX_DYNAMIC_ATTN_GRPS 8
466
467struct attn_route {
468 u32 sig[4];
469};
470
471struct bnx2x {
472 /* Fields used in the tx and intr/napi performance paths
473 * are grouped together in the beginning of the structure
474 */
475 struct bnx2x_fastpath *fp;
476 void __iomem *regview;
477 void __iomem *doorbells;
478
479 struct net_device *dev;
480 struct pci_dev *pdev;
481
482 atomic_t intr_sem;
483 struct msix_entry msix_table[MAX_CONTEXT+1];
484
485 int tx_ring_size;
486
487#ifdef BCM_VLAN
488 struct vlan_group *vlgrp;
489#endif
490
491 u32 rx_csum;
492 u32 rx_offset;
493 u32 rx_buf_use_size; /* useable size */
494 u32 rx_buf_size; /* with alignment */
495#define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */
496#define ETH_MIN_PACKET_SIZE 60
497#define ETH_MAX_PACKET_SIZE 1500
498#define ETH_MAX_JUMBO_PACKET_SIZE 9600
499
500 struct host_def_status_block *def_status_blk;
501#define DEF_SB_ID 16
502 u16 def_c_idx;
503 u16 def_u_idx;
504 u16 def_t_idx;
505 u16 def_x_idx;
506 u16 def_att_idx;
507 u32 attn_state;
508 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
509 u32 aeu_mask;
510 u32 nig_mask;
511
512 /* slow path ring */
513 struct eth_spe *spq;
514 dma_addr_t spq_mapping;
515 u16 spq_prod_idx;
516 u16 dsb_sp_prod_idx;
517 struct eth_spe *spq_prod_bd;
518 struct eth_spe *spq_last_bd;
519 u16 *dsb_sp_prod;
520 u16 spq_left; /* serialize spq */
521 spinlock_t spq_lock;
522
523 /* Flag for marking that there is either
524 * STAT_QUERY or CFC DELETE ramrod pending
525 */
526 u8 stat_pending;
527
c14423fe 528 /* End of fields used in the performance code paths */
a2fbb9ea
ET		 529
530 int panic;
531 int msglevel;
532
533 u32 flags;
534#define PCIX_FLAG 1
535#define PCI_32BIT_FLAG 2
536#define ONE_TDMA_FLAG 4 /* no longer used */
537#define NO_WOL_FLAG 8
538#define USING_DAC_FLAG 0x10
539#define USING_MSIX_FLAG 0x20
540#define ASF_ENABLE_FLAG 0x40
541
542 int port;
543
544 int pm_cap;
545 int pcie_cap;
546
547 /* Used to synchronize phy accesses */
548 spinlock_t phy_lock;
549
550 struct work_struct reset_task;
551 u16 in_reset_task;
552
553 struct work_struct sp_task;
554
555 struct timer_list timer;
556 int timer_interval;
557 int current_interval;
558
559 u32 shmem_base;
560
561 u32 chip_id;
562/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
563#define CHIP_ID(bp) (((bp)->chip_id) & 0xfffffff0)
564
565#define CHIP_NUM(bp) (((bp)->chip_id) & 0xffff0000)
566#define CHIP_NUM_5710 0x57100000
567
568#define CHIP_REV(bp) (((bp)->chip_id) & 0x0000f000)
569#define CHIP_REV_Ax 0x00000000
570#define CHIP_REV_Bx 0x00001000
571#define CHIP_REV_Cx 0x00002000
572#define CHIP_REV_EMUL 0x0000e000
573#define CHIP_REV_FPGA 0x0000f000
574#define CHIP_REV_IS_SLOW(bp) ((CHIP_REV(bp) == CHIP_REV_EMUL) || \
575 (CHIP_REV(bp) == CHIP_REV_FPGA))
576
577#define CHIP_METAL(bp) (((bp)->chip_id) & 0x00000ff0)
578#define CHIP_BOND_ID(bp) (((bp)->chip_id) & 0x0000000f)
579
580 u16 fw_seq;
581 u16 fw_drv_pulse_wr_seq;
582 u32 fw_mb;
583
584 u32 hw_config;
f1410647
ET		 585 u32 board;
586 u32 serdes_config;
a2fbb9ea
ET		 587 u32 lane_config;
588 u32 ext_phy_config;
589#define XGXS_EXT_PHY_TYPE(bp) (bp->ext_phy_config & \
590 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
591#define SERDES_EXT_PHY_TYPE(bp) (bp->ext_phy_config & \
592 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
593
594 u32 speed_cap_mask;
595 u32 link_config;
596#define SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH
597#define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH
598#define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
599#define SWITCH_CFG_ONE_TIME_DETECT \
600 PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT
601
602 u8 ser_lane;
603 u8 rx_lane_swap;
604 u8 tx_lane_swap;
605
606 u8 link_up;
f1410647 607 u8 phy_link_up;
a2fbb9ea
ET		 608
609 u32 supported;
610/* link settings - missing defines */
611#define SUPPORTED_2500baseT_Full (1 << 15)
a2fbb9ea
ET		 612
613 u32 phy_flags;
614/*#define PHY_SERDES_FLAG 0x1*/
615#define PHY_BMAC_FLAG 0x2
616#define PHY_EMAC_FLAG 0x4
617#define PHY_XGXS_FLAG 0x8
618#define PHY_SGMII_FLAG 0x10
619#define PHY_INT_MODE_MASK_FLAG 0x300
620#define PHY_INT_MODE_AUTO_POLLING_FLAG 0x100
621#define PHY_INT_MODE_LINK_READY_FLAG 0x200
622
623 u32 phy_addr;
624 u32 phy_id;
625
626 u32 autoneg;
627#define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
628#define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
629#define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
630#define AUTONEG_PARALLEL \
631 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
632#define AUTONEG_SGMII_FIBER_AUTODET \
633 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
634#define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
635
636 u32 req_autoneg;
637#define AUTONEG_SPEED 0x1
638#define AUTONEG_FLOW_CTRL 0x2
639
640 u32 req_line_speed;
641/* link settings - missing defines */
642#define SPEED_12000 12000
643#define SPEED_12500 12500
644#define SPEED_13000 13000
645#define SPEED_15000 15000
646#define SPEED_16000 16000
647
648 u32 req_duplex;
649 u32 req_flow_ctrl;
650#define FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO
651#define FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX
652#define FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX
653#define FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH
654#define FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE
655
a2fbb9ea
ET		 656 u32 advertising;
657/* link settings - missing defines */
658#define ADVERTISED_2500baseT_Full (1 << 15)
a2fbb9ea
ET		 659
660 u32 link_status;
661 u32 line_speed;
662 u32 duplex;
663 u32 flow_ctrl;
664
665 u32 bc_ver;
666
667 int flash_size;
668#define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
669#define NVRAM_TIMEOUT_COUNT 30000
670#define NVRAM_PAGE_SIZE 256
671
f1410647
ET		 672 u8 wol;
673
a2fbb9ea
ET		 674 int rx_ring_size;
675
676 u16 tx_quick_cons_trip_int;
677 u16 tx_quick_cons_trip;
678 u16 tx_ticks_int;
679 u16 tx_ticks;
680
681 u16 rx_quick_cons_trip_int;
682 u16 rx_quick_cons_trip;
683 u16 rx_ticks_int;
684 u16 rx_ticks;
685
686 u32 stats_ticks;
687
688 int state;
689#define BNX2X_STATE_CLOSED 0x0
690#define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
691#define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
692#define BNX2X_STATE_OPEN 0x3000
693#define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
694#define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
695#define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
696#define BNX2X_STATE_ERROR 0xF000
697
698 int num_queues;
699
700 u32 rx_mode;
701#define BNX2X_RX_MODE_NONE 0
702#define BNX2X_RX_MODE_NORMAL 1
703#define BNX2X_RX_MODE_ALLMULTI 2
704#define BNX2X_RX_MODE_PROMISC 3
705#define BNX2X_MAX_MULTICAST 64
706#define BNX2X_MAX_EMUL_MULTI 16
707
708 dma_addr_t def_status_blk_mapping;
709
710 struct bnx2x_slowpath *slowpath;
711 dma_addr_t slowpath_mapping;
712
713#ifdef BCM_ISCSI
714 void *t1;
715 dma_addr_t t1_mapping;
716 void *t2;
717 dma_addr_t t2_mapping;
718 void *timers;
719 dma_addr_t timers_mapping;
720 void *qm;
721 dma_addr_t qm_mapping;
722#endif
723
724 char *name;
a2fbb9ea
ET		 725
726 /* used to synchronize stats collecting */
727 int stats_state;
728#define STATS_STATE_DISABLE 0
729#define STATS_STATE_ENABLE 1
730#define STATS_STATE_STOP 2 /* stop stats on next iteration */
731
732 /* used by dmae command loader */
733 struct dmae_command dmae;
734 int executer_idx;
735
736 u32 old_brb_discard;
737 struct bmac_stats old_bmac;
738 struct tstorm_per_client_stats old_tclient;
739 struct z_stream_s *strm;
740 void *gunzip_buf;
741 dma_addr_t gunzip_mapping;
742 int gunzip_outlen;
743#define FW_BUF_SIZE 0x8000
744
745};
746
747
748/* DMAE command defines */
749#define DMAE_CMD_SRC_PCI 0
750#define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC
751
752#define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT)
753#define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT)
754
755#define DMAE_CMD_C_DST_PCI 0
756#define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT)
757
758#define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
759
760#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
761#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
762#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
763#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
764
765#define DMAE_CMD_PORT_0 0
766#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
767
768#define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
769#define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
770
771#define DMAE_LEN32_MAX 0x400
772
773
774/* MC hsi */
775#define RX_COPY_THRESH 92
776#define BCM_PAGE_BITS 12
777#define BCM_PAGE_SIZE (1 << BCM_PAGE_BITS)
778
779#define NUM_TX_RINGS 16
780#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_tx_bd))
781#define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
782#define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
783#define MAX_TX_BD (NUM_TX_BD - 1)
784#define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
785#define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
786 (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
787#define TX_BD(x) ((x) & MAX_TX_BD)
788#define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
789
790/* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
791#define NUM_RX_RINGS 8
792#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
793#define MAX_RX_DESC_CNT (RX_DESC_CNT - 2)
794#define RX_DESC_MASK (RX_DESC_CNT - 1)
795#define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
796#define MAX_RX_BD (NUM_RX_BD - 1)
797#define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
798#define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
799 (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
800#define RX_BD(x) ((x) & MAX_RX_BD)
801
802#define NUM_RCQ_RINGS (NUM_RX_RINGS * 2)
803#define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
804#define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1)
805#define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
806#define MAX_RCQ_BD (NUM_RCQ_BD - 1)
807#define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
808#define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
809 (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
810#define RCQ_BD(x) ((x) & MAX_RCQ_BD)
811
812
813/* used on a CID received from the HW */
814#define SW_CID(x) (le32_to_cpu(x) & \
815 (COMMON_RAMROD_ETH_RX_CQE_CID >> 1))
816#define CQE_CMD(x) (le32_to_cpu(x) >> \
817 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
818
819#define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
820 le32_to_cpu((bd)->addr_lo))
821#define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
822
823
824#define STROM_ASSERT_ARRAY_SIZE 50
825
826
827#define MDIO_INDIRECT_REG_ADDR 0x1f
828#define MDIO_SET_REG_BANK(bp, reg_bank) \
829 bnx2x_mdio22_write(bp, MDIO_INDIRECT_REG_ADDR, reg_bank)
830
831#define MDIO_ACCESS_TIMEOUT 1000
832
833
834/* must be used on a CID before placing it on a HW ring */
835#define HW_CID(bp, x) (x | (bp->port << 23))
836
837#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
838#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
839
840#define ATTN_NIG_FOR_FUNC (1L << 8)
841#define ATTN_SW_TIMER_4_FUNC (1L << 9)
842#define GPIO_2_FUNC (1L << 10)
843#define GPIO_3_FUNC (1L << 11)
844#define GPIO_4_FUNC (1L << 12)
845#define ATTN_GENERAL_ATTN_1 (1L << 13)
846#define ATTN_GENERAL_ATTN_2 (1L << 14)
847#define ATTN_GENERAL_ATTN_3 (1L << 15)
848#define ATTN_GENERAL_ATTN_4 (1L << 13)
849#define ATTN_GENERAL_ATTN_5 (1L << 14)
850#define ATTN_GENERAL_ATTN_6 (1L << 15)
851
852#define ATTN_HARD_WIRED_MASK 0xff00
853#define ATTENTION_ID 4
854
855
856#define BNX2X_BTR 3
857#define MAX_SPQ_PENDING 8
858
859
860#define BNX2X_NUM_STATS 31
861#define BNX2X_NUM_TESTS 2
862
863
864#define DPM_TRIGER_TYPE 0x40
865#define DOORBELL(bp, cid, val) \
866 do { \
867 writel((u32)val, (bp)->doorbells + (BCM_PAGE_SIZE * cid) + \
868 DPM_TRIGER_TYPE); \
869 } while (0)
870
25047950
ET		 871/* PCIE link and speed */
872#define PCICFG_LINK_WIDTH 0x1f00000
873#define PCICFG_LINK_WIDTH_SHIFT 20
874#define PCICFG_LINK_SPEED 0xf0000
875#define PCICFG_LINK_SPEED_SHIFT 16
a2fbb9ea 876
f1410647 877#define BMAC_CONTROL_RX_ENABLE 2
a2fbb9ea
ET		 878/* stuff added to make the code fit 80Col */
879
880#define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG
881#define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG
882#define TPA_TYPE(cqe) (cqe->fast_path_cqe.error_type_flags & \
883 (TPA_TYPE_START | TPA_TYPE_END))
884#define BNX2X_RX_SUM_OK(cqe) \
885 (!(cqe->fast_path_cqe.status_flags & \
886 (ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG | \
887 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)))
888
889#define BNX2X_RX_SUM_FIX(cqe) \
890 ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \
891 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \
892 (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT))
893
894
895#define MDIO_AN_CL73_OR_37_COMPLETE \
896 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
897 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
898
899#define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
900 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
901#define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
902 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
903#define GP_STATUS_SPEED_MASK \
904 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
905#define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
906#define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
907#define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
908#define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
909#define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
910#define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
911#define GP_STATUS_10G_HIG \
912 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
913#define GP_STATUS_10G_CX4 \
914 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
915#define GP_STATUS_12G_HIG \
916 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
917#define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
918#define GP_STATUS_13G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
919#define GP_STATUS_15G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
920#define GP_STATUS_16G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
921#define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
922#define GP_STATUS_10G_KX4 \
923 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
924
925#define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
926#define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
927#define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
928#define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
929#define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
930#define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
931#define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
932#define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
933#define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
934#define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
935#define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
936#define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
937#define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
938#define LINK_12GTFD LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
939#define LINK_12GXFD LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
940#define LINK_12_5GTFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
941#define LINK_12_5GXFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
942#define LINK_13GTFD LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
943#define LINK_13GXFD LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
944#define LINK_15GTFD LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
945#define LINK_15GXFD LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
946#define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
947#define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
948
f1410647 949#define NIG_STATUS_XGXS0_LINK10G \
a2fbb9ea 950 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
f1410647 951#define NIG_STATUS_XGXS0_LINK_STATUS \
a2fbb9ea 952 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
f1410647 953#define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
a2fbb9ea 954 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
f1410647 955#define NIG_STATUS_SERDES0_LINK_STATUS \
a2fbb9ea
ET		 956 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
957#define NIG_MASK_MI_INT \
958 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
959#define NIG_MASK_XGXS0_LINK10G \
960 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
961#define NIG_MASK_XGXS0_LINK_STATUS \
962 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
963#define NIG_MASK_SERDES0_LINK_STATUS \
964 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
965
966#define XGXS_RESET_BITS \
967 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
968 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
969 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
970 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
971 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
972
973#define SERDES_RESET_BITS \
974 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
975 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
976 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
977 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
978
979
980#define BNX2X_MC_ASSERT_BITS \
981 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
982 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
983 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
984 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
985
986#define BNX2X_MCP_ASSERT \
987 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
988
989#define BNX2X_DOORQ_ASSERT \
990 AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT
991
992#define HW_INTERRUT_ASSERT_SET_0 \
993 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
994 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
995 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
996 AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
997#define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
998 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
999 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1000 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1001 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR)
1002#define HW_INTERRUT_ASSERT_SET_1 \
1003 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1004 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1005 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1006 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1007 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1008 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1009 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1010 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1011 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1012 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1013 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1014#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
1015 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1016 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1017 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1018 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1019 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1020 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1021 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1022 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1023 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1024 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR)
1025#define HW_INTERRUT_ASSERT_SET_2 \
1026 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1027 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1028 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1029 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1030 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1031#define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1032 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1033 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1034 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1035 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1036 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1037 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1038
1039
1040#define ETH_RX_ERROR_FALGS (ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG | \
1041 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG | \
1042 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)
1043
1044
1045#define MULTI_FLAGS \
1046 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
1047 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1048 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
1049 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1050 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE)
1051
1052#define MULTI_MASK 0x7f
1053
1054
1055#define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS
1056#define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS
1057#define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH
1058
1059#define BNX2X_RX_SB_INDEX \
1060 &fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX]
1061
1062#define BNX2X_TX_SB_INDEX \
1063 &fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX]
1064
1065#define BNX2X_SP_DSB_INDEX \
1066&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX]
1067
1068
1069#define CAM_IS_INVALID(x) \
1070(x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1071
1072#define CAM_INVALIDATE(x) \
1073x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE
1074
1075
1076/* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */
1077
1078#endif /* bnx2x.h */
kernel source for telekom puls (alcatel/mediatek)