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bnx2x: Add new phy BCM8722
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / bnx2x / bnx2x_link.c
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cd88ccee 1/* Copyright 2008-2011 Broadcom Corporation
ea4e040a
YR		 2 *
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
7 *
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
11 * consent.
12 *
13 * Written by Yaniv Rosner
14 *
15 */
16
7995c64e
JP		 17#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
ea4e040a
YR		 19#include <linux/kernel.h>
20#include <linux/errno.h>
21#include <linux/pci.h>
22#include <linux/netdevice.h>
23#include <linux/delay.h>
24#include <linux/ethtool.h>
25#include <linux/mutex.h>
ea4e040a 26
ea4e040a
YR		 27#include "bnx2x.h"
28
29/********************************************************/
3196a88a 30#define ETH_HLEN 14
cd88ccee
YR		 31/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
32#define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
ea4e040a
YR		 33#define ETH_MIN_PACKET_SIZE 60
34#define ETH_MAX_PACKET_SIZE 1500
35#define ETH_MAX_JUMBO_PACKET_SIZE 9600
36#define MDIO_ACCESS_TIMEOUT 1000
cd88ccee 37#define BMAC_CONTROL_RX_ENABLE 2
ea4e040a
YR		 38
39/***********************************************************/
3196a88a 40/* Shortcut definitions */
ea4e040a
YR		 41/***********************************************************/
42
2f904460
EG		 43#define NIG_LATCH_BC_ENABLE_MI_INT 0
44
45#define NIG_STATUS_EMAC0_MI_INT \
46 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
ea4e040a
YR		 47#define NIG_STATUS_XGXS0_LINK10G \
48 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
49#define NIG_STATUS_XGXS0_LINK_STATUS \
50 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
51#define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
52 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
53#define NIG_STATUS_SERDES0_LINK_STATUS \
54 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
55#define NIG_MASK_MI_INT \
56 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
57#define NIG_MASK_XGXS0_LINK10G \
58 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
59#define NIG_MASK_XGXS0_LINK_STATUS \
60 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
61#define NIG_MASK_SERDES0_LINK_STATUS \
62 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
63
64#define MDIO_AN_CL73_OR_37_COMPLETE \
65 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
66 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
67
68#define XGXS_RESET_BITS \
69 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
70 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
71 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
72 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
73 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
74
75#define SERDES_RESET_BITS \
76 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
77 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
78 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
79 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
80
81#define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
82#define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
cd88ccee 83#define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
3196a88a 84#define AUTONEG_PARALLEL \
ea4e040a 85 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
3196a88a 86#define AUTONEG_SGMII_FIBER_AUTODET \
ea4e040a 87 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
3196a88a 88#define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
ea4e040a
YR		 89
90#define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
91 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
92#define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
93 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
94#define GP_STATUS_SPEED_MASK \
95 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
96#define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
97#define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
98#define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
99#define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
100#define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
101#define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
102#define GP_STATUS_10G_HIG \
103 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
104#define GP_STATUS_10G_CX4 \
105 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
106#define GP_STATUS_12G_HIG \
107 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
108#define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
109#define GP_STATUS_13G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
110#define GP_STATUS_15G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
111#define GP_STATUS_16G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
112#define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
113#define GP_STATUS_10G_KX4 \
114 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
115
cd88ccee
YR		 116#define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
117#define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
ea4e040a 118#define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
cd88ccee 119#define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
ea4e040a
YR		 120#define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
121#define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
122#define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
123#define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
124#define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
125#define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
126#define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
cd88ccee
YR		 127#define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
128#define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
129#define LINK_12GTFD LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
130#define LINK_12GXFD LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
ea4e040a
YR		 131#define LINK_12_5GTFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
132#define LINK_12_5GXFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
cd88ccee
YR		 133#define LINK_13GTFD LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
134#define LINK_13GXFD LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
135#define LINK_15GTFD LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
136#define LINK_15GXFD LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
137#define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
138#define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
ea4e040a
YR		 139
140#define PHY_XGXS_FLAG 0x1
141#define PHY_SGMII_FLAG 0x2
142#define PHY_SERDES_FLAG 0x4
143
589abe3a
EG		 144/* */
145#define SFP_EEPROM_CON_TYPE_ADDR 0x2
cd88ccee 146 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
589abe3a
EG		 147 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
148
4d295db0
EG		 149
150#define SFP_EEPROM_COMP_CODE_ADDR 0x3
151 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
152 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
153 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
154
589abe3a
EG		 155#define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
156 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
cd88ccee 157 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
4d295db0 158
cd88ccee 159#define SFP_EEPROM_OPTIONS_ADDR 0x40
589abe3a 160 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
cd88ccee 161#define SFP_EEPROM_OPTIONS_SIZE 2
589abe3a 162
cd88ccee
YR		 163#define EDC_MODE_LINEAR 0x0022
164#define EDC_MODE_LIMITING 0x0044
165#define EDC_MODE_PASSIVE_DAC 0x0055
4d295db0
EG		 166
167
bcab15c5
VZ		 168#define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
169#define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
ea4e040a
YR		 170/**********************************************************/
171/* INTERFACE */
172/**********************************************************/
e10bc84d 173
cd2be89b 174#define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
e10bc84d 175 bnx2x_cl45_write(_bp, _phy, \
7aa0711f 176 (_phy)->def_md_devad, \
ea4e040a
YR		 177 (_bank + (_addr & 0xf)), \
178 _val)
179
cd2be89b 180#define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
e10bc84d 181 bnx2x_cl45_read(_bp, _phy, \
7aa0711f 182 (_phy)->def_md_devad, \
ea4e040a
YR		 183 (_bank + (_addr & 0xf)), \
184 _val)
185
ea4e040a
YR		 186static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
187{
188 u32 val = REG_RD(bp, reg);
189
190 val |= bits;
191 REG_WR(bp, reg, val);
192 return val;
193}
194
195static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
196{
197 u32 val = REG_RD(bp, reg);
198
199 val &= ~bits;
200 REG_WR(bp, reg, val);
201 return val;
202}
203
bcab15c5
VZ		 204/******************************************************************/
205/* ETS section */
206/******************************************************************/
207void bnx2x_ets_disabled(struct link_params *params)
208{
209 /* ETS disabled configuration*/
210 struct bnx2x *bp = params->bp;
211
212 DP(NETIF_MSG_LINK, "ETS disabled configuration\n");
213
2cf7acf9 214 /*
bcab15c5
VZ		 215 * mapping between entry priority to client number (0,1,2 -debug and
216 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
217 * 3bits client num.
218 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
219 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000
220 */
221
222 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
2cf7acf9 223 /*
bcab15c5
VZ		 224 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
225 * as strict. Bits 0,1,2 - debug and management entries, 3 -
226 * COS0 entry, 4 - COS1 entry.
227 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
228 * bit4 bit3 bit2 bit1 bit0
229 * MCP and debug are strict
230 */
231
232 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
233 /* defines which entries (clients) are subjected to WFQ arbitration */
234 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
2cf7acf9
YR		 235 /*
236 * For strict priority entries defines the number of consecutive
237 * slots for the highest priority.
238 */
bcab15c5 239 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
2cf7acf9 240 /*
bcab15c5
VZ		 241 * mapping between the CREDIT_WEIGHT registers and actual client
242 * numbers
243 */
244 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
245 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
246 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
247
248 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
249 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
250 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
251 /* ETS mode disable */
252 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
2cf7acf9 253 /*
bcab15c5
VZ		 254 * If ETS mode is enabled (there is no strict priority) defines a WFQ
255 * weight for COS0/COS1.
256 */
257 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
258 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
259 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
260 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
261 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
262 /* Defines the number of consecutive slots for the strict priority */
263 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
264}
265
65a001ba 266static void bnx2x_ets_bw_limit_common(const struct link_params *params)
bcab15c5
VZ		 267{
268 /* ETS disabled configuration */
269 struct bnx2x *bp = params->bp;
270 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
2cf7acf9
YR		 271 /*
272 * defines which entries (clients) are subjected to WFQ arbitration
273 * COS0 0x8
274 * COS1 0x10
275 */
bcab15c5 276 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
2cf7acf9
YR		 277 /*
278 * mapping between the ARB_CREDIT_WEIGHT registers and actual
279 * client numbers (WEIGHT_0 does not actually have to represent
280 * client 0)
281 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
282 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010
283 */
bcab15c5
VZ		 284 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
285
286 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
287 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
288 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
289 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
290
291 /* ETS mode enabled*/
292 REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
293
294 /* Defines the number of consecutive slots for the strict priority */
295 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
2cf7acf9
YR		 296 /*
297 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
298 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0
299 * entry, 4 - COS1 entry.
300 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
301 * bit4 bit3 bit2 bit1 bit0
302 * MCP and debug are strict
303 */
bcab15c5
VZ		 304 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
305
306 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
307 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
308 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
309 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
310 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
311}
312
313void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
314 const u32 cos1_bw)
315{
316 /* ETS disabled configuration*/
317 struct bnx2x *bp = params->bp;
318 const u32 total_bw = cos0_bw + cos1_bw;
319 u32 cos0_credit_weight = 0;
320 u32 cos1_credit_weight = 0;
321
322 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
323
324 if ((0 == total_bw) ||
325 (0 == cos0_bw) ||
326 (0 == cos1_bw)) {
cd88ccee 327 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
bcab15c5
VZ		 328 return;
329 }
330
331 cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
332 total_bw;
333 cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
334 total_bw;
335
336 bnx2x_ets_bw_limit_common(params);
337
338 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
339 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
340
341 REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
342 REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
343}
344
345u8 bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
346{
347 /* ETS disabled configuration*/
348 struct bnx2x *bp = params->bp;
349 u32 val = 0;
350
bcab15c5 351 DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
2cf7acf9 352 /*
bcab15c5
VZ		 353 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
354 * as strict. Bits 0,1,2 - debug and management entries,
355 * 3 - COS0 entry, 4 - COS1 entry.
356 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
357 * bit4 bit3 bit2 bit1 bit0
358 * MCP and debug are strict
359 */
360 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
2cf7acf9 361 /*
bcab15c5
VZ		 362 * For strict priority entries defines the number of consecutive slots
363 * for the highest priority.
364 */
365 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
366 /* ETS mode disable */
367 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
368 /* Defines the number of consecutive slots for the strict priority */
369 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
370
371 /* Defines the number of consecutive slots for the strict priority */
372 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
373
2cf7acf9
YR		 374 /*
375 * mapping between entry priority to client number (0,1,2 -debug and
376 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
377 * 3bits client num.
378 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
379 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000
380 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000
381 */
bcab15c5
VZ		 382 val = (0 == strict_cos) ? 0x2318 : 0x22E0;
383 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
384
385 return 0;
386}
387/******************************************************************/
e8920674 388/* PFC section */
bcab15c5
VZ		 389/******************************************************************/
390
391static void bnx2x_bmac2_get_pfc_stat(struct link_params *params,
392 u32 pfc_frames_sent[2],
393 u32 pfc_frames_received[2])
394{
395 /* Read pfc statistic */
396 struct bnx2x *bp = params->bp;
397 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
398 NIG_REG_INGRESS_BMAC0_MEM;
399
400 DP(NETIF_MSG_LINK, "pfc statistic read from BMAC\n");
401
402 REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_STAT_GTPP,
403 pfc_frames_sent, 2);
404
405 REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_STAT_GRPP,
406 pfc_frames_received, 2);
407
408}
409static void bnx2x_emac_get_pfc_stat(struct link_params *params,
410 u32 pfc_frames_sent[2],
411 u32 pfc_frames_received[2])
412{
413 /* Read pfc statistic */
414 struct bnx2x *bp = params->bp;
415 u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
416 u32 val_xon = 0;
417 u32 val_xoff = 0;
418
419 DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
420
421 /* PFC received frames */
422 val_xoff = REG_RD(bp, emac_base +
423 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
424 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
425 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
426 val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
427
428 pfc_frames_received[0] = val_xon + val_xoff;
429
430 /* PFC received sent */
431 val_xoff = REG_RD(bp, emac_base +
432 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
433 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
434 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
435 val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
436
437 pfc_frames_sent[0] = val_xon + val_xoff;
438}
439
440void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
441 u32 pfc_frames_sent[2],
442 u32 pfc_frames_received[2])
443{
444 /* Read pfc statistic */
445 struct bnx2x *bp = params->bp;
446 u32 val = 0;
447 DP(NETIF_MSG_LINK, "pfc statistic\n");
448
449 if (!vars->link_up)
450 return;
451
452 val = REG_RD(bp, MISC_REG_RESET_REG_2);
453 if ((val & (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
454 == 0) {
455 DP(NETIF_MSG_LINK, "About to read stats from EMAC\n");
456 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
457 pfc_frames_received);
458 } else {
459 DP(NETIF_MSG_LINK, "About to read stats from BMAC\n");
460 bnx2x_bmac2_get_pfc_stat(params, pfc_frames_sent,
461 pfc_frames_received);
462 }
463}
464/******************************************************************/
465/* MAC/PBF section */
466/******************************************************************/
ea4e040a 467static void bnx2x_emac_init(struct link_params *params,
cd88ccee 468 struct link_vars *vars)
ea4e040a
YR		 469{
470 /* reset and unreset the emac core */
471 struct bnx2x *bp = params->bp;
472 u8 port = params->port;
473 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
474 u32 val;
475 u16 timeout;
476
477 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
cd88ccee 478 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
ea4e040a
YR		 479 udelay(5);
480 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
cd88ccee 481 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
ea4e040a
YR		 482
483 /* init emac - use read-modify-write */
484 /* self clear reset */
485 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
3196a88a 486 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
ea4e040a
YR		 487
488 timeout = 200;
3196a88a 489 do {
ea4e040a
YR		 490 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
491 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
492 if (!timeout) {
493 DP(NETIF_MSG_LINK, "EMAC timeout!\n");
494 return;
495 }
496 timeout--;
3196a88a 497 } while (val & EMAC_MODE_RESET);
ea4e040a
YR		 498
499 /* Set mac address */
500 val = ((params->mac_addr[0] << 8) |
501 params->mac_addr[1]);
3196a88a 502 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
ea4e040a
YR		 503
504 val = ((params->mac_addr[2] << 24) |
505 (params->mac_addr[3] << 16) |
506 (params->mac_addr[4] << 8) |
507 params->mac_addr[5]);
3196a88a 508 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
ea4e040a
YR		 509}
510
511static u8 bnx2x_emac_enable(struct link_params *params,
cd88ccee 512 struct link_vars *vars, u8 lb)
ea4e040a
YR		 513{
514 struct bnx2x *bp = params->bp;
515 u8 port = params->port;
516 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
517 u32 val;
518
519 DP(NETIF_MSG_LINK, "enabling EMAC\n");
520
521 /* enable emac and not bmac */
522 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
523
ea4e040a
YR		 524 /* ASIC */
525 if (vars->phy_flags & PHY_XGXS_FLAG) {
526 u32 ser_lane = ((params->lane_config &
cd88ccee
YR		 527 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
528 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
ea4e040a
YR		 529
530 DP(NETIF_MSG_LINK, "XGXS\n");
531 /* select the master lanes (out of 0-3) */
cd88ccee 532 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
ea4e040a 533 /* select XGXS */
cd88ccee 534 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
ea4e040a
YR		 535
536 } else { /* SerDes */
537 DP(NETIF_MSG_LINK, "SerDes\n");
538 /* select SerDes */
cd88ccee 539 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
ea4e040a
YR		 540 }
541
811a2f2d 542 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
cd88ccee 543 EMAC_RX_MODE_RESET);
811a2f2d 544 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
cd88ccee 545 EMAC_TX_MODE_RESET);
ea4e040a
YR		 546
547 if (CHIP_REV_IS_SLOW(bp)) {
548 /* config GMII mode */
549 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
cd88ccee 550 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
ea4e040a
YR		 551 } else { /* ASIC */
552 /* pause enable/disable */
553 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
554 EMAC_RX_MODE_FLOW_EN);
ea4e040a
YR		 555
556 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
bcab15c5
VZ		 557 (EMAC_TX_MODE_EXT_PAUSE_EN |
558 EMAC_TX_MODE_FLOW_EN));
559 if (!(params->feature_config_flags &
560 FEATURE_CONFIG_PFC_ENABLED)) {
561 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
562 bnx2x_bits_en(bp, emac_base +
563 EMAC_REG_EMAC_RX_MODE,
564 EMAC_RX_MODE_FLOW_EN);
565
566 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
567 bnx2x_bits_en(bp, emac_base +
568 EMAC_REG_EMAC_TX_MODE,
569 (EMAC_TX_MODE_EXT_PAUSE_EN |
570 EMAC_TX_MODE_FLOW_EN));
571 } else
572 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
573 EMAC_TX_MODE_FLOW_EN);
ea4e040a
YR		 574 }
575
576 /* KEEP_VLAN_TAG, promiscuous */
577 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
578 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
bcab15c5 579
2cf7acf9
YR		 580 /*
581 * Setting this bit causes MAC control frames (except for pause
582 * frames) to be passed on for processing. This setting has no
583 * affect on the operation of the pause frames. This bit effects
584 * all packets regardless of RX Parser packet sorting logic.
585 * Turn the PFC off to make sure we are in Xon state before
586 * enabling it.
587 */
bcab15c5
VZ		 588 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
589 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
590 DP(NETIF_MSG_LINK, "PFC is enabled\n");
591 /* Enable PFC again */
592 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
593 EMAC_REG_RX_PFC_MODE_RX_EN |
594 EMAC_REG_RX_PFC_MODE_TX_EN |
595 EMAC_REG_RX_PFC_MODE_PRIORITIES);
596
597 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
598 ((0x0101 <<
599 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
600 (0x00ff <<
601 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
602 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
603 }
3196a88a 604 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
ea4e040a
YR		 605
606 /* Set Loopback */
607 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
608 if (lb)
609 val |= 0x810;
610 else
611 val &= ~0x810;
3196a88a 612 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
ea4e040a 613
6c55c3cd
EG		 614 /* enable emac */
615 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
616
ea4e040a 617 /* enable emac for jumbo packets */
3196a88a 618 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
ea4e040a
YR		 619 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
620 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
621
622 /* strip CRC */
623 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
624
625 /* disable the NIG in/out to the bmac */
626 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
627 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
628 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
629
630 /* enable the NIG in/out to the emac */
631 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
632 val = 0;
bcab15c5
VZ		 633 if ((params->feature_config_flags &
634 FEATURE_CONFIG_PFC_ENABLED) ||
635 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
ea4e040a
YR		 636 val = 1;
637
638 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
639 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
640
02a23165 641 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
ea4e040a
YR		 642
643 vars->mac_type = MAC_TYPE_EMAC;
644 return 0;
645}
646
bcab15c5
VZ		 647static void bnx2x_update_pfc_bmac1(struct link_params *params,
648 struct link_vars *vars)
649{
650 u32 wb_data[2];
651 struct bnx2x *bp = params->bp;
652 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
653 NIG_REG_INGRESS_BMAC0_MEM;
654
655 u32 val = 0x14;
656 if ((!(params->feature_config_flags &
657 FEATURE_CONFIG_PFC_ENABLED)) &&
658 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
659 /* Enable BigMAC to react on received Pause packets */
660 val |= (1<<5);
661 wb_data[0] = val;
662 wb_data[1] = 0;
663 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
664
665 /* tx control */
666 val = 0xc0;
667 if (!(params->feature_config_flags &
668 FEATURE_CONFIG_PFC_ENABLED) &&
669 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
670 val |= 0x800000;
671 wb_data[0] = val;
672 wb_data[1] = 0;
673 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
674}
675
676static void bnx2x_update_pfc_bmac2(struct link_params *params,
677 struct link_vars *vars,
678 u8 is_lb)
f2e0899f
DK		 679{
680 /*
681 * Set rx control: Strip CRC and enable BigMAC to relay
682 * control packets to the system as well
683 */
684 u32 wb_data[2];
685 struct bnx2x *bp = params->bp;
686 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
687 NIG_REG_INGRESS_BMAC0_MEM;
688 u32 val = 0x14;
ea4e040a 689
bcab15c5
VZ		 690 if ((!(params->feature_config_flags &
691 FEATURE_CONFIG_PFC_ENABLED)) &&
692 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
f2e0899f
DK		 693 /* Enable BigMAC to react on received Pause packets */
694 val |= (1<<5);
695 wb_data[0] = val;
696 wb_data[1] = 0;
cd88ccee 697 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
f2e0899f 698 udelay(30);
ea4e040a 699
f2e0899f
DK		 700 /* Tx control */
701 val = 0xc0;
bcab15c5
VZ		 702 if (!(params->feature_config_flags &
703 FEATURE_CONFIG_PFC_ENABLED) &&
704 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
f2e0899f
DK		 705 val |= 0x800000;
706 wb_data[0] = val;
707 wb_data[1] = 0;
bcab15c5
VZ		 708 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
709
710 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
711 DP(NETIF_MSG_LINK, "PFC is enabled\n");
712 /* Enable PFC RX & TX & STATS and set 8 COS */
713 wb_data[0] = 0x0;
714 wb_data[0] |= (1<<0); /* RX */
715 wb_data[0] |= (1<<1); /* TX */
716 wb_data[0] |= (1<<2); /* Force initial Xon */
717 wb_data[0] |= (1<<3); /* 8 cos */
718 wb_data[0] |= (1<<5); /* STATS */
719 wb_data[1] = 0;
720 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
721 wb_data, 2);
722 /* Clear the force Xon */
723 wb_data[0] &= ~(1<<2);
724 } else {
725 DP(NETIF_MSG_LINK, "PFC is disabled\n");
726 /* disable PFC RX & TX & STATS and set 8 COS */
727 wb_data[0] = 0x8;
728 wb_data[1] = 0;
729 }
730
731 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
f2e0899f 732
2cf7acf9
YR		 733 /*
734 * Set Time (based unit is 512 bit time) between automatic
735 * re-sending of PP packets amd enable automatic re-send of
736 * Per-Priroity Packet as long as pp_gen is asserted and
737 * pp_disable is low.
738 */
f2e0899f 739 val = 0x8000;
bcab15c5
VZ		 740 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
741 val |= (1<<16); /* enable automatic re-send */
742
f2e0899f
DK		 743 wb_data[0] = val;
744 wb_data[1] = 0;
745 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
cd88ccee 746 wb_data, 2);
f2e0899f
DK		 747
748 /* mac control */
749 val = 0x3; /* Enable RX and TX */
750 if (is_lb) {
751 val |= 0x4; /* Local loopback */
752 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
753 }
bcab15c5
VZ		 754 /* When PFC enabled, Pass pause frames towards the NIG. */
755 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
756 val |= ((1<<6)|(1<<5));
f2e0899f
DK		 757
758 wb_data[0] = val;
759 wb_data[1] = 0;
cd88ccee 760 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
f2e0899f
DK		 761}
762
bcab15c5
VZ		 763static void bnx2x_update_pfc_brb(struct link_params *params,
764 struct link_vars *vars,
765 struct bnx2x_nig_brb_pfc_port_params *pfc_params)
766{
767 struct bnx2x *bp = params->bp;
768 int set_pfc = params->feature_config_flags &
769 FEATURE_CONFIG_PFC_ENABLED;
770
771 /* default - pause configuration */
772 u32 pause_xoff_th = PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_PAUSEABLE;
773 u32 pause_xon_th = PFC_BRB_MAC_PAUSE_XON_THRESHOLD_PAUSEABLE;
774 u32 full_xoff_th = PFC_BRB_MAC_FULL_XOFF_THRESHOLD_PAUSEABLE;
775 u32 full_xon_th = PFC_BRB_MAC_FULL_XON_THRESHOLD_PAUSEABLE;
776
777 if (set_pfc && pfc_params)
778 /* First COS */
779 if (!pfc_params->cos0_pauseable) {
780 pause_xoff_th =
781 PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_NON_PAUSEABLE;
782 pause_xon_th =
783 PFC_BRB_MAC_PAUSE_XON_THRESHOLD_NON_PAUSEABLE;
784 full_xoff_th =
785 PFC_BRB_MAC_FULL_XOFF_THRESHOLD_NON_PAUSEABLE;
786 full_xon_th =
787 PFC_BRB_MAC_FULL_XON_THRESHOLD_NON_PAUSEABLE;
788 }
2cf7acf9
YR		 789 /*
790 * The number of free blocks below which the pause signal to class 0
791 * of MAC #n is asserted. n=0,1
792 */
bcab15c5 793 REG_WR(bp, BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 , pause_xoff_th);
2cf7acf9
YR		 794 /*
795 * The number of free blocks above which the pause signal to class 0
796 * of MAC #n is de-asserted. n=0,1
797 */
bcab15c5 798 REG_WR(bp, BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , pause_xon_th);
2cf7acf9
YR		 799 /*
800 * The number of free blocks below which the full signal to class 0
801 * of MAC #n is asserted. n=0,1
802 */
bcab15c5 803 REG_WR(bp, BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , full_xoff_th);
2cf7acf9
YR		 804 /*
805 * The number of free blocks above which the full signal to class 0
806 * of MAC #n is de-asserted. n=0,1
807 */
bcab15c5
VZ		 808 REG_WR(bp, BRB1_REG_FULL_0_XON_THRESHOLD_0 , full_xon_th);
809
810 if (set_pfc && pfc_params) {
811 /* Second COS */
812 if (pfc_params->cos1_pauseable) {
813 pause_xoff_th =
814 PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_PAUSEABLE;
815 pause_xon_th =
816 PFC_BRB_MAC_PAUSE_XON_THRESHOLD_PAUSEABLE;
817 full_xoff_th =
818 PFC_BRB_MAC_FULL_XOFF_THRESHOLD_PAUSEABLE;
819 full_xon_th =
820 PFC_BRB_MAC_FULL_XON_THRESHOLD_PAUSEABLE;
821 } else {
822 pause_xoff_th =
823 PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_NON_PAUSEABLE;
824 pause_xon_th =
825 PFC_BRB_MAC_PAUSE_XON_THRESHOLD_NON_PAUSEABLE;
826 full_xoff_th =
827 PFC_BRB_MAC_FULL_XOFF_THRESHOLD_NON_PAUSEABLE;
828 full_xon_th =
829 PFC_BRB_MAC_FULL_XON_THRESHOLD_NON_PAUSEABLE;
830 }
2cf7acf9 831 /*
bcab15c5
VZ		 832 * The number of free blocks below which the pause signal to
833 * class 1 of MAC #n is asserted. n=0,1
2cf7acf9 834 */
bcab15c5 835 REG_WR(bp, BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0, pause_xoff_th);
2cf7acf9 836 /*
bcab15c5
VZ		 837 * The number of free blocks above which the pause signal to
838 * class 1 of MAC #n is de-asserted. n=0,1
2cf7acf9 839 */
bcab15c5 840 REG_WR(bp, BRB1_REG_PAUSE_1_XON_THRESHOLD_0, pause_xon_th);
2cf7acf9 841 /*
bcab15c5
VZ		 842 * The number of free blocks below which the full signal to
843 * class 1 of MAC #n is asserted. n=0,1
2cf7acf9 844 */
bcab15c5 845 REG_WR(bp, BRB1_REG_FULL_1_XOFF_THRESHOLD_0, full_xoff_th);
2cf7acf9 846 /*
bcab15c5
VZ		 847 * The number of free blocks above which the full signal to
848 * class 1 of MAC #n is de-asserted. n=0,1
2cf7acf9 849 */
bcab15c5
VZ		 850 REG_WR(bp, BRB1_REG_FULL_1_XON_THRESHOLD_0, full_xon_th);
851 }
852}
853
854static void bnx2x_update_pfc_nig(struct link_params *params,
855 struct link_vars *vars,
856 struct bnx2x_nig_brb_pfc_port_params *nig_params)
857{
858 u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
859 u32 llfc_enable = 0, xcm0_out_en = 0, p0_hwpfc_enable = 0;
860 u32 pkt_priority_to_cos = 0;
861 u32 val;
862 struct bnx2x *bp = params->bp;
863 int port = params->port;
864 int set_pfc = params->feature_config_flags &
865 FEATURE_CONFIG_PFC_ENABLED;
866 DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
867
2cf7acf9 868 /*
bcab15c5
VZ		 869 * When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
870 * MAC control frames (that are not pause packets)
871 * will be forwarded to the XCM.
872 */
873 xcm_mask = REG_RD(bp,
874 port ? NIG_REG_LLH1_XCM_MASK :
875 NIG_REG_LLH0_XCM_MASK);
2cf7acf9 876 /*
bcab15c5
VZ		 877 * nig params will override non PFC params, since it's possible to
878 * do transition from PFC to SAFC
879 */
880 if (set_pfc) {
881 pause_enable = 0;
882 llfc_out_en = 0;
883 llfc_enable = 0;
884 ppp_enable = 1;
885 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
886 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
887 xcm0_out_en = 0;
888 p0_hwpfc_enable = 1;
889 } else {
890 if (nig_params) {
891 llfc_out_en = nig_params->llfc_out_en;
892 llfc_enable = nig_params->llfc_enable;
893 pause_enable = nig_params->pause_enable;
894 } else /*defaul non PFC mode - PAUSE */
895 pause_enable = 1;
896
897 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
898 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
899 xcm0_out_en = 1;
900 }
901
902 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
903 NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
904 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
905 NIG_REG_LLFC_ENABLE_0, llfc_enable);
906 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
907 NIG_REG_PAUSE_ENABLE_0, pause_enable);
908
909 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
910 NIG_REG_PPP_ENABLE_0, ppp_enable);
911
912 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
913 NIG_REG_LLH0_XCM_MASK, xcm_mask);
914
915 REG_WR(bp, NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
916
917 /* output enable for RX_XCM # IF */
918 REG_WR(bp, NIG_REG_XCM0_OUT_EN, xcm0_out_en);
919
920 /* HW PFC TX enable */
921 REG_WR(bp, NIG_REG_P0_HWPFC_ENABLE, p0_hwpfc_enable);
922
923 /* 0x2 = BMAC, 0x1= EMAC */
924 switch (vars->mac_type) {
925 case MAC_TYPE_EMAC:
926 val = 1;
927 break;
928 case MAC_TYPE_BMAC:
929 val = 0;
930 break;
931 default:
932 val = 0;
933 break;
934 }
935 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT, val);
936
937 if (nig_params) {
938 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
939
940 REG_WR(bp, port ? NIG_REG_P1_RX_COS0_PRIORITY_MASK :
941 NIG_REG_P0_RX_COS0_PRIORITY_MASK,
942 nig_params->rx_cos0_priority_mask);
943
944 REG_WR(bp, port ? NIG_REG_P1_RX_COS1_PRIORITY_MASK :
945 NIG_REG_P0_RX_COS1_PRIORITY_MASK,
946 nig_params->rx_cos1_priority_mask);
947
948 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
949 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
950 nig_params->llfc_high_priority_classes);
951
952 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
953 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
954 nig_params->llfc_low_priority_classes);
955 }
956 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
957 NIG_REG_P0_PKT_PRIORITY_TO_COS,
958 pkt_priority_to_cos);
959}
960
961
962void bnx2x_update_pfc(struct link_params *params,
963 struct link_vars *vars,
964 struct bnx2x_nig_brb_pfc_port_params *pfc_params)
965{
2cf7acf9 966 /*
bcab15c5
VZ		 967 * The PFC and pause are orthogonal to one another, meaning when
968 * PFC is enabled, the pause are disabled, and when PFC is
969 * disabled, pause are set according to the pause result.
970 */
971 u32 val;
972 struct bnx2x *bp = params->bp;
973
974 /* update NIG params */
975 bnx2x_update_pfc_nig(params, vars, pfc_params);
976
977 /* update BRB params */
978 bnx2x_update_pfc_brb(params, vars, pfc_params);
979
980 if (!vars->link_up)
981 return;
982
983 val = REG_RD(bp, MISC_REG_RESET_REG_2);
984 if ((val & (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
985 == 0) {
986 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
987 bnx2x_emac_enable(params, vars, 0);
988 return;
989 }
990
991 DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
992 if (CHIP_IS_E2(bp))
993 bnx2x_update_pfc_bmac2(params, vars, 0);
994 else
995 bnx2x_update_pfc_bmac1(params, vars);
996
997 val = 0;
998 if ((params->feature_config_flags &
999 FEATURE_CONFIG_PFC_ENABLED) ||
1000 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1001 val = 1;
1002 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
1003}
f2e0899f
DK		 1004
1005static u8 bnx2x_bmac1_enable(struct link_params *params,
1006 struct link_vars *vars,
cd88ccee 1007 u8 is_lb)
ea4e040a
YR		 1008{
1009 struct bnx2x *bp = params->bp;
1010 u8 port = params->port;
1011 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
1012 NIG_REG_INGRESS_BMAC0_MEM;
1013 u32 wb_data[2];
1014 u32 val;
1015
f2e0899f 1016 DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
ea4e040a
YR		 1017
1018 /* XGXS control */
1019 wb_data[0] = 0x3c;
1020 wb_data[1] = 0;
cd88ccee
YR		 1021 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
1022 wb_data, 2);
ea4e040a
YR		 1023
1024 /* tx MAC SA */
1025 wb_data[0] = ((params->mac_addr[2] << 24) |
1026 (params->mac_addr[3] << 16) |
1027 (params->mac_addr[4] << 8) |
1028 params->mac_addr[5]);
1029 wb_data[1] = ((params->mac_addr[0] << 8) |
1030 params->mac_addr[1]);
cd88ccee 1031 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
ea4e040a 1032
ea4e040a
YR		 1033 /* mac control */
1034 val = 0x3;
1035 if (is_lb) {
1036 val |= 0x4;
1037 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
1038 }
1039 wb_data[0] = val;
1040 wb_data[1] = 0;
cd88ccee 1041 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
ea4e040a 1042
ea4e040a
YR		 1043 /* set rx mtu */
1044 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1045 wb_data[1] = 0;
cd88ccee 1046 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
ea4e040a 1047
bcab15c5 1048 bnx2x_update_pfc_bmac1(params, vars);
ea4e040a
YR		 1049
1050 /* set tx mtu */
1051 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1052 wb_data[1] = 0;
cd88ccee 1053 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
ea4e040a
YR		 1054
1055 /* set cnt max size */
1056 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1057 wb_data[1] = 0;
cd88ccee 1058 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
ea4e040a
YR		 1059
1060 /* configure safc */
1061 wb_data[0] = 0x1000200;
1062 wb_data[1] = 0;
1063 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
1064 wb_data, 2);
f2e0899f
DK		 1065
1066 return 0;
1067}
1068
1069static u8 bnx2x_bmac2_enable(struct link_params *params,
1070 struct link_vars *vars,
1071 u8 is_lb)
1072{
1073 struct bnx2x *bp = params->bp;
1074 u8 port = params->port;
1075 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
1076 NIG_REG_INGRESS_BMAC0_MEM;
1077 u32 wb_data[2];
1078
1079 DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
1080
1081 wb_data[0] = 0;
1082 wb_data[1] = 0;
cd88ccee 1083 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
f2e0899f
DK		 1084 udelay(30);
1085
1086 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
1087 wb_data[0] = 0x3c;
1088 wb_data[1] = 0;
cd88ccee
YR		 1089 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
1090 wb_data, 2);
f2e0899f
DK		 1091
1092 udelay(30);
1093
1094 /* tx MAC SA */
1095 wb_data[0] = ((params->mac_addr[2] << 24) |
1096 (params->mac_addr[3] << 16) |
1097 (params->mac_addr[4] << 8) |
1098 params->mac_addr[5]);
1099 wb_data[1] = ((params->mac_addr[0] << 8) |
1100 params->mac_addr[1]);
1101 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
cd88ccee 1102 wb_data, 2);
f2e0899f
DK		 1103
1104 udelay(30);
1105
1106 /* Configure SAFC */
1107 wb_data[0] = 0x1000200;
1108 wb_data[1] = 0;
1109 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
cd88ccee 1110 wb_data, 2);
f2e0899f
DK		 1111 udelay(30);
1112
1113 /* set rx mtu */
1114 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1115 wb_data[1] = 0;
cd88ccee 1116 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
f2e0899f
DK		 1117 udelay(30);
1118
1119 /* set tx mtu */
1120 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1121 wb_data[1] = 0;
cd88ccee 1122 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
f2e0899f
DK		 1123 udelay(30);
1124 /* set cnt max size */
1125 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
1126 wb_data[1] = 0;
cd88ccee 1127 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
f2e0899f 1128 udelay(30);
bcab15c5 1129 bnx2x_update_pfc_bmac2(params, vars, is_lb);
f2e0899f
DK		 1130
1131 return 0;
1132}
1133
8d96286a 1134static u8 bnx2x_bmac_enable(struct link_params *params,
f2e0899f
DK		 1135 struct link_vars *vars,
1136 u8 is_lb)
1137{
1138 u8 rc, port = params->port;
1139 struct bnx2x *bp = params->bp;
1140 u32 val;
1141 /* reset and unreset the BigMac */
1142 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
cd88ccee 1143 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1d9c05d4 1144 msleep(1);
f2e0899f
DK		 1145
1146 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
cd88ccee 1147 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
f2e0899f
DK		 1148
1149 /* enable access for bmac registers */
1150 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
1151
1152 /* Enable BMAC according to BMAC type*/
1153 if (CHIP_IS_E2(bp))
1154 rc = bnx2x_bmac2_enable(params, vars, is_lb);
1155 else
1156 rc = bnx2x_bmac1_enable(params, vars, is_lb);
ea4e040a
YR		 1157 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
1158 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
1159 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
1160 val = 0;
bcab15c5
VZ		 1161 if ((params->feature_config_flags &
1162 FEATURE_CONFIG_PFC_ENABLED) ||
1163 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
ea4e040a
YR		 1164 val = 1;
1165 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
1166 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
1167 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
1168 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
1169 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
1170 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
1171
1172 vars->mac_type = MAC_TYPE_BMAC;
f2e0899f 1173 return rc;
ea4e040a
YR		 1174}
1175
ea4e040a
YR		 1176
1177static void bnx2x_update_mng(struct link_params *params, u32 link_status)
1178{
1179 struct bnx2x *bp = params->bp;
ab6ad5a4 1180
ea4e040a 1181 REG_WR(bp, params->shmem_base +
cd88ccee
YR		 1182 offsetof(struct shmem_region,
1183 port_mb[params->port].link_status), link_status);
ea4e040a
YR		 1184}
1185
1186static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
1187{
1188 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
cd88ccee 1189 NIG_REG_INGRESS_BMAC0_MEM;
ea4e040a 1190 u32 wb_data[2];
3196a88a 1191 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
ea4e040a
YR		 1192
1193 /* Only if the bmac is out of reset */
1194 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1195 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
1196 nig_bmac_enable) {
1197
f2e0899f
DK		 1198 if (CHIP_IS_E2(bp)) {
1199 /* Clear Rx Enable bit in BMAC_CONTROL register */
1200 REG_RD_DMAE(bp, bmac_addr +
cd88ccee
YR		 1201 BIGMAC2_REGISTER_BMAC_CONTROL,
1202 wb_data, 2);
f2e0899f
DK		 1203 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
1204 REG_WR_DMAE(bp, bmac_addr +
cd88ccee
YR		 1205 BIGMAC2_REGISTER_BMAC_CONTROL,
1206 wb_data, 2);
f2e0899f
DK		 1207 } else {
1208 /* Clear Rx Enable bit in BMAC_CONTROL register */
1209 REG_RD_DMAE(bp, bmac_addr +
1210 BIGMAC_REGISTER_BMAC_CONTROL,
1211 wb_data, 2);
1212 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
1213 REG_WR_DMAE(bp, bmac_addr +
1214 BIGMAC_REGISTER_BMAC_CONTROL,
1215 wb_data, 2);
1216 }
ea4e040a
YR		 1217 msleep(1);
1218 }
1219}
1220
1221static u8 bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
cd88ccee 1222 u32 line_speed)
ea4e040a
YR		 1223{
1224 struct bnx2x *bp = params->bp;
1225 u8 port = params->port;
1226 u32 init_crd, crd;
1227 u32 count = 1000;
ea4e040a
YR		 1228
1229 /* disable port */
1230 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
1231
1232 /* wait for init credit */
1233 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
1234 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
1235 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
1236
1237 while ((init_crd != crd) && count) {
1238 msleep(5);
1239
1240 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
1241 count--;
1242 }
1243 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
1244 if (init_crd != crd) {
1245 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
1246 init_crd, crd);
1247 return -EINVAL;
1248 }
1249
c0700f90 1250 if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
8c99e7b0
YR		 1251 line_speed == SPEED_10 ||
1252 line_speed == SPEED_100 ||
1253 line_speed == SPEED_1000 ||
1254 line_speed == SPEED_2500) {
1255 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
ea4e040a
YR		 1256 /* update threshold */
1257 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
1258 /* update init credit */
cd88ccee 1259 init_crd = 778; /* (800-18-4) */
ea4e040a
YR		 1260
1261 } else {
1262 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
1263 ETH_OVREHEAD)/16;
8c99e7b0 1264 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
ea4e040a
YR		 1265 /* update threshold */
1266 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
1267 /* update init credit */
1268 switch (line_speed) {
ea4e040a
YR		 1269 case SPEED_10000:
1270 init_crd = thresh + 553 - 22;
1271 break;
1272
1273 case SPEED_12000:
1274 init_crd = thresh + 664 - 22;
1275 break;
1276
1277 case SPEED_13000:
1278 init_crd = thresh + 742 - 22;
1279 break;
1280
1281 case SPEED_16000:
1282 init_crd = thresh + 778 - 22;
1283 break;
1284 default:
1285 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
1286 line_speed);
1287 return -EINVAL;
ea4e040a
YR		 1288 }
1289 }
1290 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
1291 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
1292 line_speed, init_crd);
1293
1294 /* probe the credit changes */
1295 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
1296 msleep(5);
1297 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
1298
1299 /* enable port */
1300 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
1301 return 0;
1302}
1303
e8920674
DK		 1304/**
1305 * bnx2x_get_emac_base - retrive emac base address
2cf7acf9 1306 *
e8920674
DK		 1307 * @bp: driver handle
1308 * @mdc_mdio_access: access type
1309 * @port: port id
2cf7acf9
YR		 1310 *
1311 * This function selects the MDC/MDIO access (through emac0 or
1312 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
1313 * phy has a default access mode, which could also be overridden
1314 * by nvram configuration. This parameter, whether this is the
1315 * default phy configuration, or the nvram overrun
1316 * configuration, is passed here as mdc_mdio_access and selects
1317 * the emac_base for the CL45 read/writes operations
1318 */
c18aa15d
YR		 1319static u32 bnx2x_get_emac_base(struct bnx2x *bp,
1320 u32 mdc_mdio_access, u8 port)
ea4e040a 1321{
c18aa15d
YR		 1322 u32 emac_base = 0;
1323 switch (mdc_mdio_access) {
1324 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
1325 break;
1326 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
1327 if (REG_RD(bp, NIG_REG_PORT_SWAP))
1328 emac_base = GRCBASE_EMAC1;
1329 else
1330 emac_base = GRCBASE_EMAC0;
1331 break;
1332 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
589abe3a
EG		 1333 if (REG_RD(bp, NIG_REG_PORT_SWAP))
1334 emac_base = GRCBASE_EMAC0;
1335 else
1336 emac_base = GRCBASE_EMAC1;
ea4e040a 1337 break;
c18aa15d
YR		 1338 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
1339 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1340 break;
1341 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
6378c025 1342 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
ea4e040a
YR		 1343 break;
1344 default:
ea4e040a
YR		 1345 break;
1346 }
1347 return emac_base;
1348
1349}
1350
2cf7acf9
YR		 1351/******************************************************************/
1352/* CL45 access functions */
1353/******************************************************************/
65a001ba
YR		 1354static u8 bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
1355 u8 devad, u16 reg, u16 val)
ea4e040a
YR		 1356{
1357 u32 tmp, saved_mode;
1358 u8 i, rc = 0;
2cf7acf9
YR		 1359 /*
1360 * Set clause 45 mode, slow down the MDIO clock to 2.5MHz
ea4e040a
YR		 1361 * (a value of 49==0x31) and make sure that the AUTO poll is off
1362 */
589abe3a 1363
e10bc84d 1364 saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
ea4e040a
YR		 1365 tmp = saved_mode & ~(EMAC_MDIO_MODE_AUTO_POLL |
1366 EMAC_MDIO_MODE_CLOCK_CNT);
1367 tmp |= (EMAC_MDIO_MODE_CLAUSE_45 |
1368 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
e10bc84d
YR		 1369 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp);
1370 REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
ea4e040a
YR		 1371 udelay(40);
1372
1373 /* address */
1374
e10bc84d 1375 tmp = ((phy->addr << 21) | (devad << 16) | reg |
ea4e040a
YR		 1376 EMAC_MDIO_COMM_COMMAND_ADDRESS |
1377 EMAC_MDIO_COMM_START_BUSY);
e10bc84d 1378 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
ea4e040a
YR		 1379
1380 for (i = 0; i < 50; i++) {
1381 udelay(10);
1382
cd88ccee 1383 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
ea4e040a
YR		 1384 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1385 udelay(5);
1386 break;
1387 }
1388 }
1389 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1390 DP(NETIF_MSG_LINK, "write phy register failed\n");
6d870c39 1391 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
ea4e040a
YR		 1392 rc = -EFAULT;
1393 } else {
1394 /* data */
e10bc84d 1395 tmp = ((phy->addr << 21) | (devad << 16) | val |
ea4e040a
YR		 1396 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
1397 EMAC_MDIO_COMM_START_BUSY);
e10bc84d 1398 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
ea4e040a
YR		 1399
1400 for (i = 0; i < 50; i++) {
1401 udelay(10);
1402
e10bc84d 1403 tmp = REG_RD(bp, phy->mdio_ctrl +
cd88ccee 1404 EMAC_REG_EMAC_MDIO_COMM);
ea4e040a
YR		 1405 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1406 udelay(5);
1407 break;
1408 }
1409 }
1410 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1411 DP(NETIF_MSG_LINK, "write phy register failed\n");
6d870c39 1412 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
ea4e040a
YR		 1413 rc = -EFAULT;
1414 }
1415 }
1416
1417 /* Restore the saved mode */
e10bc84d 1418 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
ea4e040a
YR		 1419
1420 return rc;
1421}
1422
65a001ba
YR		 1423static u8 bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
1424 u8 devad, u16 reg, u16 *ret_val)
ea4e040a
YR		 1425{
1426 u32 val, saved_mode;
1427 u16 i;
1428 u8 rc = 0;
2cf7acf9
YR		 1429 /*
1430 * Set clause 45 mode, slow down the MDIO clock to 2.5MHz
ea4e040a
YR		 1431 * (a value of 49==0x31) and make sure that the AUTO poll is off
1432 */
589abe3a 1433
e10bc84d
YR		 1434 saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1435 val = saved_mode & ~((EMAC_MDIO_MODE_AUTO_POLL |
cd88ccee 1436 EMAC_MDIO_MODE_CLOCK_CNT));
ea4e040a 1437 val |= (EMAC_MDIO_MODE_CLAUSE_45 |
ab6ad5a4 1438 (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
e10bc84d
YR		 1439 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
1440 REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
ea4e040a
YR		 1441 udelay(40);
1442
1443 /* address */
e10bc84d 1444 val = ((phy->addr << 21) | (devad << 16) | reg |
ea4e040a
YR		 1445 EMAC_MDIO_COMM_COMMAND_ADDRESS |
1446 EMAC_MDIO_COMM_START_BUSY);
e10bc84d 1447 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
ea4e040a
YR		 1448
1449 for (i = 0; i < 50; i++) {
1450 udelay(10);
1451
e10bc84d 1452 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
ea4e040a
YR		 1453 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1454 udelay(5);
1455 break;
1456 }
1457 }
1458 if (val & EMAC_MDIO_COMM_START_BUSY) {
1459 DP(NETIF_MSG_LINK, "read phy register failed\n");
6d870c39 1460 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
ea4e040a
YR		 1461 *ret_val = 0;
1462 rc = -EFAULT;
1463
1464 } else {
1465 /* data */
e10bc84d 1466 val = ((phy->addr << 21) | (devad << 16) |
ea4e040a
YR		 1467 EMAC_MDIO_COMM_COMMAND_READ_45 |
1468 EMAC_MDIO_COMM_START_BUSY);
e10bc84d 1469 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
ea4e040a
YR		 1470
1471 for (i = 0; i < 50; i++) {
1472 udelay(10);
1473
e10bc84d 1474 val = REG_RD(bp, phy->mdio_ctrl +
cd88ccee 1475 EMAC_REG_EMAC_MDIO_COMM);
ea4e040a
YR		 1476 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1477 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
1478 break;
1479 }
1480 }
1481 if (val & EMAC_MDIO_COMM_START_BUSY) {
1482 DP(NETIF_MSG_LINK, "read phy register failed\n");
6d870c39 1483 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
ea4e040a
YR		 1484 *ret_val = 0;
1485 rc = -EFAULT;
1486 }
1487 }
1488
1489 /* Restore the saved mode */
e10bc84d 1490 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
ea4e040a
YR		 1491
1492 return rc;
1493}
1494
e10bc84d
YR		 1495u8 bnx2x_phy_read(struct link_params *params, u8 phy_addr,
1496 u8 devad, u16 reg, u16 *ret_val)
1497{
1498 u8 phy_index;
2cf7acf9 1499 /*
e10bc84d
YR		 1500 * Probe for the phy according to the given phy_addr, and execute
1501 * the read request on it
1502 */
1503 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
1504 if (params->phy[phy_index].addr == phy_addr) {
1505 return bnx2x_cl45_read(params->bp,
1506 &params->phy[phy_index], devad,
1507 reg, ret_val);
1508 }
1509 }
1510 return -EINVAL;
1511}
1512
1513u8 bnx2x_phy_write(struct link_params *params, u8 phy_addr,
1514 u8 devad, u16 reg, u16 val)
1515{
1516 u8 phy_index;
2cf7acf9 1517 /*
e10bc84d
YR		 1518 * Probe for the phy according to the given phy_addr, and execute
1519 * the write request on it
1520 */
1521 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
1522 if (params->phy[phy_index].addr == phy_addr) {
1523 return bnx2x_cl45_write(params->bp,
1524 &params->phy[phy_index], devad,
1525 reg, val);
1526 }
1527 }
1528 return -EINVAL;
1529}
1530
f2e0899f
DK		 1531static void bnx2x_set_aer_mmd_xgxs(struct link_params *params,
1532 struct bnx2x_phy *phy)
ea4e040a 1533{
ea4e040a 1534 u32 ser_lane;
f2e0899f
DK		 1535 u16 offset, aer_val;
1536 struct bnx2x *bp = params->bp;
ea4e040a
YR		 1537 ser_lane = ((params->lane_config &
1538 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1539 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1540
f2e0899f
DK		 1541 offset = phy->addr + ser_lane;
1542 if (CHIP_IS_E2(bp))
82a0d475 1543 aer_val = 0x3800 + offset - 1;
f2e0899f
DK		 1544 else
1545 aer_val = 0x3800 + offset;
cd2be89b 1546 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
cd88ccee 1547 MDIO_AER_BLOCK_AER_REG, aer_val);
f2e0899f
DK		 1548}
1549static void bnx2x_set_aer_mmd_serdes(struct bnx2x *bp,
1550 struct bnx2x_phy *phy)
1551{
cd2be89b 1552 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 1553 MDIO_REG_BANK_AER_BLOCK,
1554 MDIO_AER_BLOCK_AER_REG, 0x3800);
ea4e040a
YR		 1555}
1556
de6eae1f
YR		 1557/******************************************************************/
1558/* Internal phy section */
1559/******************************************************************/
ea4e040a 1560
de6eae1f
YR		 1561static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
1562{
1563 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
ea4e040a 1564
de6eae1f
YR		 1565 /* Set Clause 22 */
1566 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
1567 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
1568 udelay(500);
1569 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
1570 udelay(500);
1571 /* Set Clause 45 */
1572 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
ea4e040a
YR		 1573}
1574
de6eae1f 1575static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
ea4e040a 1576{
de6eae1f 1577 u32 val;
ea4e040a 1578
de6eae1f 1579 DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
ea4e040a 1580
de6eae1f 1581 val = SERDES_RESET_BITS << (port*16);
c1b73990 1582
de6eae1f
YR		 1583 /* reset and unreset the SerDes/XGXS */
1584 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
1585 udelay(500);
1586 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
ea4e040a 1587
de6eae1f 1588 bnx2x_set_serdes_access(bp, port);
ea4e040a 1589
cd88ccee
YR		 1590 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
1591 DEFAULT_PHY_DEV_ADDR);
de6eae1f
YR		 1592}
1593
1594static void bnx2x_xgxs_deassert(struct link_params *params)
1595{
1596 struct bnx2x *bp = params->bp;
1597 u8 port;
1598 u32 val;
1599 DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
1600 port = params->port;
1601
1602 val = XGXS_RESET_BITS << (port*16);
1603
1604 /* reset and unreset the SerDes/XGXS */
1605 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
1606 udelay(500);
1607 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
1608
cd88ccee 1609 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 0);
de6eae1f 1610 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
cd88ccee 1611 params->phy[INT_PHY].def_md_devad);
de6eae1f
YR		 1612}
1613
a22f0788 1614
de6eae1f 1615void bnx2x_link_status_update(struct link_params *params,
cd88ccee 1616 struct link_vars *vars)
de6eae1f
YR		 1617{
1618 struct bnx2x *bp = params->bp;
1619 u8 link_10g;
1620 u8 port = params->port;
1621
de6eae1f 1622 vars->link_status = REG_RD(bp, params->shmem_base +
cd88ccee
YR		 1623 offsetof(struct shmem_region,
1624 port_mb[port].link_status));
de6eae1f
YR		 1625
1626 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
1627
1628 if (vars->link_up) {
1629 DP(NETIF_MSG_LINK, "phy link up\n");
1630
1631 vars->phy_link_up = 1;
1632 vars->duplex = DUPLEX_FULL;
1633 switch (vars->link_status &
cd88ccee 1634 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
de6eae1f
YR		 1635 case LINK_10THD:
1636 vars->duplex = DUPLEX_HALF;
1637 /* fall thru */
1638 case LINK_10TFD:
1639 vars->line_speed = SPEED_10;
1640 break;
1641
1642 case LINK_100TXHD:
1643 vars->duplex = DUPLEX_HALF;
1644 /* fall thru */
1645 case LINK_100T4:
1646 case LINK_100TXFD:
1647 vars->line_speed = SPEED_100;
1648 break;
1649
1650 case LINK_1000THD:
1651 vars->duplex = DUPLEX_HALF;
1652 /* fall thru */
1653 case LINK_1000TFD:
1654 vars->line_speed = SPEED_1000;
1655 break;
1656
1657 case LINK_2500THD:
1658 vars->duplex = DUPLEX_HALF;
1659 /* fall thru */
1660 case LINK_2500TFD:
1661 vars->line_speed = SPEED_2500;
1662 break;
1663
1664 case LINK_10GTFD:
1665 vars->line_speed = SPEED_10000;
1666 break;
1667
1668 case LINK_12GTFD:
1669 vars->line_speed = SPEED_12000;
1670 break;
1671
1672 case LINK_12_5GTFD:
1673 vars->line_speed = SPEED_12500;
1674 break;
1675
1676 case LINK_13GTFD:
1677 vars->line_speed = SPEED_13000;
1678 break;
1679
1680 case LINK_15GTFD:
1681 vars->line_speed = SPEED_15000;
1682 break;
1683
1684 case LINK_16GTFD:
1685 vars->line_speed = SPEED_16000;
1686 break;
1687
1688 default:
1689 break;
1690 }
de6eae1f
YR		 1691 vars->flow_ctrl = 0;
1692 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
1693 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
1694
1695 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
1696 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
1697
1698 if (!vars->flow_ctrl)
1699 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
1700
1701 if (vars->line_speed &&
1702 ((vars->line_speed == SPEED_10) ||
1703 (vars->line_speed == SPEED_100))) {
1704 vars->phy_flags |= PHY_SGMII_FLAG;
1705 } else {
1706 vars->phy_flags &= ~PHY_SGMII_FLAG;
1707 }
1708
1709 /* anything 10 and over uses the bmac */
1710 link_10g = ((vars->line_speed == SPEED_10000) ||
1711 (vars->line_speed == SPEED_12000) ||
1712 (vars->line_speed == SPEED_12500) ||
1713 (vars->line_speed == SPEED_13000) ||
1714 (vars->line_speed == SPEED_15000) ||
1715 (vars->line_speed == SPEED_16000));
1716 if (link_10g)
1717 vars->mac_type = MAC_TYPE_BMAC;
1718 else
1719 vars->mac_type = MAC_TYPE_EMAC;
1720
1721 } else { /* link down */
1722 DP(NETIF_MSG_LINK, "phy link down\n");
1723
1724 vars->phy_link_up = 0;
1725
1726 vars->line_speed = 0;
1727 vars->duplex = DUPLEX_FULL;
1728 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
1729
1730 /* indicate no mac active */
1731 vars->mac_type = MAC_TYPE_NONE;
1732 }
1733
1734 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x\n",
1735 vars->link_status, vars->phy_link_up);
1736 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n",
1737 vars->line_speed, vars->duplex, vars->flow_ctrl);
1738}
1739
1740
1741static void bnx2x_set_master_ln(struct link_params *params,
1742 struct bnx2x_phy *phy)
1743{
1744 struct bnx2x *bp = params->bp;
1745 u16 new_master_ln, ser_lane;
cd88ccee 1746 ser_lane = ((params->lane_config &
de6eae1f 1747 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
cd88ccee 1748 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
de6eae1f
YR		 1749
1750 /* set the master_ln for AN */
cd2be89b 1751 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 1752 MDIO_REG_BANK_XGXS_BLOCK2,
1753 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1754 &new_master_ln);
de6eae1f 1755
cd2be89b 1756 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 1757 MDIO_REG_BANK_XGXS_BLOCK2 ,
1758 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1759 (new_master_ln | ser_lane));
de6eae1f
YR		 1760}
1761
1762static u8 bnx2x_reset_unicore(struct link_params *params,
1763 struct bnx2x_phy *phy,
1764 u8 set_serdes)
1765{
1766 struct bnx2x *bp = params->bp;
1767 u16 mii_control;
1768 u16 i;
cd2be89b 1769 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 1770 MDIO_REG_BANK_COMBO_IEEE0,
1771 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
de6eae1f
YR		 1772
1773 /* reset the unicore */
cd2be89b 1774 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 1775 MDIO_REG_BANK_COMBO_IEEE0,
1776 MDIO_COMBO_IEEE0_MII_CONTROL,
1777 (mii_control |
1778 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
de6eae1f
YR		 1779 if (set_serdes)
1780 bnx2x_set_serdes_access(bp, params->port);
1781
1782 /* wait for the reset to self clear */
1783 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
1784 udelay(5);
1785
1786 /* the reset erased the previous bank value */
cd2be89b 1787 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 1788 MDIO_REG_BANK_COMBO_IEEE0,
1789 MDIO_COMBO_IEEE0_MII_CONTROL,
1790 &mii_control);
de6eae1f
YR		 1791
1792 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
1793 udelay(5);
1794 return 0;
1795 }
1796 }
ea4e040a 1797
6d870c39
YR		 1798 netdev_err(bp->dev, "Warning: PHY was not initialized,"
1799 " Port %d\n",
1800 params->port);
ea4e040a
YR		 1801 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
1802 return -EINVAL;
1803
1804}
1805
e10bc84d
YR		 1806static void bnx2x_set_swap_lanes(struct link_params *params,
1807 struct bnx2x_phy *phy)
ea4e040a
YR		 1808{
1809 struct bnx2x *bp = params->bp;
2cf7acf9
YR		 1810 /*
1811 * Each two bits represents a lane number:
1812 * No swap is 0123 => 0x1b no need to enable the swap
1813 */
ea4e040a
YR		 1814 u16 ser_lane, rx_lane_swap, tx_lane_swap;
1815
1816 ser_lane = ((params->lane_config &
cd88ccee
YR		 1817 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1818 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
ea4e040a 1819 rx_lane_swap = ((params->lane_config &
cd88ccee
YR		 1820 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
1821 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
ea4e040a 1822 tx_lane_swap = ((params->lane_config &
cd88ccee
YR		 1823 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
1824 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
ea4e040a
YR		 1825
1826 if (rx_lane_swap != 0x1b) {
cd2be89b 1827 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 1828 MDIO_REG_BANK_XGXS_BLOCK2,
1829 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
1830 (rx_lane_swap |
1831 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
1832 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
ea4e040a 1833 } else {
cd2be89b 1834 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 1835 MDIO_REG_BANK_XGXS_BLOCK2,
1836 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
ea4e040a
YR		 1837 }
1838
1839 if (tx_lane_swap != 0x1b) {
cd2be89b 1840 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 1841 MDIO_REG_BANK_XGXS_BLOCK2,
1842 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
1843 (tx_lane_swap |
1844 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
ea4e040a 1845 } else {
cd2be89b 1846 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 1847 MDIO_REG_BANK_XGXS_BLOCK2,
1848 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
ea4e040a
YR		 1849 }
1850}
1851
e10bc84d
YR		 1852static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
1853 struct link_params *params)
ea4e040a
YR		 1854{
1855 struct bnx2x *bp = params->bp;
1856 u16 control2;
cd2be89b 1857 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 1858 MDIO_REG_BANK_SERDES_DIGITAL,
1859 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1860 &control2);
7aa0711f 1861 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
18afb0a6
YR		 1862 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
1863 else
1864 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
7aa0711f
YR		 1865 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
1866 phy->speed_cap_mask, control2);
cd2be89b 1867 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 1868 MDIO_REG_BANK_SERDES_DIGITAL,
1869 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1870 control2);
ea4e040a 1871
e10bc84d 1872 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
c18aa15d 1873 (phy->speed_cap_mask &
18afb0a6 1874 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
ea4e040a
YR		 1875 DP(NETIF_MSG_LINK, "XGXS\n");
1876
cd2be89b 1877 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 1878 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1879 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
1880 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
ea4e040a 1881
cd2be89b 1882 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 1883 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1884 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1885 &control2);
ea4e040a
YR		 1886
1887
1888 control2 |=
1889 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
1890
cd2be89b 1891 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 1892 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1893 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1894 control2);
ea4e040a
YR		 1895
1896 /* Disable parallel detection of HiG */
cd2be89b 1897 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 1898 MDIO_REG_BANK_XGXS_BLOCK2,
1899 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
1900 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
1901 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
ea4e040a
YR		 1902 }
1903}
1904
e10bc84d
YR		 1905static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
1906 struct link_params *params,
cd88ccee
YR		 1907 struct link_vars *vars,
1908 u8 enable_cl73)
ea4e040a
YR		 1909{
1910 struct bnx2x *bp = params->bp;
1911 u16 reg_val;
1912
1913 /* CL37 Autoneg */
cd2be89b 1914 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 1915 MDIO_REG_BANK_COMBO_IEEE0,
1916 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
ea4e040a
YR		 1917
1918 /* CL37 Autoneg Enabled */
8c99e7b0 1919 if (vars->line_speed == SPEED_AUTO_NEG)
ea4e040a
YR		 1920 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
1921 else /* CL37 Autoneg Disabled */
1922 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1923 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
1924
cd2be89b 1925 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 1926 MDIO_REG_BANK_COMBO_IEEE0,
1927 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
ea4e040a
YR		 1928
1929 /* Enable/Disable Autodetection */
1930
cd2be89b 1931 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 1932 MDIO_REG_BANK_SERDES_DIGITAL,
1933 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
239d686d
EG		 1934 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
1935 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
1936 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
8c99e7b0 1937 if (vars->line_speed == SPEED_AUTO_NEG)
ea4e040a
YR		 1938 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1939 else
1940 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1941
cd2be89b 1942 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 1943 MDIO_REG_BANK_SERDES_DIGITAL,
1944 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
ea4e040a
YR		 1945
1946 /* Enable TetonII and BAM autoneg */
cd2be89b 1947 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 1948 MDIO_REG_BANK_BAM_NEXT_PAGE,
1949 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
ea4e040a 1950 &reg_val);
8c99e7b0 1951 if (vars->line_speed == SPEED_AUTO_NEG) {
ea4e040a
YR		 1952 /* Enable BAM aneg Mode and TetonII aneg Mode */
1953 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1954 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1955 } else {
1956 /* TetonII and BAM Autoneg Disabled */
1957 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1958 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1959 }
cd2be89b 1960 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 1961 MDIO_REG_BANK_BAM_NEXT_PAGE,
1962 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1963 reg_val);
ea4e040a 1964
239d686d
EG		 1965 if (enable_cl73) {
1966 /* Enable Cl73 FSM status bits */
cd2be89b 1967 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 1968 MDIO_REG_BANK_CL73_USERB0,
1969 MDIO_CL73_USERB0_CL73_UCTRL,
1970 0xe);
239d686d
EG		 1971
1972 /* Enable BAM Station Manager*/
cd2be89b 1973 CL22_WR_OVER_CL45(bp, phy,
239d686d
EG		 1974 MDIO_REG_BANK_CL73_USERB0,
1975 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
1976 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
1977 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
1978 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
1979
7846e471 1980 /* Advertise CL73 link speeds */
cd2be89b 1981 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 1982 MDIO_REG_BANK_CL73_IEEEB1,
1983 MDIO_CL73_IEEEB1_AN_ADV2,
1984 &reg_val);
7aa0711f 1985 if (phy->speed_cap_mask &
7846e471
YR		 1986 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
1987 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
7aa0711f 1988 if (phy->speed_cap_mask &
7846e471
YR		 1989 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
1990 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
239d686d 1991
cd2be89b 1992 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 1993 MDIO_REG_BANK_CL73_IEEEB1,
1994 MDIO_CL73_IEEEB1_AN_ADV2,
1995 reg_val);
239d686d 1996
239d686d
EG		 1997 /* CL73 Autoneg Enabled */
1998 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
1999
2000 } else /* CL73 Autoneg Disabled */
2001 reg_val = 0;
ea4e040a 2002
cd2be89b 2003 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 2004 MDIO_REG_BANK_CL73_IEEEB0,
2005 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
ea4e040a
YR		 2006}
2007
2008/* program SerDes, forced speed */
e10bc84d
YR		 2009static void bnx2x_program_serdes(struct bnx2x_phy *phy,
2010 struct link_params *params,
cd88ccee 2011 struct link_vars *vars)
ea4e040a
YR		 2012{
2013 struct bnx2x *bp = params->bp;
2014 u16 reg_val;
2015
57937203 2016 /* program duplex, disable autoneg and sgmii*/
cd2be89b 2017 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2018 MDIO_REG_BANK_COMBO_IEEE0,
2019 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
ea4e040a 2020 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
57937203
EG		 2021 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2022 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
7aa0711f 2023 if (phy->req_duplex == DUPLEX_FULL)
ea4e040a 2024 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
cd2be89b 2025 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 2026 MDIO_REG_BANK_COMBO_IEEE0,
2027 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
ea4e040a 2028
2cf7acf9
YR		 2029 /*
2030 * program speed
2031 * - needed only if the speed is greater than 1G (2.5G or 10G)
2032 */
cd2be89b 2033 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2034 MDIO_REG_BANK_SERDES_DIGITAL,
2035 MDIO_SERDES_DIGITAL_MISC1, &reg_val);
8c99e7b0
YR		 2036 /* clearing the speed value before setting the right speed */
2037 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
2038
2039 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
2040 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
2041
2042 if (!((vars->line_speed == SPEED_1000) ||
2043 (vars->line_speed == SPEED_100) ||
2044 (vars->line_speed == SPEED_10))) {
2045
ea4e040a
YR		 2046 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
2047 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
8c99e7b0 2048 if (vars->line_speed == SPEED_10000)
ea4e040a
YR		 2049 reg_val |=
2050 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
8c99e7b0 2051 if (vars->line_speed == SPEED_13000)
ea4e040a
YR		 2052 reg_val |=
2053 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G;
8c99e7b0
YR		 2054 }
2055
cd2be89b 2056 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 2057 MDIO_REG_BANK_SERDES_DIGITAL,
2058 MDIO_SERDES_DIGITAL_MISC1, reg_val);
8c99e7b0 2059
ea4e040a
YR		 2060}
2061
e10bc84d
YR		 2062static void bnx2x_set_brcm_cl37_advertisment(struct bnx2x_phy *phy,
2063 struct link_params *params)
ea4e040a
YR		 2064{
2065 struct bnx2x *bp = params->bp;
2066 u16 val = 0;
2067
2068 /* configure the 48 bits for BAM AN */
2069
2070 /* set extended capabilities */
7aa0711f 2071 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
ea4e040a 2072 val |= MDIO_OVER_1G_UP1_2_5G;
7aa0711f 2073 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
ea4e040a 2074 val |= MDIO_OVER_1G_UP1_10G;
cd2be89b 2075 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 2076 MDIO_REG_BANK_OVER_1G,
2077 MDIO_OVER_1G_UP1, val);
ea4e040a 2078
cd2be89b 2079 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 2080 MDIO_REG_BANK_OVER_1G,
2081 MDIO_OVER_1G_UP3, 0x400);
ea4e040a
YR		 2082}
2083
e10bc84d
YR		 2084static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
2085 struct link_params *params, u16 *ieee_fc)
ea4e040a 2086{
d5cb9e99 2087 struct bnx2x *bp = params->bp;
8c99e7b0 2088 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
2cf7acf9
YR		 2089 /*
2090 * Resolve pause mode and advertisement.
2091 * Please refer to Table 28B-3 of the 802.3ab-1999 spec
2092 */
ea4e040a 2093
7aa0711f 2094 switch (phy->req_flow_ctrl) {
c0700f90 2095 case BNX2X_FLOW_CTRL_AUTO:
cd88ccee
YR		 2096 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH)
2097 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
2098 else
8c99e7b0 2099 *ieee_fc |=
cd88ccee 2100 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
ea4e040a 2101 break;
c0700f90 2102 case BNX2X_FLOW_CTRL_TX:
cd88ccee 2103 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
ea4e040a
YR		 2104 break;
2105
c0700f90
DM		 2106 case BNX2X_FLOW_CTRL_RX:
2107 case BNX2X_FLOW_CTRL_BOTH:
8c99e7b0 2108 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
ea4e040a
YR		 2109 break;
2110
c0700f90 2111 case BNX2X_FLOW_CTRL_NONE:
ea4e040a 2112 default:
8c99e7b0 2113 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
ea4e040a
YR		 2114 break;
2115 }
d5cb9e99 2116 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
8c99e7b0 2117}
ea4e040a 2118
e10bc84d
YR		 2119static void bnx2x_set_ieee_aneg_advertisment(struct bnx2x_phy *phy,
2120 struct link_params *params,
cd88ccee 2121 u16 ieee_fc)
8c99e7b0
YR		 2122{
2123 struct bnx2x *bp = params->bp;
7846e471 2124 u16 val;
8c99e7b0 2125 /* for AN, we are always publishing full duplex */
ea4e040a 2126
cd2be89b 2127 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 2128 MDIO_REG_BANK_COMBO_IEEE0,
2129 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
cd2be89b 2130 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2131 MDIO_REG_BANK_CL73_IEEEB1,
2132 MDIO_CL73_IEEEB1_AN_ADV1, &val);
7846e471
YR		 2133 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
2134 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
cd2be89b 2135 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 2136 MDIO_REG_BANK_CL73_IEEEB1,
2137 MDIO_CL73_IEEEB1_AN_ADV1, val);
ea4e040a
YR		 2138}
2139
e10bc84d
YR		 2140static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
2141 struct link_params *params,
2142 u8 enable_cl73)
ea4e040a
YR		 2143{
2144 struct bnx2x *bp = params->bp;
3a36f2ef 2145 u16 mii_control;
239d686d 2146
ea4e040a 2147 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
3a36f2ef 2148 /* Enable and restart BAM/CL37 aneg */
ea4e040a 2149
239d686d 2150 if (enable_cl73) {
cd2be89b 2151 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2152 MDIO_REG_BANK_CL73_IEEEB0,
2153 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2154 &mii_control);
239d686d 2155
cd2be89b 2156 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 2157 MDIO_REG_BANK_CL73_IEEEB0,
2158 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2159 (mii_control |
2160 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
2161 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
239d686d
EG		 2162 } else {
2163
cd2be89b 2164 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2165 MDIO_REG_BANK_COMBO_IEEE0,
2166 MDIO_COMBO_IEEE0_MII_CONTROL,
2167 &mii_control);
239d686d
EG		 2168 DP(NETIF_MSG_LINK,
2169 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
2170 mii_control);
cd2be89b 2171 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 2172 MDIO_REG_BANK_COMBO_IEEE0,
2173 MDIO_COMBO_IEEE0_MII_CONTROL,
2174 (mii_control |
2175 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2176 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
239d686d 2177 }
ea4e040a
YR		 2178}
2179
e10bc84d
YR		 2180static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
2181 struct link_params *params,
cd88ccee 2182 struct link_vars *vars)
ea4e040a
YR		 2183{
2184 struct bnx2x *bp = params->bp;
2185 u16 control1;
2186
2187 /* in SGMII mode, the unicore is always slave */
2188
cd2be89b 2189 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2190 MDIO_REG_BANK_SERDES_DIGITAL,
2191 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
2192 &control1);
ea4e040a
YR		 2193 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
2194 /* set sgmii mode (and not fiber) */
2195 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
2196 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
2197 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
cd2be89b 2198 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 2199 MDIO_REG_BANK_SERDES_DIGITAL,
2200 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
2201 control1);
ea4e040a
YR		 2202
2203 /* if forced speed */
8c99e7b0 2204 if (!(vars->line_speed == SPEED_AUTO_NEG)) {
ea4e040a
YR		 2205 /* set speed, disable autoneg */
2206 u16 mii_control;
2207
cd2be89b 2208 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2209 MDIO_REG_BANK_COMBO_IEEE0,
2210 MDIO_COMBO_IEEE0_MII_CONTROL,
2211 &mii_control);
ea4e040a
YR		 2212 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2213 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
2214 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
2215
8c99e7b0 2216 switch (vars->line_speed) {
ea4e040a
YR		 2217 case SPEED_100:
2218 mii_control |=
2219 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
2220 break;
2221 case SPEED_1000:
2222 mii_control |=
2223 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
2224 break;
2225 case SPEED_10:
2226 /* there is nothing to set for 10M */
2227 break;
2228 default:
2229 /* invalid speed for SGMII */
8c99e7b0
YR		 2230 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2231 vars->line_speed);
ea4e040a
YR		 2232 break;
2233 }
2234
2235 /* setting the full duplex */
7aa0711f 2236 if (phy->req_duplex == DUPLEX_FULL)
ea4e040a
YR		 2237 mii_control |=
2238 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
cd2be89b 2239 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 2240 MDIO_REG_BANK_COMBO_IEEE0,
2241 MDIO_COMBO_IEEE0_MII_CONTROL,
2242 mii_control);
ea4e040a
YR		 2243
2244 } else { /* AN mode */
2245 /* enable and restart AN */
e10bc84d 2246 bnx2x_restart_autoneg(phy, params, 0);
ea4e040a
YR		 2247 }
2248}
2249
2250
2251/*
2252 * link management
2253 */
2254
2255static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
8c99e7b0 2256{ /* LD LP */
cd88ccee
YR		 2257 switch (pause_result) { /* ASYM P ASYM P */
2258 case 0xb: /* 1 0 1 1 */
c0700f90 2259 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
ea4e040a
YR		 2260 break;
2261
cd88ccee 2262 case 0xe: /* 1 1 1 0 */
c0700f90 2263 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
ea4e040a
YR		 2264 break;
2265
cd88ccee
YR		 2266 case 0x5: /* 0 1 0 1 */
2267 case 0x7: /* 0 1 1 1 */
2268 case 0xd: /* 1 1 0 1 */
2269 case 0xf: /* 1 1 1 1 */
c0700f90 2270 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
ea4e040a
YR		 2271 break;
2272
2273 default:
2274 break;
2275 }
7aa0711f
YR		 2276 if (pause_result & (1<<0))
2277 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
2278 if (pause_result & (1<<1))
2279 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
ea4e040a
YR		 2280}
2281
e10bc84d
YR		 2282static u8 bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
2283 struct link_params *params)
15ddd2d0
YR		 2284{
2285 struct bnx2x *bp = params->bp;
2286 u16 pd_10g, status2_1000x;
7aa0711f
YR		 2287 if (phy->req_line_speed != SPEED_AUTO_NEG)
2288 return 0;
cd2be89b 2289 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2290 MDIO_REG_BANK_SERDES_DIGITAL,
2291 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
2292 &status2_1000x);
cd2be89b 2293 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2294 MDIO_REG_BANK_SERDES_DIGITAL,
2295 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
2296 &status2_1000x);
15ddd2d0
YR		 2297 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
2298 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
2299 params->port);
2300 return 1;
2301 }
2302
cd2be89b 2303 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2304 MDIO_REG_BANK_10G_PARALLEL_DETECT,
2305 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
2306 &pd_10g);
15ddd2d0
YR		 2307
2308 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
2309 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
2310 params->port);
2311 return 1;
2312 }
2313 return 0;
2314}
ea4e040a 2315
e10bc84d
YR		 2316static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
2317 struct link_params *params,
2318 struct link_vars *vars,
2319 u32 gp_status)
ea4e040a
YR		 2320{
2321 struct bnx2x *bp = params->bp;
3196a88a
EG		 2322 u16 ld_pause; /* local driver */
2323 u16 lp_pause; /* link partner */
ea4e040a
YR		 2324 u16 pause_result;
2325
c0700f90 2326 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a
YR		 2327
2328 /* resolve from gp_status in case of AN complete and not sgmii */
7aa0711f
YR		 2329 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
2330 vars->flow_ctrl = phy->req_flow_ctrl;
2331 else if (phy->req_line_speed != SPEED_AUTO_NEG)
2332 vars->flow_ctrl = params->req_fc_auto_adv;
2333 else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
2334 (!(vars->phy_flags & PHY_SGMII_FLAG))) {
e10bc84d 2335 if (bnx2x_direct_parallel_detect_used(phy, params)) {
15ddd2d0
YR		 2336 vars->flow_ctrl = params->req_fc_auto_adv;
2337 return;
2338 }
7846e471
YR		 2339 if ((gp_status &
2340 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
2341 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
2342 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
2343 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
2344
cd2be89b 2345 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2346 MDIO_REG_BANK_CL73_IEEEB1,
2347 MDIO_CL73_IEEEB1_AN_ADV1,
2348 &ld_pause);
cd2be89b 2349 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2350 MDIO_REG_BANK_CL73_IEEEB1,
2351 MDIO_CL73_IEEEB1_AN_LP_ADV1,
2352 &lp_pause);
7846e471
YR		 2353 pause_result = (ld_pause &
2354 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK)
2355 >> 8;
2356 pause_result |= (lp_pause &
2357 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK)
2358 >> 10;
2359 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n",
2360 pause_result);
2361 } else {
cd2be89b 2362 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2363 MDIO_REG_BANK_COMBO_IEEE0,
2364 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
2365 &ld_pause);
cd2be89b 2366 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2367 MDIO_REG_BANK_COMBO_IEEE0,
2368 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
2369 &lp_pause);
7846e471 2370 pause_result = (ld_pause &
ea4e040a 2371 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
7846e471 2372 pause_result |= (lp_pause &
cd88ccee 2373 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
7846e471
YR		 2374 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n",
2375 pause_result);
2376 }
ea4e040a 2377 bnx2x_pause_resolve(vars, pause_result);
ea4e040a
YR		 2378 }
2379 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
2380}
2381
e10bc84d
YR		 2382static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
2383 struct link_params *params)
239d686d
EG		 2384{
2385 struct bnx2x *bp = params->bp;
2386 u16 rx_status, ustat_val, cl37_fsm_recieved;
2387 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
2388 /* Step 1: Make sure signal is detected */
cd2be89b 2389 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2390 MDIO_REG_BANK_RX0,
2391 MDIO_RX0_RX_STATUS,
2392 &rx_status);
239d686d
EG		 2393 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
2394 (MDIO_RX0_RX_STATUS_SIGDET)) {
2395 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
2396 "rx_status(0x80b0) = 0x%x\n", rx_status);
cd2be89b 2397 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 2398 MDIO_REG_BANK_CL73_IEEEB0,
2399 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2400 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
239d686d
EG		 2401 return;
2402 }
2403 /* Step 2: Check CL73 state machine */
cd2be89b 2404 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2405 MDIO_REG_BANK_CL73_USERB0,
2406 MDIO_CL73_USERB0_CL73_USTAT1,
2407 &ustat_val);
239d686d
EG		 2408 if ((ustat_val &
2409 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
2410 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
2411 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
2412 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
2413 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
2414 "ustat_val(0x8371) = 0x%x\n", ustat_val);
2415 return;
2416 }
2cf7acf9
YR		 2417 /*
2418 * Step 3: Check CL37 Message Pages received to indicate LP
2419 * supports only CL37
2420 */
cd2be89b 2421 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2422 MDIO_REG_BANK_REMOTE_PHY,
2423 MDIO_REMOTE_PHY_MISC_RX_STATUS,
2424 &cl37_fsm_recieved);
239d686d
EG		 2425 if ((cl37_fsm_recieved &
2426 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
2427 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
2428 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
2429 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
2430 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
2431 "misc_rx_status(0x8330) = 0x%x\n",
2432 cl37_fsm_recieved);
2433 return;
2434 }
2cf7acf9
YR		 2435 /*
2436 * The combined cl37/cl73 fsm state information indicating that
2437 * we are connected to a device which does not support cl73, but
2438 * does support cl37 BAM. In this case we disable cl73 and
2439 * restart cl37 auto-neg
2440 */
2441
239d686d 2442 /* Disable CL73 */
cd2be89b 2443 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 2444 MDIO_REG_BANK_CL73_IEEEB0,
2445 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2446 0);
239d686d 2447 /* Restart CL37 autoneg */
e10bc84d 2448 bnx2x_restart_autoneg(phy, params, 0);
239d686d
EG		 2449 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
2450}
7aa0711f
YR		 2451
2452static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
2453 struct link_params *params,
2454 struct link_vars *vars,
2455 u32 gp_status)
2456{
2457 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
2458 vars->link_status |=
2459 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
2460
2461 if (bnx2x_direct_parallel_detect_used(phy, params))
2462 vars->link_status |=
2463 LINK_STATUS_PARALLEL_DETECTION_USED;
2464}
2465
b7737c9b
YR		 2466static u8 bnx2x_link_settings_status(struct bnx2x_phy *phy,
2467 struct link_params *params,
2468 struct link_vars *vars)
ea4e040a
YR		 2469{
2470 struct bnx2x *bp = params->bp;
cd88ccee 2471 u16 new_line_speed, gp_status;
ea4e040a 2472 u8 rc = 0;
c18aa15d 2473
b7737c9b 2474 /* Read gp_status */
cd2be89b 2475 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2476 MDIO_REG_BANK_GP_STATUS,
2477 MDIO_GP_STATUS_TOP_AN_STATUS1,
2478 &gp_status);
7f02c4ad 2479
7aa0711f
YR		 2480 if (phy->req_line_speed == SPEED_AUTO_NEG)
2481 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
ea4e040a
YR		 2482 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
2483 DP(NETIF_MSG_LINK, "phy link up gp_status=0x%x\n",
2484 gp_status);
2485
2486 vars->phy_link_up = 1;
2487 vars->link_status |= LINK_STATUS_LINK_UP;
2488
2489 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
2490 vars->duplex = DUPLEX_FULL;
2491 else
2492 vars->duplex = DUPLEX_HALF;
2493
7aa0711f
YR		 2494 if (SINGLE_MEDIA_DIRECT(params)) {
2495 bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
2496 if (phy->req_line_speed == SPEED_AUTO_NEG)
2497 bnx2x_xgxs_an_resolve(phy, params, vars,
2498 gp_status);
2499 }
ea4e040a
YR		 2500
2501 switch (gp_status & GP_STATUS_SPEED_MASK) {
2502 case GP_STATUS_10M:
6c55c3cd 2503 new_line_speed = SPEED_10;
ea4e040a
YR		 2504 if (vars->duplex == DUPLEX_FULL)
2505 vars->link_status |= LINK_10TFD;
2506 else
2507 vars->link_status |= LINK_10THD;
2508 break;
2509
2510 case GP_STATUS_100M:
6c55c3cd 2511 new_line_speed = SPEED_100;
ea4e040a
YR		 2512 if (vars->duplex == DUPLEX_FULL)
2513 vars->link_status |= LINK_100TXFD;
2514 else
2515 vars->link_status |= LINK_100TXHD;
2516 break;
2517
2518 case GP_STATUS_1G:
2519 case GP_STATUS_1G_KX:
6c55c3cd 2520 new_line_speed = SPEED_1000;
ea4e040a
YR		 2521 if (vars->duplex == DUPLEX_FULL)
2522 vars->link_status |= LINK_1000TFD;
2523 else
2524 vars->link_status |= LINK_1000THD;
2525 break;
2526
2527 case GP_STATUS_2_5G:
6c55c3cd 2528 new_line_speed = SPEED_2500;
ea4e040a
YR		 2529 if (vars->duplex == DUPLEX_FULL)
2530 vars->link_status |= LINK_2500TFD;
2531 else
2532 vars->link_status |= LINK_2500THD;
2533 break;
2534
2535 case GP_STATUS_5G:
2536 case GP_STATUS_6G:
2537 DP(NETIF_MSG_LINK,
2538 "link speed unsupported gp_status 0x%x\n",
2539 gp_status);
2540 return -EINVAL;
ab6ad5a4 2541
ea4e040a
YR		 2542 case GP_STATUS_10G_KX4:
2543 case GP_STATUS_10G_HIG:
2544 case GP_STATUS_10G_CX4:
6c55c3cd 2545 new_line_speed = SPEED_10000;
ea4e040a
YR		 2546 vars->link_status |= LINK_10GTFD;
2547 break;
2548
2549 case GP_STATUS_12G_HIG:
6c55c3cd 2550 new_line_speed = SPEED_12000;
ea4e040a
YR		 2551 vars->link_status |= LINK_12GTFD;
2552 break;
2553
2554 case GP_STATUS_12_5G:
6c55c3cd 2555 new_line_speed = SPEED_12500;
ea4e040a
YR		 2556 vars->link_status |= LINK_12_5GTFD;
2557 break;
2558
2559 case GP_STATUS_13G:
6c55c3cd 2560 new_line_speed = SPEED_13000;
ea4e040a
YR		 2561 vars->link_status |= LINK_13GTFD;
2562 break;
2563
2564 case GP_STATUS_15G:
6c55c3cd 2565 new_line_speed = SPEED_15000;
ea4e040a
YR		 2566 vars->link_status |= LINK_15GTFD;
2567 break;
2568
2569 case GP_STATUS_16G:
6c55c3cd 2570 new_line_speed = SPEED_16000;
ea4e040a
YR		 2571 vars->link_status |= LINK_16GTFD;
2572 break;
2573
2574 default:
2575 DP(NETIF_MSG_LINK,
2576 "link speed unsupported gp_status 0x%x\n",
2577 gp_status);
ab6ad5a4 2578 return -EINVAL;
ea4e040a
YR		 2579 }
2580
6c55c3cd 2581 vars->line_speed = new_line_speed;
ea4e040a 2582
ea4e040a
YR		 2583 } else { /* link_down */
2584 DP(NETIF_MSG_LINK, "phy link down\n");
2585
2586 vars->phy_link_up = 0;
57963ed9 2587
ea4e040a 2588 vars->duplex = DUPLEX_FULL;
c0700f90 2589 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a 2590 vars->mac_type = MAC_TYPE_NONE;
239d686d 2591
c18aa15d
YR		 2592 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
2593 SINGLE_MEDIA_DIRECT(params)) {
239d686d 2594 /* Check signal is detected */
c18aa15d 2595 bnx2x_check_fallback_to_cl37(phy, params);
239d686d 2596 }
ea4e040a
YR		 2597 }
2598
2381a55c 2599 DP(NETIF_MSG_LINK, "gp_status 0x%x phy_link_up %x line_speed %x\n",
ea4e040a 2600 gp_status, vars->phy_link_up, vars->line_speed);
a22f0788
YR		 2601 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
2602 vars->duplex, vars->flow_ctrl, vars->link_status);
ea4e040a
YR		 2603 return rc;
2604}
2605
ed8680a7 2606static void bnx2x_set_gmii_tx_driver(struct link_params *params)
ea4e040a
YR		 2607{
2608 struct bnx2x *bp = params->bp;
e10bc84d 2609 struct bnx2x_phy *phy = &params->phy[INT_PHY];
ea4e040a
YR		 2610 u16 lp_up2;
2611 u16 tx_driver;
c2c8b03e 2612 u16 bank;
ea4e040a
YR		 2613
2614 /* read precomp */
cd2be89b 2615 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2616 MDIO_REG_BANK_OVER_1G,
2617 MDIO_OVER_1G_LP_UP2, &lp_up2);
ea4e040a 2618
ea4e040a
YR		 2619 /* bits [10:7] at lp_up2, positioned at [15:12] */
2620 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
2621 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
2622 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
2623
c2c8b03e
EG		 2624 if (lp_up2 == 0)
2625 return;
2626
2627 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
2628 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
cd2be89b 2629 CL22_RD_OVER_CL45(bp, phy,
cd88ccee
YR		 2630 bank,
2631 MDIO_TX0_TX_DRIVER, &tx_driver);
c2c8b03e
EG		 2632
2633 /* replace tx_driver bits [15:12] */
2634 if (lp_up2 !=
2635 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
2636 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
2637 tx_driver |= lp_up2;
cd2be89b 2638 CL22_WR_OVER_CL45(bp, phy,
cd88ccee
YR		 2639 bank,
2640 MDIO_TX0_TX_DRIVER, tx_driver);
c2c8b03e 2641 }
ea4e040a
YR		 2642 }
2643}
2644
2645static u8 bnx2x_emac_program(struct link_params *params,
b7737c9b 2646 struct link_vars *vars)
ea4e040a
YR		 2647{
2648 struct bnx2x *bp = params->bp;
2649 u8 port = params->port;
2650 u16 mode = 0;
2651
2652 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
2653 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
cd88ccee
YR		 2654 EMAC_REG_EMAC_MODE,
2655 (EMAC_MODE_25G_MODE |
2656 EMAC_MODE_PORT_MII_10M |
2657 EMAC_MODE_HALF_DUPLEX));
b7737c9b 2658 switch (vars->line_speed) {
ea4e040a
YR		 2659 case SPEED_10:
2660 mode |= EMAC_MODE_PORT_MII_10M;
2661 break;
2662
2663 case SPEED_100:
2664 mode |= EMAC_MODE_PORT_MII;
2665 break;
2666
2667 case SPEED_1000:
2668 mode |= EMAC_MODE_PORT_GMII;
2669 break;
2670
2671 case SPEED_2500:
2672 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
2673 break;
2674
2675 default:
2676 /* 10G not valid for EMAC */
b7737c9b
YR		 2677 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2678 vars->line_speed);
ea4e040a
YR		 2679 return -EINVAL;
2680 }
2681
b7737c9b 2682 if (vars->duplex == DUPLEX_HALF)
ea4e040a
YR		 2683 mode |= EMAC_MODE_HALF_DUPLEX;
2684 bnx2x_bits_en(bp,
cd88ccee
YR		 2685 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
2686 mode);
ea4e040a 2687
7f02c4ad 2688 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
ea4e040a
YR		 2689 return 0;
2690}
2691
de6eae1f
YR		 2692static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
2693 struct link_params *params)
b7737c9b 2694{
de6eae1f
YR		 2695
2696 u16 bank, i = 0;
2697 struct bnx2x *bp = params->bp;
2698
2699 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
2700 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
cd2be89b 2701 CL22_WR_OVER_CL45(bp, phy,
de6eae1f
YR		 2702 bank,
2703 MDIO_RX0_RX_EQ_BOOST,
2704 phy->rx_preemphasis[i]);
2705 }
2706
2707 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
2708 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
cd2be89b 2709 CL22_WR_OVER_CL45(bp, phy,
de6eae1f
YR		 2710 bank,
2711 MDIO_TX0_TX_DRIVER,
2712 phy->tx_preemphasis[i]);
2713 }
2714}
2715
2716static void bnx2x_init_internal_phy(struct bnx2x_phy *phy,
2717 struct link_params *params,
2718 struct link_vars *vars)
2719{
2720 struct bnx2x *bp = params->bp;
2721 u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
2722 (params->loopback_mode == LOOPBACK_XGXS));
2723 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
2724 if (SINGLE_MEDIA_DIRECT(params) &&
2725 (params->feature_config_flags &
2726 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
2727 bnx2x_set_preemphasis(phy, params);
2728
2729 /* forced speed requested? */
2730 if (vars->line_speed != SPEED_AUTO_NEG ||
2731 (SINGLE_MEDIA_DIRECT(params) &&
cd88ccee 2732 params->loopback_mode == LOOPBACK_EXT)) {
de6eae1f
YR		 2733 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
2734
2735 /* disable autoneg */
2736 bnx2x_set_autoneg(phy, params, vars, 0);
2737
2738 /* program speed and duplex */
2739 bnx2x_program_serdes(phy, params, vars);
2740
2741 } else { /* AN_mode */
2742 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
2743
2744 /* AN enabled */
2745 bnx2x_set_brcm_cl37_advertisment(phy, params);
2746
2747 /* program duplex & pause advertisement (for aneg) */
2748 bnx2x_set_ieee_aneg_advertisment(phy, params,
cd88ccee 2749 vars->ieee_fc);
de6eae1f
YR		 2750
2751 /* enable autoneg */
2752 bnx2x_set_autoneg(phy, params, vars, enable_cl73);
2753
2754 /* enable and restart AN */
2755 bnx2x_restart_autoneg(phy, params, enable_cl73);
2756 }
2757
2758 } else { /* SGMII mode */
2759 DP(NETIF_MSG_LINK, "SGMII\n");
2760
2761 bnx2x_initialize_sgmii_process(phy, params, vars);
2762 }
2763}
2764
2765static u8 bnx2x_init_serdes(struct bnx2x_phy *phy,
2766 struct link_params *params,
2767 struct link_vars *vars)
2768{
2769 u8 rc;
2770 vars->phy_flags |= PHY_SGMII_FLAG;
b7737c9b 2771 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
f2e0899f 2772 bnx2x_set_aer_mmd_serdes(params->bp, phy);
b7737c9b
YR		 2773 rc = bnx2x_reset_unicore(params, phy, 1);
2774 /* reset the SerDes and wait for reset bit return low */
2775 if (rc != 0)
2776 return rc;
f2e0899f 2777 bnx2x_set_aer_mmd_serdes(params->bp, phy);
b7737c9b
YR		 2778
2779 return rc;
2780}
2781
2782static u8 bnx2x_init_xgxs(struct bnx2x_phy *phy,
2783 struct link_params *params,
2784 struct link_vars *vars)
2785{
2786 u8 rc;
2787 vars->phy_flags = PHY_XGXS_FLAG;
2788 if ((phy->req_line_speed &&
2789 ((phy->req_line_speed == SPEED_100) ||
2790 (phy->req_line_speed == SPEED_10))) ||
2791 (!phy->req_line_speed &&
2792 (phy->speed_cap_mask >=
2793 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
2794 (phy->speed_cap_mask <
2795 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
2796 ))
2797 vars->phy_flags |= PHY_SGMII_FLAG;
2798 else
2799 vars->phy_flags &= ~PHY_SGMII_FLAG;
2800
2801 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
f2e0899f 2802 bnx2x_set_aer_mmd_xgxs(params, phy);
b7737c9b
YR		 2803 bnx2x_set_master_ln(params, phy);
2804
2805 rc = bnx2x_reset_unicore(params, phy, 0);
2806 /* reset the SerDes and wait for reset bit return low */
2807 if (rc != 0)
2808 return rc;
2809
f2e0899f 2810 bnx2x_set_aer_mmd_xgxs(params, phy);
e10bc84d 2811
b7737c9b
YR		 2812 /* setting the masterLn_def again after the reset */
2813 bnx2x_set_master_ln(params, phy);
2814 bnx2x_set_swap_lanes(params, phy);
2815
2816 return rc;
2817}
c18aa15d 2818
de6eae1f 2819static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
6d870c39
YR		 2820 struct bnx2x_phy *phy,
2821 struct link_params *params)
ea4e040a 2822{
de6eae1f 2823 u16 cnt, ctrl;
25985edc 2824 /* Wait for soft reset to get cleared up to 1 sec */
de6eae1f
YR		 2825 for (cnt = 0; cnt < 1000; cnt++) {
2826 bnx2x_cl45_read(bp, phy,
2827 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, &ctrl);
2828 if (!(ctrl & (1<<15)))
2829 break;
2830 msleep(1);
2831 }
6d870c39
YR		 2832
2833 if (cnt == 1000)
2834 netdev_err(bp->dev, "Warning: PHY was not initialized,"
2835 " Port %d\n",
2836 params->port);
de6eae1f
YR		 2837 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
2838 return cnt;
ea4e040a
YR		 2839}
2840
de6eae1f 2841static void bnx2x_link_int_enable(struct link_params *params)
a35da8db 2842{
de6eae1f
YR		 2843 u8 port = params->port;
2844 u32 mask;
2845 struct bnx2x *bp = params->bp;
c18aa15d 2846
2cf7acf9 2847 /* Setting the status to report on link up for either XGXS or SerDes */
de6eae1f
YR		 2848 if (params->switch_cfg == SWITCH_CFG_10G) {
2849 mask = (NIG_MASK_XGXS0_LINK10G |
2850 NIG_MASK_XGXS0_LINK_STATUS);
2851 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
2852 if (!(SINGLE_MEDIA_DIRECT(params)) &&
2853 params->phy[INT_PHY].type !=
2854 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
2855 mask |= NIG_MASK_MI_INT;
2856 DP(NETIF_MSG_LINK, "enabled external phy int\n");
2857 }
2858
2859 } else { /* SerDes */
2860 mask = NIG_MASK_SERDES0_LINK_STATUS;
2861 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
2862 if (!(SINGLE_MEDIA_DIRECT(params)) &&
2863 params->phy[INT_PHY].type !=
2864 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
2865 mask |= NIG_MASK_MI_INT;
2866 DP(NETIF_MSG_LINK, "enabled external phy int\n");
2867 }
2868 }
2869 bnx2x_bits_en(bp,
2870 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
2871 mask);
2872
2873 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
2874 (params->switch_cfg == SWITCH_CFG_10G),
2875 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
2876 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
2877 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
2878 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
2879 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
2880 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
2881 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
2882 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
a35da8db
EG		 2883}
2884
a22f0788
YR		 2885static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
2886 u8 exp_mi_int)
a35da8db 2887{
a22f0788
YR		 2888 u32 latch_status = 0;
2889
2cf7acf9 2890 /*
a22f0788
YR		 2891 * Disable the MI INT ( external phy int ) by writing 1 to the
2892 * status register. Link down indication is high-active-signal,
2893 * so in this case we need to write the status to clear the XOR
de6eae1f
YR		 2894 */
2895 /* Read Latched signals */
2896 latch_status = REG_RD(bp,
a22f0788
YR		 2897 NIG_REG_LATCH_STATUS_0 + port*8);
2898 DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
de6eae1f 2899 /* Handle only those with latched-signal=up.*/
a22f0788
YR		 2900 if (exp_mi_int)
2901 bnx2x_bits_en(bp,
2902 NIG_REG_STATUS_INTERRUPT_PORT0
2903 + port*4,
2904 NIG_STATUS_EMAC0_MI_INT);
2905 else
2906 bnx2x_bits_dis(bp,
2907 NIG_REG_STATUS_INTERRUPT_PORT0
2908 + port*4,
2909 NIG_STATUS_EMAC0_MI_INT);
2910
de6eae1f 2911 if (latch_status & 1) {
a22f0788 2912
de6eae1f
YR		 2913 /* For all latched-signal=up : Re-Arm Latch signals */
2914 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
cd88ccee 2915 (latch_status & 0xfffe) | (latch_status & 1));
de6eae1f 2916 }
a22f0788 2917 /* For all latched-signal=up,Write original_signal to status */
a35da8db
EG		 2918}
2919
de6eae1f 2920static void bnx2x_link_int_ack(struct link_params *params,
cd88ccee 2921 struct link_vars *vars, u8 is_10g)
b1607af5 2922{
e10bc84d 2923 struct bnx2x *bp = params->bp;
de6eae1f 2924 u8 port = params->port;
e10bc84d 2925
2cf7acf9
YR		 2926 /*
2927 * First reset all status we assume only one line will be
2928 * change at a time
2929 */
de6eae1f 2930 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
cd88ccee
YR		 2931 (NIG_STATUS_XGXS0_LINK10G |
2932 NIG_STATUS_XGXS0_LINK_STATUS |
2933 NIG_STATUS_SERDES0_LINK_STATUS));
de6eae1f
YR		 2934 if (vars->phy_link_up) {
2935 if (is_10g) {
2cf7acf9
YR		 2936 /*
2937 * Disable the 10G link interrupt by writing 1 to the
2938 * status register
de6eae1f
YR		 2939 */
2940 DP(NETIF_MSG_LINK, "10G XGXS phy link up\n");
2941 bnx2x_bits_en(bp,
2942 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2943 NIG_STATUS_XGXS0_LINK10G);
b1607af5 2944
de6eae1f 2945 } else if (params->switch_cfg == SWITCH_CFG_10G) {
2cf7acf9
YR		 2946 /*
2947 * Disable the link interrupt by writing 1 to the
2948 * relevant lane in the status register
de6eae1f
YR		 2949 */
2950 u32 ser_lane = ((params->lane_config &
2951 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
2952 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
b1607af5 2953
de6eae1f
YR		 2954 DP(NETIF_MSG_LINK, "%d speed XGXS phy link up\n",
2955 vars->line_speed);
2956 bnx2x_bits_en(bp,
2957 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2958 ((1 << ser_lane) <<
2959 NIG_STATUS_XGXS0_LINK_STATUS_SIZE));
ea4e040a 2960
de6eae1f
YR		 2961 } else { /* SerDes */
2962 DP(NETIF_MSG_LINK, "SerDes phy link up\n");
2cf7acf9
YR		 2963 /*
2964 * Disable the link interrupt by writing 1 to the status
2965 * register
de6eae1f
YR		 2966 */
2967 bnx2x_bits_en(bp,
2968 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2969 NIG_STATUS_SERDES0_LINK_STATUS);
2970 }
ea4e040a 2971
ea4e040a 2972 }
ea4e040a 2973}
ea4e040a 2974
de6eae1f
YR		 2975static u8 bnx2x_format_ver(u32 num, u8 *str, u16 *len)
2976{
2977 u8 *str_ptr = str;
2978 u32 mask = 0xf0000000;
2979 u8 shift = 8*4;
2980 u8 digit;
a22f0788 2981 u8 remove_leading_zeros = 1;
de6eae1f
YR		 2982 if (*len < 10) {
2983 /* Need more than 10chars for this format */
2984 *str_ptr = '\0';
a22f0788 2985 (*len)--;
de6eae1f 2986 return -EINVAL;
ea4e040a 2987 }
de6eae1f 2988 while (shift > 0) {
ea4e040a 2989
de6eae1f
YR		 2990 shift -= 4;
2991 digit = ((num & mask) >> shift);
a22f0788
YR		 2992 if (digit == 0 && remove_leading_zeros) {
2993 mask = mask >> 4;
2994 continue;
2995 } else if (digit < 0xa)
de6eae1f
YR		 2996 *str_ptr = digit + '0';
2997 else
2998 *str_ptr = digit - 0xa + 'a';
a22f0788 2999 remove_leading_zeros = 0;
de6eae1f 3000 str_ptr++;
a22f0788 3001 (*len)--;
de6eae1f
YR		 3002 mask = mask >> 4;
3003 if (shift == 4*4) {
a22f0788 3004 *str_ptr = '.';
de6eae1f 3005 str_ptr++;
a22f0788
YR		 3006 (*len)--;
3007 remove_leading_zeros = 1;
ea4e040a 3008 }
ea4e040a 3009 }
de6eae1f 3010 return 0;
ea4e040a
YR		 3011}
3012
a22f0788 3013
de6eae1f 3014static u8 bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
ea4e040a 3015{
de6eae1f
YR		 3016 str[0] = '\0';
3017 (*len)--;
3018 return 0;
3019}
ea4e040a 3020
de6eae1f
YR		 3021u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
3022 u8 *version, u16 len)
3023{
3024 struct bnx2x *bp;
3025 u32 spirom_ver = 0;
3026 u8 status = 0;
3027 u8 *ver_p = version;
a22f0788 3028 u16 remain_len = len;
de6eae1f
YR		 3029 if (version == NULL || params == NULL)
3030 return -EINVAL;
3031 bp = params->bp;
ea4e040a 3032
de6eae1f
YR		 3033 /* Extract first external phy*/
3034 version[0] = '\0';
3035 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
ea4e040a 3036
a22f0788 3037 if (params->phy[EXT_PHY1].format_fw_ver) {
de6eae1f
YR		 3038 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
3039 ver_p,
a22f0788
YR		 3040 &remain_len);
3041 ver_p += (len - remain_len);
3042 }
3043 if ((params->num_phys == MAX_PHYS) &&
3044 (params->phy[EXT_PHY2].ver_addr != 0)) {
cd88ccee 3045 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
a22f0788
YR		 3046 if (params->phy[EXT_PHY2].format_fw_ver) {
3047 *ver_p = '/';
3048 ver_p++;
3049 remain_len--;
3050 status |= params->phy[EXT_PHY2].format_fw_ver(
3051 spirom_ver,
3052 ver_p,
3053 &remain_len);
3054 ver_p = version + (len - remain_len);
3055 }
3056 }
3057 *ver_p = '\0';
de6eae1f 3058 return status;
6bbca910 3059}
ea4e040a 3060
de6eae1f
YR		 3061static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
3062 struct link_params *params)
589abe3a 3063{
de6eae1f 3064 u8 port = params->port;
589abe3a 3065 struct bnx2x *bp = params->bp;
589abe3a 3066
de6eae1f
YR		 3067 if (phy->req_line_speed != SPEED_1000) {
3068 u32 md_devad;
589abe3a 3069
de6eae1f 3070 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
589abe3a 3071
de6eae1f
YR		 3072 /* change the uni_phy_addr in the nig */
3073 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
cd88ccee 3074 port*0x18));
cc1cb004 3075
de6eae1f 3076 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 0x5);
589abe3a 3077
de6eae1f 3078 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 3079 5,
3080 (MDIO_REG_BANK_AER_BLOCK +
3081 (MDIO_AER_BLOCK_AER_REG & 0xf)),
3082 0x2800);
589abe3a 3083
de6eae1f 3084 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 3085 5,
3086 (MDIO_REG_BANK_CL73_IEEEB0 +
3087 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
3088 0x6041);
de6eae1f
YR		 3089 msleep(200);
3090 /* set aer mmd back */
f2e0899f 3091 bnx2x_set_aer_mmd_xgxs(params, phy);
589abe3a 3092
de6eae1f 3093 /* and md_devad */
cd88ccee 3094 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, md_devad);
de6eae1f
YR		 3095 } else {
3096 u16 mii_ctrl;
3097 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
3098 bnx2x_cl45_read(bp, phy, 5,
3099 (MDIO_REG_BANK_COMBO_IEEE0 +
3100 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
3101 &mii_ctrl);
3102 bnx2x_cl45_write(bp, phy, 5,
3103 (MDIO_REG_BANK_COMBO_IEEE0 +
3104 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
3105 mii_ctrl |
3106 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
3107 }
589abe3a
EG		 3108}
3109
7f02c4ad
YR		 3110u8 bnx2x_set_led(struct link_params *params,
3111 struct link_vars *vars, u8 mode, u32 speed)
4d295db0 3112{
de6eae1f
YR		 3113 u8 port = params->port;
3114 u16 hw_led_mode = params->hw_led_mode;
7f02c4ad 3115 u8 rc = 0, phy_idx;
de6eae1f
YR		 3116 u32 tmp;
3117 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
589abe3a 3118 struct bnx2x *bp = params->bp;
de6eae1f
YR		 3119 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
3120 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
3121 speed, hw_led_mode);
7f02c4ad
YR		 3122 /* In case */
3123 for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
3124 if (params->phy[phy_idx].set_link_led) {
3125 params->phy[phy_idx].set_link_led(
3126 &params->phy[phy_idx], params, mode);
3127 }
3128 }
3129
de6eae1f 3130 switch (mode) {
7f02c4ad 3131 case LED_MODE_FRONT_PANEL_OFF:
de6eae1f
YR		 3132 case LED_MODE_OFF:
3133 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
3134 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
cd88ccee 3135 SHARED_HW_CFG_LED_MAC1);
589abe3a 3136
de6eae1f
YR		 3137 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3138 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
3139 break;
589abe3a 3140
de6eae1f 3141 case LED_MODE_OPER:
2cf7acf9 3142 /*
7f02c4ad
YR		 3143 * For all other phys, OPER mode is same as ON, so in case
3144 * link is down, do nothing
2cf7acf9 3145 */
7f02c4ad
YR		 3146 if (!vars->link_up)
3147 break;
3148 case LED_MODE_ON:
e4d78f12
YR		 3149 if (((params->phy[EXT_PHY1].type ==
3150 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
3151 (params->phy[EXT_PHY1].type ==
3152 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
1f48353a 3153 CHIP_IS_E2(bp) && params->num_phys == 2) {
2cf7acf9
YR		 3154 /*
3155 * This is a work-around for E2+8727 Configurations
3156 */
1f48353a
YR		 3157 if (mode == LED_MODE_ON ||
3158 speed == SPEED_10000){
3159 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
3160 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
3161
3162 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3163 EMAC_WR(bp, EMAC_REG_EMAC_LED,
3164 (tmp | EMAC_LED_OVERRIDE));
3165 return rc;
3166 }
3167 } else if (SINGLE_MEDIA_DIRECT(params)) {
2cf7acf9
YR		 3168 /*
3169 * This is a work-around for HW issue found when link
3170 * is up in CL73
3171 */
de6eae1f
YR		 3172 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
3173 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
3174 } else {
cd88ccee 3175 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, hw_led_mode);
de6eae1f 3176 }
589abe3a 3177
cd88ccee 3178 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
de6eae1f
YR		 3179 /* Set blinking rate to ~15.9Hz */
3180 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
cd88ccee 3181 LED_BLINK_RATE_VAL);
de6eae1f 3182 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
cd88ccee 3183 port*4, 1);
de6eae1f 3184 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
cd88ccee 3185 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp & (~EMAC_LED_OVERRIDE)));
589abe3a 3186
de6eae1f
YR		 3187 if (CHIP_IS_E1(bp) &&
3188 ((speed == SPEED_2500) ||
3189 (speed == SPEED_1000) ||
3190 (speed == SPEED_100) ||
3191 (speed == SPEED_10))) {
2cf7acf9
YR		 3192 /*
3193 * On Everest 1 Ax chip versions for speeds less than
3194 * 10G LED scheme is different
3195 */
de6eae1f 3196 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
cd88ccee 3197 + port*4, 1);
de6eae1f 3198 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
cd88ccee 3199 port*4, 0);
de6eae1f 3200 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
cd88ccee 3201 port*4, 1);
de6eae1f
YR		 3202 }
3203 break;
589abe3a 3204
de6eae1f
YR		 3205 default:
3206 rc = -EINVAL;
3207 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
3208 mode);
3209 break;
589abe3a 3210 }
de6eae1f 3211 return rc;
589abe3a 3212
4d295db0
EG		 3213}
3214
2cf7acf9 3215/*
a22f0788
YR		 3216 * This function comes to reflect the actual link state read DIRECTLY from the
3217 * HW
3218 */
3219u8 bnx2x_test_link(struct link_params *params, struct link_vars *vars,
3220 u8 is_serdes)
4d295db0
EG		 3221{
3222 struct bnx2x *bp = params->bp;
de6eae1f 3223 u16 gp_status = 0, phy_index = 0;
a22f0788
YR		 3224 u8 ext_phy_link_up = 0, serdes_phy_type;
3225 struct link_vars temp_vars;
4d295db0 3226
cd2be89b 3227 CL22_RD_OVER_CL45(bp, &params->phy[INT_PHY],
cd88ccee
YR		 3228 MDIO_REG_BANK_GP_STATUS,
3229 MDIO_GP_STATUS_TOP_AN_STATUS1,
3230 &gp_status);
de6eae1f 3231 /* link is up only if both local phy and external phy are up */
a22f0788
YR		 3232 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
3233 return -ESRCH;
3234
3235 switch (params->num_phys) {
3236 case 1:
3237 /* No external PHY */
3238 return 0;
3239 case 2:
3240 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
3241 &params->phy[EXT_PHY1],
3242 params, &temp_vars);
3243 break;
3244 case 3: /* Dual Media */
de6eae1f
YR		 3245 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3246 phy_index++) {
a22f0788
YR		 3247 serdes_phy_type = ((params->phy[phy_index].media_type ==
3248 ETH_PHY_SFP_FIBER) ||
3249 (params->phy[phy_index].media_type ==
3250 ETH_PHY_XFP_FIBER));
3251
3252 if (is_serdes != serdes_phy_type)
3253 continue;
3254 if (params->phy[phy_index].read_status) {
3255 ext_phy_link_up |=
de6eae1f
YR		 3256 params->phy[phy_index].read_status(
3257 &params->phy[phy_index],
3258 params, &temp_vars);
a22f0788 3259 }
de6eae1f 3260 }
a22f0788 3261 break;
4d295db0 3262 }
a22f0788
YR		 3263 if (ext_phy_link_up)
3264 return 0;
de6eae1f
YR		 3265 return -ESRCH;
3266}
4d295db0 3267
de6eae1f
YR		 3268static u8 bnx2x_link_initialize(struct link_params *params,
3269 struct link_vars *vars)
3270{
3271 u8 rc = 0;
3272 u8 phy_index, non_ext_phy;
3273 struct bnx2x *bp = params->bp;
2cf7acf9
YR		 3274 /*
3275 * In case of external phy existence, the line speed would be the
3276 * line speed linked up by the external phy. In case it is direct
3277 * only, then the line_speed during initialization will be
3278 * equal to the req_line_speed
3279 */
de6eae1f 3280 vars->line_speed = params->phy[INT_PHY].req_line_speed;
4d295db0 3281
2cf7acf9 3282 /*
de6eae1f
YR		 3283 * Initialize the internal phy in case this is a direct board
3284 * (no external phys), or this board has external phy which requires
3285 * to first.
3286 */
4d295db0 3287
de6eae1f
YR		 3288 if (params->phy[INT_PHY].config_init)
3289 params->phy[INT_PHY].config_init(
3290 &params->phy[INT_PHY],
3291 params, vars);
4d295db0 3292
de6eae1f
YR		 3293 /* init ext phy and enable link state int */
3294 non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
3295 (params->loopback_mode == LOOPBACK_XGXS));
4d295db0 3296
de6eae1f
YR		 3297 if (non_ext_phy ||
3298 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
3299 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
3300 struct bnx2x_phy *phy = &params->phy[INT_PHY];
3301 if (vars->line_speed == SPEED_AUTO_NEG)
3302 bnx2x_set_parallel_detection(phy, params);
3303 bnx2x_init_internal_phy(phy, params, vars);
4d295db0
EG		 3304 }
3305
de6eae1f
YR		 3306 /* Init external phy*/
3307 if (!non_ext_phy)
3308 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3309 phy_index++) {
2cf7acf9 3310 /*
a22f0788
YR		 3311 * No need to initialize second phy in case of first
3312 * phy only selection. In case of second phy, we do
3313 * need to initialize the first phy, since they are
3314 * connected.
2cf7acf9 3315 */
a22f0788
YR		 3316 if (phy_index == EXT_PHY2 &&
3317 (bnx2x_phy_selection(params) ==
3318 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
2cf7acf9 3319 DP(NETIF_MSG_LINK, "Ignoring second phy\n");
a22f0788
YR		 3320 continue;
3321 }
de6eae1f
YR		 3322 params->phy[phy_index].config_init(
3323 &params->phy[phy_index],
3324 params, vars);
3325 }
4d295db0 3326
de6eae1f
YR		 3327 /* Reset the interrupt indication after phy was initialized */
3328 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
3329 params->port*4,
3330 (NIG_STATUS_XGXS0_LINK10G |
3331 NIG_STATUS_XGXS0_LINK_STATUS |
3332 NIG_STATUS_SERDES0_LINK_STATUS |
3333 NIG_MASK_MI_INT));
3334 return rc;
3335}
4d295db0 3336
de6eae1f
YR		 3337static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
3338 struct link_params *params)
3339{
3340 /* reset the SerDes/XGXS */
cd88ccee
YR		 3341 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
3342 (0x1ff << (params->port*16)));
589abe3a
EG		 3343}
3344
de6eae1f
YR		 3345static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
3346 struct link_params *params)
4d295db0 3347{
de6eae1f
YR		 3348 struct bnx2x *bp = params->bp;
3349 u8 gpio_port;
3350 /* HW reset */
f2e0899f
DK		 3351 if (CHIP_IS_E2(bp))
3352 gpio_port = BP_PATH(bp);
3353 else
3354 gpio_port = params->port;
de6eae1f 3355 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
cd88ccee
YR		 3356 MISC_REGISTERS_GPIO_OUTPUT_LOW,
3357 gpio_port);
de6eae1f 3358 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
cd88ccee
YR		 3359 MISC_REGISTERS_GPIO_OUTPUT_LOW,
3360 gpio_port);
de6eae1f 3361 DP(NETIF_MSG_LINK, "reset external PHY\n");
4d295db0 3362}
589abe3a 3363
de6eae1f
YR		 3364static u8 bnx2x_update_link_down(struct link_params *params,
3365 struct link_vars *vars)
589abe3a
EG		 3366{
3367 struct bnx2x *bp = params->bp;
de6eae1f 3368 u8 port = params->port;
589abe3a 3369
de6eae1f 3370 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
7f02c4ad 3371 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
589abe3a 3372
de6eae1f
YR		 3373 /* indicate no mac active */
3374 vars->mac_type = MAC_TYPE_NONE;
ab6ad5a4 3375
de6eae1f
YR		 3376 /* update shared memory */
3377 vars->link_status = 0;
3378 vars->line_speed = 0;
3379 bnx2x_update_mng(params, vars->link_status);
589abe3a 3380
de6eae1f
YR		 3381 /* activate nig drain */
3382 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
4d295db0 3383
de6eae1f
YR		 3384 /* disable emac */
3385 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
3386
3387 msleep(10);
3388
3389 /* reset BigMac */
3390 bnx2x_bmac_rx_disable(bp, params->port);
cd88ccee
YR		 3391 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
3392 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
589abe3a
EG		 3393 return 0;
3394}
de6eae1f
YR		 3395
3396static u8 bnx2x_update_link_up(struct link_params *params,
3397 struct link_vars *vars,
3398 u8 link_10g)
589abe3a
EG		 3399{
3400 struct bnx2x *bp = params->bp;
de6eae1f
YR		 3401 u8 port = params->port;
3402 u8 rc = 0;
4d295db0 3403
de6eae1f 3404 vars->link_status |= LINK_STATUS_LINK_UP;
7f02c4ad 3405
de6eae1f
YR		 3406 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
3407 vars->link_status |=
3408 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
589abe3a 3409
de6eae1f
YR		 3410 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
3411 vars->link_status |=
3412 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
7f02c4ad 3413
de6eae1f
YR		 3414 if (link_10g) {
3415 bnx2x_bmac_enable(params, vars, 0);
7f02c4ad
YR		 3416 bnx2x_set_led(params, vars,
3417 LED_MODE_OPER, SPEED_10000);
de6eae1f
YR		 3418 } else {
3419 rc = bnx2x_emac_program(params, vars);
cc1cb004 3420
de6eae1f 3421 bnx2x_emac_enable(params, vars, 0);
cc1cb004 3422
de6eae1f
YR		 3423 /* AN complete? */
3424 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
3425 && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
3426 SINGLE_MEDIA_DIRECT(params))
3427 bnx2x_set_gmii_tx_driver(params);
3428 }
cc1cb004 3429
de6eae1f 3430 /* PBF - link up */
f2e0899f
DK		 3431 if (!(CHIP_IS_E2(bp)))
3432 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
3433 vars->line_speed);
589abe3a 3434
de6eae1f
YR		 3435 /* disable drain */
3436 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
589abe3a 3437
de6eae1f
YR		 3438 /* update shared memory */
3439 bnx2x_update_mng(params, vars->link_status);
3440 msleep(20);
3441 return rc;
589abe3a 3442}
2cf7acf9 3443/*
de6eae1f
YR		 3444 * The bnx2x_link_update function should be called upon link
3445 * interrupt.
3446 * Link is considered up as follows:
3447 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
3448 * to be up
3449 * - SINGLE_MEDIA - The link between the 577xx and the external
3450 * phy (XGXS) need to up as well as the external link of the
3451 * phy (PHY_EXT1)
3452 * - DUAL_MEDIA - The link between the 577xx and the first
3453 * external phy needs to be up, and at least one of the 2
3454 * external phy link must be up.
3455 */
3456u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
4d295db0 3457{
de6eae1f
YR		 3458 struct bnx2x *bp = params->bp;
3459 struct link_vars phy_vars[MAX_PHYS];
3460 u8 port = params->port;
3461 u8 link_10g, phy_index;
3462 u8 ext_phy_link_up = 0, cur_link_up, rc = 0;
3463 u8 is_mi_int = 0;
3464 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
3465 u8 active_external_phy = INT_PHY;
3466 vars->link_status = 0;
3467 for (phy_index = INT_PHY; phy_index < params->num_phys;
3468 phy_index++) {
3469 phy_vars[phy_index].flow_ctrl = 0;
3470 phy_vars[phy_index].link_status = 0;
3471 phy_vars[phy_index].line_speed = 0;
3472 phy_vars[phy_index].duplex = DUPLEX_FULL;
3473 phy_vars[phy_index].phy_link_up = 0;
3474 phy_vars[phy_index].link_up = 0;
3475 }
4d295db0 3476
de6eae1f
YR		 3477 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
3478 port, (vars->phy_flags & PHY_XGXS_FLAG),
3479 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
4d295db0 3480
de6eae1f 3481 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
cd88ccee 3482 port*0x18) > 0);
de6eae1f
YR		 3483 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
3484 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
3485 is_mi_int,
cd88ccee 3486 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
4d295db0 3487
de6eae1f
YR		 3488 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
3489 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
3490 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
4d295db0 3491
de6eae1f
YR		 3492 /* disable emac */
3493 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
4d295db0 3494
2cf7acf9
YR		 3495 /*
3496 * Step 1:
3497 * Check external link change only for external phys, and apply
3498 * priority selection between them in case the link on both phys
3499 * is up. Note that the instead of the common vars, a temporary
3500 * vars argument is used since each phy may have different link/
3501 * speed/duplex result
3502 */
de6eae1f
YR		 3503 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3504 phy_index++) {
3505 struct bnx2x_phy *phy = &params->phy[phy_index];
3506 if (!phy->read_status)
3507 continue;
3508 /* Read link status and params of this ext phy */
3509 cur_link_up = phy->read_status(phy, params,
3510 &phy_vars[phy_index]);
3511 if (cur_link_up) {
3512 DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
3513 phy_index);
3514 } else {
3515 DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
3516 phy_index);
3517 continue;
3518 }
e10bc84d 3519
de6eae1f
YR		 3520 if (!ext_phy_link_up) {
3521 ext_phy_link_up = 1;
3522 active_external_phy = phy_index;
a22f0788
YR		 3523 } else {
3524 switch (bnx2x_phy_selection(params)) {
3525 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
3526 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
2cf7acf9 3527 /*
a22f0788
YR		 3528 * In this option, the first PHY makes sure to pass the
3529 * traffic through itself only.
3530 * Its not clear how to reset the link on the second phy
2cf7acf9 3531 */
a22f0788
YR		 3532 active_external_phy = EXT_PHY1;
3533 break;
3534 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
2cf7acf9 3535 /*
a22f0788
YR		 3536 * In this option, the first PHY makes sure to pass the
3537 * traffic through the second PHY.
2cf7acf9 3538 */
a22f0788
YR		 3539 active_external_phy = EXT_PHY2;
3540 break;
3541 default:
2cf7acf9 3542 /*
a22f0788
YR		 3543 * Link indication on both PHYs with the following cases
3544 * is invalid:
3545 * - FIRST_PHY means that second phy wasn't initialized,
3546 * hence its link is expected to be down
3547 * - SECOND_PHY means that first phy should not be able
3548 * to link up by itself (using configuration)
3549 * - DEFAULT should be overriden during initialiazation
2cf7acf9 3550 */
a22f0788
YR		 3551 DP(NETIF_MSG_LINK, "Invalid link indication"
3552 "mpc=0x%x. DISABLING LINK !!!\n",
3553 params->multi_phy_config);
3554 ext_phy_link_up = 0;
3555 break;
3556 }
589abe3a 3557 }
589abe3a 3558 }
de6eae1f 3559 prev_line_speed = vars->line_speed;
2cf7acf9
YR		 3560 /*
3561 * Step 2:
3562 * Read the status of the internal phy. In case of
3563 * DIRECT_SINGLE_MEDIA board, this link is the external link,
3564 * otherwise this is the link between the 577xx and the first
3565 * external phy
3566 */
de6eae1f
YR		 3567 if (params->phy[INT_PHY].read_status)
3568 params->phy[INT_PHY].read_status(
3569 &params->phy[INT_PHY],
3570 params, vars);
2cf7acf9 3571 /*
de6eae1f
YR		 3572 * The INT_PHY flow control reside in the vars. This include the
3573 * case where the speed or flow control are not set to AUTO.
3574 * Otherwise, the active external phy flow control result is set
3575 * to the vars. The ext_phy_line_speed is needed to check if the
3576 * speed is different between the internal phy and external phy.
3577 * This case may be result of intermediate link speed change.
4d295db0 3578 */
de6eae1f
YR		 3579 if (active_external_phy > INT_PHY) {
3580 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
2cf7acf9 3581 /*
de6eae1f
YR		 3582 * Link speed is taken from the XGXS. AN and FC result from
3583 * the external phy.
4d295db0 3584 */
de6eae1f 3585 vars->link_status |= phy_vars[active_external_phy].link_status;
a22f0788 3586
2cf7acf9 3587 /*
a22f0788
YR		 3588 * if active_external_phy is first PHY and link is up - disable
3589 * disable TX on second external PHY
3590 */
3591 if (active_external_phy == EXT_PHY1) {
3592 if (params->phy[EXT_PHY2].phy_specific_func) {
3593 DP(NETIF_MSG_LINK, "Disabling TX on"
3594 " EXT_PHY2\n");
3595 params->phy[EXT_PHY2].phy_specific_func(
3596 &params->phy[EXT_PHY2],
3597 params, DISABLE_TX);
3598 }
3599 }
3600
de6eae1f
YR		 3601 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
3602 vars->duplex = phy_vars[active_external_phy].duplex;
3603 if (params->phy[active_external_phy].supported &
3604 SUPPORTED_FIBRE)
3605 vars->link_status |= LINK_STATUS_SERDES_LINK;
3606 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
3607 active_external_phy);
3608 }
a22f0788
YR		 3609
3610 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3611 phy_index++) {
3612 if (params->phy[phy_index].flags &
3613 FLAGS_REARM_LATCH_SIGNAL) {
3614 bnx2x_rearm_latch_signal(bp, port,
3615 phy_index ==
3616 active_external_phy);
3617 break;
3618 }
3619 }
de6eae1f
YR		 3620 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
3621 " ext_phy_line_speed = %d\n", vars->flow_ctrl,
3622 vars->link_status, ext_phy_line_speed);
2cf7acf9 3623 /*
de6eae1f
YR		 3624 * Upon link speed change set the NIG into drain mode. Comes to
3625 * deals with possible FIFO glitch due to clk change when speed
3626 * is decreased without link down indicator
3627 */
4d295db0 3628
de6eae1f
YR		 3629 if (vars->phy_link_up) {
3630 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
3631 (ext_phy_line_speed != vars->line_speed)) {
3632 DP(NETIF_MSG_LINK, "Internal link speed %d is"
3633 " different than the external"
3634 " link speed %d\n", vars->line_speed,
3635 ext_phy_line_speed);
3636 vars->phy_link_up = 0;
3637 } else if (prev_line_speed != vars->line_speed) {
cd88ccee
YR		 3638 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
3639 0);
de6eae1f
YR		 3640 msleep(1);
3641 }
3642 }
e10bc84d 3643
de6eae1f
YR		 3644 /* anything 10 and over uses the bmac */
3645 link_10g = ((vars->line_speed == SPEED_10000) ||
3646 (vars->line_speed == SPEED_12000) ||
3647 (vars->line_speed == SPEED_12500) ||
3648 (vars->line_speed == SPEED_13000) ||
3649 (vars->line_speed == SPEED_15000) ||
3650 (vars->line_speed == SPEED_16000));
589abe3a 3651
a22f0788 3652 bnx2x_link_int_ack(params, vars, link_10g);
589abe3a 3653
2cf7acf9
YR		 3654 /*
3655 * In case external phy link is up, and internal link is down
3656 * (not initialized yet probably after link initialization, it
3657 * needs to be initialized.
3658 * Note that after link down-up as result of cable plug, the xgxs
3659 * link would probably become up again without the need
3660 * initialize it
3661 */
de6eae1f
YR		 3662 if (!(SINGLE_MEDIA_DIRECT(params))) {
3663 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
3664 " init_preceding = %d\n", ext_phy_link_up,
3665 vars->phy_link_up,
3666 params->phy[EXT_PHY1].flags &
3667 FLAGS_INIT_XGXS_FIRST);
3668 if (!(params->phy[EXT_PHY1].flags &
3669 FLAGS_INIT_XGXS_FIRST)
3670 && ext_phy_link_up && !vars->phy_link_up) {
3671 vars->line_speed = ext_phy_line_speed;
3672 if (vars->line_speed < SPEED_1000)
3673 vars->phy_flags |= PHY_SGMII_FLAG;
3674 else
3675 vars->phy_flags &= ~PHY_SGMII_FLAG;
3676 bnx2x_init_internal_phy(&params->phy[INT_PHY],
3677 params,
3678 vars);
4d295db0 3679 }
589abe3a 3680 }
2cf7acf9
YR		 3681 /*
3682 * Link is up only if both local phy and external phy (in case of
3683 * non-direct board) are up
4d295db0 3684 */
de6eae1f
YR		 3685 vars->link_up = (vars->phy_link_up &&
3686 (ext_phy_link_up ||
3687 SINGLE_MEDIA_DIRECT(params)));
3688
3689 if (vars->link_up)
3690 rc = bnx2x_update_link_up(params, vars, link_10g);
4d295db0 3691 else
de6eae1f 3692 rc = bnx2x_update_link_down(params, vars);
589abe3a 3693
4d295db0 3694 return rc;
589abe3a
EG		 3695}
3696
589abe3a 3697
de6eae1f
YR		 3698/*****************************************************************************/
3699/* External Phy section */
3700/*****************************************************************************/
3701void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
3702{
3703 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
cd88ccee 3704 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
de6eae1f
YR		 3705 msleep(1);
3706 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
cd88ccee 3707 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
de6eae1f 3708}
589abe3a 3709
de6eae1f
YR		 3710static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
3711 u32 spirom_ver, u32 ver_addr)
3712{
3713 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
3714 (u16)(spirom_ver>>16), (u16)spirom_ver, port);
4d295db0 3715
de6eae1f
YR		 3716 if (ver_addr)
3717 REG_WR(bp, ver_addr, spirom_ver);
589abe3a
EG		 3718}
3719
de6eae1f
YR		 3720static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
3721 struct bnx2x_phy *phy,
3722 u8 port)
6bbca910 3723{
de6eae1f
YR		 3724 u16 fw_ver1, fw_ver2;
3725
3726 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
cd88ccee 3727 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
de6eae1f 3728 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
cd88ccee 3729 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
de6eae1f
YR		 3730 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
3731 phy->ver_addr);
ea4e040a 3732}
ab6ad5a4 3733
de6eae1f
YR		 3734static void bnx2x_ext_phy_set_pause(struct link_params *params,
3735 struct bnx2x_phy *phy,
3736 struct link_vars *vars)
ea4e040a 3737{
ea4e040a 3738 u16 val;
de6eae1f
YR		 3739 struct bnx2x *bp = params->bp;
3740 /* read modify write pause advertizing */
3741 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
ea4e040a 3742
de6eae1f 3743 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
ea4e040a 3744
de6eae1f
YR		 3745 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3746 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3747 if ((vars->ieee_fc &
3748 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3749 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
cd88ccee 3750 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
de6eae1f
YR		 3751 }
3752 if ((vars->ieee_fc &
3753 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3754 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3755 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3756 }
3757 DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3758 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3759}
3760
3761static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3762 struct link_params *params,
3763 struct link_vars *vars)
3764{
3765 struct bnx2x *bp = params->bp;
3766 u16 ld_pause; /* local */
3767 u16 lp_pause; /* link partner */
3768 u16 pause_result;
3769 u8 ret = 0;
3770 /* read twice */
3771
3772 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3773
3774 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
3775 vars->flow_ctrl = phy->req_flow_ctrl;
3776 else if (phy->req_line_speed != SPEED_AUTO_NEG)
3777 vars->flow_ctrl = params->req_fc_auto_adv;
3778 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3779 ret = 1;
3780 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 3781 MDIO_AN_DEVAD,
3782 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
de6eae1f 3783 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 3784 MDIO_AN_DEVAD,
3785 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
de6eae1f
YR		 3786 pause_result = (ld_pause &
3787 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3788 pause_result |= (lp_pause &
3789 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3790 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n",
3791 pause_result);
3792 bnx2x_pause_resolve(vars, pause_result);
3793 }
3794 return ret;
3795}
3796
3797static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
3798 struct bnx2x_phy *phy,
3799 struct link_vars *vars)
3800{
3801 u16 val;
3802 bnx2x_cl45_read(bp, phy,
3803 MDIO_AN_DEVAD,
3804 MDIO_AN_REG_STATUS, &val);
3805 bnx2x_cl45_read(bp, phy,
3806 MDIO_AN_DEVAD,
3807 MDIO_AN_REG_STATUS, &val);
3808 if (val & (1<<5))
3809 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
3810 if ((val & (1<<0)) == 0)
3811 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
3812}
3813
3814/******************************************************************/
3815/* common BCM8073/BCM8727 PHY SECTION */
3816/******************************************************************/
3817static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
3818 struct link_params *params,
3819 struct link_vars *vars)
3820{
3821 struct bnx2x *bp = params->bp;
3822 if (phy->req_line_speed == SPEED_10 ||
3823 phy->req_line_speed == SPEED_100) {
3824 vars->flow_ctrl = phy->req_flow_ctrl;
3825 return;
3826 }
3827
3828 if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
3829 (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
3830 u16 pause_result;
3831 u16 ld_pause; /* local */
3832 u16 lp_pause; /* link partner */
3833 bnx2x_cl45_read(bp, phy,
3834 MDIO_AN_DEVAD,
3835 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3836
3837 bnx2x_cl45_read(bp, phy,
3838 MDIO_AN_DEVAD,
3839 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3840 pause_result = (ld_pause &
3841 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
3842 pause_result |= (lp_pause &
3843 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
3844
3845 bnx2x_pause_resolve(vars, pause_result);
3846 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
3847 pause_result);
3848 }
3849}
5c99274b 3850static u8 bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
de6eae1f
YR		 3851 struct bnx2x_phy *phy,
3852 u8 port)
3853{
5c99274b
YR		 3854 u32 count = 0;
3855 u16 fw_ver1, fw_msgout;
3856 u8 rc = 0;
3857
de6eae1f
YR		 3858 /* Boot port from external ROM */
3859 /* EDC grst */
3860 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 3861 MDIO_PMA_DEVAD,
3862 MDIO_PMA_REG_GEN_CTRL,
3863 0x0001);
de6eae1f
YR		 3864
3865 /* ucode reboot and rst */
3866 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 3867 MDIO_PMA_DEVAD,
3868 MDIO_PMA_REG_GEN_CTRL,
3869 0x008c);
de6eae1f
YR		 3870
3871 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 3872 MDIO_PMA_DEVAD,
3873 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
de6eae1f
YR		 3874
3875 /* Reset internal microprocessor */
3876 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 3877 MDIO_PMA_DEVAD,
3878 MDIO_PMA_REG_GEN_CTRL,
3879 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
de6eae1f
YR		 3880
3881 /* Release srst bit */
3882 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 3883 MDIO_PMA_DEVAD,
3884 MDIO_PMA_REG_GEN_CTRL,
3885 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
de6eae1f 3886
5c99274b
YR		 3887 /* Delay 100ms per the PHY specifications */
3888 msleep(100);
3889
3890 /* 8073 sometimes taking longer to download */
3891 do {
3892 count++;
3893 if (count > 300) {
3894 DP(NETIF_MSG_LINK,
3895 "bnx2x_8073_8727_external_rom_boot port %x:"
3896 "Download failed. fw version = 0x%x\n",
3897 port, fw_ver1);
3898 rc = -EINVAL;
3899 break;
3900 }
3901
3902 bnx2x_cl45_read(bp, phy,
3903 MDIO_PMA_DEVAD,
3904 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
3905 bnx2x_cl45_read(bp, phy,
3906 MDIO_PMA_DEVAD,
3907 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
3908
3909 msleep(1);
3910 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
3911 ((fw_msgout & 0xff) != 0x03 && (phy->type ==
3912 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
de6eae1f
YR		 3913
3914 /* Clear ser_boot_ctl bit */
3915 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 3916 MDIO_PMA_DEVAD,
3917 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
de6eae1f 3918 bnx2x_save_bcm_spirom_ver(bp, phy, port);
5c99274b
YR		 3919
3920 DP(NETIF_MSG_LINK,
3921 "bnx2x_8073_8727_external_rom_boot port %x:"
3922 "Download complete. fw version = 0x%x\n",
3923 port, fw_ver1);
3924
3925 return rc;
de6eae1f
YR		 3926}
3927
de6eae1f
YR		 3928/******************************************************************/
3929/* BCM8073 PHY SECTION */
3930/******************************************************************/
3931static u8 bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
3932{
3933 /* This is only required for 8073A1, version 102 only */
3934 u16 val;
3935
3936 /* Read 8073 HW revision*/
3937 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 3938 MDIO_PMA_DEVAD,
3939 MDIO_PMA_REG_8073_CHIP_REV, &val);
de6eae1f
YR		 3940
3941 if (val != 1) {
3942 /* No need to workaround in 8073 A1 */
3943 return 0;
3944 }
3945
3946 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 3947 MDIO_PMA_DEVAD,
3948 MDIO_PMA_REG_ROM_VER2, &val);
de6eae1f
YR		 3949
3950 /* SNR should be applied only for version 0x102 */
3951 if (val != 0x102)
3952 return 0;
3953
3954 return 1;
3955}
3956
3957static u8 bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
3958{
3959 u16 val, cnt, cnt1 ;
3960
3961 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 3962 MDIO_PMA_DEVAD,
3963 MDIO_PMA_REG_8073_CHIP_REV, &val);
de6eae1f
YR		 3964
3965 if (val > 0) {
3966 /* No need to workaround in 8073 A1 */
3967 return 0;
3968 }
3969 /* XAUI workaround in 8073 A0: */
3970
2cf7acf9
YR		 3971 /*
3972 * After loading the boot ROM and restarting Autoneg, poll
3973 * Dev1, Reg $C820:
3974 */
de6eae1f
YR		 3975
3976 for (cnt = 0; cnt < 1000; cnt++) {
3977 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 3978 MDIO_PMA_DEVAD,
3979 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
3980 &val);
2cf7acf9
YR		 3981 /*
3982 * If bit [14] = 0 or bit [13] = 0, continue on with
3983 * system initialization (XAUI work-around not required, as
3984 * these bits indicate 2.5G or 1G link up).
3985 */
de6eae1f
YR		 3986 if (!(val & (1<<14)) || !(val & (1<<13))) {
3987 DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
3988 return 0;
3989 } else if (!(val & (1<<15))) {
2cf7acf9
YR		 3990 DP(NETIF_MSG_LINK, "bit 15 went off\n");
3991 /*
3992 * If bit 15 is 0, then poll Dev1, Reg $C841 until it's
3993 * MSB (bit15) goes to 1 (indicating that the XAUI
3994 * workaround has completed), then continue on with
3995 * system initialization.
3996 */
de6eae1f
YR		 3997 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
3998 bnx2x_cl45_read(bp, phy,
3999 MDIO_PMA_DEVAD,
4000 MDIO_PMA_REG_8073_XAUI_WA, &val);
4001 if (val & (1<<15)) {
4002 DP(NETIF_MSG_LINK,
4003 "XAUI workaround has completed\n");
4004 return 0;
4005 }
4006 msleep(3);
4007 }
4008 break;
4009 }
4010 msleep(3);
4011 }
4012 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
4013 return -EINVAL;
4014}
4015
4016static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
4017{
4018 /* Force KR or KX */
4019 bnx2x_cl45_write(bp, phy,
4020 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
4021 bnx2x_cl45_write(bp, phy,
4022 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
4023 bnx2x_cl45_write(bp, phy,
4024 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
4025 bnx2x_cl45_write(bp, phy,
4026 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
4027}
4028
6bbca910 4029static void bnx2x_8073_set_pause_cl37(struct link_params *params,
e10bc84d
YR		 4030 struct bnx2x_phy *phy,
4031 struct link_vars *vars)
ea4e040a 4032{
6bbca910 4033 u16 cl37_val;
e10bc84d
YR		 4034 struct bnx2x *bp = params->bp;
4035 bnx2x_cl45_read(bp, phy,
62b29a5d 4036 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
6bbca910
YR		 4037
4038 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
4039 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
e10bc84d 4040 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
6bbca910
YR		 4041 if ((vars->ieee_fc &
4042 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
4043 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
4044 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
4045 }
4046 if ((vars->ieee_fc &
4047 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
4048 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
4049 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
4050 }
4051 if ((vars->ieee_fc &
4052 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
4053 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
4054 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
4055 }
4056 DP(NETIF_MSG_LINK,
4057 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
4058
e10bc84d 4059 bnx2x_cl45_write(bp, phy,
62b29a5d 4060 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
6bbca910 4061 msleep(500);
ea4e040a
YR		 4062}
4063
de6eae1f
YR		 4064static u8 bnx2x_8073_config_init(struct bnx2x_phy *phy,
4065 struct link_params *params,
4066 struct link_vars *vars)
ea4e040a 4067{
e10bc84d 4068 struct bnx2x *bp = params->bp;
de6eae1f
YR		 4069 u16 val = 0, tmp1;
4070 u8 gpio_port;
4071 DP(NETIF_MSG_LINK, "Init 8073\n");
e10bc84d 4072
f2e0899f
DK		 4073 if (CHIP_IS_E2(bp))
4074 gpio_port = BP_PATH(bp);
4075 else
4076 gpio_port = params->port;
de6eae1f
YR		 4077 /* Restore normal power mode*/
4078 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
cd88ccee 4079 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
e10bc84d 4080
de6eae1f 4081 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
cd88ccee 4082 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
ea4e040a 4083
de6eae1f
YR		 4084 /* enable LASI */
4085 bnx2x_cl45_write(bp, phy,
4086 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL, (1<<2));
4087 bnx2x_cl45_write(bp, phy,
4088 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x0004);
c2c8b03e 4089
de6eae1f 4090 bnx2x_8073_set_pause_cl37(params, phy, vars);
57963ed9 4091
e10bc84d 4092 bnx2x_cl45_read(bp, phy,
de6eae1f 4093 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
2f904460 4094
de6eae1f
YR		 4095 bnx2x_cl45_read(bp, phy,
4096 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1);
2f904460 4097
de6eae1f 4098 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
a1e4be39 4099
74d7a119
YR		 4100 /* Swap polarity if required - Must be done only in non-1G mode */
4101 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
4102 /* Configure the 8073 to swap _P and _N of the KR lines */
4103 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
4104 /* 10G Rx/Tx and 1G Tx signal polarity swap */
4105 bnx2x_cl45_read(bp, phy,
4106 MDIO_PMA_DEVAD,
4107 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
4108 bnx2x_cl45_write(bp, phy,
4109 MDIO_PMA_DEVAD,
4110 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
4111 (val | (3<<9)));
4112 }
4113
4114
de6eae1f 4115 /* Enable CL37 BAM */
121839be
YR		 4116 if (REG_RD(bp, params->shmem_base +
4117 offsetof(struct shmem_region, dev_info.
4118 port_hw_config[params->port].default_cfg)) &
4119 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
57963ed9 4120
121839be
YR		 4121 bnx2x_cl45_read(bp, phy,
4122 MDIO_AN_DEVAD,
4123 MDIO_AN_REG_8073_BAM, &val);
4124 bnx2x_cl45_write(bp, phy,
4125 MDIO_AN_DEVAD,
4126 MDIO_AN_REG_8073_BAM, val | 1);
4127 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
4128 }
de6eae1f
YR		 4129 if (params->loopback_mode == LOOPBACK_EXT) {
4130 bnx2x_807x_force_10G(bp, phy);
4131 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
4132 return 0;
4133 } else {
4134 bnx2x_cl45_write(bp, phy,
4135 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
4136 }
4137 if (phy->req_line_speed != SPEED_AUTO_NEG) {
4138 if (phy->req_line_speed == SPEED_10000) {
4139 val = (1<<7);
4140 } else if (phy->req_line_speed == SPEED_2500) {
4141 val = (1<<5);
2cf7acf9
YR		 4142 /*
4143 * Note that 2.5G works only when used with 1G
25985edc 4144 * advertisement
2cf7acf9 4145 */
de6eae1f
YR		 4146 } else
4147 val = (1<<5);
4148 } else {
4149 val = 0;
4150 if (phy->speed_cap_mask &
4151 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4152 val |= (1<<7);
57963ed9 4153
25985edc 4154 /* Note that 2.5G works only when used with 1G advertisement */
de6eae1f
YR		 4155 if (phy->speed_cap_mask &
4156 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
4157 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
4158 val |= (1<<5);
4159 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
4160 }
57963ed9 4161
de6eae1f
YR		 4162 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
4163 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
57963ed9 4164
de6eae1f
YR		 4165 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
4166 (phy->req_line_speed == SPEED_AUTO_NEG)) ||
4167 (phy->req_line_speed == SPEED_2500)) {
4168 u16 phy_ver;
4169 /* Allow 2.5G for A1 and above */
4170 bnx2x_cl45_read(bp, phy,
4171 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
4172 &phy_ver);
4173 DP(NETIF_MSG_LINK, "Add 2.5G\n");
4174 if (phy_ver > 0)
4175 tmp1 |= 1;
4176 else
4177 tmp1 &= 0xfffe;
4178 } else {
4179 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
4180 tmp1 &= 0xfffe;
4181 }
57963ed9 4182
de6eae1f
YR		 4183 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
4184 /* Add support for CL37 (passive mode) II */
57963ed9 4185
de6eae1f
YR		 4186 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
4187 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
4188 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
4189 0x20 : 0x40)));
57963ed9 4190
de6eae1f
YR		 4191 /* Add support for CL37 (passive mode) III */
4192 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
57963ed9 4193
2cf7acf9
YR		 4194 /*
4195 * The SNR will improve about 2db by changing BW and FEE main
4196 * tap. Rest commands are executed after link is up
4197 * Change FFE main cursor to 5 in EDC register
4198 */
de6eae1f
YR		 4199 if (bnx2x_8073_is_snr_needed(bp, phy))
4200 bnx2x_cl45_write(bp, phy,
4201 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
4202 0xFB0C);
57963ed9 4203
de6eae1f
YR		 4204 /* Enable FEC (Forware Error Correction) Request in the AN */
4205 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
4206 tmp1 |= (1<<15);
4207 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
57963ed9 4208
de6eae1f 4209 bnx2x_ext_phy_set_pause(params, phy, vars);
57963ed9 4210
de6eae1f
YR		 4211 /* Restart autoneg */
4212 msleep(500);
4213 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
4214 DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
4215 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
4216 return 0;
b7737c9b 4217}
ea4e040a 4218
de6eae1f 4219static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
b7737c9b
YR		 4220 struct link_params *params,
4221 struct link_vars *vars)
4222{
4223 struct bnx2x *bp = params->bp;
de6eae1f
YR		 4224 u8 link_up = 0;
4225 u16 val1, val2;
4226 u16 link_status = 0;
4227 u16 an1000_status = 0;
a35da8db 4228
de6eae1f
YR		 4229 bnx2x_cl45_read(bp, phy,
4230 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
b7737c9b 4231
de6eae1f 4232 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
ea4e040a 4233
de6eae1f
YR		 4234 /* clear the interrupt LASI status register */
4235 bnx2x_cl45_read(bp, phy,
4236 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
4237 bnx2x_cl45_read(bp, phy,
4238 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
4239 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
4240 /* Clear MSG-OUT */
4241 bnx2x_cl45_read(bp, phy,
4242 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
4243
4244 /* Check the LASI */
4245 bnx2x_cl45_read(bp, phy,
4246 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2);
4247
4248 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
4249
4250 /* Check the link status */
4251 bnx2x_cl45_read(bp, phy,
4252 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
4253 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
4254
4255 bnx2x_cl45_read(bp, phy,
4256 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
4257 bnx2x_cl45_read(bp, phy,
4258 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
4259 link_up = ((val1 & 4) == 4);
4260 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
4261
4262 if (link_up &&
4263 ((phy->req_line_speed != SPEED_10000))) {
4264 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
4265 return 0;
62b29a5d 4266 }
de6eae1f
YR		 4267 bnx2x_cl45_read(bp, phy,
4268 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
4269 bnx2x_cl45_read(bp, phy,
4270 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
62b29a5d 4271
de6eae1f
YR		 4272 /* Check the link status on 1.1.2 */
4273 bnx2x_cl45_read(bp, phy,
4274 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
4275 bnx2x_cl45_read(bp, phy,
4276 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
4277 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
4278 "an_link_status=0x%x\n", val2, val1, an1000_status);
62b29a5d 4279
de6eae1f
YR		 4280 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
4281 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
2cf7acf9
YR		 4282 /*
4283 * The SNR will improve about 2dbby changing the BW and FEE main
4284 * tap. The 1st write to change FFE main tap is set before
4285 * restart AN. Change PLL Bandwidth in EDC register
4286 */
62b29a5d 4287 bnx2x_cl45_write(bp, phy,
de6eae1f
YR		 4288 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
4289 0x26BC);
62b29a5d 4290
de6eae1f 4291 /* Change CDR Bandwidth in EDC register */
62b29a5d 4292 bnx2x_cl45_write(bp, phy,
de6eae1f
YR		 4293 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
4294 0x0333);
4295 }
4296 bnx2x_cl45_read(bp, phy,
4297 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
4298 &link_status);
62b29a5d 4299
de6eae1f
YR		 4300 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
4301 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
4302 link_up = 1;
4303 vars->line_speed = SPEED_10000;
4304 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
4305 params->port);
4306 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
4307 link_up = 1;
4308 vars->line_speed = SPEED_2500;
4309 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
4310 params->port);
4311 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
4312 link_up = 1;
4313 vars->line_speed = SPEED_1000;
4314 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
4315 params->port);
4316 } else {
4317 link_up = 0;
4318 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
4319 params->port);
62b29a5d 4320 }
de6eae1f
YR		 4321
4322 if (link_up) {
74d7a119
YR		 4323 /* Swap polarity if required */
4324 if (params->lane_config &
4325 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
4326 /* Configure the 8073 to swap P and N of the KR lines */
4327 bnx2x_cl45_read(bp, phy,
4328 MDIO_XS_DEVAD,
4329 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
2cf7acf9
YR		 4330 /*
4331 * Set bit 3 to invert Rx in 1G mode and clear this bit
4332 * when it`s in 10G mode.
4333 */
74d7a119
YR		 4334 if (vars->line_speed == SPEED_1000) {
4335 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
4336 "the 8073\n");
4337 val1 |= (1<<3);
4338 } else
4339 val1 &= ~(1<<3);
4340
4341 bnx2x_cl45_write(bp, phy,
4342 MDIO_XS_DEVAD,
4343 MDIO_XS_REG_8073_RX_CTRL_PCIE,
4344 val1);
4345 }
de6eae1f
YR		 4346 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
4347 bnx2x_8073_resolve_fc(phy, params, vars);
791f18c0 4348 vars->duplex = DUPLEX_FULL;
de6eae1f
YR		 4349 }
4350 return link_up;
b7737c9b
YR		 4351}
4352
de6eae1f
YR		 4353static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
4354 struct link_params *params)
4355{
4356 struct bnx2x *bp = params->bp;
4357 u8 gpio_port;
f2e0899f
DK		 4358 if (CHIP_IS_E2(bp))
4359 gpio_port = BP_PATH(bp);
4360 else
4361 gpio_port = params->port;
de6eae1f
YR		 4362 DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
4363 gpio_port);
4364 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
cd88ccee
YR		 4365 MISC_REGISTERS_GPIO_OUTPUT_LOW,
4366 gpio_port);
de6eae1f
YR		 4367}
4368
4369/******************************************************************/
4370/* BCM8705 PHY SECTION */
4371/******************************************************************/
4372static u8 bnx2x_8705_config_init(struct bnx2x_phy *phy,
b7737c9b
YR		 4373 struct link_params *params,
4374 struct link_vars *vars)
4375{
4376 struct bnx2x *bp = params->bp;
de6eae1f 4377 DP(NETIF_MSG_LINK, "init 8705\n");
b7737c9b
YR		 4378 /* Restore normal power mode*/
4379 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
cd88ccee 4380 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
de6eae1f
YR		 4381 /* HW reset */
4382 bnx2x_ext_phy_hw_reset(bp, params->port);
4383 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
6d870c39 4384 bnx2x_wait_reset_complete(bp, phy, params);
b7737c9b 4385
de6eae1f
YR		 4386 bnx2x_cl45_write(bp, phy,
4387 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
4388 bnx2x_cl45_write(bp, phy,
4389 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
4390 bnx2x_cl45_write(bp, phy,
4391 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
4392 bnx2x_cl45_write(bp, phy,
4393 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
4394 /* BCM8705 doesn't have microcode, hence the 0 */
4395 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
4396 return 0;
4397}
4d295db0 4398
de6eae1f
YR		 4399static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
4400 struct link_params *params,
4401 struct link_vars *vars)
4402{
4403 u8 link_up = 0;
4404 u16 val1, rx_sd;
4405 struct bnx2x *bp = params->bp;
4406 DP(NETIF_MSG_LINK, "read status 8705\n");
4407 bnx2x_cl45_read(bp, phy,
4408 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
4409 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
62b29a5d 4410
de6eae1f
YR		 4411 bnx2x_cl45_read(bp, phy,
4412 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
4413 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
62b29a5d 4414
de6eae1f
YR		 4415 bnx2x_cl45_read(bp, phy,
4416 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
c2c8b03e 4417
de6eae1f
YR		 4418 bnx2x_cl45_read(bp, phy,
4419 MDIO_PMA_DEVAD, 0xc809, &val1);
4420 bnx2x_cl45_read(bp, phy,
4421 MDIO_PMA_DEVAD, 0xc809, &val1);
c2c8b03e 4422
de6eae1f
YR		 4423 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
4424 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
4425 if (link_up) {
4426 vars->line_speed = SPEED_10000;
4427 bnx2x_ext_phy_resolve_fc(phy, params, vars);
62b29a5d 4428 }
de6eae1f
YR		 4429 return link_up;
4430}
d90d96ba 4431
de6eae1f
YR		 4432/******************************************************************/
4433/* SFP+ module Section */
4434/******************************************************************/
a8db5b4c
YR		 4435static u8 bnx2x_get_gpio_port(struct link_params *params)
4436{
4437 u8 gpio_port;
4438 u32 swap_val, swap_override;
4439 struct bnx2x *bp = params->bp;
4440 if (CHIP_IS_E2(bp))
4441 gpio_port = BP_PATH(bp);
4442 else
4443 gpio_port = params->port;
4444 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
4445 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
4446 return gpio_port ^ (swap_val && swap_override);
4447}
4448static void bnx2x_sfp_set_transmitter(struct link_params *params,
de6eae1f 4449 struct bnx2x_phy *phy,
de6eae1f
YR		 4450 u8 tx_en)
4451{
4452 u16 val;
a8db5b4c
YR		 4453 u8 port = params->port;
4454 struct bnx2x *bp = params->bp;
4455 u32 tx_en_mode;
d90d96ba 4456
de6eae1f 4457 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
a8db5b4c
YR		 4458 tx_en_mode = REG_RD(bp, params->shmem_base +
4459 offsetof(struct shmem_region,
4460 dev_info.port_hw_config[port].sfp_ctrl)) &
4461 PORT_HW_CFG_TX_LASER_MASK;
4462 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
4463 "mode = %x\n", tx_en, port, tx_en_mode);
4464 switch (tx_en_mode) {
4465 case PORT_HW_CFG_TX_LASER_MDIO:
d90d96ba 4466
a8db5b4c
YR		 4467 bnx2x_cl45_read(bp, phy,
4468 MDIO_PMA_DEVAD,
4469 MDIO_PMA_REG_PHY_IDENTIFIER,
4470 &val);
b7737c9b 4471
a8db5b4c
YR		 4472 if (tx_en)
4473 val &= ~(1<<15);
4474 else
4475 val |= (1<<15);
4476
4477 bnx2x_cl45_write(bp, phy,
4478 MDIO_PMA_DEVAD,
4479 MDIO_PMA_REG_PHY_IDENTIFIER,
4480 val);
4481 break;
4482 case PORT_HW_CFG_TX_LASER_GPIO0:
4483 case PORT_HW_CFG_TX_LASER_GPIO1:
4484 case PORT_HW_CFG_TX_LASER_GPIO2:
4485 case PORT_HW_CFG_TX_LASER_GPIO3:
4486 {
4487 u16 gpio_pin;
4488 u8 gpio_port, gpio_mode;
4489 if (tx_en)
4490 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
4491 else
4492 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
4493
4494 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
4495 gpio_port = bnx2x_get_gpio_port(params);
4496 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
4497 break;
4498 }
4499 default:
4500 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
4501 break;
4502 }
b7737c9b
YR		 4503}
4504
de6eae1f
YR		 4505static u8 bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4506 struct link_params *params,
cd88ccee 4507 u16 addr, u8 byte_cnt, u8 *o_buf)
b7737c9b
YR		 4508{
4509 struct bnx2x *bp = params->bp;
de6eae1f
YR		 4510 u16 val = 0;
4511 u16 i;
4512 if (byte_cnt > 16) {
4513 DP(NETIF_MSG_LINK, "Reading from eeprom is"
4514 " is limited to 0xf\n");
4515 return -EINVAL;
4516 }
4517 /* Set the read command byte count */
62b29a5d 4518 bnx2x_cl45_write(bp, phy,
de6eae1f 4519 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
cd88ccee 4520 (byte_cnt | 0xa000));
ea4e040a 4521
de6eae1f
YR		 4522 /* Set the read command address */
4523 bnx2x_cl45_write(bp, phy,
4524 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
cd88ccee 4525 addr);
ea4e040a 4526
de6eae1f 4527 /* Activate read command */
62b29a5d 4528 bnx2x_cl45_write(bp, phy,
de6eae1f 4529 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
cd88ccee 4530 0x2c0f);
ea4e040a 4531
de6eae1f
YR		 4532 /* Wait up to 500us for command complete status */
4533 for (i = 0; i < 100; i++) {
4534 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 4535 MDIO_PMA_DEVAD,
4536 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
de6eae1f
YR		 4537 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4538 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
4539 break;
4540 udelay(5);
62b29a5d 4541 }
62b29a5d 4542
de6eae1f
YR		 4543 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
4544 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
4545 DP(NETIF_MSG_LINK,
4546 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
4547 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
4548 return -EINVAL;
62b29a5d 4549 }
e10bc84d 4550
de6eae1f
YR		 4551 /* Read the buffer */
4552 for (i = 0; i < byte_cnt; i++) {
62b29a5d 4553 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 4554 MDIO_PMA_DEVAD,
4555 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
de6eae1f 4556 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
62b29a5d 4557 }
6bbca910 4558
de6eae1f
YR		 4559 for (i = 0; i < 100; i++) {
4560 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 4561 MDIO_PMA_DEVAD,
4562 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
de6eae1f
YR		 4563 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4564 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
6f38ad93 4565 return 0;
de6eae1f
YR		 4566 msleep(1);
4567 }
4568 return -EINVAL;
b7737c9b 4569}
4d295db0 4570
de6eae1f
YR		 4571static u8 bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4572 struct link_params *params,
cd88ccee 4573 u16 addr, u8 byte_cnt, u8 *o_buf)
b7737c9b 4574{
b7737c9b 4575 struct bnx2x *bp = params->bp;
de6eae1f 4576 u16 val, i;
ea4e040a 4577
de6eae1f
YR		 4578 if (byte_cnt > 16) {
4579 DP(NETIF_MSG_LINK, "Reading from eeprom is"
4580 " is limited to 0xf\n");
4581 return -EINVAL;
4582 }
4d295db0 4583
de6eae1f
YR		 4584 /* Need to read from 1.8000 to clear it */
4585 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 4586 MDIO_PMA_DEVAD,
4587 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
4588 &val);
4d295db0 4589
de6eae1f 4590 /* Set the read command byte count */
62b29a5d 4591 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 4592 MDIO_PMA_DEVAD,
4593 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
4594 ((byte_cnt < 2) ? 2 : byte_cnt));
ea4e040a 4595
de6eae1f 4596 /* Set the read command address */
62b29a5d 4597 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 4598 MDIO_PMA_DEVAD,
4599 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
4600 addr);
de6eae1f 4601 /* Set the destination address */
62b29a5d 4602 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 4603 MDIO_PMA_DEVAD,
4604 0x8004,
4605 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
62b29a5d 4606
de6eae1f 4607 /* Activate read command */
62b29a5d 4608 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 4609 MDIO_PMA_DEVAD,
4610 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
4611 0x8002);
2cf7acf9
YR		 4612 /*
4613 * Wait appropriate time for two-wire command to finish before
4614 * polling the status register
4615 */
de6eae1f 4616 msleep(1);
4d295db0 4617
de6eae1f
YR		 4618 /* Wait up to 500us for command complete status */
4619 for (i = 0; i < 100; i++) {
62b29a5d 4620 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 4621 MDIO_PMA_DEVAD,
4622 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
de6eae1f
YR		 4623 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4624 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
4625 break;
4626 udelay(5);
62b29a5d 4627 }
4d295db0 4628
de6eae1f
YR		 4629 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
4630 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
4631 DP(NETIF_MSG_LINK,
4632 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
4633 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
65a001ba 4634 return -EFAULT;
de6eae1f 4635 }
62b29a5d 4636
de6eae1f
YR		 4637 /* Read the buffer */
4638 for (i = 0; i < byte_cnt; i++) {
4639 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 4640 MDIO_PMA_DEVAD,
4641 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
de6eae1f
YR		 4642 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
4643 }
4d295db0 4644
de6eae1f
YR		 4645 for (i = 0; i < 100; i++) {
4646 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 4647 MDIO_PMA_DEVAD,
4648 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
de6eae1f
YR		 4649 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4650 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
6f38ad93 4651 return 0;
de6eae1f 4652 msleep(1);
62b29a5d
YR		 4653 }
4654
de6eae1f 4655 return -EINVAL;
b7737c9b
YR		 4656}
4657
cd88ccee
YR		 4658u8 bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4659 struct link_params *params, u16 addr,
4660 u8 byte_cnt, u8 *o_buf)
b7737c9b 4661{
e4d78f12
YR		 4662 u8 rc = -EINVAL;
4663 switch (phy->type) {
4664 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
4665 rc = bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
4666 byte_cnt, o_buf);
4667 break;
4668 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
4669 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
4670 rc = bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
4671 byte_cnt, o_buf);
4672 break;
4673 }
4674 return rc;
b7737c9b
YR		 4675}
4676
de6eae1f
YR		 4677static u8 bnx2x_get_edc_mode(struct bnx2x_phy *phy,
4678 struct link_params *params,
cd88ccee 4679 u16 *edc_mode)
b7737c9b
YR		 4680{
4681 struct bnx2x *bp = params->bp;
de6eae1f
YR		 4682 u8 val, check_limiting_mode = 0;
4683 *edc_mode = EDC_MODE_LIMITING;
62b29a5d 4684
de6eae1f
YR		 4685 /* First check for copper cable */
4686 if (bnx2x_read_sfp_module_eeprom(phy,
4687 params,
4688 SFP_EEPROM_CON_TYPE_ADDR,
4689 1,
4690 &val) != 0) {
4691 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
4692 return -EINVAL;
4693 }
a1e4be39 4694
de6eae1f
YR		 4695 switch (val) {
4696 case SFP_EEPROM_CON_TYPE_VAL_COPPER:
4697 {
4698 u8 copper_module_type;
62b29a5d 4699
2cf7acf9
YR		 4700 /*
4701 * Check if its active cable (includes SFP+ module)
4702 * of passive cable
4703 */
de6eae1f
YR		 4704 if (bnx2x_read_sfp_module_eeprom(phy,
4705 params,
4706 SFP_EEPROM_FC_TX_TECH_ADDR,
4707 1,
4708 &copper_module_type) !=
4709 0) {
4710 DP(NETIF_MSG_LINK,
4711 "Failed to read copper-cable-type"
4712 " from SFP+ EEPROM\n");
4713 return -EINVAL;
4714 }
4f60dab1 4715
de6eae1f
YR		 4716 if (copper_module_type &
4717 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
4718 DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
4719 check_limiting_mode = 1;
4720 } else if (copper_module_type &
4721 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
4722 DP(NETIF_MSG_LINK, "Passive Copper"
4723 " cable detected\n");
4724 *edc_mode =
4725 EDC_MODE_PASSIVE_DAC;
4726 } else {
4727 DP(NETIF_MSG_LINK, "Unknown copper-cable-"
4728 "type 0x%x !!!\n", copper_module_type);
4729 return -EINVAL;
4730 }
4731 break;
62b29a5d 4732 }
de6eae1f
YR		 4733 case SFP_EEPROM_CON_TYPE_VAL_LC:
4734 DP(NETIF_MSG_LINK, "Optic module detected\n");
4735 check_limiting_mode = 1;
4736 break;
4737 default:
4738 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
4739 val);
4740 return -EINVAL;
62b29a5d 4741 }
2f904460 4742
de6eae1f
YR		 4743 if (check_limiting_mode) {
4744 u8 options[SFP_EEPROM_OPTIONS_SIZE];
4745 if (bnx2x_read_sfp_module_eeprom(phy,
4746 params,
4747 SFP_EEPROM_OPTIONS_ADDR,
4748 SFP_EEPROM_OPTIONS_SIZE,
4749 options) != 0) {
4750 DP(NETIF_MSG_LINK, "Failed to read Option"
4751 " field from module EEPROM\n");
4752 return -EINVAL;
4753 }
4754 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
4755 *edc_mode = EDC_MODE_LINEAR;
4756 else
4757 *edc_mode = EDC_MODE_LIMITING;
62b29a5d 4758 }
de6eae1f 4759 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
62b29a5d 4760 return 0;
b7737c9b 4761}
2cf7acf9
YR		 4762/*
4763 * This function read the relevant field from the module (SFP+), and verify it
4764 * is compliant with this board
4765 */
de6eae1f
YR		 4766static u8 bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
4767 struct link_params *params)
b7737c9b
YR		 4768{
4769 struct bnx2x *bp = params->bp;
a22f0788
YR		 4770 u32 val, cmd;
4771 u32 fw_resp, fw_cmd_param;
de6eae1f
YR		 4772 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
4773 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
a22f0788 4774 phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
de6eae1f
YR		 4775 val = REG_RD(bp, params->shmem_base +
4776 offsetof(struct shmem_region, dev_info.
4777 port_feature_config[params->port].config));
4778 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
4779 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
4780 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
4781 return 0;
4782 }
ea4e040a 4783
a22f0788
YR		 4784 if (params->feature_config_flags &
4785 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
4786 /* Use specific phy request */
4787 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
4788 } else if (params->feature_config_flags &
4789 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
4790 /* Use first phy request only in case of non-dual media*/
4791 if (DUAL_MEDIA(params)) {
4792 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
4793 "verification\n");
4794 return -EINVAL;
4795 }
4796 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
4797 } else {
4798 /* No support in OPT MDL detection */
de6eae1f 4799 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
a22f0788 4800 "verification\n");
de6eae1f
YR		 4801 return -EINVAL;
4802 }
523224a3 4803
a22f0788
YR		 4804 fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
4805 fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
de6eae1f
YR		 4806 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
4807 DP(NETIF_MSG_LINK, "Approved module\n");
4808 return 0;
4809 }
b7737c9b 4810
de6eae1f
YR		 4811 /* format the warning message */
4812 if (bnx2x_read_sfp_module_eeprom(phy,
4813 params,
cd88ccee
YR		 4814 SFP_EEPROM_VENDOR_NAME_ADDR,
4815 SFP_EEPROM_VENDOR_NAME_SIZE,
4816 (u8 *)vendor_name))
de6eae1f
YR		 4817 vendor_name[0] = '\0';
4818 else
4819 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
4820 if (bnx2x_read_sfp_module_eeprom(phy,
4821 params,
cd88ccee
YR		 4822 SFP_EEPROM_PART_NO_ADDR,
4823 SFP_EEPROM_PART_NO_SIZE,
4824 (u8 *)vendor_pn))
de6eae1f
YR		 4825 vendor_pn[0] = '\0';
4826 else
4827 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
4828
6d870c39
YR		 4829 netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected,"
4830 " Port %d from %s part number %s\n",
4831 params->port, vendor_name, vendor_pn);
a22f0788 4832 phy->flags |= FLAGS_SFP_NOT_APPROVED;
de6eae1f 4833 return -EINVAL;
b7737c9b 4834}
7aa0711f 4835
de6eae1f
YR		 4836static u8 bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
4837 struct link_params *params)
7aa0711f 4838
4d295db0 4839{
de6eae1f 4840 u8 val;
4d295db0 4841 struct bnx2x *bp = params->bp;
de6eae1f 4842 u16 timeout;
2cf7acf9
YR		 4843 /*
4844 * Initialization time after hot-plug may take up to 300ms for
4845 * some phys type ( e.g. JDSU )
4846 */
4847
de6eae1f
YR		 4848 for (timeout = 0; timeout < 60; timeout++) {
4849 if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val)
4850 == 0) {
4851 DP(NETIF_MSG_LINK, "SFP+ module initialization "
4852 "took %d ms\n", timeout * 5);
4853 return 0;
4854 }
4855 msleep(5);
4856 }
4857 return -EINVAL;
4858}
4d295db0 4859
de6eae1f
YR		 4860static void bnx2x_8727_power_module(struct bnx2x *bp,
4861 struct bnx2x_phy *phy,
4862 u8 is_power_up) {
4863 /* Make sure GPIOs are not using for LED mode */
4864 u16 val;
4865 /*
2cf7acf9 4866 * In the GPIO register, bit 4 is use to determine if the GPIOs are
de6eae1f
YR		 4867 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
4868 * output
4869 * Bits 0-1 determine the gpios value for OUTPUT in case bit 4 val is 0
4870 * Bits 8-9 determine the gpios value for INPUT in case bit 4 val is 1
4871 * where the 1st bit is the over-current(only input), and 2nd bit is
4872 * for power( only output )
2cf7acf9 4873 *
de6eae1f
YR		 4874 * In case of NOC feature is disabled and power is up, set GPIO control
4875 * as input to enable listening of over-current indication
4876 */
4877 if (phy->flags & FLAGS_NOC)
4878 return;
4879 if (!(phy->flags &
4880 FLAGS_NOC) && is_power_up)
4881 val = (1<<4);
4882 else
4883 /*
4884 * Set GPIO control to OUTPUT, and set the power bit
4885 * to according to the is_power_up
4886 */
4887 val = ((!(is_power_up)) << 1);
4d295db0 4888
de6eae1f
YR		 4889 bnx2x_cl45_write(bp, phy,
4890 MDIO_PMA_DEVAD,
4891 MDIO_PMA_REG_8727_GPIO_CTRL,
4892 val);
4893}
4d295db0 4894
de6eae1f
YR		 4895static u8 bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
4896 struct bnx2x_phy *phy,
4897 u16 edc_mode)
4898{
4899 u16 cur_limiting_mode;
4d295db0 4900
de6eae1f 4901 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 4902 MDIO_PMA_DEVAD,
4903 MDIO_PMA_REG_ROM_VER2,
4904 &cur_limiting_mode);
de6eae1f
YR		 4905 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
4906 cur_limiting_mode);
4907
4908 if (edc_mode == EDC_MODE_LIMITING) {
cd88ccee 4909 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
e10bc84d 4910 bnx2x_cl45_write(bp, phy,
62b29a5d 4911 MDIO_PMA_DEVAD,
de6eae1f
YR		 4912 MDIO_PMA_REG_ROM_VER2,
4913 EDC_MODE_LIMITING);
4914 } else { /* LRM mode ( default )*/
4d295db0 4915
de6eae1f 4916 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
4d295db0 4917
2cf7acf9
YR		 4918 /*
4919 * Changing to LRM mode takes quite few seconds. So do it only
4920 * if current mode is limiting (default is LRM)
4921 */
de6eae1f
YR		 4922 if (cur_limiting_mode != EDC_MODE_LIMITING)
4923 return 0;
4d295db0 4924
de6eae1f 4925 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 4926 MDIO_PMA_DEVAD,
4927 MDIO_PMA_REG_LRM_MODE,
4928 0);
de6eae1f 4929 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 4930 MDIO_PMA_DEVAD,
4931 MDIO_PMA_REG_ROM_VER2,
4932 0x128);
de6eae1f 4933 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 4934 MDIO_PMA_DEVAD,
4935 MDIO_PMA_REG_MISC_CTRL0,
4936 0x4008);
de6eae1f 4937 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 4938 MDIO_PMA_DEVAD,
4939 MDIO_PMA_REG_LRM_MODE,
4940 0xaaaa);
4d295db0 4941 }
de6eae1f 4942 return 0;
4d295db0
EG		 4943}
4944
de6eae1f
YR		 4945static u8 bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
4946 struct bnx2x_phy *phy,
cd88ccee 4947 u16 edc_mode)
ea4e040a 4948{
de6eae1f
YR		 4949 u16 phy_identifier;
4950 u16 rom_ver2_val;
62b29a5d 4951 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 4952 MDIO_PMA_DEVAD,
4953 MDIO_PMA_REG_PHY_IDENTIFIER,
4954 &phy_identifier);
ea4e040a 4955
de6eae1f 4956 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 4957 MDIO_PMA_DEVAD,
4958 MDIO_PMA_REG_PHY_IDENTIFIER,
4959 (phy_identifier & ~(1<<9)));
ea4e040a 4960
62b29a5d 4961 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 4962 MDIO_PMA_DEVAD,
4963 MDIO_PMA_REG_ROM_VER2,
4964 &rom_ver2_val);
de6eae1f
YR		 4965 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
4966 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 4967 MDIO_PMA_DEVAD,
4968 MDIO_PMA_REG_ROM_VER2,
4969 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
4d295db0 4970
de6eae1f 4971 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 4972 MDIO_PMA_DEVAD,
4973 MDIO_PMA_REG_PHY_IDENTIFIER,
4974 (phy_identifier | (1<<9)));
4d295db0 4975
de6eae1f 4976 return 0;
b7737c9b 4977}
ea4e040a 4978
a22f0788
YR		 4979static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
4980 struct link_params *params,
4981 u32 action)
4982{
4983 struct bnx2x *bp = params->bp;
4984
4985 switch (action) {
4986 case DISABLE_TX:
a8db5b4c 4987 bnx2x_sfp_set_transmitter(params, phy, 0);
a22f0788
YR		 4988 break;
4989 case ENABLE_TX:
4990 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
a8db5b4c 4991 bnx2x_sfp_set_transmitter(params, phy, 1);
a22f0788
YR		 4992 break;
4993 default:
4994 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
4995 action);
4996 return;
4997 }
4998}
4999
a8db5b4c
YR		 5000static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
5001 u8 gpio_mode)
5002{
5003 struct bnx2x *bp = params->bp;
5004
5005 u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
5006 offsetof(struct shmem_region,
5007 dev_info.port_hw_config[params->port].sfp_ctrl)) &
5008 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
5009 switch (fault_led_gpio) {
5010 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
5011 return;
5012 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
5013 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
5014 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
5015 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
5016 {
5017 u8 gpio_port = bnx2x_get_gpio_port(params);
5018 u16 gpio_pin = fault_led_gpio -
5019 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
5020 DP(NETIF_MSG_LINK, "Set fault module-detected led "
5021 "pin %x port %x mode %x\n",
5022 gpio_pin, gpio_port, gpio_mode);
5023 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
5024 }
5025 break;
5026 default:
5027 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
5028 fault_led_gpio);
5029 }
5030}
5031
e4d78f12
YR		 5032static void bnx2x_power_sfp_module(struct link_params *params,
5033 struct bnx2x_phy *phy,
5034 u8 power)
5035{
5036 struct bnx2x *bp = params->bp;
5037 DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
5038
5039 switch (phy->type) {
5040 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
5041 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
5042 bnx2x_8727_power_module(params->bp, phy, power);
5043 break;
5044 default:
5045 break;
5046 }
5047}
5048
5049static void bnx2x_set_limiting_mode(struct link_params *params,
5050 struct bnx2x_phy *phy,
5051 u16 edc_mode)
5052{
5053 switch (phy->type) {
5054 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
5055 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
5056 break;
5057 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
5058 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
5059 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
5060 break;
5061 }
5062}
5063
de6eae1f
YR		 5064static u8 bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
5065 struct link_params *params)
b7737c9b 5066{
b7737c9b 5067 struct bnx2x *bp = params->bp;
de6eae1f
YR		 5068 u16 edc_mode;
5069 u8 rc = 0;
ea4e040a 5070
de6eae1f
YR		 5071 u32 val = REG_RD(bp, params->shmem_base +
5072 offsetof(struct shmem_region, dev_info.
5073 port_feature_config[params->port].config));
62b29a5d 5074
de6eae1f
YR		 5075 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
5076 params->port);
e4d78f12
YR		 5077 /* Power up module */
5078 bnx2x_power_sfp_module(params, phy, 1);
de6eae1f
YR		 5079 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
5080 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
5081 return -EINVAL;
cd88ccee 5082 } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
de6eae1f
YR		 5083 /* check SFP+ module compatibility */
5084 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
5085 rc = -EINVAL;
5086 /* Turn on fault module-detected led */
a8db5b4c
YR		 5087 bnx2x_set_sfp_module_fault_led(params,
5088 MISC_REGISTERS_GPIO_HIGH);
5089
e4d78f12
YR		 5090 /* Check if need to power down the SFP+ module */
5091 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
5092 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
de6eae1f 5093 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
e4d78f12 5094 bnx2x_power_sfp_module(params, phy, 0);
de6eae1f
YR		 5095 return rc;
5096 }
5097 } else {
5098 /* Turn off fault module-detected led */
a8db5b4c 5099 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
62b29a5d 5100 }
b7737c9b 5101
2cf7acf9
YR		 5102 /*
5103 * Check and set limiting mode / LRM mode on 8726. On 8727 it
5104 * is done automatically
5105 */
e4d78f12
YR		 5106 bnx2x_set_limiting_mode(params, phy, edc_mode);
5107
de6eae1f
YR		 5108 /*
5109 * Enable transmit for this module if the module is approved, or
5110 * if unapproved modules should also enable the Tx laser
5111 */
5112 if (rc == 0 ||
5113 (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
5114 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
a8db5b4c 5115 bnx2x_sfp_set_transmitter(params, phy, 1);
de6eae1f 5116 else
a8db5b4c 5117 bnx2x_sfp_set_transmitter(params, phy, 0);
b7737c9b 5118
de6eae1f
YR		 5119 return rc;
5120}
5121
5122void bnx2x_handle_module_detect_int(struct link_params *params)
b7737c9b
YR		 5123{
5124 struct bnx2x *bp = params->bp;
de6eae1f
YR		 5125 struct bnx2x_phy *phy = &params->phy[EXT_PHY1];
5126 u32 gpio_val;
5127 u8 port = params->port;
4d295db0 5128
de6eae1f 5129 /* Set valid module led off */
a8db5b4c 5130 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
4d295db0 5131
2cf7acf9 5132 /* Get current gpio val reflecting module plugged in / out*/
de6eae1f 5133 gpio_val = bnx2x_get_gpio(bp, MISC_REGISTERS_GPIO_3, port);
62b29a5d 5134
de6eae1f
YR		 5135 /* Call the handling function in case module is detected */
5136 if (gpio_val == 0) {
e4d78f12 5137 bnx2x_power_sfp_module(params, phy, 1);
de6eae1f
YR		 5138 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
5139 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
5140 port);
4d295db0 5141
de6eae1f
YR		 5142 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
5143 bnx2x_sfp_module_detection(phy, params);
5144 else
5145 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
5146 } else {
5147 u32 val = REG_RD(bp, params->shmem_base +
cd88ccee
YR		 5148 offsetof(struct shmem_region, dev_info.
5149 port_feature_config[params->port].
5150 config));
4d295db0 5151
de6eae1f
YR		 5152 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
5153 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
5154 port);
2cf7acf9
YR		 5155 /*
5156 * Module was plugged out.
5157 * Disable transmit for this module
5158 */
de6eae1f
YR		 5159 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
5160 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
a8db5b4c 5161 bnx2x_sfp_set_transmitter(params, phy, 0);
62b29a5d 5162 }
de6eae1f 5163}
62b29a5d 5164
de6eae1f
YR		 5165/******************************************************************/
5166/* common BCM8706/BCM8726 PHY SECTION */
5167/******************************************************************/
5168static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
5169 struct link_params *params,
5170 struct link_vars *vars)
5171{
5172 u8 link_up = 0;
5173 u16 val1, val2, rx_sd, pcs_status;
5174 struct bnx2x *bp = params->bp;
5175 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
5176 /* Clear RX Alarm*/
62b29a5d 5177 bnx2x_cl45_read(bp, phy,
de6eae1f
YR		 5178 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2);
5179 /* clear LASI indication*/
5180 bnx2x_cl45_read(bp, phy,
5181 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
5182 bnx2x_cl45_read(bp, phy,
5183 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2);
5184 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
62b29a5d
YR		 5185
5186 bnx2x_cl45_read(bp, phy,
de6eae1f
YR		 5187 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
5188 bnx2x_cl45_read(bp, phy,
5189 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
5190 bnx2x_cl45_read(bp, phy,
5191 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
5192 bnx2x_cl45_read(bp, phy,
5193 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
62b29a5d 5194
de6eae1f
YR		 5195 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
5196 " link_status 0x%x\n", rx_sd, pcs_status, val2);
2cf7acf9
YR		 5197 /*
5198 * link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
5199 * are set, or if the autoneg bit 1 is set
de6eae1f
YR		 5200 */
5201 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
5202 if (link_up) {
5203 if (val2 & (1<<1))
5204 vars->line_speed = SPEED_1000;
5205 else
5206 vars->line_speed = SPEED_10000;
62b29a5d 5207 bnx2x_ext_phy_resolve_fc(phy, params, vars);
791f18c0 5208 vars->duplex = DUPLEX_FULL;
de6eae1f 5209 }
62b29a5d 5210 return link_up;
b7737c9b 5211}
62b29a5d 5212
de6eae1f
YR		 5213/******************************************************************/
5214/* BCM8706 PHY SECTION */
5215/******************************************************************/
5216static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
b7737c9b
YR		 5217 struct link_params *params,
5218 struct link_vars *vars)
5219{
a8db5b4c
YR		 5220 u32 tx_en_mode;
5221 u16 cnt, val, tmp1;
b7737c9b 5222 struct bnx2x *bp = params->bp;
de6eae1f 5223 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
cd88ccee 5224 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
de6eae1f
YR		 5225 /* HW reset */
5226 bnx2x_ext_phy_hw_reset(bp, params->port);
5227 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
6d870c39 5228 bnx2x_wait_reset_complete(bp, phy, params);
ea4e040a 5229
de6eae1f
YR		 5230 /* Wait until fw is loaded */
5231 for (cnt = 0; cnt < 100; cnt++) {
5232 bnx2x_cl45_read(bp, phy,
5233 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
5234 if (val)
5235 break;
5236 msleep(10);
5237 }
5238 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
5239 if ((params->feature_config_flags &
5240 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
5241 u8 i;
5242 u16 reg;
5243 for (i = 0; i < 4; i++) {
5244 reg = MDIO_XS_8706_REG_BANK_RX0 +
5245 i*(MDIO_XS_8706_REG_BANK_RX1 -
5246 MDIO_XS_8706_REG_BANK_RX0);
5247 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
5248 /* Clear first 3 bits of the control */
5249 val &= ~0x7;
5250 /* Set control bits according to configuration */
5251 val |= (phy->rx_preemphasis[i] & 0x7);
5252 DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
5253 " reg 0x%x <-- val 0x%x\n", reg, val);
5254 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
5255 }
5256 }
5257 /* Force speed */
5258 if (phy->req_line_speed == SPEED_10000) {
5259 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
ea4e040a 5260
de6eae1f
YR		 5261 bnx2x_cl45_write(bp, phy,
5262 MDIO_PMA_DEVAD,
5263 MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
5264 bnx2x_cl45_write(bp, phy,
5265 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 1);
5266 } else {
25985edc 5267 /* Force 1Gbps using autoneg with 1G advertisement */
6bbca910 5268
de6eae1f
YR		 5269 /* Allow CL37 through CL73 */
5270 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
5271 bnx2x_cl45_write(bp, phy,
5272 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
6bbca910 5273
25985edc 5274 /* Enable Full-Duplex advertisement on CL37 */
de6eae1f
YR		 5275 bnx2x_cl45_write(bp, phy,
5276 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
5277 /* Enable CL37 AN */
5278 bnx2x_cl45_write(bp, phy,
5279 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
5280 /* 1G support */
5281 bnx2x_cl45_write(bp, phy,
5282 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
6bbca910 5283
de6eae1f
YR		 5284 /* Enable clause 73 AN */
5285 bnx2x_cl45_write(bp, phy,
5286 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
5287 bnx2x_cl45_write(bp, phy,
5288 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5289 0x0400);
5290 bnx2x_cl45_write(bp, phy,
5291 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,
5292 0x0004);
5293 }
5294 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
a8db5b4c
YR		 5295
5296 /*
5297 * If TX Laser is controlled by GPIO_0, do not let PHY go into low
5298 * power mode, if TX Laser is disabled
5299 */
5300
5301 tx_en_mode = REG_RD(bp, params->shmem_base +
5302 offsetof(struct shmem_region,
5303 dev_info.port_hw_config[params->port].sfp_ctrl))
5304 & PORT_HW_CFG_TX_LASER_MASK;
5305
5306 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
5307 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
5308 bnx2x_cl45_read(bp, phy,
5309 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
5310 tmp1 |= 0x1;
5311 bnx2x_cl45_write(bp, phy,
5312 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
5313 }
5314
de6eae1f
YR		 5315 return 0;
5316}
ea4e040a 5317
de6eae1f
YR		 5318static u8 bnx2x_8706_read_status(struct bnx2x_phy *phy,
5319 struct link_params *params,
5320 struct link_vars *vars)
5321{
5322 return bnx2x_8706_8726_read_status(phy, params, vars);
5323}
6bbca910 5324
de6eae1f
YR		 5325/******************************************************************/
5326/* BCM8726 PHY SECTION */
5327/******************************************************************/
5328static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
5329 struct link_params *params)
5330{
5331 struct bnx2x *bp = params->bp;
5332 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
5333 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
5334}
62b29a5d 5335
de6eae1f
YR		 5336static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
5337 struct link_params *params)
5338{
5339 struct bnx2x *bp = params->bp;
5340 /* Need to wait 100ms after reset */
5341 msleep(100);
62b29a5d 5342
de6eae1f
YR		 5343 /* Micro controller re-boot */
5344 bnx2x_cl45_write(bp, phy,
5345 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
62b29a5d 5346
de6eae1f
YR		 5347 /* Set soft reset */
5348 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 5349 MDIO_PMA_DEVAD,
5350 MDIO_PMA_REG_GEN_CTRL,
5351 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
62b29a5d 5352
de6eae1f 5353 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 5354 MDIO_PMA_DEVAD,
5355 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
6bbca910 5356
de6eae1f 5357 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 5358 MDIO_PMA_DEVAD,
5359 MDIO_PMA_REG_GEN_CTRL,
5360 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
de6eae1f
YR		 5361
5362 /* wait for 150ms for microcode load */
5363 msleep(150);
5364
5365 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
5366 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 5367 MDIO_PMA_DEVAD,
5368 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
de6eae1f
YR		 5369
5370 msleep(200);
5371 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
b7737c9b
YR		 5372}
5373
de6eae1f 5374static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
b7737c9b
YR		 5375 struct link_params *params,
5376 struct link_vars *vars)
5377{
5378 struct bnx2x *bp = params->bp;
de6eae1f
YR		 5379 u16 val1;
5380 u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
62b29a5d
YR		 5381 if (link_up) {
5382 bnx2x_cl45_read(bp, phy,
de6eae1f
YR		 5383 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
5384 &val1);
5385 if (val1 & (1<<15)) {
5386 DP(NETIF_MSG_LINK, "Tx is disabled\n");
5387 link_up = 0;
5388 vars->line_speed = 0;
5389 }
62b29a5d
YR		 5390 }
5391 return link_up;
b7737c9b
YR		 5392}
5393
de6eae1f
YR		 5394
5395static u8 bnx2x_8726_config_init(struct bnx2x_phy *phy,
5396 struct link_params *params,
5397 struct link_vars *vars)
b7737c9b
YR		 5398{
5399 struct bnx2x *bp = params->bp;
de6eae1f
YR		 5400 u32 val;
5401 u32 swap_val, swap_override, aeu_gpio_mask, offset;
5402 DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
62b29a5d 5403
de6eae1f 5404 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
6d870c39 5405 bnx2x_wait_reset_complete(bp, phy, params);
62b29a5d 5406
de6eae1f 5407 bnx2x_8726_external_rom_boot(phy, params);
62b29a5d 5408
2cf7acf9
YR		 5409 /*
5410 * Need to call module detected on initialization since the module
5411 * detection triggered by actual module insertion might occur before
5412 * driver is loaded, and when driver is loaded, it reset all
5413 * registers, including the transmitter
5414 */
de6eae1f 5415 bnx2x_sfp_module_detection(phy, params);
62b29a5d 5416
de6eae1f
YR		 5417 if (phy->req_line_speed == SPEED_1000) {
5418 DP(NETIF_MSG_LINK, "Setting 1G force\n");
5419 bnx2x_cl45_write(bp, phy,
5420 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
5421 bnx2x_cl45_write(bp, phy,
5422 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
5423 bnx2x_cl45_write(bp, phy,
5424 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x5);
5425 bnx2x_cl45_write(bp, phy,
5426 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5427 0x400);
5428 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5429 (phy->speed_cap_mask &
5430 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
5431 ((phy->speed_cap_mask &
5432 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
5433 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
5434 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
5435 /* Set Flow control */
5436 bnx2x_ext_phy_set_pause(params, phy, vars);
5437 bnx2x_cl45_write(bp, phy,
5438 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
5439 bnx2x_cl45_write(bp, phy,
5440 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
5441 bnx2x_cl45_write(bp, phy,
5442 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
5443 bnx2x_cl45_write(bp, phy,
5444 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
5445 bnx2x_cl45_write(bp, phy,
5446 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
2cf7acf9
YR		 5447 /*
5448 * Enable RX-ALARM control to receive interrupt for 1G speed
5449 * change
5450 */
de6eae1f
YR		 5451 bnx2x_cl45_write(bp, phy,
5452 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x4);
5453 bnx2x_cl45_write(bp, phy,
5454 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5455 0x400);
62b29a5d 5456
de6eae1f
YR		 5457 } else { /* Default 10G. Set only LASI control */
5458 bnx2x_cl45_write(bp, phy,
5459 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 1);
7aa0711f
YR		 5460 }
5461
de6eae1f
YR		 5462 /* Set TX PreEmphasis if needed */
5463 if ((params->feature_config_flags &
5464 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
5465 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
5466 "TX_CTRL2 0x%x\n",
5467 phy->tx_preemphasis[0],
5468 phy->tx_preemphasis[1]);
5469 bnx2x_cl45_write(bp, phy,
5470 MDIO_PMA_DEVAD,
5471 MDIO_PMA_REG_8726_TX_CTRL1,
5472 phy->tx_preemphasis[0]);
c18aa15d 5473
de6eae1f
YR		 5474 bnx2x_cl45_write(bp, phy,
5475 MDIO_PMA_DEVAD,
5476 MDIO_PMA_REG_8726_TX_CTRL2,
5477 phy->tx_preemphasis[1]);
5478 }
ab6ad5a4 5479
de6eae1f
YR		 5480 /* Set GPIO3 to trigger SFP+ module insertion/removal */
5481 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
cd88ccee 5482 MISC_REGISTERS_GPIO_INPUT_HI_Z, params->port);
ea4e040a 5483
de6eae1f
YR		 5484 /* The GPIO should be swapped if the swap register is set and active */
5485 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
5486 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
ea4e040a 5487
de6eae1f
YR		 5488 /* Select function upon port-swap configuration */
5489 if (params->port == 0) {
5490 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5491 aeu_gpio_mask = (swap_val && swap_override) ?
5492 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 :
5493 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0;
5494 } else {
5495 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
5496 aeu_gpio_mask = (swap_val && swap_override) ?
5497 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 :
5498 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1;
ea4e040a 5499 }
de6eae1f
YR		 5500 val = REG_RD(bp, offset);
5501 /* add GPIO3 to group */
5502 val |= aeu_gpio_mask;
5503 REG_WR(bp, offset, val);
5504 return 0;
ab6ad5a4 5505
ea4e040a
YR		 5506}
5507
de6eae1f
YR		 5508static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
5509 struct link_params *params)
2f904460 5510{
de6eae1f
YR		 5511 struct bnx2x *bp = params->bp;
5512 DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
5513 /* Set serial boot control for external load */
5514 bnx2x_cl45_write(bp, phy,
5515 MDIO_PMA_DEVAD,
5516 MDIO_PMA_REG_GEN_CTRL, 0x0001);
5517}
5518
5519/******************************************************************/
5520/* BCM8727 PHY SECTION */
5521/******************************************************************/
7f02c4ad
YR		 5522
5523static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
5524 struct link_params *params, u8 mode)
5525{
5526 struct bnx2x *bp = params->bp;
5527 u16 led_mode_bitmask = 0;
5528 u16 gpio_pins_bitmask = 0;
5529 u16 val;
5530 /* Only NOC flavor requires to set the LED specifically */
5531 if (!(phy->flags & FLAGS_NOC))
5532 return;
5533 switch (mode) {
5534 case LED_MODE_FRONT_PANEL_OFF:
5535 case LED_MODE_OFF:
5536 led_mode_bitmask = 0;
5537 gpio_pins_bitmask = 0x03;
5538 break;
5539 case LED_MODE_ON:
5540 led_mode_bitmask = 0;
5541 gpio_pins_bitmask = 0x02;
5542 break;
5543 case LED_MODE_OPER:
5544 led_mode_bitmask = 0x60;
5545 gpio_pins_bitmask = 0x11;
5546 break;
5547 }
5548 bnx2x_cl45_read(bp, phy,
5549 MDIO_PMA_DEVAD,
5550 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
5551 &val);
5552 val &= 0xff8f;
5553 val |= led_mode_bitmask;
5554 bnx2x_cl45_write(bp, phy,
5555 MDIO_PMA_DEVAD,
5556 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
5557 val);
5558 bnx2x_cl45_read(bp, phy,
5559 MDIO_PMA_DEVAD,
5560 MDIO_PMA_REG_8727_GPIO_CTRL,
5561 &val);
5562 val &= 0xffe0;
5563 val |= gpio_pins_bitmask;
5564 bnx2x_cl45_write(bp, phy,
5565 MDIO_PMA_DEVAD,
5566 MDIO_PMA_REG_8727_GPIO_CTRL,
5567 val);
5568}
de6eae1f
YR		 5569static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
5570 struct link_params *params) {
5571 u32 swap_val, swap_override;
5572 u8 port;
2cf7acf9 5573 /*
de6eae1f
YR		 5574 * The PHY reset is controlled by GPIO 1. Fake the port number
5575 * to cancel the swap done in set_gpio()
2f904460 5576 */
de6eae1f
YR		 5577 struct bnx2x *bp = params->bp;
5578 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
5579 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
5580 port = (swap_val && swap_override) ^ 1;
5581 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
cd88ccee 5582 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
2f904460 5583}
e10bc84d 5584
de6eae1f
YR		 5585static u8 bnx2x_8727_config_init(struct bnx2x_phy *phy,
5586 struct link_params *params,
5587 struct link_vars *vars)
ea4e040a 5588{
a8db5b4c
YR		 5589 u32 tx_en_mode;
5590 u16 tmp1, val, mod_abs, tmp2;
de6eae1f
YR		 5591 u16 rx_alarm_ctrl_val;
5592 u16 lasi_ctrl_val;
ea4e040a 5593 struct bnx2x *bp = params->bp;
de6eae1f 5594 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
ea4e040a 5595
6d870c39 5596 bnx2x_wait_reset_complete(bp, phy, params);
de6eae1f
YR		 5597 rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
5598 lasi_ctrl_val = 0x0004;
ea4e040a 5599
de6eae1f
YR		 5600 DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
5601 /* enable LASI */
5602 bnx2x_cl45_write(bp, phy,
5603 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5604 rx_alarm_ctrl_val);
ea4e040a 5605
de6eae1f
YR		 5606 bnx2x_cl45_write(bp, phy,
5607 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, lasi_ctrl_val);
ea4e040a 5608
2cf7acf9
YR		 5609 /*
5610 * Initially configure MOD_ABS to interrupt when module is
5611 * presence( bit 8)
5612 */
de6eae1f
YR		 5613 bnx2x_cl45_read(bp, phy,
5614 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
2cf7acf9
YR		 5615 /*
5616 * Set EDC off by setting OPTXLOS signal input to low (bit 9).
5617 * When the EDC is off it locks onto a reference clock and avoids
5618 * becoming 'lost'
5619 */
7f02c4ad
YR		 5620 mod_abs &= ~(1<<8);
5621 if (!(phy->flags & FLAGS_NOC))
5622 mod_abs &= ~(1<<9);
de6eae1f
YR		 5623 bnx2x_cl45_write(bp, phy,
5624 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
ea4e040a 5625
ea4e040a 5626
de6eae1f
YR		 5627 /* Make MOD_ABS give interrupt on change */
5628 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
5629 &val);
5630 val |= (1<<12);
7f02c4ad
YR		 5631 if (phy->flags & FLAGS_NOC)
5632 val |= (3<<5);
b7737c9b 5633
2cf7acf9 5634 /*
7f02c4ad
YR		 5635 * Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
5636 * status which reflect SFP+ module over-current
5637 */
5638 if (!(phy->flags & FLAGS_NOC))
5639 val &= 0xff8f; /* Reset bits 4-6 */
de6eae1f
YR		 5640 bnx2x_cl45_write(bp, phy,
5641 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
ea4e040a 5642
de6eae1f
YR		 5643 bnx2x_8727_power_module(bp, phy, 1);
5644
5645 bnx2x_cl45_read(bp, phy,
5646 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
5647
5648 bnx2x_cl45_read(bp, phy,
5649 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1);
5650
5651 /* Set option 1G speed */
5652 if (phy->req_line_speed == SPEED_1000) {
5653 DP(NETIF_MSG_LINK, "Setting 1G force\n");
5654 bnx2x_cl45_write(bp, phy,
5655 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
5656 bnx2x_cl45_write(bp, phy,
5657 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
5658 bnx2x_cl45_read(bp, phy,
5659 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
5660 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
2cf7acf9 5661 /*
a22f0788
YR		 5662 * Power down the XAUI until link is up in case of dual-media
5663 * and 1G
5664 */
5665 if (DUAL_MEDIA(params)) {
5666 bnx2x_cl45_read(bp, phy,
5667 MDIO_PMA_DEVAD,
5668 MDIO_PMA_REG_8727_PCS_GP, &val);
5669 val |= (3<<10);
5670 bnx2x_cl45_write(bp, phy,
5671 MDIO_PMA_DEVAD,
5672 MDIO_PMA_REG_8727_PCS_GP, val);
5673 }
de6eae1f
YR		 5674 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5675 ((phy->speed_cap_mask &
5676 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
5677 ((phy->speed_cap_mask &
5678 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
5679 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
5680
5681 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
5682 bnx2x_cl45_write(bp, phy,
5683 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
5684 bnx2x_cl45_write(bp, phy,
5685 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
5686 } else {
2cf7acf9 5687 /*
de6eae1f
YR		 5688 * Since the 8727 has only single reset pin, need to set the 10G
5689 * registers although it is default
5690 */
5691 bnx2x_cl45_write(bp, phy,
5692 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
5693 0x0020);
5694 bnx2x_cl45_write(bp, phy,
5695 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
5696 bnx2x_cl45_write(bp, phy,
5697 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
5698 bnx2x_cl45_write(bp, phy,
5699 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
5700 0x0008);
ea4e040a 5701 }
ea4e040a 5702
2cf7acf9
YR		 5703 /*
5704 * Set 2-wire transfer rate of SFP+ module EEPROM
de6eae1f
YR		 5705 * to 100Khz since some DACs(direct attached cables) do
5706 * not work at 400Khz.
5707 */
5708 bnx2x_cl45_write(bp, phy,
5709 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
5710 0xa001);
b7737c9b 5711
de6eae1f
YR		 5712 /* Set TX PreEmphasis if needed */
5713 if ((params->feature_config_flags &
5714 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
5715 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
5716 phy->tx_preemphasis[0],
5717 phy->tx_preemphasis[1]);
5718 bnx2x_cl45_write(bp, phy,
5719 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
5720 phy->tx_preemphasis[0]);
ea4e040a 5721
de6eae1f
YR		 5722 bnx2x_cl45_write(bp, phy,
5723 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
5724 phy->tx_preemphasis[1]);
5725 }
ea4e040a 5726
a8db5b4c
YR		 5727 /*
5728 * If TX Laser is controlled by GPIO_0, do not let PHY go into low
5729 * power mode, if TX Laser is disabled
5730 */
5731 tx_en_mode = REG_RD(bp, params->shmem_base +
5732 offsetof(struct shmem_region,
5733 dev_info.port_hw_config[params->port].sfp_ctrl))
5734 & PORT_HW_CFG_TX_LASER_MASK;
5735
5736 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
5737
5738 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
5739 bnx2x_cl45_read(bp, phy,
5740 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
5741 tmp2 |= 0x1000;
5742 tmp2 &= 0xFFEF;
5743 bnx2x_cl45_write(bp, phy,
5744 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
5745 }
5746
de6eae1f 5747 return 0;
ea4e040a
YR		 5748}
5749
de6eae1f
YR		 5750static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
5751 struct link_params *params)
ea4e040a 5752{
ea4e040a 5753 struct bnx2x *bp = params->bp;
de6eae1f
YR		 5754 u16 mod_abs, rx_alarm_status;
5755 u32 val = REG_RD(bp, params->shmem_base +
5756 offsetof(struct shmem_region, dev_info.
5757 port_feature_config[params->port].
5758 config));
5759 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 5760 MDIO_PMA_DEVAD,
5761 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
de6eae1f 5762 if (mod_abs & (1<<8)) {
ea4e040a 5763
de6eae1f
YR		 5764 /* Module is absent */
5765 DP(NETIF_MSG_LINK, "MOD_ABS indication "
5766 "show module is absent\n");
ea4e040a 5767
2cf7acf9
YR		 5768 /*
5769 * 1. Set mod_abs to detect next module
5770 * presence event
5771 * 2. Set EDC off by setting OPTXLOS signal input to low
5772 * (bit 9).
5773 * When the EDC is off it locks onto a reference clock and
5774 * avoids becoming 'lost'.
5775 */
7f02c4ad
YR		 5776 mod_abs &= ~(1<<8);
5777 if (!(phy->flags & FLAGS_NOC))
5778 mod_abs &= ~(1<<9);
de6eae1f 5779 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 5780 MDIO_PMA_DEVAD,
5781 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
ea4e040a 5782
2cf7acf9
YR		 5783 /*
5784 * Clear RX alarm since it stays up as long as
5785 * the mod_abs wasn't changed
5786 */
de6eae1f 5787 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 5788 MDIO_PMA_DEVAD,
5789 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
ea4e040a 5790
de6eae1f
YR		 5791 } else {
5792 /* Module is present */
5793 DP(NETIF_MSG_LINK, "MOD_ABS indication "
5794 "show module is present\n");
2cf7acf9
YR		 5795 /*
5796 * First disable transmitter, and if the module is ok, the
5797 * module_detection will enable it
5798 * 1. Set mod_abs to detect next module absent event ( bit 8)
5799 * 2. Restore the default polarity of the OPRXLOS signal and
5800 * this signal will then correctly indicate the presence or
5801 * absence of the Rx signal. (bit 9)
5802 */
7f02c4ad
YR		 5803 mod_abs |= (1<<8);
5804 if (!(phy->flags & FLAGS_NOC))
5805 mod_abs |= (1<<9);
e10bc84d 5806 bnx2x_cl45_write(bp, phy,
de6eae1f
YR		 5807 MDIO_PMA_DEVAD,
5808 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
ea4e040a 5809
2cf7acf9
YR		 5810 /*
5811 * Clear RX alarm since it stays up as long as the mod_abs
5812 * wasn't changed. This is need to be done before calling the
5813 * module detection, otherwise it will clear* the link update
5814 * alarm
5815 */
de6eae1f
YR		 5816 bnx2x_cl45_read(bp, phy,
5817 MDIO_PMA_DEVAD,
5818 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
ea4e040a 5819
ea4e040a 5820
de6eae1f
YR		 5821 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
5822 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
a8db5b4c 5823 bnx2x_sfp_set_transmitter(params, phy, 0);
de6eae1f
YR		 5824
5825 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
5826 bnx2x_sfp_module_detection(phy, params);
5827 else
5828 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
ea4e040a 5829 }
de6eae1f
YR		 5830
5831 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
2cf7acf9
YR		 5832 rx_alarm_status);
5833 /* No need to check link status in case of module plugged in/out */
ea4e040a
YR		 5834}
5835
de6eae1f
YR		 5836static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
5837 struct link_params *params,
5838 struct link_vars *vars)
5839
ea4e040a
YR		 5840{
5841 struct bnx2x *bp = params->bp;
de6eae1f
YR		 5842 u8 link_up = 0;
5843 u16 link_status = 0;
a22f0788
YR		 5844 u16 rx_alarm_status, lasi_ctrl, val1;
5845
5846 /* If PHY is not initialized, do not check link status */
5847 bnx2x_cl45_read(bp, phy,
5848 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,
5849 &lasi_ctrl);
5850 if (!lasi_ctrl)
5851 return 0;
5852
de6eae1f
YR		 5853 /* Check the LASI */
5854 bnx2x_cl45_read(bp, phy,
5855 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM,
5856 &rx_alarm_status);
5857 vars->line_speed = 0;
5858 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status);
5859
5860 bnx2x_cl45_read(bp, phy,
5861 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
5862
5863 DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
5864
5865 /* Clear MSG-OUT */
5866 bnx2x_cl45_read(bp, phy,
5867 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
5868
2cf7acf9 5869 /*
de6eae1f
YR		 5870 * If a module is present and there is need to check
5871 * for over current
5872 */
5873 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
5874 /* Check over-current using 8727 GPIO0 input*/
5875 bnx2x_cl45_read(bp, phy,
5876 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
5877 &val1);
5878
5879 if ((val1 & (1<<8)) == 0) {
5880 DP(NETIF_MSG_LINK, "8727 Power fault has been detected"
5881 " on port %d\n", params->port);
5882 netdev_err(bp->dev, "Error: Power fault on Port %d has"
5883 " been detected and the power to "
5884 "that SFP+ module has been removed"
5885 " to prevent failure of the card."
5886 " Please remove the SFP+ module and"
5887 " restart the system to clear this"
5888 " error.\n",
2cf7acf9
YR		 5889 params->port);
5890 /* Disable all RX_ALARMs except for mod_abs */
de6eae1f
YR		 5891 bnx2x_cl45_write(bp, phy,
5892 MDIO_PMA_DEVAD,
5893 MDIO_PMA_REG_RX_ALARM_CTRL, (1<<5));
5894
5895 bnx2x_cl45_read(bp, phy,
5896 MDIO_PMA_DEVAD,
5897 MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
5898 /* Wait for module_absent_event */
5899 val1 |= (1<<8);
5900 bnx2x_cl45_write(bp, phy,
5901 MDIO_PMA_DEVAD,
5902 MDIO_PMA_REG_PHY_IDENTIFIER, val1);
5903 /* Clear RX alarm */
5904 bnx2x_cl45_read(bp, phy,
5905 MDIO_PMA_DEVAD,
5906 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
5907 return 0;
5908 }
5909 } /* Over current check */
5910
5911 /* When module absent bit is set, check module */
5912 if (rx_alarm_status & (1<<5)) {
5913 bnx2x_8727_handle_mod_abs(phy, params);
5914 /* Enable all mod_abs and link detection bits */
5915 bnx2x_cl45_write(bp, phy,
5916 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5917 ((1<<5) | (1<<2)));
5918 }
a22f0788
YR		 5919 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser if SFP is approved\n");
5920 bnx2x_8727_specific_func(phy, params, ENABLE_TX);
de6eae1f
YR		 5921 /* If transmitter is disabled, ignore false link up indication */
5922 bnx2x_cl45_read(bp, phy,
5923 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
5924 if (val1 & (1<<15)) {
5925 DP(NETIF_MSG_LINK, "Tx is disabled\n");
5926 return 0;
5927 }
5928
5929 bnx2x_cl45_read(bp, phy,
5930 MDIO_PMA_DEVAD,
5931 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
5932
2cf7acf9
YR		 5933 /*
5934 * Bits 0..2 --> speed detected,
5935 * Bits 13..15--> link is down
5936 */
de6eae1f
YR		 5937 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
5938 link_up = 1;
5939 vars->line_speed = SPEED_10000;
2cf7acf9
YR		 5940 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
5941 params->port);
de6eae1f
YR		 5942 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
5943 link_up = 1;
5944 vars->line_speed = SPEED_1000;
5945 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
5946 params->port);
5947 } else {
5948 link_up = 0;
5949 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
5950 params->port);
5951 }
791f18c0 5952 if (link_up) {
de6eae1f 5953 bnx2x_ext_phy_resolve_fc(phy, params, vars);
791f18c0
YR		 5954 vars->duplex = DUPLEX_FULL;
5955 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
5956 }
a22f0788
YR		 5957
5958 if ((DUAL_MEDIA(params)) &&
5959 (phy->req_line_speed == SPEED_1000)) {
5960 bnx2x_cl45_read(bp, phy,
5961 MDIO_PMA_DEVAD,
5962 MDIO_PMA_REG_8727_PCS_GP, &val1);
2cf7acf9 5963 /*
a22f0788
YR		 5964 * In case of dual-media board and 1G, power up the XAUI side,
5965 * otherwise power it down. For 10G it is done automatically
5966 */
5967 if (link_up)
5968 val1 &= ~(3<<10);
5969 else
5970 val1 |= (3<<10);
5971 bnx2x_cl45_write(bp, phy,
5972 MDIO_PMA_DEVAD,
5973 MDIO_PMA_REG_8727_PCS_GP, val1);
5974 }
de6eae1f 5975 return link_up;
b7737c9b 5976}
ea4e040a 5977
de6eae1f
YR		 5978static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
5979 struct link_params *params)
b7737c9b
YR		 5980{
5981 struct bnx2x *bp = params->bp;
de6eae1f 5982 /* Disable Transmitter */
a8db5b4c 5983 bnx2x_sfp_set_transmitter(params, phy, 0);
a22f0788
YR		 5984 /* Clear LASI */
5985 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0);
5986
ea4e040a 5987}
c18aa15d 5988
de6eae1f
YR		 5989/******************************************************************/
5990/* BCM8481/BCM84823/BCM84833 PHY SECTION */
5991/******************************************************************/
5992static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
5993 struct link_params *params)
ea4e040a 5994{
c87bca1e 5995 u16 val, fw_ver1, fw_ver2, cnt, adj;
de6eae1f 5996 struct bnx2x *bp = params->bp;
ea4e040a 5997
c87bca1e
YR		 5998 adj = 0;
5999 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
6000 adj = -1;
6001
de6eae1f
YR		 6002 /* For the 32 bits registers in 848xx, access via MDIO2ARM interface.*/
6003 /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
c87bca1e
YR		 6004 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819 + adj, 0x0014);
6005 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A + adj, 0xc200);
6006 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B + adj, 0x0000);
6007 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C + adj, 0x0300);
6008 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817 + adj, 0x0009);
ea4e040a 6009
de6eae1f 6010 for (cnt = 0; cnt < 100; cnt++) {
c87bca1e 6011 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818 + adj, &val);
de6eae1f
YR		 6012 if (val & 1)
6013 break;
6014 udelay(5);
6015 }
6016 if (cnt == 100) {
6017 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(1)\n");
6018 bnx2x_save_spirom_version(bp, params->port, 0,
6019 phy->ver_addr);
6020 return;
6021 }
ea4e040a 6022
ea4e040a 6023
de6eae1f 6024 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
c87bca1e
YR		 6025 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819 + adj, 0x0000);
6026 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A + adj, 0xc200);
6027 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817 + adj, 0x000A);
de6eae1f 6028 for (cnt = 0; cnt < 100; cnt++) {
c87bca1e 6029 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818 + adj, &val);
de6eae1f
YR		 6030 if (val & 1)
6031 break;
6032 udelay(5);
6033 }
6034 if (cnt == 100) {
6035 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(2)\n");
6036 bnx2x_save_spirom_version(bp, params->port, 0,
6037 phy->ver_addr);
6038 return;
ea4e040a
YR		 6039 }
6040
de6eae1f 6041 /* lower 16 bits of the register SPI_FW_STATUS */
c87bca1e 6042 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B + adj, &fw_ver1);
de6eae1f 6043 /* upper 16 bits of register SPI_FW_STATUS */
c87bca1e 6044 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C + adj, &fw_ver2);
ea4e040a 6045
de6eae1f
YR		 6046 bnx2x_save_spirom_version(bp, params->port, (fw_ver2<<16) | fw_ver1,
6047 phy->ver_addr);
6048}
ea4e040a 6049
de6eae1f
YR		 6050static void bnx2x_848xx_set_led(struct bnx2x *bp,
6051 struct bnx2x_phy *phy)
ea4e040a 6052{
c87bca1e
YR		 6053 u16 val, adj;
6054
6055 adj = 0;
6056 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
6057 adj = -1;
7846e471 6058
de6eae1f
YR		 6059 /* PHYC_CTL_LED_CTL */
6060 bnx2x_cl45_read(bp, phy,
6061 MDIO_PMA_DEVAD,
c87bca1e 6062 MDIO_PMA_REG_8481_LINK_SIGNAL + adj, &val);
de6eae1f
YR		 6063 val &= 0xFE00;
6064 val |= 0x0092;
345b5d52 6065
de6eae1f
YR		 6066 bnx2x_cl45_write(bp, phy,
6067 MDIO_PMA_DEVAD,
c87bca1e 6068 MDIO_PMA_REG_8481_LINK_SIGNAL + adj, val);
ea4e040a 6069
de6eae1f
YR		 6070 bnx2x_cl45_write(bp, phy,
6071 MDIO_PMA_DEVAD,
c87bca1e 6072 MDIO_PMA_REG_8481_LED1_MASK + adj,
de6eae1f 6073 0x80);
ea4e040a 6074
de6eae1f
YR		 6075 bnx2x_cl45_write(bp, phy,
6076 MDIO_PMA_DEVAD,
c87bca1e 6077 MDIO_PMA_REG_8481_LED2_MASK + adj,
de6eae1f 6078 0x18);
ea4e040a 6079
f25b3c8b 6080 /* Select activity source by Tx and Rx, as suggested by PHY AE */
de6eae1f
YR		 6081 bnx2x_cl45_write(bp, phy,
6082 MDIO_PMA_DEVAD,
c87bca1e 6083 MDIO_PMA_REG_8481_LED3_MASK + adj,
f25b3c8b
YR		 6084 0x0006);
6085
6086 /* Select the closest activity blink rate to that in 10/100/1000 */
6087 bnx2x_cl45_write(bp, phy,
6088 MDIO_PMA_DEVAD,
c87bca1e 6089 MDIO_PMA_REG_8481_LED3_BLINK + adj,
f25b3c8b
YR		 6090 0);
6091
6092 bnx2x_cl45_read(bp, phy,
6093 MDIO_PMA_DEVAD,
c87bca1e 6094 MDIO_PMA_REG_84823_CTL_LED_CTL_1 + adj, &val);
f25b3c8b
YR		 6095 val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/
6096
6097 bnx2x_cl45_write(bp, phy,
6098 MDIO_PMA_DEVAD,
c87bca1e 6099 MDIO_PMA_REG_84823_CTL_LED_CTL_1 + adj, val);
ea4e040a 6100
de6eae1f
YR		 6101 /* 'Interrupt Mask' */
6102 bnx2x_cl45_write(bp, phy,
6103 MDIO_AN_DEVAD,
6104 0xFFFB, 0xFFFD);
ea4e040a
YR		 6105}
6106
de6eae1f 6107static u8 bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
a22f0788
YR		 6108 struct link_params *params,
6109 struct link_vars *vars)
ea4e040a 6110{
c18aa15d 6111 struct bnx2x *bp = params->bp;
de6eae1f 6112 u16 autoneg_val, an_1000_val, an_10_100_val;
2cf7acf9
YR		 6113 /*
6114 * This phy uses the NIG latch mechanism since link indication
6115 * arrives through its LED4 and not via its LASI signal, so we
6116 * get steady signal instead of clear on read
6117 */
de6eae1f
YR		 6118 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
6119 1 << NIG_LATCH_BC_ENABLE_MI_INT);
ea4e040a 6120
de6eae1f
YR		 6121 bnx2x_cl45_write(bp, phy,
6122 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
ea4e040a 6123
de6eae1f 6124 bnx2x_848xx_set_led(bp, phy);
ea4e040a 6125
de6eae1f
YR		 6126 /* set 1000 speed advertisement */
6127 bnx2x_cl45_read(bp, phy,
6128 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
6129 &an_1000_val);
57963ed9 6130
de6eae1f
YR		 6131 bnx2x_ext_phy_set_pause(params, phy, vars);
6132 bnx2x_cl45_read(bp, phy,
6133 MDIO_AN_DEVAD,
6134 MDIO_AN_REG_8481_LEGACY_AN_ADV,
6135 &an_10_100_val);
6136 bnx2x_cl45_read(bp, phy,
6137 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
6138 &autoneg_val);
6139 /* Disable forced speed */
6140 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
6141 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
ea4e040a 6142
de6eae1f
YR		 6143 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6144 (phy->speed_cap_mask &
6145 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
6146 (phy->req_line_speed == SPEED_1000)) {
6147 an_1000_val |= (1<<8);
6148 autoneg_val |= (1<<9 | 1<<12);
6149 if (phy->req_duplex == DUPLEX_FULL)
6150 an_1000_val |= (1<<9);
6151 DP(NETIF_MSG_LINK, "Advertising 1G\n");
6152 } else
6153 an_1000_val &= ~((1<<8) | (1<<9));
ea4e040a 6154
de6eae1f
YR		 6155 bnx2x_cl45_write(bp, phy,
6156 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
6157 an_1000_val);
ea4e040a 6158
de6eae1f
YR		 6159 /* set 10 speed advertisement */
6160 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6161 (phy->speed_cap_mask &
6162 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
6163 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
6164 an_10_100_val |= (1<<7);
6165 /* Enable autoneg and restart autoneg for legacy speeds */
6166 autoneg_val |= (1<<9 | 1<<12);
b7737c9b 6167
de6eae1f
YR		 6168 if (phy->req_duplex == DUPLEX_FULL)
6169 an_10_100_val |= (1<<8);
6170 DP(NETIF_MSG_LINK, "Advertising 100M\n");
6171 }
6172 /* set 10 speed advertisement */
6173 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6174 (phy->speed_cap_mask &
6175 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
6176 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
6177 an_10_100_val |= (1<<5);
6178 autoneg_val |= (1<<9 | 1<<12);
6179 if (phy->req_duplex == DUPLEX_FULL)
6180 an_10_100_val |= (1<<6);
6181 DP(NETIF_MSG_LINK, "Advertising 10M\n");
6182 }
b7737c9b 6183
de6eae1f
YR		 6184 /* Only 10/100 are allowed to work in FORCE mode */
6185 if (phy->req_line_speed == SPEED_100) {
6186 autoneg_val |= (1<<13);
6187 /* Enabled AUTO-MDIX when autoneg is disabled */
6188 bnx2x_cl45_write(bp, phy,
6189 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
6190 (1<<15 | 1<<9 | 7<<0));
6191 DP(NETIF_MSG_LINK, "Setting 100M force\n");
6192 }
6193 if (phy->req_line_speed == SPEED_10) {
6194 /* Enabled AUTO-MDIX when autoneg is disabled */
6195 bnx2x_cl45_write(bp, phy,
6196 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
6197 (1<<15 | 1<<9 | 7<<0));
6198 DP(NETIF_MSG_LINK, "Setting 10M force\n");
6199 }
b7737c9b 6200
de6eae1f
YR		 6201 bnx2x_cl45_write(bp, phy,
6202 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
6203 an_10_100_val);
b7737c9b 6204
de6eae1f
YR		 6205 if (phy->req_duplex == DUPLEX_FULL)
6206 autoneg_val |= (1<<8);
b7737c9b 6207
de6eae1f
YR		 6208 bnx2x_cl45_write(bp, phy,
6209 MDIO_AN_DEVAD,
6210 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
b7737c9b 6211
de6eae1f
YR		 6212 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6213 (phy->speed_cap_mask &
6214 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
6215 (phy->req_line_speed == SPEED_10000)) {
6216 DP(NETIF_MSG_LINK, "Advertising 10G\n");
6217 /* Restart autoneg for 10G*/
6218
6219 bnx2x_cl45_write(bp, phy,
6220 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
6221 0x3200);
6222 } else if (phy->req_line_speed != SPEED_10 &&
6223 phy->req_line_speed != SPEED_100) {
6224 bnx2x_cl45_write(bp, phy,
6225 MDIO_AN_DEVAD,
6226 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
6227 1);
b7737c9b 6228 }
de6eae1f
YR		 6229 /* Save spirom version */
6230 bnx2x_save_848xx_spirom_version(phy, params);
6231
6232 return 0;
b7737c9b
YR		 6233}
6234
de6eae1f
YR		 6235static u8 bnx2x_8481_config_init(struct bnx2x_phy *phy,
6236 struct link_params *params,
6237 struct link_vars *vars)
ea4e040a
YR		 6238{
6239 struct bnx2x *bp = params->bp;
de6eae1f
YR		 6240 /* Restore normal power mode*/
6241 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
cd88ccee 6242 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
b7737c9b 6243
de6eae1f
YR		 6244 /* HW reset */
6245 bnx2x_ext_phy_hw_reset(bp, params->port);
6d870c39 6246 bnx2x_wait_reset_complete(bp, phy, params);
ab6ad5a4 6247
de6eae1f
YR		 6248 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
6249 return bnx2x_848xx_cmn_config_init(phy, params, vars);
6250}
ea4e040a 6251
de6eae1f
YR		 6252static u8 bnx2x_848x3_config_init(struct bnx2x_phy *phy,
6253 struct link_params *params,
6254 struct link_vars *vars)
6255{
6256 struct bnx2x *bp = params->bp;
6a71bbe0 6257 u8 port, initialize = 1;
c87bca1e 6258 u16 val, adj;
de6eae1f 6259 u16 temp;
1bef68e3 6260 u32 actual_phy_selection, cms_enable;
a22f0788 6261 u8 rc = 0;
7f02c4ad
YR		 6262
6263 /* This is just for MDIO_CTL_REG_84823_MEDIA register. */
c87bca1e
YR		 6264 adj = 0;
6265 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
6266 adj = 3;
7f02c4ad 6267
de6eae1f 6268 msleep(1);
6a71bbe0
YR		 6269 if (CHIP_IS_E2(bp))
6270 port = BP_PATH(bp);
6271 else
6272 port = params->port;
de6eae1f
YR		 6273 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
6274 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
7f02c4ad 6275 port);
6d870c39 6276 bnx2x_wait_reset_complete(bp, phy, params);
9bffeac1
YR		 6277 /* Wait for GPHY to come out of reset */
6278 msleep(50);
2cf7acf9
YR		 6279 /*
6280 * BCM84823 requires that XGXS links up first @ 10G for normal behavior
6281 */
de6eae1f
YR		 6282 temp = vars->line_speed;
6283 vars->line_speed = SPEED_10000;
a22f0788
YR		 6284 bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
6285 bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
de6eae1f 6286 vars->line_speed = temp;
a22f0788
YR		 6287
6288 /* Set dual-media configuration according to configuration */
6289
6290 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
c87bca1e 6291 MDIO_CTL_REG_84823_MEDIA + adj, &val);
a22f0788
YR		 6292 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
6293 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
6294 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
6295 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
6296 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
6297 val |= MDIO_CTL_REG_84823_CTRL_MAC_XFI |
6298 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L;
6299
6300 actual_phy_selection = bnx2x_phy_selection(params);
6301
6302 switch (actual_phy_selection) {
6303 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
25985edc 6304 /* Do nothing. Essentially this is like the priority copper */
a22f0788
YR		 6305 break;
6306 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6307 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
6308 break;
6309 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6310 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
6311 break;
6312 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6313 /* Do nothing here. The first PHY won't be initialized at all */
6314 break;
6315 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6316 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
6317 initialize = 0;
6318 break;
6319 }
6320 if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
6321 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
6322
6323 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
c87bca1e 6324 MDIO_CTL_REG_84823_MEDIA + adj, val);
a22f0788
YR		 6325 DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
6326 params->multi_phy_config, val);
6327
6328 if (initialize)
6329 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
6330 else
6331 bnx2x_save_848xx_spirom_version(phy, params);
1bef68e3
YR		 6332 cms_enable = REG_RD(bp, params->shmem_base +
6333 offsetof(struct shmem_region,
6334 dev_info.port_hw_config[params->port].default_cfg)) &
6335 PORT_HW_CFG_ENABLE_CMS_MASK;
6336
6337 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
6338 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
6339 if (cms_enable)
6340 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
6341 else
6342 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
6343 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
6344 MDIO_CTL_REG_84823_USER_CTRL_REG, val);
6345
6346
a22f0788 6347 return rc;
de6eae1f 6348}
ea4e040a 6349
de6eae1f 6350static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
cd88ccee
YR		 6351 struct link_params *params,
6352 struct link_vars *vars)
de6eae1f
YR		 6353{
6354 struct bnx2x *bp = params->bp;
c87bca1e 6355 u16 val, val1, val2, adj;
de6eae1f 6356 u8 link_up = 0;
ea4e040a 6357
c87bca1e
YR		 6358 /* Reg offset adjustment for 84833 */
6359 adj = 0;
6360 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
6361 adj = -1;
6362
de6eae1f
YR		 6363 /* Check 10G-BaseT link status */
6364 /* Check PMD signal ok */
6365 bnx2x_cl45_read(bp, phy,
6366 MDIO_AN_DEVAD, 0xFFFA, &val1);
6367 bnx2x_cl45_read(bp, phy,
c87bca1e 6368 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL + adj,
de6eae1f
YR		 6369 &val2);
6370 DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
ea4e040a 6371
de6eae1f
YR		 6372 /* Check link 10G */
6373 if (val2 & (1<<11)) {
ea4e040a 6374 vars->line_speed = SPEED_10000;
791f18c0 6375 vars->duplex = DUPLEX_FULL;
de6eae1f
YR		 6376 link_up = 1;
6377 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
6378 } else { /* Check Legacy speed link */
6379 u16 legacy_status, legacy_speed;
ea4e040a 6380
de6eae1f
YR		 6381 /* Enable expansion register 0x42 (Operation mode status) */
6382 bnx2x_cl45_write(bp, phy,
6383 MDIO_AN_DEVAD,
6384 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
ea4e040a 6385
de6eae1f
YR		 6386 /* Get legacy speed operation status */
6387 bnx2x_cl45_read(bp, phy,
6388 MDIO_AN_DEVAD,
6389 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
6390 &legacy_status);
ea4e040a 6391
de6eae1f
YR		 6392 DP(NETIF_MSG_LINK, "Legacy speed status"
6393 " = 0x%x\n", legacy_status);
6394 link_up = ((legacy_status & (1<<11)) == (1<<11));
6395 if (link_up) {
6396 legacy_speed = (legacy_status & (3<<9));
6397 if (legacy_speed == (0<<9))
6398 vars->line_speed = SPEED_10;
6399 else if (legacy_speed == (1<<9))
6400 vars->line_speed = SPEED_100;
6401 else if (legacy_speed == (2<<9))
6402 vars->line_speed = SPEED_1000;
6403 else /* Should not happen */
6404 vars->line_speed = 0;
ea4e040a 6405
de6eae1f
YR		 6406 if (legacy_status & (1<<8))
6407 vars->duplex = DUPLEX_FULL;
6408 else
6409 vars->duplex = DUPLEX_HALF;
ea4e040a 6410
de6eae1f
YR		 6411 DP(NETIF_MSG_LINK, "Link is up in %dMbps,"
6412 " is_duplex_full= %d\n", vars->line_speed,
6413 (vars->duplex == DUPLEX_FULL));
6414 /* Check legacy speed AN resolution */
6415 bnx2x_cl45_read(bp, phy,
6416 MDIO_AN_DEVAD,
6417 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
6418 &val);
6419 if (val & (1<<5))
6420 vars->link_status |=
6421 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6422 bnx2x_cl45_read(bp, phy,
6423 MDIO_AN_DEVAD,
6424 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
6425 &val);
6426 if ((val & (1<<0)) == 0)
6427 vars->link_status |=
6428 LINK_STATUS_PARALLEL_DETECTION_USED;
ea4e040a 6429 }
ea4e040a 6430 }
de6eae1f
YR		 6431 if (link_up) {
6432 DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n",
6433 vars->line_speed);
6434 bnx2x_ext_phy_resolve_fc(phy, params, vars);
6435 }
589abe3a 6436
de6eae1f 6437 return link_up;
b7737c9b
YR		 6438}
6439
de6eae1f 6440static u8 bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
b7737c9b 6441{
de6eae1f
YR		 6442 u8 status = 0;
6443 u32 spirom_ver;
6444 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
6445 status = bnx2x_format_ver(spirom_ver, str, len);
6446 return status;
b7737c9b 6447}
de6eae1f
YR		 6448
6449static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
6450 struct link_params *params)
b7737c9b 6451{
de6eae1f 6452 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
cd88ccee 6453 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
de6eae1f 6454 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
cd88ccee 6455 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
b7737c9b 6456}
de6eae1f 6457
b7737c9b
YR		 6458static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
6459 struct link_params *params)
6460{
6461 bnx2x_cl45_write(params->bp, phy,
6462 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
6463 bnx2x_cl45_write(params->bp, phy,
6464 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
6465}
6466
6467static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
6468 struct link_params *params)
6469{
6470 struct bnx2x *bp = params->bp;
6a71bbe0
YR		 6471 u8 port;
6472 if (CHIP_IS_E2(bp))
6473 port = BP_PATH(bp);
6474 else
6475 port = params->port;
b7737c9b 6476 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
cd88ccee
YR		 6477 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6478 port);
b7737c9b
YR		 6479}
6480
7f02c4ad
YR		 6481static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
6482 struct link_params *params, u8 mode)
6483{
6484 struct bnx2x *bp = params->bp;
6485 u16 val;
6486
6487 switch (mode) {
6488 case LED_MODE_OFF:
6489
6490 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", params->port);
6491
6492 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6493 SHARED_HW_CFG_LED_EXTPHY1) {
6494
6495 /* Set LED masks */
6496 bnx2x_cl45_write(bp, phy,
6497 MDIO_PMA_DEVAD,
6498 MDIO_PMA_REG_8481_LED1_MASK,
6499 0x0);
6500
6501 bnx2x_cl45_write(bp, phy,
6502 MDIO_PMA_DEVAD,
6503 MDIO_PMA_REG_8481_LED2_MASK,
6504 0x0);
6505
6506 bnx2x_cl45_write(bp, phy,
6507 MDIO_PMA_DEVAD,
6508 MDIO_PMA_REG_8481_LED3_MASK,
6509 0x0);
6510
6511 bnx2x_cl45_write(bp, phy,
6512 MDIO_PMA_DEVAD,
6513 MDIO_PMA_REG_8481_LED5_MASK,
6514 0x0);
6515
6516 } else {
6517 bnx2x_cl45_write(bp, phy,
6518 MDIO_PMA_DEVAD,
6519 MDIO_PMA_REG_8481_LED1_MASK,
6520 0x0);
6521 }
6522 break;
6523 case LED_MODE_FRONT_PANEL_OFF:
6524
6525 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
6526 params->port);
6527
6528 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6529 SHARED_HW_CFG_LED_EXTPHY1) {
6530
6531 /* Set LED masks */
6532 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 6533 MDIO_PMA_DEVAD,
6534 MDIO_PMA_REG_8481_LED1_MASK,
6535 0x0);
7f02c4ad
YR		 6536
6537 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 6538 MDIO_PMA_DEVAD,
6539 MDIO_PMA_REG_8481_LED2_MASK,
6540 0x0);
7f02c4ad
YR		 6541
6542 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 6543 MDIO_PMA_DEVAD,
6544 MDIO_PMA_REG_8481_LED3_MASK,
6545 0x0);
7f02c4ad
YR		 6546
6547 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 6548 MDIO_PMA_DEVAD,
6549 MDIO_PMA_REG_8481_LED5_MASK,
6550 0x20);
7f02c4ad
YR		 6551
6552 } else {
6553 bnx2x_cl45_write(bp, phy,
6554 MDIO_PMA_DEVAD,
6555 MDIO_PMA_REG_8481_LED1_MASK,
6556 0x0);
6557 }
6558 break;
6559 case LED_MODE_ON:
6560
6561 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", params->port);
6562
6563 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6564 SHARED_HW_CFG_LED_EXTPHY1) {
6565 /* Set control reg */
6566 bnx2x_cl45_read(bp, phy,
6567 MDIO_PMA_DEVAD,
6568 MDIO_PMA_REG_8481_LINK_SIGNAL,
6569 &val);
6570 val &= 0x8000;
6571 val |= 0x2492;
6572
6573 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 6574 MDIO_PMA_DEVAD,
6575 MDIO_PMA_REG_8481_LINK_SIGNAL,
6576 val);
7f02c4ad
YR		 6577
6578 /* Set LED masks */
6579 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 6580 MDIO_PMA_DEVAD,
6581 MDIO_PMA_REG_8481_LED1_MASK,
6582 0x0);
7f02c4ad
YR		 6583
6584 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 6585 MDIO_PMA_DEVAD,
6586 MDIO_PMA_REG_8481_LED2_MASK,
6587 0x20);
7f02c4ad
YR		 6588
6589 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 6590 MDIO_PMA_DEVAD,
6591 MDIO_PMA_REG_8481_LED3_MASK,
6592 0x20);
7f02c4ad
YR		 6593
6594 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 6595 MDIO_PMA_DEVAD,
6596 MDIO_PMA_REG_8481_LED5_MASK,
6597 0x0);
7f02c4ad
YR		 6598 } else {
6599 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 6600 MDIO_PMA_DEVAD,
6601 MDIO_PMA_REG_8481_LED1_MASK,
6602 0x20);
7f02c4ad
YR		 6603 }
6604 break;
6605
6606 case LED_MODE_OPER:
6607
6608 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", params->port);
6609
6610 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6611 SHARED_HW_CFG_LED_EXTPHY1) {
6612
6613 /* Set control reg */
6614 bnx2x_cl45_read(bp, phy,
6615 MDIO_PMA_DEVAD,
6616 MDIO_PMA_REG_8481_LINK_SIGNAL,
6617 &val);
6618
6619 if (!((val &
cd88ccee
YR		 6620 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
6621 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
2cf7acf9 6622 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
7f02c4ad
YR		 6623 bnx2x_cl45_write(bp, phy,
6624 MDIO_PMA_DEVAD,
6625 MDIO_PMA_REG_8481_LINK_SIGNAL,
6626 0xa492);
6627 }
6628
6629 /* Set LED masks */
6630 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 6631 MDIO_PMA_DEVAD,
6632 MDIO_PMA_REG_8481_LED1_MASK,
6633 0x10);
7f02c4ad
YR		 6634
6635 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 6636 MDIO_PMA_DEVAD,
6637 MDIO_PMA_REG_8481_LED2_MASK,
6638 0x80);
7f02c4ad
YR		 6639
6640 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 6641 MDIO_PMA_DEVAD,
6642 MDIO_PMA_REG_8481_LED3_MASK,
6643 0x98);
7f02c4ad
YR		 6644
6645 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 6646 MDIO_PMA_DEVAD,
6647 MDIO_PMA_REG_8481_LED5_MASK,
6648 0x40);
7f02c4ad
YR		 6649
6650 } else {
6651 bnx2x_cl45_write(bp, phy,
6652 MDIO_PMA_DEVAD,
6653 MDIO_PMA_REG_8481_LED1_MASK,
6654 0x80);
53eda06d
YR		 6655
6656 /* Tell LED3 to blink on source */
6657 bnx2x_cl45_read(bp, phy,
6658 MDIO_PMA_DEVAD,
6659 MDIO_PMA_REG_8481_LINK_SIGNAL,
6660 &val);
6661 val &= ~(7<<6);
6662 val |= (1<<6); /* A83B[8:6]= 1 */
6663 bnx2x_cl45_write(bp, phy,
6664 MDIO_PMA_DEVAD,
6665 MDIO_PMA_REG_8481_LINK_SIGNAL,
6666 val);
7f02c4ad
YR		 6667 }
6668 break;
6669 }
6670}
de6eae1f
YR		 6671/******************************************************************/
6672/* SFX7101 PHY SECTION */
6673/******************************************************************/
6674static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
6675 struct link_params *params)
b7737c9b
YR		 6676{
6677 struct bnx2x *bp = params->bp;
de6eae1f
YR		 6678 /* SFX7101_XGXS_TEST1 */
6679 bnx2x_cl45_write(bp, phy,
6680 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
589abe3a
EG		 6681}
6682
de6eae1f
YR		 6683static u8 bnx2x_7101_config_init(struct bnx2x_phy *phy,
6684 struct link_params *params,
6685 struct link_vars *vars)
ea4e040a 6686{
de6eae1f 6687 u16 fw_ver1, fw_ver2, val;
ea4e040a 6688 struct bnx2x *bp = params->bp;
de6eae1f 6689 DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
ea4e040a 6690
de6eae1f
YR		 6691 /* Restore normal power mode*/
6692 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
cd88ccee 6693 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
de6eae1f
YR		 6694 /* HW reset */
6695 bnx2x_ext_phy_hw_reset(bp, params->port);
6d870c39 6696 bnx2x_wait_reset_complete(bp, phy, params);
ea4e040a 6697
de6eae1f
YR		 6698 bnx2x_cl45_write(bp, phy,
6699 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x1);
6700 DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
6701 bnx2x_cl45_write(bp, phy,
6702 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
ea4e040a 6703
de6eae1f
YR		 6704 bnx2x_ext_phy_set_pause(params, phy, vars);
6705 /* Restart autoneg */
6706 bnx2x_cl45_read(bp, phy,
6707 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
6708 val |= 0x200;
6709 bnx2x_cl45_write(bp, phy,
6710 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
ea4e040a 6711
de6eae1f
YR		 6712 /* Save spirom version */
6713 bnx2x_cl45_read(bp, phy,
6714 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
ea4e040a 6715
de6eae1f
YR		 6716 bnx2x_cl45_read(bp, phy,
6717 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
6718 bnx2x_save_spirom_version(bp, params->port,
6719 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
6720 return 0;
6721}
ea4e040a 6722
de6eae1f
YR		 6723static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
6724 struct link_params *params,
6725 struct link_vars *vars)
57963ed9
YR		 6726{
6727 struct bnx2x *bp = params->bp;
de6eae1f
YR		 6728 u8 link_up;
6729 u16 val1, val2;
6730 bnx2x_cl45_read(bp, phy,
6731 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2);
6732 bnx2x_cl45_read(bp, phy,
6733 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
6734 DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
6735 val2, val1);
6736 bnx2x_cl45_read(bp, phy,
6737 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
6738 bnx2x_cl45_read(bp, phy,
6739 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
6740 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
6741 val2, val1);
6742 link_up = ((val1 & 4) == 4);
2cf7acf9 6743 /* if link is up print the AN outcome of the SFX7101 PHY */
de6eae1f
YR		 6744 if (link_up) {
6745 bnx2x_cl45_read(bp, phy,
6746 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
6747 &val2);
6748 vars->line_speed = SPEED_10000;
791f18c0 6749 vars->duplex = DUPLEX_FULL;
de6eae1f
YR		 6750 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
6751 val2, (val2 & (1<<14)));
6752 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
6753 bnx2x_ext_phy_resolve_fc(phy, params, vars);
6754 }
6755 return link_up;
6756}
6c55c3cd 6757
6c55c3cd 6758
de6eae1f
YR		 6759static u8 bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
6760{
6761 if (*len < 5)
6762 return -EINVAL;
6763 str[0] = (spirom_ver & 0xFF);
6764 str[1] = (spirom_ver & 0xFF00) >> 8;
6765 str[2] = (spirom_ver & 0xFF0000) >> 16;
6766 str[3] = (spirom_ver & 0xFF000000) >> 24;
6767 str[4] = '\0';
6768 *len -= 5;
57963ed9
YR		 6769 return 0;
6770}
6771
de6eae1f 6772void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
57963ed9 6773{
de6eae1f 6774 u16 val, cnt;
7aa0711f 6775
de6eae1f 6776 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 6777 MDIO_PMA_DEVAD,
6778 MDIO_PMA_REG_7101_RESET, &val);
57963ed9 6779
de6eae1f
YR		 6780 for (cnt = 0; cnt < 10; cnt++) {
6781 msleep(50);
6782 /* Writes a self-clearing reset */
6783 bnx2x_cl45_write(bp, phy,
cd88ccee
YR		 6784 MDIO_PMA_DEVAD,
6785 MDIO_PMA_REG_7101_RESET,
6786 (val | (1<<15)));
de6eae1f
YR		 6787 /* Wait for clear */
6788 bnx2x_cl45_read(bp, phy,
cd88ccee
YR		 6789 MDIO_PMA_DEVAD,
6790 MDIO_PMA_REG_7101_RESET, &val);
0c786f02 6791
de6eae1f
YR		 6792 if ((val & (1<<15)) == 0)
6793 break;
57963ed9 6794 }
57963ed9 6795}
ea4e040a 6796
de6eae1f
YR		 6797static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
6798 struct link_params *params) {
6799 /* Low power mode is controlled by GPIO 2 */
6800 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
cd88ccee 6801 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
de6eae1f
YR		 6802 /* The PHY reset is controlled by GPIO 1 */
6803 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
cd88ccee 6804 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
de6eae1f 6805}
ea4e040a 6806
7f02c4ad
YR		 6807static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
6808 struct link_params *params, u8 mode)
6809{
6810 u16 val = 0;
6811 struct bnx2x *bp = params->bp;
6812 switch (mode) {
6813 case LED_MODE_FRONT_PANEL_OFF:
6814 case LED_MODE_OFF:
6815 val = 2;
6816 break;
6817 case LED_MODE_ON:
6818 val = 1;
6819 break;
6820 case LED_MODE_OPER:
6821 val = 0;
6822 break;
6823 }
6824 bnx2x_cl45_write(bp, phy,
6825 MDIO_PMA_DEVAD,
6826 MDIO_PMA_REG_7107_LINK_LED_CNTL,
6827 val);
6828}
6829
de6eae1f
YR		 6830/******************************************************************/
6831/* STATIC PHY DECLARATION */
6832/******************************************************************/
ea4e040a 6833
de6eae1f
YR		 6834static struct bnx2x_phy phy_null = {
6835 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
6836 .addr = 0,
6837 .flags = FLAGS_INIT_XGXS_FIRST,
6838 .def_md_devad = 0,
6839 .reserved = 0,
6840 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6841 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6842 .mdio_ctrl = 0,
6843 .supported = 0,
6844 .media_type = ETH_PHY_NOT_PRESENT,
6845 .ver_addr = 0,
cd88ccee
YR		 6846 .req_flow_ctrl = 0,
6847 .req_line_speed = 0,
6848 .speed_cap_mask = 0,
de6eae1f
YR		 6849 .req_duplex = 0,
6850 .rsrv = 0,
6851 .config_init = (config_init_t)NULL,
6852 .read_status = (read_status_t)NULL,
6853 .link_reset = (link_reset_t)NULL,
6854 .config_loopback = (config_loopback_t)NULL,
6855 .format_fw_ver = (format_fw_ver_t)NULL,
6856 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 6857 .set_link_led = (set_link_led_t)NULL,
6858 .phy_specific_func = (phy_specific_func_t)NULL
de6eae1f 6859};
ea4e040a 6860
de6eae1f
YR		 6861static struct bnx2x_phy phy_serdes = {
6862 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
6863 .addr = 0xff,
6864 .flags = 0,
6865 .def_md_devad = 0,
6866 .reserved = 0,
6867 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6868 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6869 .mdio_ctrl = 0,
6870 .supported = (SUPPORTED_10baseT_Half |
6871 SUPPORTED_10baseT_Full |
6872 SUPPORTED_100baseT_Half |
6873 SUPPORTED_100baseT_Full |
6874 SUPPORTED_1000baseT_Full |
6875 SUPPORTED_2500baseX_Full |
6876 SUPPORTED_TP |
6877 SUPPORTED_Autoneg |
6878 SUPPORTED_Pause |
6879 SUPPORTED_Asym_Pause),
6880 .media_type = ETH_PHY_UNSPECIFIED,
6881 .ver_addr = 0,
6882 .req_flow_ctrl = 0,
cd88ccee
YR		 6883 .req_line_speed = 0,
6884 .speed_cap_mask = 0,
de6eae1f
YR		 6885 .req_duplex = 0,
6886 .rsrv = 0,
6887 .config_init = (config_init_t)bnx2x_init_serdes,
6888 .read_status = (read_status_t)bnx2x_link_settings_status,
6889 .link_reset = (link_reset_t)bnx2x_int_link_reset,
6890 .config_loopback = (config_loopback_t)NULL,
6891 .format_fw_ver = (format_fw_ver_t)NULL,
6892 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 6893 .set_link_led = (set_link_led_t)NULL,
6894 .phy_specific_func = (phy_specific_func_t)NULL
de6eae1f 6895};
b7737c9b
YR		 6896
6897static struct bnx2x_phy phy_xgxs = {
6898 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
6899 .addr = 0xff,
6900 .flags = 0,
6901 .def_md_devad = 0,
6902 .reserved = 0,
6903 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6904 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6905 .mdio_ctrl = 0,
6906 .supported = (SUPPORTED_10baseT_Half |
6907 SUPPORTED_10baseT_Full |
6908 SUPPORTED_100baseT_Half |
6909 SUPPORTED_100baseT_Full |
6910 SUPPORTED_1000baseT_Full |
6911 SUPPORTED_2500baseX_Full |
6912 SUPPORTED_10000baseT_Full |
6913 SUPPORTED_FIBRE |
6914 SUPPORTED_Autoneg |
6915 SUPPORTED_Pause |
6916 SUPPORTED_Asym_Pause),
6917 .media_type = ETH_PHY_UNSPECIFIED,
6918 .ver_addr = 0,
6919 .req_flow_ctrl = 0,
cd88ccee
YR		 6920 .req_line_speed = 0,
6921 .speed_cap_mask = 0,
b7737c9b
YR		 6922 .req_duplex = 0,
6923 .rsrv = 0,
6924 .config_init = (config_init_t)bnx2x_init_xgxs,
6925 .read_status = (read_status_t)bnx2x_link_settings_status,
6926 .link_reset = (link_reset_t)bnx2x_int_link_reset,
6927 .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
6928 .format_fw_ver = (format_fw_ver_t)NULL,
6929 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 6930 .set_link_led = (set_link_led_t)NULL,
6931 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b
YR		 6932};
6933
6934static struct bnx2x_phy phy_7101 = {
6935 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6936 .addr = 0xff,
6937 .flags = FLAGS_FAN_FAILURE_DET_REQ,
6938 .def_md_devad = 0,
6939 .reserved = 0,
6940 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6941 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6942 .mdio_ctrl = 0,
6943 .supported = (SUPPORTED_10000baseT_Full |
6944 SUPPORTED_TP |
6945 SUPPORTED_Autoneg |
6946 SUPPORTED_Pause |
6947 SUPPORTED_Asym_Pause),
6948 .media_type = ETH_PHY_BASE_T,
6949 .ver_addr = 0,
6950 .req_flow_ctrl = 0,
cd88ccee
YR		 6951 .req_line_speed = 0,
6952 .speed_cap_mask = 0,
b7737c9b
YR		 6953 .req_duplex = 0,
6954 .rsrv = 0,
6955 .config_init = (config_init_t)bnx2x_7101_config_init,
6956 .read_status = (read_status_t)bnx2x_7101_read_status,
6957 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
6958 .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
6959 .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver,
6960 .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset,
7f02c4ad 6961 .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led,
a22f0788 6962 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b
YR		 6963};
6964static struct bnx2x_phy phy_8073 = {
6965 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6966 .addr = 0xff,
6967 .flags = FLAGS_HW_LOCK_REQUIRED,
6968 .def_md_devad = 0,
6969 .reserved = 0,
6970 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6971 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6972 .mdio_ctrl = 0,
6973 .supported = (SUPPORTED_10000baseT_Full |
6974 SUPPORTED_2500baseX_Full |
6975 SUPPORTED_1000baseT_Full |
6976 SUPPORTED_FIBRE |
6977 SUPPORTED_Autoneg |
6978 SUPPORTED_Pause |
6979 SUPPORTED_Asym_Pause),
6980 .media_type = ETH_PHY_UNSPECIFIED,
6981 .ver_addr = 0,
cd88ccee
YR		 6982 .req_flow_ctrl = 0,
6983 .req_line_speed = 0,
6984 .speed_cap_mask = 0,
b7737c9b
YR		 6985 .req_duplex = 0,
6986 .rsrv = 0,
62b29a5d 6987 .config_init = (config_init_t)bnx2x_8073_config_init,
b7737c9b
YR		 6988 .read_status = (read_status_t)bnx2x_8073_read_status,
6989 .link_reset = (link_reset_t)bnx2x_8073_link_reset,
6990 .config_loopback = (config_loopback_t)NULL,
6991 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
6992 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 6993 .set_link_led = (set_link_led_t)NULL,
6994 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b
YR		 6995};
6996static struct bnx2x_phy phy_8705 = {
6997 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
6998 .addr = 0xff,
6999 .flags = FLAGS_INIT_XGXS_FIRST,
7000 .def_md_devad = 0,
7001 .reserved = 0,
7002 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7003 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7004 .mdio_ctrl = 0,
7005 .supported = (SUPPORTED_10000baseT_Full |
7006 SUPPORTED_FIBRE |
7007 SUPPORTED_Pause |
7008 SUPPORTED_Asym_Pause),
7009 .media_type = ETH_PHY_XFP_FIBER,
7010 .ver_addr = 0,
7011 .req_flow_ctrl = 0,
7012 .req_line_speed = 0,
7013 .speed_cap_mask = 0,
7014 .req_duplex = 0,
7015 .rsrv = 0,
7016 .config_init = (config_init_t)bnx2x_8705_config_init,
7017 .read_status = (read_status_t)bnx2x_8705_read_status,
7018 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
7019 .config_loopback = (config_loopback_t)NULL,
7020 .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver,
7021 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 7022 .set_link_led = (set_link_led_t)NULL,
7023 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b
YR		 7024};
7025static struct bnx2x_phy phy_8706 = {
7026 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
7027 .addr = 0xff,
7028 .flags = FLAGS_INIT_XGXS_FIRST,
7029 .def_md_devad = 0,
7030 .reserved = 0,
7031 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7032 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7033 .mdio_ctrl = 0,
7034 .supported = (SUPPORTED_10000baseT_Full |
7035 SUPPORTED_1000baseT_Full |
7036 SUPPORTED_FIBRE |
7037 SUPPORTED_Pause |
7038 SUPPORTED_Asym_Pause),
7039 .media_type = ETH_PHY_SFP_FIBER,
7040 .ver_addr = 0,
7041 .req_flow_ctrl = 0,
7042 .req_line_speed = 0,
7043 .speed_cap_mask = 0,
7044 .req_duplex = 0,
7045 .rsrv = 0,
7046 .config_init = (config_init_t)bnx2x_8706_config_init,
7047 .read_status = (read_status_t)bnx2x_8706_read_status,
7048 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
7049 .config_loopback = (config_loopback_t)NULL,
7050 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
7051 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 7052 .set_link_led = (set_link_led_t)NULL,
7053 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b
YR		 7054};
7055
7056static struct bnx2x_phy phy_8726 = {
7057 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
7058 .addr = 0xff,
7059 .flags = (FLAGS_HW_LOCK_REQUIRED |
7060 FLAGS_INIT_XGXS_FIRST),
7061 .def_md_devad = 0,
7062 .reserved = 0,
7063 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7064 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7065 .mdio_ctrl = 0,
7066 .supported = (SUPPORTED_10000baseT_Full |
7067 SUPPORTED_1000baseT_Full |
7068 SUPPORTED_Autoneg |
7069 SUPPORTED_FIBRE |
7070 SUPPORTED_Pause |
7071 SUPPORTED_Asym_Pause),
7072 .media_type = ETH_PHY_SFP_FIBER,
7073 .ver_addr = 0,
7074 .req_flow_ctrl = 0,
7075 .req_line_speed = 0,
7076 .speed_cap_mask = 0,
7077 .req_duplex = 0,
7078 .rsrv = 0,
7079 .config_init = (config_init_t)bnx2x_8726_config_init,
7080 .read_status = (read_status_t)bnx2x_8726_read_status,
7081 .link_reset = (link_reset_t)bnx2x_8726_link_reset,
7082 .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
7083 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
7084 .hw_reset = (hw_reset_t)NULL,
a22f0788
YR		 7085 .set_link_led = (set_link_led_t)NULL,
7086 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b
YR		 7087};
7088
7089static struct bnx2x_phy phy_8727 = {
7090 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
7091 .addr = 0xff,
7092 .flags = FLAGS_FAN_FAILURE_DET_REQ,
7093 .def_md_devad = 0,
7094 .reserved = 0,
7095 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7096 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7097 .mdio_ctrl = 0,
7098 .supported = (SUPPORTED_10000baseT_Full |
7099 SUPPORTED_1000baseT_Full |
b7737c9b
YR		 7100 SUPPORTED_FIBRE |
7101 SUPPORTED_Pause |
7102 SUPPORTED_Asym_Pause),
7103 .media_type = ETH_PHY_SFP_FIBER,
7104 .ver_addr = 0,
7105 .req_flow_ctrl = 0,
7106 .req_line_speed = 0,
7107 .speed_cap_mask = 0,
7108 .req_duplex = 0,
7109 .rsrv = 0,
7110 .config_init = (config_init_t)bnx2x_8727_config_init,
7111 .read_status = (read_status_t)bnx2x_8727_read_status,
7112 .link_reset = (link_reset_t)bnx2x_8727_link_reset,
7113 .config_loopback = (config_loopback_t)NULL,
7114 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
7115 .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset,
7f02c4ad 7116 .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led,
a22f0788 7117 .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
b7737c9b
YR		 7118};
7119static struct bnx2x_phy phy_8481 = {
7120 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
7121 .addr = 0xff,
a22f0788
YR		 7122 .flags = FLAGS_FAN_FAILURE_DET_REQ |
7123 FLAGS_REARM_LATCH_SIGNAL,
b7737c9b
YR		 7124 .def_md_devad = 0,
7125 .reserved = 0,
7126 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7127 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7128 .mdio_ctrl = 0,
7129 .supported = (SUPPORTED_10baseT_Half |
7130 SUPPORTED_10baseT_Full |
7131 SUPPORTED_100baseT_Half |
7132 SUPPORTED_100baseT_Full |
7133 SUPPORTED_1000baseT_Full |
7134 SUPPORTED_10000baseT_Full |
7135 SUPPORTED_TP |
7136 SUPPORTED_Autoneg |
7137 SUPPORTED_Pause |
7138 SUPPORTED_Asym_Pause),
7139 .media_type = ETH_PHY_BASE_T,
7140 .ver_addr = 0,
7141 .req_flow_ctrl = 0,
7142 .req_line_speed = 0,
7143 .speed_cap_mask = 0,
7144 .req_duplex = 0,
7145 .rsrv = 0,
7146 .config_init = (config_init_t)bnx2x_8481_config_init,
7147 .read_status = (read_status_t)bnx2x_848xx_read_status,
7148 .link_reset = (link_reset_t)bnx2x_8481_link_reset,
7149 .config_loopback = (config_loopback_t)NULL,
7150 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
7151 .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset,
7f02c4ad 7152 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
a22f0788 7153 .phy_specific_func = (phy_specific_func_t)NULL
b7737c9b
YR		 7154};
7155
de6eae1f
YR		 7156static struct bnx2x_phy phy_84823 = {
7157 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
7158 .addr = 0xff,
a22f0788
YR		 7159 .flags = FLAGS_FAN_FAILURE_DET_REQ |
7160 FLAGS_REARM_LATCH_SIGNAL,
de6eae1f
YR		 7161 .def_md_devad = 0,
7162 .reserved = 0,
7163 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7164 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7165 .mdio_ctrl = 0,
7166 .supported = (SUPPORTED_10baseT_Half |
7167 SUPPORTED_10baseT_Full |
7168 SUPPORTED_100baseT_Half |
7169 SUPPORTED_100baseT_Full |
7170 SUPPORTED_1000baseT_Full |
7171 SUPPORTED_10000baseT_Full |
7172 SUPPORTED_TP |
7173 SUPPORTED_Autoneg |
7174 SUPPORTED_Pause |
7175 SUPPORTED_Asym_Pause),
7176 .media_type = ETH_PHY_BASE_T,
7177 .ver_addr = 0,
7178 .req_flow_ctrl = 0,
7179 .req_line_speed = 0,
7180 .speed_cap_mask = 0,
7181 .req_duplex = 0,
7182 .rsrv = 0,
7183 .config_init = (config_init_t)bnx2x_848x3_config_init,
7184 .read_status = (read_status_t)bnx2x_848xx_read_status,
7185 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
7186 .config_loopback = (config_loopback_t)NULL,
7187 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
7188 .hw_reset = (hw_reset_t)NULL,
7f02c4ad 7189 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
a22f0788 7190 .phy_specific_func = (phy_specific_func_t)NULL
de6eae1f
YR		 7191};
7192
c87bca1e
YR		 7193static struct bnx2x_phy phy_84833 = {
7194 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
7195 .addr = 0xff,
7196 .flags = FLAGS_FAN_FAILURE_DET_REQ |
7197 FLAGS_REARM_LATCH_SIGNAL,
7198 .def_md_devad = 0,
7199 .reserved = 0,
7200 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7201 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7202 .mdio_ctrl = 0,
7203 .supported = (SUPPORTED_10baseT_Half |
7204 SUPPORTED_10baseT_Full |
7205 SUPPORTED_100baseT_Half |
7206 SUPPORTED_100baseT_Full |
7207 SUPPORTED_1000baseT_Full |
7208 SUPPORTED_10000baseT_Full |
7209 SUPPORTED_TP |
7210 SUPPORTED_Autoneg |
7211 SUPPORTED_Pause |
7212 SUPPORTED_Asym_Pause),
7213 .media_type = ETH_PHY_BASE_T,
7214 .ver_addr = 0,
7215 .req_flow_ctrl = 0,
7216 .req_line_speed = 0,
7217 .speed_cap_mask = 0,
7218 .req_duplex = 0,
7219 .rsrv = 0,
7220 .config_init = (config_init_t)bnx2x_848x3_config_init,
7221 .read_status = (read_status_t)bnx2x_848xx_read_status,
7222 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
7223 .config_loopback = (config_loopback_t)NULL,
7224 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
7225 .hw_reset = (hw_reset_t)NULL,
7226 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
7227 .phy_specific_func = (phy_specific_func_t)NULL
7228};
7229
de6eae1f
YR		 7230/*****************************************************************/
7231/* */
7232/* Populate the phy according. Main function: bnx2x_populate_phy */
7233/* */
7234/*****************************************************************/
7235
7236static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
7237 struct bnx2x_phy *phy, u8 port,
7238 u8 phy_index)
7239{
7240 /* Get the 4 lanes xgxs config rx and tx */
7241 u32 rx = 0, tx = 0, i;
7242 for (i = 0; i < 2; i++) {
2cf7acf9 7243 /*
de6eae1f
YR		 7244 * INT_PHY and EXT_PHY1 share the same value location in the
7245 * shmem. When num_phys is greater than 1, than this value
7246 * applies only to EXT_PHY1
7247 */
a22f0788
YR		 7248 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
7249 rx = REG_RD(bp, shmem_base +
7250 offsetof(struct shmem_region,
cd88ccee 7251 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
a22f0788
YR		 7252
7253 tx = REG_RD(bp, shmem_base +
7254 offsetof(struct shmem_region,
cd88ccee 7255 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
a22f0788
YR		 7256 } else {
7257 rx = REG_RD(bp, shmem_base +
7258 offsetof(struct shmem_region,
cd88ccee 7259 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
de6eae1f 7260
a22f0788
YR		 7261 tx = REG_RD(bp, shmem_base +
7262 offsetof(struct shmem_region,
cd88ccee 7263 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
a22f0788 7264 }
de6eae1f
YR		 7265
7266 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
7267 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
7268
7269 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
7270 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
7271 }
7272}
7273
7274static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
7275 u8 phy_index, u8 port)
7276{
7277 u32 ext_phy_config = 0;
7278 switch (phy_index) {
7279 case EXT_PHY1:
7280 ext_phy_config = REG_RD(bp, shmem_base +
7281 offsetof(struct shmem_region,
7282 dev_info.port_hw_config[port].external_phy_config));
7283 break;
a22f0788
YR		 7284 case EXT_PHY2:
7285 ext_phy_config = REG_RD(bp, shmem_base +
7286 offsetof(struct shmem_region,
7287 dev_info.port_hw_config[port].external_phy_config2));
7288 break;
de6eae1f
YR		 7289 default:
7290 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
7291 return -EINVAL;
7292 }
7293
7294 return ext_phy_config;
7295}
7296static u8 bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
7297 struct bnx2x_phy *phy)
7298{
7299 u32 phy_addr;
7300 u32 chip_id;
7301 u32 switch_cfg = (REG_RD(bp, shmem_base +
7302 offsetof(struct shmem_region,
7303 dev_info.port_feature_config[port].link_config)) &
7304 PORT_FEATURE_CONNECTED_SWITCH_MASK);
7305 chip_id = REG_RD(bp, MISC_REG_CHIP_NUM) << 16;
7306 switch (switch_cfg) {
7307 case SWITCH_CFG_1G:
7308 phy_addr = REG_RD(bp,
7309 NIG_REG_SERDES0_CTRL_PHY_ADDR +
7310 port * 0x10);
7311 *phy = phy_serdes;
7312 break;
7313 case SWITCH_CFG_10G:
7314 phy_addr = REG_RD(bp,
7315 NIG_REG_XGXS0_CTRL_PHY_ADDR +
7316 port * 0x18);
7317 *phy = phy_xgxs;
7318 break;
7319 default:
7320 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
7321 return -EINVAL;
7322 }
7323 phy->addr = (u8)phy_addr;
7324 phy->mdio_ctrl = bnx2x_get_emac_base(bp,
7325 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
7326 port);
f2e0899f
DK		 7327 if (CHIP_IS_E2(bp))
7328 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
7329 else
7330 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
de6eae1f
YR		 7331
7332 DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
7333 port, phy->addr, phy->mdio_ctrl);
7334
7335 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
7336 return 0;
7337}
7338
7339static u8 bnx2x_populate_ext_phy(struct bnx2x *bp,
7340 u8 phy_index,
7341 u32 shmem_base,
a22f0788 7342 u32 shmem2_base,
de6eae1f
YR		 7343 u8 port,
7344 struct bnx2x_phy *phy)
7345{
7346 u32 ext_phy_config, phy_type, config2;
7347 u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
7348 ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
7349 phy_index, port);
7350 phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
7351 /* Select the phy type */
7352 switch (phy_type) {
7353 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
7354 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
7355 *phy = phy_8073;
7356 break;
7357 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
7358 *phy = phy_8705;
7359 break;
7360 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
7361 *phy = phy_8706;
7362 break;
7363 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7364 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
7365 *phy = phy_8726;
7366 break;
7367 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
7368 /* BCM8727_NOC => BCM8727 no over current */
7369 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
7370 *phy = phy_8727;
7371 phy->flags |= FLAGS_NOC;
7372 break;
e4d78f12 7373 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
de6eae1f
YR		 7374 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7375 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
7376 *phy = phy_8727;
7377 break;
7378 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
7379 *phy = phy_8481;
7380 break;
7381 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
7382 *phy = phy_84823;
7383 break;
c87bca1e
YR		 7384 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
7385 *phy = phy_84833;
7386 break;
de6eae1f
YR		 7387 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
7388 *phy = phy_7101;
7389 break;
7390 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
7391 *phy = phy_null;
7392 return -EINVAL;
7393 default:
7394 *phy = phy_null;
7395 return 0;
7396 }
7397
7398 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
7399 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
7400
2cf7acf9
YR		 7401 /*
7402 * The shmem address of the phy version is located on different
7403 * structures. In case this structure is too old, do not set
7404 * the address
7405 */
de6eae1f
YR		 7406 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
7407 dev_info.shared_hw_config.config2));
a22f0788
YR		 7408 if (phy_index == EXT_PHY1) {
7409 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
7410 port_mb[port].ext_phy_fw_version);
de6eae1f 7411
cd88ccee
YR		 7412 /* Check specific mdc mdio settings */
7413 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
7414 mdc_mdio_access = config2 &
7415 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
a22f0788
YR		 7416 } else {
7417 u32 size = REG_RD(bp, shmem2_base);
de6eae1f 7418
a22f0788
YR		 7419 if (size >
7420 offsetof(struct shmem2_region, ext_phy_fw_version2)) {
7421 phy->ver_addr = shmem2_base +
7422 offsetof(struct shmem2_region,
7423 ext_phy_fw_version2[port]);
7424 }
7425 /* Check specific mdc mdio settings */
7426 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
7427 mdc_mdio_access = (config2 &
7428 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
7429 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
7430 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
7431 }
de6eae1f
YR		 7432 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
7433
2cf7acf9 7434 /*
de6eae1f
YR		 7435 * In case mdc/mdio_access of the external phy is different than the
7436 * mdc/mdio access of the XGXS, a HW lock must be taken in each access
7437 * to prevent one port interfere with another port's CL45 operations.
7438 */
7439 if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH)
7440 phy->flags |= FLAGS_HW_LOCK_REQUIRED;
7441 DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
7442 phy_type, port, phy_index);
7443 DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n",
7444 phy->addr, phy->mdio_ctrl);
7445 return 0;
7446}
7447
7448static u8 bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
a22f0788 7449 u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
de6eae1f
YR		 7450{
7451 u8 status = 0;
7452 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
7453 if (phy_index == INT_PHY)
7454 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
a22f0788 7455 status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
de6eae1f
YR		 7456 port, phy);
7457 return status;
7458}
7459
7460static void bnx2x_phy_def_cfg(struct link_params *params,
7461 struct bnx2x_phy *phy,
a22f0788 7462 u8 phy_index)
de6eae1f
YR		 7463{
7464 struct bnx2x *bp = params->bp;
7465 u32 link_config;
7466 /* Populate the default phy configuration for MF mode */
a22f0788
YR		 7467 if (phy_index == EXT_PHY2) {
7468 link_config = REG_RD(bp, params->shmem_base +
cd88ccee 7469 offsetof(struct shmem_region, dev_info.
a22f0788
YR		 7470 port_feature_config[params->port].link_config2));
7471 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
cd88ccee
YR		 7472 offsetof(struct shmem_region,
7473 dev_info.
a22f0788
YR		 7474 port_hw_config[params->port].speed_capability_mask2));
7475 } else {
7476 link_config = REG_RD(bp, params->shmem_base +
cd88ccee 7477 offsetof(struct shmem_region, dev_info.
a22f0788
YR		 7478 port_feature_config[params->port].link_config));
7479 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
cd88ccee
YR		 7480 offsetof(struct shmem_region,
7481 dev_info.
7482 port_hw_config[params->port].speed_capability_mask));
a22f0788
YR		 7483 }
7484 DP(NETIF_MSG_LINK, "Default config phy idx %x cfg 0x%x speed_cap_mask"
7485 " 0x%x\n", phy_index, link_config, phy->speed_cap_mask);
de6eae1f
YR		 7486
7487 phy->req_duplex = DUPLEX_FULL;
7488 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
7489 case PORT_FEATURE_LINK_SPEED_10M_HALF:
7490 phy->req_duplex = DUPLEX_HALF;
7491 case PORT_FEATURE_LINK_SPEED_10M_FULL:
7492 phy->req_line_speed = SPEED_10;
7493 break;
7494 case PORT_FEATURE_LINK_SPEED_100M_HALF:
7495 phy->req_duplex = DUPLEX_HALF;
7496 case PORT_FEATURE_LINK_SPEED_100M_FULL:
7497 phy->req_line_speed = SPEED_100;
7498 break;
7499 case PORT_FEATURE_LINK_SPEED_1G:
7500 phy->req_line_speed = SPEED_1000;
7501 break;
7502 case PORT_FEATURE_LINK_SPEED_2_5G:
7503 phy->req_line_speed = SPEED_2500;
7504 break;
7505 case PORT_FEATURE_LINK_SPEED_10G_CX4:
7506 phy->req_line_speed = SPEED_10000;
7507 break;
7508 default:
7509 phy->req_line_speed = SPEED_AUTO_NEG;
7510 break;
7511 }
7512
7513 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
7514 case PORT_FEATURE_FLOW_CONTROL_AUTO:
7515 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
7516 break;
7517 case PORT_FEATURE_FLOW_CONTROL_TX:
7518 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
7519 break;
7520 case PORT_FEATURE_FLOW_CONTROL_RX:
7521 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
7522 break;
7523 case PORT_FEATURE_FLOW_CONTROL_BOTH:
7524 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
7525 break;
7526 default:
7527 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7528 break;
7529 }
7530}
7531
a22f0788
YR		 7532u32 bnx2x_phy_selection(struct link_params *params)
7533{
7534 u32 phy_config_swapped, prio_cfg;
7535 u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
7536
7537 phy_config_swapped = params->multi_phy_config &
7538 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
7539
7540 prio_cfg = params->multi_phy_config &
7541 PORT_HW_CFG_PHY_SELECTION_MASK;
7542
7543 if (phy_config_swapped) {
7544 switch (prio_cfg) {
7545 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
7546 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
7547 break;
7548 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
7549 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
7550 break;
7551 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
7552 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
7553 break;
7554 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
7555 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
7556 break;
7557 }
7558 } else
7559 return_cfg = prio_cfg;
7560
7561 return return_cfg;
7562}
7563
7564
de6eae1f
YR		 7565u8 bnx2x_phy_probe(struct link_params *params)
7566{
7567 u8 phy_index, actual_phy_idx, link_cfg_idx;
a22f0788 7568 u32 phy_config_swapped;
de6eae1f
YR		 7569 struct bnx2x *bp = params->bp;
7570 struct bnx2x_phy *phy;
7571 params->num_phys = 0;
7572 DP(NETIF_MSG_LINK, "Begin phy probe\n");
a22f0788
YR		 7573 phy_config_swapped = params->multi_phy_config &
7574 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
de6eae1f
YR		 7575
7576 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
7577 phy_index++) {
7578 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
7579 actual_phy_idx = phy_index;
a22f0788
YR		 7580 if (phy_config_swapped) {
7581 if (phy_index == EXT_PHY1)
7582 actual_phy_idx = EXT_PHY2;
7583 else if (phy_index == EXT_PHY2)
7584 actual_phy_idx = EXT_PHY1;
7585 }
7586 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
7587 " actual_phy_idx %x\n", phy_config_swapped,
7588 phy_index, actual_phy_idx);
de6eae1f
YR		 7589 phy = &params->phy[actual_phy_idx];
7590 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
a22f0788 7591 params->shmem2_base, params->port,
de6eae1f
YR		 7592 phy) != 0) {
7593 params->num_phys = 0;
7594 DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
7595 phy_index);
7596 for (phy_index = INT_PHY;
7597 phy_index < MAX_PHYS;
7598 phy_index++)
7599 *phy = phy_null;
7600 return -EINVAL;
7601 }
7602 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
7603 break;
7604
a22f0788 7605 bnx2x_phy_def_cfg(params, phy, phy_index);
de6eae1f
YR		 7606 params->num_phys++;
7607 }
7608
7609 DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
7610 return 0;
7611}
7612
de6eae1f
YR		 7613static void set_phy_vars(struct link_params *params)
7614{
7615 struct bnx2x *bp = params->bp;
a22f0788
YR		 7616 u8 actual_phy_idx, phy_index, link_cfg_idx;
7617 u8 phy_config_swapped = params->multi_phy_config &
7618 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
de6eae1f
YR		 7619 for (phy_index = INT_PHY; phy_index < params->num_phys;
7620 phy_index++) {
a22f0788 7621 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
de6eae1f 7622 actual_phy_idx = phy_index;
a22f0788
YR		 7623 if (phy_config_swapped) {
7624 if (phy_index == EXT_PHY1)
7625 actual_phy_idx = EXT_PHY2;
7626 else if (phy_index == EXT_PHY2)
7627 actual_phy_idx = EXT_PHY1;
7628 }
cd88ccee 7629 params->phy[actual_phy_idx].req_flow_ctrl =
a22f0788 7630 params->req_flow_ctrl[link_cfg_idx];
de6eae1f
YR		 7631
7632 params->phy[actual_phy_idx].req_line_speed =
a22f0788 7633 params->req_line_speed[link_cfg_idx];
de6eae1f
YR		 7634
7635 params->phy[actual_phy_idx].speed_cap_mask =
a22f0788 7636 params->speed_cap_mask[link_cfg_idx];
de6eae1f
YR		 7637
7638 params->phy[actual_phy_idx].req_duplex =
a22f0788 7639 params->req_duplex[link_cfg_idx];
de6eae1f
YR		 7640
7641 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
7642 " speed_cap_mask %x\n",
7643 params->phy[actual_phy_idx].req_flow_ctrl,
7644 params->phy[actual_phy_idx].req_line_speed,
7645 params->phy[actual_phy_idx].speed_cap_mask);
7646 }
7647}
7648
7649u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
7650{
7651 struct bnx2x *bp = params->bp;
de6eae1f 7652 DP(NETIF_MSG_LINK, "Phy Initialization started\n");
a22f0788
YR		 7653 DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
7654 params->req_line_speed[0], params->req_flow_ctrl[0]);
7655 DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
7656 params->req_line_speed[1], params->req_flow_ctrl[1]);
de6eae1f
YR		 7657 vars->link_status = 0;
7658 vars->phy_link_up = 0;
7659 vars->link_up = 0;
7660 vars->line_speed = 0;
7661 vars->duplex = DUPLEX_FULL;
7662 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7663 vars->mac_type = MAC_TYPE_NONE;
7664 vars->phy_flags = 0;
7665
7666 /* disable attentions */
7667 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
7668 (NIG_MASK_XGXS0_LINK_STATUS |
7669 NIG_MASK_XGXS0_LINK10G |
7670 NIG_MASK_SERDES0_LINK_STATUS |
7671 NIG_MASK_MI_INT));
7672
7673 bnx2x_emac_init(params, vars);
7674
7675 if (params->num_phys == 0) {
7676 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
7677 return -EINVAL;
7678 }
7679 set_phy_vars(params);
7680
7681 DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
de6eae1f
YR		 7682 if (params->loopback_mode == LOOPBACK_BMAC) {
7683
7684 vars->link_up = 1;
7685 vars->line_speed = SPEED_10000;
7686 vars->duplex = DUPLEX_FULL;
7687 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7688 vars->mac_type = MAC_TYPE_BMAC;
b7737c9b 7689
de6eae1f 7690 vars->phy_flags = PHY_XGXS_FLAG;
b7737c9b 7691
de6eae1f 7692 bnx2x_xgxs_deassert(params);
b7737c9b 7693
de6eae1f
YR		 7694 /* set bmac loopback */
7695 bnx2x_bmac_enable(params, vars, 1);
b7737c9b 7696
cd88ccee 7697 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
b7737c9b 7698
de6eae1f 7699 } else if (params->loopback_mode == LOOPBACK_EMAC) {
b7737c9b 7700
de6eae1f
YR		 7701 vars->link_up = 1;
7702 vars->line_speed = SPEED_1000;
7703 vars->duplex = DUPLEX_FULL;
7704 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7705 vars->mac_type = MAC_TYPE_EMAC;
b7737c9b 7706
de6eae1f 7707 vars->phy_flags = PHY_XGXS_FLAG;
e10bc84d 7708
de6eae1f
YR		 7709 bnx2x_xgxs_deassert(params);
7710 /* set bmac loopback */
7711 bnx2x_emac_enable(params, vars, 1);
7712 bnx2x_emac_program(params, vars);
cd88ccee 7713 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
b7737c9b 7714
de6eae1f
YR		 7715 } else if ((params->loopback_mode == LOOPBACK_XGXS) ||
7716 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
b7737c9b 7717
de6eae1f 7718 vars->link_up = 1;
de6eae1f 7719 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
a22f0788
YR		 7720 vars->duplex = DUPLEX_FULL;
7721 if (params->req_line_speed[0] == SPEED_1000) {
7722 vars->line_speed = SPEED_1000;
7723 vars->mac_type = MAC_TYPE_EMAC;
7724 } else {
7725 vars->line_speed = SPEED_10000;
7726 vars->mac_type = MAC_TYPE_BMAC;
7727 }
62b29a5d 7728
de6eae1f
YR		 7729 bnx2x_xgxs_deassert(params);
7730 bnx2x_link_initialize(params, vars);
c18aa15d 7731
a22f0788
YR		 7732 if (params->req_line_speed[0] == SPEED_1000) {
7733 bnx2x_emac_program(params, vars);
7734 bnx2x_emac_enable(params, vars, 0);
7735 } else
cd88ccee 7736 bnx2x_bmac_enable(params, vars, 0);
de6eae1f
YR		 7737 if (params->loopback_mode == LOOPBACK_XGXS) {
7738 /* set 10G XGXS loopback */
7739 params->phy[INT_PHY].config_loopback(
7740 &params->phy[INT_PHY],
7741 params);
c18aa15d 7742
de6eae1f
YR		 7743 } else {
7744 /* set external phy loopback */
7745 u8 phy_index;
7746 for (phy_index = EXT_PHY1;
7747 phy_index < params->num_phys; phy_index++) {
7748 if (params->phy[phy_index].config_loopback)
7749 params->phy[phy_index].config_loopback(
7750 &params->phy[phy_index],
7751 params);
7752 }
7753 }
cd88ccee 7754 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
de6eae1f 7755
7f02c4ad
YR		 7756 bnx2x_set_led(params, vars,
7757 LED_MODE_OPER, vars->line_speed);
de6eae1f
YR		 7758 } else
7759 /* No loopback */
7760 {
7761 if (params->switch_cfg == SWITCH_CFG_10G)
7762 bnx2x_xgxs_deassert(params);
7763 else
7764 bnx2x_serdes_deassert(bp, params->port);
7f02c4ad 7765
de6eae1f
YR		 7766 bnx2x_link_initialize(params, vars);
7767 msleep(30);
7768 bnx2x_link_int_enable(params);
7769 }
e10bc84d
YR		 7770 return 0;
7771}
de6eae1f 7772u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
cd88ccee 7773 u8 reset_ext_phy)
b7737c9b
YR		 7774{
7775 struct bnx2x *bp = params->bp;
cf1d972c 7776 u8 phy_index, port = params->port, clear_latch_ind = 0;
de6eae1f
YR		 7777 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
7778 /* disable attentions */
7779 vars->link_status = 0;
7780 bnx2x_update_mng(params, vars->link_status);
7781 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
cd88ccee
YR		 7782 (NIG_MASK_XGXS0_LINK_STATUS |
7783 NIG_MASK_XGXS0_LINK10G |
7784 NIG_MASK_SERDES0_LINK_STATUS |
7785 NIG_MASK_MI_INT));
b7737c9b 7786
de6eae1f
YR		 7787 /* activate nig drain */
7788 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
b7737c9b 7789
de6eae1f
YR		 7790 /* disable nig egress interface */
7791 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
7792 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
b7737c9b 7793
de6eae1f
YR		 7794 /* Stop BigMac rx */
7795 bnx2x_bmac_rx_disable(bp, port);
b7737c9b 7796
de6eae1f
YR		 7797 /* disable emac */
7798 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
b7737c9b 7799
de6eae1f 7800 msleep(10);
25985edc 7801 /* The PHY reset is controlled by GPIO 1
de6eae1f
YR		 7802 * Hold it as vars low
7803 */
7804 /* clear link led */
7f02c4ad
YR		 7805 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
7806
de6eae1f
YR		 7807 if (reset_ext_phy) {
7808 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
7809 phy_index++) {
7810 if (params->phy[phy_index].link_reset)
7811 params->phy[phy_index].link_reset(
7812 &params->phy[phy_index],
7813 params);
cf1d972c
YR		 7814 if (params->phy[phy_index].flags &
7815 FLAGS_REARM_LATCH_SIGNAL)
7816 clear_latch_ind = 1;
b7737c9b 7817 }
b7737c9b
YR		 7818 }
7819
cf1d972c
YR		 7820 if (clear_latch_ind) {
7821 /* Clear latching indication */
7822 bnx2x_rearm_latch_signal(bp, port, 0);
7823 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
7824 1 << NIG_LATCH_BC_ENABLE_MI_INT);
7825 }
de6eae1f
YR		 7826 if (params->phy[INT_PHY].link_reset)
7827 params->phy[INT_PHY].link_reset(
7828 &params->phy[INT_PHY], params);
7829 /* reset BigMac */
7830 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7831 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
b7737c9b 7832
de6eae1f
YR		 7833 /* disable nig ingress interface */
7834 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
7835 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
7836 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
7837 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
7838 vars->link_up = 0;
b7737c9b
YR		 7839 return 0;
7840}
7841
de6eae1f
YR		 7842/****************************************************************************/
7843/* Common function */
7844/****************************************************************************/
f2e0899f
DK		 7845static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp,
7846 u32 shmem_base_path[],
7847 u32 shmem2_base_path[], u8 phy_index,
7848 u32 chip_id)
6bbca910 7849{
e10bc84d
YR		 7850 struct bnx2x_phy phy[PORT_MAX];
7851 struct bnx2x_phy *phy_blk[PORT_MAX];
6bbca910 7852 u16 val;
c8e64df4 7853 s8 port = 0;
f2e0899f 7854 s8 port_of_path = 0;
c8e64df4
YR		 7855 u32 swap_val, swap_override;
7856 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7857 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7858 port ^= (swap_val && swap_override);
7859 bnx2x_ext_phy_hw_reset(bp, port);
6bbca910
YR		 7860 /* PART1 - Reset both phys */
7861 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
f2e0899f
DK		 7862 u32 shmem_base, shmem2_base;
7863 /* In E2, same phy is using for port0 of the two paths */
7864 if (CHIP_IS_E2(bp)) {
7865 shmem_base = shmem_base_path[port];
7866 shmem2_base = shmem2_base_path[port];
7867 port_of_path = 0;
7868 } else {
7869 shmem_base = shmem_base_path[0];
7870 shmem2_base = shmem2_base_path[0];
7871 port_of_path = port;
7872 }
7873
6bbca910 7874 /* Extract the ext phy address for the port */
a22f0788 7875 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
f2e0899f 7876 port_of_path, &phy[port]) !=
e10bc84d
YR		 7877 0) {
7878 DP(NETIF_MSG_LINK, "populate_phy failed\n");
7879 return -EINVAL;
7880 }
6bbca910 7881 /* disable attentions */
6a71bbe0
YR		 7882 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
7883 port_of_path*4,
cd88ccee
YR		 7884 (NIG_MASK_XGXS0_LINK_STATUS |
7885 NIG_MASK_XGXS0_LINK10G |
7886 NIG_MASK_SERDES0_LINK_STATUS |
7887 NIG_MASK_MI_INT));
6bbca910 7888
6bbca910
YR		 7889 /* Need to take the phy out of low power mode in order
7890 to write to access its registers */
7891 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
cd88ccee
YR		 7892 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
7893 port);
6bbca910
YR		 7894
7895 /* Reset the phy */
e10bc84d 7896 bnx2x_cl45_write(bp, &phy[port],
cd88ccee
YR		 7897 MDIO_PMA_DEVAD,
7898 MDIO_PMA_REG_CTRL,
7899 1<<15);
6bbca910
YR		 7900 }
7901
7902 /* Add delay of 150ms after reset */
7903 msleep(150);
7904
e10bc84d
YR		 7905 if (phy[PORT_0].addr & 0x1) {
7906 phy_blk[PORT_0] = &(phy[PORT_1]);
7907 phy_blk[PORT_1] = &(phy[PORT_0]);
7908 } else {
7909 phy_blk[PORT_0] = &(phy[PORT_0]);
7910 phy_blk[PORT_1] = &(phy[PORT_1]);
7911 }
7912
6bbca910
YR		 7913 /* PART2 - Download firmware to both phys */
7914 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
f2e0899f
DK		 7915 if (CHIP_IS_E2(bp))
7916 port_of_path = 0;
7917 else
7918 port_of_path = port;
6bbca910 7919
f2e0899f
DK		 7920 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
7921 phy_blk[port]->addr);
5c99274b
YR		 7922 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
7923 port_of_path))
6bbca910 7924 return -EINVAL;
6bbca910
YR		 7925
7926 /* Only set bit 10 = 1 (Tx power down) */
e10bc84d 7927 bnx2x_cl45_read(bp, phy_blk[port],
cd88ccee
YR		 7928 MDIO_PMA_DEVAD,
7929 MDIO_PMA_REG_TX_POWER_DOWN, &val);
6bbca910
YR		 7930
7931 /* Phase1 of TX_POWER_DOWN reset */
e10bc84d 7932 bnx2x_cl45_write(bp, phy_blk[port],
cd88ccee
YR		 7933 MDIO_PMA_DEVAD,
7934 MDIO_PMA_REG_TX_POWER_DOWN,
7935 (val | 1<<10));
6bbca910
YR		 7936 }
7937
2cf7acf9
YR		 7938 /*
7939 * Toggle Transmitter: Power down and then up with 600ms delay
7940 * between
7941 */
6bbca910
YR		 7942 msleep(600);
7943
7944 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
7945 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
f5372251 7946 /* Phase2 of POWER_DOWN_RESET */
6bbca910 7947 /* Release bit 10 (Release Tx power down) */
e10bc84d 7948 bnx2x_cl45_read(bp, phy_blk[port],
cd88ccee
YR		 7949 MDIO_PMA_DEVAD,
7950 MDIO_PMA_REG_TX_POWER_DOWN, &val);
6bbca910 7951
e10bc84d 7952 bnx2x_cl45_write(bp, phy_blk[port],
cd88ccee
YR		 7953 MDIO_PMA_DEVAD,
7954 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
6bbca910
YR		 7955 msleep(15);
7956
7957 /* Read modify write the SPI-ROM version select register */
e10bc84d 7958 bnx2x_cl45_read(bp, phy_blk[port],
cd88ccee
YR		 7959 MDIO_PMA_DEVAD,
7960 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
e10bc84d 7961 bnx2x_cl45_write(bp, phy_blk[port],
cd88ccee
YR		 7962 MDIO_PMA_DEVAD,
7963 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
6bbca910
YR		 7964
7965 /* set GPIO2 back to LOW */
7966 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
cd88ccee 7967 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6bbca910
YR		 7968 }
7969 return 0;
6bbca910 7970}
f2e0899f
DK		 7971static u8 bnx2x_8726_common_init_phy(struct bnx2x *bp,
7972 u32 shmem_base_path[],
7973 u32 shmem2_base_path[], u8 phy_index,
7974 u32 chip_id)
de6eae1f
YR		 7975{
7976 u32 val;
7977 s8 port;
7978 struct bnx2x_phy phy;
7979 /* Use port1 because of the static port-swap */
7980 /* Enable the module detection interrupt */
7981 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
7982 val |= ((1<<MISC_REGISTERS_GPIO_3)|
7983 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
7984 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
7985
650154bf 7986 bnx2x_ext_phy_hw_reset(bp, 0);
de6eae1f
YR		 7987 msleep(5);
7988 for (port = 0; port < PORT_MAX; port++) {
f2e0899f
DK		 7989 u32 shmem_base, shmem2_base;
7990
7991 /* In E2, same phy is using for port0 of the two paths */
7992 if (CHIP_IS_E2(bp)) {
7993 shmem_base = shmem_base_path[port];
7994 shmem2_base = shmem2_base_path[port];
7995 } else {
7996 shmem_base = shmem_base_path[0];
7997 shmem2_base = shmem2_base_path[0];
7998 }
de6eae1f 7999 /* Extract the ext phy address for the port */
a22f0788 8000 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
de6eae1f
YR		 8001 port, &phy) !=
8002 0) {
8003 DP(NETIF_MSG_LINK, "populate phy failed\n");
8004 return -EINVAL;
8005 }
8006
8007 /* Reset phy*/
8008 bnx2x_cl45_write(bp, &phy,
8009 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
8010
8011
8012 /* Set fault module detected LED on */
8013 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
cd88ccee
YR		 8014 MISC_REGISTERS_GPIO_HIGH,
8015 port);
de6eae1f
YR		 8016 }
8017
8018 return 0;
8019}
a8db5b4c
YR		 8020static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
8021 u8 *io_gpio, u8 *io_port)
8022{
8023
8024 u32 phy_gpio_reset = REG_RD(bp, shmem_base +
8025 offsetof(struct shmem_region,
8026 dev_info.port_hw_config[PORT_0].default_cfg));
8027 switch (phy_gpio_reset) {
8028 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
8029 *io_gpio = 0;
8030 *io_port = 0;
8031 break;
8032 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
8033 *io_gpio = 1;
8034 *io_port = 0;
8035 break;
8036 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
8037 *io_gpio = 2;
8038 *io_port = 0;
8039 break;
8040 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
8041 *io_gpio = 3;
8042 *io_port = 0;
8043 break;
8044 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
8045 *io_gpio = 0;
8046 *io_port = 1;
8047 break;
8048 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
8049 *io_gpio = 1;
8050 *io_port = 1;
8051 break;
8052 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
8053 *io_gpio = 2;
8054 *io_port = 1;
8055 break;
8056 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
8057 *io_gpio = 3;
8058 *io_port = 1;
8059 break;
8060 default:
8061 /* Don't override the io_gpio and io_port */
8062 break;
8063 }
8064}
f2e0899f
DK		 8065static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp,
8066 u32 shmem_base_path[],
8067 u32 shmem2_base_path[], u8 phy_index,
8068 u32 chip_id)
4d295db0 8069{
a8db5b4c 8070 s8 port, reset_gpio;
4d295db0 8071 u32 swap_val, swap_override;
e10bc84d
YR		 8072 struct bnx2x_phy phy[PORT_MAX];
8073 struct bnx2x_phy *phy_blk[PORT_MAX];
f2e0899f 8074 s8 port_of_path;
cd88ccee
YR		 8075 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8076 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
4d295db0 8077
a8db5b4c 8078 reset_gpio = MISC_REGISTERS_GPIO_1;
a22f0788 8079 port = 1;
4d295db0 8080
a8db5b4c
YR		 8081 /*
8082 * Retrieve the reset gpio/port which control the reset.
8083 * Default is GPIO1, PORT1
8084 */
8085 bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
8086 (u8 *)&reset_gpio, (u8 *)&port);
a22f0788
YR		 8087
8088 /* Calculate the port based on port swap */
8089 port ^= (swap_val && swap_override);
8090
a8db5b4c
YR		 8091 /* Initiate PHY reset*/
8092 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
8093 port);
8094 msleep(1);
8095 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
8096 port);
8097
a22f0788 8098 msleep(5);
bc7f0a05 8099
4d295db0 8100 /* PART1 - Reset both phys */
a22f0788 8101 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
f2e0899f
DK		 8102 u32 shmem_base, shmem2_base;
8103
8104 /* In E2, same phy is using for port0 of the two paths */
8105 if (CHIP_IS_E2(bp)) {
8106 shmem_base = shmem_base_path[port];
8107 shmem2_base = shmem2_base_path[port];
8108 port_of_path = 0;
8109 } else {
8110 shmem_base = shmem_base_path[0];
8111 shmem2_base = shmem2_base_path[0];
8112 port_of_path = port;
8113 }
8114
4d295db0 8115 /* Extract the ext phy address for the port */
a22f0788 8116 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
f2e0899f 8117 port_of_path, &phy[port]) !=
e10bc84d
YR		 8118 0) {
8119 DP(NETIF_MSG_LINK, "populate phy failed\n");
8120 return -EINVAL;
8121 }
4d295db0 8122 /* disable attentions */
f2e0899f
DK		 8123 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
8124 port_of_path*4,
8125 (NIG_MASK_XGXS0_LINK_STATUS |
8126 NIG_MASK_XGXS0_LINK10G |
8127 NIG_MASK_SERDES0_LINK_STATUS |
8128 NIG_MASK_MI_INT));
4d295db0 8129
4d295db0
EG		 8130
8131 /* Reset the phy */
e10bc84d 8132 bnx2x_cl45_write(bp, &phy[port],
cd88ccee 8133 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
4d295db0
EG		 8134 }
8135
8136 /* Add delay of 150ms after reset */
8137 msleep(150);
e10bc84d
YR		 8138 if (phy[PORT_0].addr & 0x1) {
8139 phy_blk[PORT_0] = &(phy[PORT_1]);
8140 phy_blk[PORT_1] = &(phy[PORT_0]);
8141 } else {
8142 phy_blk[PORT_0] = &(phy[PORT_0]);
8143 phy_blk[PORT_1] = &(phy[PORT_1]);
8144 }
4d295db0 8145 /* PART2 - Download firmware to both phys */
e10bc84d 8146 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
cd88ccee 8147 if (CHIP_IS_E2(bp))
f2e0899f
DK		 8148 port_of_path = 0;
8149 else
8150 port_of_path = port;
8151 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
8152 phy_blk[port]->addr);
5c99274b
YR		 8153 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
8154 port_of_path))
4d295db0 8155 return -EINVAL;
4d295db0 8156
5c99274b 8157 }
4d295db0
EG		 8158 return 0;
8159}
8160
f2e0899f
DK		 8161static u8 bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
8162 u32 shmem2_base_path[], u8 phy_index,
8163 u32 ext_phy_type, u32 chip_id)
6bbca910
YR		 8164{
8165 u8 rc = 0;
6bbca910
YR		 8166
8167 switch (ext_phy_type) {
8168 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
f2e0899f
DK		 8169 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
8170 shmem2_base_path,
8171 phy_index, chip_id);
6bbca910 8172 break;
e4d78f12 8173 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
4d295db0
EG		 8174 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8175 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
f2e0899f
DK		 8176 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
8177 shmem2_base_path,
8178 phy_index, chip_id);
4d295db0
EG		 8179 break;
8180
589abe3a 8181 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
2cf7acf9
YR		 8182 /*
8183 * GPIO1 affects both ports, so there's need to pull
8184 * it for single port alone
8185 */
f2e0899f
DK		 8186 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
8187 shmem2_base_path,
8188 phy_index, chip_id);
a22f0788
YR		 8189 break;
8190 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
8191 rc = -EINVAL;
4f60dab1 8192 break;
6bbca910
YR		 8193 default:
8194 DP(NETIF_MSG_LINK,
2cf7acf9
YR		 8195 "ext_phy 0x%x common init not required\n",
8196 ext_phy_type);
6bbca910
YR		 8197 break;
8198 }
8199
6d870c39
YR		 8200 if (rc != 0)
8201 netdev_err(bp->dev, "Warning: PHY was not initialized,"
8202 " Port %d\n",
8203 0);
6bbca910
YR		 8204 return rc;
8205}
8206
f2e0899f
DK		 8207u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
8208 u32 shmem2_base_path[], u32 chip_id)
a22f0788
YR		 8209{
8210 u8 rc = 0;
b21a3424 8211 u32 phy_ver;
a22f0788
YR		 8212 u8 phy_index;
8213 u32 ext_phy_type, ext_phy_config;
8214 DP(NETIF_MSG_LINK, "Begin common phy init\n");
8215
b21a3424
YR		 8216 /* Check if common init was already done */
8217 phy_ver = REG_RD(bp, shmem_base_path[0] +
8218 offsetof(struct shmem_region,
8219 port_mb[PORT_0].ext_phy_fw_version));
8220 if (phy_ver) {
8221 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
8222 phy_ver);
8223 return 0;
8224 }
8225
a22f0788
YR		 8226 /* Read the ext_phy_type for arbitrary port(0) */
8227 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
8228 phy_index++) {
8229 ext_phy_config = bnx2x_get_ext_phy_config(bp,
f2e0899f 8230 shmem_base_path[0],
a22f0788
YR		 8231 phy_index, 0);
8232 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
f2e0899f
DK		 8233 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
8234 shmem2_base_path,
8235 phy_index, ext_phy_type,
8236 chip_id);
a22f0788
YR		 8237 }
8238 return rc;
8239}
d90d96ba 8240
a22f0788 8241u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base)
d90d96ba
YR		 8242{
8243 u8 phy_index;
8244 struct bnx2x_phy phy;
8245 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
8246 phy_index++) {
a22f0788 8247 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
d90d96ba
YR		 8248 0, &phy) != 0) {
8249 DP(NETIF_MSG_LINK, "populate phy failed\n");
8250 return 0;
8251 }
8252
8253 if (phy.flags & FLAGS_HW_LOCK_REQUIRED)
8254 return 1;
8255 }
8256 return 0;
8257}
8258
8259u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
8260 u32 shmem_base,
a22f0788 8261 u32 shmem2_base,
d90d96ba
YR		 8262 u8 port)
8263{
8264 u8 phy_index, fan_failure_det_req = 0;
8265 struct bnx2x_phy phy;
8266 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
8267 phy_index++) {
a22f0788 8268 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
d90d96ba
YR		 8269 port, &phy)
8270 != 0) {
8271 DP(NETIF_MSG_LINK, "populate phy failed\n");
8272 return 0;
8273 }
8274 fan_failure_det_req |= (phy.flags &
8275 FLAGS_FAN_FAILURE_DET_REQ);
8276 }
8277 return fan_failure_det_req;
8278}
8279
8280void bnx2x_hw_reset_phy(struct link_params *params)
8281{
8282 u8 phy_index;
8283 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
8284 phy_index++) {
8285 if (params->phy[phy_index].hw_reset) {
8286 params->phy[phy_index].hw_reset(
8287 &params->phy[phy_index],
8288 params);
8289 params->phy[phy_index] = phy_null;
8290 }
8291 }
8292}
kernel source for telekom puls (alcatel/mediatek)