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d05c26ce | 1 | /* Copyright 2008-2009 Broadcom Corporation |
ea4e040a YR |
2 | * |
3 | * Unless you and Broadcom execute a separate written software license | |
4 | * agreement governing use of this software, this software is licensed to you | |
5 | * under the terms of the GNU General Public License version 2, available | |
6 | * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). | |
7 | * | |
8 | * Notwithstanding the above, under no circumstances may you combine this | |
9 | * software in any way with any other Broadcom software provided under a | |
10 | * license other than the GPL, without Broadcom's express prior written | |
11 | * consent. | |
12 | * | |
13 | * Written by Yaniv Rosner | |
14 | * | |
15 | */ | |
16 | ||
7995c64e JP |
17 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
18 | ||
ea4e040a YR |
19 | #include <linux/kernel.h> |
20 | #include <linux/errno.h> | |
21 | #include <linux/pci.h> | |
22 | #include <linux/netdevice.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/ethtool.h> | |
25 | #include <linux/mutex.h> | |
ea4e040a | 26 | |
ea4e040a YR |
27 | #include "bnx2x.h" |
28 | ||
29 | /********************************************************/ | |
3196a88a | 30 | #define ETH_HLEN 14 |
523224a3 | 31 | #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)/* 16 for CRC + VLAN + LLC */ |
ea4e040a YR |
32 | #define ETH_MIN_PACKET_SIZE 60 |
33 | #define ETH_MAX_PACKET_SIZE 1500 | |
34 | #define ETH_MAX_JUMBO_PACKET_SIZE 9600 | |
35 | #define MDIO_ACCESS_TIMEOUT 1000 | |
36 | #define BMAC_CONTROL_RX_ENABLE 2 | |
ea4e040a YR |
37 | |
38 | /***********************************************************/ | |
3196a88a | 39 | /* Shortcut definitions */ |
ea4e040a YR |
40 | /***********************************************************/ |
41 | ||
2f904460 EG |
42 | #define NIG_LATCH_BC_ENABLE_MI_INT 0 |
43 | ||
44 | #define NIG_STATUS_EMAC0_MI_INT \ | |
45 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT | |
ea4e040a YR |
46 | #define NIG_STATUS_XGXS0_LINK10G \ |
47 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G | |
48 | #define NIG_STATUS_XGXS0_LINK_STATUS \ | |
49 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS | |
50 | #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \ | |
51 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE | |
52 | #define NIG_STATUS_SERDES0_LINK_STATUS \ | |
53 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS | |
54 | #define NIG_MASK_MI_INT \ | |
55 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT | |
56 | #define NIG_MASK_XGXS0_LINK10G \ | |
57 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G | |
58 | #define NIG_MASK_XGXS0_LINK_STATUS \ | |
59 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS | |
60 | #define NIG_MASK_SERDES0_LINK_STATUS \ | |
61 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS | |
62 | ||
63 | #define MDIO_AN_CL73_OR_37_COMPLETE \ | |
64 | (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \ | |
65 | MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE) | |
66 | ||
67 | #define XGXS_RESET_BITS \ | |
68 | (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \ | |
69 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \ | |
70 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \ | |
71 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \ | |
72 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB) | |
73 | ||
74 | #define SERDES_RESET_BITS \ | |
75 | (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \ | |
76 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \ | |
77 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \ | |
78 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD) | |
79 | ||
80 | #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37 | |
81 | #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73 | |
3196a88a EG |
82 | #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM |
83 | #define AUTONEG_PARALLEL \ | |
ea4e040a | 84 | SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION |
3196a88a | 85 | #define AUTONEG_SGMII_FIBER_AUTODET \ |
ea4e040a | 86 | SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT |
3196a88a | 87 | #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY |
ea4e040a YR |
88 | |
89 | #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \ | |
90 | MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE | |
91 | #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \ | |
92 | MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE | |
93 | #define GP_STATUS_SPEED_MASK \ | |
94 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK | |
95 | #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M | |
96 | #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M | |
97 | #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G | |
98 | #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G | |
99 | #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G | |
100 | #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G | |
101 | #define GP_STATUS_10G_HIG \ | |
102 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG | |
103 | #define GP_STATUS_10G_CX4 \ | |
104 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 | |
105 | #define GP_STATUS_12G_HIG \ | |
106 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG | |
107 | #define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G | |
108 | #define GP_STATUS_13G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G | |
109 | #define GP_STATUS_15G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G | |
110 | #define GP_STATUS_16G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G | |
111 | #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX | |
112 | #define GP_STATUS_10G_KX4 \ | |
113 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 | |
114 | ||
115 | #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD | |
116 | #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD | |
117 | #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD | |
118 | #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4 | |
119 | #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD | |
120 | #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD | |
121 | #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD | |
122 | #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD | |
123 | #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD | |
124 | #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD | |
125 | #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD | |
126 | #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD | |
127 | #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD | |
128 | #define LINK_12GTFD LINK_STATUS_SPEED_AND_DUPLEX_12GTFD | |
129 | #define LINK_12GXFD LINK_STATUS_SPEED_AND_DUPLEX_12GXFD | |
130 | #define LINK_12_5GTFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD | |
131 | #define LINK_12_5GXFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD | |
132 | #define LINK_13GTFD LINK_STATUS_SPEED_AND_DUPLEX_13GTFD | |
133 | #define LINK_13GXFD LINK_STATUS_SPEED_AND_DUPLEX_13GXFD | |
134 | #define LINK_15GTFD LINK_STATUS_SPEED_AND_DUPLEX_15GTFD | |
135 | #define LINK_15GXFD LINK_STATUS_SPEED_AND_DUPLEX_15GXFD | |
136 | #define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD | |
137 | #define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD | |
138 | ||
139 | #define PHY_XGXS_FLAG 0x1 | |
140 | #define PHY_SGMII_FLAG 0x2 | |
141 | #define PHY_SERDES_FLAG 0x4 | |
142 | ||
589abe3a EG |
143 | /* */ |
144 | #define SFP_EEPROM_CON_TYPE_ADDR 0x2 | |
145 | #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7 | |
146 | #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21 | |
147 | ||
4d295db0 EG |
148 | |
149 | #define SFP_EEPROM_COMP_CODE_ADDR 0x3 | |
150 | #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4) | |
151 | #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5) | |
152 | #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6) | |
153 | ||
589abe3a EG |
154 | #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8 |
155 | #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4 | |
156 | #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8 | |
4d295db0 | 157 | |
589abe3a EG |
158 | #define SFP_EEPROM_OPTIONS_ADDR 0x40 |
159 | #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1 | |
160 | #define SFP_EEPROM_OPTIONS_SIZE 2 | |
161 | ||
4d295db0 EG |
162 | #define EDC_MODE_LINEAR 0x0022 |
163 | #define EDC_MODE_LIMITING 0x0044 | |
164 | #define EDC_MODE_PASSIVE_DAC 0x0055 | |
165 | ||
166 | ||
589abe3a | 167 | |
ea4e040a YR |
168 | /**********************************************************/ |
169 | /* INTERFACE */ | |
170 | /**********************************************************/ | |
e10bc84d YR |
171 | |
172 | #define CL45_WR_OVER_CL22(_bp, _phy, _bank, _addr, _val) \ | |
173 | bnx2x_cl45_write(_bp, _phy, \ | |
7aa0711f | 174 | (_phy)->def_md_devad, \ |
ea4e040a YR |
175 | (_bank + (_addr & 0xf)), \ |
176 | _val) | |
177 | ||
e10bc84d YR |
178 | #define CL45_RD_OVER_CL22(_bp, _phy, _bank, _addr, _val) \ |
179 | bnx2x_cl45_read(_bp, _phy, \ | |
7aa0711f | 180 | (_phy)->def_md_devad, \ |
ea4e040a YR |
181 | (_bank + (_addr & 0xf)), \ |
182 | _val) | |
183 | ||
8d96286a | 184 | static u8 bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy, |
185 | u8 devad, u16 reg, u16 *ret_val); | |
186 | ||
187 | static u8 bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy, | |
188 | u8 devad, u16 reg, u16 val); | |
189 | ||
ea4e040a YR |
190 | static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits) |
191 | { | |
192 | u32 val = REG_RD(bp, reg); | |
193 | ||
194 | val |= bits; | |
195 | REG_WR(bp, reg, val); | |
196 | return val; | |
197 | } | |
198 | ||
199 | static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits) | |
200 | { | |
201 | u32 val = REG_RD(bp, reg); | |
202 | ||
203 | val &= ~bits; | |
204 | REG_WR(bp, reg, val); | |
205 | return val; | |
206 | } | |
207 | ||
208 | static void bnx2x_emac_init(struct link_params *params, | |
209 | struct link_vars *vars) | |
210 | { | |
211 | /* reset and unreset the emac core */ | |
212 | struct bnx2x *bp = params->bp; | |
213 | u8 port = params->port; | |
214 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
215 | u32 val; | |
216 | u16 timeout; | |
217 | ||
218 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
219 | (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); | |
220 | udelay(5); | |
221 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, | |
222 | (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); | |
223 | ||
224 | /* init emac - use read-modify-write */ | |
225 | /* self clear reset */ | |
226 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); | |
3196a88a | 227 | EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET)); |
ea4e040a YR |
228 | |
229 | timeout = 200; | |
3196a88a | 230 | do { |
ea4e040a YR |
231 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); |
232 | DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val); | |
233 | if (!timeout) { | |
234 | DP(NETIF_MSG_LINK, "EMAC timeout!\n"); | |
235 | return; | |
236 | } | |
237 | timeout--; | |
3196a88a | 238 | } while (val & EMAC_MODE_RESET); |
ea4e040a YR |
239 | |
240 | /* Set mac address */ | |
241 | val = ((params->mac_addr[0] << 8) | | |
242 | params->mac_addr[1]); | |
3196a88a | 243 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val); |
ea4e040a YR |
244 | |
245 | val = ((params->mac_addr[2] << 24) | | |
246 | (params->mac_addr[3] << 16) | | |
247 | (params->mac_addr[4] << 8) | | |
248 | params->mac_addr[5]); | |
3196a88a | 249 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val); |
ea4e040a YR |
250 | } |
251 | ||
252 | static u8 bnx2x_emac_enable(struct link_params *params, | |
253 | struct link_vars *vars, u8 lb) | |
254 | { | |
255 | struct bnx2x *bp = params->bp; | |
256 | u8 port = params->port; | |
257 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
258 | u32 val; | |
259 | ||
260 | DP(NETIF_MSG_LINK, "enabling EMAC\n"); | |
261 | ||
262 | /* enable emac and not bmac */ | |
263 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1); | |
264 | ||
265 | /* for paladium */ | |
266 | if (CHIP_REV_IS_EMUL(bp)) { | |
267 | /* Use lane 1 (of lanes 0-3) */ | |
268 | REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1); | |
269 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + | |
270 | port*4, 1); | |
271 | } | |
272 | /* for fpga */ | |
273 | else | |
274 | ||
275 | if (CHIP_REV_IS_FPGA(bp)) { | |
276 | /* Use lane 1 (of lanes 0-3) */ | |
277 | DP(NETIF_MSG_LINK, "bnx2x_emac_enable: Setting FPGA\n"); | |
278 | ||
279 | REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1); | |
280 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, | |
281 | 0); | |
282 | } else | |
283 | /* ASIC */ | |
284 | if (vars->phy_flags & PHY_XGXS_FLAG) { | |
285 | u32 ser_lane = ((params->lane_config & | |
286 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> | |
287 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); | |
288 | ||
289 | DP(NETIF_MSG_LINK, "XGXS\n"); | |
290 | /* select the master lanes (out of 0-3) */ | |
291 | REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + | |
292 | port*4, ser_lane); | |
293 | /* select XGXS */ | |
294 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + | |
295 | port*4, 1); | |
296 | ||
297 | } else { /* SerDes */ | |
298 | DP(NETIF_MSG_LINK, "SerDes\n"); | |
299 | /* select SerDes */ | |
300 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + | |
301 | port*4, 0); | |
302 | } | |
303 | ||
811a2f2d EG |
304 | bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE, |
305 | EMAC_RX_MODE_RESET); | |
306 | bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, | |
307 | EMAC_TX_MODE_RESET); | |
ea4e040a YR |
308 | |
309 | if (CHIP_REV_IS_SLOW(bp)) { | |
310 | /* config GMII mode */ | |
311 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); | |
3196a88a | 312 | EMAC_WR(bp, EMAC_REG_EMAC_MODE, |
ea4e040a YR |
313 | (val | EMAC_MODE_PORT_GMII)); |
314 | } else { /* ASIC */ | |
315 | /* pause enable/disable */ | |
316 | bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE, | |
317 | EMAC_RX_MODE_FLOW_EN); | |
c0700f90 | 318 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) |
ea4e040a YR |
319 | bnx2x_bits_en(bp, emac_base + |
320 | EMAC_REG_EMAC_RX_MODE, | |
321 | EMAC_RX_MODE_FLOW_EN); | |
322 | ||
323 | bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE, | |
8c99e7b0 YR |
324 | (EMAC_TX_MODE_EXT_PAUSE_EN | |
325 | EMAC_TX_MODE_FLOW_EN)); | |
c0700f90 | 326 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) |
ea4e040a YR |
327 | bnx2x_bits_en(bp, emac_base + |
328 | EMAC_REG_EMAC_TX_MODE, | |
8c99e7b0 YR |
329 | (EMAC_TX_MODE_EXT_PAUSE_EN | |
330 | EMAC_TX_MODE_FLOW_EN)); | |
ea4e040a YR |
331 | } |
332 | ||
333 | /* KEEP_VLAN_TAG, promiscuous */ | |
334 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE); | |
335 | val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS; | |
3196a88a | 336 | EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val); |
ea4e040a YR |
337 | |
338 | /* Set Loopback */ | |
339 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); | |
340 | if (lb) | |
341 | val |= 0x810; | |
342 | else | |
343 | val &= ~0x810; | |
3196a88a | 344 | EMAC_WR(bp, EMAC_REG_EMAC_MODE, val); |
ea4e040a | 345 | |
6c55c3cd EG |
346 | /* enable emac */ |
347 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1); | |
348 | ||
ea4e040a | 349 | /* enable emac for jumbo packets */ |
3196a88a | 350 | EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE, |
ea4e040a YR |
351 | (EMAC_RX_MTU_SIZE_JUMBO_ENA | |
352 | (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD))); | |
353 | ||
354 | /* strip CRC */ | |
355 | REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1); | |
356 | ||
357 | /* disable the NIG in/out to the bmac */ | |
358 | REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0); | |
359 | REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0); | |
360 | REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0); | |
361 | ||
362 | /* enable the NIG in/out to the emac */ | |
363 | REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1); | |
364 | val = 0; | |
c0700f90 | 365 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) |
ea4e040a YR |
366 | val = 1; |
367 | ||
368 | REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val); | |
369 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1); | |
370 | ||
371 | if (CHIP_REV_IS_EMUL(bp)) { | |
372 | /* take the BigMac out of reset */ | |
373 | REG_WR(bp, | |
374 | GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, | |
375 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); | |
376 | ||
377 | /* enable access for bmac registers */ | |
378 | REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); | |
6f65497b EG |
379 | } else |
380 | REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0); | |
ea4e040a YR |
381 | |
382 | vars->mac_type = MAC_TYPE_EMAC; | |
383 | return 0; | |
384 | } | |
385 | ||
f2e0899f DK |
386 | static void bnx2x_update_bmac2(struct link_params *params, |
387 | struct link_vars *vars, | |
388 | u8 is_lb) | |
389 | { | |
390 | /* | |
391 | * Set rx control: Strip CRC and enable BigMAC to relay | |
392 | * control packets to the system as well | |
393 | */ | |
394 | u32 wb_data[2]; | |
395 | struct bnx2x *bp = params->bp; | |
396 | u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : | |
397 | NIG_REG_INGRESS_BMAC0_MEM; | |
398 | u32 val = 0x14; | |
ea4e040a | 399 | |
f2e0899f DK |
400 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) |
401 | /* Enable BigMAC to react on received Pause packets */ | |
402 | val |= (1<<5); | |
403 | wb_data[0] = val; | |
404 | wb_data[1] = 0; | |
405 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, | |
406 | wb_data, 2); | |
407 | udelay(30); | |
ea4e040a | 408 | |
f2e0899f DK |
409 | /* Tx control */ |
410 | val = 0xc0; | |
411 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) | |
412 | val |= 0x800000; | |
413 | wb_data[0] = val; | |
414 | wb_data[1] = 0; | |
415 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, | |
416 | wb_data, 2); | |
417 | ||
418 | val = 0x8000; | |
419 | wb_data[0] = val; | |
420 | wb_data[1] = 0; | |
421 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL, | |
422 | wb_data, 2); | |
423 | ||
424 | /* mac control */ | |
425 | val = 0x3; /* Enable RX and TX */ | |
426 | if (is_lb) { | |
427 | val |= 0x4; /* Local loopback */ | |
428 | DP(NETIF_MSG_LINK, "enable bmac loopback\n"); | |
429 | } | |
430 | ||
431 | wb_data[0] = val; | |
432 | wb_data[1] = 0; | |
433 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, | |
434 | wb_data, 2); | |
435 | } | |
436 | ||
437 | ||
438 | static u8 bnx2x_bmac1_enable(struct link_params *params, | |
439 | struct link_vars *vars, | |
ea4e040a YR |
440 | u8 is_lb) |
441 | { | |
442 | struct bnx2x *bp = params->bp; | |
443 | u8 port = params->port; | |
444 | u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : | |
445 | NIG_REG_INGRESS_BMAC0_MEM; | |
446 | u32 wb_data[2]; | |
447 | u32 val; | |
448 | ||
f2e0899f | 449 | DP(NETIF_MSG_LINK, "Enabling BigMAC1\n"); |
ea4e040a YR |
450 | |
451 | /* XGXS control */ | |
452 | wb_data[0] = 0x3c; | |
453 | wb_data[1] = 0; | |
454 | REG_WR_DMAE(bp, bmac_addr + | |
455 | BIGMAC_REGISTER_BMAC_XGXS_CONTROL, | |
456 | wb_data, 2); | |
457 | ||
458 | /* tx MAC SA */ | |
459 | wb_data[0] = ((params->mac_addr[2] << 24) | | |
460 | (params->mac_addr[3] << 16) | | |
461 | (params->mac_addr[4] << 8) | | |
462 | params->mac_addr[5]); | |
463 | wb_data[1] = ((params->mac_addr[0] << 8) | | |
464 | params->mac_addr[1]); | |
465 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, | |
466 | wb_data, 2); | |
467 | ||
468 | /* tx control */ | |
469 | val = 0xc0; | |
c0700f90 | 470 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) |
ea4e040a YR |
471 | val |= 0x800000; |
472 | wb_data[0] = val; | |
473 | wb_data[1] = 0; | |
474 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, | |
475 | wb_data, 2); | |
476 | ||
477 | /* mac control */ | |
478 | val = 0x3; | |
479 | if (is_lb) { | |
480 | val |= 0x4; | |
481 | DP(NETIF_MSG_LINK, "enable bmac loopback\n"); | |
482 | } | |
483 | wb_data[0] = val; | |
484 | wb_data[1] = 0; | |
485 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, | |
486 | wb_data, 2); | |
487 | ||
ea4e040a YR |
488 | /* set rx mtu */ |
489 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; | |
490 | wb_data[1] = 0; | |
491 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, | |
492 | wb_data, 2); | |
493 | ||
494 | /* rx control set to don't strip crc */ | |
495 | val = 0x14; | |
c0700f90 | 496 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) |
ea4e040a YR |
497 | val |= 0x20; |
498 | wb_data[0] = val; | |
499 | wb_data[1] = 0; | |
500 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, | |
501 | wb_data, 2); | |
502 | ||
503 | /* set tx mtu */ | |
504 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; | |
505 | wb_data[1] = 0; | |
506 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, | |
507 | wb_data, 2); | |
508 | ||
509 | /* set cnt max size */ | |
510 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; | |
511 | wb_data[1] = 0; | |
512 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, | |
513 | wb_data, 2); | |
514 | ||
515 | /* configure safc */ | |
516 | wb_data[0] = 0x1000200; | |
517 | wb_data[1] = 0; | |
518 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS, | |
519 | wb_data, 2); | |
520 | /* fix for emulation */ | |
521 | if (CHIP_REV_IS_EMUL(bp)) { | |
522 | wb_data[0] = 0xf000; | |
523 | wb_data[1] = 0; | |
524 | REG_WR_DMAE(bp, | |
525 | bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD, | |
526 | wb_data, 2); | |
527 | } | |
528 | ||
f2e0899f DK |
529 | |
530 | return 0; | |
531 | } | |
532 | ||
533 | static u8 bnx2x_bmac2_enable(struct link_params *params, | |
534 | struct link_vars *vars, | |
535 | u8 is_lb) | |
536 | { | |
537 | struct bnx2x *bp = params->bp; | |
538 | u8 port = params->port; | |
539 | u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : | |
540 | NIG_REG_INGRESS_BMAC0_MEM; | |
541 | u32 wb_data[2]; | |
542 | ||
543 | DP(NETIF_MSG_LINK, "Enabling BigMAC2\n"); | |
544 | ||
545 | wb_data[0] = 0; | |
546 | wb_data[1] = 0; | |
547 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, | |
548 | wb_data, 2); | |
549 | udelay(30); | |
550 | ||
551 | /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */ | |
552 | wb_data[0] = 0x3c; | |
553 | wb_data[1] = 0; | |
554 | REG_WR_DMAE(bp, bmac_addr + | |
555 | BIGMAC2_REGISTER_BMAC_XGXS_CONTROL, | |
556 | wb_data, 2); | |
557 | ||
558 | udelay(30); | |
559 | ||
560 | /* tx MAC SA */ | |
561 | wb_data[0] = ((params->mac_addr[2] << 24) | | |
562 | (params->mac_addr[3] << 16) | | |
563 | (params->mac_addr[4] << 8) | | |
564 | params->mac_addr[5]); | |
565 | wb_data[1] = ((params->mac_addr[0] << 8) | | |
566 | params->mac_addr[1]); | |
567 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR, | |
568 | wb_data, 2); | |
569 | ||
570 | udelay(30); | |
571 | ||
572 | /* Configure SAFC */ | |
573 | wb_data[0] = 0x1000200; | |
574 | wb_data[1] = 0; | |
575 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS, | |
576 | wb_data, 2); | |
577 | udelay(30); | |
578 | ||
579 | /* set rx mtu */ | |
580 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; | |
581 | wb_data[1] = 0; | |
582 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, | |
583 | wb_data, 2); | |
584 | udelay(30); | |
585 | ||
586 | /* set tx mtu */ | |
587 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; | |
588 | wb_data[1] = 0; | |
589 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, | |
590 | wb_data, 2); | |
591 | udelay(30); | |
592 | /* set cnt max size */ | |
593 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2; | |
594 | wb_data[1] = 0; | |
595 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, | |
596 | wb_data, 2); | |
597 | udelay(30); | |
598 | bnx2x_update_bmac2(params, vars, is_lb); | |
599 | ||
600 | return 0; | |
601 | } | |
602 | ||
8d96286a | 603 | static u8 bnx2x_bmac_enable(struct link_params *params, |
f2e0899f DK |
604 | struct link_vars *vars, |
605 | u8 is_lb) | |
606 | { | |
607 | u8 rc, port = params->port; | |
608 | struct bnx2x *bp = params->bp; | |
609 | u32 val; | |
610 | /* reset and unreset the BigMac */ | |
611 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
612 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); | |
1d9c05d4 | 613 | msleep(1); |
f2e0899f DK |
614 | |
615 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, | |
616 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); | |
617 | ||
618 | /* enable access for bmac registers */ | |
619 | REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); | |
620 | ||
621 | /* Enable BMAC according to BMAC type*/ | |
622 | if (CHIP_IS_E2(bp)) | |
623 | rc = bnx2x_bmac2_enable(params, vars, is_lb); | |
624 | else | |
625 | rc = bnx2x_bmac1_enable(params, vars, is_lb); | |
ea4e040a YR |
626 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1); |
627 | REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0); | |
628 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0); | |
629 | val = 0; | |
c0700f90 | 630 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) |
ea4e040a YR |
631 | val = 1; |
632 | REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val); | |
633 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0); | |
634 | REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0); | |
635 | REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0); | |
636 | REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1); | |
637 | REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1); | |
638 | ||
639 | vars->mac_type = MAC_TYPE_BMAC; | |
f2e0899f | 640 | return rc; |
ea4e040a YR |
641 | } |
642 | ||
ea4e040a YR |
643 | |
644 | static void bnx2x_update_mng(struct link_params *params, u32 link_status) | |
645 | { | |
646 | struct bnx2x *bp = params->bp; | |
ab6ad5a4 | 647 | |
ea4e040a YR |
648 | REG_WR(bp, params->shmem_base + |
649 | offsetof(struct shmem_region, | |
650 | port_mb[params->port].link_status), | |
651 | link_status); | |
652 | } | |
653 | ||
654 | static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port) | |
655 | { | |
656 | u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : | |
657 | NIG_REG_INGRESS_BMAC0_MEM; | |
658 | u32 wb_data[2]; | |
3196a88a | 659 | u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4); |
ea4e040a YR |
660 | |
661 | /* Only if the bmac is out of reset */ | |
662 | if (REG_RD(bp, MISC_REG_RESET_REG_2) & | |
663 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) && | |
664 | nig_bmac_enable) { | |
665 | ||
f2e0899f DK |
666 | if (CHIP_IS_E2(bp)) { |
667 | /* Clear Rx Enable bit in BMAC_CONTROL register */ | |
668 | REG_RD_DMAE(bp, bmac_addr + | |
669 | BIGMAC2_REGISTER_BMAC_CONTROL, | |
670 | wb_data, 2); | |
671 | wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; | |
672 | REG_WR_DMAE(bp, bmac_addr + | |
673 | BIGMAC2_REGISTER_BMAC_CONTROL, | |
674 | wb_data, 2); | |
675 | } else { | |
676 | /* Clear Rx Enable bit in BMAC_CONTROL register */ | |
677 | REG_RD_DMAE(bp, bmac_addr + | |
678 | BIGMAC_REGISTER_BMAC_CONTROL, | |
679 | wb_data, 2); | |
680 | wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; | |
681 | REG_WR_DMAE(bp, bmac_addr + | |
682 | BIGMAC_REGISTER_BMAC_CONTROL, | |
683 | wb_data, 2); | |
684 | } | |
ea4e040a YR |
685 | msleep(1); |
686 | } | |
687 | } | |
688 | ||
689 | static u8 bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl, | |
690 | u32 line_speed) | |
691 | { | |
692 | struct bnx2x *bp = params->bp; | |
693 | u8 port = params->port; | |
694 | u32 init_crd, crd; | |
695 | u32 count = 1000; | |
ea4e040a YR |
696 | |
697 | /* disable port */ | |
698 | REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1); | |
699 | ||
700 | /* wait for init credit */ | |
701 | init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4); | |
702 | crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); | |
703 | DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd); | |
704 | ||
705 | while ((init_crd != crd) && count) { | |
706 | msleep(5); | |
707 | ||
708 | crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); | |
709 | count--; | |
710 | } | |
711 | crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); | |
712 | if (init_crd != crd) { | |
713 | DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n", | |
714 | init_crd, crd); | |
715 | return -EINVAL; | |
716 | } | |
717 | ||
c0700f90 | 718 | if (flow_ctrl & BNX2X_FLOW_CTRL_RX || |
8c99e7b0 YR |
719 | line_speed == SPEED_10 || |
720 | line_speed == SPEED_100 || | |
721 | line_speed == SPEED_1000 || | |
722 | line_speed == SPEED_2500) { | |
723 | REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1); | |
ea4e040a YR |
724 | /* update threshold */ |
725 | REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0); | |
726 | /* update init credit */ | |
8c99e7b0 | 727 | init_crd = 778; /* (800-18-4) */ |
ea4e040a YR |
728 | |
729 | } else { | |
730 | u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE + | |
731 | ETH_OVREHEAD)/16; | |
8c99e7b0 | 732 | REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); |
ea4e040a YR |
733 | /* update threshold */ |
734 | REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh); | |
735 | /* update init credit */ | |
736 | switch (line_speed) { | |
ea4e040a YR |
737 | case SPEED_10000: |
738 | init_crd = thresh + 553 - 22; | |
739 | break; | |
740 | ||
741 | case SPEED_12000: | |
742 | init_crd = thresh + 664 - 22; | |
743 | break; | |
744 | ||
745 | case SPEED_13000: | |
746 | init_crd = thresh + 742 - 22; | |
747 | break; | |
748 | ||
749 | case SPEED_16000: | |
750 | init_crd = thresh + 778 - 22; | |
751 | break; | |
752 | default: | |
753 | DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", | |
754 | line_speed); | |
755 | return -EINVAL; | |
ea4e040a YR |
756 | } |
757 | } | |
758 | REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd); | |
759 | DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n", | |
760 | line_speed, init_crd); | |
761 | ||
762 | /* probe the credit changes */ | |
763 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1); | |
764 | msleep(5); | |
765 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0); | |
766 | ||
767 | /* enable port */ | |
768 | REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0); | |
769 | return 0; | |
770 | } | |
771 | ||
c18aa15d YR |
772 | static u32 bnx2x_get_emac_base(struct bnx2x *bp, |
773 | u32 mdc_mdio_access, u8 port) | |
ea4e040a | 774 | { |
c18aa15d YR |
775 | u32 emac_base = 0; |
776 | switch (mdc_mdio_access) { | |
777 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE: | |
778 | break; | |
779 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0: | |
780 | if (REG_RD(bp, NIG_REG_PORT_SWAP)) | |
781 | emac_base = GRCBASE_EMAC1; | |
782 | else | |
783 | emac_base = GRCBASE_EMAC0; | |
784 | break; | |
785 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1: | |
589abe3a EG |
786 | if (REG_RD(bp, NIG_REG_PORT_SWAP)) |
787 | emac_base = GRCBASE_EMAC0; | |
788 | else | |
789 | emac_base = GRCBASE_EMAC1; | |
ea4e040a | 790 | break; |
c18aa15d YR |
791 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH: |
792 | emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
793 | break; | |
794 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED: | |
6378c025 | 795 | emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1; |
ea4e040a YR |
796 | break; |
797 | default: | |
ea4e040a YR |
798 | break; |
799 | } | |
800 | return emac_base; | |
801 | ||
802 | } | |
803 | ||
e10bc84d YR |
804 | u8 bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy, |
805 | u8 devad, u16 reg, u16 val) | |
ea4e040a YR |
806 | { |
807 | u32 tmp, saved_mode; | |
808 | u8 i, rc = 0; | |
ea4e040a YR |
809 | |
810 | /* set clause 45 mode, slow down the MDIO clock to 2.5MHz | |
811 | * (a value of 49==0x31) and make sure that the AUTO poll is off | |
812 | */ | |
589abe3a | 813 | |
e10bc84d | 814 | saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); |
ea4e040a YR |
815 | tmp = saved_mode & ~(EMAC_MDIO_MODE_AUTO_POLL | |
816 | EMAC_MDIO_MODE_CLOCK_CNT); | |
817 | tmp |= (EMAC_MDIO_MODE_CLAUSE_45 | | |
818 | (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT)); | |
e10bc84d YR |
819 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp); |
820 | REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); | |
ea4e040a YR |
821 | udelay(40); |
822 | ||
823 | /* address */ | |
824 | ||
e10bc84d | 825 | tmp = ((phy->addr << 21) | (devad << 16) | reg | |
ea4e040a YR |
826 | EMAC_MDIO_COMM_COMMAND_ADDRESS | |
827 | EMAC_MDIO_COMM_START_BUSY); | |
e10bc84d | 828 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); |
ea4e040a YR |
829 | |
830 | for (i = 0; i < 50; i++) { | |
831 | udelay(10); | |
832 | ||
e10bc84d YR |
833 | tmp = REG_RD(bp, phy->mdio_ctrl + |
834 | EMAC_REG_EMAC_MDIO_COMM); | |
ea4e040a YR |
835 | if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { |
836 | udelay(5); | |
837 | break; | |
838 | } | |
839 | } | |
840 | if (tmp & EMAC_MDIO_COMM_START_BUSY) { | |
841 | DP(NETIF_MSG_LINK, "write phy register failed\n"); | |
842 | rc = -EFAULT; | |
843 | } else { | |
844 | /* data */ | |
e10bc84d | 845 | tmp = ((phy->addr << 21) | (devad << 16) | val | |
ea4e040a YR |
846 | EMAC_MDIO_COMM_COMMAND_WRITE_45 | |
847 | EMAC_MDIO_COMM_START_BUSY); | |
e10bc84d | 848 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); |
ea4e040a YR |
849 | |
850 | for (i = 0; i < 50; i++) { | |
851 | udelay(10); | |
852 | ||
e10bc84d | 853 | tmp = REG_RD(bp, phy->mdio_ctrl + |
ea4e040a YR |
854 | EMAC_REG_EMAC_MDIO_COMM); |
855 | if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { | |
856 | udelay(5); | |
857 | break; | |
858 | } | |
859 | } | |
860 | if (tmp & EMAC_MDIO_COMM_START_BUSY) { | |
861 | DP(NETIF_MSG_LINK, "write phy register failed\n"); | |
862 | rc = -EFAULT; | |
863 | } | |
864 | } | |
865 | ||
866 | /* Restore the saved mode */ | |
e10bc84d | 867 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode); |
ea4e040a YR |
868 | |
869 | return rc; | |
870 | } | |
871 | ||
e10bc84d YR |
872 | u8 bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy, |
873 | u8 devad, u16 reg, u16 *ret_val) | |
ea4e040a YR |
874 | { |
875 | u32 val, saved_mode; | |
876 | u16 i; | |
877 | u8 rc = 0; | |
878 | ||
ea4e040a YR |
879 | /* set clause 45 mode, slow down the MDIO clock to 2.5MHz |
880 | * (a value of 49==0x31) and make sure that the AUTO poll is off | |
881 | */ | |
589abe3a | 882 | |
e10bc84d YR |
883 | saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); |
884 | val = saved_mode & ~((EMAC_MDIO_MODE_AUTO_POLL | | |
ea4e040a YR |
885 | EMAC_MDIO_MODE_CLOCK_CNT)); |
886 | val |= (EMAC_MDIO_MODE_CLAUSE_45 | | |
ab6ad5a4 | 887 | (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT)); |
e10bc84d YR |
888 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val); |
889 | REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); | |
ea4e040a YR |
890 | udelay(40); |
891 | ||
892 | /* address */ | |
e10bc84d | 893 | val = ((phy->addr << 21) | (devad << 16) | reg | |
ea4e040a YR |
894 | EMAC_MDIO_COMM_COMMAND_ADDRESS | |
895 | EMAC_MDIO_COMM_START_BUSY); | |
e10bc84d | 896 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); |
ea4e040a YR |
897 | |
898 | for (i = 0; i < 50; i++) { | |
899 | udelay(10); | |
900 | ||
e10bc84d | 901 | val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); |
ea4e040a YR |
902 | if (!(val & EMAC_MDIO_COMM_START_BUSY)) { |
903 | udelay(5); | |
904 | break; | |
905 | } | |
906 | } | |
907 | if (val & EMAC_MDIO_COMM_START_BUSY) { | |
908 | DP(NETIF_MSG_LINK, "read phy register failed\n"); | |
909 | ||
910 | *ret_val = 0; | |
911 | rc = -EFAULT; | |
912 | ||
913 | } else { | |
914 | /* data */ | |
e10bc84d | 915 | val = ((phy->addr << 21) | (devad << 16) | |
ea4e040a YR |
916 | EMAC_MDIO_COMM_COMMAND_READ_45 | |
917 | EMAC_MDIO_COMM_START_BUSY); | |
e10bc84d | 918 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); |
ea4e040a YR |
919 | |
920 | for (i = 0; i < 50; i++) { | |
921 | udelay(10); | |
922 | ||
e10bc84d | 923 | val = REG_RD(bp, phy->mdio_ctrl + |
ea4e040a YR |
924 | EMAC_REG_EMAC_MDIO_COMM); |
925 | if (!(val & EMAC_MDIO_COMM_START_BUSY)) { | |
926 | *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); | |
927 | break; | |
928 | } | |
929 | } | |
930 | if (val & EMAC_MDIO_COMM_START_BUSY) { | |
931 | DP(NETIF_MSG_LINK, "read phy register failed\n"); | |
932 | ||
933 | *ret_val = 0; | |
934 | rc = -EFAULT; | |
935 | } | |
936 | } | |
937 | ||
938 | /* Restore the saved mode */ | |
e10bc84d | 939 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode); |
ea4e040a YR |
940 | |
941 | return rc; | |
942 | } | |
943 | ||
e10bc84d YR |
944 | u8 bnx2x_phy_read(struct link_params *params, u8 phy_addr, |
945 | u8 devad, u16 reg, u16 *ret_val) | |
946 | { | |
947 | u8 phy_index; | |
948 | /** | |
949 | * Probe for the phy according to the given phy_addr, and execute | |
950 | * the read request on it | |
951 | */ | |
952 | for (phy_index = 0; phy_index < params->num_phys; phy_index++) { | |
953 | if (params->phy[phy_index].addr == phy_addr) { | |
954 | return bnx2x_cl45_read(params->bp, | |
955 | ¶ms->phy[phy_index], devad, | |
956 | reg, ret_val); | |
957 | } | |
958 | } | |
959 | return -EINVAL; | |
960 | } | |
961 | ||
962 | u8 bnx2x_phy_write(struct link_params *params, u8 phy_addr, | |
963 | u8 devad, u16 reg, u16 val) | |
964 | { | |
965 | u8 phy_index; | |
966 | /** | |
967 | * Probe for the phy according to the given phy_addr, and execute | |
968 | * the write request on it | |
969 | */ | |
970 | for (phy_index = 0; phy_index < params->num_phys; phy_index++) { | |
971 | if (params->phy[phy_index].addr == phy_addr) { | |
972 | return bnx2x_cl45_write(params->bp, | |
973 | ¶ms->phy[phy_index], devad, | |
974 | reg, val); | |
975 | } | |
976 | } | |
977 | return -EINVAL; | |
978 | } | |
979 | ||
f2e0899f DK |
980 | static void bnx2x_set_aer_mmd_xgxs(struct link_params *params, |
981 | struct bnx2x_phy *phy) | |
ea4e040a | 982 | { |
ea4e040a | 983 | u32 ser_lane; |
f2e0899f DK |
984 | u16 offset, aer_val; |
985 | struct bnx2x *bp = params->bp; | |
ea4e040a YR |
986 | ser_lane = ((params->lane_config & |
987 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> | |
988 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); | |
989 | ||
f2e0899f DK |
990 | offset = phy->addr + ser_lane; |
991 | if (CHIP_IS_E2(bp)) | |
992 | aer_val = 0x2800 + offset - 1; | |
993 | else | |
994 | aer_val = 0x3800 + offset; | |
e10bc84d | 995 | CL45_WR_OVER_CL22(bp, phy, |
f2e0899f DK |
996 | MDIO_REG_BANK_AER_BLOCK, |
997 | MDIO_AER_BLOCK_AER_REG, aer_val); | |
998 | } | |
999 | static void bnx2x_set_aer_mmd_serdes(struct bnx2x *bp, | |
1000 | struct bnx2x_phy *phy) | |
1001 | { | |
1002 | CL45_WR_OVER_CL22(bp, phy, | |
1003 | MDIO_REG_BANK_AER_BLOCK, | |
1004 | MDIO_AER_BLOCK_AER_REG, 0x3800); | |
ea4e040a YR |
1005 | } |
1006 | ||
de6eae1f YR |
1007 | /******************************************************************/ |
1008 | /* Internal phy section */ | |
1009 | /******************************************************************/ | |
ea4e040a | 1010 | |
de6eae1f YR |
1011 | static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port) |
1012 | { | |
1013 | u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
ea4e040a | 1014 | |
de6eae1f YR |
1015 | /* Set Clause 22 */ |
1016 | REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1); | |
1017 | REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000); | |
1018 | udelay(500); | |
1019 | REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f); | |
1020 | udelay(500); | |
1021 | /* Set Clause 45 */ | |
1022 | REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0); | |
ea4e040a YR |
1023 | } |
1024 | ||
de6eae1f | 1025 | static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port) |
ea4e040a | 1026 | { |
de6eae1f | 1027 | u32 val; |
ea4e040a | 1028 | |
de6eae1f | 1029 | DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n"); |
ea4e040a | 1030 | |
de6eae1f | 1031 | val = SERDES_RESET_BITS << (port*16); |
c1b73990 | 1032 | |
de6eae1f YR |
1033 | /* reset and unreset the SerDes/XGXS */ |
1034 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); | |
1035 | udelay(500); | |
1036 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); | |
ea4e040a | 1037 | |
de6eae1f | 1038 | bnx2x_set_serdes_access(bp, port); |
ea4e040a | 1039 | |
de6eae1f YR |
1040 | REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + |
1041 | port*0x10, | |
1042 | DEFAULT_PHY_DEV_ADDR); | |
1043 | } | |
1044 | ||
1045 | static void bnx2x_xgxs_deassert(struct link_params *params) | |
1046 | { | |
1047 | struct bnx2x *bp = params->bp; | |
1048 | u8 port; | |
1049 | u32 val; | |
1050 | DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n"); | |
1051 | port = params->port; | |
1052 | ||
1053 | val = XGXS_RESET_BITS << (port*16); | |
1054 | ||
1055 | /* reset and unreset the SerDes/XGXS */ | |
1056 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); | |
1057 | udelay(500); | |
1058 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); | |
1059 | ||
1060 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + | |
1061 | port*0x18, 0); | |
1062 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, | |
1063 | params->phy[INT_PHY].def_md_devad); | |
1064 | } | |
1065 | ||
a22f0788 | 1066 | |
de6eae1f YR |
1067 | void bnx2x_link_status_update(struct link_params *params, |
1068 | struct link_vars *vars) | |
1069 | { | |
1070 | struct bnx2x *bp = params->bp; | |
1071 | u8 link_10g; | |
1072 | u8 port = params->port; | |
1073 | ||
de6eae1f YR |
1074 | vars->link_status = REG_RD(bp, params->shmem_base + |
1075 | offsetof(struct shmem_region, | |
1076 | port_mb[port].link_status)); | |
1077 | ||
1078 | vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP); | |
1079 | ||
1080 | if (vars->link_up) { | |
1081 | DP(NETIF_MSG_LINK, "phy link up\n"); | |
1082 | ||
1083 | vars->phy_link_up = 1; | |
1084 | vars->duplex = DUPLEX_FULL; | |
1085 | switch (vars->link_status & | |
1086 | LINK_STATUS_SPEED_AND_DUPLEX_MASK) { | |
1087 | case LINK_10THD: | |
1088 | vars->duplex = DUPLEX_HALF; | |
1089 | /* fall thru */ | |
1090 | case LINK_10TFD: | |
1091 | vars->line_speed = SPEED_10; | |
1092 | break; | |
1093 | ||
1094 | case LINK_100TXHD: | |
1095 | vars->duplex = DUPLEX_HALF; | |
1096 | /* fall thru */ | |
1097 | case LINK_100T4: | |
1098 | case LINK_100TXFD: | |
1099 | vars->line_speed = SPEED_100; | |
1100 | break; | |
1101 | ||
1102 | case LINK_1000THD: | |
1103 | vars->duplex = DUPLEX_HALF; | |
1104 | /* fall thru */ | |
1105 | case LINK_1000TFD: | |
1106 | vars->line_speed = SPEED_1000; | |
1107 | break; | |
1108 | ||
1109 | case LINK_2500THD: | |
1110 | vars->duplex = DUPLEX_HALF; | |
1111 | /* fall thru */ | |
1112 | case LINK_2500TFD: | |
1113 | vars->line_speed = SPEED_2500; | |
1114 | break; | |
1115 | ||
1116 | case LINK_10GTFD: | |
1117 | vars->line_speed = SPEED_10000; | |
1118 | break; | |
1119 | ||
1120 | case LINK_12GTFD: | |
1121 | vars->line_speed = SPEED_12000; | |
1122 | break; | |
1123 | ||
1124 | case LINK_12_5GTFD: | |
1125 | vars->line_speed = SPEED_12500; | |
1126 | break; | |
1127 | ||
1128 | case LINK_13GTFD: | |
1129 | vars->line_speed = SPEED_13000; | |
1130 | break; | |
1131 | ||
1132 | case LINK_15GTFD: | |
1133 | vars->line_speed = SPEED_15000; | |
1134 | break; | |
1135 | ||
1136 | case LINK_16GTFD: | |
1137 | vars->line_speed = SPEED_16000; | |
1138 | break; | |
1139 | ||
1140 | default: | |
1141 | break; | |
1142 | } | |
de6eae1f YR |
1143 | vars->flow_ctrl = 0; |
1144 | if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED) | |
1145 | vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX; | |
1146 | ||
1147 | if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED) | |
1148 | vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX; | |
1149 | ||
1150 | if (!vars->flow_ctrl) | |
1151 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
1152 | ||
1153 | if (vars->line_speed && | |
1154 | ((vars->line_speed == SPEED_10) || | |
1155 | (vars->line_speed == SPEED_100))) { | |
1156 | vars->phy_flags |= PHY_SGMII_FLAG; | |
1157 | } else { | |
1158 | vars->phy_flags &= ~PHY_SGMII_FLAG; | |
1159 | } | |
1160 | ||
1161 | /* anything 10 and over uses the bmac */ | |
1162 | link_10g = ((vars->line_speed == SPEED_10000) || | |
1163 | (vars->line_speed == SPEED_12000) || | |
1164 | (vars->line_speed == SPEED_12500) || | |
1165 | (vars->line_speed == SPEED_13000) || | |
1166 | (vars->line_speed == SPEED_15000) || | |
1167 | (vars->line_speed == SPEED_16000)); | |
1168 | if (link_10g) | |
1169 | vars->mac_type = MAC_TYPE_BMAC; | |
1170 | else | |
1171 | vars->mac_type = MAC_TYPE_EMAC; | |
1172 | ||
1173 | } else { /* link down */ | |
1174 | DP(NETIF_MSG_LINK, "phy link down\n"); | |
1175 | ||
1176 | vars->phy_link_up = 0; | |
1177 | ||
1178 | vars->line_speed = 0; | |
1179 | vars->duplex = DUPLEX_FULL; | |
1180 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
1181 | ||
1182 | /* indicate no mac active */ | |
1183 | vars->mac_type = MAC_TYPE_NONE; | |
1184 | } | |
1185 | ||
1186 | DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x\n", | |
1187 | vars->link_status, vars->phy_link_up); | |
1188 | DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n", | |
1189 | vars->line_speed, vars->duplex, vars->flow_ctrl); | |
1190 | } | |
1191 | ||
1192 | ||
1193 | static void bnx2x_set_master_ln(struct link_params *params, | |
1194 | struct bnx2x_phy *phy) | |
1195 | { | |
1196 | struct bnx2x *bp = params->bp; | |
1197 | u16 new_master_ln, ser_lane; | |
1198 | ser_lane = ((params->lane_config & | |
1199 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> | |
1200 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); | |
1201 | ||
1202 | /* set the master_ln for AN */ | |
1203 | CL45_RD_OVER_CL22(bp, phy, | |
1204 | MDIO_REG_BANK_XGXS_BLOCK2, | |
1205 | MDIO_XGXS_BLOCK2_TEST_MODE_LANE, | |
1206 | &new_master_ln); | |
1207 | ||
1208 | CL45_WR_OVER_CL22(bp, phy, | |
1209 | MDIO_REG_BANK_XGXS_BLOCK2 , | |
1210 | MDIO_XGXS_BLOCK2_TEST_MODE_LANE, | |
1211 | (new_master_ln | ser_lane)); | |
1212 | } | |
1213 | ||
1214 | static u8 bnx2x_reset_unicore(struct link_params *params, | |
1215 | struct bnx2x_phy *phy, | |
1216 | u8 set_serdes) | |
1217 | { | |
1218 | struct bnx2x *bp = params->bp; | |
1219 | u16 mii_control; | |
1220 | u16 i; | |
1221 | ||
1222 | CL45_RD_OVER_CL22(bp, phy, | |
1223 | MDIO_REG_BANK_COMBO_IEEE0, | |
1224 | MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control); | |
1225 | ||
1226 | /* reset the unicore */ | |
1227 | CL45_WR_OVER_CL22(bp, phy, | |
1228 | MDIO_REG_BANK_COMBO_IEEE0, | |
1229 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
1230 | (mii_control | | |
1231 | MDIO_COMBO_IEEO_MII_CONTROL_RESET)); | |
1232 | if (set_serdes) | |
1233 | bnx2x_set_serdes_access(bp, params->port); | |
1234 | ||
1235 | /* wait for the reset to self clear */ | |
1236 | for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) { | |
1237 | udelay(5); | |
1238 | ||
1239 | /* the reset erased the previous bank value */ | |
1240 | CL45_RD_OVER_CL22(bp, phy, | |
1241 | MDIO_REG_BANK_COMBO_IEEE0, | |
1242 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
1243 | &mii_control); | |
1244 | ||
1245 | if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) { | |
1246 | udelay(5); | |
1247 | return 0; | |
1248 | } | |
1249 | } | |
ea4e040a YR |
1250 | |
1251 | DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n"); | |
1252 | return -EINVAL; | |
1253 | ||
1254 | } | |
1255 | ||
e10bc84d YR |
1256 | static void bnx2x_set_swap_lanes(struct link_params *params, |
1257 | struct bnx2x_phy *phy) | |
ea4e040a YR |
1258 | { |
1259 | struct bnx2x *bp = params->bp; | |
1260 | /* Each two bits represents a lane number: | |
1261 | No swap is 0123 => 0x1b no need to enable the swap */ | |
1262 | u16 ser_lane, rx_lane_swap, tx_lane_swap; | |
1263 | ||
1264 | ser_lane = ((params->lane_config & | |
1265 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> | |
1266 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); | |
1267 | rx_lane_swap = ((params->lane_config & | |
1268 | PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >> | |
1269 | PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT); | |
1270 | tx_lane_swap = ((params->lane_config & | |
1271 | PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >> | |
1272 | PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT); | |
1273 | ||
1274 | if (rx_lane_swap != 0x1b) { | |
e10bc84d | 1275 | CL45_WR_OVER_CL22(bp, phy, |
ea4e040a YR |
1276 | MDIO_REG_BANK_XGXS_BLOCK2, |
1277 | MDIO_XGXS_BLOCK2_RX_LN_SWAP, | |
1278 | (rx_lane_swap | | |
1279 | MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE | | |
1280 | MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE)); | |
1281 | } else { | |
e10bc84d | 1282 | CL45_WR_OVER_CL22(bp, phy, |
ea4e040a YR |
1283 | MDIO_REG_BANK_XGXS_BLOCK2, |
1284 | MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0); | |
1285 | } | |
1286 | ||
1287 | if (tx_lane_swap != 0x1b) { | |
e10bc84d | 1288 | CL45_WR_OVER_CL22(bp, phy, |
ea4e040a YR |
1289 | MDIO_REG_BANK_XGXS_BLOCK2, |
1290 | MDIO_XGXS_BLOCK2_TX_LN_SWAP, | |
1291 | (tx_lane_swap | | |
1292 | MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE)); | |
1293 | } else { | |
e10bc84d | 1294 | CL45_WR_OVER_CL22(bp, phy, |
ea4e040a YR |
1295 | MDIO_REG_BANK_XGXS_BLOCK2, |
1296 | MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0); | |
1297 | } | |
1298 | } | |
1299 | ||
e10bc84d YR |
1300 | static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy, |
1301 | struct link_params *params) | |
ea4e040a YR |
1302 | { |
1303 | struct bnx2x *bp = params->bp; | |
1304 | u16 control2; | |
e10bc84d | 1305 | CL45_RD_OVER_CL22(bp, phy, |
ea4e040a YR |
1306 | MDIO_REG_BANK_SERDES_DIGITAL, |
1307 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, | |
1308 | &control2); | |
7aa0711f | 1309 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) |
18afb0a6 YR |
1310 | control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; |
1311 | else | |
1312 | control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; | |
7aa0711f YR |
1313 | DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n", |
1314 | phy->speed_cap_mask, control2); | |
e10bc84d | 1315 | CL45_WR_OVER_CL22(bp, phy, |
ea4e040a YR |
1316 | MDIO_REG_BANK_SERDES_DIGITAL, |
1317 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, | |
1318 | control2); | |
1319 | ||
e10bc84d | 1320 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && |
c18aa15d | 1321 | (phy->speed_cap_mask & |
18afb0a6 | 1322 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { |
ea4e040a YR |
1323 | DP(NETIF_MSG_LINK, "XGXS\n"); |
1324 | ||
e10bc84d | 1325 | CL45_WR_OVER_CL22(bp, phy, |
ea4e040a YR |
1326 | MDIO_REG_BANK_10G_PARALLEL_DETECT, |
1327 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK, | |
1328 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT); | |
1329 | ||
e10bc84d | 1330 | CL45_RD_OVER_CL22(bp, phy, |
ea4e040a YR |
1331 | MDIO_REG_BANK_10G_PARALLEL_DETECT, |
1332 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, | |
1333 | &control2); | |
1334 | ||
1335 | ||
1336 | control2 |= | |
1337 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN; | |
1338 | ||
e10bc84d | 1339 | CL45_WR_OVER_CL22(bp, phy, |
ea4e040a YR |
1340 | MDIO_REG_BANK_10G_PARALLEL_DETECT, |
1341 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, | |
1342 | control2); | |
1343 | ||
1344 | /* Disable parallel detection of HiG */ | |
e10bc84d | 1345 | CL45_WR_OVER_CL22(bp, phy, |
ea4e040a YR |
1346 | MDIO_REG_BANK_XGXS_BLOCK2, |
1347 | MDIO_XGXS_BLOCK2_UNICORE_MODE_10G, | |
1348 | MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS | | |
1349 | MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS); | |
1350 | } | |
1351 | } | |
1352 | ||
e10bc84d YR |
1353 | static void bnx2x_set_autoneg(struct bnx2x_phy *phy, |
1354 | struct link_params *params, | |
239d686d EG |
1355 | struct link_vars *vars, |
1356 | u8 enable_cl73) | |
ea4e040a YR |
1357 | { |
1358 | struct bnx2x *bp = params->bp; | |
1359 | u16 reg_val; | |
1360 | ||
1361 | /* CL37 Autoneg */ | |
e10bc84d | 1362 | CL45_RD_OVER_CL22(bp, phy, |
ea4e040a YR |
1363 | MDIO_REG_BANK_COMBO_IEEE0, |
1364 | MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); | |
1365 | ||
1366 | /* CL37 Autoneg Enabled */ | |
8c99e7b0 | 1367 | if (vars->line_speed == SPEED_AUTO_NEG) |
ea4e040a YR |
1368 | reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN; |
1369 | else /* CL37 Autoneg Disabled */ | |
1370 | reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | | |
1371 | MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN); | |
1372 | ||
e10bc84d | 1373 | CL45_WR_OVER_CL22(bp, phy, |
ea4e040a YR |
1374 | MDIO_REG_BANK_COMBO_IEEE0, |
1375 | MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); | |
1376 | ||
1377 | /* Enable/Disable Autodetection */ | |
1378 | ||
e10bc84d | 1379 | CL45_RD_OVER_CL22(bp, phy, |
ea4e040a YR |
1380 | MDIO_REG_BANK_SERDES_DIGITAL, |
1381 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val); | |
239d686d EG |
1382 | reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN | |
1383 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT); | |
1384 | reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE; | |
8c99e7b0 | 1385 | if (vars->line_speed == SPEED_AUTO_NEG) |
ea4e040a YR |
1386 | reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; |
1387 | else | |
1388 | reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; | |
1389 | ||
e10bc84d | 1390 | CL45_WR_OVER_CL22(bp, phy, |
ea4e040a YR |
1391 | MDIO_REG_BANK_SERDES_DIGITAL, |
1392 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val); | |
1393 | ||
1394 | /* Enable TetonII and BAM autoneg */ | |
e10bc84d | 1395 | CL45_RD_OVER_CL22(bp, phy, |
ea4e040a YR |
1396 | MDIO_REG_BANK_BAM_NEXT_PAGE, |
1397 | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, | |
1398 | ®_val); | |
8c99e7b0 | 1399 | if (vars->line_speed == SPEED_AUTO_NEG) { |
ea4e040a YR |
1400 | /* Enable BAM aneg Mode and TetonII aneg Mode */ |
1401 | reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | | |
1402 | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); | |
1403 | } else { | |
1404 | /* TetonII and BAM Autoneg Disabled */ | |
1405 | reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | | |
1406 | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); | |
1407 | } | |
e10bc84d | 1408 | CL45_WR_OVER_CL22(bp, phy, |
ea4e040a YR |
1409 | MDIO_REG_BANK_BAM_NEXT_PAGE, |
1410 | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, | |
1411 | reg_val); | |
1412 | ||
239d686d EG |
1413 | if (enable_cl73) { |
1414 | /* Enable Cl73 FSM status bits */ | |
e10bc84d | 1415 | CL45_WR_OVER_CL22(bp, phy, |
239d686d EG |
1416 | MDIO_REG_BANK_CL73_USERB0, |
1417 | MDIO_CL73_USERB0_CL73_UCTRL, | |
7846e471 | 1418 | 0xe); |
239d686d EG |
1419 | |
1420 | /* Enable BAM Station Manager*/ | |
e10bc84d | 1421 | CL45_WR_OVER_CL22(bp, phy, |
239d686d EG |
1422 | MDIO_REG_BANK_CL73_USERB0, |
1423 | MDIO_CL73_USERB0_CL73_BAM_CTRL1, | |
1424 | MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN | | |
1425 | MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN | | |
1426 | MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN); | |
1427 | ||
7846e471 | 1428 | /* Advertise CL73 link speeds */ |
e10bc84d | 1429 | CL45_RD_OVER_CL22(bp, phy, |
239d686d EG |
1430 | MDIO_REG_BANK_CL73_IEEEB1, |
1431 | MDIO_CL73_IEEEB1_AN_ADV2, | |
1432 | ®_val); | |
7aa0711f | 1433 | if (phy->speed_cap_mask & |
7846e471 YR |
1434 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) |
1435 | reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4; | |
7aa0711f | 1436 | if (phy->speed_cap_mask & |
7846e471 YR |
1437 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) |
1438 | reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX; | |
239d686d | 1439 | |
e10bc84d | 1440 | CL45_WR_OVER_CL22(bp, phy, |
de6eae1f YR |
1441 | MDIO_REG_BANK_CL73_IEEEB1, |
1442 | MDIO_CL73_IEEEB1_AN_ADV2, | |
1443 | reg_val); | |
239d686d | 1444 | |
239d686d EG |
1445 | /* CL73 Autoneg Enabled */ |
1446 | reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN; | |
1447 | ||
1448 | } else /* CL73 Autoneg Disabled */ | |
1449 | reg_val = 0; | |
ea4e040a | 1450 | |
e10bc84d | 1451 | CL45_WR_OVER_CL22(bp, phy, |
ea4e040a YR |
1452 | MDIO_REG_BANK_CL73_IEEEB0, |
1453 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val); | |
1454 | } | |
1455 | ||
1456 | /* program SerDes, forced speed */ | |
e10bc84d YR |
1457 | static void bnx2x_program_serdes(struct bnx2x_phy *phy, |
1458 | struct link_params *params, | |
8c99e7b0 | 1459 | struct link_vars *vars) |
ea4e040a YR |
1460 | { |
1461 | struct bnx2x *bp = params->bp; | |
1462 | u16 reg_val; | |
1463 | ||
57937203 | 1464 | /* program duplex, disable autoneg and sgmii*/ |
e10bc84d | 1465 | CL45_RD_OVER_CL22(bp, phy, |
ea4e040a YR |
1466 | MDIO_REG_BANK_COMBO_IEEE0, |
1467 | MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); | |
1468 | reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX | | |
57937203 EG |
1469 | MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | |
1470 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK); | |
7aa0711f | 1471 | if (phy->req_duplex == DUPLEX_FULL) |
ea4e040a | 1472 | reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; |
e10bc84d | 1473 | CL45_WR_OVER_CL22(bp, phy, |
ea4e040a YR |
1474 | MDIO_REG_BANK_COMBO_IEEE0, |
1475 | MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); | |
1476 | ||
1477 | /* program speed | |
1478 | - needed only if the speed is greater than 1G (2.5G or 10G) */ | |
e10bc84d | 1479 | CL45_RD_OVER_CL22(bp, phy, |
ea4e040a YR |
1480 | MDIO_REG_BANK_SERDES_DIGITAL, |
1481 | MDIO_SERDES_DIGITAL_MISC1, ®_val); | |
8c99e7b0 YR |
1482 | /* clearing the speed value before setting the right speed */ |
1483 | DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val); | |
1484 | ||
1485 | reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK | | |
1486 | MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); | |
1487 | ||
1488 | if (!((vars->line_speed == SPEED_1000) || | |
1489 | (vars->line_speed == SPEED_100) || | |
1490 | (vars->line_speed == SPEED_10))) { | |
1491 | ||
ea4e040a YR |
1492 | reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M | |
1493 | MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); | |
8c99e7b0 | 1494 | if (vars->line_speed == SPEED_10000) |
ea4e040a YR |
1495 | reg_val |= |
1496 | MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4; | |
8c99e7b0 | 1497 | if (vars->line_speed == SPEED_13000) |
ea4e040a YR |
1498 | reg_val |= |
1499 | MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G; | |
8c99e7b0 YR |
1500 | } |
1501 | ||
e10bc84d | 1502 | CL45_WR_OVER_CL22(bp, phy, |
ea4e040a YR |
1503 | MDIO_REG_BANK_SERDES_DIGITAL, |
1504 | MDIO_SERDES_DIGITAL_MISC1, reg_val); | |
8c99e7b0 | 1505 | |
ea4e040a YR |
1506 | } |
1507 | ||
e10bc84d YR |
1508 | static void bnx2x_set_brcm_cl37_advertisment(struct bnx2x_phy *phy, |
1509 | struct link_params *params) | |
ea4e040a YR |
1510 | { |
1511 | struct bnx2x *bp = params->bp; | |
1512 | u16 val = 0; | |
1513 | ||
1514 | /* configure the 48 bits for BAM AN */ | |
1515 | ||
1516 | /* set extended capabilities */ | |
7aa0711f | 1517 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) |
ea4e040a | 1518 | val |= MDIO_OVER_1G_UP1_2_5G; |
7aa0711f | 1519 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) |
ea4e040a | 1520 | val |= MDIO_OVER_1G_UP1_10G; |
e10bc84d | 1521 | CL45_WR_OVER_CL22(bp, phy, |
ea4e040a YR |
1522 | MDIO_REG_BANK_OVER_1G, |
1523 | MDIO_OVER_1G_UP1, val); | |
1524 | ||
e10bc84d | 1525 | CL45_WR_OVER_CL22(bp, phy, |
ea4e040a | 1526 | MDIO_REG_BANK_OVER_1G, |
239d686d | 1527 | MDIO_OVER_1G_UP3, 0x400); |
ea4e040a YR |
1528 | } |
1529 | ||
e10bc84d YR |
1530 | static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy, |
1531 | struct link_params *params, u16 *ieee_fc) | |
ea4e040a | 1532 | { |
d5cb9e99 | 1533 | struct bnx2x *bp = params->bp; |
8c99e7b0 | 1534 | *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX; |
ea4e040a YR |
1535 | /* resolve pause mode and advertisement |
1536 | * Please refer to Table 28B-3 of the 802.3ab-1999 spec */ | |
1537 | ||
7aa0711f | 1538 | switch (phy->req_flow_ctrl) { |
c0700f90 DM |
1539 | case BNX2X_FLOW_CTRL_AUTO: |
1540 | if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) { | |
8c99e7b0 | 1541 | *ieee_fc |= |
ea4e040a YR |
1542 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; |
1543 | } else { | |
8c99e7b0 | 1544 | *ieee_fc |= |
ea4e040a YR |
1545 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; |
1546 | } | |
1547 | break; | |
c0700f90 | 1548 | case BNX2X_FLOW_CTRL_TX: |
8c99e7b0 | 1549 | *ieee_fc |= |
ea4e040a YR |
1550 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; |
1551 | break; | |
1552 | ||
c0700f90 DM |
1553 | case BNX2X_FLOW_CTRL_RX: |
1554 | case BNX2X_FLOW_CTRL_BOTH: | |
8c99e7b0 | 1555 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; |
ea4e040a YR |
1556 | break; |
1557 | ||
c0700f90 | 1558 | case BNX2X_FLOW_CTRL_NONE: |
ea4e040a | 1559 | default: |
8c99e7b0 | 1560 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; |
ea4e040a YR |
1561 | break; |
1562 | } | |
d5cb9e99 | 1563 | DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc); |
8c99e7b0 | 1564 | } |
ea4e040a | 1565 | |
e10bc84d YR |
1566 | static void bnx2x_set_ieee_aneg_advertisment(struct bnx2x_phy *phy, |
1567 | struct link_params *params, | |
1ef70b9c | 1568 | u16 ieee_fc) |
8c99e7b0 YR |
1569 | { |
1570 | struct bnx2x *bp = params->bp; | |
7846e471 | 1571 | u16 val; |
8c99e7b0 | 1572 | /* for AN, we are always publishing full duplex */ |
ea4e040a | 1573 | |
e10bc84d | 1574 | CL45_WR_OVER_CL22(bp, phy, |
ea4e040a | 1575 | MDIO_REG_BANK_COMBO_IEEE0, |
1ef70b9c | 1576 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc); |
e10bc84d | 1577 | CL45_RD_OVER_CL22(bp, phy, |
7846e471 YR |
1578 | MDIO_REG_BANK_CL73_IEEEB1, |
1579 | MDIO_CL73_IEEEB1_AN_ADV1, &val); | |
1580 | val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH; | |
1581 | val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK); | |
e10bc84d | 1582 | CL45_WR_OVER_CL22(bp, phy, |
7846e471 YR |
1583 | MDIO_REG_BANK_CL73_IEEEB1, |
1584 | MDIO_CL73_IEEEB1_AN_ADV1, val); | |
ea4e040a YR |
1585 | } |
1586 | ||
e10bc84d YR |
1587 | static void bnx2x_restart_autoneg(struct bnx2x_phy *phy, |
1588 | struct link_params *params, | |
1589 | u8 enable_cl73) | |
ea4e040a YR |
1590 | { |
1591 | struct bnx2x *bp = params->bp; | |
3a36f2ef | 1592 | u16 mii_control; |
239d686d | 1593 | |
ea4e040a | 1594 | DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n"); |
3a36f2ef | 1595 | /* Enable and restart BAM/CL37 aneg */ |
ea4e040a | 1596 | |
239d686d | 1597 | if (enable_cl73) { |
e10bc84d | 1598 | CL45_RD_OVER_CL22(bp, phy, |
239d686d EG |
1599 | MDIO_REG_BANK_CL73_IEEEB0, |
1600 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, | |
1601 | &mii_control); | |
1602 | ||
e10bc84d | 1603 | CL45_WR_OVER_CL22(bp, phy, |
239d686d EG |
1604 | MDIO_REG_BANK_CL73_IEEEB0, |
1605 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, | |
1606 | (mii_control | | |
1607 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN | | |
1608 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN)); | |
1609 | } else { | |
1610 | ||
e10bc84d | 1611 | CL45_RD_OVER_CL22(bp, phy, |
239d686d EG |
1612 | MDIO_REG_BANK_COMBO_IEEE0, |
1613 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
1614 | &mii_control); | |
1615 | DP(NETIF_MSG_LINK, | |
1616 | "bnx2x_restart_autoneg mii_control before = 0x%x\n", | |
1617 | mii_control); | |
e10bc84d | 1618 | CL45_WR_OVER_CL22(bp, phy, |
239d686d EG |
1619 | MDIO_REG_BANK_COMBO_IEEE0, |
1620 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
1621 | (mii_control | | |
1622 | MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | | |
1623 | MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN)); | |
1624 | } | |
ea4e040a YR |
1625 | } |
1626 | ||
e10bc84d YR |
1627 | static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy, |
1628 | struct link_params *params, | |
8c99e7b0 | 1629 | struct link_vars *vars) |
ea4e040a YR |
1630 | { |
1631 | struct bnx2x *bp = params->bp; | |
1632 | u16 control1; | |
1633 | ||
1634 | /* in SGMII mode, the unicore is always slave */ | |
1635 | ||
e10bc84d | 1636 | CL45_RD_OVER_CL22(bp, phy, |
ea4e040a YR |
1637 | MDIO_REG_BANK_SERDES_DIGITAL, |
1638 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, | |
1639 | &control1); | |
1640 | control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT; | |
1641 | /* set sgmii mode (and not fiber) */ | |
1642 | control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE | | |
1643 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET | | |
1644 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE); | |
e10bc84d | 1645 | CL45_WR_OVER_CL22(bp, phy, |
ea4e040a YR |
1646 | MDIO_REG_BANK_SERDES_DIGITAL, |
1647 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, | |
1648 | control1); | |
1649 | ||
1650 | /* if forced speed */ | |
8c99e7b0 | 1651 | if (!(vars->line_speed == SPEED_AUTO_NEG)) { |
ea4e040a YR |
1652 | /* set speed, disable autoneg */ |
1653 | u16 mii_control; | |
1654 | ||
e10bc84d | 1655 | CL45_RD_OVER_CL22(bp, phy, |
ea4e040a YR |
1656 | MDIO_REG_BANK_COMBO_IEEE0, |
1657 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
1658 | &mii_control); | |
1659 | mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | | |
1660 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK| | |
1661 | MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX); | |
1662 | ||
8c99e7b0 | 1663 | switch (vars->line_speed) { |
ea4e040a YR |
1664 | case SPEED_100: |
1665 | mii_control |= | |
1666 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100; | |
1667 | break; | |
1668 | case SPEED_1000: | |
1669 | mii_control |= | |
1670 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000; | |
1671 | break; | |
1672 | case SPEED_10: | |
1673 | /* there is nothing to set for 10M */ | |
1674 | break; | |
1675 | default: | |
1676 | /* invalid speed for SGMII */ | |
8c99e7b0 YR |
1677 | DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", |
1678 | vars->line_speed); | |
ea4e040a YR |
1679 | break; |
1680 | } | |
1681 | ||
1682 | /* setting the full duplex */ | |
7aa0711f | 1683 | if (phy->req_duplex == DUPLEX_FULL) |
ea4e040a YR |
1684 | mii_control |= |
1685 | MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; | |
e10bc84d | 1686 | CL45_WR_OVER_CL22(bp, phy, |
ea4e040a YR |
1687 | MDIO_REG_BANK_COMBO_IEEE0, |
1688 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
1689 | mii_control); | |
1690 | ||
1691 | } else { /* AN mode */ | |
1692 | /* enable and restart AN */ | |
e10bc84d | 1693 | bnx2x_restart_autoneg(phy, params, 0); |
ea4e040a YR |
1694 | } |
1695 | } | |
1696 | ||
1697 | ||
1698 | /* | |
1699 | * link management | |
1700 | */ | |
1701 | ||
1702 | static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result) | |
8c99e7b0 YR |
1703 | { /* LD LP */ |
1704 | switch (pause_result) { /* ASYM P ASYM P */ | |
1705 | case 0xb: /* 1 0 1 1 */ | |
c0700f90 | 1706 | vars->flow_ctrl = BNX2X_FLOW_CTRL_TX; |
ea4e040a YR |
1707 | break; |
1708 | ||
8c99e7b0 | 1709 | case 0xe: /* 1 1 1 0 */ |
c0700f90 | 1710 | vars->flow_ctrl = BNX2X_FLOW_CTRL_RX; |
ea4e040a YR |
1711 | break; |
1712 | ||
8c99e7b0 YR |
1713 | case 0x5: /* 0 1 0 1 */ |
1714 | case 0x7: /* 0 1 1 1 */ | |
1715 | case 0xd: /* 1 1 0 1 */ | |
1716 | case 0xf: /* 1 1 1 1 */ | |
c0700f90 | 1717 | vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH; |
ea4e040a YR |
1718 | break; |
1719 | ||
1720 | default: | |
1721 | break; | |
1722 | } | |
7aa0711f YR |
1723 | if (pause_result & (1<<0)) |
1724 | vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE; | |
1725 | if (pause_result & (1<<1)) | |
1726 | vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE; | |
ea4e040a YR |
1727 | } |
1728 | ||
e10bc84d YR |
1729 | static u8 bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy, |
1730 | struct link_params *params) | |
15ddd2d0 YR |
1731 | { |
1732 | struct bnx2x *bp = params->bp; | |
1733 | u16 pd_10g, status2_1000x; | |
7aa0711f YR |
1734 | if (phy->req_line_speed != SPEED_AUTO_NEG) |
1735 | return 0; | |
e10bc84d | 1736 | CL45_RD_OVER_CL22(bp, phy, |
15ddd2d0 YR |
1737 | MDIO_REG_BANK_SERDES_DIGITAL, |
1738 | MDIO_SERDES_DIGITAL_A_1000X_STATUS2, | |
1739 | &status2_1000x); | |
e10bc84d | 1740 | CL45_RD_OVER_CL22(bp, phy, |
15ddd2d0 YR |
1741 | MDIO_REG_BANK_SERDES_DIGITAL, |
1742 | MDIO_SERDES_DIGITAL_A_1000X_STATUS2, | |
1743 | &status2_1000x); | |
1744 | if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) { | |
1745 | DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n", | |
1746 | params->port); | |
1747 | return 1; | |
1748 | } | |
1749 | ||
e10bc84d | 1750 | CL45_RD_OVER_CL22(bp, phy, |
15ddd2d0 YR |
1751 | MDIO_REG_BANK_10G_PARALLEL_DETECT, |
1752 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, | |
1753 | &pd_10g); | |
1754 | ||
1755 | if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) { | |
1756 | DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n", | |
1757 | params->port); | |
1758 | return 1; | |
1759 | } | |
1760 | return 0; | |
1761 | } | |
ea4e040a | 1762 | |
e10bc84d YR |
1763 | static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy, |
1764 | struct link_params *params, | |
1765 | struct link_vars *vars, | |
1766 | u32 gp_status) | |
ea4e040a YR |
1767 | { |
1768 | struct bnx2x *bp = params->bp; | |
3196a88a EG |
1769 | u16 ld_pause; /* local driver */ |
1770 | u16 lp_pause; /* link partner */ | |
ea4e040a YR |
1771 | u16 pause_result; |
1772 | ||
c0700f90 | 1773 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
ea4e040a YR |
1774 | |
1775 | /* resolve from gp_status in case of AN complete and not sgmii */ | |
7aa0711f YR |
1776 | if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) |
1777 | vars->flow_ctrl = phy->req_flow_ctrl; | |
1778 | else if (phy->req_line_speed != SPEED_AUTO_NEG) | |
1779 | vars->flow_ctrl = params->req_fc_auto_adv; | |
1780 | else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) && | |
1781 | (!(vars->phy_flags & PHY_SGMII_FLAG))) { | |
e10bc84d | 1782 | if (bnx2x_direct_parallel_detect_used(phy, params)) { |
15ddd2d0 YR |
1783 | vars->flow_ctrl = params->req_fc_auto_adv; |
1784 | return; | |
1785 | } | |
7846e471 YR |
1786 | if ((gp_status & |
1787 | (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | | |
1788 | MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) == | |
1789 | (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | | |
1790 | MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) { | |
1791 | ||
e10bc84d | 1792 | CL45_RD_OVER_CL22(bp, phy, |
7846e471 YR |
1793 | MDIO_REG_BANK_CL73_IEEEB1, |
1794 | MDIO_CL73_IEEEB1_AN_ADV1, | |
1795 | &ld_pause); | |
e10bc84d | 1796 | CL45_RD_OVER_CL22(bp, phy, |
7846e471 YR |
1797 | MDIO_REG_BANK_CL73_IEEEB1, |
1798 | MDIO_CL73_IEEEB1_AN_LP_ADV1, | |
1799 | &lp_pause); | |
1800 | pause_result = (ld_pause & | |
1801 | MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) | |
1802 | >> 8; | |
1803 | pause_result |= (lp_pause & | |
1804 | MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) | |
1805 | >> 10; | |
1806 | DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", | |
1807 | pause_result); | |
1808 | } else { | |
e10bc84d | 1809 | CL45_RD_OVER_CL22(bp, phy, |
7846e471 YR |
1810 | MDIO_REG_BANK_COMBO_IEEE0, |
1811 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV, | |
1812 | &ld_pause); | |
e10bc84d | 1813 | CL45_RD_OVER_CL22(bp, phy, |
7846e471 YR |
1814 | MDIO_REG_BANK_COMBO_IEEE0, |
1815 | MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1, | |
1816 | &lp_pause); | |
1817 | pause_result = (ld_pause & | |
ea4e040a | 1818 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5; |
7846e471 | 1819 | pause_result |= (lp_pause & |
ea4e040a | 1820 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7; |
7846e471 YR |
1821 | DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", |
1822 | pause_result); | |
1823 | } | |
ea4e040a | 1824 | bnx2x_pause_resolve(vars, pause_result); |
ea4e040a YR |
1825 | } |
1826 | DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl); | |
1827 | } | |
1828 | ||
e10bc84d YR |
1829 | static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy, |
1830 | struct link_params *params) | |
239d686d EG |
1831 | { |
1832 | struct bnx2x *bp = params->bp; | |
1833 | u16 rx_status, ustat_val, cl37_fsm_recieved; | |
1834 | DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n"); | |
1835 | /* Step 1: Make sure signal is detected */ | |
e10bc84d | 1836 | CL45_RD_OVER_CL22(bp, phy, |
239d686d EG |
1837 | MDIO_REG_BANK_RX0, |
1838 | MDIO_RX0_RX_STATUS, | |
1839 | &rx_status); | |
1840 | if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) != | |
1841 | (MDIO_RX0_RX_STATUS_SIGDET)) { | |
1842 | DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73." | |
1843 | "rx_status(0x80b0) = 0x%x\n", rx_status); | |
e10bc84d | 1844 | CL45_WR_OVER_CL22(bp, phy, |
239d686d EG |
1845 | MDIO_REG_BANK_CL73_IEEEB0, |
1846 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, | |
1847 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN); | |
1848 | return; | |
1849 | } | |
1850 | /* Step 2: Check CL73 state machine */ | |
e10bc84d | 1851 | CL45_RD_OVER_CL22(bp, phy, |
239d686d EG |
1852 | MDIO_REG_BANK_CL73_USERB0, |
1853 | MDIO_CL73_USERB0_CL73_USTAT1, | |
1854 | &ustat_val); | |
1855 | if ((ustat_val & | |
1856 | (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | | |
1857 | MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) != | |
1858 | (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | | |
1859 | MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) { | |
1860 | DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. " | |
1861 | "ustat_val(0x8371) = 0x%x\n", ustat_val); | |
1862 | return; | |
1863 | } | |
1864 | /* Step 3: Check CL37 Message Pages received to indicate LP | |
1865 | supports only CL37 */ | |
e10bc84d | 1866 | CL45_RD_OVER_CL22(bp, phy, |
239d686d EG |
1867 | MDIO_REG_BANK_REMOTE_PHY, |
1868 | MDIO_REMOTE_PHY_MISC_RX_STATUS, | |
1869 | &cl37_fsm_recieved); | |
1870 | if ((cl37_fsm_recieved & | |
1871 | (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | | |
1872 | MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) != | |
1873 | (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | | |
1874 | MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) { | |
1875 | DP(NETIF_MSG_LINK, "No CL37 FSM were received. " | |
1876 | "misc_rx_status(0x8330) = 0x%x\n", | |
1877 | cl37_fsm_recieved); | |
1878 | return; | |
1879 | } | |
1880 | /* The combined cl37/cl73 fsm state information indicating that we are | |
1881 | connected to a device which does not support cl73, but does support | |
1882 | cl37 BAM. In this case we disable cl73 and restart cl37 auto-neg */ | |
1883 | /* Disable CL73 */ | |
e10bc84d | 1884 | CL45_WR_OVER_CL22(bp, phy, |
239d686d EG |
1885 | MDIO_REG_BANK_CL73_IEEEB0, |
1886 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, | |
1887 | 0); | |
1888 | /* Restart CL37 autoneg */ | |
e10bc84d | 1889 | bnx2x_restart_autoneg(phy, params, 0); |
239d686d EG |
1890 | DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n"); |
1891 | } | |
7aa0711f YR |
1892 | |
1893 | static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy, | |
1894 | struct link_params *params, | |
1895 | struct link_vars *vars, | |
1896 | u32 gp_status) | |
1897 | { | |
1898 | if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) | |
1899 | vars->link_status |= | |
1900 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; | |
1901 | ||
1902 | if (bnx2x_direct_parallel_detect_used(phy, params)) | |
1903 | vars->link_status |= | |
1904 | LINK_STATUS_PARALLEL_DETECTION_USED; | |
1905 | } | |
1906 | ||
b7737c9b YR |
1907 | static u8 bnx2x_link_settings_status(struct bnx2x_phy *phy, |
1908 | struct link_params *params, | |
1909 | struct link_vars *vars) | |
ea4e040a YR |
1910 | { |
1911 | struct bnx2x *bp = params->bp; | |
b7737c9b | 1912 | u16 new_line_speed , gp_status; |
ea4e040a | 1913 | u8 rc = 0; |
c18aa15d | 1914 | |
b7737c9b YR |
1915 | /* Read gp_status */ |
1916 | CL45_RD_OVER_CL22(bp, phy, | |
1917 | MDIO_REG_BANK_GP_STATUS, | |
1918 | MDIO_GP_STATUS_TOP_AN_STATUS1, | |
1919 | &gp_status); | |
7f02c4ad | 1920 | |
7aa0711f YR |
1921 | if (phy->req_line_speed == SPEED_AUTO_NEG) |
1922 | vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; | |
ea4e040a YR |
1923 | if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) { |
1924 | DP(NETIF_MSG_LINK, "phy link up gp_status=0x%x\n", | |
1925 | gp_status); | |
1926 | ||
1927 | vars->phy_link_up = 1; | |
1928 | vars->link_status |= LINK_STATUS_LINK_UP; | |
1929 | ||
1930 | if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS) | |
1931 | vars->duplex = DUPLEX_FULL; | |
1932 | else | |
1933 | vars->duplex = DUPLEX_HALF; | |
1934 | ||
7aa0711f YR |
1935 | if (SINGLE_MEDIA_DIRECT(params)) { |
1936 | bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status); | |
1937 | if (phy->req_line_speed == SPEED_AUTO_NEG) | |
1938 | bnx2x_xgxs_an_resolve(phy, params, vars, | |
1939 | gp_status); | |
1940 | } | |
ea4e040a YR |
1941 | |
1942 | switch (gp_status & GP_STATUS_SPEED_MASK) { | |
1943 | case GP_STATUS_10M: | |
6c55c3cd | 1944 | new_line_speed = SPEED_10; |
ea4e040a YR |
1945 | if (vars->duplex == DUPLEX_FULL) |
1946 | vars->link_status |= LINK_10TFD; | |
1947 | else | |
1948 | vars->link_status |= LINK_10THD; | |
1949 | break; | |
1950 | ||
1951 | case GP_STATUS_100M: | |
6c55c3cd | 1952 | new_line_speed = SPEED_100; |
ea4e040a YR |
1953 | if (vars->duplex == DUPLEX_FULL) |
1954 | vars->link_status |= LINK_100TXFD; | |
1955 | else | |
1956 | vars->link_status |= LINK_100TXHD; | |
1957 | break; | |
1958 | ||
1959 | case GP_STATUS_1G: | |
1960 | case GP_STATUS_1G_KX: | |
6c55c3cd | 1961 | new_line_speed = SPEED_1000; |
ea4e040a YR |
1962 | if (vars->duplex == DUPLEX_FULL) |
1963 | vars->link_status |= LINK_1000TFD; | |
1964 | else | |
1965 | vars->link_status |= LINK_1000THD; | |
1966 | break; | |
1967 | ||
1968 | case GP_STATUS_2_5G: | |
6c55c3cd | 1969 | new_line_speed = SPEED_2500; |
ea4e040a YR |
1970 | if (vars->duplex == DUPLEX_FULL) |
1971 | vars->link_status |= LINK_2500TFD; | |
1972 | else | |
1973 | vars->link_status |= LINK_2500THD; | |
1974 | break; | |
1975 | ||
1976 | case GP_STATUS_5G: | |
1977 | case GP_STATUS_6G: | |
1978 | DP(NETIF_MSG_LINK, | |
1979 | "link speed unsupported gp_status 0x%x\n", | |
1980 | gp_status); | |
1981 | return -EINVAL; | |
ab6ad5a4 | 1982 | |
ea4e040a YR |
1983 | case GP_STATUS_10G_KX4: |
1984 | case GP_STATUS_10G_HIG: | |
1985 | case GP_STATUS_10G_CX4: | |
6c55c3cd | 1986 | new_line_speed = SPEED_10000; |
ea4e040a YR |
1987 | vars->link_status |= LINK_10GTFD; |
1988 | break; | |
1989 | ||
1990 | case GP_STATUS_12G_HIG: | |
6c55c3cd | 1991 | new_line_speed = SPEED_12000; |
ea4e040a YR |
1992 | vars->link_status |= LINK_12GTFD; |
1993 | break; | |
1994 | ||
1995 | case GP_STATUS_12_5G: | |
6c55c3cd | 1996 | new_line_speed = SPEED_12500; |
ea4e040a YR |
1997 | vars->link_status |= LINK_12_5GTFD; |
1998 | break; | |
1999 | ||
2000 | case GP_STATUS_13G: | |
6c55c3cd | 2001 | new_line_speed = SPEED_13000; |
ea4e040a YR |
2002 | vars->link_status |= LINK_13GTFD; |
2003 | break; | |
2004 | ||
2005 | case GP_STATUS_15G: | |
6c55c3cd | 2006 | new_line_speed = SPEED_15000; |
ea4e040a YR |
2007 | vars->link_status |= LINK_15GTFD; |
2008 | break; | |
2009 | ||
2010 | case GP_STATUS_16G: | |
6c55c3cd | 2011 | new_line_speed = SPEED_16000; |
ea4e040a YR |
2012 | vars->link_status |= LINK_16GTFD; |
2013 | break; | |
2014 | ||
2015 | default: | |
2016 | DP(NETIF_MSG_LINK, | |
2017 | "link speed unsupported gp_status 0x%x\n", | |
2018 | gp_status); | |
ab6ad5a4 | 2019 | return -EINVAL; |
ea4e040a YR |
2020 | } |
2021 | ||
6c55c3cd | 2022 | vars->line_speed = new_line_speed; |
ea4e040a | 2023 | |
ea4e040a YR |
2024 | } else { /* link_down */ |
2025 | DP(NETIF_MSG_LINK, "phy link down\n"); | |
2026 | ||
2027 | vars->phy_link_up = 0; | |
57963ed9 | 2028 | |
ea4e040a | 2029 | vars->duplex = DUPLEX_FULL; |
c0700f90 | 2030 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
ea4e040a | 2031 | vars->mac_type = MAC_TYPE_NONE; |
239d686d | 2032 | |
c18aa15d YR |
2033 | if ((phy->req_line_speed == SPEED_AUTO_NEG) && |
2034 | SINGLE_MEDIA_DIRECT(params)) { | |
239d686d | 2035 | /* Check signal is detected */ |
c18aa15d | 2036 | bnx2x_check_fallback_to_cl37(phy, params); |
239d686d | 2037 | } |
ea4e040a YR |
2038 | } |
2039 | ||
2381a55c | 2040 | DP(NETIF_MSG_LINK, "gp_status 0x%x phy_link_up %x line_speed %x\n", |
ea4e040a | 2041 | gp_status, vars->phy_link_up, vars->line_speed); |
a22f0788 YR |
2042 | DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", |
2043 | vars->duplex, vars->flow_ctrl, vars->link_status); | |
ea4e040a YR |
2044 | return rc; |
2045 | } | |
2046 | ||
ed8680a7 | 2047 | static void bnx2x_set_gmii_tx_driver(struct link_params *params) |
ea4e040a YR |
2048 | { |
2049 | struct bnx2x *bp = params->bp; | |
e10bc84d | 2050 | struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; |
ea4e040a YR |
2051 | u16 lp_up2; |
2052 | u16 tx_driver; | |
c2c8b03e | 2053 | u16 bank; |
ea4e040a YR |
2054 | |
2055 | /* read precomp */ | |
e10bc84d | 2056 | CL45_RD_OVER_CL22(bp, phy, |
ea4e040a YR |
2057 | MDIO_REG_BANK_OVER_1G, |
2058 | MDIO_OVER_1G_LP_UP2, &lp_up2); | |
2059 | ||
ea4e040a YR |
2060 | /* bits [10:7] at lp_up2, positioned at [15:12] */ |
2061 | lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >> | |
2062 | MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) << | |
2063 | MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT); | |
2064 | ||
c2c8b03e EG |
2065 | if (lp_up2 == 0) |
2066 | return; | |
2067 | ||
2068 | for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3; | |
2069 | bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) { | |
e10bc84d | 2070 | CL45_RD_OVER_CL22(bp, phy, |
c2c8b03e EG |
2071 | bank, |
2072 | MDIO_TX0_TX_DRIVER, &tx_driver); | |
2073 | ||
2074 | /* replace tx_driver bits [15:12] */ | |
2075 | if (lp_up2 != | |
2076 | (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) { | |
2077 | tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK; | |
2078 | tx_driver |= lp_up2; | |
e10bc84d | 2079 | CL45_WR_OVER_CL22(bp, phy, |
c2c8b03e EG |
2080 | bank, |
2081 | MDIO_TX0_TX_DRIVER, tx_driver); | |
2082 | } | |
ea4e040a YR |
2083 | } |
2084 | } | |
2085 | ||
2086 | static u8 bnx2x_emac_program(struct link_params *params, | |
b7737c9b | 2087 | struct link_vars *vars) |
ea4e040a YR |
2088 | { |
2089 | struct bnx2x *bp = params->bp; | |
2090 | u8 port = params->port; | |
2091 | u16 mode = 0; | |
2092 | ||
2093 | DP(NETIF_MSG_LINK, "setting link speed & duplex\n"); | |
2094 | bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 + | |
2095 | EMAC_REG_EMAC_MODE, | |
2096 | (EMAC_MODE_25G_MODE | | |
2097 | EMAC_MODE_PORT_MII_10M | | |
2098 | EMAC_MODE_HALF_DUPLEX)); | |
b7737c9b | 2099 | switch (vars->line_speed) { |
ea4e040a YR |
2100 | case SPEED_10: |
2101 | mode |= EMAC_MODE_PORT_MII_10M; | |
2102 | break; | |
2103 | ||
2104 | case SPEED_100: | |
2105 | mode |= EMAC_MODE_PORT_MII; | |
2106 | break; | |
2107 | ||
2108 | case SPEED_1000: | |
2109 | mode |= EMAC_MODE_PORT_GMII; | |
2110 | break; | |
2111 | ||
2112 | case SPEED_2500: | |
2113 | mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII); | |
2114 | break; | |
2115 | ||
2116 | default: | |
2117 | /* 10G not valid for EMAC */ | |
b7737c9b YR |
2118 | DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", |
2119 | vars->line_speed); | |
ea4e040a YR |
2120 | return -EINVAL; |
2121 | } | |
2122 | ||
b7737c9b | 2123 | if (vars->duplex == DUPLEX_HALF) |
ea4e040a YR |
2124 | mode |= EMAC_MODE_HALF_DUPLEX; |
2125 | bnx2x_bits_en(bp, | |
2126 | GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE, | |
2127 | mode); | |
2128 | ||
7f02c4ad | 2129 | bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed); |
ea4e040a YR |
2130 | return 0; |
2131 | } | |
2132 | ||
de6eae1f YR |
2133 | static void bnx2x_set_preemphasis(struct bnx2x_phy *phy, |
2134 | struct link_params *params) | |
b7737c9b | 2135 | { |
de6eae1f YR |
2136 | |
2137 | u16 bank, i = 0; | |
2138 | struct bnx2x *bp = params->bp; | |
2139 | ||
2140 | for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3; | |
2141 | bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) { | |
2142 | CL45_WR_OVER_CL22(bp, phy, | |
2143 | bank, | |
2144 | MDIO_RX0_RX_EQ_BOOST, | |
2145 | phy->rx_preemphasis[i]); | |
2146 | } | |
2147 | ||
2148 | for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3; | |
2149 | bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) { | |
2150 | CL45_WR_OVER_CL22(bp, phy, | |
2151 | bank, | |
2152 | MDIO_TX0_TX_DRIVER, | |
2153 | phy->tx_preemphasis[i]); | |
2154 | } | |
2155 | } | |
2156 | ||
2157 | static void bnx2x_init_internal_phy(struct bnx2x_phy *phy, | |
2158 | struct link_params *params, | |
2159 | struct link_vars *vars) | |
2160 | { | |
2161 | struct bnx2x *bp = params->bp; | |
2162 | u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) || | |
2163 | (params->loopback_mode == LOOPBACK_XGXS)); | |
2164 | if (!(vars->phy_flags & PHY_SGMII_FLAG)) { | |
2165 | if (SINGLE_MEDIA_DIRECT(params) && | |
2166 | (params->feature_config_flags & | |
2167 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) | |
2168 | bnx2x_set_preemphasis(phy, params); | |
2169 | ||
2170 | /* forced speed requested? */ | |
2171 | if (vars->line_speed != SPEED_AUTO_NEG || | |
2172 | (SINGLE_MEDIA_DIRECT(params) && | |
2173 | params->loopback_mode == LOOPBACK_EXT)) { | |
2174 | DP(NETIF_MSG_LINK, "not SGMII, no AN\n"); | |
2175 | ||
2176 | /* disable autoneg */ | |
2177 | bnx2x_set_autoneg(phy, params, vars, 0); | |
2178 | ||
2179 | /* program speed and duplex */ | |
2180 | bnx2x_program_serdes(phy, params, vars); | |
2181 | ||
2182 | } else { /* AN_mode */ | |
2183 | DP(NETIF_MSG_LINK, "not SGMII, AN\n"); | |
2184 | ||
2185 | /* AN enabled */ | |
2186 | bnx2x_set_brcm_cl37_advertisment(phy, params); | |
2187 | ||
2188 | /* program duplex & pause advertisement (for aneg) */ | |
2189 | bnx2x_set_ieee_aneg_advertisment(phy, params, | |
2190 | vars->ieee_fc); | |
2191 | ||
2192 | /* enable autoneg */ | |
2193 | bnx2x_set_autoneg(phy, params, vars, enable_cl73); | |
2194 | ||
2195 | /* enable and restart AN */ | |
2196 | bnx2x_restart_autoneg(phy, params, enable_cl73); | |
2197 | } | |
2198 | ||
2199 | } else { /* SGMII mode */ | |
2200 | DP(NETIF_MSG_LINK, "SGMII\n"); | |
2201 | ||
2202 | bnx2x_initialize_sgmii_process(phy, params, vars); | |
2203 | } | |
2204 | } | |
2205 | ||
2206 | static u8 bnx2x_init_serdes(struct bnx2x_phy *phy, | |
2207 | struct link_params *params, | |
2208 | struct link_vars *vars) | |
2209 | { | |
2210 | u8 rc; | |
2211 | vars->phy_flags |= PHY_SGMII_FLAG; | |
b7737c9b | 2212 | bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); |
f2e0899f | 2213 | bnx2x_set_aer_mmd_serdes(params->bp, phy); |
b7737c9b YR |
2214 | rc = bnx2x_reset_unicore(params, phy, 1); |
2215 | /* reset the SerDes and wait for reset bit return low */ | |
2216 | if (rc != 0) | |
2217 | return rc; | |
f2e0899f | 2218 | bnx2x_set_aer_mmd_serdes(params->bp, phy); |
b7737c9b YR |
2219 | |
2220 | return rc; | |
2221 | } | |
2222 | ||
2223 | static u8 bnx2x_init_xgxs(struct bnx2x_phy *phy, | |
2224 | struct link_params *params, | |
2225 | struct link_vars *vars) | |
2226 | { | |
2227 | u8 rc; | |
2228 | vars->phy_flags = PHY_XGXS_FLAG; | |
2229 | if ((phy->req_line_speed && | |
2230 | ((phy->req_line_speed == SPEED_100) || | |
2231 | (phy->req_line_speed == SPEED_10))) || | |
2232 | (!phy->req_line_speed && | |
2233 | (phy->speed_cap_mask >= | |
2234 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) && | |
2235 | (phy->speed_cap_mask < | |
2236 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) | |
2237 | )) | |
2238 | vars->phy_flags |= PHY_SGMII_FLAG; | |
2239 | else | |
2240 | vars->phy_flags &= ~PHY_SGMII_FLAG; | |
2241 | ||
2242 | bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); | |
f2e0899f | 2243 | bnx2x_set_aer_mmd_xgxs(params, phy); |
b7737c9b YR |
2244 | bnx2x_set_master_ln(params, phy); |
2245 | ||
2246 | rc = bnx2x_reset_unicore(params, phy, 0); | |
2247 | /* reset the SerDes and wait for reset bit return low */ | |
2248 | if (rc != 0) | |
2249 | return rc; | |
2250 | ||
f2e0899f | 2251 | bnx2x_set_aer_mmd_xgxs(params, phy); |
e10bc84d | 2252 | |
b7737c9b YR |
2253 | /* setting the masterLn_def again after the reset */ |
2254 | bnx2x_set_master_ln(params, phy); | |
2255 | bnx2x_set_swap_lanes(params, phy); | |
2256 | ||
2257 | return rc; | |
2258 | } | |
c18aa15d | 2259 | |
de6eae1f YR |
2260 | static u16 bnx2x_wait_reset_complete(struct bnx2x *bp, |
2261 | struct bnx2x_phy *phy) | |
ea4e040a | 2262 | { |
de6eae1f YR |
2263 | u16 cnt, ctrl; |
2264 | /* Wait for soft reset to get cleared upto 1 sec */ | |
2265 | for (cnt = 0; cnt < 1000; cnt++) { | |
2266 | bnx2x_cl45_read(bp, phy, | |
2267 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, &ctrl); | |
2268 | if (!(ctrl & (1<<15))) | |
2269 | break; | |
2270 | msleep(1); | |
2271 | } | |
2272 | DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt); | |
2273 | return cnt; | |
ea4e040a YR |
2274 | } |
2275 | ||
de6eae1f | 2276 | static void bnx2x_link_int_enable(struct link_params *params) |
a35da8db | 2277 | { |
de6eae1f YR |
2278 | u8 port = params->port; |
2279 | u32 mask; | |
2280 | struct bnx2x *bp = params->bp; | |
c18aa15d | 2281 | |
de6eae1f YR |
2282 | /* setting the status to report on link up |
2283 | for either XGXS or SerDes */ | |
2284 | ||
2285 | if (params->switch_cfg == SWITCH_CFG_10G) { | |
2286 | mask = (NIG_MASK_XGXS0_LINK10G | | |
2287 | NIG_MASK_XGXS0_LINK_STATUS); | |
2288 | DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n"); | |
2289 | if (!(SINGLE_MEDIA_DIRECT(params)) && | |
2290 | params->phy[INT_PHY].type != | |
2291 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) { | |
2292 | mask |= NIG_MASK_MI_INT; | |
2293 | DP(NETIF_MSG_LINK, "enabled external phy int\n"); | |
2294 | } | |
2295 | ||
2296 | } else { /* SerDes */ | |
2297 | mask = NIG_MASK_SERDES0_LINK_STATUS; | |
2298 | DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n"); | |
2299 | if (!(SINGLE_MEDIA_DIRECT(params)) && | |
2300 | params->phy[INT_PHY].type != | |
2301 | PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) { | |
2302 | mask |= NIG_MASK_MI_INT; | |
2303 | DP(NETIF_MSG_LINK, "enabled external phy int\n"); | |
2304 | } | |
2305 | } | |
2306 | bnx2x_bits_en(bp, | |
2307 | NIG_REG_MASK_INTERRUPT_PORT0 + port*4, | |
2308 | mask); | |
2309 | ||
2310 | DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port, | |
2311 | (params->switch_cfg == SWITCH_CFG_10G), | |
2312 | REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); | |
2313 | DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n", | |
2314 | REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), | |
2315 | REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18), | |
2316 | REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c)); | |
2317 | DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", | |
2318 | REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), | |
2319 | REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); | |
a35da8db EG |
2320 | } |
2321 | ||
a22f0788 YR |
2322 | static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port, |
2323 | u8 exp_mi_int) | |
a35da8db | 2324 | { |
a22f0788 YR |
2325 | u32 latch_status = 0; |
2326 | ||
2327 | /** | |
2328 | * Disable the MI INT ( external phy int ) by writing 1 to the | |
2329 | * status register. Link down indication is high-active-signal, | |
2330 | * so in this case we need to write the status to clear the XOR | |
de6eae1f YR |
2331 | */ |
2332 | /* Read Latched signals */ | |
2333 | latch_status = REG_RD(bp, | |
a22f0788 YR |
2334 | NIG_REG_LATCH_STATUS_0 + port*8); |
2335 | DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status); | |
de6eae1f | 2336 | /* Handle only those with latched-signal=up.*/ |
a22f0788 YR |
2337 | if (exp_mi_int) |
2338 | bnx2x_bits_en(bp, | |
2339 | NIG_REG_STATUS_INTERRUPT_PORT0 | |
2340 | + port*4, | |
2341 | NIG_STATUS_EMAC0_MI_INT); | |
2342 | else | |
2343 | bnx2x_bits_dis(bp, | |
2344 | NIG_REG_STATUS_INTERRUPT_PORT0 | |
2345 | + port*4, | |
2346 | NIG_STATUS_EMAC0_MI_INT); | |
2347 | ||
de6eae1f | 2348 | if (latch_status & 1) { |
a22f0788 | 2349 | |
de6eae1f YR |
2350 | /* For all latched-signal=up : Re-Arm Latch signals */ |
2351 | REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8, | |
7f02c4ad | 2352 | (latch_status & 0xfffe) | (latch_status & 1)); |
de6eae1f | 2353 | } |
a22f0788 | 2354 | /* For all latched-signal=up,Write original_signal to status */ |
a35da8db EG |
2355 | } |
2356 | ||
de6eae1f | 2357 | static void bnx2x_link_int_ack(struct link_params *params, |
a22f0788 | 2358 | struct link_vars *vars, u8 is_10g) |
b1607af5 | 2359 | { |
e10bc84d | 2360 | struct bnx2x *bp = params->bp; |
de6eae1f | 2361 | u8 port = params->port; |
e10bc84d | 2362 | |
de6eae1f YR |
2363 | /* first reset all status |
2364 | * we assume only one line will be change at a time */ | |
2365 | bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, | |
2366 | (NIG_STATUS_XGXS0_LINK10G | | |
2367 | NIG_STATUS_XGXS0_LINK_STATUS | | |
2368 | NIG_STATUS_SERDES0_LINK_STATUS)); | |
de6eae1f YR |
2369 | if (vars->phy_link_up) { |
2370 | if (is_10g) { | |
2371 | /* Disable the 10G link interrupt | |
2372 | * by writing 1 to the status register | |
2373 | */ | |
2374 | DP(NETIF_MSG_LINK, "10G XGXS phy link up\n"); | |
2375 | bnx2x_bits_en(bp, | |
2376 | NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, | |
2377 | NIG_STATUS_XGXS0_LINK10G); | |
b1607af5 | 2378 | |
de6eae1f YR |
2379 | } else if (params->switch_cfg == SWITCH_CFG_10G) { |
2380 | /* Disable the link interrupt | |
2381 | * by writing 1 to the relevant lane | |
2382 | * in the status register | |
2383 | */ | |
2384 | u32 ser_lane = ((params->lane_config & | |
2385 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> | |
2386 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); | |
b1607af5 | 2387 | |
de6eae1f YR |
2388 | DP(NETIF_MSG_LINK, "%d speed XGXS phy link up\n", |
2389 | vars->line_speed); | |
2390 | bnx2x_bits_en(bp, | |
2391 | NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, | |
2392 | ((1 << ser_lane) << | |
2393 | NIG_STATUS_XGXS0_LINK_STATUS_SIZE)); | |
ea4e040a | 2394 | |
de6eae1f YR |
2395 | } else { /* SerDes */ |
2396 | DP(NETIF_MSG_LINK, "SerDes phy link up\n"); | |
2397 | /* Disable the link interrupt | |
2398 | * by writing 1 to the status register | |
2399 | */ | |
2400 | bnx2x_bits_en(bp, | |
2401 | NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, | |
2402 | NIG_STATUS_SERDES0_LINK_STATUS); | |
2403 | } | |
ea4e040a | 2404 | |
ea4e040a | 2405 | } |
ea4e040a | 2406 | } |
ea4e040a | 2407 | |
de6eae1f YR |
2408 | static u8 bnx2x_format_ver(u32 num, u8 *str, u16 *len) |
2409 | { | |
2410 | u8 *str_ptr = str; | |
2411 | u32 mask = 0xf0000000; | |
2412 | u8 shift = 8*4; | |
2413 | u8 digit; | |
a22f0788 | 2414 | u8 remove_leading_zeros = 1; |
de6eae1f YR |
2415 | if (*len < 10) { |
2416 | /* Need more than 10chars for this format */ | |
2417 | *str_ptr = '\0'; | |
a22f0788 | 2418 | (*len)--; |
de6eae1f | 2419 | return -EINVAL; |
ea4e040a | 2420 | } |
de6eae1f | 2421 | while (shift > 0) { |
ea4e040a | 2422 | |
de6eae1f YR |
2423 | shift -= 4; |
2424 | digit = ((num & mask) >> shift); | |
a22f0788 YR |
2425 | if (digit == 0 && remove_leading_zeros) { |
2426 | mask = mask >> 4; | |
2427 | continue; | |
2428 | } else if (digit < 0xa) | |
de6eae1f YR |
2429 | *str_ptr = digit + '0'; |
2430 | else | |
2431 | *str_ptr = digit - 0xa + 'a'; | |
a22f0788 | 2432 | remove_leading_zeros = 0; |
de6eae1f | 2433 | str_ptr++; |
a22f0788 | 2434 | (*len)--; |
de6eae1f YR |
2435 | mask = mask >> 4; |
2436 | if (shift == 4*4) { | |
a22f0788 | 2437 | *str_ptr = '.'; |
de6eae1f | 2438 | str_ptr++; |
a22f0788 YR |
2439 | (*len)--; |
2440 | remove_leading_zeros = 1; | |
ea4e040a | 2441 | } |
ea4e040a | 2442 | } |
de6eae1f | 2443 | return 0; |
ea4e040a YR |
2444 | } |
2445 | ||
a22f0788 | 2446 | |
de6eae1f | 2447 | static u8 bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len) |
ea4e040a | 2448 | { |
de6eae1f YR |
2449 | str[0] = '\0'; |
2450 | (*len)--; | |
2451 | return 0; | |
2452 | } | |
ea4e040a | 2453 | |
de6eae1f YR |
2454 | u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded, |
2455 | u8 *version, u16 len) | |
2456 | { | |
2457 | struct bnx2x *bp; | |
2458 | u32 spirom_ver = 0; | |
2459 | u8 status = 0; | |
2460 | u8 *ver_p = version; | |
a22f0788 | 2461 | u16 remain_len = len; |
de6eae1f YR |
2462 | if (version == NULL || params == NULL) |
2463 | return -EINVAL; | |
2464 | bp = params->bp; | |
ea4e040a | 2465 | |
de6eae1f YR |
2466 | /* Extract first external phy*/ |
2467 | version[0] = '\0'; | |
2468 | spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr); | |
ea4e040a | 2469 | |
a22f0788 | 2470 | if (params->phy[EXT_PHY1].format_fw_ver) { |
de6eae1f YR |
2471 | status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver, |
2472 | ver_p, | |
a22f0788 YR |
2473 | &remain_len); |
2474 | ver_p += (len - remain_len); | |
2475 | } | |
2476 | if ((params->num_phys == MAX_PHYS) && | |
2477 | (params->phy[EXT_PHY2].ver_addr != 0)) { | |
2478 | spirom_ver = REG_RD(bp, | |
2479 | params->phy[EXT_PHY2].ver_addr); | |
2480 | if (params->phy[EXT_PHY2].format_fw_ver) { | |
2481 | *ver_p = '/'; | |
2482 | ver_p++; | |
2483 | remain_len--; | |
2484 | status |= params->phy[EXT_PHY2].format_fw_ver( | |
2485 | spirom_ver, | |
2486 | ver_p, | |
2487 | &remain_len); | |
2488 | ver_p = version + (len - remain_len); | |
2489 | } | |
2490 | } | |
2491 | *ver_p = '\0'; | |
de6eae1f | 2492 | return status; |
6bbca910 | 2493 | } |
ea4e040a | 2494 | |
de6eae1f YR |
2495 | static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy, |
2496 | struct link_params *params) | |
589abe3a | 2497 | { |
de6eae1f | 2498 | u8 port = params->port; |
589abe3a | 2499 | struct bnx2x *bp = params->bp; |
589abe3a | 2500 | |
de6eae1f YR |
2501 | if (phy->req_line_speed != SPEED_1000) { |
2502 | u32 md_devad; | |
589abe3a | 2503 | |
de6eae1f | 2504 | DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n"); |
589abe3a | 2505 | |
de6eae1f YR |
2506 | /* change the uni_phy_addr in the nig */ |
2507 | md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD + | |
2508 | port*0x18)); | |
cc1cb004 | 2509 | |
de6eae1f | 2510 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 0x5); |
589abe3a | 2511 | |
de6eae1f YR |
2512 | bnx2x_cl45_write(bp, phy, |
2513 | 5, | |
2514 | (MDIO_REG_BANK_AER_BLOCK + | |
2515 | (MDIO_AER_BLOCK_AER_REG & 0xf)), | |
2516 | 0x2800); | |
589abe3a | 2517 | |
de6eae1f YR |
2518 | bnx2x_cl45_write(bp, phy, |
2519 | 5, | |
2520 | (MDIO_REG_BANK_CL73_IEEEB0 + | |
2521 | (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)), | |
2522 | 0x6041); | |
2523 | msleep(200); | |
2524 | /* set aer mmd back */ | |
f2e0899f | 2525 | bnx2x_set_aer_mmd_xgxs(params, phy); |
589abe3a | 2526 | |
de6eae1f YR |
2527 | /* and md_devad */ |
2528 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, | |
2529 | md_devad); | |
2530 | ||
2531 | } else { | |
2532 | u16 mii_ctrl; | |
2533 | DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n"); | |
2534 | bnx2x_cl45_read(bp, phy, 5, | |
2535 | (MDIO_REG_BANK_COMBO_IEEE0 + | |
2536 | (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), | |
2537 | &mii_ctrl); | |
2538 | bnx2x_cl45_write(bp, phy, 5, | |
2539 | (MDIO_REG_BANK_COMBO_IEEE0 + | |
2540 | (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), | |
2541 | mii_ctrl | | |
2542 | MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK); | |
2543 | } | |
589abe3a EG |
2544 | } |
2545 | ||
7f02c4ad YR |
2546 | u8 bnx2x_set_led(struct link_params *params, |
2547 | struct link_vars *vars, u8 mode, u32 speed) | |
4d295db0 | 2548 | { |
de6eae1f YR |
2549 | u8 port = params->port; |
2550 | u16 hw_led_mode = params->hw_led_mode; | |
7f02c4ad | 2551 | u8 rc = 0, phy_idx; |
de6eae1f YR |
2552 | u32 tmp; |
2553 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
589abe3a | 2554 | struct bnx2x *bp = params->bp; |
de6eae1f YR |
2555 | DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode); |
2556 | DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n", | |
2557 | speed, hw_led_mode); | |
7f02c4ad YR |
2558 | /* In case */ |
2559 | for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) { | |
2560 | if (params->phy[phy_idx].set_link_led) { | |
2561 | params->phy[phy_idx].set_link_led( | |
2562 | ¶ms->phy[phy_idx], params, mode); | |
2563 | } | |
2564 | } | |
2565 | ||
de6eae1f | 2566 | switch (mode) { |
7f02c4ad | 2567 | case LED_MODE_FRONT_PANEL_OFF: |
de6eae1f YR |
2568 | case LED_MODE_OFF: |
2569 | REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0); | |
2570 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, | |
2571 | SHARED_HW_CFG_LED_MAC1); | |
589abe3a | 2572 | |
de6eae1f YR |
2573 | tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); |
2574 | EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE)); | |
2575 | break; | |
589abe3a | 2576 | |
de6eae1f | 2577 | case LED_MODE_OPER: |
7f02c4ad YR |
2578 | /** |
2579 | * For all other phys, OPER mode is same as ON, so in case | |
2580 | * link is down, do nothing | |
2581 | **/ | |
2582 | if (!vars->link_up) | |
2583 | break; | |
2584 | case LED_MODE_ON: | |
de6eae1f | 2585 | if (SINGLE_MEDIA_DIRECT(params)) { |
7f02c4ad YR |
2586 | /** |
2587 | * This is a work-around for HW issue found when link | |
2588 | * is up in CL73 | |
2589 | */ | |
de6eae1f YR |
2590 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); |
2591 | REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); | |
2592 | } else { | |
2593 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, | |
2594 | hw_led_mode); | |
2595 | } | |
589abe3a | 2596 | |
de6eae1f YR |
2597 | REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + |
2598 | port*4, 0); | |
2599 | /* Set blinking rate to ~15.9Hz */ | |
2600 | REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, | |
2601 | LED_BLINK_RATE_VAL); | |
2602 | REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + | |
2603 | port*4, 1); | |
2604 | tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); | |
2605 | EMAC_WR(bp, EMAC_REG_EMAC_LED, | |
2606 | (tmp & (~EMAC_LED_OVERRIDE))); | |
589abe3a | 2607 | |
de6eae1f YR |
2608 | if (CHIP_IS_E1(bp) && |
2609 | ((speed == SPEED_2500) || | |
2610 | (speed == SPEED_1000) || | |
2611 | (speed == SPEED_100) || | |
2612 | (speed == SPEED_10))) { | |
2613 | /* On Everest 1 Ax chip versions for speeds less than | |
2614 | 10G LED scheme is different */ | |
2615 | REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 | |
2616 | + port*4, 1); | |
2617 | REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + | |
2618 | port*4, 0); | |
2619 | REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + | |
2620 | port*4, 1); | |
2621 | } | |
2622 | break; | |
589abe3a | 2623 | |
de6eae1f YR |
2624 | default: |
2625 | rc = -EINVAL; | |
2626 | DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n", | |
2627 | mode); | |
2628 | break; | |
589abe3a | 2629 | } |
de6eae1f | 2630 | return rc; |
589abe3a | 2631 | |
4d295db0 EG |
2632 | } |
2633 | ||
a22f0788 YR |
2634 | /** |
2635 | * This function comes to reflect the actual link state read DIRECTLY from the | |
2636 | * HW | |
2637 | */ | |
2638 | u8 bnx2x_test_link(struct link_params *params, struct link_vars *vars, | |
2639 | u8 is_serdes) | |
4d295db0 EG |
2640 | { |
2641 | struct bnx2x *bp = params->bp; | |
de6eae1f | 2642 | u16 gp_status = 0, phy_index = 0; |
a22f0788 YR |
2643 | u8 ext_phy_link_up = 0, serdes_phy_type; |
2644 | struct link_vars temp_vars; | |
4d295db0 | 2645 | |
de6eae1f YR |
2646 | CL45_RD_OVER_CL22(bp, ¶ms->phy[INT_PHY], |
2647 | MDIO_REG_BANK_GP_STATUS, | |
2648 | MDIO_GP_STATUS_TOP_AN_STATUS1, | |
2649 | &gp_status); | |
2650 | /* link is up only if both local phy and external phy are up */ | |
a22f0788 YR |
2651 | if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)) |
2652 | return -ESRCH; | |
2653 | ||
2654 | switch (params->num_phys) { | |
2655 | case 1: | |
2656 | /* No external PHY */ | |
2657 | return 0; | |
2658 | case 2: | |
2659 | ext_phy_link_up = params->phy[EXT_PHY1].read_status( | |
2660 | ¶ms->phy[EXT_PHY1], | |
2661 | params, &temp_vars); | |
2662 | break; | |
2663 | case 3: /* Dual Media */ | |
de6eae1f YR |
2664 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; |
2665 | phy_index++) { | |
a22f0788 YR |
2666 | serdes_phy_type = ((params->phy[phy_index].media_type == |
2667 | ETH_PHY_SFP_FIBER) || | |
2668 | (params->phy[phy_index].media_type == | |
2669 | ETH_PHY_XFP_FIBER)); | |
2670 | ||
2671 | if (is_serdes != serdes_phy_type) | |
2672 | continue; | |
2673 | if (params->phy[phy_index].read_status) { | |
2674 | ext_phy_link_up |= | |
de6eae1f YR |
2675 | params->phy[phy_index].read_status( |
2676 | ¶ms->phy[phy_index], | |
2677 | params, &temp_vars); | |
a22f0788 | 2678 | } |
de6eae1f | 2679 | } |
a22f0788 | 2680 | break; |
4d295db0 | 2681 | } |
a22f0788 YR |
2682 | if (ext_phy_link_up) |
2683 | return 0; | |
de6eae1f YR |
2684 | return -ESRCH; |
2685 | } | |
4d295db0 | 2686 | |
de6eae1f YR |
2687 | static u8 bnx2x_link_initialize(struct link_params *params, |
2688 | struct link_vars *vars) | |
2689 | { | |
2690 | u8 rc = 0; | |
2691 | u8 phy_index, non_ext_phy; | |
2692 | struct bnx2x *bp = params->bp; | |
2693 | /** | |
2694 | * In case of external phy existence, the line speed would be the | |
2695 | * line speed linked up by the external phy. In case it is direct | |
2696 | * only, then the line_speed during initialization will be | |
2697 | * equal to the req_line_speed | |
2698 | */ | |
2699 | vars->line_speed = params->phy[INT_PHY].req_line_speed; | |
4d295db0 | 2700 | |
de6eae1f YR |
2701 | /** |
2702 | * Initialize the internal phy in case this is a direct board | |
2703 | * (no external phys), or this board has external phy which requires | |
2704 | * to first. | |
2705 | */ | |
4d295db0 | 2706 | |
de6eae1f YR |
2707 | if (params->phy[INT_PHY].config_init) |
2708 | params->phy[INT_PHY].config_init( | |
2709 | ¶ms->phy[INT_PHY], | |
2710 | params, vars); | |
4d295db0 | 2711 | |
de6eae1f YR |
2712 | /* init ext phy and enable link state int */ |
2713 | non_ext_phy = (SINGLE_MEDIA_DIRECT(params) || | |
2714 | (params->loopback_mode == LOOPBACK_XGXS)); | |
4d295db0 | 2715 | |
de6eae1f YR |
2716 | if (non_ext_phy || |
2717 | (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) || | |
2718 | (params->loopback_mode == LOOPBACK_EXT_PHY)) { | |
2719 | struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; | |
2720 | if (vars->line_speed == SPEED_AUTO_NEG) | |
2721 | bnx2x_set_parallel_detection(phy, params); | |
2722 | bnx2x_init_internal_phy(phy, params, vars); | |
4d295db0 EG |
2723 | } |
2724 | ||
de6eae1f YR |
2725 | /* Init external phy*/ |
2726 | if (!non_ext_phy) | |
2727 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; | |
2728 | phy_index++) { | |
a22f0788 YR |
2729 | /** |
2730 | * No need to initialize second phy in case of first | |
2731 | * phy only selection. In case of second phy, we do | |
2732 | * need to initialize the first phy, since they are | |
2733 | * connected. | |
2734 | **/ | |
2735 | if (phy_index == EXT_PHY2 && | |
2736 | (bnx2x_phy_selection(params) == | |
2737 | PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) { | |
2738 | DP(NETIF_MSG_LINK, "Not initializing" | |
2739 | "second phy\n"); | |
2740 | continue; | |
2741 | } | |
de6eae1f YR |
2742 | params->phy[phy_index].config_init( |
2743 | ¶ms->phy[phy_index], | |
2744 | params, vars); | |
2745 | } | |
4d295db0 | 2746 | |
de6eae1f YR |
2747 | /* Reset the interrupt indication after phy was initialized */ |
2748 | bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + | |
2749 | params->port*4, | |
2750 | (NIG_STATUS_XGXS0_LINK10G | | |
2751 | NIG_STATUS_XGXS0_LINK_STATUS | | |
2752 | NIG_STATUS_SERDES0_LINK_STATUS | | |
2753 | NIG_MASK_MI_INT)); | |
2754 | return rc; | |
2755 | } | |
4d295db0 | 2756 | |
de6eae1f YR |
2757 | static void bnx2x_int_link_reset(struct bnx2x_phy *phy, |
2758 | struct link_params *params) | |
2759 | { | |
2760 | /* reset the SerDes/XGXS */ | |
2761 | REG_WR(params->bp, GRCBASE_MISC + | |
2762 | MISC_REGISTERS_RESET_REG_3_CLEAR, | |
2763 | (0x1ff << (params->port*16))); | |
589abe3a EG |
2764 | } |
2765 | ||
de6eae1f YR |
2766 | static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy, |
2767 | struct link_params *params) | |
4d295db0 | 2768 | { |
de6eae1f YR |
2769 | struct bnx2x *bp = params->bp; |
2770 | u8 gpio_port; | |
2771 | /* HW reset */ | |
f2e0899f DK |
2772 | if (CHIP_IS_E2(bp)) |
2773 | gpio_port = BP_PATH(bp); | |
2774 | else | |
2775 | gpio_port = params->port; | |
de6eae1f YR |
2776 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, |
2777 | MISC_REGISTERS_GPIO_OUTPUT_LOW, | |
2778 | gpio_port); | |
2779 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
2780 | MISC_REGISTERS_GPIO_OUTPUT_LOW, | |
2781 | gpio_port); | |
2782 | DP(NETIF_MSG_LINK, "reset external PHY\n"); | |
4d295db0 | 2783 | } |
589abe3a | 2784 | |
de6eae1f YR |
2785 | static u8 bnx2x_update_link_down(struct link_params *params, |
2786 | struct link_vars *vars) | |
589abe3a EG |
2787 | { |
2788 | struct bnx2x *bp = params->bp; | |
de6eae1f | 2789 | u8 port = params->port; |
589abe3a | 2790 | |
de6eae1f | 2791 | DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port); |
7f02c4ad | 2792 | bnx2x_set_led(params, vars, LED_MODE_OFF, 0); |
589abe3a | 2793 | |
de6eae1f YR |
2794 | /* indicate no mac active */ |
2795 | vars->mac_type = MAC_TYPE_NONE; | |
ab6ad5a4 | 2796 | |
de6eae1f YR |
2797 | /* update shared memory */ |
2798 | vars->link_status = 0; | |
2799 | vars->line_speed = 0; | |
2800 | bnx2x_update_mng(params, vars->link_status); | |
589abe3a | 2801 | |
de6eae1f YR |
2802 | /* activate nig drain */ |
2803 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); | |
4d295db0 | 2804 | |
de6eae1f YR |
2805 | /* disable emac */ |
2806 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); | |
2807 | ||
2808 | msleep(10); | |
2809 | ||
2810 | /* reset BigMac */ | |
2811 | bnx2x_bmac_rx_disable(bp, params->port); | |
2812 | REG_WR(bp, GRCBASE_MISC + | |
2813 | MISC_REGISTERS_RESET_REG_2_CLEAR, | |
2814 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); | |
589abe3a EG |
2815 | return 0; |
2816 | } | |
de6eae1f YR |
2817 | |
2818 | static u8 bnx2x_update_link_up(struct link_params *params, | |
2819 | struct link_vars *vars, | |
2820 | u8 link_10g) | |
589abe3a EG |
2821 | { |
2822 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
2823 | u8 port = params->port; |
2824 | u8 rc = 0; | |
4d295db0 | 2825 | |
de6eae1f | 2826 | vars->link_status |= LINK_STATUS_LINK_UP; |
7f02c4ad | 2827 | |
de6eae1f YR |
2828 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) |
2829 | vars->link_status |= | |
2830 | LINK_STATUS_TX_FLOW_CONTROL_ENABLED; | |
589abe3a | 2831 | |
de6eae1f YR |
2832 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) |
2833 | vars->link_status |= | |
2834 | LINK_STATUS_RX_FLOW_CONTROL_ENABLED; | |
7f02c4ad | 2835 | |
de6eae1f YR |
2836 | if (link_10g) { |
2837 | bnx2x_bmac_enable(params, vars, 0); | |
7f02c4ad YR |
2838 | bnx2x_set_led(params, vars, |
2839 | LED_MODE_OPER, SPEED_10000); | |
de6eae1f YR |
2840 | } else { |
2841 | rc = bnx2x_emac_program(params, vars); | |
cc1cb004 | 2842 | |
de6eae1f | 2843 | bnx2x_emac_enable(params, vars, 0); |
cc1cb004 | 2844 | |
de6eae1f YR |
2845 | /* AN complete? */ |
2846 | if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) | |
2847 | && (!(vars->phy_flags & PHY_SGMII_FLAG)) && | |
2848 | SINGLE_MEDIA_DIRECT(params)) | |
2849 | bnx2x_set_gmii_tx_driver(params); | |
2850 | } | |
cc1cb004 | 2851 | |
de6eae1f | 2852 | /* PBF - link up */ |
f2e0899f DK |
2853 | if (!(CHIP_IS_E2(bp))) |
2854 | rc |= bnx2x_pbf_update(params, vars->flow_ctrl, | |
2855 | vars->line_speed); | |
589abe3a | 2856 | |
de6eae1f YR |
2857 | /* disable drain */ |
2858 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0); | |
589abe3a | 2859 | |
de6eae1f YR |
2860 | /* update shared memory */ |
2861 | bnx2x_update_mng(params, vars->link_status); | |
2862 | msleep(20); | |
2863 | return rc; | |
589abe3a | 2864 | } |
de6eae1f YR |
2865 | /** |
2866 | * The bnx2x_link_update function should be called upon link | |
2867 | * interrupt. | |
2868 | * Link is considered up as follows: | |
2869 | * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs | |
2870 | * to be up | |
2871 | * - SINGLE_MEDIA - The link between the 577xx and the external | |
2872 | * phy (XGXS) need to up as well as the external link of the | |
2873 | * phy (PHY_EXT1) | |
2874 | * - DUAL_MEDIA - The link between the 577xx and the first | |
2875 | * external phy needs to be up, and at least one of the 2 | |
2876 | * external phy link must be up. | |
2877 | */ | |
2878 | u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars) | |
4d295db0 | 2879 | { |
de6eae1f YR |
2880 | struct bnx2x *bp = params->bp; |
2881 | struct link_vars phy_vars[MAX_PHYS]; | |
2882 | u8 port = params->port; | |
2883 | u8 link_10g, phy_index; | |
2884 | u8 ext_phy_link_up = 0, cur_link_up, rc = 0; | |
2885 | u8 is_mi_int = 0; | |
2886 | u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed; | |
2887 | u8 active_external_phy = INT_PHY; | |
2888 | vars->link_status = 0; | |
2889 | for (phy_index = INT_PHY; phy_index < params->num_phys; | |
2890 | phy_index++) { | |
2891 | phy_vars[phy_index].flow_ctrl = 0; | |
2892 | phy_vars[phy_index].link_status = 0; | |
2893 | phy_vars[phy_index].line_speed = 0; | |
2894 | phy_vars[phy_index].duplex = DUPLEX_FULL; | |
2895 | phy_vars[phy_index].phy_link_up = 0; | |
2896 | phy_vars[phy_index].link_up = 0; | |
2897 | } | |
4d295db0 | 2898 | |
de6eae1f YR |
2899 | DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n", |
2900 | port, (vars->phy_flags & PHY_XGXS_FLAG), | |
2901 | REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); | |
4d295db0 | 2902 | |
de6eae1f YR |
2903 | is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + |
2904 | port*0x18) > 0); | |
2905 | DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n", | |
2906 | REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), | |
2907 | is_mi_int, | |
2908 | REG_RD(bp, | |
2909 | NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c)); | |
4d295db0 | 2910 | |
de6eae1f YR |
2911 | DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", |
2912 | REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), | |
2913 | REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); | |
4d295db0 | 2914 | |
de6eae1f YR |
2915 | /* disable emac */ |
2916 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); | |
4d295db0 | 2917 | |
de6eae1f YR |
2918 | /** |
2919 | * Step 1: | |
2920 | * Check external link change only for external phys, and apply | |
2921 | * priority selection between them in case the link on both phys | |
2922 | * is up. Note that the instead of the common vars, a temporary | |
2923 | * vars argument is used since each phy may have different link/ | |
2924 | * speed/duplex result | |
2925 | */ | |
2926 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; | |
2927 | phy_index++) { | |
2928 | struct bnx2x_phy *phy = ¶ms->phy[phy_index]; | |
2929 | if (!phy->read_status) | |
2930 | continue; | |
2931 | /* Read link status and params of this ext phy */ | |
2932 | cur_link_up = phy->read_status(phy, params, | |
2933 | &phy_vars[phy_index]); | |
2934 | if (cur_link_up) { | |
2935 | DP(NETIF_MSG_LINK, "phy in index %d link is up\n", | |
2936 | phy_index); | |
2937 | } else { | |
2938 | DP(NETIF_MSG_LINK, "phy in index %d link is down\n", | |
2939 | phy_index); | |
2940 | continue; | |
2941 | } | |
e10bc84d | 2942 | |
de6eae1f YR |
2943 | if (!ext_phy_link_up) { |
2944 | ext_phy_link_up = 1; | |
2945 | active_external_phy = phy_index; | |
a22f0788 YR |
2946 | } else { |
2947 | switch (bnx2x_phy_selection(params)) { | |
2948 | case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: | |
2949 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: | |
2950 | /** | |
2951 | * In this option, the first PHY makes sure to pass the | |
2952 | * traffic through itself only. | |
2953 | * Its not clear how to reset the link on the second phy | |
2954 | **/ | |
2955 | active_external_phy = EXT_PHY1; | |
2956 | break; | |
2957 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: | |
2958 | /** | |
2959 | * In this option, the first PHY makes sure to pass the | |
2960 | * traffic through the second PHY. | |
2961 | **/ | |
2962 | active_external_phy = EXT_PHY2; | |
2963 | break; | |
2964 | default: | |
2965 | /** | |
2966 | * Link indication on both PHYs with the following cases | |
2967 | * is invalid: | |
2968 | * - FIRST_PHY means that second phy wasn't initialized, | |
2969 | * hence its link is expected to be down | |
2970 | * - SECOND_PHY means that first phy should not be able | |
2971 | * to link up by itself (using configuration) | |
2972 | * - DEFAULT should be overriden during initialiazation | |
2973 | **/ | |
2974 | DP(NETIF_MSG_LINK, "Invalid link indication" | |
2975 | "mpc=0x%x. DISABLING LINK !!!\n", | |
2976 | params->multi_phy_config); | |
2977 | ext_phy_link_up = 0; | |
2978 | break; | |
2979 | } | |
589abe3a | 2980 | } |
589abe3a | 2981 | } |
de6eae1f YR |
2982 | prev_line_speed = vars->line_speed; |
2983 | /** | |
2984 | * Step 2: | |
2985 | * Read the status of the internal phy. In case of | |
2986 | * DIRECT_SINGLE_MEDIA board, this link is the external link, | |
2987 | * otherwise this is the link between the 577xx and the first | |
2988 | * external phy | |
4d295db0 | 2989 | */ |
de6eae1f YR |
2990 | if (params->phy[INT_PHY].read_status) |
2991 | params->phy[INT_PHY].read_status( | |
2992 | ¶ms->phy[INT_PHY], | |
2993 | params, vars); | |
2994 | /** | |
2995 | * The INT_PHY flow control reside in the vars. This include the | |
2996 | * case where the speed or flow control are not set to AUTO. | |
2997 | * Otherwise, the active external phy flow control result is set | |
2998 | * to the vars. The ext_phy_line_speed is needed to check if the | |
2999 | * speed is different between the internal phy and external phy. | |
3000 | * This case may be result of intermediate link speed change. | |
4d295db0 | 3001 | */ |
de6eae1f YR |
3002 | if (active_external_phy > INT_PHY) { |
3003 | vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl; | |
3004 | /** | |
3005 | * Link speed is taken from the XGXS. AN and FC result from | |
3006 | * the external phy. | |
4d295db0 | 3007 | */ |
de6eae1f | 3008 | vars->link_status |= phy_vars[active_external_phy].link_status; |
a22f0788 YR |
3009 | |
3010 | /** | |
3011 | * if active_external_phy is first PHY and link is up - disable | |
3012 | * disable TX on second external PHY | |
3013 | */ | |
3014 | if (active_external_phy == EXT_PHY1) { | |
3015 | if (params->phy[EXT_PHY2].phy_specific_func) { | |
3016 | DP(NETIF_MSG_LINK, "Disabling TX on" | |
3017 | " EXT_PHY2\n"); | |
3018 | params->phy[EXT_PHY2].phy_specific_func( | |
3019 | ¶ms->phy[EXT_PHY2], | |
3020 | params, DISABLE_TX); | |
3021 | } | |
3022 | } | |
3023 | ||
de6eae1f YR |
3024 | ext_phy_line_speed = phy_vars[active_external_phy].line_speed; |
3025 | vars->duplex = phy_vars[active_external_phy].duplex; | |
3026 | if (params->phy[active_external_phy].supported & | |
3027 | SUPPORTED_FIBRE) | |
3028 | vars->link_status |= LINK_STATUS_SERDES_LINK; | |
3029 | DP(NETIF_MSG_LINK, "Active external phy selected: %x\n", | |
3030 | active_external_phy); | |
3031 | } | |
a22f0788 YR |
3032 | |
3033 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; | |
3034 | phy_index++) { | |
3035 | if (params->phy[phy_index].flags & | |
3036 | FLAGS_REARM_LATCH_SIGNAL) { | |
3037 | bnx2x_rearm_latch_signal(bp, port, | |
3038 | phy_index == | |
3039 | active_external_phy); | |
3040 | break; | |
3041 | } | |
3042 | } | |
de6eae1f YR |
3043 | DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x," |
3044 | " ext_phy_line_speed = %d\n", vars->flow_ctrl, | |
3045 | vars->link_status, ext_phy_line_speed); | |
3046 | /** | |
3047 | * Upon link speed change set the NIG into drain mode. Comes to | |
3048 | * deals with possible FIFO glitch due to clk change when speed | |
3049 | * is decreased without link down indicator | |
3050 | */ | |
4d295db0 | 3051 | |
de6eae1f YR |
3052 | if (vars->phy_link_up) { |
3053 | if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up && | |
3054 | (ext_phy_line_speed != vars->line_speed)) { | |
3055 | DP(NETIF_MSG_LINK, "Internal link speed %d is" | |
3056 | " different than the external" | |
3057 | " link speed %d\n", vars->line_speed, | |
3058 | ext_phy_line_speed); | |
3059 | vars->phy_link_up = 0; | |
3060 | } else if (prev_line_speed != vars->line_speed) { | |
3061 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE | |
3062 | + params->port*4, 0); | |
3063 | msleep(1); | |
3064 | } | |
3065 | } | |
e10bc84d | 3066 | |
de6eae1f YR |
3067 | /* anything 10 and over uses the bmac */ |
3068 | link_10g = ((vars->line_speed == SPEED_10000) || | |
3069 | (vars->line_speed == SPEED_12000) || | |
3070 | (vars->line_speed == SPEED_12500) || | |
3071 | (vars->line_speed == SPEED_13000) || | |
3072 | (vars->line_speed == SPEED_15000) || | |
3073 | (vars->line_speed == SPEED_16000)); | |
589abe3a | 3074 | |
a22f0788 | 3075 | bnx2x_link_int_ack(params, vars, link_10g); |
589abe3a | 3076 | |
de6eae1f YR |
3077 | /** |
3078 | * In case external phy link is up, and internal link is down | |
3079 | * (not initialized yet probably after link initialization, it | |
3080 | * needs to be initialized. | |
3081 | * Note that after link down-up as result of cable plug, the xgxs | |
3082 | * link would probably become up again without the need | |
3083 | * initialize it | |
3084 | */ | |
3085 | if (!(SINGLE_MEDIA_DIRECT(params))) { | |
3086 | DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d," | |
3087 | " init_preceding = %d\n", ext_phy_link_up, | |
3088 | vars->phy_link_up, | |
3089 | params->phy[EXT_PHY1].flags & | |
3090 | FLAGS_INIT_XGXS_FIRST); | |
3091 | if (!(params->phy[EXT_PHY1].flags & | |
3092 | FLAGS_INIT_XGXS_FIRST) | |
3093 | && ext_phy_link_up && !vars->phy_link_up) { | |
3094 | vars->line_speed = ext_phy_line_speed; | |
3095 | if (vars->line_speed < SPEED_1000) | |
3096 | vars->phy_flags |= PHY_SGMII_FLAG; | |
3097 | else | |
3098 | vars->phy_flags &= ~PHY_SGMII_FLAG; | |
3099 | bnx2x_init_internal_phy(¶ms->phy[INT_PHY], | |
3100 | params, | |
3101 | vars); | |
4d295db0 | 3102 | } |
589abe3a | 3103 | } |
de6eae1f YR |
3104 | /** |
3105 | * Link is up only if both local phy and external phy (in case of | |
3106 | * non-direct board) are up | |
4d295db0 | 3107 | */ |
de6eae1f YR |
3108 | vars->link_up = (vars->phy_link_up && |
3109 | (ext_phy_link_up || | |
3110 | SINGLE_MEDIA_DIRECT(params))); | |
3111 | ||
3112 | if (vars->link_up) | |
3113 | rc = bnx2x_update_link_up(params, vars, link_10g); | |
4d295db0 | 3114 | else |
de6eae1f | 3115 | rc = bnx2x_update_link_down(params, vars); |
589abe3a | 3116 | |
4d295db0 | 3117 | return rc; |
589abe3a EG |
3118 | } |
3119 | ||
589abe3a | 3120 | |
de6eae1f YR |
3121 | /*****************************************************************************/ |
3122 | /* External Phy section */ | |
3123 | /*****************************************************************************/ | |
3124 | void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port) | |
3125 | { | |
3126 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, | |
3127 | MISC_REGISTERS_GPIO_OUTPUT_LOW, port); | |
3128 | msleep(1); | |
3129 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, | |
3130 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); | |
3131 | } | |
589abe3a | 3132 | |
de6eae1f YR |
3133 | static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port, |
3134 | u32 spirom_ver, u32 ver_addr) | |
3135 | { | |
3136 | DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n", | |
3137 | (u16)(spirom_ver>>16), (u16)spirom_ver, port); | |
4d295db0 | 3138 | |
de6eae1f YR |
3139 | if (ver_addr) |
3140 | REG_WR(bp, ver_addr, spirom_ver); | |
589abe3a EG |
3141 | } |
3142 | ||
de6eae1f YR |
3143 | static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp, |
3144 | struct bnx2x_phy *phy, | |
3145 | u8 port) | |
6bbca910 | 3146 | { |
de6eae1f YR |
3147 | u16 fw_ver1, fw_ver2; |
3148 | ||
3149 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, | |
3150 | MDIO_PMA_REG_ROM_VER1, &fw_ver1); | |
3151 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, | |
3152 | MDIO_PMA_REG_ROM_VER2, &fw_ver2); | |
3153 | bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2), | |
3154 | phy->ver_addr); | |
ea4e040a | 3155 | } |
ab6ad5a4 | 3156 | |
de6eae1f YR |
3157 | static void bnx2x_ext_phy_set_pause(struct link_params *params, |
3158 | struct bnx2x_phy *phy, | |
3159 | struct link_vars *vars) | |
ea4e040a | 3160 | { |
ea4e040a | 3161 | u16 val; |
de6eae1f YR |
3162 | struct bnx2x *bp = params->bp; |
3163 | /* read modify write pause advertizing */ | |
3164 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val); | |
ea4e040a | 3165 | |
de6eae1f | 3166 | val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH; |
ea4e040a | 3167 | |
de6eae1f YR |
3168 | /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ |
3169 | bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); | |
3170 | if ((vars->ieee_fc & | |
3171 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == | |
3172 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { | |
3173 | val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; | |
3174 | } | |
3175 | if ((vars->ieee_fc & | |
3176 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == | |
3177 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { | |
3178 | val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; | |
3179 | } | |
3180 | DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val); | |
3181 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val); | |
3182 | } | |
3183 | ||
3184 | static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy, | |
3185 | struct link_params *params, | |
3186 | struct link_vars *vars) | |
3187 | { | |
3188 | struct bnx2x *bp = params->bp; | |
3189 | u16 ld_pause; /* local */ | |
3190 | u16 lp_pause; /* link partner */ | |
3191 | u16 pause_result; | |
3192 | u8 ret = 0; | |
3193 | /* read twice */ | |
3194 | ||
3195 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
3196 | ||
3197 | if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) | |
3198 | vars->flow_ctrl = phy->req_flow_ctrl; | |
3199 | else if (phy->req_line_speed != SPEED_AUTO_NEG) | |
3200 | vars->flow_ctrl = params->req_fc_auto_adv; | |
3201 | else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { | |
3202 | ret = 1; | |
3203 | bnx2x_cl45_read(bp, phy, | |
3204 | MDIO_AN_DEVAD, | |
3205 | MDIO_AN_REG_ADV_PAUSE, &ld_pause); | |
3206 | bnx2x_cl45_read(bp, phy, | |
3207 | MDIO_AN_DEVAD, | |
3208 | MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); | |
3209 | pause_result = (ld_pause & | |
3210 | MDIO_AN_REG_ADV_PAUSE_MASK) >> 8; | |
3211 | pause_result |= (lp_pause & | |
3212 | MDIO_AN_REG_ADV_PAUSE_MASK) >> 10; | |
3213 | DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", | |
3214 | pause_result); | |
3215 | bnx2x_pause_resolve(vars, pause_result); | |
3216 | } | |
3217 | return ret; | |
3218 | } | |
3219 | ||
3220 | static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp, | |
3221 | struct bnx2x_phy *phy, | |
3222 | struct link_vars *vars) | |
3223 | { | |
3224 | u16 val; | |
3225 | bnx2x_cl45_read(bp, phy, | |
3226 | MDIO_AN_DEVAD, | |
3227 | MDIO_AN_REG_STATUS, &val); | |
3228 | bnx2x_cl45_read(bp, phy, | |
3229 | MDIO_AN_DEVAD, | |
3230 | MDIO_AN_REG_STATUS, &val); | |
3231 | if (val & (1<<5)) | |
3232 | vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; | |
3233 | if ((val & (1<<0)) == 0) | |
3234 | vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED; | |
3235 | } | |
3236 | ||
3237 | /******************************************************************/ | |
3238 | /* common BCM8073/BCM8727 PHY SECTION */ | |
3239 | /******************************************************************/ | |
3240 | static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy, | |
3241 | struct link_params *params, | |
3242 | struct link_vars *vars) | |
3243 | { | |
3244 | struct bnx2x *bp = params->bp; | |
3245 | if (phy->req_line_speed == SPEED_10 || | |
3246 | phy->req_line_speed == SPEED_100) { | |
3247 | vars->flow_ctrl = phy->req_flow_ctrl; | |
3248 | return; | |
3249 | } | |
3250 | ||
3251 | if (bnx2x_ext_phy_resolve_fc(phy, params, vars) && | |
3252 | (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) { | |
3253 | u16 pause_result; | |
3254 | u16 ld_pause; /* local */ | |
3255 | u16 lp_pause; /* link partner */ | |
3256 | bnx2x_cl45_read(bp, phy, | |
3257 | MDIO_AN_DEVAD, | |
3258 | MDIO_AN_REG_CL37_FC_LD, &ld_pause); | |
3259 | ||
3260 | bnx2x_cl45_read(bp, phy, | |
3261 | MDIO_AN_DEVAD, | |
3262 | MDIO_AN_REG_CL37_FC_LP, &lp_pause); | |
3263 | pause_result = (ld_pause & | |
3264 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5; | |
3265 | pause_result |= (lp_pause & | |
3266 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7; | |
3267 | ||
3268 | bnx2x_pause_resolve(vars, pause_result); | |
3269 | DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n", | |
3270 | pause_result); | |
3271 | } | |
3272 | } | |
3273 | ||
3274 | static void bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp, | |
3275 | struct bnx2x_phy *phy, | |
3276 | u8 port) | |
3277 | { | |
3278 | /* Boot port from external ROM */ | |
3279 | /* EDC grst */ | |
3280 | bnx2x_cl45_write(bp, phy, | |
3281 | MDIO_PMA_DEVAD, | |
3282 | MDIO_PMA_REG_GEN_CTRL, | |
3283 | 0x0001); | |
3284 | ||
3285 | /* ucode reboot and rst */ | |
3286 | bnx2x_cl45_write(bp, phy, | |
3287 | MDIO_PMA_DEVAD, | |
3288 | MDIO_PMA_REG_GEN_CTRL, | |
3289 | 0x008c); | |
3290 | ||
3291 | bnx2x_cl45_write(bp, phy, | |
3292 | MDIO_PMA_DEVAD, | |
3293 | MDIO_PMA_REG_MISC_CTRL1, 0x0001); | |
3294 | ||
3295 | /* Reset internal microprocessor */ | |
3296 | bnx2x_cl45_write(bp, phy, | |
3297 | MDIO_PMA_DEVAD, | |
3298 | MDIO_PMA_REG_GEN_CTRL, | |
3299 | MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); | |
3300 | ||
3301 | /* Release srst bit */ | |
3302 | bnx2x_cl45_write(bp, phy, | |
3303 | MDIO_PMA_DEVAD, | |
3304 | MDIO_PMA_REG_GEN_CTRL, | |
3305 | MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); | |
3306 | ||
3307 | /* wait for 120ms for code download via SPI port */ | |
3308 | msleep(120); | |
3309 | ||
3310 | /* Clear ser_boot_ctl bit */ | |
3311 | bnx2x_cl45_write(bp, phy, | |
3312 | MDIO_PMA_DEVAD, | |
3313 | MDIO_PMA_REG_MISC_CTRL1, 0x0000); | |
3314 | bnx2x_save_bcm_spirom_ver(bp, phy, port); | |
3315 | } | |
3316 | ||
3317 | static void bnx2x_8073_set_xaui_low_power_mode(struct bnx2x *bp, | |
3318 | struct bnx2x_phy *phy) | |
3319 | { | |
3320 | u16 val; | |
3321 | bnx2x_cl45_read(bp, phy, | |
3322 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val); | |
3323 | ||
3324 | if (val == 0) { | |
3325 | /* Mustn't set low power mode in 8073 A0 */ | |
3326 | return; | |
3327 | } | |
3328 | ||
3329 | /* Disable PLL sequencer (use read-modify-write to clear bit 13) */ | |
3330 | bnx2x_cl45_read(bp, phy, | |
62b29a5d | 3331 | MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, &val); |
ea4e040a | 3332 | val &= ~(1<<13); |
e10bc84d | 3333 | bnx2x_cl45_write(bp, phy, |
ea4e040a YR |
3334 | MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val); |
3335 | ||
3336 | /* PLL controls */ | |
62b29a5d YR |
3337 | bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805E, 0x1077); |
3338 | bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805D, 0x0000); | |
3339 | bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805C, 0x030B); | |
3340 | bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805B, 0x1240); | |
3341 | bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805A, 0x2490); | |
ea4e040a YR |
3342 | |
3343 | /* Tx Controls */ | |
62b29a5d YR |
3344 | bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80A7, 0x0C74); |
3345 | bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80A6, 0x9041); | |
3346 | bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80A5, 0x4640); | |
ea4e040a YR |
3347 | |
3348 | /* Rx Controls */ | |
62b29a5d YR |
3349 | bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80FE, 0x01C4); |
3350 | bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80FD, 0x9249); | |
3351 | bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80FC, 0x2015); | |
ea4e040a YR |
3352 | |
3353 | /* Enable PLL sequencer (use read-modify-write to set bit 13) */ | |
62b29a5d | 3354 | bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, &val); |
ea4e040a | 3355 | val |= (1<<13); |
62b29a5d | 3356 | bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val); |
ea4e040a | 3357 | } |
6bbca910 | 3358 | |
de6eae1f YR |
3359 | /******************************************************************/ |
3360 | /* BCM8073 PHY SECTION */ | |
3361 | /******************************************************************/ | |
3362 | static u8 bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy) | |
3363 | { | |
3364 | /* This is only required for 8073A1, version 102 only */ | |
3365 | u16 val; | |
3366 | ||
3367 | /* Read 8073 HW revision*/ | |
3368 | bnx2x_cl45_read(bp, phy, | |
3369 | MDIO_PMA_DEVAD, | |
3370 | MDIO_PMA_REG_8073_CHIP_REV, &val); | |
3371 | ||
3372 | if (val != 1) { | |
3373 | /* No need to workaround in 8073 A1 */ | |
3374 | return 0; | |
3375 | } | |
3376 | ||
3377 | bnx2x_cl45_read(bp, phy, | |
3378 | MDIO_PMA_DEVAD, | |
3379 | MDIO_PMA_REG_ROM_VER2, &val); | |
3380 | ||
3381 | /* SNR should be applied only for version 0x102 */ | |
3382 | if (val != 0x102) | |
3383 | return 0; | |
3384 | ||
3385 | return 1; | |
3386 | } | |
3387 | ||
3388 | static u8 bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy) | |
3389 | { | |
3390 | u16 val, cnt, cnt1 ; | |
3391 | ||
3392 | bnx2x_cl45_read(bp, phy, | |
3393 | MDIO_PMA_DEVAD, | |
3394 | MDIO_PMA_REG_8073_CHIP_REV, &val); | |
3395 | ||
3396 | if (val > 0) { | |
3397 | /* No need to workaround in 8073 A1 */ | |
3398 | return 0; | |
3399 | } | |
3400 | /* XAUI workaround in 8073 A0: */ | |
3401 | ||
3402 | /* After loading the boot ROM and restarting Autoneg, | |
3403 | poll Dev1, Reg $C820: */ | |
3404 | ||
3405 | for (cnt = 0; cnt < 1000; cnt++) { | |
3406 | bnx2x_cl45_read(bp, phy, | |
3407 | MDIO_PMA_DEVAD, | |
3408 | MDIO_PMA_REG_8073_SPEED_LINK_STATUS, | |
3409 | &val); | |
3410 | /* If bit [14] = 0 or bit [13] = 0, continue on with | |
3411 | system initialization (XAUI work-around not required, | |
3412 | as these bits indicate 2.5G or 1G link up). */ | |
3413 | if (!(val & (1<<14)) || !(val & (1<<13))) { | |
3414 | DP(NETIF_MSG_LINK, "XAUI work-around not required\n"); | |
3415 | return 0; | |
3416 | } else if (!(val & (1<<15))) { | |
3417 | DP(NETIF_MSG_LINK, "clc bit 15 went off\n"); | |
3418 | /* If bit 15 is 0, then poll Dev1, Reg $C841 until | |
3419 | it's MSB (bit 15) goes to 1 (indicating that the | |
3420 | XAUI workaround has completed), | |
3421 | then continue on with system initialization.*/ | |
3422 | for (cnt1 = 0; cnt1 < 1000; cnt1++) { | |
3423 | bnx2x_cl45_read(bp, phy, | |
3424 | MDIO_PMA_DEVAD, | |
3425 | MDIO_PMA_REG_8073_XAUI_WA, &val); | |
3426 | if (val & (1<<15)) { | |
3427 | DP(NETIF_MSG_LINK, | |
3428 | "XAUI workaround has completed\n"); | |
3429 | return 0; | |
3430 | } | |
3431 | msleep(3); | |
3432 | } | |
3433 | break; | |
3434 | } | |
3435 | msleep(3); | |
3436 | } | |
3437 | DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n"); | |
3438 | return -EINVAL; | |
3439 | } | |
3440 | ||
3441 | static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy) | |
3442 | { | |
3443 | /* Force KR or KX */ | |
3444 | bnx2x_cl45_write(bp, phy, | |
3445 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); | |
3446 | bnx2x_cl45_write(bp, phy, | |
3447 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b); | |
3448 | bnx2x_cl45_write(bp, phy, | |
3449 | MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000); | |
3450 | bnx2x_cl45_write(bp, phy, | |
3451 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); | |
3452 | } | |
3453 | ||
6bbca910 | 3454 | static void bnx2x_8073_set_pause_cl37(struct link_params *params, |
e10bc84d YR |
3455 | struct bnx2x_phy *phy, |
3456 | struct link_vars *vars) | |
ea4e040a | 3457 | { |
6bbca910 | 3458 | u16 cl37_val; |
e10bc84d YR |
3459 | struct bnx2x *bp = params->bp; |
3460 | bnx2x_cl45_read(bp, phy, | |
62b29a5d | 3461 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val); |
6bbca910 YR |
3462 | |
3463 | cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; | |
3464 | /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ | |
e10bc84d | 3465 | bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); |
6bbca910 YR |
3466 | if ((vars->ieee_fc & |
3467 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) == | |
3468 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) { | |
3469 | cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC; | |
3470 | } | |
3471 | if ((vars->ieee_fc & | |
3472 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == | |
3473 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { | |
3474 | cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; | |
3475 | } | |
3476 | if ((vars->ieee_fc & | |
3477 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == | |
3478 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { | |
3479 | cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; | |
3480 | } | |
3481 | DP(NETIF_MSG_LINK, | |
3482 | "Ext phy AN advertize cl37 0x%x\n", cl37_val); | |
3483 | ||
e10bc84d | 3484 | bnx2x_cl45_write(bp, phy, |
62b29a5d | 3485 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val); |
6bbca910 | 3486 | msleep(500); |
ea4e040a YR |
3487 | } |
3488 | ||
de6eae1f YR |
3489 | static u8 bnx2x_8073_config_init(struct bnx2x_phy *phy, |
3490 | struct link_params *params, | |
3491 | struct link_vars *vars) | |
ea4e040a | 3492 | { |
e10bc84d | 3493 | struct bnx2x *bp = params->bp; |
de6eae1f YR |
3494 | u16 val = 0, tmp1; |
3495 | u8 gpio_port; | |
3496 | DP(NETIF_MSG_LINK, "Init 8073\n"); | |
e10bc84d | 3497 | |
f2e0899f DK |
3498 | if (CHIP_IS_E2(bp)) |
3499 | gpio_port = BP_PATH(bp); | |
3500 | else | |
3501 | gpio_port = params->port; | |
de6eae1f YR |
3502 | /* Restore normal power mode*/ |
3503 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
3504 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); | |
e10bc84d | 3505 | |
de6eae1f YR |
3506 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, |
3507 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); | |
ea4e040a | 3508 | |
de6eae1f YR |
3509 | /* enable LASI */ |
3510 | bnx2x_cl45_write(bp, phy, | |
3511 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL, (1<<2)); | |
3512 | bnx2x_cl45_write(bp, phy, | |
3513 | MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x0004); | |
c2c8b03e | 3514 | |
de6eae1f | 3515 | bnx2x_8073_set_pause_cl37(params, phy, vars); |
57963ed9 | 3516 | |
de6eae1f | 3517 | bnx2x_8073_set_xaui_low_power_mode(bp, phy); |
e10bc84d | 3518 | |
e10bc84d | 3519 | bnx2x_cl45_read(bp, phy, |
de6eae1f | 3520 | MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); |
2f904460 | 3521 | |
de6eae1f YR |
3522 | bnx2x_cl45_read(bp, phy, |
3523 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1); | |
2f904460 | 3524 | |
de6eae1f | 3525 | DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1); |
a1e4be39 | 3526 | |
de6eae1f YR |
3527 | /* Enable CL37 BAM */ |
3528 | bnx2x_cl45_read(bp, phy, | |
3529 | MDIO_AN_DEVAD, | |
3530 | MDIO_AN_REG_8073_BAM, &val); | |
e10bc84d | 3531 | bnx2x_cl45_write(bp, phy, |
a1e4be39 | 3532 | MDIO_AN_DEVAD, |
de6eae1f | 3533 | MDIO_AN_REG_8073_BAM, val | 1); |
57963ed9 | 3534 | |
de6eae1f YR |
3535 | if (params->loopback_mode == LOOPBACK_EXT) { |
3536 | bnx2x_807x_force_10G(bp, phy); | |
3537 | DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n"); | |
3538 | return 0; | |
3539 | } else { | |
3540 | bnx2x_cl45_write(bp, phy, | |
3541 | MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002); | |
3542 | } | |
3543 | if (phy->req_line_speed != SPEED_AUTO_NEG) { | |
3544 | if (phy->req_line_speed == SPEED_10000) { | |
3545 | val = (1<<7); | |
3546 | } else if (phy->req_line_speed == SPEED_2500) { | |
3547 | val = (1<<5); | |
3548 | /* Note that 2.5G works only | |
3549 | when used with 1G advertisment */ | |
3550 | } else | |
3551 | val = (1<<5); | |
3552 | } else { | |
3553 | val = 0; | |
3554 | if (phy->speed_cap_mask & | |
3555 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) | |
3556 | val |= (1<<7); | |
57963ed9 | 3557 | |
de6eae1f YR |
3558 | /* Note that 2.5G works only when |
3559 | used with 1G advertisment */ | |
3560 | if (phy->speed_cap_mask & | |
3561 | (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G | | |
3562 | PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) | |
3563 | val |= (1<<5); | |
3564 | DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val); | |
3565 | } | |
57963ed9 | 3566 | |
de6eae1f YR |
3567 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val); |
3568 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1); | |
57963ed9 | 3569 | |
de6eae1f YR |
3570 | if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) && |
3571 | (phy->req_line_speed == SPEED_AUTO_NEG)) || | |
3572 | (phy->req_line_speed == SPEED_2500)) { | |
3573 | u16 phy_ver; | |
3574 | /* Allow 2.5G for A1 and above */ | |
3575 | bnx2x_cl45_read(bp, phy, | |
3576 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, | |
3577 | &phy_ver); | |
3578 | DP(NETIF_MSG_LINK, "Add 2.5G\n"); | |
3579 | if (phy_ver > 0) | |
3580 | tmp1 |= 1; | |
3581 | else | |
3582 | tmp1 &= 0xfffe; | |
3583 | } else { | |
3584 | DP(NETIF_MSG_LINK, "Disable 2.5G\n"); | |
3585 | tmp1 &= 0xfffe; | |
3586 | } | |
57963ed9 | 3587 | |
de6eae1f YR |
3588 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1); |
3589 | /* Add support for CL37 (passive mode) II */ | |
57963ed9 | 3590 | |
de6eae1f YR |
3591 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1); |
3592 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, | |
3593 | (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ? | |
3594 | 0x20 : 0x40))); | |
57963ed9 | 3595 | |
de6eae1f YR |
3596 | /* Add support for CL37 (passive mode) III */ |
3597 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); | |
57963ed9 | 3598 | |
de6eae1f YR |
3599 | /* The SNR will improve about 2db by changing |
3600 | BW and FEE main tap. Rest commands are executed | |
3601 | after link is up*/ | |
3602 | if (bnx2x_8073_is_snr_needed(bp, phy)) | |
3603 | bnx2x_cl45_write(bp, phy, | |
3604 | MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN, | |
3605 | 0xFB0C); | |
57963ed9 | 3606 | |
de6eae1f YR |
3607 | /* Enable FEC (Forware Error Correction) Request in the AN */ |
3608 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1); | |
3609 | tmp1 |= (1<<15); | |
3610 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1); | |
57963ed9 | 3611 | |
de6eae1f | 3612 | bnx2x_ext_phy_set_pause(params, phy, vars); |
57963ed9 | 3613 | |
de6eae1f YR |
3614 | /* Restart autoneg */ |
3615 | msleep(500); | |
3616 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); | |
3617 | DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n", | |
3618 | ((val & (1<<5)) > 0), ((val & (1<<7)) > 0)); | |
3619 | return 0; | |
b7737c9b | 3620 | } |
ea4e040a | 3621 | |
de6eae1f | 3622 | static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy, |
b7737c9b YR |
3623 | struct link_params *params, |
3624 | struct link_vars *vars) | |
3625 | { | |
3626 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
3627 | u8 link_up = 0; |
3628 | u16 val1, val2; | |
3629 | u16 link_status = 0; | |
3630 | u16 an1000_status = 0; | |
a35da8db | 3631 | |
de6eae1f YR |
3632 | bnx2x_cl45_read(bp, phy, |
3633 | MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1); | |
b7737c9b | 3634 | |
de6eae1f | 3635 | DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1); |
ea4e040a | 3636 | |
de6eae1f YR |
3637 | /* clear the interrupt LASI status register */ |
3638 | bnx2x_cl45_read(bp, phy, | |
3639 | MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); | |
3640 | bnx2x_cl45_read(bp, phy, | |
3641 | MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1); | |
3642 | DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1); | |
3643 | /* Clear MSG-OUT */ | |
3644 | bnx2x_cl45_read(bp, phy, | |
3645 | MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); | |
3646 | ||
3647 | /* Check the LASI */ | |
3648 | bnx2x_cl45_read(bp, phy, | |
3649 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2); | |
3650 | ||
3651 | DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2); | |
3652 | ||
3653 | /* Check the link status */ | |
3654 | bnx2x_cl45_read(bp, phy, | |
3655 | MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); | |
3656 | DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2); | |
3657 | ||
3658 | bnx2x_cl45_read(bp, phy, | |
3659 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); | |
3660 | bnx2x_cl45_read(bp, phy, | |
3661 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); | |
3662 | link_up = ((val1 & 4) == 4); | |
3663 | DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1); | |
3664 | ||
3665 | if (link_up && | |
3666 | ((phy->req_line_speed != SPEED_10000))) { | |
3667 | if (bnx2x_8073_xaui_wa(bp, phy) != 0) | |
3668 | return 0; | |
62b29a5d | 3669 | } |
de6eae1f YR |
3670 | bnx2x_cl45_read(bp, phy, |
3671 | MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); | |
3672 | bnx2x_cl45_read(bp, phy, | |
3673 | MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); | |
62b29a5d | 3674 | |
de6eae1f YR |
3675 | /* Check the link status on 1.1.2 */ |
3676 | bnx2x_cl45_read(bp, phy, | |
3677 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); | |
3678 | bnx2x_cl45_read(bp, phy, | |
3679 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); | |
3680 | DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x," | |
3681 | "an_link_status=0x%x\n", val2, val1, an1000_status); | |
62b29a5d | 3682 | |
de6eae1f YR |
3683 | link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1))); |
3684 | if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) { | |
3685 | /* The SNR will improve about 2dbby | |
3686 | changing the BW and FEE main tap.*/ | |
3687 | /* The 1st write to change FFE main | |
3688 | tap is set before restart AN */ | |
3689 | /* Change PLL Bandwidth in EDC | |
3690 | register */ | |
62b29a5d | 3691 | bnx2x_cl45_write(bp, phy, |
de6eae1f YR |
3692 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH, |
3693 | 0x26BC); | |
62b29a5d | 3694 | |
de6eae1f | 3695 | /* Change CDR Bandwidth in EDC register */ |
62b29a5d | 3696 | bnx2x_cl45_write(bp, phy, |
de6eae1f YR |
3697 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH, |
3698 | 0x0333); | |
3699 | } | |
3700 | bnx2x_cl45_read(bp, phy, | |
3701 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS, | |
3702 | &link_status); | |
62b29a5d | 3703 | |
de6eae1f YR |
3704 | /* Bits 0..2 --> speed detected, bits 13..15--> link is down */ |
3705 | if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { | |
3706 | link_up = 1; | |
3707 | vars->line_speed = SPEED_10000; | |
3708 | DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n", | |
3709 | params->port); | |
3710 | } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) { | |
3711 | link_up = 1; | |
3712 | vars->line_speed = SPEED_2500; | |
3713 | DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n", | |
3714 | params->port); | |
3715 | } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { | |
3716 | link_up = 1; | |
3717 | vars->line_speed = SPEED_1000; | |
3718 | DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n", | |
3719 | params->port); | |
3720 | } else { | |
3721 | link_up = 0; | |
3722 | DP(NETIF_MSG_LINK, "port %x: External link is down\n", | |
3723 | params->port); | |
62b29a5d | 3724 | } |
de6eae1f YR |
3725 | |
3726 | if (link_up) { | |
3727 | bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); | |
3728 | bnx2x_8073_resolve_fc(phy, params, vars); | |
3729 | } | |
3730 | return link_up; | |
b7737c9b YR |
3731 | } |
3732 | ||
de6eae1f YR |
3733 | static void bnx2x_8073_link_reset(struct bnx2x_phy *phy, |
3734 | struct link_params *params) | |
3735 | { | |
3736 | struct bnx2x *bp = params->bp; | |
3737 | u8 gpio_port; | |
f2e0899f DK |
3738 | if (CHIP_IS_E2(bp)) |
3739 | gpio_port = BP_PATH(bp); | |
3740 | else | |
3741 | gpio_port = params->port; | |
de6eae1f YR |
3742 | DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n", |
3743 | gpio_port); | |
3744 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
3745 | MISC_REGISTERS_GPIO_OUTPUT_LOW, | |
3746 | gpio_port); | |
3747 | } | |
3748 | ||
3749 | /******************************************************************/ | |
3750 | /* BCM8705 PHY SECTION */ | |
3751 | /******************************************************************/ | |
3752 | static u8 bnx2x_8705_config_init(struct bnx2x_phy *phy, | |
b7737c9b YR |
3753 | struct link_params *params, |
3754 | struct link_vars *vars) | |
3755 | { | |
3756 | struct bnx2x *bp = params->bp; | |
de6eae1f | 3757 | DP(NETIF_MSG_LINK, "init 8705\n"); |
b7737c9b YR |
3758 | /* Restore normal power mode*/ |
3759 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
3760 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); | |
de6eae1f YR |
3761 | /* HW reset */ |
3762 | bnx2x_ext_phy_hw_reset(bp, params->port); | |
3763 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); | |
b7737c9b YR |
3764 | bnx2x_wait_reset_complete(bp, phy); |
3765 | ||
de6eae1f YR |
3766 | bnx2x_cl45_write(bp, phy, |
3767 | MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288); | |
3768 | bnx2x_cl45_write(bp, phy, | |
3769 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf); | |
3770 | bnx2x_cl45_write(bp, phy, | |
3771 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100); | |
3772 | bnx2x_cl45_write(bp, phy, | |
3773 | MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1); | |
3774 | /* BCM8705 doesn't have microcode, hence the 0 */ | |
3775 | bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0); | |
3776 | return 0; | |
3777 | } | |
4d295db0 | 3778 | |
de6eae1f YR |
3779 | static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy, |
3780 | struct link_params *params, | |
3781 | struct link_vars *vars) | |
3782 | { | |
3783 | u8 link_up = 0; | |
3784 | u16 val1, rx_sd; | |
3785 | struct bnx2x *bp = params->bp; | |
3786 | DP(NETIF_MSG_LINK, "read status 8705\n"); | |
3787 | bnx2x_cl45_read(bp, phy, | |
3788 | MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); | |
3789 | DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); | |
62b29a5d | 3790 | |
de6eae1f YR |
3791 | bnx2x_cl45_read(bp, phy, |
3792 | MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); | |
3793 | DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); | |
62b29a5d | 3794 | |
de6eae1f YR |
3795 | bnx2x_cl45_read(bp, phy, |
3796 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); | |
c2c8b03e | 3797 | |
de6eae1f YR |
3798 | bnx2x_cl45_read(bp, phy, |
3799 | MDIO_PMA_DEVAD, 0xc809, &val1); | |
3800 | bnx2x_cl45_read(bp, phy, | |
3801 | MDIO_PMA_DEVAD, 0xc809, &val1); | |
c2c8b03e | 3802 | |
de6eae1f YR |
3803 | DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1); |
3804 | link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0)); | |
3805 | if (link_up) { | |
3806 | vars->line_speed = SPEED_10000; | |
3807 | bnx2x_ext_phy_resolve_fc(phy, params, vars); | |
62b29a5d | 3808 | } |
de6eae1f YR |
3809 | return link_up; |
3810 | } | |
d90d96ba | 3811 | |
de6eae1f YR |
3812 | /******************************************************************/ |
3813 | /* SFP+ module Section */ | |
3814 | /******************************************************************/ | |
3815 | static void bnx2x_sfp_set_transmitter(struct bnx2x *bp, | |
3816 | struct bnx2x_phy *phy, | |
3817 | u8 port, | |
3818 | u8 tx_en) | |
3819 | { | |
3820 | u16 val; | |
d90d96ba | 3821 | |
de6eae1f YR |
3822 | DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x\n", |
3823 | tx_en, port); | |
3824 | /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/ | |
3825 | bnx2x_cl45_read(bp, phy, | |
3826 | MDIO_PMA_DEVAD, | |
3827 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
3828 | &val); | |
d90d96ba | 3829 | |
de6eae1f YR |
3830 | if (tx_en) |
3831 | val &= ~(1<<15); | |
3832 | else | |
3833 | val |= (1<<15); | |
b7737c9b | 3834 | |
de6eae1f YR |
3835 | bnx2x_cl45_write(bp, phy, |
3836 | MDIO_PMA_DEVAD, | |
3837 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
3838 | val); | |
b7737c9b YR |
3839 | } |
3840 | ||
de6eae1f YR |
3841 | static u8 bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
3842 | struct link_params *params, | |
3843 | u16 addr, u8 byte_cnt, u8 *o_buf) | |
b7737c9b YR |
3844 | { |
3845 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
3846 | u16 val = 0; |
3847 | u16 i; | |
3848 | if (byte_cnt > 16) { | |
3849 | DP(NETIF_MSG_LINK, "Reading from eeprom is" | |
3850 | " is limited to 0xf\n"); | |
3851 | return -EINVAL; | |
3852 | } | |
3853 | /* Set the read command byte count */ | |
62b29a5d | 3854 | bnx2x_cl45_write(bp, phy, |
de6eae1f YR |
3855 | MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, |
3856 | (byte_cnt | 0xa000)); | |
ea4e040a | 3857 | |
de6eae1f YR |
3858 | /* Set the read command address */ |
3859 | bnx2x_cl45_write(bp, phy, | |
3860 | MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, | |
3861 | addr); | |
ea4e040a | 3862 | |
de6eae1f | 3863 | /* Activate read command */ |
62b29a5d | 3864 | bnx2x_cl45_write(bp, phy, |
de6eae1f YR |
3865 | MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, |
3866 | 0x2c0f); | |
ea4e040a | 3867 | |
de6eae1f YR |
3868 | /* Wait up to 500us for command complete status */ |
3869 | for (i = 0; i < 100; i++) { | |
3870 | bnx2x_cl45_read(bp, phy, | |
3871 | MDIO_PMA_DEVAD, | |
3872 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); | |
3873 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == | |
3874 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) | |
3875 | break; | |
3876 | udelay(5); | |
62b29a5d | 3877 | } |
62b29a5d | 3878 | |
de6eae1f YR |
3879 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != |
3880 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { | |
3881 | DP(NETIF_MSG_LINK, | |
3882 | "Got bad status 0x%x when reading from SFP+ EEPROM\n", | |
3883 | (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); | |
3884 | return -EINVAL; | |
62b29a5d | 3885 | } |
e10bc84d | 3886 | |
de6eae1f YR |
3887 | /* Read the buffer */ |
3888 | for (i = 0; i < byte_cnt; i++) { | |
62b29a5d | 3889 | bnx2x_cl45_read(bp, phy, |
de6eae1f YR |
3890 | MDIO_PMA_DEVAD, |
3891 | MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val); | |
3892 | o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK); | |
62b29a5d | 3893 | } |
6bbca910 | 3894 | |
de6eae1f YR |
3895 | for (i = 0; i < 100; i++) { |
3896 | bnx2x_cl45_read(bp, phy, | |
3897 | MDIO_PMA_DEVAD, | |
3898 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); | |
3899 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == | |
3900 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) | |
3901 | return 0;; | |
3902 | msleep(1); | |
3903 | } | |
3904 | return -EINVAL; | |
b7737c9b | 3905 | } |
4d295db0 | 3906 | |
de6eae1f YR |
3907 | static u8 bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
3908 | struct link_params *params, | |
3909 | u16 addr, u8 byte_cnt, u8 *o_buf) | |
b7737c9b | 3910 | { |
b7737c9b | 3911 | struct bnx2x *bp = params->bp; |
de6eae1f | 3912 | u16 val, i; |
ea4e040a | 3913 | |
de6eae1f YR |
3914 | if (byte_cnt > 16) { |
3915 | DP(NETIF_MSG_LINK, "Reading from eeprom is" | |
3916 | " is limited to 0xf\n"); | |
3917 | return -EINVAL; | |
3918 | } | |
4d295db0 | 3919 | |
de6eae1f YR |
3920 | /* Need to read from 1.8000 to clear it */ |
3921 | bnx2x_cl45_read(bp, phy, | |
3922 | MDIO_PMA_DEVAD, | |
3923 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, | |
3924 | &val); | |
4d295db0 | 3925 | |
de6eae1f | 3926 | /* Set the read command byte count */ |
62b29a5d | 3927 | bnx2x_cl45_write(bp, phy, |
de6eae1f YR |
3928 | MDIO_PMA_DEVAD, |
3929 | MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, | |
3930 | ((byte_cnt < 2) ? 2 : byte_cnt)); | |
ea4e040a | 3931 | |
de6eae1f | 3932 | /* Set the read command address */ |
62b29a5d | 3933 | bnx2x_cl45_write(bp, phy, |
de6eae1f YR |
3934 | MDIO_PMA_DEVAD, |
3935 | MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, | |
3936 | addr); | |
3937 | /* Set the destination address */ | |
62b29a5d | 3938 | bnx2x_cl45_write(bp, phy, |
de6eae1f YR |
3939 | MDIO_PMA_DEVAD, |
3940 | 0x8004, | |
3941 | MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF); | |
62b29a5d | 3942 | |
de6eae1f | 3943 | /* Activate read command */ |
62b29a5d | 3944 | bnx2x_cl45_write(bp, phy, |
de6eae1f YR |
3945 | MDIO_PMA_DEVAD, |
3946 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, | |
3947 | 0x8002); | |
3948 | /* Wait appropriate time for two-wire command to finish before | |
3949 | polling the status register */ | |
3950 | msleep(1); | |
4d295db0 | 3951 | |
de6eae1f YR |
3952 | /* Wait up to 500us for command complete status */ |
3953 | for (i = 0; i < 100; i++) { | |
62b29a5d | 3954 | bnx2x_cl45_read(bp, phy, |
de6eae1f YR |
3955 | MDIO_PMA_DEVAD, |
3956 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); | |
3957 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == | |
3958 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) | |
3959 | break; | |
3960 | udelay(5); | |
62b29a5d | 3961 | } |
4d295db0 | 3962 | |
de6eae1f YR |
3963 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != |
3964 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { | |
3965 | DP(NETIF_MSG_LINK, | |
3966 | "Got bad status 0x%x when reading from SFP+ EEPROM\n", | |
3967 | (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); | |
3968 | return -EINVAL; | |
3969 | } | |
62b29a5d | 3970 | |
de6eae1f YR |
3971 | /* Read the buffer */ |
3972 | for (i = 0; i < byte_cnt; i++) { | |
3973 | bnx2x_cl45_read(bp, phy, | |
3974 | MDIO_PMA_DEVAD, | |
3975 | MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val); | |
3976 | o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK); | |
3977 | } | |
4d295db0 | 3978 | |
de6eae1f YR |
3979 | for (i = 0; i < 100; i++) { |
3980 | bnx2x_cl45_read(bp, phy, | |
3981 | MDIO_PMA_DEVAD, | |
3982 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); | |
3983 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == | |
3984 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) | |
3985 | return 0;; | |
3986 | msleep(1); | |
62b29a5d YR |
3987 | } |
3988 | ||
de6eae1f | 3989 | return -EINVAL; |
b7737c9b YR |
3990 | } |
3991 | ||
8d96286a | 3992 | static u8 bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
3993 | struct link_params *params, u16 addr, | |
3994 | u8 byte_cnt, u8 *o_buf) | |
b7737c9b | 3995 | { |
de6eae1f YR |
3996 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) |
3997 | return bnx2x_8726_read_sfp_module_eeprom(phy, params, addr, | |
3998 | byte_cnt, o_buf); | |
3999 | else if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) | |
4000 | return bnx2x_8727_read_sfp_module_eeprom(phy, params, addr, | |
4001 | byte_cnt, o_buf); | |
4002 | return -EINVAL; | |
b7737c9b YR |
4003 | } |
4004 | ||
de6eae1f YR |
4005 | static u8 bnx2x_get_edc_mode(struct bnx2x_phy *phy, |
4006 | struct link_params *params, | |
4007 | u16 *edc_mode) | |
b7737c9b YR |
4008 | { |
4009 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
4010 | u8 val, check_limiting_mode = 0; |
4011 | *edc_mode = EDC_MODE_LIMITING; | |
62b29a5d | 4012 | |
de6eae1f YR |
4013 | /* First check for copper cable */ |
4014 | if (bnx2x_read_sfp_module_eeprom(phy, | |
4015 | params, | |
4016 | SFP_EEPROM_CON_TYPE_ADDR, | |
4017 | 1, | |
4018 | &val) != 0) { | |
4019 | DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n"); | |
4020 | return -EINVAL; | |
4021 | } | |
a1e4be39 | 4022 | |
de6eae1f YR |
4023 | switch (val) { |
4024 | case SFP_EEPROM_CON_TYPE_VAL_COPPER: | |
4025 | { | |
4026 | u8 copper_module_type; | |
62b29a5d | 4027 | |
de6eae1f YR |
4028 | /* Check if its active cable( includes SFP+ module) |
4029 | of passive cable*/ | |
4030 | if (bnx2x_read_sfp_module_eeprom(phy, | |
4031 | params, | |
4032 | SFP_EEPROM_FC_TX_TECH_ADDR, | |
4033 | 1, | |
4034 | &copper_module_type) != | |
4035 | 0) { | |
4036 | DP(NETIF_MSG_LINK, | |
4037 | "Failed to read copper-cable-type" | |
4038 | " from SFP+ EEPROM\n"); | |
4039 | return -EINVAL; | |
4040 | } | |
4f60dab1 | 4041 | |
de6eae1f YR |
4042 | if (copper_module_type & |
4043 | SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) { | |
4044 | DP(NETIF_MSG_LINK, "Active Copper cable detected\n"); | |
4045 | check_limiting_mode = 1; | |
4046 | } else if (copper_module_type & | |
4047 | SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) { | |
4048 | DP(NETIF_MSG_LINK, "Passive Copper" | |
4049 | " cable detected\n"); | |
4050 | *edc_mode = | |
4051 | EDC_MODE_PASSIVE_DAC; | |
4052 | } else { | |
4053 | DP(NETIF_MSG_LINK, "Unknown copper-cable-" | |
4054 | "type 0x%x !!!\n", copper_module_type); | |
4055 | return -EINVAL; | |
4056 | } | |
4057 | break; | |
62b29a5d | 4058 | } |
de6eae1f YR |
4059 | case SFP_EEPROM_CON_TYPE_VAL_LC: |
4060 | DP(NETIF_MSG_LINK, "Optic module detected\n"); | |
4061 | check_limiting_mode = 1; | |
4062 | break; | |
4063 | default: | |
4064 | DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n", | |
4065 | val); | |
4066 | return -EINVAL; | |
62b29a5d | 4067 | } |
2f904460 | 4068 | |
de6eae1f YR |
4069 | if (check_limiting_mode) { |
4070 | u8 options[SFP_EEPROM_OPTIONS_SIZE]; | |
4071 | if (bnx2x_read_sfp_module_eeprom(phy, | |
4072 | params, | |
4073 | SFP_EEPROM_OPTIONS_ADDR, | |
4074 | SFP_EEPROM_OPTIONS_SIZE, | |
4075 | options) != 0) { | |
4076 | DP(NETIF_MSG_LINK, "Failed to read Option" | |
4077 | " field from module EEPROM\n"); | |
4078 | return -EINVAL; | |
4079 | } | |
4080 | if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK)) | |
4081 | *edc_mode = EDC_MODE_LINEAR; | |
4082 | else | |
4083 | *edc_mode = EDC_MODE_LIMITING; | |
62b29a5d | 4084 | } |
de6eae1f | 4085 | DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode); |
62b29a5d | 4086 | return 0; |
b7737c9b | 4087 | } |
de6eae1f YR |
4088 | /* This function read the relevant field from the module ( SFP+ ), |
4089 | and verify it is compliant with this board */ | |
4090 | static u8 bnx2x_verify_sfp_module(struct bnx2x_phy *phy, | |
4091 | struct link_params *params) | |
b7737c9b YR |
4092 | { |
4093 | struct bnx2x *bp = params->bp; | |
a22f0788 YR |
4094 | u32 val, cmd; |
4095 | u32 fw_resp, fw_cmd_param; | |
de6eae1f YR |
4096 | char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1]; |
4097 | char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1]; | |
a22f0788 | 4098 | phy->flags &= ~FLAGS_SFP_NOT_APPROVED; |
de6eae1f YR |
4099 | val = REG_RD(bp, params->shmem_base + |
4100 | offsetof(struct shmem_region, dev_info. | |
4101 | port_feature_config[params->port].config)); | |
4102 | if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == | |
4103 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) { | |
4104 | DP(NETIF_MSG_LINK, "NOT enforcing module verification\n"); | |
4105 | return 0; | |
4106 | } | |
ea4e040a | 4107 | |
a22f0788 YR |
4108 | if (params->feature_config_flags & |
4109 | FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) { | |
4110 | /* Use specific phy request */ | |
4111 | cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL; | |
4112 | } else if (params->feature_config_flags & | |
4113 | FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) { | |
4114 | /* Use first phy request only in case of non-dual media*/ | |
4115 | if (DUAL_MEDIA(params)) { | |
4116 | DP(NETIF_MSG_LINK, "FW does not support OPT MDL " | |
4117 | "verification\n"); | |
4118 | return -EINVAL; | |
4119 | } | |
4120 | cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL; | |
4121 | } else { | |
4122 | /* No support in OPT MDL detection */ | |
de6eae1f | 4123 | DP(NETIF_MSG_LINK, "FW does not support OPT MDL " |
a22f0788 | 4124 | "verification\n"); |
de6eae1f YR |
4125 | return -EINVAL; |
4126 | } | |
523224a3 | 4127 | |
a22f0788 YR |
4128 | fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl); |
4129 | fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param); | |
de6eae1f YR |
4130 | if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) { |
4131 | DP(NETIF_MSG_LINK, "Approved module\n"); | |
4132 | return 0; | |
4133 | } | |
b7737c9b | 4134 | |
de6eae1f YR |
4135 | /* format the warning message */ |
4136 | if (bnx2x_read_sfp_module_eeprom(phy, | |
4137 | params, | |
4138 | SFP_EEPROM_VENDOR_NAME_ADDR, | |
4139 | SFP_EEPROM_VENDOR_NAME_SIZE, | |
4140 | (u8 *)vendor_name)) | |
4141 | vendor_name[0] = '\0'; | |
4142 | else | |
4143 | vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0'; | |
4144 | if (bnx2x_read_sfp_module_eeprom(phy, | |
4145 | params, | |
4146 | SFP_EEPROM_PART_NO_ADDR, | |
4147 | SFP_EEPROM_PART_NO_SIZE, | |
4148 | (u8 *)vendor_pn)) | |
4149 | vendor_pn[0] = '\0'; | |
4150 | else | |
4151 | vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0'; | |
4152 | ||
4153 | netdev_info(bp->dev, "Warning: Unqualified SFP+ module detected," | |
4154 | " Port %d from %s part number %s\n", | |
4155 | params->port, vendor_name, vendor_pn); | |
a22f0788 | 4156 | phy->flags |= FLAGS_SFP_NOT_APPROVED; |
de6eae1f | 4157 | return -EINVAL; |
b7737c9b | 4158 | } |
7aa0711f | 4159 | |
de6eae1f YR |
4160 | static u8 bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy, |
4161 | struct link_params *params) | |
7aa0711f | 4162 | |
4d295db0 | 4163 | { |
de6eae1f | 4164 | u8 val; |
4d295db0 | 4165 | struct bnx2x *bp = params->bp; |
de6eae1f YR |
4166 | u16 timeout; |
4167 | /* Initialization time after hot-plug may take up to 300ms for some | |
4168 | phys type ( e.g. JDSU ) */ | |
4169 | for (timeout = 0; timeout < 60; timeout++) { | |
4170 | if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val) | |
4171 | == 0) { | |
4172 | DP(NETIF_MSG_LINK, "SFP+ module initialization " | |
4173 | "took %d ms\n", timeout * 5); | |
4174 | return 0; | |
4175 | } | |
4176 | msleep(5); | |
4177 | } | |
4178 | return -EINVAL; | |
4179 | } | |
4d295db0 | 4180 | |
de6eae1f YR |
4181 | static void bnx2x_8727_power_module(struct bnx2x *bp, |
4182 | struct bnx2x_phy *phy, | |
4183 | u8 is_power_up) { | |
4184 | /* Make sure GPIOs are not using for LED mode */ | |
4185 | u16 val; | |
4186 | /* | |
4187 | * In the GPIO register, bit 4 is use to detemine if the GPIOs are | |
4188 | * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for | |
4189 | * output | |
4190 | * Bits 0-1 determine the gpios value for OUTPUT in case bit 4 val is 0 | |
4191 | * Bits 8-9 determine the gpios value for INPUT in case bit 4 val is 1 | |
4192 | * where the 1st bit is the over-current(only input), and 2nd bit is | |
4193 | * for power( only output ) | |
4194 | */ | |
4d295db0 | 4195 | |
de6eae1f YR |
4196 | /* |
4197 | * In case of NOC feature is disabled and power is up, set GPIO control | |
4198 | * as input to enable listening of over-current indication | |
4199 | */ | |
4200 | if (phy->flags & FLAGS_NOC) | |
4201 | return; | |
4202 | if (!(phy->flags & | |
4203 | FLAGS_NOC) && is_power_up) | |
4204 | val = (1<<4); | |
4205 | else | |
4206 | /* | |
4207 | * Set GPIO control to OUTPUT, and set the power bit | |
4208 | * to according to the is_power_up | |
4209 | */ | |
4210 | val = ((!(is_power_up)) << 1); | |
4d295db0 | 4211 | |
de6eae1f YR |
4212 | bnx2x_cl45_write(bp, phy, |
4213 | MDIO_PMA_DEVAD, | |
4214 | MDIO_PMA_REG_8727_GPIO_CTRL, | |
4215 | val); | |
4216 | } | |
4d295db0 | 4217 | |
de6eae1f YR |
4218 | static u8 bnx2x_8726_set_limiting_mode(struct bnx2x *bp, |
4219 | struct bnx2x_phy *phy, | |
4220 | u16 edc_mode) | |
4221 | { | |
4222 | u16 cur_limiting_mode; | |
4d295db0 | 4223 | |
de6eae1f YR |
4224 | bnx2x_cl45_read(bp, phy, |
4225 | MDIO_PMA_DEVAD, | |
4226 | MDIO_PMA_REG_ROM_VER2, | |
4227 | &cur_limiting_mode); | |
4228 | DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n", | |
4229 | cur_limiting_mode); | |
4230 | ||
4231 | if (edc_mode == EDC_MODE_LIMITING) { | |
4232 | DP(NETIF_MSG_LINK, | |
4233 | "Setting LIMITING MODE\n"); | |
e10bc84d | 4234 | bnx2x_cl45_write(bp, phy, |
62b29a5d | 4235 | MDIO_PMA_DEVAD, |
de6eae1f YR |
4236 | MDIO_PMA_REG_ROM_VER2, |
4237 | EDC_MODE_LIMITING); | |
4238 | } else { /* LRM mode ( default )*/ | |
4d295db0 | 4239 | |
de6eae1f | 4240 | DP(NETIF_MSG_LINK, "Setting LRM MODE\n"); |
4d295db0 | 4241 | |
de6eae1f YR |
4242 | /* Changing to LRM mode takes quite few seconds. |
4243 | So do it only if current mode is limiting | |
4244 | ( default is LRM )*/ | |
4245 | if (cur_limiting_mode != EDC_MODE_LIMITING) | |
4246 | return 0; | |
4d295db0 | 4247 | |
de6eae1f YR |
4248 | bnx2x_cl45_write(bp, phy, |
4249 | MDIO_PMA_DEVAD, | |
4250 | MDIO_PMA_REG_LRM_MODE, | |
4251 | 0); | |
4252 | bnx2x_cl45_write(bp, phy, | |
4253 | MDIO_PMA_DEVAD, | |
4254 | MDIO_PMA_REG_ROM_VER2, | |
4255 | 0x128); | |
4256 | bnx2x_cl45_write(bp, phy, | |
4257 | MDIO_PMA_DEVAD, | |
4258 | MDIO_PMA_REG_MISC_CTRL0, | |
4259 | 0x4008); | |
4260 | bnx2x_cl45_write(bp, phy, | |
4261 | MDIO_PMA_DEVAD, | |
4262 | MDIO_PMA_REG_LRM_MODE, | |
4263 | 0xaaaa); | |
4d295db0 | 4264 | } |
de6eae1f | 4265 | return 0; |
4d295db0 EG |
4266 | } |
4267 | ||
de6eae1f YR |
4268 | static u8 bnx2x_8727_set_limiting_mode(struct bnx2x *bp, |
4269 | struct bnx2x_phy *phy, | |
4270 | u16 edc_mode) | |
ea4e040a | 4271 | { |
de6eae1f YR |
4272 | u16 phy_identifier; |
4273 | u16 rom_ver2_val; | |
62b29a5d | 4274 | bnx2x_cl45_read(bp, phy, |
de6eae1f YR |
4275 | MDIO_PMA_DEVAD, |
4276 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
4277 | &phy_identifier); | |
ea4e040a | 4278 | |
de6eae1f YR |
4279 | bnx2x_cl45_write(bp, phy, |
4280 | MDIO_PMA_DEVAD, | |
4281 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
4282 | (phy_identifier & ~(1<<9))); | |
ea4e040a | 4283 | |
62b29a5d | 4284 | bnx2x_cl45_read(bp, phy, |
de6eae1f YR |
4285 | MDIO_PMA_DEVAD, |
4286 | MDIO_PMA_REG_ROM_VER2, | |
4287 | &rom_ver2_val); | |
4288 | /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */ | |
4289 | bnx2x_cl45_write(bp, phy, | |
4290 | MDIO_PMA_DEVAD, | |
4291 | MDIO_PMA_REG_ROM_VER2, | |
4292 | (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff)); | |
4d295db0 | 4293 | |
de6eae1f YR |
4294 | bnx2x_cl45_write(bp, phy, |
4295 | MDIO_PMA_DEVAD, | |
4296 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
4297 | (phy_identifier | (1<<9))); | |
4d295db0 | 4298 | |
de6eae1f | 4299 | return 0; |
b7737c9b | 4300 | } |
ea4e040a | 4301 | |
a22f0788 YR |
4302 | static void bnx2x_8727_specific_func(struct bnx2x_phy *phy, |
4303 | struct link_params *params, | |
4304 | u32 action) | |
4305 | { | |
4306 | struct bnx2x *bp = params->bp; | |
4307 | ||
4308 | switch (action) { | |
4309 | case DISABLE_TX: | |
4310 | bnx2x_sfp_set_transmitter(bp, phy, params->port, 0); | |
4311 | break; | |
4312 | case ENABLE_TX: | |
4313 | if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) | |
4314 | bnx2x_sfp_set_transmitter(bp, phy, params->port, 1); | |
4315 | break; | |
4316 | default: | |
4317 | DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n", | |
4318 | action); | |
4319 | return; | |
4320 | } | |
4321 | } | |
4322 | ||
de6eae1f YR |
4323 | static u8 bnx2x_sfp_module_detection(struct bnx2x_phy *phy, |
4324 | struct link_params *params) | |
b7737c9b | 4325 | { |
b7737c9b | 4326 | struct bnx2x *bp = params->bp; |
de6eae1f YR |
4327 | u16 edc_mode; |
4328 | u8 rc = 0; | |
ea4e040a | 4329 | |
de6eae1f YR |
4330 | u32 val = REG_RD(bp, params->shmem_base + |
4331 | offsetof(struct shmem_region, dev_info. | |
4332 | port_feature_config[params->port].config)); | |
62b29a5d | 4333 | |
de6eae1f YR |
4334 | DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n", |
4335 | params->port); | |
4336 | ||
4337 | if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) { | |
4338 | DP(NETIF_MSG_LINK, "Failed to get valid module type\n"); | |
4339 | return -EINVAL; | |
4340 | } else if (bnx2x_verify_sfp_module(phy, params) != | |
4341 | 0) { | |
4342 | /* check SFP+ module compatibility */ | |
4343 | DP(NETIF_MSG_LINK, "Module verification failed!!\n"); | |
4344 | rc = -EINVAL; | |
4345 | /* Turn on fault module-detected led */ | |
4346 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, | |
4347 | MISC_REGISTERS_GPIO_HIGH, | |
4348 | params->port); | |
4349 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) && | |
4350 | ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == | |
4351 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN)) { | |
4352 | /* Shutdown SFP+ module */ | |
4353 | DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n"); | |
4354 | bnx2x_8727_power_module(bp, phy, 0); | |
4355 | return rc; | |
4356 | } | |
4357 | } else { | |
4358 | /* Turn off fault module-detected led */ | |
4359 | DP(NETIF_MSG_LINK, "Turn off fault module-detected led\n"); | |
4360 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, | |
4361 | MISC_REGISTERS_GPIO_LOW, | |
4362 | params->port); | |
62b29a5d | 4363 | } |
b7737c9b | 4364 | |
de6eae1f YR |
4365 | /* power up the SFP module */ |
4366 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) | |
4367 | bnx2x_8727_power_module(bp, phy, 1); | |
c18aa15d | 4368 | |
de6eae1f YR |
4369 | /* Check and set limiting mode / LRM mode on 8726. |
4370 | On 8727 it is done automatically */ | |
4371 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) | |
4372 | bnx2x_8726_set_limiting_mode(bp, phy, edc_mode); | |
4373 | else | |
4374 | bnx2x_8727_set_limiting_mode(bp, phy, edc_mode); | |
4375 | /* | |
4376 | * Enable transmit for this module if the module is approved, or | |
4377 | * if unapproved modules should also enable the Tx laser | |
4378 | */ | |
4379 | if (rc == 0 || | |
4380 | (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) != | |
4381 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) | |
4382 | bnx2x_sfp_set_transmitter(bp, phy, params->port, 1); | |
4383 | else | |
4384 | bnx2x_sfp_set_transmitter(bp, phy, params->port, 0); | |
b7737c9b | 4385 | |
de6eae1f YR |
4386 | return rc; |
4387 | } | |
4388 | ||
4389 | void bnx2x_handle_module_detect_int(struct link_params *params) | |
b7737c9b YR |
4390 | { |
4391 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
4392 | struct bnx2x_phy *phy = ¶ms->phy[EXT_PHY1]; |
4393 | u32 gpio_val; | |
4394 | u8 port = params->port; | |
4d295db0 | 4395 | |
de6eae1f YR |
4396 | /* Set valid module led off */ |
4397 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, | |
4398 | MISC_REGISTERS_GPIO_HIGH, | |
4399 | params->port); | |
4d295db0 | 4400 | |
de6eae1f YR |
4401 | /* Get current gpio val refelecting module plugged in / out*/ |
4402 | gpio_val = bnx2x_get_gpio(bp, MISC_REGISTERS_GPIO_3, port); | |
62b29a5d | 4403 | |
de6eae1f YR |
4404 | /* Call the handling function in case module is detected */ |
4405 | if (gpio_val == 0) { | |
4d295db0 | 4406 | |
de6eae1f YR |
4407 | bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3, |
4408 | MISC_REGISTERS_GPIO_INT_OUTPUT_CLR, | |
4409 | port); | |
4d295db0 | 4410 | |
de6eae1f YR |
4411 | if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) |
4412 | bnx2x_sfp_module_detection(phy, params); | |
4413 | else | |
4414 | DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); | |
4415 | } else { | |
4416 | u32 val = REG_RD(bp, params->shmem_base + | |
4417 | offsetof(struct shmem_region, dev_info. | |
4418 | port_feature_config[params->port]. | |
4419 | config)); | |
4d295db0 | 4420 | |
de6eae1f YR |
4421 | bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3, |
4422 | MISC_REGISTERS_GPIO_INT_OUTPUT_SET, | |
4423 | port); | |
4424 | /* Module was plugged out. */ | |
4425 | /* Disable transmit for this module */ | |
4426 | if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == | |
4427 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) | |
4428 | bnx2x_sfp_set_transmitter(bp, phy, params->port, 0); | |
62b29a5d | 4429 | } |
de6eae1f | 4430 | } |
62b29a5d | 4431 | |
de6eae1f YR |
4432 | /******************************************************************/ |
4433 | /* common BCM8706/BCM8726 PHY SECTION */ | |
4434 | /******************************************************************/ | |
4435 | static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy, | |
4436 | struct link_params *params, | |
4437 | struct link_vars *vars) | |
4438 | { | |
4439 | u8 link_up = 0; | |
4440 | u16 val1, val2, rx_sd, pcs_status; | |
4441 | struct bnx2x *bp = params->bp; | |
4442 | DP(NETIF_MSG_LINK, "XGXS 8706/8726\n"); | |
4443 | /* Clear RX Alarm*/ | |
62b29a5d | 4444 | bnx2x_cl45_read(bp, phy, |
de6eae1f YR |
4445 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2); |
4446 | /* clear LASI indication*/ | |
4447 | bnx2x_cl45_read(bp, phy, | |
4448 | MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1); | |
4449 | bnx2x_cl45_read(bp, phy, | |
4450 | MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2); | |
4451 | DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2); | |
62b29a5d YR |
4452 | |
4453 | bnx2x_cl45_read(bp, phy, | |
de6eae1f YR |
4454 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); |
4455 | bnx2x_cl45_read(bp, phy, | |
4456 | MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status); | |
4457 | bnx2x_cl45_read(bp, phy, | |
4458 | MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); | |
4459 | bnx2x_cl45_read(bp, phy, | |
4460 | MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); | |
62b29a5d | 4461 | |
de6eae1f YR |
4462 | DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps" |
4463 | " link_status 0x%x\n", rx_sd, pcs_status, val2); | |
4464 | /* link is up if both bit 0 of pmd_rx_sd and | |
4465 | * bit 0 of pcs_status are set, or if the autoneg bit | |
4466 | * 1 is set | |
4467 | */ | |
4468 | link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1))); | |
4469 | if (link_up) { | |
4470 | if (val2 & (1<<1)) | |
4471 | vars->line_speed = SPEED_1000; | |
4472 | else | |
4473 | vars->line_speed = SPEED_10000; | |
62b29a5d | 4474 | bnx2x_ext_phy_resolve_fc(phy, params, vars); |
de6eae1f | 4475 | } |
62b29a5d | 4476 | return link_up; |
b7737c9b | 4477 | } |
62b29a5d | 4478 | |
de6eae1f YR |
4479 | /******************************************************************/ |
4480 | /* BCM8706 PHY SECTION */ | |
4481 | /******************************************************************/ | |
4482 | static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy, | |
b7737c9b YR |
4483 | struct link_params *params, |
4484 | struct link_vars *vars) | |
4485 | { | |
de6eae1f | 4486 | u16 cnt, val; |
b7737c9b | 4487 | struct bnx2x *bp = params->bp; |
de6eae1f YR |
4488 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, |
4489 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); | |
4490 | /* HW reset */ | |
4491 | bnx2x_ext_phy_hw_reset(bp, params->port); | |
4492 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); | |
4493 | bnx2x_wait_reset_complete(bp, phy); | |
ea4e040a | 4494 | |
de6eae1f YR |
4495 | /* Wait until fw is loaded */ |
4496 | for (cnt = 0; cnt < 100; cnt++) { | |
4497 | bnx2x_cl45_read(bp, phy, | |
4498 | MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val); | |
4499 | if (val) | |
4500 | break; | |
4501 | msleep(10); | |
4502 | } | |
4503 | DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt); | |
4504 | if ((params->feature_config_flags & | |
4505 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { | |
4506 | u8 i; | |
4507 | u16 reg; | |
4508 | for (i = 0; i < 4; i++) { | |
4509 | reg = MDIO_XS_8706_REG_BANK_RX0 + | |
4510 | i*(MDIO_XS_8706_REG_BANK_RX1 - | |
4511 | MDIO_XS_8706_REG_BANK_RX0); | |
4512 | bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val); | |
4513 | /* Clear first 3 bits of the control */ | |
4514 | val &= ~0x7; | |
4515 | /* Set control bits according to configuration */ | |
4516 | val |= (phy->rx_preemphasis[i] & 0x7); | |
4517 | DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706" | |
4518 | " reg 0x%x <-- val 0x%x\n", reg, val); | |
4519 | bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val); | |
4520 | } | |
4521 | } | |
4522 | /* Force speed */ | |
4523 | if (phy->req_line_speed == SPEED_10000) { | |
4524 | DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n"); | |
ea4e040a | 4525 | |
de6eae1f YR |
4526 | bnx2x_cl45_write(bp, phy, |
4527 | MDIO_PMA_DEVAD, | |
4528 | MDIO_PMA_REG_DIGITAL_CTRL, 0x400); | |
4529 | bnx2x_cl45_write(bp, phy, | |
4530 | MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 1); | |
4531 | } else { | |
4532 | /* Force 1Gbps using autoneg with 1G advertisment */ | |
6bbca910 | 4533 | |
de6eae1f YR |
4534 | /* Allow CL37 through CL73 */ |
4535 | DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n"); | |
4536 | bnx2x_cl45_write(bp, phy, | |
4537 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); | |
6bbca910 | 4538 | |
de6eae1f YR |
4539 | /* Enable Full-Duplex advertisment on CL37 */ |
4540 | bnx2x_cl45_write(bp, phy, | |
4541 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020); | |
4542 | /* Enable CL37 AN */ | |
4543 | bnx2x_cl45_write(bp, phy, | |
4544 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); | |
4545 | /* 1G support */ | |
4546 | bnx2x_cl45_write(bp, phy, | |
4547 | MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5)); | |
6bbca910 | 4548 | |
de6eae1f YR |
4549 | /* Enable clause 73 AN */ |
4550 | bnx2x_cl45_write(bp, phy, | |
4551 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); | |
4552 | bnx2x_cl45_write(bp, phy, | |
4553 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL, | |
4554 | 0x0400); | |
4555 | bnx2x_cl45_write(bp, phy, | |
4556 | MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, | |
4557 | 0x0004); | |
4558 | } | |
4559 | bnx2x_save_bcm_spirom_ver(bp, phy, params->port); | |
4560 | return 0; | |
4561 | } | |
ea4e040a | 4562 | |
de6eae1f YR |
4563 | static u8 bnx2x_8706_read_status(struct bnx2x_phy *phy, |
4564 | struct link_params *params, | |
4565 | struct link_vars *vars) | |
4566 | { | |
4567 | return bnx2x_8706_8726_read_status(phy, params, vars); | |
4568 | } | |
6bbca910 | 4569 | |
de6eae1f YR |
4570 | /******************************************************************/ |
4571 | /* BCM8726 PHY SECTION */ | |
4572 | /******************************************************************/ | |
4573 | static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy, | |
4574 | struct link_params *params) | |
4575 | { | |
4576 | struct bnx2x *bp = params->bp; | |
4577 | DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n"); | |
4578 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001); | |
4579 | } | |
62b29a5d | 4580 | |
de6eae1f YR |
4581 | static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy, |
4582 | struct link_params *params) | |
4583 | { | |
4584 | struct bnx2x *bp = params->bp; | |
4585 | /* Need to wait 100ms after reset */ | |
4586 | msleep(100); | |
62b29a5d | 4587 | |
de6eae1f YR |
4588 | /* Micro controller re-boot */ |
4589 | bnx2x_cl45_write(bp, phy, | |
4590 | MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B); | |
62b29a5d | 4591 | |
de6eae1f YR |
4592 | /* Set soft reset */ |
4593 | bnx2x_cl45_write(bp, phy, | |
4594 | MDIO_PMA_DEVAD, | |
4595 | MDIO_PMA_REG_GEN_CTRL, | |
4596 | MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); | |
62b29a5d | 4597 | |
de6eae1f YR |
4598 | bnx2x_cl45_write(bp, phy, |
4599 | MDIO_PMA_DEVAD, | |
4600 | MDIO_PMA_REG_MISC_CTRL1, 0x0001); | |
6bbca910 | 4601 | |
de6eae1f YR |
4602 | bnx2x_cl45_write(bp, phy, |
4603 | MDIO_PMA_DEVAD, | |
4604 | MDIO_PMA_REG_GEN_CTRL, | |
4605 | MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); | |
4606 | ||
4607 | /* wait for 150ms for microcode load */ | |
4608 | msleep(150); | |
4609 | ||
4610 | /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */ | |
4611 | bnx2x_cl45_write(bp, phy, | |
4612 | MDIO_PMA_DEVAD, | |
4613 | MDIO_PMA_REG_MISC_CTRL1, 0x0000); | |
4614 | ||
4615 | msleep(200); | |
4616 | bnx2x_save_bcm_spirom_ver(bp, phy, params->port); | |
b7737c9b YR |
4617 | } |
4618 | ||
de6eae1f | 4619 | static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy, |
b7737c9b YR |
4620 | struct link_params *params, |
4621 | struct link_vars *vars) | |
4622 | { | |
4623 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
4624 | u16 val1; |
4625 | u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars); | |
62b29a5d YR |
4626 | if (link_up) { |
4627 | bnx2x_cl45_read(bp, phy, | |
de6eae1f YR |
4628 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, |
4629 | &val1); | |
4630 | if (val1 & (1<<15)) { | |
4631 | DP(NETIF_MSG_LINK, "Tx is disabled\n"); | |
4632 | link_up = 0; | |
4633 | vars->line_speed = 0; | |
4634 | } | |
62b29a5d YR |
4635 | } |
4636 | return link_up; | |
b7737c9b YR |
4637 | } |
4638 | ||
de6eae1f YR |
4639 | |
4640 | static u8 bnx2x_8726_config_init(struct bnx2x_phy *phy, | |
4641 | struct link_params *params, | |
4642 | struct link_vars *vars) | |
b7737c9b YR |
4643 | { |
4644 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
4645 | u32 val; |
4646 | u32 swap_val, swap_override, aeu_gpio_mask, offset; | |
4647 | DP(NETIF_MSG_LINK, "Initializing BCM8726\n"); | |
4648 | /* Restore normal power mode*/ | |
4649 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
4650 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); | |
b7737c9b | 4651 | |
de6eae1f YR |
4652 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, |
4653 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); | |
62b29a5d | 4654 | |
de6eae1f YR |
4655 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); |
4656 | bnx2x_wait_reset_complete(bp, phy); | |
62b29a5d | 4657 | |
de6eae1f | 4658 | bnx2x_8726_external_rom_boot(phy, params); |
62b29a5d | 4659 | |
de6eae1f YR |
4660 | /* Need to call module detected on initialization since |
4661 | the module detection triggered by actual module | |
4662 | insertion might occur before driver is loaded, and when | |
4663 | driver is loaded, it reset all registers, including the | |
4664 | transmitter */ | |
4665 | bnx2x_sfp_module_detection(phy, params); | |
62b29a5d | 4666 | |
de6eae1f YR |
4667 | if (phy->req_line_speed == SPEED_1000) { |
4668 | DP(NETIF_MSG_LINK, "Setting 1G force\n"); | |
4669 | bnx2x_cl45_write(bp, phy, | |
4670 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); | |
4671 | bnx2x_cl45_write(bp, phy, | |
4672 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); | |
4673 | bnx2x_cl45_write(bp, phy, | |
4674 | MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x5); | |
4675 | bnx2x_cl45_write(bp, phy, | |
4676 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL, | |
4677 | 0x400); | |
4678 | } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && | |
4679 | (phy->speed_cap_mask & | |
4680 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) && | |
4681 | ((phy->speed_cap_mask & | |
4682 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != | |
4683 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { | |
4684 | DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); | |
4685 | /* Set Flow control */ | |
4686 | bnx2x_ext_phy_set_pause(params, phy, vars); | |
4687 | bnx2x_cl45_write(bp, phy, | |
4688 | MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20); | |
4689 | bnx2x_cl45_write(bp, phy, | |
4690 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); | |
4691 | bnx2x_cl45_write(bp, phy, | |
4692 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020); | |
4693 | bnx2x_cl45_write(bp, phy, | |
4694 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); | |
4695 | bnx2x_cl45_write(bp, phy, | |
4696 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); | |
4697 | /* Enable RX-ALARM control to receive | |
4698 | interrupt for 1G speed change */ | |
4699 | bnx2x_cl45_write(bp, phy, | |
4700 | MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x4); | |
4701 | bnx2x_cl45_write(bp, phy, | |
4702 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL, | |
4703 | 0x400); | |
62b29a5d | 4704 | |
de6eae1f YR |
4705 | } else { /* Default 10G. Set only LASI control */ |
4706 | bnx2x_cl45_write(bp, phy, | |
4707 | MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 1); | |
7aa0711f YR |
4708 | } |
4709 | ||
de6eae1f YR |
4710 | /* Set TX PreEmphasis if needed */ |
4711 | if ((params->feature_config_flags & | |
4712 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { | |
4713 | DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x," | |
4714 | "TX_CTRL2 0x%x\n", | |
4715 | phy->tx_preemphasis[0], | |
4716 | phy->tx_preemphasis[1]); | |
4717 | bnx2x_cl45_write(bp, phy, | |
4718 | MDIO_PMA_DEVAD, | |
4719 | MDIO_PMA_REG_8726_TX_CTRL1, | |
4720 | phy->tx_preemphasis[0]); | |
c18aa15d | 4721 | |
de6eae1f YR |
4722 | bnx2x_cl45_write(bp, phy, |
4723 | MDIO_PMA_DEVAD, | |
4724 | MDIO_PMA_REG_8726_TX_CTRL2, | |
4725 | phy->tx_preemphasis[1]); | |
4726 | } | |
ab6ad5a4 | 4727 | |
de6eae1f YR |
4728 | /* Set GPIO3 to trigger SFP+ module insertion/removal */ |
4729 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, | |
4730 | MISC_REGISTERS_GPIO_INPUT_HI_Z, params->port); | |
ea4e040a | 4731 | |
de6eae1f YR |
4732 | /* The GPIO should be swapped if the swap register is set and active */ |
4733 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); | |
4734 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); | |
ea4e040a | 4735 | |
de6eae1f YR |
4736 | /* Select function upon port-swap configuration */ |
4737 | if (params->port == 0) { | |
4738 | offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0; | |
4739 | aeu_gpio_mask = (swap_val && swap_override) ? | |
4740 | AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 : | |
4741 | AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0; | |
4742 | } else { | |
4743 | offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0; | |
4744 | aeu_gpio_mask = (swap_val && swap_override) ? | |
4745 | AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 : | |
4746 | AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1; | |
ea4e040a | 4747 | } |
de6eae1f YR |
4748 | val = REG_RD(bp, offset); |
4749 | /* add GPIO3 to group */ | |
4750 | val |= aeu_gpio_mask; | |
4751 | REG_WR(bp, offset, val); | |
4752 | return 0; | |
ab6ad5a4 | 4753 | |
ea4e040a YR |
4754 | } |
4755 | ||
de6eae1f YR |
4756 | static void bnx2x_8726_link_reset(struct bnx2x_phy *phy, |
4757 | struct link_params *params) | |
2f904460 | 4758 | { |
de6eae1f YR |
4759 | struct bnx2x *bp = params->bp; |
4760 | DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port); | |
4761 | /* Set serial boot control for external load */ | |
4762 | bnx2x_cl45_write(bp, phy, | |
4763 | MDIO_PMA_DEVAD, | |
4764 | MDIO_PMA_REG_GEN_CTRL, 0x0001); | |
4765 | } | |
4766 | ||
4767 | /******************************************************************/ | |
4768 | /* BCM8727 PHY SECTION */ | |
4769 | /******************************************************************/ | |
7f02c4ad YR |
4770 | |
4771 | static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy, | |
4772 | struct link_params *params, u8 mode) | |
4773 | { | |
4774 | struct bnx2x *bp = params->bp; | |
4775 | u16 led_mode_bitmask = 0; | |
4776 | u16 gpio_pins_bitmask = 0; | |
4777 | u16 val; | |
4778 | /* Only NOC flavor requires to set the LED specifically */ | |
4779 | if (!(phy->flags & FLAGS_NOC)) | |
4780 | return; | |
4781 | switch (mode) { | |
4782 | case LED_MODE_FRONT_PANEL_OFF: | |
4783 | case LED_MODE_OFF: | |
4784 | led_mode_bitmask = 0; | |
4785 | gpio_pins_bitmask = 0x03; | |
4786 | break; | |
4787 | case LED_MODE_ON: | |
4788 | led_mode_bitmask = 0; | |
4789 | gpio_pins_bitmask = 0x02; | |
4790 | break; | |
4791 | case LED_MODE_OPER: | |
4792 | led_mode_bitmask = 0x60; | |
4793 | gpio_pins_bitmask = 0x11; | |
4794 | break; | |
4795 | } | |
4796 | bnx2x_cl45_read(bp, phy, | |
4797 | MDIO_PMA_DEVAD, | |
4798 | MDIO_PMA_REG_8727_PCS_OPT_CTRL, | |
4799 | &val); | |
4800 | val &= 0xff8f; | |
4801 | val |= led_mode_bitmask; | |
4802 | bnx2x_cl45_write(bp, phy, | |
4803 | MDIO_PMA_DEVAD, | |
4804 | MDIO_PMA_REG_8727_PCS_OPT_CTRL, | |
4805 | val); | |
4806 | bnx2x_cl45_read(bp, phy, | |
4807 | MDIO_PMA_DEVAD, | |
4808 | MDIO_PMA_REG_8727_GPIO_CTRL, | |
4809 | &val); | |
4810 | val &= 0xffe0; | |
4811 | val |= gpio_pins_bitmask; | |
4812 | bnx2x_cl45_write(bp, phy, | |
4813 | MDIO_PMA_DEVAD, | |
4814 | MDIO_PMA_REG_8727_GPIO_CTRL, | |
4815 | val); | |
4816 | } | |
de6eae1f YR |
4817 | static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy, |
4818 | struct link_params *params) { | |
4819 | u32 swap_val, swap_override; | |
4820 | u8 port; | |
4821 | /** | |
4822 | * The PHY reset is controlled by GPIO 1. Fake the port number | |
4823 | * to cancel the swap done in set_gpio() | |
2f904460 | 4824 | */ |
de6eae1f YR |
4825 | struct bnx2x *bp = params->bp; |
4826 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); | |
4827 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); | |
4828 | port = (swap_val && swap_override) ^ 1; | |
4829 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, | |
4830 | MISC_REGISTERS_GPIO_OUTPUT_LOW, port); | |
2f904460 | 4831 | } |
e10bc84d | 4832 | |
de6eae1f YR |
4833 | static u8 bnx2x_8727_config_init(struct bnx2x_phy *phy, |
4834 | struct link_params *params, | |
4835 | struct link_vars *vars) | |
ea4e040a | 4836 | { |
de6eae1f YR |
4837 | u16 tmp1, val, mod_abs; |
4838 | u16 rx_alarm_ctrl_val; | |
4839 | u16 lasi_ctrl_val; | |
ea4e040a | 4840 | struct bnx2x *bp = params->bp; |
de6eae1f | 4841 | /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */ |
ea4e040a | 4842 | |
de6eae1f YR |
4843 | bnx2x_wait_reset_complete(bp, phy); |
4844 | rx_alarm_ctrl_val = (1<<2) | (1<<5) ; | |
4845 | lasi_ctrl_val = 0x0004; | |
ea4e040a | 4846 | |
de6eae1f YR |
4847 | DP(NETIF_MSG_LINK, "Initializing BCM8727\n"); |
4848 | /* enable LASI */ | |
4849 | bnx2x_cl45_write(bp, phy, | |
4850 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL, | |
4851 | rx_alarm_ctrl_val); | |
ea4e040a | 4852 | |
de6eae1f YR |
4853 | bnx2x_cl45_write(bp, phy, |
4854 | MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, lasi_ctrl_val); | |
ea4e040a | 4855 | |
de6eae1f YR |
4856 | /* Initially configure MOD_ABS to interrupt when |
4857 | module is presence( bit 8) */ | |
4858 | bnx2x_cl45_read(bp, phy, | |
4859 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); | |
4860 | /* Set EDC off by setting OPTXLOS signal input to low | |
4861 | (bit 9). | |
4862 | When the EDC is off it locks onto a reference clock and | |
4863 | avoids becoming 'lost'.*/ | |
7f02c4ad YR |
4864 | mod_abs &= ~(1<<8); |
4865 | if (!(phy->flags & FLAGS_NOC)) | |
4866 | mod_abs &= ~(1<<9); | |
de6eae1f YR |
4867 | bnx2x_cl45_write(bp, phy, |
4868 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); | |
ea4e040a | 4869 | |
ea4e040a | 4870 | |
de6eae1f YR |
4871 | /* Make MOD_ABS give interrupt on change */ |
4872 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, | |
4873 | &val); | |
4874 | val |= (1<<12); | |
7f02c4ad YR |
4875 | if (phy->flags & FLAGS_NOC) |
4876 | val |= (3<<5); | |
b7737c9b | 4877 | |
7f02c4ad YR |
4878 | /** |
4879 | * Set 8727 GPIOs to input to allow reading from the 8727 GPIO0 | |
4880 | * status which reflect SFP+ module over-current | |
4881 | */ | |
4882 | if (!(phy->flags & FLAGS_NOC)) | |
4883 | val &= 0xff8f; /* Reset bits 4-6 */ | |
de6eae1f YR |
4884 | bnx2x_cl45_write(bp, phy, |
4885 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val); | |
ea4e040a | 4886 | |
de6eae1f YR |
4887 | bnx2x_8727_power_module(bp, phy, 1); |
4888 | ||
4889 | bnx2x_cl45_read(bp, phy, | |
4890 | MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); | |
4891 | ||
4892 | bnx2x_cl45_read(bp, phy, | |
4893 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1); | |
4894 | ||
4895 | /* Set option 1G speed */ | |
4896 | if (phy->req_line_speed == SPEED_1000) { | |
4897 | DP(NETIF_MSG_LINK, "Setting 1G force\n"); | |
4898 | bnx2x_cl45_write(bp, phy, | |
4899 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); | |
4900 | bnx2x_cl45_write(bp, phy, | |
4901 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); | |
4902 | bnx2x_cl45_read(bp, phy, | |
4903 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1); | |
4904 | DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1); | |
a22f0788 YR |
4905 | /** |
4906 | * Power down the XAUI until link is up in case of dual-media | |
4907 | * and 1G | |
4908 | */ | |
4909 | if (DUAL_MEDIA(params)) { | |
4910 | bnx2x_cl45_read(bp, phy, | |
4911 | MDIO_PMA_DEVAD, | |
4912 | MDIO_PMA_REG_8727_PCS_GP, &val); | |
4913 | val |= (3<<10); | |
4914 | bnx2x_cl45_write(bp, phy, | |
4915 | MDIO_PMA_DEVAD, | |
4916 | MDIO_PMA_REG_8727_PCS_GP, val); | |
4917 | } | |
de6eae1f YR |
4918 | } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && |
4919 | ((phy->speed_cap_mask & | |
4920 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) && | |
4921 | ((phy->speed_cap_mask & | |
4922 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != | |
4923 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { | |
4924 | ||
4925 | DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); | |
4926 | bnx2x_cl45_write(bp, phy, | |
4927 | MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0); | |
4928 | bnx2x_cl45_write(bp, phy, | |
4929 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300); | |
4930 | } else { | |
4931 | /** | |
4932 | * Since the 8727 has only single reset pin, need to set the 10G | |
4933 | * registers although it is default | |
4934 | */ | |
4935 | bnx2x_cl45_write(bp, phy, | |
4936 | MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, | |
4937 | 0x0020); | |
4938 | bnx2x_cl45_write(bp, phy, | |
4939 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100); | |
4940 | bnx2x_cl45_write(bp, phy, | |
4941 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); | |
4942 | bnx2x_cl45_write(bp, phy, | |
4943 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, | |
4944 | 0x0008); | |
ea4e040a | 4945 | } |
ea4e040a | 4946 | |
de6eae1f YR |
4947 | /* Set 2-wire transfer rate of SFP+ module EEPROM |
4948 | * to 100Khz since some DACs(direct attached cables) do | |
4949 | * not work at 400Khz. | |
4950 | */ | |
4951 | bnx2x_cl45_write(bp, phy, | |
4952 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR, | |
4953 | 0xa001); | |
b7737c9b | 4954 | |
de6eae1f YR |
4955 | /* Set TX PreEmphasis if needed */ |
4956 | if ((params->feature_config_flags & | |
4957 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { | |
4958 | DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", | |
4959 | phy->tx_preemphasis[0], | |
4960 | phy->tx_preemphasis[1]); | |
4961 | bnx2x_cl45_write(bp, phy, | |
4962 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1, | |
4963 | phy->tx_preemphasis[0]); | |
ea4e040a | 4964 | |
de6eae1f YR |
4965 | bnx2x_cl45_write(bp, phy, |
4966 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2, | |
4967 | phy->tx_preemphasis[1]); | |
4968 | } | |
ea4e040a | 4969 | |
de6eae1f | 4970 | return 0; |
ea4e040a YR |
4971 | } |
4972 | ||
de6eae1f YR |
4973 | static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy, |
4974 | struct link_params *params) | |
ea4e040a | 4975 | { |
ea4e040a | 4976 | struct bnx2x *bp = params->bp; |
de6eae1f YR |
4977 | u16 mod_abs, rx_alarm_status; |
4978 | u32 val = REG_RD(bp, params->shmem_base + | |
4979 | offsetof(struct shmem_region, dev_info. | |
4980 | port_feature_config[params->port]. | |
4981 | config)); | |
4982 | bnx2x_cl45_read(bp, phy, | |
4983 | MDIO_PMA_DEVAD, | |
4984 | MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); | |
4985 | if (mod_abs & (1<<8)) { | |
ea4e040a | 4986 | |
de6eae1f YR |
4987 | /* Module is absent */ |
4988 | DP(NETIF_MSG_LINK, "MOD_ABS indication " | |
4989 | "show module is absent\n"); | |
ea4e040a | 4990 | |
de6eae1f YR |
4991 | /* 1. Set mod_abs to detect next module |
4992 | presence event | |
4993 | 2. Set EDC off by setting OPTXLOS signal input to low | |
4994 | (bit 9). | |
4995 | When the EDC is off it locks onto a reference clock and | |
4996 | avoids becoming 'lost'.*/ | |
7f02c4ad YR |
4997 | mod_abs &= ~(1<<8); |
4998 | if (!(phy->flags & FLAGS_NOC)) | |
4999 | mod_abs &= ~(1<<9); | |
de6eae1f YR |
5000 | bnx2x_cl45_write(bp, phy, |
5001 | MDIO_PMA_DEVAD, | |
5002 | MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); | |
ea4e040a | 5003 | |
de6eae1f YR |
5004 | /* Clear RX alarm since it stays up as long as |
5005 | the mod_abs wasn't changed */ | |
5006 | bnx2x_cl45_read(bp, phy, | |
5007 | MDIO_PMA_DEVAD, | |
5008 | MDIO_PMA_REG_RX_ALARM, &rx_alarm_status); | |
ea4e040a | 5009 | |
de6eae1f YR |
5010 | } else { |
5011 | /* Module is present */ | |
5012 | DP(NETIF_MSG_LINK, "MOD_ABS indication " | |
5013 | "show module is present\n"); | |
5014 | /* First thing, disable transmitter, | |
5015 | and if the module is ok, the | |
5016 | module_detection will enable it*/ | |
ea4e040a | 5017 | |
de6eae1f YR |
5018 | /* 1. Set mod_abs to detect next module |
5019 | absent event ( bit 8) | |
5020 | 2. Restore the default polarity of the OPRXLOS signal and | |
5021 | this signal will then correctly indicate the presence or | |
5022 | absence of the Rx signal. (bit 9) */ | |
7f02c4ad YR |
5023 | mod_abs |= (1<<8); |
5024 | if (!(phy->flags & FLAGS_NOC)) | |
5025 | mod_abs |= (1<<9); | |
e10bc84d | 5026 | bnx2x_cl45_write(bp, phy, |
de6eae1f YR |
5027 | MDIO_PMA_DEVAD, |
5028 | MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); | |
ea4e040a | 5029 | |
de6eae1f YR |
5030 | /* Clear RX alarm since it stays up as long as |
5031 | the mod_abs wasn't changed. This is need to be done | |
5032 | before calling the module detection, otherwise it will clear | |
5033 | the link update alarm */ | |
5034 | bnx2x_cl45_read(bp, phy, | |
5035 | MDIO_PMA_DEVAD, | |
5036 | MDIO_PMA_REG_RX_ALARM, &rx_alarm_status); | |
ea4e040a | 5037 | |
ea4e040a | 5038 | |
de6eae1f YR |
5039 | if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == |
5040 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) | |
5041 | bnx2x_sfp_set_transmitter(bp, phy, params->port, 0); | |
5042 | ||
5043 | if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) | |
5044 | bnx2x_sfp_module_detection(phy, params); | |
5045 | else | |
5046 | DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); | |
ea4e040a | 5047 | } |
de6eae1f YR |
5048 | |
5049 | DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", | |
5050 | rx_alarm_status); | |
5051 | /* No need to check link status in case of | |
5052 | module plugged in/out */ | |
ea4e040a YR |
5053 | } |
5054 | ||
de6eae1f YR |
5055 | static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy, |
5056 | struct link_params *params, | |
5057 | struct link_vars *vars) | |
5058 | ||
ea4e040a YR |
5059 | { |
5060 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
5061 | u8 link_up = 0; |
5062 | u16 link_status = 0; | |
a22f0788 YR |
5063 | u16 rx_alarm_status, lasi_ctrl, val1; |
5064 | ||
5065 | /* If PHY is not initialized, do not check link status */ | |
5066 | bnx2x_cl45_read(bp, phy, | |
5067 | MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, | |
5068 | &lasi_ctrl); | |
5069 | if (!lasi_ctrl) | |
5070 | return 0; | |
5071 | ||
de6eae1f YR |
5072 | /* Check the LASI */ |
5073 | bnx2x_cl45_read(bp, phy, | |
5074 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, | |
5075 | &rx_alarm_status); | |
5076 | vars->line_speed = 0; | |
5077 | DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status); | |
5078 | ||
5079 | bnx2x_cl45_read(bp, phy, | |
5080 | MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1); | |
5081 | ||
5082 | DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1); | |
5083 | ||
5084 | /* Clear MSG-OUT */ | |
5085 | bnx2x_cl45_read(bp, phy, | |
5086 | MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); | |
5087 | ||
5088 | /** | |
5089 | * If a module is present and there is need to check | |
5090 | * for over current | |
5091 | */ | |
5092 | if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) { | |
5093 | /* Check over-current using 8727 GPIO0 input*/ | |
5094 | bnx2x_cl45_read(bp, phy, | |
5095 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, | |
5096 | &val1); | |
5097 | ||
5098 | if ((val1 & (1<<8)) == 0) { | |
5099 | DP(NETIF_MSG_LINK, "8727 Power fault has been detected" | |
5100 | " on port %d\n", params->port); | |
5101 | netdev_err(bp->dev, "Error: Power fault on Port %d has" | |
5102 | " been detected and the power to " | |
5103 | "that SFP+ module has been removed" | |
5104 | " to prevent failure of the card." | |
5105 | " Please remove the SFP+ module and" | |
5106 | " restart the system to clear this" | |
5107 | " error.\n", | |
5108 | params->port); | |
5109 | ||
5110 | /* | |
5111 | * Disable all RX_ALARMs except for | |
5112 | * mod_abs | |
5113 | */ | |
5114 | bnx2x_cl45_write(bp, phy, | |
5115 | MDIO_PMA_DEVAD, | |
5116 | MDIO_PMA_REG_RX_ALARM_CTRL, (1<<5)); | |
5117 | ||
5118 | bnx2x_cl45_read(bp, phy, | |
5119 | MDIO_PMA_DEVAD, | |
5120 | MDIO_PMA_REG_PHY_IDENTIFIER, &val1); | |
5121 | /* Wait for module_absent_event */ | |
5122 | val1 |= (1<<8); | |
5123 | bnx2x_cl45_write(bp, phy, | |
5124 | MDIO_PMA_DEVAD, | |
5125 | MDIO_PMA_REG_PHY_IDENTIFIER, val1); | |
5126 | /* Clear RX alarm */ | |
5127 | bnx2x_cl45_read(bp, phy, | |
5128 | MDIO_PMA_DEVAD, | |
5129 | MDIO_PMA_REG_RX_ALARM, &rx_alarm_status); | |
5130 | return 0; | |
5131 | } | |
5132 | } /* Over current check */ | |
5133 | ||
5134 | /* When module absent bit is set, check module */ | |
5135 | if (rx_alarm_status & (1<<5)) { | |
5136 | bnx2x_8727_handle_mod_abs(phy, params); | |
5137 | /* Enable all mod_abs and link detection bits */ | |
5138 | bnx2x_cl45_write(bp, phy, | |
5139 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL, | |
5140 | ((1<<5) | (1<<2))); | |
5141 | } | |
a22f0788 YR |
5142 | DP(NETIF_MSG_LINK, "Enabling 8727 TX laser if SFP is approved\n"); |
5143 | bnx2x_8727_specific_func(phy, params, ENABLE_TX); | |
de6eae1f YR |
5144 | /* If transmitter is disabled, ignore false link up indication */ |
5145 | bnx2x_cl45_read(bp, phy, | |
5146 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &val1); | |
5147 | if (val1 & (1<<15)) { | |
5148 | DP(NETIF_MSG_LINK, "Tx is disabled\n"); | |
5149 | return 0; | |
5150 | } | |
5151 | ||
5152 | bnx2x_cl45_read(bp, phy, | |
5153 | MDIO_PMA_DEVAD, | |
5154 | MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status); | |
5155 | ||
5156 | /* Bits 0..2 --> speed detected, | |
5157 | bits 13..15--> link is down */ | |
5158 | if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { | |
5159 | link_up = 1; | |
5160 | vars->line_speed = SPEED_10000; | |
5161 | } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { | |
5162 | link_up = 1; | |
5163 | vars->line_speed = SPEED_1000; | |
5164 | DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n", | |
5165 | params->port); | |
5166 | } else { | |
5167 | link_up = 0; | |
5168 | DP(NETIF_MSG_LINK, "port %x: External link is down\n", | |
5169 | params->port); | |
5170 | } | |
5171 | if (link_up) | |
5172 | bnx2x_ext_phy_resolve_fc(phy, params, vars); | |
a22f0788 YR |
5173 | |
5174 | if ((DUAL_MEDIA(params)) && | |
5175 | (phy->req_line_speed == SPEED_1000)) { | |
5176 | bnx2x_cl45_read(bp, phy, | |
5177 | MDIO_PMA_DEVAD, | |
5178 | MDIO_PMA_REG_8727_PCS_GP, &val1); | |
5179 | /** | |
5180 | * In case of dual-media board and 1G, power up the XAUI side, | |
5181 | * otherwise power it down. For 10G it is done automatically | |
5182 | */ | |
5183 | if (link_up) | |
5184 | val1 &= ~(3<<10); | |
5185 | else | |
5186 | val1 |= (3<<10); | |
5187 | bnx2x_cl45_write(bp, phy, | |
5188 | MDIO_PMA_DEVAD, | |
5189 | MDIO_PMA_REG_8727_PCS_GP, val1); | |
5190 | } | |
de6eae1f | 5191 | return link_up; |
b7737c9b | 5192 | } |
ea4e040a | 5193 | |
de6eae1f YR |
5194 | static void bnx2x_8727_link_reset(struct bnx2x_phy *phy, |
5195 | struct link_params *params) | |
b7737c9b YR |
5196 | { |
5197 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
5198 | /* Disable Transmitter */ |
5199 | bnx2x_sfp_set_transmitter(bp, phy, params->port, 0); | |
a22f0788 YR |
5200 | /* Clear LASI */ |
5201 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0); | |
5202 | ||
ea4e040a | 5203 | } |
c18aa15d | 5204 | |
de6eae1f YR |
5205 | /******************************************************************/ |
5206 | /* BCM8481/BCM84823/BCM84833 PHY SECTION */ | |
5207 | /******************************************************************/ | |
5208 | static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy, | |
5209 | struct link_params *params) | |
ea4e040a | 5210 | { |
de6eae1f YR |
5211 | u16 val, fw_ver1, fw_ver2, cnt; |
5212 | struct bnx2x *bp = params->bp; | |
ea4e040a | 5213 | |
de6eae1f YR |
5214 | /* For the 32 bits registers in 848xx, access via MDIO2ARM interface.*/ |
5215 | /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */ | |
5216 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014); | |
5217 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); | |
5218 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000); | |
5219 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300); | |
5220 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009); | |
ea4e040a | 5221 | |
de6eae1f YR |
5222 | for (cnt = 0; cnt < 100; cnt++) { |
5223 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); | |
5224 | if (val & 1) | |
5225 | break; | |
5226 | udelay(5); | |
5227 | } | |
5228 | if (cnt == 100) { | |
5229 | DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(1)\n"); | |
5230 | bnx2x_save_spirom_version(bp, params->port, 0, | |
5231 | phy->ver_addr); | |
5232 | return; | |
5233 | } | |
ea4e040a | 5234 | |
ea4e040a | 5235 | |
de6eae1f YR |
5236 | /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */ |
5237 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000); | |
5238 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); | |
5239 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A); | |
5240 | for (cnt = 0; cnt < 100; cnt++) { | |
5241 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); | |
5242 | if (val & 1) | |
5243 | break; | |
5244 | udelay(5); | |
5245 | } | |
5246 | if (cnt == 100) { | |
5247 | DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(2)\n"); | |
5248 | bnx2x_save_spirom_version(bp, params->port, 0, | |
5249 | phy->ver_addr); | |
5250 | return; | |
ea4e040a YR |
5251 | } |
5252 | ||
de6eae1f YR |
5253 | /* lower 16 bits of the register SPI_FW_STATUS */ |
5254 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1); | |
5255 | /* upper 16 bits of register SPI_FW_STATUS */ | |
5256 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2); | |
ea4e040a | 5257 | |
de6eae1f YR |
5258 | bnx2x_save_spirom_version(bp, params->port, (fw_ver2<<16) | fw_ver1, |
5259 | phy->ver_addr); | |
5260 | } | |
ea4e040a | 5261 | |
de6eae1f YR |
5262 | static void bnx2x_848xx_set_led(struct bnx2x *bp, |
5263 | struct bnx2x_phy *phy) | |
ea4e040a | 5264 | { |
de6eae1f | 5265 | u16 val; |
7846e471 | 5266 | |
de6eae1f YR |
5267 | /* PHYC_CTL_LED_CTL */ |
5268 | bnx2x_cl45_read(bp, phy, | |
5269 | MDIO_PMA_DEVAD, | |
5270 | MDIO_PMA_REG_8481_LINK_SIGNAL, &val); | |
5271 | val &= 0xFE00; | |
5272 | val |= 0x0092; | |
345b5d52 | 5273 | |
de6eae1f YR |
5274 | bnx2x_cl45_write(bp, phy, |
5275 | MDIO_PMA_DEVAD, | |
5276 | MDIO_PMA_REG_8481_LINK_SIGNAL, val); | |
ea4e040a | 5277 | |
de6eae1f YR |
5278 | bnx2x_cl45_write(bp, phy, |
5279 | MDIO_PMA_DEVAD, | |
5280 | MDIO_PMA_REG_8481_LED1_MASK, | |
5281 | 0x80); | |
ea4e040a | 5282 | |
de6eae1f YR |
5283 | bnx2x_cl45_write(bp, phy, |
5284 | MDIO_PMA_DEVAD, | |
5285 | MDIO_PMA_REG_8481_LED2_MASK, | |
5286 | 0x18); | |
ea4e040a | 5287 | |
de6eae1f YR |
5288 | bnx2x_cl45_write(bp, phy, |
5289 | MDIO_PMA_DEVAD, | |
5290 | MDIO_PMA_REG_8481_LED3_MASK, | |
5291 | 0x0040); | |
ea4e040a | 5292 | |
de6eae1f YR |
5293 | /* 'Interrupt Mask' */ |
5294 | bnx2x_cl45_write(bp, phy, | |
5295 | MDIO_AN_DEVAD, | |
5296 | 0xFFFB, 0xFFFD); | |
ea4e040a YR |
5297 | } |
5298 | ||
de6eae1f | 5299 | static u8 bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy, |
a22f0788 YR |
5300 | struct link_params *params, |
5301 | struct link_vars *vars) | |
ea4e040a | 5302 | { |
c18aa15d | 5303 | struct bnx2x *bp = params->bp; |
de6eae1f | 5304 | u16 autoneg_val, an_1000_val, an_10_100_val; |
9bffeac1 | 5305 | |
de6eae1f YR |
5306 | bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4, |
5307 | 1 << NIG_LATCH_BC_ENABLE_MI_INT); | |
ea4e040a | 5308 | |
de6eae1f YR |
5309 | bnx2x_cl45_write(bp, phy, |
5310 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000); | |
ea4e040a | 5311 | |
de6eae1f | 5312 | bnx2x_848xx_set_led(bp, phy); |
ea4e040a | 5313 | |
de6eae1f YR |
5314 | /* set 1000 speed advertisement */ |
5315 | bnx2x_cl45_read(bp, phy, | |
5316 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, | |
5317 | &an_1000_val); | |
57963ed9 | 5318 | |
de6eae1f YR |
5319 | bnx2x_ext_phy_set_pause(params, phy, vars); |
5320 | bnx2x_cl45_read(bp, phy, | |
5321 | MDIO_AN_DEVAD, | |
5322 | MDIO_AN_REG_8481_LEGACY_AN_ADV, | |
5323 | &an_10_100_val); | |
5324 | bnx2x_cl45_read(bp, phy, | |
5325 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL, | |
5326 | &autoneg_val); | |
5327 | /* Disable forced speed */ | |
5328 | autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); | |
5329 | an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8)); | |
ea4e040a | 5330 | |
de6eae1f YR |
5331 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && |
5332 | (phy->speed_cap_mask & | |
5333 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || | |
5334 | (phy->req_line_speed == SPEED_1000)) { | |
5335 | an_1000_val |= (1<<8); | |
5336 | autoneg_val |= (1<<9 | 1<<12); | |
5337 | if (phy->req_duplex == DUPLEX_FULL) | |
5338 | an_1000_val |= (1<<9); | |
5339 | DP(NETIF_MSG_LINK, "Advertising 1G\n"); | |
5340 | } else | |
5341 | an_1000_val &= ~((1<<8) | (1<<9)); | |
ea4e040a | 5342 | |
de6eae1f YR |
5343 | bnx2x_cl45_write(bp, phy, |
5344 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, | |
5345 | an_1000_val); | |
ea4e040a | 5346 | |
de6eae1f YR |
5347 | /* set 10 speed advertisement */ |
5348 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && | |
5349 | (phy->speed_cap_mask & | |
5350 | (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL | | |
5351 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) { | |
5352 | an_10_100_val |= (1<<7); | |
5353 | /* Enable autoneg and restart autoneg for legacy speeds */ | |
5354 | autoneg_val |= (1<<9 | 1<<12); | |
b7737c9b | 5355 | |
de6eae1f YR |
5356 | if (phy->req_duplex == DUPLEX_FULL) |
5357 | an_10_100_val |= (1<<8); | |
5358 | DP(NETIF_MSG_LINK, "Advertising 100M\n"); | |
5359 | } | |
5360 | /* set 10 speed advertisement */ | |
5361 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && | |
5362 | (phy->speed_cap_mask & | |
5363 | (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL | | |
5364 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) { | |
5365 | an_10_100_val |= (1<<5); | |
5366 | autoneg_val |= (1<<9 | 1<<12); | |
5367 | if (phy->req_duplex == DUPLEX_FULL) | |
5368 | an_10_100_val |= (1<<6); | |
5369 | DP(NETIF_MSG_LINK, "Advertising 10M\n"); | |
5370 | } | |
b7737c9b | 5371 | |
de6eae1f YR |
5372 | /* Only 10/100 are allowed to work in FORCE mode */ |
5373 | if (phy->req_line_speed == SPEED_100) { | |
5374 | autoneg_val |= (1<<13); | |
5375 | /* Enabled AUTO-MDIX when autoneg is disabled */ | |
5376 | bnx2x_cl45_write(bp, phy, | |
5377 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, | |
5378 | (1<<15 | 1<<9 | 7<<0)); | |
5379 | DP(NETIF_MSG_LINK, "Setting 100M force\n"); | |
5380 | } | |
5381 | if (phy->req_line_speed == SPEED_10) { | |
5382 | /* Enabled AUTO-MDIX when autoneg is disabled */ | |
5383 | bnx2x_cl45_write(bp, phy, | |
5384 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, | |
5385 | (1<<15 | 1<<9 | 7<<0)); | |
5386 | DP(NETIF_MSG_LINK, "Setting 10M force\n"); | |
5387 | } | |
b7737c9b | 5388 | |
de6eae1f YR |
5389 | bnx2x_cl45_write(bp, phy, |
5390 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV, | |
5391 | an_10_100_val); | |
b7737c9b | 5392 | |
de6eae1f YR |
5393 | if (phy->req_duplex == DUPLEX_FULL) |
5394 | autoneg_val |= (1<<8); | |
b7737c9b | 5395 | |
de6eae1f YR |
5396 | bnx2x_cl45_write(bp, phy, |
5397 | MDIO_AN_DEVAD, | |
5398 | MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val); | |
b7737c9b | 5399 | |
de6eae1f YR |
5400 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && |
5401 | (phy->speed_cap_mask & | |
5402 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || | |
5403 | (phy->req_line_speed == SPEED_10000)) { | |
5404 | DP(NETIF_MSG_LINK, "Advertising 10G\n"); | |
5405 | /* Restart autoneg for 10G*/ | |
5406 | ||
5407 | bnx2x_cl45_write(bp, phy, | |
5408 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, | |
5409 | 0x3200); | |
5410 | } else if (phy->req_line_speed != SPEED_10 && | |
5411 | phy->req_line_speed != SPEED_100) { | |
5412 | bnx2x_cl45_write(bp, phy, | |
5413 | MDIO_AN_DEVAD, | |
5414 | MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, | |
5415 | 1); | |
b7737c9b | 5416 | } |
de6eae1f YR |
5417 | /* Save spirom version */ |
5418 | bnx2x_save_848xx_spirom_version(phy, params); | |
5419 | ||
5420 | return 0; | |
b7737c9b YR |
5421 | } |
5422 | ||
de6eae1f YR |
5423 | static u8 bnx2x_8481_config_init(struct bnx2x_phy *phy, |
5424 | struct link_params *params, | |
5425 | struct link_vars *vars) | |
ea4e040a YR |
5426 | { |
5427 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
5428 | /* Restore normal power mode*/ |
5429 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
5430 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); | |
b7737c9b | 5431 | |
de6eae1f YR |
5432 | /* HW reset */ |
5433 | bnx2x_ext_phy_hw_reset(bp, params->port); | |
9bffeac1 | 5434 | bnx2x_wait_reset_complete(bp, phy); |
ab6ad5a4 | 5435 | |
de6eae1f YR |
5436 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); |
5437 | return bnx2x_848xx_cmn_config_init(phy, params, vars); | |
5438 | } | |
ea4e040a | 5439 | |
de6eae1f YR |
5440 | static u8 bnx2x_848x3_config_init(struct bnx2x_phy *phy, |
5441 | struct link_params *params, | |
5442 | struct link_vars *vars) | |
5443 | { | |
5444 | struct bnx2x *bp = params->bp; | |
7f02c4ad | 5445 | u8 port = params->port, initialize = 1; |
a22f0788 | 5446 | u16 val; |
de6eae1f | 5447 | u16 temp; |
a22f0788 YR |
5448 | u32 actual_phy_selection; |
5449 | u8 rc = 0; | |
7f02c4ad YR |
5450 | |
5451 | /* This is just for MDIO_CTL_REG_84823_MEDIA register. */ | |
5452 | ||
de6eae1f YR |
5453 | msleep(1); |
5454 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, | |
5455 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, | |
7f02c4ad | 5456 | port); |
9bffeac1 YR |
5457 | bnx2x_wait_reset_complete(bp, phy); |
5458 | /* Wait for GPHY to come out of reset */ | |
5459 | msleep(50); | |
7f02c4ad YR |
5460 | /* BCM84823 requires that XGXS links up first @ 10G for normal |
5461 | behavior */ | |
de6eae1f YR |
5462 | temp = vars->line_speed; |
5463 | vars->line_speed = SPEED_10000; | |
a22f0788 YR |
5464 | bnx2x_set_autoneg(¶ms->phy[INT_PHY], params, vars, 0); |
5465 | bnx2x_program_serdes(¶ms->phy[INT_PHY], params, vars); | |
de6eae1f | 5466 | vars->line_speed = temp; |
a22f0788 YR |
5467 | |
5468 | /* Set dual-media configuration according to configuration */ | |
5469 | ||
5470 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, | |
5471 | MDIO_CTL_REG_84823_MEDIA, &val); | |
5472 | val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | | |
5473 | MDIO_CTL_REG_84823_MEDIA_LINE_MASK | | |
5474 | MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN | | |
5475 | MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK | | |
5476 | MDIO_CTL_REG_84823_MEDIA_FIBER_1G); | |
5477 | val |= MDIO_CTL_REG_84823_CTRL_MAC_XFI | | |
5478 | MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L; | |
5479 | ||
5480 | actual_phy_selection = bnx2x_phy_selection(params); | |
5481 | ||
5482 | switch (actual_phy_selection) { | |
5483 | case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: | |
5484 | /* Do nothing. Essentialy this is like the priority copper */ | |
5485 | break; | |
5486 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: | |
5487 | val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER; | |
5488 | break; | |
5489 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: | |
5490 | val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER; | |
5491 | break; | |
5492 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: | |
5493 | /* Do nothing here. The first PHY won't be initialized at all */ | |
5494 | break; | |
5495 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: | |
5496 | val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN; | |
5497 | initialize = 0; | |
5498 | break; | |
5499 | } | |
5500 | if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000) | |
5501 | val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G; | |
5502 | ||
5503 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, | |
5504 | MDIO_CTL_REG_84823_MEDIA, val); | |
5505 | DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n", | |
5506 | params->multi_phy_config, val); | |
5507 | ||
5508 | if (initialize) | |
5509 | rc = bnx2x_848xx_cmn_config_init(phy, params, vars); | |
5510 | else | |
5511 | bnx2x_save_848xx_spirom_version(phy, params); | |
5512 | return rc; | |
de6eae1f | 5513 | } |
ea4e040a | 5514 | |
de6eae1f YR |
5515 | static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy, |
5516 | struct link_params *params, | |
5517 | struct link_vars *vars) | |
5518 | { | |
5519 | struct bnx2x *bp = params->bp; | |
5520 | u16 val, val1, val2; | |
5521 | u8 link_up = 0; | |
ea4e040a | 5522 | |
de6eae1f YR |
5523 | /* Check 10G-BaseT link status */ |
5524 | /* Check PMD signal ok */ | |
5525 | bnx2x_cl45_read(bp, phy, | |
5526 | MDIO_AN_DEVAD, 0xFFFA, &val1); | |
5527 | bnx2x_cl45_read(bp, phy, | |
5528 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL, | |
5529 | &val2); | |
5530 | DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2); | |
ea4e040a | 5531 | |
de6eae1f YR |
5532 | /* Check link 10G */ |
5533 | if (val2 & (1<<11)) { | |
ea4e040a | 5534 | vars->line_speed = SPEED_10000; |
de6eae1f YR |
5535 | link_up = 1; |
5536 | bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); | |
5537 | } else { /* Check Legacy speed link */ | |
5538 | u16 legacy_status, legacy_speed; | |
ea4e040a | 5539 | |
de6eae1f YR |
5540 | /* Enable expansion register 0x42 (Operation mode status) */ |
5541 | bnx2x_cl45_write(bp, phy, | |
5542 | MDIO_AN_DEVAD, | |
5543 | MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42); | |
ea4e040a | 5544 | |
de6eae1f YR |
5545 | /* Get legacy speed operation status */ |
5546 | bnx2x_cl45_read(bp, phy, | |
5547 | MDIO_AN_DEVAD, | |
5548 | MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, | |
5549 | &legacy_status); | |
ea4e040a | 5550 | |
de6eae1f YR |
5551 | DP(NETIF_MSG_LINK, "Legacy speed status" |
5552 | " = 0x%x\n", legacy_status); | |
5553 | link_up = ((legacy_status & (1<<11)) == (1<<11)); | |
5554 | if (link_up) { | |
5555 | legacy_speed = (legacy_status & (3<<9)); | |
5556 | if (legacy_speed == (0<<9)) | |
5557 | vars->line_speed = SPEED_10; | |
5558 | else if (legacy_speed == (1<<9)) | |
5559 | vars->line_speed = SPEED_100; | |
5560 | else if (legacy_speed == (2<<9)) | |
5561 | vars->line_speed = SPEED_1000; | |
5562 | else /* Should not happen */ | |
5563 | vars->line_speed = 0; | |
ea4e040a | 5564 | |
de6eae1f YR |
5565 | if (legacy_status & (1<<8)) |
5566 | vars->duplex = DUPLEX_FULL; | |
5567 | else | |
5568 | vars->duplex = DUPLEX_HALF; | |
ea4e040a | 5569 | |
de6eae1f YR |
5570 | DP(NETIF_MSG_LINK, "Link is up in %dMbps," |
5571 | " is_duplex_full= %d\n", vars->line_speed, | |
5572 | (vars->duplex == DUPLEX_FULL)); | |
5573 | /* Check legacy speed AN resolution */ | |
5574 | bnx2x_cl45_read(bp, phy, | |
5575 | MDIO_AN_DEVAD, | |
5576 | MDIO_AN_REG_8481_LEGACY_MII_STATUS, | |
5577 | &val); | |
5578 | if (val & (1<<5)) | |
5579 | vars->link_status |= | |
5580 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; | |
5581 | bnx2x_cl45_read(bp, phy, | |
5582 | MDIO_AN_DEVAD, | |
5583 | MDIO_AN_REG_8481_LEGACY_AN_EXPANSION, | |
5584 | &val); | |
5585 | if ((val & (1<<0)) == 0) | |
5586 | vars->link_status |= | |
5587 | LINK_STATUS_PARALLEL_DETECTION_USED; | |
ea4e040a | 5588 | } |
ea4e040a | 5589 | } |
de6eae1f YR |
5590 | if (link_up) { |
5591 | DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n", | |
5592 | vars->line_speed); | |
5593 | bnx2x_ext_phy_resolve_fc(phy, params, vars); | |
5594 | } | |
589abe3a | 5595 | |
de6eae1f | 5596 | return link_up; |
b7737c9b YR |
5597 | } |
5598 | ||
de6eae1f | 5599 | static u8 bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len) |
b7737c9b | 5600 | { |
de6eae1f YR |
5601 | u8 status = 0; |
5602 | u32 spirom_ver; | |
5603 | spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F); | |
5604 | status = bnx2x_format_ver(spirom_ver, str, len); | |
5605 | return status; | |
b7737c9b | 5606 | } |
de6eae1f YR |
5607 | |
5608 | static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy, | |
5609 | struct link_params *params) | |
b7737c9b | 5610 | { |
de6eae1f YR |
5611 | bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, |
5612 | MISC_REGISTERS_GPIO_OUTPUT_LOW, 0); | |
5613 | bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, | |
5614 | MISC_REGISTERS_GPIO_OUTPUT_LOW, 1); | |
b7737c9b | 5615 | } |
de6eae1f | 5616 | |
b7737c9b YR |
5617 | static void bnx2x_8481_link_reset(struct bnx2x_phy *phy, |
5618 | struct link_params *params) | |
5619 | { | |
5620 | bnx2x_cl45_write(params->bp, phy, | |
5621 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); | |
5622 | bnx2x_cl45_write(params->bp, phy, | |
5623 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1); | |
5624 | } | |
5625 | ||
5626 | static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy, | |
5627 | struct link_params *params) | |
5628 | { | |
5629 | struct bnx2x *bp = params->bp; | |
5630 | u8 port = params->port; | |
5631 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, | |
5632 | MISC_REGISTERS_GPIO_OUTPUT_LOW, | |
5633 | port); | |
5634 | } | |
5635 | ||
7f02c4ad YR |
5636 | static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy, |
5637 | struct link_params *params, u8 mode) | |
5638 | { | |
5639 | struct bnx2x *bp = params->bp; | |
5640 | u16 val; | |
5641 | ||
5642 | switch (mode) { | |
5643 | case LED_MODE_OFF: | |
5644 | ||
5645 | DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", params->port); | |
5646 | ||
5647 | if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == | |
5648 | SHARED_HW_CFG_LED_EXTPHY1) { | |
5649 | ||
5650 | /* Set LED masks */ | |
5651 | bnx2x_cl45_write(bp, phy, | |
5652 | MDIO_PMA_DEVAD, | |
5653 | MDIO_PMA_REG_8481_LED1_MASK, | |
5654 | 0x0); | |
5655 | ||
5656 | bnx2x_cl45_write(bp, phy, | |
5657 | MDIO_PMA_DEVAD, | |
5658 | MDIO_PMA_REG_8481_LED2_MASK, | |
5659 | 0x0); | |
5660 | ||
5661 | bnx2x_cl45_write(bp, phy, | |
5662 | MDIO_PMA_DEVAD, | |
5663 | MDIO_PMA_REG_8481_LED3_MASK, | |
5664 | 0x0); | |
5665 | ||
5666 | bnx2x_cl45_write(bp, phy, | |
5667 | MDIO_PMA_DEVAD, | |
5668 | MDIO_PMA_REG_8481_LED5_MASK, | |
5669 | 0x0); | |
5670 | ||
5671 | } else { | |
5672 | bnx2x_cl45_write(bp, phy, | |
5673 | MDIO_PMA_DEVAD, | |
5674 | MDIO_PMA_REG_8481_LED1_MASK, | |
5675 | 0x0); | |
5676 | } | |
5677 | break; | |
5678 | case LED_MODE_FRONT_PANEL_OFF: | |
5679 | ||
5680 | DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n", | |
5681 | params->port); | |
5682 | ||
5683 | if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == | |
5684 | SHARED_HW_CFG_LED_EXTPHY1) { | |
5685 | ||
5686 | /* Set LED masks */ | |
5687 | bnx2x_cl45_write(bp, phy, | |
5688 | MDIO_PMA_DEVAD, | |
5689 | MDIO_PMA_REG_8481_LED1_MASK, | |
5690 | 0x0); | |
5691 | ||
5692 | bnx2x_cl45_write(bp, phy, | |
5693 | MDIO_PMA_DEVAD, | |
5694 | MDIO_PMA_REG_8481_LED2_MASK, | |
5695 | 0x0); | |
5696 | ||
5697 | bnx2x_cl45_write(bp, phy, | |
5698 | MDIO_PMA_DEVAD, | |
5699 | MDIO_PMA_REG_8481_LED3_MASK, | |
5700 | 0x0); | |
5701 | ||
5702 | bnx2x_cl45_write(bp, phy, | |
5703 | MDIO_PMA_DEVAD, | |
5704 | MDIO_PMA_REG_8481_LED5_MASK, | |
5705 | 0x20); | |
5706 | ||
5707 | } else { | |
5708 | bnx2x_cl45_write(bp, phy, | |
5709 | MDIO_PMA_DEVAD, | |
5710 | MDIO_PMA_REG_8481_LED1_MASK, | |
5711 | 0x0); | |
5712 | } | |
5713 | break; | |
5714 | case LED_MODE_ON: | |
5715 | ||
5716 | DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", params->port); | |
5717 | ||
5718 | if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == | |
5719 | SHARED_HW_CFG_LED_EXTPHY1) { | |
5720 | /* Set control reg */ | |
5721 | bnx2x_cl45_read(bp, phy, | |
5722 | MDIO_PMA_DEVAD, | |
5723 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
5724 | &val); | |
5725 | val &= 0x8000; | |
5726 | val |= 0x2492; | |
5727 | ||
5728 | bnx2x_cl45_write(bp, phy, | |
5729 | MDIO_PMA_DEVAD, | |
5730 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
5731 | val); | |
5732 | ||
5733 | /* Set LED masks */ | |
5734 | bnx2x_cl45_write(bp, phy, | |
5735 | MDIO_PMA_DEVAD, | |
5736 | MDIO_PMA_REG_8481_LED1_MASK, | |
5737 | 0x0); | |
5738 | ||
5739 | bnx2x_cl45_write(bp, phy, | |
5740 | MDIO_PMA_DEVAD, | |
5741 | MDIO_PMA_REG_8481_LED2_MASK, | |
5742 | 0x20); | |
5743 | ||
5744 | bnx2x_cl45_write(bp, phy, | |
5745 | MDIO_PMA_DEVAD, | |
5746 | MDIO_PMA_REG_8481_LED3_MASK, | |
5747 | 0x20); | |
5748 | ||
5749 | bnx2x_cl45_write(bp, phy, | |
5750 | MDIO_PMA_DEVAD, | |
5751 | MDIO_PMA_REG_8481_LED5_MASK, | |
5752 | 0x0); | |
5753 | } else { | |
5754 | bnx2x_cl45_write(bp, phy, | |
5755 | MDIO_PMA_DEVAD, | |
5756 | MDIO_PMA_REG_8481_LED1_MASK, | |
5757 | 0x20); | |
5758 | } | |
5759 | break; | |
5760 | ||
5761 | case LED_MODE_OPER: | |
5762 | ||
5763 | DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", params->port); | |
5764 | ||
5765 | if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == | |
5766 | SHARED_HW_CFG_LED_EXTPHY1) { | |
5767 | ||
5768 | /* Set control reg */ | |
5769 | bnx2x_cl45_read(bp, phy, | |
5770 | MDIO_PMA_DEVAD, | |
5771 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
5772 | &val); | |
5773 | ||
5774 | if (!((val & | |
5775 | MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK) | |
5776 | >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)){ | |
5777 | DP(NETIF_MSG_LINK, "Seting LINK_SIGNAL\n"); | |
5778 | bnx2x_cl45_write(bp, phy, | |
5779 | MDIO_PMA_DEVAD, | |
5780 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
5781 | 0xa492); | |
5782 | } | |
5783 | ||
5784 | /* Set LED masks */ | |
5785 | bnx2x_cl45_write(bp, phy, | |
5786 | MDIO_PMA_DEVAD, | |
5787 | MDIO_PMA_REG_8481_LED1_MASK, | |
5788 | 0x10); | |
5789 | ||
5790 | bnx2x_cl45_write(bp, phy, | |
5791 | MDIO_PMA_DEVAD, | |
5792 | MDIO_PMA_REG_8481_LED2_MASK, | |
5793 | 0x80); | |
5794 | ||
5795 | bnx2x_cl45_write(bp, phy, | |
5796 | MDIO_PMA_DEVAD, | |
5797 | MDIO_PMA_REG_8481_LED3_MASK, | |
5798 | 0x98); | |
5799 | ||
5800 | bnx2x_cl45_write(bp, phy, | |
5801 | MDIO_PMA_DEVAD, | |
5802 | MDIO_PMA_REG_8481_LED5_MASK, | |
5803 | 0x40); | |
5804 | ||
5805 | } else { | |
5806 | bnx2x_cl45_write(bp, phy, | |
5807 | MDIO_PMA_DEVAD, | |
5808 | MDIO_PMA_REG_8481_LED1_MASK, | |
5809 | 0x80); | |
5810 | } | |
5811 | break; | |
5812 | } | |
5813 | } | |
de6eae1f YR |
5814 | /******************************************************************/ |
5815 | /* SFX7101 PHY SECTION */ | |
5816 | /******************************************************************/ | |
5817 | static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy, | |
5818 | struct link_params *params) | |
b7737c9b YR |
5819 | { |
5820 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
5821 | /* SFX7101_XGXS_TEST1 */ |
5822 | bnx2x_cl45_write(bp, phy, | |
5823 | MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100); | |
589abe3a EG |
5824 | } |
5825 | ||
de6eae1f YR |
5826 | static u8 bnx2x_7101_config_init(struct bnx2x_phy *phy, |
5827 | struct link_params *params, | |
5828 | struct link_vars *vars) | |
ea4e040a | 5829 | { |
de6eae1f | 5830 | u16 fw_ver1, fw_ver2, val; |
ea4e040a | 5831 | struct bnx2x *bp = params->bp; |
de6eae1f | 5832 | DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n"); |
ea4e040a | 5833 | |
de6eae1f YR |
5834 | /* Restore normal power mode*/ |
5835 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
5836 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); | |
5837 | /* HW reset */ | |
5838 | bnx2x_ext_phy_hw_reset(bp, params->port); | |
5839 | bnx2x_wait_reset_complete(bp, phy); | |
ea4e040a | 5840 | |
de6eae1f YR |
5841 | bnx2x_cl45_write(bp, phy, |
5842 | MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x1); | |
5843 | DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n"); | |
5844 | bnx2x_cl45_write(bp, phy, | |
5845 | MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3)); | |
ea4e040a | 5846 | |
de6eae1f YR |
5847 | bnx2x_ext_phy_set_pause(params, phy, vars); |
5848 | /* Restart autoneg */ | |
5849 | bnx2x_cl45_read(bp, phy, | |
5850 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val); | |
5851 | val |= 0x200; | |
5852 | bnx2x_cl45_write(bp, phy, | |
5853 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val); | |
ea4e040a | 5854 | |
de6eae1f YR |
5855 | /* Save spirom version */ |
5856 | bnx2x_cl45_read(bp, phy, | |
5857 | MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1); | |
ea4e040a | 5858 | |
de6eae1f YR |
5859 | bnx2x_cl45_read(bp, phy, |
5860 | MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2); | |
5861 | bnx2x_save_spirom_version(bp, params->port, | |
5862 | (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr); | |
5863 | return 0; | |
5864 | } | |
ea4e040a | 5865 | |
de6eae1f YR |
5866 | static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy, |
5867 | struct link_params *params, | |
5868 | struct link_vars *vars) | |
57963ed9 YR |
5869 | { |
5870 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
5871 | u8 link_up; |
5872 | u16 val1, val2; | |
5873 | bnx2x_cl45_read(bp, phy, | |
5874 | MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2); | |
5875 | bnx2x_cl45_read(bp, phy, | |
5876 | MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1); | |
5877 | DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n", | |
5878 | val2, val1); | |
5879 | bnx2x_cl45_read(bp, phy, | |
5880 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); | |
5881 | bnx2x_cl45_read(bp, phy, | |
5882 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); | |
5883 | DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n", | |
5884 | val2, val1); | |
5885 | link_up = ((val1 & 4) == 4); | |
5886 | /* if link is up | |
5887 | * print the AN outcome of the SFX7101 PHY | |
5888 | */ | |
5889 | if (link_up) { | |
5890 | bnx2x_cl45_read(bp, phy, | |
5891 | MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS, | |
5892 | &val2); | |
5893 | vars->line_speed = SPEED_10000; | |
5894 | DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n", | |
5895 | val2, (val2 & (1<<14))); | |
5896 | bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); | |
5897 | bnx2x_ext_phy_resolve_fc(phy, params, vars); | |
5898 | } | |
5899 | return link_up; | |
5900 | } | |
6c55c3cd | 5901 | |
6c55c3cd | 5902 | |
de6eae1f YR |
5903 | static u8 bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len) |
5904 | { | |
5905 | if (*len < 5) | |
5906 | return -EINVAL; | |
5907 | str[0] = (spirom_ver & 0xFF); | |
5908 | str[1] = (spirom_ver & 0xFF00) >> 8; | |
5909 | str[2] = (spirom_ver & 0xFF0000) >> 16; | |
5910 | str[3] = (spirom_ver & 0xFF000000) >> 24; | |
5911 | str[4] = '\0'; | |
5912 | *len -= 5; | |
57963ed9 YR |
5913 | return 0; |
5914 | } | |
5915 | ||
de6eae1f | 5916 | void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy) |
57963ed9 | 5917 | { |
de6eae1f | 5918 | u16 val, cnt; |
7aa0711f | 5919 | |
de6eae1f YR |
5920 | bnx2x_cl45_read(bp, phy, |
5921 | MDIO_PMA_DEVAD, | |
5922 | MDIO_PMA_REG_7101_RESET, &val); | |
57963ed9 | 5923 | |
de6eae1f YR |
5924 | for (cnt = 0; cnt < 10; cnt++) { |
5925 | msleep(50); | |
5926 | /* Writes a self-clearing reset */ | |
5927 | bnx2x_cl45_write(bp, phy, | |
5928 | MDIO_PMA_DEVAD, | |
5929 | MDIO_PMA_REG_7101_RESET, | |
5930 | (val | (1<<15))); | |
5931 | /* Wait for clear */ | |
5932 | bnx2x_cl45_read(bp, phy, | |
5933 | MDIO_PMA_DEVAD, | |
5934 | MDIO_PMA_REG_7101_RESET, &val); | |
0c786f02 | 5935 | |
de6eae1f YR |
5936 | if ((val & (1<<15)) == 0) |
5937 | break; | |
57963ed9 | 5938 | } |
57963ed9 | 5939 | } |
ea4e040a | 5940 | |
de6eae1f YR |
5941 | static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy, |
5942 | struct link_params *params) { | |
5943 | /* Low power mode is controlled by GPIO 2 */ | |
5944 | bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2, | |
5945 | MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); | |
5946 | /* The PHY reset is controlled by GPIO 1 */ | |
5947 | bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, | |
5948 | MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); | |
5949 | } | |
ea4e040a | 5950 | |
7f02c4ad YR |
5951 | static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy, |
5952 | struct link_params *params, u8 mode) | |
5953 | { | |
5954 | u16 val = 0; | |
5955 | struct bnx2x *bp = params->bp; | |
5956 | switch (mode) { | |
5957 | case LED_MODE_FRONT_PANEL_OFF: | |
5958 | case LED_MODE_OFF: | |
5959 | val = 2; | |
5960 | break; | |
5961 | case LED_MODE_ON: | |
5962 | val = 1; | |
5963 | break; | |
5964 | case LED_MODE_OPER: | |
5965 | val = 0; | |
5966 | break; | |
5967 | } | |
5968 | bnx2x_cl45_write(bp, phy, | |
5969 | MDIO_PMA_DEVAD, | |
5970 | MDIO_PMA_REG_7107_LINK_LED_CNTL, | |
5971 | val); | |
5972 | } | |
5973 | ||
de6eae1f YR |
5974 | /******************************************************************/ |
5975 | /* STATIC PHY DECLARATION */ | |
5976 | /******************************************************************/ | |
ea4e040a | 5977 | |
de6eae1f YR |
5978 | static struct bnx2x_phy phy_null = { |
5979 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN, | |
5980 | .addr = 0, | |
5981 | .flags = FLAGS_INIT_XGXS_FIRST, | |
5982 | .def_md_devad = 0, | |
5983 | .reserved = 0, | |
5984 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
5985 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
5986 | .mdio_ctrl = 0, | |
5987 | .supported = 0, | |
5988 | .media_type = ETH_PHY_NOT_PRESENT, | |
5989 | .ver_addr = 0, | |
5990 | .req_flow_ctrl = 0, | |
5991 | .req_line_speed = 0, | |
5992 | .speed_cap_mask = 0, | |
5993 | .req_duplex = 0, | |
5994 | .rsrv = 0, | |
5995 | .config_init = (config_init_t)NULL, | |
5996 | .read_status = (read_status_t)NULL, | |
5997 | .link_reset = (link_reset_t)NULL, | |
5998 | .config_loopback = (config_loopback_t)NULL, | |
5999 | .format_fw_ver = (format_fw_ver_t)NULL, | |
6000 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
6001 | .set_link_led = (set_link_led_t)NULL, |
6002 | .phy_specific_func = (phy_specific_func_t)NULL | |
de6eae1f | 6003 | }; |
ea4e040a | 6004 | |
de6eae1f YR |
6005 | static struct bnx2x_phy phy_serdes = { |
6006 | .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT, | |
6007 | .addr = 0xff, | |
6008 | .flags = 0, | |
6009 | .def_md_devad = 0, | |
6010 | .reserved = 0, | |
6011 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6012 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6013 | .mdio_ctrl = 0, | |
6014 | .supported = (SUPPORTED_10baseT_Half | | |
6015 | SUPPORTED_10baseT_Full | | |
6016 | SUPPORTED_100baseT_Half | | |
6017 | SUPPORTED_100baseT_Full | | |
6018 | SUPPORTED_1000baseT_Full | | |
6019 | SUPPORTED_2500baseX_Full | | |
6020 | SUPPORTED_TP | | |
6021 | SUPPORTED_Autoneg | | |
6022 | SUPPORTED_Pause | | |
6023 | SUPPORTED_Asym_Pause), | |
6024 | .media_type = ETH_PHY_UNSPECIFIED, | |
6025 | .ver_addr = 0, | |
6026 | .req_flow_ctrl = 0, | |
6027 | .req_line_speed = 0, | |
6028 | .speed_cap_mask = 0, | |
6029 | .req_duplex = 0, | |
6030 | .rsrv = 0, | |
6031 | .config_init = (config_init_t)bnx2x_init_serdes, | |
6032 | .read_status = (read_status_t)bnx2x_link_settings_status, | |
6033 | .link_reset = (link_reset_t)bnx2x_int_link_reset, | |
6034 | .config_loopback = (config_loopback_t)NULL, | |
6035 | .format_fw_ver = (format_fw_ver_t)NULL, | |
6036 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
6037 | .set_link_led = (set_link_led_t)NULL, |
6038 | .phy_specific_func = (phy_specific_func_t)NULL | |
de6eae1f | 6039 | }; |
b7737c9b YR |
6040 | |
6041 | static struct bnx2x_phy phy_xgxs = { | |
6042 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, | |
6043 | .addr = 0xff, | |
6044 | .flags = 0, | |
6045 | .def_md_devad = 0, | |
6046 | .reserved = 0, | |
6047 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6048 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6049 | .mdio_ctrl = 0, | |
6050 | .supported = (SUPPORTED_10baseT_Half | | |
6051 | SUPPORTED_10baseT_Full | | |
6052 | SUPPORTED_100baseT_Half | | |
6053 | SUPPORTED_100baseT_Full | | |
6054 | SUPPORTED_1000baseT_Full | | |
6055 | SUPPORTED_2500baseX_Full | | |
6056 | SUPPORTED_10000baseT_Full | | |
6057 | SUPPORTED_FIBRE | | |
6058 | SUPPORTED_Autoneg | | |
6059 | SUPPORTED_Pause | | |
6060 | SUPPORTED_Asym_Pause), | |
6061 | .media_type = ETH_PHY_UNSPECIFIED, | |
6062 | .ver_addr = 0, | |
6063 | .req_flow_ctrl = 0, | |
6064 | .req_line_speed = 0, | |
6065 | .speed_cap_mask = 0, | |
6066 | .req_duplex = 0, | |
6067 | .rsrv = 0, | |
6068 | .config_init = (config_init_t)bnx2x_init_xgxs, | |
6069 | .read_status = (read_status_t)bnx2x_link_settings_status, | |
6070 | .link_reset = (link_reset_t)bnx2x_int_link_reset, | |
6071 | .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback, | |
6072 | .format_fw_ver = (format_fw_ver_t)NULL, | |
6073 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
6074 | .set_link_led = (set_link_led_t)NULL, |
6075 | .phy_specific_func = (phy_specific_func_t)NULL | |
b7737c9b YR |
6076 | }; |
6077 | ||
6078 | static struct bnx2x_phy phy_7101 = { | |
6079 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, | |
6080 | .addr = 0xff, | |
6081 | .flags = FLAGS_FAN_FAILURE_DET_REQ, | |
6082 | .def_md_devad = 0, | |
6083 | .reserved = 0, | |
6084 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6085 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6086 | .mdio_ctrl = 0, | |
6087 | .supported = (SUPPORTED_10000baseT_Full | | |
6088 | SUPPORTED_TP | | |
6089 | SUPPORTED_Autoneg | | |
6090 | SUPPORTED_Pause | | |
6091 | SUPPORTED_Asym_Pause), | |
6092 | .media_type = ETH_PHY_BASE_T, | |
6093 | .ver_addr = 0, | |
6094 | .req_flow_ctrl = 0, | |
6095 | .req_line_speed = 0, | |
6096 | .speed_cap_mask = 0, | |
6097 | .req_duplex = 0, | |
6098 | .rsrv = 0, | |
6099 | .config_init = (config_init_t)bnx2x_7101_config_init, | |
6100 | .read_status = (read_status_t)bnx2x_7101_read_status, | |
6101 | .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, | |
6102 | .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback, | |
6103 | .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver, | |
6104 | .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset, | |
7f02c4ad | 6105 | .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led, |
a22f0788 | 6106 | .phy_specific_func = (phy_specific_func_t)NULL |
b7737c9b YR |
6107 | }; |
6108 | static struct bnx2x_phy phy_8073 = { | |
6109 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, | |
6110 | .addr = 0xff, | |
6111 | .flags = FLAGS_HW_LOCK_REQUIRED, | |
6112 | .def_md_devad = 0, | |
6113 | .reserved = 0, | |
6114 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6115 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6116 | .mdio_ctrl = 0, | |
6117 | .supported = (SUPPORTED_10000baseT_Full | | |
6118 | SUPPORTED_2500baseX_Full | | |
6119 | SUPPORTED_1000baseT_Full | | |
6120 | SUPPORTED_FIBRE | | |
6121 | SUPPORTED_Autoneg | | |
6122 | SUPPORTED_Pause | | |
6123 | SUPPORTED_Asym_Pause), | |
6124 | .media_type = ETH_PHY_UNSPECIFIED, | |
6125 | .ver_addr = 0, | |
6126 | .req_flow_ctrl = 0, | |
6127 | .req_line_speed = 0, | |
6128 | .speed_cap_mask = 0, | |
6129 | .req_duplex = 0, | |
6130 | .rsrv = 0, | |
62b29a5d | 6131 | .config_init = (config_init_t)bnx2x_8073_config_init, |
b7737c9b YR |
6132 | .read_status = (read_status_t)bnx2x_8073_read_status, |
6133 | .link_reset = (link_reset_t)bnx2x_8073_link_reset, | |
6134 | .config_loopback = (config_loopback_t)NULL, | |
6135 | .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, | |
6136 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
6137 | .set_link_led = (set_link_led_t)NULL, |
6138 | .phy_specific_func = (phy_specific_func_t)NULL | |
b7737c9b YR |
6139 | }; |
6140 | static struct bnx2x_phy phy_8705 = { | |
6141 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705, | |
6142 | .addr = 0xff, | |
6143 | .flags = FLAGS_INIT_XGXS_FIRST, | |
6144 | .def_md_devad = 0, | |
6145 | .reserved = 0, | |
6146 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6147 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6148 | .mdio_ctrl = 0, | |
6149 | .supported = (SUPPORTED_10000baseT_Full | | |
6150 | SUPPORTED_FIBRE | | |
6151 | SUPPORTED_Pause | | |
6152 | SUPPORTED_Asym_Pause), | |
6153 | .media_type = ETH_PHY_XFP_FIBER, | |
6154 | .ver_addr = 0, | |
6155 | .req_flow_ctrl = 0, | |
6156 | .req_line_speed = 0, | |
6157 | .speed_cap_mask = 0, | |
6158 | .req_duplex = 0, | |
6159 | .rsrv = 0, | |
6160 | .config_init = (config_init_t)bnx2x_8705_config_init, | |
6161 | .read_status = (read_status_t)bnx2x_8705_read_status, | |
6162 | .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, | |
6163 | .config_loopback = (config_loopback_t)NULL, | |
6164 | .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver, | |
6165 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
6166 | .set_link_led = (set_link_led_t)NULL, |
6167 | .phy_specific_func = (phy_specific_func_t)NULL | |
b7737c9b YR |
6168 | }; |
6169 | static struct bnx2x_phy phy_8706 = { | |
6170 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706, | |
6171 | .addr = 0xff, | |
6172 | .flags = FLAGS_INIT_XGXS_FIRST, | |
6173 | .def_md_devad = 0, | |
6174 | .reserved = 0, | |
6175 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6176 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6177 | .mdio_ctrl = 0, | |
6178 | .supported = (SUPPORTED_10000baseT_Full | | |
6179 | SUPPORTED_1000baseT_Full | | |
6180 | SUPPORTED_FIBRE | | |
6181 | SUPPORTED_Pause | | |
6182 | SUPPORTED_Asym_Pause), | |
6183 | .media_type = ETH_PHY_SFP_FIBER, | |
6184 | .ver_addr = 0, | |
6185 | .req_flow_ctrl = 0, | |
6186 | .req_line_speed = 0, | |
6187 | .speed_cap_mask = 0, | |
6188 | .req_duplex = 0, | |
6189 | .rsrv = 0, | |
6190 | .config_init = (config_init_t)bnx2x_8706_config_init, | |
6191 | .read_status = (read_status_t)bnx2x_8706_read_status, | |
6192 | .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, | |
6193 | .config_loopback = (config_loopback_t)NULL, | |
6194 | .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, | |
6195 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
6196 | .set_link_led = (set_link_led_t)NULL, |
6197 | .phy_specific_func = (phy_specific_func_t)NULL | |
b7737c9b YR |
6198 | }; |
6199 | ||
6200 | static struct bnx2x_phy phy_8726 = { | |
6201 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, | |
6202 | .addr = 0xff, | |
6203 | .flags = (FLAGS_HW_LOCK_REQUIRED | | |
6204 | FLAGS_INIT_XGXS_FIRST), | |
6205 | .def_md_devad = 0, | |
6206 | .reserved = 0, | |
6207 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6208 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6209 | .mdio_ctrl = 0, | |
6210 | .supported = (SUPPORTED_10000baseT_Full | | |
6211 | SUPPORTED_1000baseT_Full | | |
6212 | SUPPORTED_Autoneg | | |
6213 | SUPPORTED_FIBRE | | |
6214 | SUPPORTED_Pause | | |
6215 | SUPPORTED_Asym_Pause), | |
6216 | .media_type = ETH_PHY_SFP_FIBER, | |
6217 | .ver_addr = 0, | |
6218 | .req_flow_ctrl = 0, | |
6219 | .req_line_speed = 0, | |
6220 | .speed_cap_mask = 0, | |
6221 | .req_duplex = 0, | |
6222 | .rsrv = 0, | |
6223 | .config_init = (config_init_t)bnx2x_8726_config_init, | |
6224 | .read_status = (read_status_t)bnx2x_8726_read_status, | |
6225 | .link_reset = (link_reset_t)bnx2x_8726_link_reset, | |
6226 | .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback, | |
6227 | .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, | |
6228 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
6229 | .set_link_led = (set_link_led_t)NULL, |
6230 | .phy_specific_func = (phy_specific_func_t)NULL | |
b7737c9b YR |
6231 | }; |
6232 | ||
6233 | static struct bnx2x_phy phy_8727 = { | |
6234 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, | |
6235 | .addr = 0xff, | |
6236 | .flags = FLAGS_FAN_FAILURE_DET_REQ, | |
6237 | .def_md_devad = 0, | |
6238 | .reserved = 0, | |
6239 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6240 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6241 | .mdio_ctrl = 0, | |
6242 | .supported = (SUPPORTED_10000baseT_Full | | |
6243 | SUPPORTED_1000baseT_Full | | |
b7737c9b YR |
6244 | SUPPORTED_FIBRE | |
6245 | SUPPORTED_Pause | | |
6246 | SUPPORTED_Asym_Pause), | |
6247 | .media_type = ETH_PHY_SFP_FIBER, | |
6248 | .ver_addr = 0, | |
6249 | .req_flow_ctrl = 0, | |
6250 | .req_line_speed = 0, | |
6251 | .speed_cap_mask = 0, | |
6252 | .req_duplex = 0, | |
6253 | .rsrv = 0, | |
6254 | .config_init = (config_init_t)bnx2x_8727_config_init, | |
6255 | .read_status = (read_status_t)bnx2x_8727_read_status, | |
6256 | .link_reset = (link_reset_t)bnx2x_8727_link_reset, | |
6257 | .config_loopback = (config_loopback_t)NULL, | |
6258 | .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, | |
6259 | .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset, | |
7f02c4ad | 6260 | .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led, |
a22f0788 | 6261 | .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func |
b7737c9b YR |
6262 | }; |
6263 | static struct bnx2x_phy phy_8481 = { | |
6264 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, | |
6265 | .addr = 0xff, | |
a22f0788 YR |
6266 | .flags = FLAGS_FAN_FAILURE_DET_REQ | |
6267 | FLAGS_REARM_LATCH_SIGNAL, | |
b7737c9b YR |
6268 | .def_md_devad = 0, |
6269 | .reserved = 0, | |
6270 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6271 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6272 | .mdio_ctrl = 0, | |
6273 | .supported = (SUPPORTED_10baseT_Half | | |
6274 | SUPPORTED_10baseT_Full | | |
6275 | SUPPORTED_100baseT_Half | | |
6276 | SUPPORTED_100baseT_Full | | |
6277 | SUPPORTED_1000baseT_Full | | |
6278 | SUPPORTED_10000baseT_Full | | |
6279 | SUPPORTED_TP | | |
6280 | SUPPORTED_Autoneg | | |
6281 | SUPPORTED_Pause | | |
6282 | SUPPORTED_Asym_Pause), | |
6283 | .media_type = ETH_PHY_BASE_T, | |
6284 | .ver_addr = 0, | |
6285 | .req_flow_ctrl = 0, | |
6286 | .req_line_speed = 0, | |
6287 | .speed_cap_mask = 0, | |
6288 | .req_duplex = 0, | |
6289 | .rsrv = 0, | |
6290 | .config_init = (config_init_t)bnx2x_8481_config_init, | |
6291 | .read_status = (read_status_t)bnx2x_848xx_read_status, | |
6292 | .link_reset = (link_reset_t)bnx2x_8481_link_reset, | |
6293 | .config_loopback = (config_loopback_t)NULL, | |
6294 | .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, | |
6295 | .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset, | |
7f02c4ad | 6296 | .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, |
a22f0788 | 6297 | .phy_specific_func = (phy_specific_func_t)NULL |
b7737c9b YR |
6298 | }; |
6299 | ||
de6eae1f YR |
6300 | static struct bnx2x_phy phy_84823 = { |
6301 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823, | |
6302 | .addr = 0xff, | |
a22f0788 YR |
6303 | .flags = FLAGS_FAN_FAILURE_DET_REQ | |
6304 | FLAGS_REARM_LATCH_SIGNAL, | |
de6eae1f YR |
6305 | .def_md_devad = 0, |
6306 | .reserved = 0, | |
6307 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6308 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6309 | .mdio_ctrl = 0, | |
6310 | .supported = (SUPPORTED_10baseT_Half | | |
6311 | SUPPORTED_10baseT_Full | | |
6312 | SUPPORTED_100baseT_Half | | |
6313 | SUPPORTED_100baseT_Full | | |
6314 | SUPPORTED_1000baseT_Full | | |
6315 | SUPPORTED_10000baseT_Full | | |
6316 | SUPPORTED_TP | | |
6317 | SUPPORTED_Autoneg | | |
6318 | SUPPORTED_Pause | | |
6319 | SUPPORTED_Asym_Pause), | |
6320 | .media_type = ETH_PHY_BASE_T, | |
6321 | .ver_addr = 0, | |
6322 | .req_flow_ctrl = 0, | |
6323 | .req_line_speed = 0, | |
6324 | .speed_cap_mask = 0, | |
6325 | .req_duplex = 0, | |
6326 | .rsrv = 0, | |
6327 | .config_init = (config_init_t)bnx2x_848x3_config_init, | |
6328 | .read_status = (read_status_t)bnx2x_848xx_read_status, | |
6329 | .link_reset = (link_reset_t)bnx2x_848x3_link_reset, | |
6330 | .config_loopback = (config_loopback_t)NULL, | |
6331 | .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, | |
6332 | .hw_reset = (hw_reset_t)NULL, | |
7f02c4ad | 6333 | .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, |
a22f0788 | 6334 | .phy_specific_func = (phy_specific_func_t)NULL |
de6eae1f YR |
6335 | }; |
6336 | ||
6337 | /*****************************************************************/ | |
6338 | /* */ | |
6339 | /* Populate the phy according. Main function: bnx2x_populate_phy */ | |
6340 | /* */ | |
6341 | /*****************************************************************/ | |
6342 | ||
6343 | static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base, | |
6344 | struct bnx2x_phy *phy, u8 port, | |
6345 | u8 phy_index) | |
6346 | { | |
6347 | /* Get the 4 lanes xgxs config rx and tx */ | |
6348 | u32 rx = 0, tx = 0, i; | |
6349 | for (i = 0; i < 2; i++) { | |
6350 | /** | |
6351 | * INT_PHY and EXT_PHY1 share the same value location in the | |
6352 | * shmem. When num_phys is greater than 1, than this value | |
6353 | * applies only to EXT_PHY1 | |
6354 | */ | |
a22f0788 YR |
6355 | if (phy_index == INT_PHY || phy_index == EXT_PHY1) { |
6356 | rx = REG_RD(bp, shmem_base + | |
6357 | offsetof(struct shmem_region, | |
6358 | dev_info.port_hw_config[port].xgxs_config_rx[i<<1])); | |
6359 | ||
6360 | tx = REG_RD(bp, shmem_base + | |
6361 | offsetof(struct shmem_region, | |
6362 | dev_info.port_hw_config[port].xgxs_config_tx[i<<1])); | |
6363 | } else { | |
6364 | rx = REG_RD(bp, shmem_base + | |
6365 | offsetof(struct shmem_region, | |
6366 | dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); | |
de6eae1f | 6367 | |
a22f0788 YR |
6368 | tx = REG_RD(bp, shmem_base + |
6369 | offsetof(struct shmem_region, | |
6370 | dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); | |
6371 | } | |
de6eae1f YR |
6372 | |
6373 | phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff); | |
6374 | phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff); | |
6375 | ||
6376 | phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff); | |
6377 | phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff); | |
6378 | } | |
6379 | } | |
6380 | ||
6381 | static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base, | |
6382 | u8 phy_index, u8 port) | |
6383 | { | |
6384 | u32 ext_phy_config = 0; | |
6385 | switch (phy_index) { | |
6386 | case EXT_PHY1: | |
6387 | ext_phy_config = REG_RD(bp, shmem_base + | |
6388 | offsetof(struct shmem_region, | |
6389 | dev_info.port_hw_config[port].external_phy_config)); | |
6390 | break; | |
a22f0788 YR |
6391 | case EXT_PHY2: |
6392 | ext_phy_config = REG_RD(bp, shmem_base + | |
6393 | offsetof(struct shmem_region, | |
6394 | dev_info.port_hw_config[port].external_phy_config2)); | |
6395 | break; | |
de6eae1f YR |
6396 | default: |
6397 | DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index); | |
6398 | return -EINVAL; | |
6399 | } | |
6400 | ||
6401 | return ext_phy_config; | |
6402 | } | |
6403 | static u8 bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port, | |
6404 | struct bnx2x_phy *phy) | |
6405 | { | |
6406 | u32 phy_addr; | |
6407 | u32 chip_id; | |
6408 | u32 switch_cfg = (REG_RD(bp, shmem_base + | |
6409 | offsetof(struct shmem_region, | |
6410 | dev_info.port_feature_config[port].link_config)) & | |
6411 | PORT_FEATURE_CONNECTED_SWITCH_MASK); | |
6412 | chip_id = REG_RD(bp, MISC_REG_CHIP_NUM) << 16; | |
6413 | switch (switch_cfg) { | |
6414 | case SWITCH_CFG_1G: | |
6415 | phy_addr = REG_RD(bp, | |
6416 | NIG_REG_SERDES0_CTRL_PHY_ADDR + | |
6417 | port * 0x10); | |
6418 | *phy = phy_serdes; | |
6419 | break; | |
6420 | case SWITCH_CFG_10G: | |
6421 | phy_addr = REG_RD(bp, | |
6422 | NIG_REG_XGXS0_CTRL_PHY_ADDR + | |
6423 | port * 0x18); | |
6424 | *phy = phy_xgxs; | |
6425 | break; | |
6426 | default: | |
6427 | DP(NETIF_MSG_LINK, "Invalid switch_cfg\n"); | |
6428 | return -EINVAL; | |
6429 | } | |
6430 | phy->addr = (u8)phy_addr; | |
6431 | phy->mdio_ctrl = bnx2x_get_emac_base(bp, | |
6432 | SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH, | |
6433 | port); | |
f2e0899f DK |
6434 | if (CHIP_IS_E2(bp)) |
6435 | phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR; | |
6436 | else | |
6437 | phy->def_md_devad = DEFAULT_PHY_DEV_ADDR; | |
de6eae1f YR |
6438 | |
6439 | DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n", | |
6440 | port, phy->addr, phy->mdio_ctrl); | |
6441 | ||
6442 | bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY); | |
6443 | return 0; | |
6444 | } | |
6445 | ||
6446 | static u8 bnx2x_populate_ext_phy(struct bnx2x *bp, | |
6447 | u8 phy_index, | |
6448 | u32 shmem_base, | |
a22f0788 | 6449 | u32 shmem2_base, |
de6eae1f YR |
6450 | u8 port, |
6451 | struct bnx2x_phy *phy) | |
6452 | { | |
6453 | u32 ext_phy_config, phy_type, config2; | |
6454 | u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH; | |
6455 | ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base, | |
6456 | phy_index, port); | |
6457 | phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); | |
6458 | /* Select the phy type */ | |
6459 | switch (phy_type) { | |
6460 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: | |
6461 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED; | |
6462 | *phy = phy_8073; | |
6463 | break; | |
6464 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: | |
6465 | *phy = phy_8705; | |
6466 | break; | |
6467 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: | |
6468 | *phy = phy_8706; | |
6469 | break; | |
6470 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: | |
6471 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; | |
6472 | *phy = phy_8726; | |
6473 | break; | |
6474 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: | |
6475 | /* BCM8727_NOC => BCM8727 no over current */ | |
6476 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; | |
6477 | *phy = phy_8727; | |
6478 | phy->flags |= FLAGS_NOC; | |
6479 | break; | |
6480 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: | |
6481 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; | |
6482 | *phy = phy_8727; | |
6483 | break; | |
6484 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: | |
6485 | *phy = phy_8481; | |
6486 | break; | |
6487 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823: | |
6488 | *phy = phy_84823; | |
6489 | break; | |
6490 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: | |
6491 | *phy = phy_7101; | |
6492 | break; | |
6493 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: | |
6494 | *phy = phy_null; | |
6495 | return -EINVAL; | |
6496 | default: | |
6497 | *phy = phy_null; | |
6498 | return 0; | |
6499 | } | |
6500 | ||
6501 | phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config); | |
6502 | bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index); | |
6503 | ||
6504 | /** | |
6505 | * The shmem address of the phy version is located on different | |
6506 | * structures. In case this structure is too old, do not set | |
6507 | * the address | |
6508 | */ | |
6509 | config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region, | |
6510 | dev_info.shared_hw_config.config2)); | |
a22f0788 YR |
6511 | if (phy_index == EXT_PHY1) { |
6512 | phy->ver_addr = shmem_base + offsetof(struct shmem_region, | |
6513 | port_mb[port].ext_phy_fw_version); | |
de6eae1f YR |
6514 | |
6515 | /* Check specific mdc mdio settings */ | |
6516 | if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK) | |
6517 | mdc_mdio_access = config2 & | |
6518 | SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK; | |
a22f0788 YR |
6519 | } else { |
6520 | u32 size = REG_RD(bp, shmem2_base); | |
de6eae1f | 6521 | |
a22f0788 YR |
6522 | if (size > |
6523 | offsetof(struct shmem2_region, ext_phy_fw_version2)) { | |
6524 | phy->ver_addr = shmem2_base + | |
6525 | offsetof(struct shmem2_region, | |
6526 | ext_phy_fw_version2[port]); | |
6527 | } | |
6528 | /* Check specific mdc mdio settings */ | |
6529 | if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) | |
6530 | mdc_mdio_access = (config2 & | |
6531 | SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >> | |
6532 | (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT - | |
6533 | SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT); | |
6534 | } | |
de6eae1f YR |
6535 | phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port); |
6536 | ||
6537 | /** | |
6538 | * In case mdc/mdio_access of the external phy is different than the | |
6539 | * mdc/mdio access of the XGXS, a HW lock must be taken in each access | |
6540 | * to prevent one port interfere with another port's CL45 operations. | |
6541 | */ | |
6542 | if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH) | |
6543 | phy->flags |= FLAGS_HW_LOCK_REQUIRED; | |
6544 | DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n", | |
6545 | phy_type, port, phy_index); | |
6546 | DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n", | |
6547 | phy->addr, phy->mdio_ctrl); | |
6548 | return 0; | |
6549 | } | |
6550 | ||
6551 | static u8 bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base, | |
a22f0788 | 6552 | u32 shmem2_base, u8 port, struct bnx2x_phy *phy) |
de6eae1f YR |
6553 | { |
6554 | u8 status = 0; | |
6555 | phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN; | |
6556 | if (phy_index == INT_PHY) | |
6557 | return bnx2x_populate_int_phy(bp, shmem_base, port, phy); | |
a22f0788 | 6558 | status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base, |
de6eae1f YR |
6559 | port, phy); |
6560 | return status; | |
6561 | } | |
6562 | ||
6563 | static void bnx2x_phy_def_cfg(struct link_params *params, | |
6564 | struct bnx2x_phy *phy, | |
a22f0788 | 6565 | u8 phy_index) |
de6eae1f YR |
6566 | { |
6567 | struct bnx2x *bp = params->bp; | |
6568 | u32 link_config; | |
6569 | /* Populate the default phy configuration for MF mode */ | |
a22f0788 YR |
6570 | if (phy_index == EXT_PHY2) { |
6571 | link_config = REG_RD(bp, params->shmem_base + | |
6572 | offsetof(struct shmem_region, dev_info. | |
6573 | port_feature_config[params->port].link_config2)); | |
6574 | phy->speed_cap_mask = REG_RD(bp, params->shmem_base + | |
6575 | offsetof(struct shmem_region, dev_info. | |
6576 | port_hw_config[params->port].speed_capability_mask2)); | |
6577 | } else { | |
6578 | link_config = REG_RD(bp, params->shmem_base + | |
6579 | offsetof(struct shmem_region, dev_info. | |
6580 | port_feature_config[params->port].link_config)); | |
6581 | phy->speed_cap_mask = REG_RD(bp, params->shmem_base + | |
de6eae1f | 6582 | offsetof(struct shmem_region, dev_info. |
a22f0788 YR |
6583 | port_hw_config[params->port].speed_capability_mask)); |
6584 | } | |
6585 | DP(NETIF_MSG_LINK, "Default config phy idx %x cfg 0x%x speed_cap_mask" | |
6586 | " 0x%x\n", phy_index, link_config, phy->speed_cap_mask); | |
de6eae1f YR |
6587 | |
6588 | phy->req_duplex = DUPLEX_FULL; | |
6589 | switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { | |
6590 | case PORT_FEATURE_LINK_SPEED_10M_HALF: | |
6591 | phy->req_duplex = DUPLEX_HALF; | |
6592 | case PORT_FEATURE_LINK_SPEED_10M_FULL: | |
6593 | phy->req_line_speed = SPEED_10; | |
6594 | break; | |
6595 | case PORT_FEATURE_LINK_SPEED_100M_HALF: | |
6596 | phy->req_duplex = DUPLEX_HALF; | |
6597 | case PORT_FEATURE_LINK_SPEED_100M_FULL: | |
6598 | phy->req_line_speed = SPEED_100; | |
6599 | break; | |
6600 | case PORT_FEATURE_LINK_SPEED_1G: | |
6601 | phy->req_line_speed = SPEED_1000; | |
6602 | break; | |
6603 | case PORT_FEATURE_LINK_SPEED_2_5G: | |
6604 | phy->req_line_speed = SPEED_2500; | |
6605 | break; | |
6606 | case PORT_FEATURE_LINK_SPEED_10G_CX4: | |
6607 | phy->req_line_speed = SPEED_10000; | |
6608 | break; | |
6609 | default: | |
6610 | phy->req_line_speed = SPEED_AUTO_NEG; | |
6611 | break; | |
6612 | } | |
6613 | ||
6614 | switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) { | |
6615 | case PORT_FEATURE_FLOW_CONTROL_AUTO: | |
6616 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO; | |
6617 | break; | |
6618 | case PORT_FEATURE_FLOW_CONTROL_TX: | |
6619 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX; | |
6620 | break; | |
6621 | case PORT_FEATURE_FLOW_CONTROL_RX: | |
6622 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX; | |
6623 | break; | |
6624 | case PORT_FEATURE_FLOW_CONTROL_BOTH: | |
6625 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH; | |
6626 | break; | |
6627 | default: | |
6628 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
6629 | break; | |
6630 | } | |
6631 | } | |
6632 | ||
a22f0788 YR |
6633 | u32 bnx2x_phy_selection(struct link_params *params) |
6634 | { | |
6635 | u32 phy_config_swapped, prio_cfg; | |
6636 | u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT; | |
6637 | ||
6638 | phy_config_swapped = params->multi_phy_config & | |
6639 | PORT_HW_CFG_PHY_SWAPPED_ENABLED; | |
6640 | ||
6641 | prio_cfg = params->multi_phy_config & | |
6642 | PORT_HW_CFG_PHY_SELECTION_MASK; | |
6643 | ||
6644 | if (phy_config_swapped) { | |
6645 | switch (prio_cfg) { | |
6646 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: | |
6647 | return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY; | |
6648 | break; | |
6649 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: | |
6650 | return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY; | |
6651 | break; | |
6652 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: | |
6653 | return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; | |
6654 | break; | |
6655 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: | |
6656 | return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; | |
6657 | break; | |
6658 | } | |
6659 | } else | |
6660 | return_cfg = prio_cfg; | |
6661 | ||
6662 | return return_cfg; | |
6663 | } | |
6664 | ||
6665 | ||
de6eae1f YR |
6666 | u8 bnx2x_phy_probe(struct link_params *params) |
6667 | { | |
6668 | u8 phy_index, actual_phy_idx, link_cfg_idx; | |
a22f0788 | 6669 | u32 phy_config_swapped; |
de6eae1f YR |
6670 | struct bnx2x *bp = params->bp; |
6671 | struct bnx2x_phy *phy; | |
6672 | params->num_phys = 0; | |
6673 | DP(NETIF_MSG_LINK, "Begin phy probe\n"); | |
a22f0788 YR |
6674 | phy_config_swapped = params->multi_phy_config & |
6675 | PORT_HW_CFG_PHY_SWAPPED_ENABLED; | |
de6eae1f YR |
6676 | |
6677 | for (phy_index = INT_PHY; phy_index < MAX_PHYS; | |
6678 | phy_index++) { | |
6679 | link_cfg_idx = LINK_CONFIG_IDX(phy_index); | |
6680 | actual_phy_idx = phy_index; | |
a22f0788 YR |
6681 | if (phy_config_swapped) { |
6682 | if (phy_index == EXT_PHY1) | |
6683 | actual_phy_idx = EXT_PHY2; | |
6684 | else if (phy_index == EXT_PHY2) | |
6685 | actual_phy_idx = EXT_PHY1; | |
6686 | } | |
6687 | DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x," | |
6688 | " actual_phy_idx %x\n", phy_config_swapped, | |
6689 | phy_index, actual_phy_idx); | |
de6eae1f YR |
6690 | phy = ¶ms->phy[actual_phy_idx]; |
6691 | if (bnx2x_populate_phy(bp, phy_index, params->shmem_base, | |
a22f0788 | 6692 | params->shmem2_base, params->port, |
de6eae1f YR |
6693 | phy) != 0) { |
6694 | params->num_phys = 0; | |
6695 | DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n", | |
6696 | phy_index); | |
6697 | for (phy_index = INT_PHY; | |
6698 | phy_index < MAX_PHYS; | |
6699 | phy_index++) | |
6700 | *phy = phy_null; | |
6701 | return -EINVAL; | |
6702 | } | |
6703 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) | |
6704 | break; | |
6705 | ||
a22f0788 | 6706 | bnx2x_phy_def_cfg(params, phy, phy_index); |
de6eae1f YR |
6707 | params->num_phys++; |
6708 | } | |
6709 | ||
6710 | DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys); | |
6711 | return 0; | |
6712 | } | |
6713 | ||
de6eae1f YR |
6714 | static void set_phy_vars(struct link_params *params) |
6715 | { | |
6716 | struct bnx2x *bp = params->bp; | |
a22f0788 YR |
6717 | u8 actual_phy_idx, phy_index, link_cfg_idx; |
6718 | u8 phy_config_swapped = params->multi_phy_config & | |
6719 | PORT_HW_CFG_PHY_SWAPPED_ENABLED; | |
de6eae1f YR |
6720 | for (phy_index = INT_PHY; phy_index < params->num_phys; |
6721 | phy_index++) { | |
a22f0788 | 6722 | link_cfg_idx = LINK_CONFIG_IDX(phy_index); |
de6eae1f | 6723 | actual_phy_idx = phy_index; |
a22f0788 YR |
6724 | if (phy_config_swapped) { |
6725 | if (phy_index == EXT_PHY1) | |
6726 | actual_phy_idx = EXT_PHY2; | |
6727 | else if (phy_index == EXT_PHY2) | |
6728 | actual_phy_idx = EXT_PHY1; | |
6729 | } | |
de6eae1f | 6730 | params->phy[actual_phy_idx].req_flow_ctrl = |
a22f0788 | 6731 | params->req_flow_ctrl[link_cfg_idx]; |
de6eae1f YR |
6732 | |
6733 | params->phy[actual_phy_idx].req_line_speed = | |
a22f0788 | 6734 | params->req_line_speed[link_cfg_idx]; |
de6eae1f YR |
6735 | |
6736 | params->phy[actual_phy_idx].speed_cap_mask = | |
a22f0788 | 6737 | params->speed_cap_mask[link_cfg_idx]; |
de6eae1f YR |
6738 | |
6739 | params->phy[actual_phy_idx].req_duplex = | |
a22f0788 | 6740 | params->req_duplex[link_cfg_idx]; |
de6eae1f YR |
6741 | |
6742 | DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x," | |
6743 | " speed_cap_mask %x\n", | |
6744 | params->phy[actual_phy_idx].req_flow_ctrl, | |
6745 | params->phy[actual_phy_idx].req_line_speed, | |
6746 | params->phy[actual_phy_idx].speed_cap_mask); | |
6747 | } | |
6748 | } | |
6749 | ||
6750 | u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars) | |
6751 | { | |
6752 | struct bnx2x *bp = params->bp; | |
de6eae1f | 6753 | DP(NETIF_MSG_LINK, "Phy Initialization started\n"); |
a22f0788 YR |
6754 | DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n", |
6755 | params->req_line_speed[0], params->req_flow_ctrl[0]); | |
6756 | DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n", | |
6757 | params->req_line_speed[1], params->req_flow_ctrl[1]); | |
de6eae1f YR |
6758 | vars->link_status = 0; |
6759 | vars->phy_link_up = 0; | |
6760 | vars->link_up = 0; | |
6761 | vars->line_speed = 0; | |
6762 | vars->duplex = DUPLEX_FULL; | |
6763 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
6764 | vars->mac_type = MAC_TYPE_NONE; | |
6765 | vars->phy_flags = 0; | |
6766 | ||
6767 | /* disable attentions */ | |
6768 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, | |
6769 | (NIG_MASK_XGXS0_LINK_STATUS | | |
6770 | NIG_MASK_XGXS0_LINK10G | | |
6771 | NIG_MASK_SERDES0_LINK_STATUS | | |
6772 | NIG_MASK_MI_INT)); | |
6773 | ||
6774 | bnx2x_emac_init(params, vars); | |
6775 | ||
6776 | if (params->num_phys == 0) { | |
6777 | DP(NETIF_MSG_LINK, "No phy found for initialization !!\n"); | |
6778 | return -EINVAL; | |
6779 | } | |
6780 | set_phy_vars(params); | |
6781 | ||
6782 | DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys); | |
6783 | if (CHIP_REV_IS_FPGA(bp)) { | |
6784 | ||
6785 | vars->link_up = 1; | |
6786 | vars->line_speed = SPEED_10000; | |
6787 | vars->duplex = DUPLEX_FULL; | |
6788 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
6789 | vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD); | |
6790 | /* enable on E1.5 FPGA */ | |
6791 | if (CHIP_IS_E1H(bp)) { | |
6792 | vars->flow_ctrl |= | |
6793 | (BNX2X_FLOW_CTRL_TX | | |
6794 | BNX2X_FLOW_CTRL_RX); | |
6795 | vars->link_status |= | |
6796 | (LINK_STATUS_TX_FLOW_CONTROL_ENABLED | | |
6797 | LINK_STATUS_RX_FLOW_CONTROL_ENABLED); | |
6798 | } | |
6799 | ||
6800 | bnx2x_emac_enable(params, vars, 0); | |
f2e0899f DK |
6801 | if (!(CHIP_IS_E2(bp))) |
6802 | bnx2x_pbf_update(params, vars->flow_ctrl, | |
6803 | vars->line_speed); | |
de6eae1f YR |
6804 | /* disable drain */ |
6805 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); | |
6806 | ||
6807 | /* update shared memory */ | |
6808 | bnx2x_update_mng(params, vars->link_status); | |
6809 | ||
6810 | return 0; | |
6811 | ||
6812 | } else | |
6813 | if (CHIP_REV_IS_EMUL(bp)) { | |
6814 | ||
6815 | vars->link_up = 1; | |
6816 | vars->line_speed = SPEED_10000; | |
6817 | vars->duplex = DUPLEX_FULL; | |
6818 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
6819 | vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD); | |
6820 | ||
6821 | bnx2x_bmac_enable(params, vars, 0); | |
6822 | ||
6823 | bnx2x_pbf_update(params, vars->flow_ctrl, vars->line_speed); | |
6824 | /* Disable drain */ | |
6825 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE | |
6826 | + params->port*4, 0); | |
6827 | ||
6828 | /* update shared memory */ | |
6829 | bnx2x_update_mng(params, vars->link_status); | |
6830 | ||
6831 | return 0; | |
6832 | ||
6833 | } else | |
6834 | if (params->loopback_mode == LOOPBACK_BMAC) { | |
6835 | ||
6836 | vars->link_up = 1; | |
6837 | vars->line_speed = SPEED_10000; | |
6838 | vars->duplex = DUPLEX_FULL; | |
6839 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
6840 | vars->mac_type = MAC_TYPE_BMAC; | |
b7737c9b | 6841 | |
de6eae1f | 6842 | vars->phy_flags = PHY_XGXS_FLAG; |
b7737c9b | 6843 | |
de6eae1f | 6844 | bnx2x_xgxs_deassert(params); |
b7737c9b | 6845 | |
de6eae1f YR |
6846 | /* set bmac loopback */ |
6847 | bnx2x_bmac_enable(params, vars, 1); | |
b7737c9b | 6848 | |
de6eae1f YR |
6849 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + |
6850 | params->port*4, 0); | |
b7737c9b | 6851 | |
de6eae1f | 6852 | } else if (params->loopback_mode == LOOPBACK_EMAC) { |
b7737c9b | 6853 | |
de6eae1f YR |
6854 | vars->link_up = 1; |
6855 | vars->line_speed = SPEED_1000; | |
6856 | vars->duplex = DUPLEX_FULL; | |
6857 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
6858 | vars->mac_type = MAC_TYPE_EMAC; | |
b7737c9b | 6859 | |
de6eae1f | 6860 | vars->phy_flags = PHY_XGXS_FLAG; |
e10bc84d | 6861 | |
de6eae1f YR |
6862 | bnx2x_xgxs_deassert(params); |
6863 | /* set bmac loopback */ | |
6864 | bnx2x_emac_enable(params, vars, 1); | |
6865 | bnx2x_emac_program(params, vars); | |
6866 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + | |
6867 | params->port*4, 0); | |
b7737c9b | 6868 | |
de6eae1f YR |
6869 | } else if ((params->loopback_mode == LOOPBACK_XGXS) || |
6870 | (params->loopback_mode == LOOPBACK_EXT_PHY)) { | |
b7737c9b | 6871 | |
de6eae1f | 6872 | vars->link_up = 1; |
de6eae1f | 6873 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
a22f0788 YR |
6874 | vars->duplex = DUPLEX_FULL; |
6875 | if (params->req_line_speed[0] == SPEED_1000) { | |
6876 | vars->line_speed = SPEED_1000; | |
6877 | vars->mac_type = MAC_TYPE_EMAC; | |
6878 | } else { | |
6879 | vars->line_speed = SPEED_10000; | |
6880 | vars->mac_type = MAC_TYPE_BMAC; | |
6881 | } | |
62b29a5d | 6882 | |
de6eae1f YR |
6883 | bnx2x_xgxs_deassert(params); |
6884 | bnx2x_link_initialize(params, vars); | |
c18aa15d | 6885 | |
a22f0788 YR |
6886 | if (params->req_line_speed[0] == SPEED_1000) { |
6887 | bnx2x_emac_program(params, vars); | |
6888 | bnx2x_emac_enable(params, vars, 0); | |
6889 | } else | |
de6eae1f | 6890 | bnx2x_bmac_enable(params, vars, 0); |
c18aa15d | 6891 | |
de6eae1f YR |
6892 | if (params->loopback_mode == LOOPBACK_XGXS) { |
6893 | /* set 10G XGXS loopback */ | |
6894 | params->phy[INT_PHY].config_loopback( | |
6895 | ¶ms->phy[INT_PHY], | |
6896 | params); | |
c18aa15d | 6897 | |
de6eae1f YR |
6898 | } else { |
6899 | /* set external phy loopback */ | |
6900 | u8 phy_index; | |
6901 | for (phy_index = EXT_PHY1; | |
6902 | phy_index < params->num_phys; phy_index++) { | |
6903 | if (params->phy[phy_index].config_loopback) | |
6904 | params->phy[phy_index].config_loopback( | |
6905 | ¶ms->phy[phy_index], | |
6906 | params); | |
6907 | } | |
6908 | } | |
6909 | ||
6910 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + | |
6911 | params->port*4, 0); | |
6912 | ||
7f02c4ad YR |
6913 | bnx2x_set_led(params, vars, |
6914 | LED_MODE_OPER, vars->line_speed); | |
de6eae1f YR |
6915 | } else |
6916 | /* No loopback */ | |
6917 | { | |
6918 | if (params->switch_cfg == SWITCH_CFG_10G) | |
6919 | bnx2x_xgxs_deassert(params); | |
6920 | else | |
6921 | bnx2x_serdes_deassert(bp, params->port); | |
7f02c4ad | 6922 | |
de6eae1f YR |
6923 | bnx2x_link_initialize(params, vars); |
6924 | msleep(30); | |
6925 | bnx2x_link_int_enable(params); | |
6926 | } | |
e10bc84d YR |
6927 | return 0; |
6928 | } | |
de6eae1f YR |
6929 | u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars, |
6930 | u8 reset_ext_phy) | |
b7737c9b YR |
6931 | { |
6932 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
6933 | u8 phy_index, port = params->port; |
6934 | DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port); | |
6935 | /* disable attentions */ | |
6936 | vars->link_status = 0; | |
6937 | bnx2x_update_mng(params, vars->link_status); | |
6938 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, | |
6939 | (NIG_MASK_XGXS0_LINK_STATUS | | |
6940 | NIG_MASK_XGXS0_LINK10G | | |
6941 | NIG_MASK_SERDES0_LINK_STATUS | | |
6942 | NIG_MASK_MI_INT)); | |
b7737c9b | 6943 | |
de6eae1f YR |
6944 | /* activate nig drain */ |
6945 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); | |
b7737c9b | 6946 | |
de6eae1f YR |
6947 | /* disable nig egress interface */ |
6948 | REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0); | |
6949 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); | |
b7737c9b | 6950 | |
de6eae1f YR |
6951 | /* Stop BigMac rx */ |
6952 | bnx2x_bmac_rx_disable(bp, port); | |
b7737c9b | 6953 | |
de6eae1f YR |
6954 | /* disable emac */ |
6955 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); | |
b7737c9b | 6956 | |
de6eae1f YR |
6957 | msleep(10); |
6958 | /* The PHY reset is controled by GPIO 1 | |
6959 | * Hold it as vars low | |
6960 | */ | |
6961 | /* clear link led */ | |
7f02c4ad YR |
6962 | bnx2x_set_led(params, vars, LED_MODE_OFF, 0); |
6963 | ||
de6eae1f YR |
6964 | if (reset_ext_phy) { |
6965 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; | |
6966 | phy_index++) { | |
6967 | if (params->phy[phy_index].link_reset) | |
6968 | params->phy[phy_index].link_reset( | |
6969 | ¶ms->phy[phy_index], | |
6970 | params); | |
b7737c9b | 6971 | } |
b7737c9b YR |
6972 | } |
6973 | ||
de6eae1f YR |
6974 | if (params->phy[INT_PHY].link_reset) |
6975 | params->phy[INT_PHY].link_reset( | |
6976 | ¶ms->phy[INT_PHY], params); | |
6977 | /* reset BigMac */ | |
6978 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
6979 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); | |
b7737c9b | 6980 | |
de6eae1f YR |
6981 | /* disable nig ingress interface */ |
6982 | REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0); | |
6983 | REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0); | |
6984 | REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0); | |
6985 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); | |
6986 | vars->link_up = 0; | |
b7737c9b YR |
6987 | return 0; |
6988 | } | |
6989 | ||
de6eae1f YR |
6990 | /****************************************************************************/ |
6991 | /* Common function */ | |
6992 | /****************************************************************************/ | |
f2e0899f DK |
6993 | static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp, |
6994 | u32 shmem_base_path[], | |
6995 | u32 shmem2_base_path[], u8 phy_index, | |
6996 | u32 chip_id) | |
6bbca910 | 6997 | { |
e10bc84d YR |
6998 | struct bnx2x_phy phy[PORT_MAX]; |
6999 | struct bnx2x_phy *phy_blk[PORT_MAX]; | |
6bbca910 YR |
7000 | u16 val; |
7001 | s8 port; | |
f2e0899f | 7002 | s8 port_of_path = 0; |
6bbca910 YR |
7003 | |
7004 | /* PART1 - Reset both phys */ | |
7005 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { | |
f2e0899f DK |
7006 | u32 shmem_base, shmem2_base; |
7007 | /* In E2, same phy is using for port0 of the two paths */ | |
7008 | if (CHIP_IS_E2(bp)) { | |
7009 | shmem_base = shmem_base_path[port]; | |
7010 | shmem2_base = shmem2_base_path[port]; | |
7011 | port_of_path = 0; | |
7012 | } else { | |
7013 | shmem_base = shmem_base_path[0]; | |
7014 | shmem2_base = shmem2_base_path[0]; | |
7015 | port_of_path = port; | |
7016 | } | |
7017 | ||
6bbca910 | 7018 | /* Extract the ext phy address for the port */ |
a22f0788 | 7019 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
f2e0899f | 7020 | port_of_path, &phy[port]) != |
e10bc84d YR |
7021 | 0) { |
7022 | DP(NETIF_MSG_LINK, "populate_phy failed\n"); | |
7023 | return -EINVAL; | |
7024 | } | |
6bbca910 YR |
7025 | /* disable attentions */ |
7026 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, | |
7027 | (NIG_MASK_XGXS0_LINK_STATUS | | |
7028 | NIG_MASK_XGXS0_LINK10G | | |
7029 | NIG_MASK_SERDES0_LINK_STATUS | | |
7030 | NIG_MASK_MI_INT)); | |
7031 | ||
6bbca910 YR |
7032 | /* Need to take the phy out of low power mode in order |
7033 | to write to access its registers */ | |
7034 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
7035 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); | |
7036 | ||
7037 | /* Reset the phy */ | |
e10bc84d | 7038 | bnx2x_cl45_write(bp, &phy[port], |
6bbca910 YR |
7039 | MDIO_PMA_DEVAD, |
7040 | MDIO_PMA_REG_CTRL, | |
7041 | 1<<15); | |
7042 | } | |
7043 | ||
7044 | /* Add delay of 150ms after reset */ | |
7045 | msleep(150); | |
7046 | ||
e10bc84d YR |
7047 | if (phy[PORT_0].addr & 0x1) { |
7048 | phy_blk[PORT_0] = &(phy[PORT_1]); | |
7049 | phy_blk[PORT_1] = &(phy[PORT_0]); | |
7050 | } else { | |
7051 | phy_blk[PORT_0] = &(phy[PORT_0]); | |
7052 | phy_blk[PORT_1] = &(phy[PORT_1]); | |
7053 | } | |
7054 | ||
6bbca910 YR |
7055 | /* PART2 - Download firmware to both phys */ |
7056 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { | |
7057 | u16 fw_ver1; | |
f2e0899f DK |
7058 | if (CHIP_IS_E2(bp)) |
7059 | port_of_path = 0; | |
7060 | else | |
7061 | port_of_path = port; | |
6bbca910 | 7062 | |
f2e0899f DK |
7063 | DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", |
7064 | phy_blk[port]->addr); | |
e10bc84d | 7065 | bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], |
f2e0899f | 7066 | port_of_path); |
6bbca910 | 7067 | |
e10bc84d | 7068 | bnx2x_cl45_read(bp, phy_blk[port], |
6bbca910 YR |
7069 | MDIO_PMA_DEVAD, |
7070 | MDIO_PMA_REG_ROM_VER1, &fw_ver1); | |
16b311cc | 7071 | if (fw_ver1 == 0 || fw_ver1 == 0x4321) { |
6bbca910 | 7072 | DP(NETIF_MSG_LINK, |
16b311cc EG |
7073 | "bnx2x_8073_common_init_phy port %x:" |
7074 | "Download failed. fw version = 0x%x\n", | |
7075 | port, fw_ver1); | |
6bbca910 YR |
7076 | return -EINVAL; |
7077 | } | |
7078 | ||
7079 | /* Only set bit 10 = 1 (Tx power down) */ | |
e10bc84d | 7080 | bnx2x_cl45_read(bp, phy_blk[port], |
6bbca910 YR |
7081 | MDIO_PMA_DEVAD, |
7082 | MDIO_PMA_REG_TX_POWER_DOWN, &val); | |
7083 | ||
7084 | /* Phase1 of TX_POWER_DOWN reset */ | |
e10bc84d | 7085 | bnx2x_cl45_write(bp, phy_blk[port], |
6bbca910 YR |
7086 | MDIO_PMA_DEVAD, |
7087 | MDIO_PMA_REG_TX_POWER_DOWN, | |
7088 | (val | 1<<10)); | |
7089 | } | |
7090 | ||
7091 | /* Toggle Transmitter: Power down and then up with 600ms | |
7092 | delay between */ | |
7093 | msleep(600); | |
7094 | ||
7095 | /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */ | |
7096 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { | |
f5372251 | 7097 | /* Phase2 of POWER_DOWN_RESET */ |
6bbca910 | 7098 | /* Release bit 10 (Release Tx power down) */ |
e10bc84d | 7099 | bnx2x_cl45_read(bp, phy_blk[port], |
6bbca910 YR |
7100 | MDIO_PMA_DEVAD, |
7101 | MDIO_PMA_REG_TX_POWER_DOWN, &val); | |
7102 | ||
e10bc84d | 7103 | bnx2x_cl45_write(bp, phy_blk[port], |
6bbca910 YR |
7104 | MDIO_PMA_DEVAD, |
7105 | MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10)))); | |
7106 | msleep(15); | |
7107 | ||
7108 | /* Read modify write the SPI-ROM version select register */ | |
e10bc84d | 7109 | bnx2x_cl45_read(bp, phy_blk[port], |
6bbca910 YR |
7110 | MDIO_PMA_DEVAD, |
7111 | MDIO_PMA_REG_EDC_FFE_MAIN, &val); | |
e10bc84d | 7112 | bnx2x_cl45_write(bp, phy_blk[port], |
6bbca910 YR |
7113 | MDIO_PMA_DEVAD, |
7114 | MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12))); | |
7115 | ||
7116 | /* set GPIO2 back to LOW */ | |
7117 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
7118 | MISC_REGISTERS_GPIO_OUTPUT_LOW, port); | |
7119 | } | |
7120 | return 0; | |
6bbca910 | 7121 | } |
f2e0899f DK |
7122 | static u8 bnx2x_8726_common_init_phy(struct bnx2x *bp, |
7123 | u32 shmem_base_path[], | |
7124 | u32 shmem2_base_path[], u8 phy_index, | |
7125 | u32 chip_id) | |
de6eae1f YR |
7126 | { |
7127 | u32 val; | |
7128 | s8 port; | |
7129 | struct bnx2x_phy phy; | |
7130 | /* Use port1 because of the static port-swap */ | |
7131 | /* Enable the module detection interrupt */ | |
7132 | val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); | |
7133 | val |= ((1<<MISC_REGISTERS_GPIO_3)| | |
7134 | (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT))); | |
7135 | REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); | |
7136 | ||
7137 | bnx2x_ext_phy_hw_reset(bp, 1); | |
7138 | msleep(5); | |
7139 | for (port = 0; port < PORT_MAX; port++) { | |
f2e0899f DK |
7140 | u32 shmem_base, shmem2_base; |
7141 | ||
7142 | /* In E2, same phy is using for port0 of the two paths */ | |
7143 | if (CHIP_IS_E2(bp)) { | |
7144 | shmem_base = shmem_base_path[port]; | |
7145 | shmem2_base = shmem2_base_path[port]; | |
7146 | } else { | |
7147 | shmem_base = shmem_base_path[0]; | |
7148 | shmem2_base = shmem2_base_path[0]; | |
7149 | } | |
de6eae1f | 7150 | /* Extract the ext phy address for the port */ |
a22f0788 | 7151 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
de6eae1f YR |
7152 | port, &phy) != |
7153 | 0) { | |
7154 | DP(NETIF_MSG_LINK, "populate phy failed\n"); | |
7155 | return -EINVAL; | |
7156 | } | |
7157 | ||
7158 | /* Reset phy*/ | |
7159 | bnx2x_cl45_write(bp, &phy, | |
7160 | MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001); | |
7161 | ||
7162 | ||
7163 | /* Set fault module detected LED on */ | |
7164 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, | |
7165 | MISC_REGISTERS_GPIO_HIGH, | |
7166 | port); | |
7167 | } | |
7168 | ||
7169 | return 0; | |
7170 | } | |
f2e0899f DK |
7171 | static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp, |
7172 | u32 shmem_base_path[], | |
7173 | u32 shmem2_base_path[], u8 phy_index, | |
7174 | u32 chip_id) | |
4d295db0 | 7175 | { |
a22f0788 | 7176 | s8 port; |
4d295db0 | 7177 | u32 swap_val, swap_override; |
e10bc84d YR |
7178 | struct bnx2x_phy phy[PORT_MAX]; |
7179 | struct bnx2x_phy *phy_blk[PORT_MAX]; | |
f2e0899f | 7180 | s8 port_of_path; |
4d295db0 EG |
7181 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); |
7182 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); | |
7183 | ||
a22f0788 | 7184 | port = 1; |
4d295db0 | 7185 | |
a22f0788 YR |
7186 | bnx2x_ext_phy_hw_reset(bp, port ^ (swap_val && swap_override)); |
7187 | ||
7188 | /* Calculate the port based on port swap */ | |
7189 | port ^= (swap_val && swap_override); | |
7190 | ||
7191 | msleep(5); | |
bc7f0a05 | 7192 | |
4d295db0 | 7193 | /* PART1 - Reset both phys */ |
a22f0788 | 7194 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { |
f2e0899f DK |
7195 | u32 shmem_base, shmem2_base; |
7196 | ||
7197 | /* In E2, same phy is using for port0 of the two paths */ | |
7198 | if (CHIP_IS_E2(bp)) { | |
7199 | shmem_base = shmem_base_path[port]; | |
7200 | shmem2_base = shmem2_base_path[port]; | |
7201 | port_of_path = 0; | |
7202 | } else { | |
7203 | shmem_base = shmem_base_path[0]; | |
7204 | shmem2_base = shmem2_base_path[0]; | |
7205 | port_of_path = port; | |
7206 | } | |
7207 | ||
4d295db0 | 7208 | /* Extract the ext phy address for the port */ |
a22f0788 | 7209 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
f2e0899f | 7210 | port_of_path, &phy[port]) != |
e10bc84d YR |
7211 | 0) { |
7212 | DP(NETIF_MSG_LINK, "populate phy failed\n"); | |
7213 | return -EINVAL; | |
7214 | } | |
4d295db0 | 7215 | /* disable attentions */ |
f2e0899f DK |
7216 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + |
7217 | port_of_path*4, | |
7218 | (NIG_MASK_XGXS0_LINK_STATUS | | |
7219 | NIG_MASK_XGXS0_LINK10G | | |
7220 | NIG_MASK_SERDES0_LINK_STATUS | | |
7221 | NIG_MASK_MI_INT)); | |
4d295db0 | 7222 | |
4d295db0 EG |
7223 | |
7224 | /* Reset the phy */ | |
e10bc84d | 7225 | bnx2x_cl45_write(bp, &phy[port], |
4d295db0 EG |
7226 | MDIO_PMA_DEVAD, |
7227 | MDIO_PMA_REG_CTRL, | |
7228 | 1<<15); | |
7229 | } | |
7230 | ||
7231 | /* Add delay of 150ms after reset */ | |
7232 | msleep(150); | |
e10bc84d YR |
7233 | if (phy[PORT_0].addr & 0x1) { |
7234 | phy_blk[PORT_0] = &(phy[PORT_1]); | |
7235 | phy_blk[PORT_1] = &(phy[PORT_0]); | |
7236 | } else { | |
7237 | phy_blk[PORT_0] = &(phy[PORT_0]); | |
7238 | phy_blk[PORT_1] = &(phy[PORT_1]); | |
7239 | } | |
4d295db0 | 7240 | /* PART2 - Download firmware to both phys */ |
e10bc84d | 7241 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { |
4d295db0 | 7242 | u16 fw_ver1; |
f2e0899f DK |
7243 | if (CHIP_IS_E2(bp)) |
7244 | port_of_path = 0; | |
7245 | else | |
7246 | port_of_path = port; | |
7247 | DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", | |
7248 | phy_blk[port]->addr); | |
e10bc84d | 7249 | bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], |
f2e0899f | 7250 | port_of_path); |
e10bc84d | 7251 | bnx2x_cl45_read(bp, phy_blk[port], |
4d295db0 EG |
7252 | MDIO_PMA_DEVAD, |
7253 | MDIO_PMA_REG_ROM_VER1, &fw_ver1); | |
7254 | if (fw_ver1 == 0 || fw_ver1 == 0x4321) { | |
7255 | DP(NETIF_MSG_LINK, | |
bc7f0a05 | 7256 | "bnx2x_8727_common_init_phy port %x:" |
4d295db0 EG |
7257 | "Download failed. fw version = 0x%x\n", |
7258 | port, fw_ver1); | |
7259 | return -EINVAL; | |
7260 | } | |
4d295db0 EG |
7261 | } |
7262 | ||
4d295db0 EG |
7263 | return 0; |
7264 | } | |
7265 | ||
f2e0899f DK |
7266 | static u8 bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[], |
7267 | u32 shmem2_base_path[], u8 phy_index, | |
7268 | u32 ext_phy_type, u32 chip_id) | |
6bbca910 YR |
7269 | { |
7270 | u8 rc = 0; | |
6bbca910 YR |
7271 | |
7272 | switch (ext_phy_type) { | |
7273 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: | |
f2e0899f DK |
7274 | rc = bnx2x_8073_common_init_phy(bp, shmem_base_path, |
7275 | shmem2_base_path, | |
7276 | phy_index, chip_id); | |
6bbca910 | 7277 | break; |
4d295db0 EG |
7278 | |
7279 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: | |
7280 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: | |
f2e0899f DK |
7281 | rc = bnx2x_8727_common_init_phy(bp, shmem_base_path, |
7282 | shmem2_base_path, | |
7283 | phy_index, chip_id); | |
4d295db0 EG |
7284 | break; |
7285 | ||
589abe3a EG |
7286 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: |
7287 | /* GPIO1 affects both ports, so there's need to pull | |
7288 | it for single port alone */ | |
f2e0899f DK |
7289 | rc = bnx2x_8726_common_init_phy(bp, shmem_base_path, |
7290 | shmem2_base_path, | |
7291 | phy_index, chip_id); | |
a22f0788 YR |
7292 | break; |
7293 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: | |
7294 | rc = -EINVAL; | |
4f60dab1 | 7295 | break; |
6bbca910 YR |
7296 | default: |
7297 | DP(NETIF_MSG_LINK, | |
7298 | "bnx2x_common_init_phy: ext_phy 0x%x not required\n", | |
7299 | ext_phy_type); | |
7300 | break; | |
7301 | } | |
7302 | ||
7303 | return rc; | |
7304 | } | |
7305 | ||
f2e0899f DK |
7306 | u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[], |
7307 | u32 shmem2_base_path[], u32 chip_id) | |
a22f0788 YR |
7308 | { |
7309 | u8 rc = 0; | |
7310 | u8 phy_index; | |
7311 | u32 ext_phy_type, ext_phy_config; | |
7312 | DP(NETIF_MSG_LINK, "Begin common phy init\n"); | |
7313 | ||
7314 | if (CHIP_REV_IS_EMUL(bp)) | |
7315 | return 0; | |
7316 | ||
7317 | /* Read the ext_phy_type for arbitrary port(0) */ | |
7318 | for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; | |
7319 | phy_index++) { | |
7320 | ext_phy_config = bnx2x_get_ext_phy_config(bp, | |
f2e0899f | 7321 | shmem_base_path[0], |
a22f0788 YR |
7322 | phy_index, 0); |
7323 | ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); | |
f2e0899f DK |
7324 | rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path, |
7325 | shmem2_base_path, | |
7326 | phy_index, ext_phy_type, | |
7327 | chip_id); | |
a22f0788 YR |
7328 | } |
7329 | return rc; | |
7330 | } | |
d90d96ba | 7331 | |
a22f0788 | 7332 | u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base) |
d90d96ba YR |
7333 | { |
7334 | u8 phy_index; | |
7335 | struct bnx2x_phy phy; | |
7336 | for (phy_index = INT_PHY; phy_index < MAX_PHYS; | |
7337 | phy_index++) { | |
a22f0788 | 7338 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
d90d96ba YR |
7339 | 0, &phy) != 0) { |
7340 | DP(NETIF_MSG_LINK, "populate phy failed\n"); | |
7341 | return 0; | |
7342 | } | |
7343 | ||
7344 | if (phy.flags & FLAGS_HW_LOCK_REQUIRED) | |
7345 | return 1; | |
7346 | } | |
7347 | return 0; | |
7348 | } | |
7349 | ||
7350 | u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, | |
7351 | u32 shmem_base, | |
a22f0788 | 7352 | u32 shmem2_base, |
d90d96ba YR |
7353 | u8 port) |
7354 | { | |
7355 | u8 phy_index, fan_failure_det_req = 0; | |
7356 | struct bnx2x_phy phy; | |
7357 | for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; | |
7358 | phy_index++) { | |
a22f0788 | 7359 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
d90d96ba YR |
7360 | port, &phy) |
7361 | != 0) { | |
7362 | DP(NETIF_MSG_LINK, "populate phy failed\n"); | |
7363 | return 0; | |
7364 | } | |
7365 | fan_failure_det_req |= (phy.flags & | |
7366 | FLAGS_FAN_FAILURE_DET_REQ); | |
7367 | } | |
7368 | return fan_failure_det_req; | |
7369 | } | |
7370 | ||
7371 | void bnx2x_hw_reset_phy(struct link_params *params) | |
7372 | { | |
7373 | u8 phy_index; | |
7374 | for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; | |
7375 | phy_index++) { | |
7376 | if (params->phy[phy_index].hw_reset) { | |
7377 | params->phy[phy_index].hw_reset( | |
7378 | ¶ms->phy[phy_index], | |
7379 | params); | |
7380 | params->phy[phy_index] = phy_null; | |
7381 | } | |
7382 | } | |
7383 | } |