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bnx2x, cnic: Fix SPQ return credit
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / bnx2x / bnx2x_ethtool.c
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de0c62db
DK		 1/* bnx2x_ethtool.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2010 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17#include <linux/ethtool.h>
18#include <linux/netdevice.h>
19#include <linux/types.h>
20#include <linux/sched.h>
21#include <linux/crc32.h>
22
23
24#include "bnx2x.h"
25#include "bnx2x_cmn.h"
26#include "bnx2x_dump.h"
27
28
29static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
30{
31 struct bnx2x *bp = netdev_priv(dev);
a22f0788
YR		 32 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
33 /* Dual Media boards present all available port types */
34 cmd->supported = bp->port.supported[cfg_idx] |
35 (bp->port.supported[cfg_idx ^ 1] &
36 (SUPPORTED_TP | SUPPORTED_FIBRE));
37 cmd->advertising = bp->port.advertising[cfg_idx];
de0c62db
DK		 38
39 if ((bp->state == BNX2X_STATE_OPEN) &&
40 !(bp->flags & MF_FUNC_DIS) &&
41 (bp->link_vars.link_up)) {
42 cmd->speed = bp->link_vars.line_speed;
43 cmd->duplex = bp->link_vars.duplex;
de0c62db 44 } else {
f2e0899f 45
a22f0788
YR		 46 cmd->speed = bp->link_params.req_line_speed[cfg_idx];
47 cmd->duplex = bp->link_params.req_duplex[cfg_idx];
de0c62db 48 }
f2e0899f
DK		 49 if (IS_MF(bp)) {
50 u16 vn_max_rate = ((bp->mf_config[BP_VN(bp)] &
51 FUNC_MF_CFG_MAX_BW_MASK) >> FUNC_MF_CFG_MAX_BW_SHIFT) *
52 100;
53
54 if (vn_max_rate < cmd->speed)
55 cmd->speed = vn_max_rate;
56 }
de0c62db 57
a22f0788
YR		 58 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
59 cmd->port = PORT_TP;
60 else if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
61 cmd->port = PORT_FIBRE;
62 else
63 BNX2X_ERR("XGXS PHY Failure detected\n");
64
de0c62db
DK		 65 cmd->phy_address = bp->mdio.prtad;
66 cmd->transceiver = XCVR_INTERNAL;
67
a22f0788 68 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
de0c62db
DK		 69 cmd->autoneg = AUTONEG_ENABLE;
70 else
71 cmd->autoneg = AUTONEG_DISABLE;
72
73 cmd->maxtxpkt = 0;
74 cmd->maxrxpkt = 0;
75
76 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
77 DP_LEVEL " supported 0x%x advertising 0x%x speed %d\n"
78 DP_LEVEL " duplex %d port %d phy_address %d transceiver %d\n"
79 DP_LEVEL " autoneg %d maxtxpkt %d maxrxpkt %d\n",
80 cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
81 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
82 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
83
84 return 0;
85}
86
87static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
88{
89 struct bnx2x *bp = netdev_priv(dev);
a22f0788 90 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
de0c62db 91
fb3bff17 92 if (IS_MF(bp))
de0c62db
DK		 93 return 0;
94
95 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
96 DP_LEVEL " supported 0x%x advertising 0x%x speed %d\n"
97 DP_LEVEL " duplex %d port %d phy_address %d transceiver %d\n"
98 DP_LEVEL " autoneg %d maxtxpkt %d maxrxpkt %d\n",
99 cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
100 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
101 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
102
a22f0788
YR		 103 cfg_idx = bnx2x_get_link_cfg_idx(bp);
104 old_multi_phy_config = bp->link_params.multi_phy_config;
105 switch (cmd->port) {
106 case PORT_TP:
107 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
108 break; /* no port change */
109
110 if (!(bp->port.supported[0] & SUPPORTED_TP ||
111 bp->port.supported[1] & SUPPORTED_TP)) {
112 DP(NETIF_MSG_LINK, "Unsupported port type\n");
113 return -EINVAL;
114 }
115 bp->link_params.multi_phy_config &=
116 ~PORT_HW_CFG_PHY_SELECTION_MASK;
117 if (bp->link_params.multi_phy_config &
118 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
119 bp->link_params.multi_phy_config |=
120 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
121 else
122 bp->link_params.multi_phy_config |=
123 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
124 break;
125 case PORT_FIBRE:
126 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
127 break; /* no port change */
128
129 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
130 bp->port.supported[1] & SUPPORTED_FIBRE)) {
131 DP(NETIF_MSG_LINK, "Unsupported port type\n");
132 return -EINVAL;
133 }
134 bp->link_params.multi_phy_config &=
135 ~PORT_HW_CFG_PHY_SELECTION_MASK;
136 if (bp->link_params.multi_phy_config &
137 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
138 bp->link_params.multi_phy_config |=
139 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
140 else
141 bp->link_params.multi_phy_config |=
142 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
143 break;
144 default:
145 DP(NETIF_MSG_LINK, "Unsupported port type\n");
146 return -EINVAL;
147 }
148 /* Save new config in case command complete successuly */
149 new_multi_phy_config = bp->link_params.multi_phy_config;
150 /* Get the new cfg_idx */
151 cfg_idx = bnx2x_get_link_cfg_idx(bp);
152 /* Restore old config in case command failed */
153 bp->link_params.multi_phy_config = old_multi_phy_config;
154 DP(NETIF_MSG_LINK, "cfg_idx = %x\n", cfg_idx);
155
de0c62db 156 if (cmd->autoneg == AUTONEG_ENABLE) {
a22f0788 157 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
de0c62db
DK		 158 DP(NETIF_MSG_LINK, "Autoneg not supported\n");
159 return -EINVAL;
160 }
161
162 /* advertise the requested speed and duplex if supported */
a22f0788 163 cmd->advertising &= bp->port.supported[cfg_idx];
de0c62db 164
a22f0788
YR		 165 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
166 bp->link_params.req_duplex[cfg_idx] = DUPLEX_FULL;
167 bp->port.advertising[cfg_idx] |= (ADVERTISED_Autoneg |
de0c62db
DK		 168 cmd->advertising);
169
170 } else { /* forced speed */
171 /* advertise the requested speed and duplex if supported */
a22f0788
YR		 172 u32 speed = cmd->speed;
173 speed |= (cmd->speed_hi << 16);
174 switch (speed) {
de0c62db
DK		 175 case SPEED_10:
176 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 177 if (!(bp->port.supported[cfg_idx] &
de0c62db
DK		 178 SUPPORTED_10baseT_Full)) {
179 DP(NETIF_MSG_LINK,
180 "10M full not supported\n");
181 return -EINVAL;
182 }
183
184 advertising = (ADVERTISED_10baseT_Full |
185 ADVERTISED_TP);
186 } else {
a22f0788 187 if (!(bp->port.supported[cfg_idx] &
de0c62db
DK		 188 SUPPORTED_10baseT_Half)) {
189 DP(NETIF_MSG_LINK,
190 "10M half not supported\n");
191 return -EINVAL;
192 }
193
194 advertising = (ADVERTISED_10baseT_Half |
195 ADVERTISED_TP);
196 }
197 break;
198
199 case SPEED_100:
200 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 201 if (!(bp->port.supported[cfg_idx] &
de0c62db
DK		 202 SUPPORTED_100baseT_Full)) {
203 DP(NETIF_MSG_LINK,
204 "100M full not supported\n");
205 return -EINVAL;
206 }
207
208 advertising = (ADVERTISED_100baseT_Full |
209 ADVERTISED_TP);
210 } else {
a22f0788 211 if (!(bp->port.supported[cfg_idx] &
de0c62db
DK		 212 SUPPORTED_100baseT_Half)) {
213 DP(NETIF_MSG_LINK,
214 "100M half not supported\n");
215 return -EINVAL;
216 }
217
218 advertising = (ADVERTISED_100baseT_Half |
219 ADVERTISED_TP);
220 }
221 break;
222
223 case SPEED_1000:
224 if (cmd->duplex != DUPLEX_FULL) {
225 DP(NETIF_MSG_LINK, "1G half not supported\n");
226 return -EINVAL;
227 }
228
a22f0788
YR		 229 if (!(bp->port.supported[cfg_idx] &
230 SUPPORTED_1000baseT_Full)) {
de0c62db
DK		 231 DP(NETIF_MSG_LINK, "1G full not supported\n");
232 return -EINVAL;
233 }
234
235 advertising = (ADVERTISED_1000baseT_Full |
236 ADVERTISED_TP);
237 break;
238
239 case SPEED_2500:
240 if (cmd->duplex != DUPLEX_FULL) {
241 DP(NETIF_MSG_LINK,
242 "2.5G half not supported\n");
243 return -EINVAL;
244 }
245
a22f0788
YR		 246 if (!(bp->port.supported[cfg_idx]
247 & SUPPORTED_2500baseX_Full)) {
de0c62db
DK		 248 DP(NETIF_MSG_LINK,
249 "2.5G full not supported\n");
250 return -EINVAL;
251 }
252
253 advertising = (ADVERTISED_2500baseX_Full |
254 ADVERTISED_TP);
255 break;
256
257 case SPEED_10000:
258 if (cmd->duplex != DUPLEX_FULL) {
259 DP(NETIF_MSG_LINK, "10G half not supported\n");
260 return -EINVAL;
261 }
262
a22f0788
YR		 263 if (!(bp->port.supported[cfg_idx]
264 & SUPPORTED_10000baseT_Full)) {
de0c62db
DK		 265 DP(NETIF_MSG_LINK, "10G full not supported\n");
266 return -EINVAL;
267 }
268
269 advertising = (ADVERTISED_10000baseT_Full |
270 ADVERTISED_FIBRE);
271 break;
272
273 default:
a22f0788 274 DP(NETIF_MSG_LINK, "Unsupported speed %d\n", speed);
de0c62db
DK		 275 return -EINVAL;
276 }
277
a22f0788
YR		 278 bp->link_params.req_line_speed[cfg_idx] = speed;
279 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
280 bp->port.advertising[cfg_idx] = advertising;
de0c62db
DK		 281 }
282
283 DP(NETIF_MSG_LINK, "req_line_speed %d\n"
284 DP_LEVEL " req_duplex %d advertising 0x%x\n",
a22f0788
YR		 285 bp->link_params.req_line_speed[cfg_idx],
286 bp->link_params.req_duplex[cfg_idx],
287 bp->port.advertising[cfg_idx]);
de0c62db 288
a22f0788
YR		 289 /* Set new config */
290 bp->link_params.multi_phy_config = new_multi_phy_config;
de0c62db
DK		 291 if (netif_running(dev)) {
292 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
293 bnx2x_link_set(bp);
294 }
295
296 return 0;
297}
298
299#define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
300#define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
f2e0899f 301#define IS_E2_ONLINE(info) (((info) & RI_E2_ONLINE) == RI_E2_ONLINE)
de0c62db
DK		 302
303static int bnx2x_get_regs_len(struct net_device *dev)
304{
305 struct bnx2x *bp = netdev_priv(dev);
306 int regdump_len = 0;
307 int i;
308
309 if (CHIP_IS_E1(bp)) {
310 for (i = 0; i < REGS_COUNT; i++)
311 if (IS_E1_ONLINE(reg_addrs[i].info))
312 regdump_len += reg_addrs[i].size;
313
314 for (i = 0; i < WREGS_COUNT_E1; i++)
315 if (IS_E1_ONLINE(wreg_addrs_e1[i].info))
316 regdump_len += wreg_addrs_e1[i].size *
317 (1 + wreg_addrs_e1[i].read_regs_count);
318
f2e0899f 319 } else if (CHIP_IS_E1H(bp)) {
de0c62db
DK		 320 for (i = 0; i < REGS_COUNT; i++)
321 if (IS_E1H_ONLINE(reg_addrs[i].info))
322 regdump_len += reg_addrs[i].size;
323
324 for (i = 0; i < WREGS_COUNT_E1H; i++)
325 if (IS_E1H_ONLINE(wreg_addrs_e1h[i].info))
326 regdump_len += wreg_addrs_e1h[i].size *
327 (1 + wreg_addrs_e1h[i].read_regs_count);
f2e0899f
DK		 328 } else if (CHIP_IS_E2(bp)) {
329 for (i = 0; i < REGS_COUNT; i++)
330 if (IS_E2_ONLINE(reg_addrs[i].info))
331 regdump_len += reg_addrs[i].size;
332
333 for (i = 0; i < WREGS_COUNT_E2; i++)
334 if (IS_E2_ONLINE(wreg_addrs_e2[i].info))
335 regdump_len += wreg_addrs_e2[i].size *
336 (1 + wreg_addrs_e2[i].read_regs_count);
de0c62db
DK		 337 }
338 regdump_len *= 4;
339 regdump_len += sizeof(struct dump_hdr);
340
341 return regdump_len;
342}
343
f2e0899f
DK		 344static inline void bnx2x_read_pages_regs_e2(struct bnx2x *bp, u32 *p)
345{
346 u32 i, j, k, n;
347
348 for (i = 0; i < PAGE_MODE_VALUES_E2; i++) {
349 for (j = 0; j < PAGE_WRITE_REGS_E2; j++) {
350 REG_WR(bp, page_write_regs_e2[j], page_vals_e2[i]);
351 for (k = 0; k < PAGE_READ_REGS_E2; k++)
352 if (IS_E2_ONLINE(page_read_regs_e2[k].info))
353 for (n = 0; n <
354 page_read_regs_e2[k].size; n++)
355 *p++ = REG_RD(bp,
356 page_read_regs_e2[k].addr + n*4);
357 }
358 }
359}
360
de0c62db
DK		 361static void bnx2x_get_regs(struct net_device *dev,
362 struct ethtool_regs *regs, void *_p)
363{
364 u32 *p = _p, i, j;
365 struct bnx2x *bp = netdev_priv(dev);
366 struct dump_hdr dump_hdr = {0};
367
368 regs->version = 0;
369 memset(p, 0, regs->len);
370
371 if (!netif_running(bp->dev))
372 return;
373
374 dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
375 dump_hdr.dump_sign = dump_sign_all;
376 dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
377 dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
378 dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
379 dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
f2e0899f
DK		 380
381 if (CHIP_IS_E1(bp))
382 dump_hdr.info = RI_E1_ONLINE;
383 else if (CHIP_IS_E1H(bp))
384 dump_hdr.info = RI_E1H_ONLINE;
385 else if (CHIP_IS_E2(bp))
386 dump_hdr.info = RI_E2_ONLINE |
387 (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP);
de0c62db
DK		 388
389 memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
390 p += dump_hdr.hdr_size + 1;
391
392 if (CHIP_IS_E1(bp)) {
393 for (i = 0; i < REGS_COUNT; i++)
394 if (IS_E1_ONLINE(reg_addrs[i].info))
395 for (j = 0; j < reg_addrs[i].size; j++)
396 *p++ = REG_RD(bp,
397 reg_addrs[i].addr + j*4);
398
f2e0899f 399 } else if (CHIP_IS_E1H(bp)) {
de0c62db
DK		 400 for (i = 0; i < REGS_COUNT; i++)
401 if (IS_E1H_ONLINE(reg_addrs[i].info))
402 for (j = 0; j < reg_addrs[i].size; j++)
403 *p++ = REG_RD(bp,
404 reg_addrs[i].addr + j*4);
f2e0899f
DK		 405
406 } else if (CHIP_IS_E2(bp)) {
407 for (i = 0; i < REGS_COUNT; i++)
408 if (IS_E2_ONLINE(reg_addrs[i].info))
409 for (j = 0; j < reg_addrs[i].size; j++)
410 *p++ = REG_RD(bp,
411 reg_addrs[i].addr + j*4);
412
413 bnx2x_read_pages_regs_e2(bp, p);
de0c62db
DK		 414 }
415}
416
f2e0899f 417#define PHY_FW_VER_LEN 20
de0c62db
DK		 418
419static void bnx2x_get_drvinfo(struct net_device *dev,
420 struct ethtool_drvinfo *info)
421{
422 struct bnx2x *bp = netdev_priv(dev);
423 u8 phy_fw_ver[PHY_FW_VER_LEN];
424
425 strcpy(info->driver, DRV_MODULE_NAME);
426 strcpy(info->version, DRV_MODULE_VERSION);
427
428 phy_fw_ver[0] = '\0';
429 if (bp->port.pmf) {
430 bnx2x_acquire_phy_lock(bp);
431 bnx2x_get_ext_phy_fw_version(&bp->link_params,
432 (bp->state != BNX2X_STATE_CLOSED),
433 phy_fw_ver, PHY_FW_VER_LEN);
434 bnx2x_release_phy_lock(bp);
435 }
436
437 strncpy(info->fw_version, bp->fw_ver, 32);
438 snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
439 "bc %d.%d.%d%s%s",
440 (bp->common.bc_ver & 0xff0000) >> 16,
441 (bp->common.bc_ver & 0xff00) >> 8,
442 (bp->common.bc_ver & 0xff),
443 ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
444 strcpy(info->bus_info, pci_name(bp->pdev));
445 info->n_stats = BNX2X_NUM_STATS;
446 info->testinfo_len = BNX2X_NUM_TESTS;
447 info->eedump_len = bp->common.flash_size;
448 info->regdump_len = bnx2x_get_regs_len(dev);
449}
450
451static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
452{
453 struct bnx2x *bp = netdev_priv(dev);
454
455 if (bp->flags & NO_WOL_FLAG) {
456 wol->supported = 0;
457 wol->wolopts = 0;
458 } else {
459 wol->supported = WAKE_MAGIC;
460 if (bp->wol)
461 wol->wolopts = WAKE_MAGIC;
462 else
463 wol->wolopts = 0;
464 }
465 memset(&wol->sopass, 0, sizeof(wol->sopass));
466}
467
468static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
469{
470 struct bnx2x *bp = netdev_priv(dev);
471
472 if (wol->wolopts & ~WAKE_MAGIC)
473 return -EINVAL;
474
475 if (wol->wolopts & WAKE_MAGIC) {
476 if (bp->flags & NO_WOL_FLAG)
477 return -EINVAL;
478
479 bp->wol = 1;
480 } else
481 bp->wol = 0;
482
483 return 0;
484}
485
486static u32 bnx2x_get_msglevel(struct net_device *dev)
487{
488 struct bnx2x *bp = netdev_priv(dev);
489
490 return bp->msg_enable;
491}
492
493static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
494{
495 struct bnx2x *bp = netdev_priv(dev);
496
497 if (capable(CAP_NET_ADMIN))
498 bp->msg_enable = level;
499}
500
501static int bnx2x_nway_reset(struct net_device *dev)
502{
503 struct bnx2x *bp = netdev_priv(dev);
504
505 if (!bp->port.pmf)
506 return 0;
507
508 if (netif_running(dev)) {
509 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
510 bnx2x_link_set(bp);
511 }
512
513 return 0;
514}
515
516static u32 bnx2x_get_link(struct net_device *dev)
517{
518 struct bnx2x *bp = netdev_priv(dev);
519
f2e0899f 520 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
de0c62db
DK		 521 return 0;
522
523 return bp->link_vars.link_up;
524}
525
526static int bnx2x_get_eeprom_len(struct net_device *dev)
527{
528 struct bnx2x *bp = netdev_priv(dev);
529
530 return bp->common.flash_size;
531}
532
533static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
534{
535 int port = BP_PORT(bp);
536 int count, i;
537 u32 val = 0;
538
539 /* adjust timeout for emulation/FPGA */
540 count = NVRAM_TIMEOUT_COUNT;
541 if (CHIP_REV_IS_SLOW(bp))
542 count *= 100;
543
544 /* request access to nvram interface */
545 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
546 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
547
548 for (i = 0; i < count*10; i++) {
549 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
550 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
551 break;
552
553 udelay(5);
554 }
555
556 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
557 DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n");
558 return -EBUSY;
559 }
560
561 return 0;
562}
563
564static int bnx2x_release_nvram_lock(struct bnx2x *bp)
565{
566 int port = BP_PORT(bp);
567 int count, i;
568 u32 val = 0;
569
570 /* adjust timeout for emulation/FPGA */
571 count = NVRAM_TIMEOUT_COUNT;
572 if (CHIP_REV_IS_SLOW(bp))
573 count *= 100;
574
575 /* relinquish nvram interface */
576 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
577 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
578
579 for (i = 0; i < count*10; i++) {
580 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
581 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
582 break;
583
584 udelay(5);
585 }
586
587 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
588 DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n");
589 return -EBUSY;
590 }
591
592 return 0;
593}
594
595static void bnx2x_enable_nvram_access(struct bnx2x *bp)
596{
597 u32 val;
598
599 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
600
601 /* enable both bits, even on read */
602 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
603 (val | MCPR_NVM_ACCESS_ENABLE_EN |
604 MCPR_NVM_ACCESS_ENABLE_WR_EN));
605}
606
607static void bnx2x_disable_nvram_access(struct bnx2x *bp)
608{
609 u32 val;
610
611 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
612
613 /* disable both bits, even after read */
614 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
615 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
616 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
617}
618
619static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
620 u32 cmd_flags)
621{
622 int count, i, rc;
623 u32 val;
624
625 /* build the command word */
626 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
627
628 /* need to clear DONE bit separately */
629 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
630
631 /* address of the NVRAM to read from */
632 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
633 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
634
635 /* issue a read command */
636 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
637
638 /* adjust timeout for emulation/FPGA */
639 count = NVRAM_TIMEOUT_COUNT;
640 if (CHIP_REV_IS_SLOW(bp))
641 count *= 100;
642
643 /* wait for completion */
644 *ret_val = 0;
645 rc = -EBUSY;
646 for (i = 0; i < count; i++) {
647 udelay(5);
648 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
649
650 if (val & MCPR_NVM_COMMAND_DONE) {
651 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
652 /* we read nvram data in cpu order
653 * but ethtool sees it as an array of bytes
654 * converting to big-endian will do the work */
655 *ret_val = cpu_to_be32(val);
656 rc = 0;
657 break;
658 }
659 }
660
661 return rc;
662}
663
664static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
665 int buf_size)
666{
667 int rc;
668 u32 cmd_flags;
669 __be32 val;
670
671 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
672 DP(BNX2X_MSG_NVM,
673 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
674 offset, buf_size);
675 return -EINVAL;
676 }
677
678 if (offset + buf_size > bp->common.flash_size) {
679 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
680 " buf_size (0x%x) > flash_size (0x%x)\n",
681 offset, buf_size, bp->common.flash_size);
682 return -EINVAL;
683 }
684
685 /* request access to nvram interface */
686 rc = bnx2x_acquire_nvram_lock(bp);
687 if (rc)
688 return rc;
689
690 /* enable access to nvram interface */
691 bnx2x_enable_nvram_access(bp);
692
693 /* read the first word(s) */
694 cmd_flags = MCPR_NVM_COMMAND_FIRST;
695 while ((buf_size > sizeof(u32)) && (rc == 0)) {
696 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
697 memcpy(ret_buf, &val, 4);
698
699 /* advance to the next dword */
700 offset += sizeof(u32);
701 ret_buf += sizeof(u32);
702 buf_size -= sizeof(u32);
703 cmd_flags = 0;
704 }
705
706 if (rc == 0) {
707 cmd_flags |= MCPR_NVM_COMMAND_LAST;
708 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
709 memcpy(ret_buf, &val, 4);
710 }
711
712 /* disable access to nvram interface */
713 bnx2x_disable_nvram_access(bp);
714 bnx2x_release_nvram_lock(bp);
715
716 return rc;
717}
718
719static int bnx2x_get_eeprom(struct net_device *dev,
720 struct ethtool_eeprom *eeprom, u8 *eebuf)
721{
722 struct bnx2x *bp = netdev_priv(dev);
723 int rc;
724
725 if (!netif_running(dev))
726 return -EAGAIN;
727
728 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
729 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
730 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
731 eeprom->len, eeprom->len);
732
733 /* parameters already validated in ethtool_get_eeprom */
734
735 rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
736
737 return rc;
738}
739
740static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
741 u32 cmd_flags)
742{
743 int count, i, rc;
744
745 /* build the command word */
746 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
747
748 /* need to clear DONE bit separately */
749 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
750
751 /* write the data */
752 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
753
754 /* address of the NVRAM to write to */
755 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
756 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
757
758 /* issue the write command */
759 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
760
761 /* adjust timeout for emulation/FPGA */
762 count = NVRAM_TIMEOUT_COUNT;
763 if (CHIP_REV_IS_SLOW(bp))
764 count *= 100;
765
766 /* wait for completion */
767 rc = -EBUSY;
768 for (i = 0; i < count; i++) {
769 udelay(5);
770 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
771 if (val & MCPR_NVM_COMMAND_DONE) {
772 rc = 0;
773 break;
774 }
775 }
776
777 return rc;
778}
779
780#define BYTE_OFFSET(offset) (8 * (offset & 0x03))
781
782static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
783 int buf_size)
784{
785 int rc;
786 u32 cmd_flags;
787 u32 align_offset;
788 __be32 val;
789
790 if (offset + buf_size > bp->common.flash_size) {
791 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
792 " buf_size (0x%x) > flash_size (0x%x)\n",
793 offset, buf_size, bp->common.flash_size);
794 return -EINVAL;
795 }
796
797 /* request access to nvram interface */
798 rc = bnx2x_acquire_nvram_lock(bp);
799 if (rc)
800 return rc;
801
802 /* enable access to nvram interface */
803 bnx2x_enable_nvram_access(bp);
804
805 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
806 align_offset = (offset & ~0x03);
807 rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
808
809 if (rc == 0) {
810 val &= ~(0xff << BYTE_OFFSET(offset));
811 val |= (*data_buf << BYTE_OFFSET(offset));
812
813 /* nvram data is returned as an array of bytes
814 * convert it back to cpu order */
815 val = be32_to_cpu(val);
816
817 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
818 cmd_flags);
819 }
820
821 /* disable access to nvram interface */
822 bnx2x_disable_nvram_access(bp);
823 bnx2x_release_nvram_lock(bp);
824
825 return rc;
826}
827
828static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
829 int buf_size)
830{
831 int rc;
832 u32 cmd_flags;
833 u32 val;
834 u32 written_so_far;
835
836 if (buf_size == 1) /* ethtool */
837 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
838
839 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
840 DP(BNX2X_MSG_NVM,
841 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
842 offset, buf_size);
843 return -EINVAL;
844 }
845
846 if (offset + buf_size > bp->common.flash_size) {
847 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
848 " buf_size (0x%x) > flash_size (0x%x)\n",
849 offset, buf_size, bp->common.flash_size);
850 return -EINVAL;
851 }
852
853 /* request access to nvram interface */
854 rc = bnx2x_acquire_nvram_lock(bp);
855 if (rc)
856 return rc;
857
858 /* enable access to nvram interface */
859 bnx2x_enable_nvram_access(bp);
860
861 written_so_far = 0;
862 cmd_flags = MCPR_NVM_COMMAND_FIRST;
863 while ((written_so_far < buf_size) && (rc == 0)) {
864 if (written_so_far == (buf_size - sizeof(u32)))
865 cmd_flags |= MCPR_NVM_COMMAND_LAST;
866 else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0)
867 cmd_flags |= MCPR_NVM_COMMAND_LAST;
868 else if ((offset % NVRAM_PAGE_SIZE) == 0)
869 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
870
871 memcpy(&val, data_buf, 4);
872
873 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
874
875 /* advance to the next dword */
876 offset += sizeof(u32);
877 data_buf += sizeof(u32);
878 written_so_far += sizeof(u32);
879 cmd_flags = 0;
880 }
881
882 /* disable access to nvram interface */
883 bnx2x_disable_nvram_access(bp);
884 bnx2x_release_nvram_lock(bp);
885
886 return rc;
887}
888
889static int bnx2x_set_eeprom(struct net_device *dev,
890 struct ethtool_eeprom *eeprom, u8 *eebuf)
891{
892 struct bnx2x *bp = netdev_priv(dev);
893 int port = BP_PORT(bp);
894 int rc = 0;
e10bc84d 895 u32 ext_phy_config;
de0c62db
DK		 896 if (!netif_running(dev))
897 return -EAGAIN;
898
899 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
900 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
901 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
902 eeprom->len, eeprom->len);
903
904 /* parameters already validated in ethtool_set_eeprom */
905
906 /* PHY eeprom can be accessed only by the PMF */
907 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
908 !bp->port.pmf)
909 return -EINVAL;
910
e10bc84d
YR		 911 ext_phy_config =
912 SHMEM_RD(bp,
913 dev_info.port_hw_config[port].external_phy_config);
914
de0c62db
DK		 915 if (eeprom->magic == 0x50485950) {
916 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
917 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
918
919 bnx2x_acquire_phy_lock(bp);
920 rc |= bnx2x_link_reset(&bp->link_params,
921 &bp->link_vars, 0);
e10bc84d 922 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db
DK		 923 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
924 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
925 MISC_REGISTERS_GPIO_HIGH, port);
926 bnx2x_release_phy_lock(bp);
927 bnx2x_link_report(bp);
928
929 } else if (eeprom->magic == 0x50485952) {
930 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
931 if (bp->state == BNX2X_STATE_OPEN) {
932 bnx2x_acquire_phy_lock(bp);
933 rc |= bnx2x_link_reset(&bp->link_params,
934 &bp->link_vars, 1);
935
936 rc |= bnx2x_phy_init(&bp->link_params,
937 &bp->link_vars);
938 bnx2x_release_phy_lock(bp);
939 bnx2x_calc_fc_adv(bp);
940 }
941 } else if (eeprom->magic == 0x53985943) {
942 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
e10bc84d 943 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db 944 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
de0c62db
DK		 945
946 /* DSP Remove Download Mode */
947 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
948 MISC_REGISTERS_GPIO_LOW, port);
949
950 bnx2x_acquire_phy_lock(bp);
951
e10bc84d
YR		 952 bnx2x_sfx7101_sp_sw_reset(bp,
953 &bp->link_params.phy[EXT_PHY1]);
de0c62db
DK		 954
955 /* wait 0.5 sec to allow it to run */
956 msleep(500);
957 bnx2x_ext_phy_hw_reset(bp, port);
958 msleep(500);
959 bnx2x_release_phy_lock(bp);
960 }
961 } else
962 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
963
964 return rc;
965}
966static int bnx2x_get_coalesce(struct net_device *dev,
967 struct ethtool_coalesce *coal)
968{
969 struct bnx2x *bp = netdev_priv(dev);
970
971 memset(coal, 0, sizeof(struct ethtool_coalesce));
972
973 coal->rx_coalesce_usecs = bp->rx_ticks;
974 coal->tx_coalesce_usecs = bp->tx_ticks;
975
976 return 0;
977}
978
979static int bnx2x_set_coalesce(struct net_device *dev,
980 struct ethtool_coalesce *coal)
981{
982 struct bnx2x *bp = netdev_priv(dev);
983
984 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
985 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
986 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
987
988 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
989 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
990 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
991
992 if (netif_running(dev))
993 bnx2x_update_coalesce(bp);
994
995 return 0;
996}
997
998static void bnx2x_get_ringparam(struct net_device *dev,
999 struct ethtool_ringparam *ering)
1000{
1001 struct bnx2x *bp = netdev_priv(dev);
1002
1003 ering->rx_max_pending = MAX_RX_AVAIL;
1004 ering->rx_mini_max_pending = 0;
1005 ering->rx_jumbo_max_pending = 0;
1006
25141580
DK		 1007 if (bp->rx_ring_size)
1008 ering->rx_pending = bp->rx_ring_size;
1009 else
1010 if (bp->state == BNX2X_STATE_OPEN && bp->num_queues)
1011 ering->rx_pending = MAX_RX_AVAIL/bp->num_queues;
1012 else
1013 ering->rx_pending = MAX_RX_AVAIL;
1014
de0c62db
DK		 1015 ering->rx_mini_pending = 0;
1016 ering->rx_jumbo_pending = 0;
1017
1018 ering->tx_max_pending = MAX_TX_AVAIL;
1019 ering->tx_pending = bp->tx_ring_size;
1020}
1021
1022static int bnx2x_set_ringparam(struct net_device *dev,
1023 struct ethtool_ringparam *ering)
1024{
1025 struct bnx2x *bp = netdev_priv(dev);
1026 int rc = 0;
1027
1028 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1029 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1030 return -EAGAIN;
1031 }
1032
1033 if ((ering->rx_pending > MAX_RX_AVAIL) ||
25141580 1034 (ering->rx_pending < MIN_RX_AVAIL) ||
de0c62db
DK		 1035 (ering->tx_pending > MAX_TX_AVAIL) ||
1036 (ering->tx_pending <= MAX_SKB_FRAGS + 4))
1037 return -EINVAL;
1038
1039 bp->rx_ring_size = ering->rx_pending;
1040 bp->tx_ring_size = ering->tx_pending;
1041
1042 if (netif_running(dev)) {
1043 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1044 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
1045 }
1046
1047 return rc;
1048}
1049
1050static void bnx2x_get_pauseparam(struct net_device *dev,
1051 struct ethtool_pauseparam *epause)
1052{
1053 struct bnx2x *bp = netdev_priv(dev);
a22f0788
YR		 1054 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1055 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1056 BNX2X_FLOW_CTRL_AUTO);
de0c62db
DK		 1057
1058 epause->rx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) ==
1059 BNX2X_FLOW_CTRL_RX);
1060 epause->tx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) ==
1061 BNX2X_FLOW_CTRL_TX);
1062
1063 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1064 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
1065 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1066}
1067
1068static int bnx2x_set_pauseparam(struct net_device *dev,
1069 struct ethtool_pauseparam *epause)
1070{
1071 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1072 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
fb3bff17 1073 if (IS_MF(bp))
de0c62db
DK		 1074 return 0;
1075
1076 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1077 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
1078 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1079
a22f0788 1080 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
de0c62db
DK		 1081
1082 if (epause->rx_pause)
a22f0788 1083 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
de0c62db
DK		 1084
1085 if (epause->tx_pause)
a22f0788 1086 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
de0c62db 1087
a22f0788
YR		 1088 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1089 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
de0c62db
DK		 1090
1091 if (epause->autoneg) {
a22f0788 1092 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
de0c62db
DK		 1093 DP(NETIF_MSG_LINK, "autoneg not supported\n");
1094 return -EINVAL;
1095 }
1096
a22f0788
YR		 1097 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1098 bp->link_params.req_flow_ctrl[cfg_idx] =
1099 BNX2X_FLOW_CTRL_AUTO;
1100 }
de0c62db
DK		 1101 }
1102
1103 DP(NETIF_MSG_LINK,
a22f0788 1104 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
de0c62db
DK		 1105
1106 if (netif_running(dev)) {
1107 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1108 bnx2x_link_set(bp);
1109 }
1110
1111 return 0;
1112}
1113
1114static int bnx2x_set_flags(struct net_device *dev, u32 data)
1115{
1116 struct bnx2x *bp = netdev_priv(dev);
1117 int changed = 0;
1118 int rc = 0;
1119
1120 if (data & ~(ETH_FLAG_LRO | ETH_FLAG_RXHASH))
1121 return -EINVAL;
1122
1123 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1124 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1125 return -EAGAIN;
1126 }
1127
1128 /* TPA requires Rx CSUM offloading */
1129 if ((data & ETH_FLAG_LRO) && bp->rx_csum) {
1130 if (!bp->disable_tpa) {
1131 if (!(dev->features & NETIF_F_LRO)) {
1132 dev->features |= NETIF_F_LRO;
1133 bp->flags |= TPA_ENABLE_FLAG;
1134 changed = 1;
1135 }
1136 } else
1137 rc = -EINVAL;
1138 } else if (dev->features & NETIF_F_LRO) {
1139 dev->features &= ~NETIF_F_LRO;
1140 bp->flags &= ~TPA_ENABLE_FLAG;
1141 changed = 1;
1142 }
1143
1144 if (data & ETH_FLAG_RXHASH)
1145 dev->features |= NETIF_F_RXHASH;
1146 else
1147 dev->features &= ~NETIF_F_RXHASH;
1148
1149 if (changed && netif_running(dev)) {
1150 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1151 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
1152 }
1153
1154 return rc;
1155}
1156
1157static u32 bnx2x_get_rx_csum(struct net_device *dev)
1158{
1159 struct bnx2x *bp = netdev_priv(dev);
1160
1161 return bp->rx_csum;
1162}
1163
1164static int bnx2x_set_rx_csum(struct net_device *dev, u32 data)
1165{
1166 struct bnx2x *bp = netdev_priv(dev);
1167 int rc = 0;
1168
1169 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1170 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1171 return -EAGAIN;
1172 }
1173
1174 bp->rx_csum = data;
1175
1176 /* Disable TPA, when Rx CSUM is disabled. Otherwise all
1177 TPA'ed packets will be discarded due to wrong TCP CSUM */
1178 if (!data) {
1179 u32 flags = ethtool_op_get_flags(dev);
1180
1181 rc = bnx2x_set_flags(dev, (flags & ~ETH_FLAG_LRO));
1182 }
1183
1184 return rc;
1185}
1186
1187static int bnx2x_set_tso(struct net_device *dev, u32 data)
1188{
1189 if (data) {
1190 dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
1191 dev->features |= NETIF_F_TSO6;
1192 } else {
1193 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO_ECN);
1194 dev->features &= ~NETIF_F_TSO6;
1195 }
1196
1197 return 0;
1198}
1199
1200static const struct {
1201 char string[ETH_GSTRING_LEN];
1202} bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
1203 { "register_test (offline)" },
1204 { "memory_test (offline)" },
1205 { "loopback_test (offline)" },
1206 { "nvram_test (online)" },
1207 { "interrupt_test (online)" },
1208 { "link_test (online)" },
1209 { "idle check (online)" }
1210};
1211
1212static int bnx2x_test_registers(struct bnx2x *bp)
1213{
1214 int idx, i, rc = -ENODEV;
1215 u32 wr_val = 0;
1216 int port = BP_PORT(bp);
1217 static const struct {
1218 u32 offset0;
1219 u32 offset1;
1220 u32 mask;
1221 } reg_tbl[] = {
1222/* 0 */ { BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
1223 { DORQ_REG_DB_ADDR0, 4, 0xffffffff },
1224 { HC_REG_AGG_INT_0, 4, 0x000003ff },
1225 { PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
1226 { PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
1227 { PRS_REG_CID_PORT_0, 4, 0x00ffffff },
1228 { PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
1229 { PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1230 { PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
1231 { PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1232/* 10 */ { PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
1233 { QM_REG_CONNNUM_0, 4, 0x000fffff },
1234 { TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
1235 { SRC_REG_KEYRSS0_0, 40, 0xffffffff },
1236 { SRC_REG_KEYRSS0_7, 40, 0xffffffff },
1237 { XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
1238 { XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
1239 { XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
1240 { NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
1241 { NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
1242/* 20 */ { NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
1243 { NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
1244 { NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
1245 { NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
1246 { NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
1247 { NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
1248 { NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
1249 { NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
1250 { NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
1251 { NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
1252/* 30 */ { NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
1253 { NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
1254 { NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
1255 { NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001 },
1256 { NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
1257 { NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
1258 { NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
1259
1260 { 0xffffffff, 0, 0x00000000 }
1261 };
1262
1263 if (!netif_running(bp->dev))
1264 return rc;
1265
1266 /* Repeat the test twice:
1267 First by writing 0x00000000, second by writing 0xffffffff */
1268 for (idx = 0; idx < 2; idx++) {
1269
1270 switch (idx) {
1271 case 0:
1272 wr_val = 0;
1273 break;
1274 case 1:
1275 wr_val = 0xffffffff;
1276 break;
1277 }
1278
1279 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
1280 u32 offset, mask, save_val, val;
f2e0899f
DK		 1281 if (CHIP_IS_E2(bp) &&
1282 reg_tbl[i].offset0 == HC_REG_AGG_INT_0)
1283 continue;
de0c62db
DK		 1284
1285 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
1286 mask = reg_tbl[i].mask;
1287
1288 save_val = REG_RD(bp, offset);
1289
1290 REG_WR(bp, offset, (wr_val & mask));
1291 val = REG_RD(bp, offset);
1292
1293 /* Restore the original register's value */
1294 REG_WR(bp, offset, save_val);
1295
1296 /* verify value is as expected */
1297 if ((val & mask) != (wr_val & mask)) {
1298 DP(NETIF_MSG_PROBE,
1299 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
1300 offset, val, wr_val, mask);
1301 goto test_reg_exit;
1302 }
1303 }
1304 }
1305
1306 rc = 0;
1307
1308test_reg_exit:
1309 return rc;
1310}
1311
1312static int bnx2x_test_memory(struct bnx2x *bp)
1313{
1314 int i, j, rc = -ENODEV;
1315 u32 val;
1316 static const struct {
1317 u32 offset;
1318 int size;
1319 } mem_tbl[] = {
1320 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
1321 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
1322 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
1323 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
1324 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
1325 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
1326 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
1327
1328 { 0xffffffff, 0 }
1329 };
1330 static const struct {
1331 char *name;
1332 u32 offset;
1333 u32 e1_mask;
1334 u32 e1h_mask;
f2e0899f 1335 u32 e2_mask;
de0c62db 1336 } prty_tbl[] = {
f2e0899f
DK		 1337 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 0x3ffc0, 0, 0 },
1338 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 0x2, 0x2, 0 },
1339 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 0, 0, 0 },
1340 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 0x3ffc0, 0, 0 },
1341 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 0x3ffc0, 0, 0 },
1342 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 0x3ffc1, 0, 0 },
1343
1344 { NULL, 0xffffffff, 0, 0, 0 }
de0c62db
DK		 1345 };
1346
1347 if (!netif_running(bp->dev))
1348 return rc;
1349
f2e0899f
DK		 1350 /* pre-Check the parity status */
1351 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1352 val = REG_RD(bp, prty_tbl[i].offset);
1353 if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) ||
1354 (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask))) ||
1355 (CHIP_IS_E2(bp) && (val & ~(prty_tbl[i].e2_mask)))) {
1356 DP(NETIF_MSG_HW,
1357 "%s is 0x%x\n", prty_tbl[i].name, val);
1358 goto test_mem_exit;
1359 }
1360 }
1361
de0c62db
DK		 1362 /* Go through all the memories */
1363 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
1364 for (j = 0; j < mem_tbl[i].size; j++)
1365 REG_RD(bp, mem_tbl[i].offset + j*4);
1366
1367 /* Check the parity status */
1368 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1369 val = REG_RD(bp, prty_tbl[i].offset);
1370 if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) ||
f2e0899f
DK		 1371 (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask))) ||
1372 (CHIP_IS_E2(bp) && (val & ~(prty_tbl[i].e2_mask)))) {
de0c62db
DK		 1373 DP(NETIF_MSG_HW,
1374 "%s is 0x%x\n", prty_tbl[i].name, val);
1375 goto test_mem_exit;
1376 }
1377 }
1378
1379 rc = 0;
1380
1381test_mem_exit:
1382 return rc;
1383}
1384
a22f0788 1385static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
de0c62db 1386{
f2e0899f 1387 int cnt = 1400;
de0c62db
DK		 1388
1389 if (link_up)
a22f0788 1390 while (bnx2x_link_test(bp, is_serdes) && cnt--)
de0c62db
DK		 1391 msleep(10);
1392}
1393
1394static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode, u8 link_up)
1395{
1396 unsigned int pkt_size, num_pkts, i;
1397 struct sk_buff *skb;
1398 unsigned char *packet;
1399 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
1400 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
1401 u16 tx_start_idx, tx_idx;
1402 u16 rx_start_idx, rx_idx;
1403 u16 pkt_prod, bd_prod;
1404 struct sw_tx_bd *tx_buf;
1405 struct eth_tx_start_bd *tx_start_bd;
f2e0899f
DK		 1406 struct eth_tx_parse_bd_e1x *pbd_e1x = NULL;
1407 struct eth_tx_parse_bd_e2 *pbd_e2 = NULL;
de0c62db
DK		 1408 dma_addr_t mapping;
1409 union eth_rx_cqe *cqe;
1410 u8 cqe_fp_flags;
1411 struct sw_rx_bd *rx_buf;
1412 u16 len;
1413 int rc = -ENODEV;
1414
1415 /* check the loopback mode */
1416 switch (loopback_mode) {
1417 case BNX2X_PHY_LOOPBACK:
de6eae1f 1418 if (bp->link_params.loopback_mode != LOOPBACK_XGXS)
de0c62db
DK		 1419 return -EINVAL;
1420 break;
1421 case BNX2X_MAC_LOOPBACK:
1422 bp->link_params.loopback_mode = LOOPBACK_BMAC;
1423 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1424 break;
1425 default:
1426 return -EINVAL;
1427 }
1428
1429 /* prepare the loopback packet */
1430 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
1431 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
1432 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
1433 if (!skb) {
1434 rc = -ENOMEM;
1435 goto test_loopback_exit;
1436 }
1437 packet = skb_put(skb, pkt_size);
1438 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
1439 memset(packet + ETH_ALEN, 0, ETH_ALEN);
1440 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
1441 for (i = ETH_HLEN; i < pkt_size; i++)
1442 packet[i] = (unsigned char) (i & 0xff);
1443
1444 /* send the loopback packet */
1445 num_pkts = 0;
1446 tx_start_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
1447 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1448
1449 pkt_prod = fp_tx->tx_pkt_prod++;
1450 tx_buf = &fp_tx->tx_buf_ring[TX_BD(pkt_prod)];
1451 tx_buf->first_bd = fp_tx->tx_bd_prod;
1452 tx_buf->skb = skb;
1453 tx_buf->flags = 0;
1454
1455 bd_prod = TX_BD(fp_tx->tx_bd_prod);
1456 tx_start_bd = &fp_tx->tx_desc_ring[bd_prod].start_bd;
1457 mapping = dma_map_single(&bp->pdev->dev, skb->data,
1458 skb_headlen(skb), DMA_TO_DEVICE);
1459 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1460 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1461 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
1462 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
523224a3 1463 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
de0c62db 1464 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
523224a3
DK		 1465 SET_FLAG(tx_start_bd->general_data,
1466 ETH_TX_START_BD_ETH_ADDR_TYPE,
1467 UNICAST_ADDRESS);
1468 SET_FLAG(tx_start_bd->general_data,
1469 ETH_TX_START_BD_HDR_NBDS,
1470 1);
de0c62db
DK		 1471
1472 /* turn on parsing and get a BD */
1473 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
523224a3 1474 pbd_e1x = &fp_tx->tx_desc_ring[bd_prod].parse_bd_e1x;
f2e0899f 1475 pbd_e2 = &fp_tx->tx_desc_ring[bd_prod].parse_bd_e2;
de0c62db 1476
f2e0899f 1477 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
523224a3 1478 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
de0c62db
DK		 1479
1480 wmb();
1481
1482 fp_tx->tx_db.data.prod += 2;
1483 barrier();
1484 DOORBELL(bp, fp_tx->index, fp_tx->tx_db.raw);
1485
1486 mmiowb();
1487
1488 num_pkts++;
1489 fp_tx->tx_bd_prod += 2; /* start + pbd */
1490
1491 udelay(100);
1492
1493 tx_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
1494 if (tx_idx != tx_start_idx + num_pkts)
1495 goto test_loopback_exit;
1496
f2e0899f
DK		 1497 /* Unlike HC IGU won't generate an interrupt for status block
1498 * updates that have been performed while interrupts were
1499 * disabled.
1500 */
1501 if (bp->common.int_block == INT_BLOCK_IGU)
1502 bnx2x_tx_int(fp_tx);
1503
de0c62db
DK		 1504 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1505 if (rx_idx != rx_start_idx + num_pkts)
1506 goto test_loopback_exit;
1507
1508 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
1509 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
1510 if (CQE_TYPE(cqe_fp_flags) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
1511 goto test_loopback_rx_exit;
1512
1513 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
1514 if (len != pkt_size)
1515 goto test_loopback_rx_exit;
1516
1517 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
1518 skb = rx_buf->skb;
1519 skb_reserve(skb, cqe->fast_path_cqe.placement_offset);
1520 for (i = ETH_HLEN; i < pkt_size; i++)
1521 if (*(skb->data + i) != (unsigned char) (i & 0xff))
1522 goto test_loopback_rx_exit;
1523
1524 rc = 0;
1525
1526test_loopback_rx_exit:
1527
1528 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
1529 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
1530 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
1531 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
1532
1533 /* Update producers */
1534 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
1535 fp_rx->rx_sge_prod);
1536
1537test_loopback_exit:
1538 bp->link_params.loopback_mode = LOOPBACK_NONE;
1539
1540 return rc;
1541}
1542
1543static int bnx2x_test_loopback(struct bnx2x *bp, u8 link_up)
1544{
1545 int rc = 0, res;
1546
1547 if (BP_NOMCP(bp))
1548 return rc;
1549
1550 if (!netif_running(bp->dev))
1551 return BNX2X_LOOPBACK_FAILED;
1552
1553 bnx2x_netif_stop(bp, 1);
1554 bnx2x_acquire_phy_lock(bp);
1555
1556 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK, link_up);
1557 if (res) {
1558 DP(NETIF_MSG_PROBE, " PHY loopback failed (res %d)\n", res);
1559 rc |= BNX2X_PHY_LOOPBACK_FAILED;
1560 }
1561
1562 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK, link_up);
1563 if (res) {
1564 DP(NETIF_MSG_PROBE, " MAC loopback failed (res %d)\n", res);
1565 rc |= BNX2X_MAC_LOOPBACK_FAILED;
1566 }
1567
1568 bnx2x_release_phy_lock(bp);
1569 bnx2x_netif_start(bp);
1570
1571 return rc;
1572}
1573
1574#define CRC32_RESIDUAL 0xdebb20e3
1575
1576static int bnx2x_test_nvram(struct bnx2x *bp)
1577{
1578 static const struct {
1579 int offset;
1580 int size;
1581 } nvram_tbl[] = {
1582 { 0, 0x14 }, /* bootstrap */
1583 { 0x14, 0xec }, /* dir */
1584 { 0x100, 0x350 }, /* manuf_info */
1585 { 0x450, 0xf0 }, /* feature_info */
1586 { 0x640, 0x64 }, /* upgrade_key_info */
1587 { 0x6a4, 0x64 },
1588 { 0x708, 0x70 }, /* manuf_key_info */
1589 { 0x778, 0x70 },
1590 { 0, 0 }
1591 };
1592 __be32 buf[0x350 / 4];
1593 u8 *data = (u8 *)buf;
1594 int i, rc;
1595 u32 magic, crc;
1596
1597 if (BP_NOMCP(bp))
1598 return 0;
1599
1600 rc = bnx2x_nvram_read(bp, 0, data, 4);
1601 if (rc) {
1602 DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc);
1603 goto test_nvram_exit;
1604 }
1605
1606 magic = be32_to_cpu(buf[0]);
1607 if (magic != 0x669955aa) {
1608 DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic);
1609 rc = -ENODEV;
1610 goto test_nvram_exit;
1611 }
1612
1613 for (i = 0; nvram_tbl[i].size; i++) {
1614
1615 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
1616 nvram_tbl[i].size);
1617 if (rc) {
1618 DP(NETIF_MSG_PROBE,
1619 "nvram_tbl[%d] read data (rc %d)\n", i, rc);
1620 goto test_nvram_exit;
1621 }
1622
1623 crc = ether_crc_le(nvram_tbl[i].size, data);
1624 if (crc != CRC32_RESIDUAL) {
1625 DP(NETIF_MSG_PROBE,
1626 "nvram_tbl[%d] crc value (0x%08x)\n", i, crc);
1627 rc = -ENODEV;
1628 goto test_nvram_exit;
1629 }
1630 }
1631
1632test_nvram_exit:
1633 return rc;
1634}
1635
1636static int bnx2x_test_intr(struct bnx2x *bp)
1637{
1638 struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
1639 int i, rc;
1640
1641 if (!netif_running(bp->dev))
1642 return -ENODEV;
1643
1644 config->hdr.length = 0;
1645 if (CHIP_IS_E1(bp))
f2e0899f 1646 config->hdr.offset = (BP_PORT(bp) ? 32 : 0);
de0c62db
DK		 1647 else
1648 config->hdr.offset = BP_FUNC(bp);
1649 config->hdr.client_id = bp->fp->cl_id;
1650 config->hdr.reserved1 = 0;
1651
1652 bp->set_mac_pending++;
1653 smp_wmb();
523224a3 1654 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
de0c62db 1655 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
523224a3 1656 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 1);
de0c62db
DK		 1657 if (rc == 0) {
1658 for (i = 0; i < 10; i++) {
1659 if (!bp->set_mac_pending)
1660 break;
1661 smp_rmb();
1662 msleep_interruptible(10);
1663 }
1664 if (i == 10)
1665 rc = -ENODEV;
1666 }
1667
1668 return rc;
1669}
1670
1671static void bnx2x_self_test(struct net_device *dev,
1672 struct ethtool_test *etest, u64 *buf)
1673{
1674 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1675 u8 is_serdes;
de0c62db
DK		 1676 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1677 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1678 etest->flags |= ETH_TEST_FL_FAILED;
1679 return;
1680 }
1681
1682 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
1683
1684 if (!netif_running(dev))
1685 return;
1686
1687 /* offline tests are not supported in MF mode */
fb3bff17 1688 if (IS_MF(bp))
de0c62db 1689 etest->flags &= ~ETH_TEST_FL_OFFLINE;
a22f0788 1690 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
de0c62db
DK		 1691
1692 if (etest->flags & ETH_TEST_FL_OFFLINE) {
1693 int port = BP_PORT(bp);
1694 u32 val;
1695 u8 link_up;
1696
1697 /* save current value of input enable for TX port IF */
1698 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
1699 /* disable input for TX port IF */
1700 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
1701
a22f0788
YR		 1702 link_up = bp->link_vars.link_up;
1703
de0c62db
DK		 1704 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1705 bnx2x_nic_load(bp, LOAD_DIAG);
1706 /* wait until link state is restored */
a22f0788 1707 bnx2x_wait_for_link(bp, link_up, is_serdes);
de0c62db
DK		 1708
1709 if (bnx2x_test_registers(bp) != 0) {
1710 buf[0] = 1;
1711 etest->flags |= ETH_TEST_FL_FAILED;
1712 }
1713 if (bnx2x_test_memory(bp) != 0) {
1714 buf[1] = 1;
1715 etest->flags |= ETH_TEST_FL_FAILED;
1716 }
1717 buf[2] = bnx2x_test_loopback(bp, link_up);
1718 if (buf[2] != 0)
1719 etest->flags |= ETH_TEST_FL_FAILED;
1720
1721 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1722
1723 /* restore input for TX port IF */
1724 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
1725
1726 bnx2x_nic_load(bp, LOAD_NORMAL);
1727 /* wait until link state is restored */
a22f0788 1728 bnx2x_wait_for_link(bp, link_up, is_serdes);
de0c62db
DK		 1729 }
1730 if (bnx2x_test_nvram(bp) != 0) {
1731 buf[3] = 1;
1732 etest->flags |= ETH_TEST_FL_FAILED;
1733 }
1734 if (bnx2x_test_intr(bp) != 0) {
1735 buf[4] = 1;
1736 etest->flags |= ETH_TEST_FL_FAILED;
1737 }
1738 if (bp->port.pmf)
a22f0788 1739 if (bnx2x_link_test(bp, is_serdes) != 0) {
de0c62db
DK		 1740 buf[5] = 1;
1741 etest->flags |= ETH_TEST_FL_FAILED;
1742 }
1743
1744#ifdef BNX2X_EXTRA_DEBUG
1745 bnx2x_panic_dump(bp);
1746#endif
1747}
1748
1749static const struct {
1750 long offset;
1751 int size;
1752 u8 string[ETH_GSTRING_LEN];
1753} bnx2x_q_stats_arr[BNX2X_NUM_Q_STATS] = {
1754/* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%d]: rx_bytes" },
1755 { Q_STATS_OFFSET32(error_bytes_received_hi),
1756 8, "[%d]: rx_error_bytes" },
1757 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
1758 8, "[%d]: rx_ucast_packets" },
1759 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
1760 8, "[%d]: rx_mcast_packets" },
1761 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
1762 8, "[%d]: rx_bcast_packets" },
1763 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%d]: rx_discards" },
1764 { Q_STATS_OFFSET32(rx_err_discard_pkt),
1765 4, "[%d]: rx_phy_ip_err_discards"},
1766 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
1767 4, "[%d]: rx_skb_alloc_discard" },
1768 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%d]: rx_csum_offload_errors" },
1769
1770/* 10 */{ Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%d]: tx_bytes" },
1771 { Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
1772 8, "[%d]: tx_ucast_packets" },
1773 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
1774 8, "[%d]: tx_mcast_packets" },
1775 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
1776 8, "[%d]: tx_bcast_packets" }
1777};
1778
1779static const struct {
1780 long offset;
1781 int size;
1782 u32 flags;
1783#define STATS_FLAGS_PORT 1
1784#define STATS_FLAGS_FUNC 2
1785#define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
1786 u8 string[ETH_GSTRING_LEN];
1787} bnx2x_stats_arr[BNX2X_NUM_STATS] = {
1788/* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
1789 8, STATS_FLAGS_BOTH, "rx_bytes" },
1790 { STATS_OFFSET32(error_bytes_received_hi),
1791 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
1792 { STATS_OFFSET32(total_unicast_packets_received_hi),
1793 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
1794 { STATS_OFFSET32(total_multicast_packets_received_hi),
1795 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
1796 { STATS_OFFSET32(total_broadcast_packets_received_hi),
1797 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
1798 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
1799 8, STATS_FLAGS_PORT, "rx_crc_errors" },
1800 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
1801 8, STATS_FLAGS_PORT, "rx_align_errors" },
1802 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
1803 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
1804 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
1805 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
1806/* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
1807 8, STATS_FLAGS_PORT, "rx_fragments" },
1808 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
1809 8, STATS_FLAGS_PORT, "rx_jabbers" },
1810 { STATS_OFFSET32(no_buff_discard_hi),
1811 8, STATS_FLAGS_BOTH, "rx_discards" },
1812 { STATS_OFFSET32(mac_filter_discard),
1813 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
1814 { STATS_OFFSET32(xxoverflow_discard),
1815 4, STATS_FLAGS_PORT, "rx_fw_discards" },
1816 { STATS_OFFSET32(brb_drop_hi),
1817 8, STATS_FLAGS_PORT, "rx_brb_discard" },
1818 { STATS_OFFSET32(brb_truncate_hi),
1819 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
1820 { STATS_OFFSET32(pause_frames_received_hi),
1821 8, STATS_FLAGS_PORT, "rx_pause_frames" },
1822 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
1823 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
1824 { STATS_OFFSET32(nig_timer_max),
1825 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
1826/* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
1827 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
1828 { STATS_OFFSET32(rx_skb_alloc_failed),
1829 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
1830 { STATS_OFFSET32(hw_csum_err),
1831 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
1832
1833 { STATS_OFFSET32(total_bytes_transmitted_hi),
1834 8, STATS_FLAGS_BOTH, "tx_bytes" },
1835 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
1836 8, STATS_FLAGS_PORT, "tx_error_bytes" },
1837 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
1838 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
1839 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
1840 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
1841 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
1842 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
1843 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
1844 8, STATS_FLAGS_PORT, "tx_mac_errors" },
1845 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
1846 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
1847/* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
1848 8, STATS_FLAGS_PORT, "tx_single_collisions" },
1849 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
1850 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
1851 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
1852 8, STATS_FLAGS_PORT, "tx_deferred" },
1853 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
1854 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
1855 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
1856 8, STATS_FLAGS_PORT, "tx_late_collisions" },
1857 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
1858 8, STATS_FLAGS_PORT, "tx_total_collisions" },
1859 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
1860 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
1861 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
1862 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
1863 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
1864 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
1865 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
1866 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
1867/* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
1868 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
1869 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
1870 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
1871 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
1872 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
1873 { STATS_OFFSET32(pause_frames_sent_hi),
1874 8, STATS_FLAGS_PORT, "tx_pause_frames" }
1875};
1876
1877#define IS_PORT_STAT(i) \
1878 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
1879#define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
fb3bff17
DK		 1880#define IS_MF_MODE_STAT(bp) \
1881 (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
de0c62db
DK		 1882
1883static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
1884{
1885 struct bnx2x *bp = netdev_priv(dev);
1886 int i, num_stats;
1887
1888 switch (stringset) {
1889 case ETH_SS_STATS:
1890 if (is_multi(bp)) {
1891 num_stats = BNX2X_NUM_Q_STATS * bp->num_queues;
fb3bff17 1892 if (!IS_MF_MODE_STAT(bp))
de0c62db
DK		 1893 num_stats += BNX2X_NUM_STATS;
1894 } else {
fb3bff17 1895 if (IS_MF_MODE_STAT(bp)) {
de0c62db
DK		 1896 num_stats = 0;
1897 for (i = 0; i < BNX2X_NUM_STATS; i++)
1898 if (IS_FUNC_STAT(i))
1899 num_stats++;
1900 } else
1901 num_stats = BNX2X_NUM_STATS;
1902 }
1903 return num_stats;
1904
1905 case ETH_SS_TEST:
1906 return BNX2X_NUM_TESTS;
1907
1908 default:
1909 return -EINVAL;
1910 }
1911}
1912
1913static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
1914{
1915 struct bnx2x *bp = netdev_priv(dev);
1916 int i, j, k;
1917
1918 switch (stringset) {
1919 case ETH_SS_STATS:
1920 if (is_multi(bp)) {
1921 k = 0;
1922 for_each_queue(bp, i) {
1923 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
1924 sprintf(buf + (k + j)*ETH_GSTRING_LEN,
1925 bnx2x_q_stats_arr[j].string, i);
1926 k += BNX2X_NUM_Q_STATS;
1927 }
fb3bff17 1928 if (IS_MF_MODE_STAT(bp))
de0c62db
DK		 1929 break;
1930 for (j = 0; j < BNX2X_NUM_STATS; j++)
1931 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
1932 bnx2x_stats_arr[j].string);
1933 } else {
1934 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
fb3bff17 1935 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
de0c62db
DK		 1936 continue;
1937 strcpy(buf + j*ETH_GSTRING_LEN,
1938 bnx2x_stats_arr[i].string);
1939 j++;
1940 }
1941 }
1942 break;
1943
1944 case ETH_SS_TEST:
1945 memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
1946 break;
1947 }
1948}
1949
1950static void bnx2x_get_ethtool_stats(struct net_device *dev,
1951 struct ethtool_stats *stats, u64 *buf)
1952{
1953 struct bnx2x *bp = netdev_priv(dev);
1954 u32 *hw_stats, *offset;
1955 int i, j, k;
1956
1957 if (is_multi(bp)) {
1958 k = 0;
1959 for_each_queue(bp, i) {
1960 hw_stats = (u32 *)&bp->fp[i].eth_q_stats;
1961 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
1962 if (bnx2x_q_stats_arr[j].size == 0) {
1963 /* skip this counter */
1964 buf[k + j] = 0;
1965 continue;
1966 }
1967 offset = (hw_stats +
1968 bnx2x_q_stats_arr[j].offset);
1969 if (bnx2x_q_stats_arr[j].size == 4) {
1970 /* 4-byte counter */
1971 buf[k + j] = (u64) *offset;
1972 continue;
1973 }
1974 /* 8-byte counter */
1975 buf[k + j] = HILO_U64(*offset, *(offset + 1));
1976 }
1977 k += BNX2X_NUM_Q_STATS;
1978 }
fb3bff17 1979 if (IS_MF_MODE_STAT(bp))
de0c62db
DK		 1980 return;
1981 hw_stats = (u32 *)&bp->eth_stats;
1982 for (j = 0; j < BNX2X_NUM_STATS; j++) {
1983 if (bnx2x_stats_arr[j].size == 0) {
1984 /* skip this counter */
1985 buf[k + j] = 0;
1986 continue;
1987 }
1988 offset = (hw_stats + bnx2x_stats_arr[j].offset);
1989 if (bnx2x_stats_arr[j].size == 4) {
1990 /* 4-byte counter */
1991 buf[k + j] = (u64) *offset;
1992 continue;
1993 }
1994 /* 8-byte counter */
1995 buf[k + j] = HILO_U64(*offset, *(offset + 1));
1996 }
1997 } else {
1998 hw_stats = (u32 *)&bp->eth_stats;
1999 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
fb3bff17 2000 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
de0c62db
DK		 2001 continue;
2002 if (bnx2x_stats_arr[i].size == 0) {
2003 /* skip this counter */
2004 buf[j] = 0;
2005 j++;
2006 continue;
2007 }
2008 offset = (hw_stats + bnx2x_stats_arr[i].offset);
2009 if (bnx2x_stats_arr[i].size == 4) {
2010 /* 4-byte counter */
2011 buf[j] = (u64) *offset;
2012 j++;
2013 continue;
2014 }
2015 /* 8-byte counter */
2016 buf[j] = HILO_U64(*offset, *(offset + 1));
2017 j++;
2018 }
2019 }
2020}
2021
2022static int bnx2x_phys_id(struct net_device *dev, u32 data)
2023{
2024 struct bnx2x *bp = netdev_priv(dev);
2025 int i;
2026
2027 if (!netif_running(dev))
2028 return 0;
2029
2030 if (!bp->port.pmf)
2031 return 0;
2032
2033 if (data == 0)
2034 data = 2;
2035
2036 for (i = 0; i < (data * 2); i++) {
2037 if ((i % 2) == 0)
7f02c4ad
YR		 2038 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2039 LED_MODE_OPER, SPEED_1000);
de0c62db 2040 else
7f02c4ad
YR		 2041 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2042 LED_MODE_OFF, 0);
de0c62db
DK		 2043
2044 msleep_interruptible(500);
2045 if (signal_pending(current))
2046 break;
2047 }
2048
2049 if (bp->link_vars.link_up)
7f02c4ad 2050 bnx2x_set_led(&bp->link_params, &bp->link_vars, LED_MODE_OPER,
de0c62db
DK		 2051 bp->link_vars.line_speed);
2052
2053 return 0;
2054}
2055
2056static const struct ethtool_ops bnx2x_ethtool_ops = {
2057 .get_settings = bnx2x_get_settings,
2058 .set_settings = bnx2x_set_settings,
2059 .get_drvinfo = bnx2x_get_drvinfo,
2060 .get_regs_len = bnx2x_get_regs_len,
2061 .get_regs = bnx2x_get_regs,
2062 .get_wol = bnx2x_get_wol,
2063 .set_wol = bnx2x_set_wol,
2064 .get_msglevel = bnx2x_get_msglevel,
2065 .set_msglevel = bnx2x_set_msglevel,
2066 .nway_reset = bnx2x_nway_reset,
2067 .get_link = bnx2x_get_link,
2068 .get_eeprom_len = bnx2x_get_eeprom_len,
2069 .get_eeprom = bnx2x_get_eeprom,
2070 .set_eeprom = bnx2x_set_eeprom,
2071 .get_coalesce = bnx2x_get_coalesce,
2072 .set_coalesce = bnx2x_set_coalesce,
2073 .get_ringparam = bnx2x_get_ringparam,
2074 .set_ringparam = bnx2x_set_ringparam,
2075 .get_pauseparam = bnx2x_get_pauseparam,
2076 .set_pauseparam = bnx2x_set_pauseparam,
2077 .get_rx_csum = bnx2x_get_rx_csum,
2078 .set_rx_csum = bnx2x_set_rx_csum,
2079 .get_tx_csum = ethtool_op_get_tx_csum,
2080 .set_tx_csum = ethtool_op_set_tx_hw_csum,
2081 .set_flags = bnx2x_set_flags,
2082 .get_flags = ethtool_op_get_flags,
2083 .get_sg = ethtool_op_get_sg,
2084 .set_sg = ethtool_op_set_sg,
2085 .get_tso = ethtool_op_get_tso,
2086 .set_tso = bnx2x_set_tso,
2087 .self_test = bnx2x_self_test,
2088 .get_sset_count = bnx2x_get_sset_count,
2089 .get_strings = bnx2x_get_strings,
2090 .phys_id = bnx2x_phys_id,
2091 .get_ethtool_stats = bnx2x_get_ethtool_stats,
2092};
2093
2094void bnx2x_set_ethtool_ops(struct net_device *netdev)
2095{
2096 SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
2097}
kernel source for telekom puls (alcatel/mediatek)