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bnx2: Zero out context memory for 5709.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / bnx2.c
CommitLineData
b6016b76
MC		 1/* bnx2.c: Broadcom NX2 network driver.
2 *
feebb331 3 * Copyright (c) 2004-2008 Broadcom Corporation
b6016b76
MC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
f2a4f052
MC		 12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15
16#include <linux/kernel.h>
17#include <linux/timer.h>
18#include <linux/errno.h>
19#include <linux/ioport.h>
20#include <linux/slab.h>
21#include <linux/vmalloc.h>
22#include <linux/interrupt.h>
23#include <linux/pci.h>
24#include <linux/init.h>
25#include <linux/netdevice.h>
26#include <linux/etherdevice.h>
27#include <linux/skbuff.h>
28#include <linux/dma-mapping.h>
1977f032 29#include <linux/bitops.h>
f2a4f052
MC		 30#include <asm/io.h>
31#include <asm/irq.h>
32#include <linux/delay.h>
33#include <asm/byteorder.h>
c86a31f4 34#include <asm/page.h>
f2a4f052
MC		 35#include <linux/time.h>
36#include <linux/ethtool.h>
37#include <linux/mii.h>
38#ifdef NETIF_F_HW_VLAN_TX
39#include <linux/if_vlan.h>
40#define BCM_VLAN 1
41#endif
f2a4f052 42#include <net/ip.h>
de081fa5 43#include <net/tcp.h>
f2a4f052 44#include <net/checksum.h>
f2a4f052
MC		 45#include <linux/workqueue.h>
46#include <linux/crc32.h>
47#include <linux/prefetch.h>
29b12174 48#include <linux/cache.h>
fba9fe91 49#include <linux/zlib.h>
f2a4f052 50
b6016b76
MC		 51#include "bnx2.h"
52#include "bnx2_fw.h"
d43584c8 53#include "bnx2_fw2.h"
b6016b76 54
110d0ef9 55#define FW_BUF_SIZE 0x10000
b3448b0b 56
b6016b76
MC		 57#define DRV_MODULE_NAME "bnx2"
58#define PFX DRV_MODULE_NAME ": "
c73b1d1f
MC		 59#define DRV_MODULE_VERSION "1.7.4"
60#define DRV_MODULE_RELDATE "February 18, 2008"
b6016b76
MC		 61
62#define RUN_AT(x) (jiffies + (x))
63
64/* Time in jiffies before concluding the transmitter is hung. */
65#define TX_TIMEOUT (5*HZ)
66
fefa8645 67static char version[] __devinitdata =
b6016b76
MC		 68 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
69
70MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
05d0f1cf 71MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver");
b6016b76
MC		 72MODULE_LICENSE("GPL");
73MODULE_VERSION(DRV_MODULE_VERSION);
74
75static int disable_msi = 0;
76
77module_param(disable_msi, int, 0);
78MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
79
80typedef enum {
81 BCM5706 = 0,
82 NC370T,
83 NC370I,
84 BCM5706S,
85 NC370F,
5b0c76ad
MC		 86 BCM5708,
87 BCM5708S,
bac0dff6 88 BCM5709,
27a005b8 89 BCM5709S,
b6016b76
MC		 90} board_t;
91
92/* indexed by board_t, above */
fefa8645 93static struct {
b6016b76
MC		 94 char *name;
95} board_info[] __devinitdata = {
96 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
97 { "HP NC370T Multifunction Gigabit Server Adapter" },
98 { "HP NC370i Multifunction Gigabit Server Adapter" },
99 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
100 { "HP NC370F Multifunction Gigabit Server Adapter" },
5b0c76ad
MC		 101 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
102 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
bac0dff6 103 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
27a005b8 104 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
b6016b76
MC		 105 };
106
107static struct pci_device_id bnx2_pci_tbl[] = {
108 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
109 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
110 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
111 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
112 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
5b0c76ad
MC		 114 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
b6016b76
MC		 116 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
117 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
118 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
5b0c76ad
MC		 120 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
bac0dff6
MC		 122 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
27a005b8
MC		 124 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
b6016b76
MC		 126 { 0, }
127};
128
129static struct flash_spec flash_table[] =
130{
e30372c9
MC		 131#define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
132#define NONBUFFERED_FLAGS (BNX2_NV_WREN)
b6016b76 133 /* Slow EEPROM */
37137709 134 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
e30372c9 135 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
b6016b76
MC		 136 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
137 "EEPROM - slow"},
37137709
MC		 138 /* Expansion entry 0001 */
139 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 140 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 141 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
142 "Entry 0001"},
b6016b76
MC		 143 /* Saifun SA25F010 (non-buffered flash) */
144 /* strap, cfg1, & write1 need updates */
37137709 145 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 146 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
b6016b76
MC		 147 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
148 "Non-buffered flash (128kB)"},
149 /* Saifun SA25F020 (non-buffered flash) */
150 /* strap, cfg1, & write1 need updates */
37137709 151 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 152 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
b6016b76
MC		 153 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
154 "Non-buffered flash (256kB)"},
37137709
MC		 155 /* Expansion entry 0100 */
156 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 157 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 158 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
159 "Entry 0100"},
160 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
6aa20a22 161 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
e30372c9 162 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
37137709
MC		 163 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
164 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
165 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
166 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
e30372c9 167 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
37137709
MC		 168 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
169 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
170 /* Saifun SA25F005 (non-buffered flash) */
171 /* strap, cfg1, & write1 need updates */
172 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 173 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 174 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
175 "Non-buffered flash (64kB)"},
176 /* Fast EEPROM */
177 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
e30372c9 178 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
37137709
MC		 179 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
180 "EEPROM - fast"},
181 /* Expansion entry 1001 */
182 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 183 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 184 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
185 "Entry 1001"},
186 /* Expansion entry 1010 */
187 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 188 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 189 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
190 "Entry 1010"},
191 /* ATMEL AT45DB011B (buffered flash) */
192 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 193 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 194 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
195 "Buffered flash (128kB)"},
196 /* Expansion entry 1100 */
197 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 198 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 199 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
200 "Entry 1100"},
201 /* Expansion entry 1101 */
202 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 203 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 204 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
205 "Entry 1101"},
206 /* Ateml Expansion entry 1110 */
207 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 208 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 209 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
210 "Entry 1110 (Atmel)"},
211 /* ATMEL AT45DB021B (buffered flash) */
212 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 213 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 214 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
215 "Buffered flash (256kB)"},
b6016b76
MC		 216};
217
e30372c9
MC		 218static struct flash_spec flash_5709 = {
219 .flags = BNX2_NV_BUFFERED,
220 .page_bits = BCM5709_FLASH_PAGE_BITS,
221 .page_size = BCM5709_FLASH_PAGE_SIZE,
222 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
223 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
224 .name = "5709 Buffered flash (256kB)",
225};
226
b6016b76
MC		 227MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
228
a550c99b 229static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_napi *bnapi)
e89bbf10 230{
2f8af120 231 u32 diff;
e89bbf10 232
2f8af120 233 smp_mb();
faac9c4b
MC		 234
235 /* The ring uses 256 indices for 255 entries, one of them
236 * needs to be skipped.
237 */
a550c99b 238 diff = bp->tx_prod - bnapi->tx_cons;
faac9c4b
MC		 239 if (unlikely(diff >= TX_DESC_CNT)) {
240 diff &= 0xffff;
241 if (diff == TX_DESC_CNT)
242 diff = MAX_TX_DESC_CNT;
243 }
e89bbf10
MC		 244 return (bp->tx_ring_size - diff);
245}
246
b6016b76
MC		 247static u32
248bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
249{
1b8227c4
MC		 250 u32 val;
251
252 spin_lock_bh(&bp->indirect_lock);
b6016b76 253 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
1b8227c4
MC		 254 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
255 spin_unlock_bh(&bp->indirect_lock);
256 return val;
b6016b76
MC		 257}
258
259static void
260bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
261{
1b8227c4 262 spin_lock_bh(&bp->indirect_lock);
b6016b76
MC		 263 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
264 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
1b8227c4 265 spin_unlock_bh(&bp->indirect_lock);
b6016b76
MC		 266}
267
2726d6e1
MC		 268static void
269bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
270{
271 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
272}
273
274static u32
275bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
276{
277 return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
278}
279
b6016b76
MC		 280static void
281bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
282{
283 offset += cid_addr;
1b8227c4 284 spin_lock_bh(&bp->indirect_lock);
59b47d8a
MC		 285 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
286 int i;
287
288 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
289 REG_WR(bp, BNX2_CTX_CTX_CTRL,
290 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
291 for (i = 0; i < 5; i++) {
292 u32 val;
293 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
294 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
295 break;
296 udelay(5);
297 }
298 } else {
299 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
300 REG_WR(bp, BNX2_CTX_DATA, val);
301 }
1b8227c4 302 spin_unlock_bh(&bp->indirect_lock);
b6016b76
MC		 303}
304
305static int
306bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
307{
308 u32 val1;
309 int i, ret;
310
583c28e5 311 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 312 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
313 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
314
315 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
316 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
317
318 udelay(40);
319 }
320
321 val1 = (bp->phy_addr << 21) | (reg << 16) |
322 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
323 BNX2_EMAC_MDIO_COMM_START_BUSY;
324 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
325
326 for (i = 0; i < 50; i++) {
327 udelay(10);
328
329 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
330 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
331 udelay(5);
332
333 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
334 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
335
336 break;
337 }
338 }
339
340 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
341 *val = 0x0;
342 ret = -EBUSY;
343 }
344 else {
345 *val = val1;
346 ret = 0;
347 }
348
583c28e5 349 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 350 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
351 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
352
353 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
354 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
355
356 udelay(40);
357 }
358
359 return ret;
360}
361
362static int
363bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
364{
365 u32 val1;
366 int i, ret;
367
583c28e5 368 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 369 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
370 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
371
372 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
373 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
374
375 udelay(40);
376 }
377
378 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
379 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
380 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
381 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
6aa20a22 382
b6016b76
MC		 383 for (i = 0; i < 50; i++) {
384 udelay(10);
385
386 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
387 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
388 udelay(5);
389 break;
390 }
391 }
392
393 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
394 ret = -EBUSY;
395 else
396 ret = 0;
397
583c28e5 398 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
b6016b76
MC		 399 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
400 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
401
402 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
403 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
404
405 udelay(40);
406 }
407
408 return ret;
409}
410
411static void
412bnx2_disable_int(struct bnx2 *bp)
413{
b4b36042
MC		 414 int i;
415 struct bnx2_napi *bnapi;
416
417 for (i = 0; i < bp->irq_nvecs; i++) {
418 bnapi = &bp->bnx2_napi[i];
419 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
420 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
421 }
b6016b76
MC		 422 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
423}
424
425static void
426bnx2_enable_int(struct bnx2 *bp)
427{
b4b36042
MC		 428 int i;
429 struct bnx2_napi *bnapi;
35efa7c1 430
b4b36042
MC		 431 for (i = 0; i < bp->irq_nvecs; i++) {
432 bnapi = &bp->bnx2_napi[i];
1269a8a6 433
b4b36042
MC		 434 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
435 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
436 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
437 bnapi->last_status_idx);
b6016b76 438
b4b36042
MC		 439 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
440 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
441 bnapi->last_status_idx);
442 }
bf5295bb 443 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
b6016b76
MC		 444}
445
446static void
447bnx2_disable_int_sync(struct bnx2 *bp)
448{
b4b36042
MC		 449 int i;
450
b6016b76
MC		 451 atomic_inc(&bp->intr_sem);
452 bnx2_disable_int(bp);
b4b36042
MC		 453 for (i = 0; i < bp->irq_nvecs; i++)
454 synchronize_irq(bp->irq_tbl[i].vector);
b6016b76
MC		 455}
456
35efa7c1
MC		 457static void
458bnx2_napi_disable(struct bnx2 *bp)
459{
b4b36042
MC		 460 int i;
461
462 for (i = 0; i < bp->irq_nvecs; i++)
463 napi_disable(&bp->bnx2_napi[i].napi);
35efa7c1
MC		 464}
465
466static void
467bnx2_napi_enable(struct bnx2 *bp)
468{
b4b36042
MC		 469 int i;
470
471 for (i = 0; i < bp->irq_nvecs; i++)
472 napi_enable(&bp->bnx2_napi[i].napi);
35efa7c1
MC		 473}
474
b6016b76
MC		 475static void
476bnx2_netif_stop(struct bnx2 *bp)
477{
478 bnx2_disable_int_sync(bp);
479 if (netif_running(bp->dev)) {
35efa7c1 480 bnx2_napi_disable(bp);
b6016b76
MC		 481 netif_tx_disable(bp->dev);
482 bp->dev->trans_start = jiffies; /* prevent tx timeout */
483 }
484}
485
486static void
487bnx2_netif_start(struct bnx2 *bp)
488{
489 if (atomic_dec_and_test(&bp->intr_sem)) {
490 if (netif_running(bp->dev)) {
491 netif_wake_queue(bp->dev);
35efa7c1 492 bnx2_napi_enable(bp);
b6016b76
MC		 493 bnx2_enable_int(bp);
494 }
495 }
496}
497
498static void
499bnx2_free_mem(struct bnx2 *bp)
500{
13daffa2
MC		 501 int i;
502
59b47d8a
MC		 503 for (i = 0; i < bp->ctx_pages; i++) {
504 if (bp->ctx_blk[i]) {
505 pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
506 bp->ctx_blk[i],
507 bp->ctx_blk_mapping[i]);
508 bp->ctx_blk[i] = NULL;
509 }
510 }
b6016b76 511 if (bp->status_blk) {
0f31f994 512 pci_free_consistent(bp->pdev, bp->status_stats_size,
b6016b76
MC		 513 bp->status_blk, bp->status_blk_mapping);
514 bp->status_blk = NULL;
0f31f994 515 bp->stats_blk = NULL;
b6016b76
MC		 516 }
517 if (bp->tx_desc_ring) {
e343d55c 518 pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
b6016b76
MC		 519 bp->tx_desc_ring, bp->tx_desc_mapping);
520 bp->tx_desc_ring = NULL;
521 }
b4558ea9
JJ		 522 kfree(bp->tx_buf_ring);
523 bp->tx_buf_ring = NULL;
13daffa2
MC		 524 for (i = 0; i < bp->rx_max_ring; i++) {
525 if (bp->rx_desc_ring[i])
e343d55c 526 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
13daffa2
MC		 527 bp->rx_desc_ring[i],
528 bp->rx_desc_mapping[i]);
529 bp->rx_desc_ring[i] = NULL;
530 }
531 vfree(bp->rx_buf_ring);
b4558ea9 532 bp->rx_buf_ring = NULL;
47bf4246
MC		 533 for (i = 0; i < bp->rx_max_pg_ring; i++) {
534 if (bp->rx_pg_desc_ring[i])
535 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
536 bp->rx_pg_desc_ring[i],
537 bp->rx_pg_desc_mapping[i]);
538 bp->rx_pg_desc_ring[i] = NULL;
539 }
540 if (bp->rx_pg_ring)
541 vfree(bp->rx_pg_ring);
542 bp->rx_pg_ring = NULL;
b6016b76
MC		 543}
544
545static int
546bnx2_alloc_mem(struct bnx2 *bp)
547{
0f31f994 548 int i, status_blk_size;
13daffa2 549
e343d55c 550 bp->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
b6016b76
MC		 551 if (bp->tx_buf_ring == NULL)
552 return -ENOMEM;
553
e343d55c 554 bp->tx_desc_ring = pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
b6016b76
MC		 555 &bp->tx_desc_mapping);
556 if (bp->tx_desc_ring == NULL)
557 goto alloc_mem_err;
558
e343d55c 559 bp->rx_buf_ring = vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
b6016b76
MC		 560 if (bp->rx_buf_ring == NULL)
561 goto alloc_mem_err;
562
e343d55c 563 memset(bp->rx_buf_ring, 0, SW_RXBD_RING_SIZE * bp->rx_max_ring);
13daffa2
MC		 564
565 for (i = 0; i < bp->rx_max_ring; i++) {
566 bp->rx_desc_ring[i] =
e343d55c 567 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
13daffa2
MC		 568 &bp->rx_desc_mapping[i]);
569 if (bp->rx_desc_ring[i] == NULL)
570 goto alloc_mem_err;
571
572 }
b6016b76 573
47bf4246
MC		 574 if (bp->rx_pg_ring_size) {
575 bp->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
576 bp->rx_max_pg_ring);
577 if (bp->rx_pg_ring == NULL)
578 goto alloc_mem_err;
579
580 memset(bp->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
581 bp->rx_max_pg_ring);
582 }
583
584 for (i = 0; i < bp->rx_max_pg_ring; i++) {
585 bp->rx_pg_desc_ring[i] =
586 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
587 &bp->rx_pg_desc_mapping[i]);
588 if (bp->rx_pg_desc_ring[i] == NULL)
589 goto alloc_mem_err;
590
591 }
592
0f31f994
MC		 593 /* Combine status and statistics blocks into one allocation. */
594 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
f86e82fb 595 if (bp->flags & BNX2_FLAG_MSIX_CAP)
b4b36042
MC		 596 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
597 BNX2_SBLK_MSIX_ALIGN_SIZE);
0f31f994
MC		 598 bp->status_stats_size = status_blk_size +
599 sizeof(struct statistics_block);
600
601 bp->status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
b6016b76
MC		 602 &bp->status_blk_mapping);
603 if (bp->status_blk == NULL)
604 goto alloc_mem_err;
605
0f31f994 606 memset(bp->status_blk, 0, bp->status_stats_size);
b6016b76 607
b4b36042 608 bp->bnx2_napi[0].status_blk = bp->status_blk;
f86e82fb 609 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
b4b36042
MC		 610 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
611 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
612
57851d84 613 bnapi->status_blk_msix = (void *)
b4b36042
MC		 614 ((unsigned long) bp->status_blk +
615 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
616 bnapi->int_num = i << 24;
617 }
618 }
35efa7c1 619
0f31f994
MC		 620 bp->stats_blk = (void *) ((unsigned long) bp->status_blk +
621 status_blk_size);
b6016b76 622
0f31f994 623 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
b6016b76 624
59b47d8a
MC		 625 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
626 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
627 if (bp->ctx_pages == 0)
628 bp->ctx_pages = 1;
629 for (i = 0; i < bp->ctx_pages; i++) {
630 bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
631 BCM_PAGE_SIZE,
632 &bp->ctx_blk_mapping[i]);
633 if (bp->ctx_blk[i] == NULL)
634 goto alloc_mem_err;
635 }
636 }
b6016b76
MC		 637 return 0;
638
639alloc_mem_err:
640 bnx2_free_mem(bp);
641 return -ENOMEM;
642}
643
e3648b3d
MC		 644static void
645bnx2_report_fw_link(struct bnx2 *bp)
646{
647 u32 fw_link_status = 0;
648
583c28e5 649 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 650 return;
651
e3648b3d
MC		 652 if (bp->link_up) {
653 u32 bmsr;
654
655 switch (bp->line_speed) {
656 case SPEED_10:
657 if (bp->duplex == DUPLEX_HALF)
658 fw_link_status = BNX2_LINK_STATUS_10HALF;
659 else
660 fw_link_status = BNX2_LINK_STATUS_10FULL;
661 break;
662 case SPEED_100:
663 if (bp->duplex == DUPLEX_HALF)
664 fw_link_status = BNX2_LINK_STATUS_100HALF;
665 else
666 fw_link_status = BNX2_LINK_STATUS_100FULL;
667 break;
668 case SPEED_1000:
669 if (bp->duplex == DUPLEX_HALF)
670 fw_link_status = BNX2_LINK_STATUS_1000HALF;
671 else
672 fw_link_status = BNX2_LINK_STATUS_1000FULL;
673 break;
674 case SPEED_2500:
675 if (bp->duplex == DUPLEX_HALF)
676 fw_link_status = BNX2_LINK_STATUS_2500HALF;
677 else
678 fw_link_status = BNX2_LINK_STATUS_2500FULL;
679 break;
680 }
681
682 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
683
684 if (bp->autoneg) {
685 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
686
ca58c3af
MC		 687 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
688 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
e3648b3d
MC		 689
690 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
583c28e5 691 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
e3648b3d
MC		 692 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
693 else
694 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
695 }
696 }
697 else
698 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
699
2726d6e1 700 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
e3648b3d
MC		 701}
702
9b1084b8
MC		 703static char *
704bnx2_xceiver_str(struct bnx2 *bp)
705{
706 return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
583c28e5 707 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
9b1084b8
MC		 708 "Copper"));
709}
710
b6016b76
MC		 711static void
712bnx2_report_link(struct bnx2 *bp)
713{
714 if (bp->link_up) {
715 netif_carrier_on(bp->dev);
9b1084b8
MC		 716 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
717 bnx2_xceiver_str(bp));
b6016b76
MC		 718
719 printk("%d Mbps ", bp->line_speed);
720
721 if (bp->duplex == DUPLEX_FULL)
722 printk("full duplex");
723 else
724 printk("half duplex");
725
726 if (bp->flow_ctrl) {
727 if (bp->flow_ctrl & FLOW_CTRL_RX) {
728 printk(", receive ");
729 if (bp->flow_ctrl & FLOW_CTRL_TX)
730 printk("& transmit ");
731 }
732 else {
733 printk(", transmit ");
734 }
735 printk("flow control ON");
736 }
737 printk("\n");
738 }
739 else {
740 netif_carrier_off(bp->dev);
9b1084b8
MC		 741 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
742 bnx2_xceiver_str(bp));
b6016b76 743 }
e3648b3d
MC		 744
745 bnx2_report_fw_link(bp);
b6016b76
MC		 746}
747
748static void
749bnx2_resolve_flow_ctrl(struct bnx2 *bp)
750{
751 u32 local_adv, remote_adv;
752
753 bp->flow_ctrl = 0;
6aa20a22 754 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
b6016b76
MC		 755 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
756
757 if (bp->duplex == DUPLEX_FULL) {
758 bp->flow_ctrl = bp->req_flow_ctrl;
759 }
760 return;
761 }
762
763 if (bp->duplex != DUPLEX_FULL) {
764 return;
765 }
766
583c28e5 767 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
5b0c76ad
MC		 768 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
769 u32 val;
770
771 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
772 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
773 bp->flow_ctrl |= FLOW_CTRL_TX;
774 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
775 bp->flow_ctrl |= FLOW_CTRL_RX;
776 return;
777 }
778
ca58c3af
MC		 779 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
780 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76 781
583c28e5 782 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 783 u32 new_local_adv = 0;
784 u32 new_remote_adv = 0;
785
786 if (local_adv & ADVERTISE_1000XPAUSE)
787 new_local_adv |= ADVERTISE_PAUSE_CAP;
788 if (local_adv & ADVERTISE_1000XPSE_ASYM)
789 new_local_adv |= ADVERTISE_PAUSE_ASYM;
790 if (remote_adv & ADVERTISE_1000XPAUSE)
791 new_remote_adv |= ADVERTISE_PAUSE_CAP;
792 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
793 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
794
795 local_adv = new_local_adv;
796 remote_adv = new_remote_adv;
797 }
798
799 /* See Table 28B-3 of 802.3ab-1999 spec. */
800 if (local_adv & ADVERTISE_PAUSE_CAP) {
801 if(local_adv & ADVERTISE_PAUSE_ASYM) {
802 if (remote_adv & ADVERTISE_PAUSE_CAP) {
803 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
804 }
805 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
806 bp->flow_ctrl = FLOW_CTRL_RX;
807 }
808 }
809 else {
810 if (remote_adv & ADVERTISE_PAUSE_CAP) {
811 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
812 }
813 }
814 }
815 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
816 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
817 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
818
819 bp->flow_ctrl = FLOW_CTRL_TX;
820 }
821 }
822}
823
27a005b8
MC		 824static int
825bnx2_5709s_linkup(struct bnx2 *bp)
826{
827 u32 val, speed;
828
829 bp->link_up = 1;
830
831 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
832 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
833 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
834
835 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
836 bp->line_speed = bp->req_line_speed;
837 bp->duplex = bp->req_duplex;
838 return 0;
839 }
840 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
841 switch (speed) {
842 case MII_BNX2_GP_TOP_AN_SPEED_10:
843 bp->line_speed = SPEED_10;
844 break;
845 case MII_BNX2_GP_TOP_AN_SPEED_100:
846 bp->line_speed = SPEED_100;
847 break;
848 case MII_BNX2_GP_TOP_AN_SPEED_1G:
849 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
850 bp->line_speed = SPEED_1000;
851 break;
852 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
853 bp->line_speed = SPEED_2500;
854 break;
855 }
856 if (val & MII_BNX2_GP_TOP_AN_FD)
857 bp->duplex = DUPLEX_FULL;
858 else
859 bp->duplex = DUPLEX_HALF;
860 return 0;
861}
862
b6016b76 863static int
5b0c76ad
MC		 864bnx2_5708s_linkup(struct bnx2 *bp)
865{
866 u32 val;
867
868 bp->link_up = 1;
869 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
870 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
871 case BCM5708S_1000X_STAT1_SPEED_10:
872 bp->line_speed = SPEED_10;
873 break;
874 case BCM5708S_1000X_STAT1_SPEED_100:
875 bp->line_speed = SPEED_100;
876 break;
877 case BCM5708S_1000X_STAT1_SPEED_1G:
878 bp->line_speed = SPEED_1000;
879 break;
880 case BCM5708S_1000X_STAT1_SPEED_2G5:
881 bp->line_speed = SPEED_2500;
882 break;
883 }
884 if (val & BCM5708S_1000X_STAT1_FD)
885 bp->duplex = DUPLEX_FULL;
886 else
887 bp->duplex = DUPLEX_HALF;
888
889 return 0;
890}
891
892static int
893bnx2_5706s_linkup(struct bnx2 *bp)
b6016b76
MC		 894{
895 u32 bmcr, local_adv, remote_adv, common;
896
897 bp->link_up = 1;
898 bp->line_speed = SPEED_1000;
899
ca58c3af 900 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 901 if (bmcr & BMCR_FULLDPLX) {
902 bp->duplex = DUPLEX_FULL;
903 }
904 else {
905 bp->duplex = DUPLEX_HALF;
906 }
907
908 if (!(bmcr & BMCR_ANENABLE)) {
909 return 0;
910 }
911
ca58c3af
MC		 912 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
913 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76
MC		 914
915 common = local_adv & remote_adv;
916 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
917
918 if (common & ADVERTISE_1000XFULL) {
919 bp->duplex = DUPLEX_FULL;
920 }
921 else {
922 bp->duplex = DUPLEX_HALF;
923 }
924 }
925
926 return 0;
927}
928
929static int
930bnx2_copper_linkup(struct bnx2 *bp)
931{
932 u32 bmcr;
933
ca58c3af 934 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 935 if (bmcr & BMCR_ANENABLE) {
936 u32 local_adv, remote_adv, common;
937
938 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
939 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
940
941 common = local_adv & (remote_adv >> 2);
942 if (common & ADVERTISE_1000FULL) {
943 bp->line_speed = SPEED_1000;
944 bp->duplex = DUPLEX_FULL;
945 }
946 else if (common & ADVERTISE_1000HALF) {
947 bp->line_speed = SPEED_1000;
948 bp->duplex = DUPLEX_HALF;
949 }
950 else {
ca58c3af
MC		 951 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
952 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76
MC		 953
954 common = local_adv & remote_adv;
955 if (common & ADVERTISE_100FULL) {
956 bp->line_speed = SPEED_100;
957 bp->duplex = DUPLEX_FULL;
958 }
959 else if (common & ADVERTISE_100HALF) {
960 bp->line_speed = SPEED_100;
961 bp->duplex = DUPLEX_HALF;
962 }
963 else if (common & ADVERTISE_10FULL) {
964 bp->line_speed = SPEED_10;
965 bp->duplex = DUPLEX_FULL;
966 }
967 else if (common & ADVERTISE_10HALF) {
968 bp->line_speed = SPEED_10;
969 bp->duplex = DUPLEX_HALF;
970 }
971 else {
972 bp->line_speed = 0;
973 bp->link_up = 0;
974 }
975 }
976 }
977 else {
978 if (bmcr & BMCR_SPEED100) {
979 bp->line_speed = SPEED_100;
980 }
981 else {
982 bp->line_speed = SPEED_10;
983 }
984 if (bmcr & BMCR_FULLDPLX) {
985 bp->duplex = DUPLEX_FULL;
986 }
987 else {
988 bp->duplex = DUPLEX_HALF;
989 }
990 }
991
992 return 0;
993}
994
83e3fc89
MC		 995static void
996bnx2_init_rx_context0(struct bnx2 *bp)
997{
998 u32 val, rx_cid_addr = GET_CID_ADDR(RX_CID);
999
1000 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1001 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1002 val |= 0x02 << 8;
1003
1004 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1005 u32 lo_water, hi_water;
1006
1007 if (bp->flow_ctrl & FLOW_CTRL_TX)
1008 lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1009 else
1010 lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1011 if (lo_water >= bp->rx_ring_size)
1012 lo_water = 0;
1013
1014 hi_water = bp->rx_ring_size / 4;
1015
1016 if (hi_water <= lo_water)
1017 lo_water = 0;
1018
1019 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1020 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1021
1022 if (hi_water > 0xf)
1023 hi_water = 0xf;
1024 else if (hi_water == 0)
1025 lo_water = 0;
1026 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1027 }
1028 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1029}
1030
b6016b76
MC		 1031static int
1032bnx2_set_mac_link(struct bnx2 *bp)
1033{
1034 u32 val;
1035
1036 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1037 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1038 (bp->duplex == DUPLEX_HALF)) {
1039 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1040 }
1041
1042 /* Configure the EMAC mode register. */
1043 val = REG_RD(bp, BNX2_EMAC_MODE);
1044
1045 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
5b0c76ad 1046 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
59b47d8a 1047 BNX2_EMAC_MODE_25G_MODE);
b6016b76
MC		 1048
1049 if (bp->link_up) {
5b0c76ad
MC		 1050 switch (bp->line_speed) {
1051 case SPEED_10:
59b47d8a
MC		 1052 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1053 val |= BNX2_EMAC_MODE_PORT_MII_10M;
5b0c76ad
MC		 1054 break;
1055 }
1056 /* fall through */
1057 case SPEED_100:
1058 val |= BNX2_EMAC_MODE_PORT_MII;
1059 break;
1060 case SPEED_2500:
59b47d8a 1061 val |= BNX2_EMAC_MODE_25G_MODE;
5b0c76ad
MC		 1062 /* fall through */
1063 case SPEED_1000:
1064 val |= BNX2_EMAC_MODE_PORT_GMII;
1065 break;
1066 }
b6016b76
MC		 1067 }
1068 else {
1069 val |= BNX2_EMAC_MODE_PORT_GMII;
1070 }
1071
1072 /* Set the MAC to operate in the appropriate duplex mode. */
1073 if (bp->duplex == DUPLEX_HALF)
1074 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1075 REG_WR(bp, BNX2_EMAC_MODE, val);
1076
1077 /* Enable/disable rx PAUSE. */
1078 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1079
1080 if (bp->flow_ctrl & FLOW_CTRL_RX)
1081 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1082 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1083
1084 /* Enable/disable tx PAUSE. */
1085 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1086 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1087
1088 if (bp->flow_ctrl & FLOW_CTRL_TX)
1089 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1090 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1091
1092 /* Acknowledge the interrupt. */
1093 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1094
83e3fc89
MC		 1095 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1096 bnx2_init_rx_context0(bp);
1097
b6016b76
MC		 1098 return 0;
1099}
1100
27a005b8
MC		 1101static void
1102bnx2_enable_bmsr1(struct bnx2 *bp)
1103{
583c28e5 1104 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
27a005b8
MC		 1105 (CHIP_NUM(bp) == CHIP_NUM_5709))
1106 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1107 MII_BNX2_BLK_ADDR_GP_STATUS);
1108}
1109
1110static void
1111bnx2_disable_bmsr1(struct bnx2 *bp)
1112{
583c28e5 1113 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
27a005b8
MC		 1114 (CHIP_NUM(bp) == CHIP_NUM_5709))
1115 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1116 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1117}
1118
605a9e20
MC		 1119static int
1120bnx2_test_and_enable_2g5(struct bnx2 *bp)
1121{
1122 u32 up1;
1123 int ret = 1;
1124
583c28e5 1125 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1126 return 0;
1127
1128 if (bp->autoneg & AUTONEG_SPEED)
1129 bp->advertising |= ADVERTISED_2500baseX_Full;
1130
27a005b8
MC		 1131 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1132 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1133
605a9e20
MC		 1134 bnx2_read_phy(bp, bp->mii_up1, &up1);
1135 if (!(up1 & BCM5708S_UP1_2G5)) {
1136 up1 |= BCM5708S_UP1_2G5;
1137 bnx2_write_phy(bp, bp->mii_up1, up1);
1138 ret = 0;
1139 }
1140
27a005b8
MC		 1141 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1142 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1143 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1144
605a9e20
MC		 1145 return ret;
1146}
1147
1148static int
1149bnx2_test_and_disable_2g5(struct bnx2 *bp)
1150{
1151 u32 up1;
1152 int ret = 0;
1153
583c28e5 1154 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1155 return 0;
1156
27a005b8
MC		 1157 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1158 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1159
605a9e20
MC		 1160 bnx2_read_phy(bp, bp->mii_up1, &up1);
1161 if (up1 & BCM5708S_UP1_2G5) {
1162 up1 &= ~BCM5708S_UP1_2G5;
1163 bnx2_write_phy(bp, bp->mii_up1, up1);
1164 ret = 1;
1165 }
1166
27a005b8
MC		 1167 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1168 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1169 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1170
605a9e20
MC		 1171 return ret;
1172}
1173
1174static void
1175bnx2_enable_forced_2g5(struct bnx2 *bp)
1176{
1177 u32 bmcr;
1178
583c28e5 1179 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1180 return;
1181
27a005b8
MC		 1182 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1183 u32 val;
1184
1185 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1186 MII_BNX2_BLK_ADDR_SERDES_DIG);
1187 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1188 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1189 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1190 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1191
1192 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1193 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1194 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1195
1196 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
605a9e20
MC		 1197 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1198 bmcr |= BCM5708S_BMCR_FORCE_2500;
1199 }
1200
1201 if (bp->autoneg & AUTONEG_SPEED) {
1202 bmcr &= ~BMCR_ANENABLE;
1203 if (bp->req_duplex == DUPLEX_FULL)
1204 bmcr |= BMCR_FULLDPLX;
1205 }
1206 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1207}
1208
1209static void
1210bnx2_disable_forced_2g5(struct bnx2 *bp)
1211{
1212 u32 bmcr;
1213
583c28e5 1214 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1215 return;
1216
27a005b8
MC		 1217 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1218 u32 val;
1219
1220 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1221 MII_BNX2_BLK_ADDR_SERDES_DIG);
1222 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1223 val &= ~MII_BNX2_SD_MISC1_FORCE;
1224 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1225
1226 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1227 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1228 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1229
1230 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
605a9e20
MC		 1231 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1232 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1233 }
1234
1235 if (bp->autoneg & AUTONEG_SPEED)
1236 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1237 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1238}
1239
b2fadeae
MC		 1240static void
1241bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1242{
1243 u32 val;
1244
1245 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1246 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1247 if (start)
1248 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1249 else
1250 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1251}
1252
b6016b76
MC		 1253static int
1254bnx2_set_link(struct bnx2 *bp)
1255{
1256 u32 bmsr;
1257 u8 link_up;
1258
80be4434 1259 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
b6016b76
MC		 1260 bp->link_up = 1;
1261 return 0;
1262 }
1263
583c28e5 1264 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 1265 return 0;
1266
b6016b76
MC		 1267 link_up = bp->link_up;
1268
27a005b8
MC		 1269 bnx2_enable_bmsr1(bp);
1270 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1271 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1272 bnx2_disable_bmsr1(bp);
b6016b76 1273
583c28e5 1274 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
b6016b76 1275 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
a2724e25 1276 u32 val, an_dbg;
b6016b76 1277
583c28e5 1278 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
b2fadeae 1279 bnx2_5706s_force_link_dn(bp, 0);
583c28e5 1280 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
b2fadeae 1281 }
b6016b76 1282 val = REG_RD(bp, BNX2_EMAC_STATUS);
a2724e25
MC		 1283
1284 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1285 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1286 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1287
1288 if ((val & BNX2_EMAC_STATUS_LINK) &&
1289 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
b6016b76
MC		 1290 bmsr |= BMSR_LSTATUS;
1291 else
1292 bmsr &= ~BMSR_LSTATUS;
1293 }
1294
1295 if (bmsr & BMSR_LSTATUS) {
1296 bp->link_up = 1;
1297
583c28e5 1298 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5b0c76ad
MC		 1299 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1300 bnx2_5706s_linkup(bp);
1301 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1302 bnx2_5708s_linkup(bp);
27a005b8
MC		 1303 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1304 bnx2_5709s_linkup(bp);
b6016b76
MC		 1305 }
1306 else {
1307 bnx2_copper_linkup(bp);
1308 }
1309 bnx2_resolve_flow_ctrl(bp);
1310 }
1311 else {
583c28e5 1312 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
605a9e20
MC		 1313 (bp->autoneg & AUTONEG_SPEED))
1314 bnx2_disable_forced_2g5(bp);
b6016b76 1315
583c28e5 1316 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
b2fadeae
MC		 1317 u32 bmcr;
1318
1319 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1320 bmcr |= BMCR_ANENABLE;
1321 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1322
583c28e5 1323 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
b2fadeae 1324 }
b6016b76
MC		 1325 bp->link_up = 0;
1326 }
1327
1328 if (bp->link_up != link_up) {
1329 bnx2_report_link(bp);
1330 }
1331
1332 bnx2_set_mac_link(bp);
1333
1334 return 0;
1335}
1336
1337static int
1338bnx2_reset_phy(struct bnx2 *bp)
1339{
1340 int i;
1341 u32 reg;
1342
ca58c3af 1343 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
b6016b76
MC		 1344
1345#define PHY_RESET_MAX_WAIT 100
1346 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1347 udelay(10);
1348
ca58c3af 1349 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
b6016b76
MC		 1350 if (!(reg & BMCR_RESET)) {
1351 udelay(20);
1352 break;
1353 }
1354 }
1355 if (i == PHY_RESET_MAX_WAIT) {
1356 return -EBUSY;
1357 }
1358 return 0;
1359}
1360
1361static u32
1362bnx2_phy_get_pause_adv(struct bnx2 *bp)
1363{
1364 u32 adv = 0;
1365
1366 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1367 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1368
583c28e5 1369 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1370 adv = ADVERTISE_1000XPAUSE;
1371 }
1372 else {
1373 adv = ADVERTISE_PAUSE_CAP;
1374 }
1375 }
1376 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
583c28e5 1377 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1378 adv = ADVERTISE_1000XPSE_ASYM;
1379 }
1380 else {
1381 adv = ADVERTISE_PAUSE_ASYM;
1382 }
1383 }
1384 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
583c28e5 1385 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1386 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1387 }
1388 else {
1389 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1390 }
1391 }
1392 return adv;
1393}
1394
0d8a6571
MC		 1395static int bnx2_fw_sync(struct bnx2 *, u32, int);
1396
b6016b76 1397static int
0d8a6571
MC		 1398bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1399{
1400 u32 speed_arg = 0, pause_adv;
1401
1402 pause_adv = bnx2_phy_get_pause_adv(bp);
1403
1404 if (bp->autoneg & AUTONEG_SPEED) {
1405 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1406 if (bp->advertising & ADVERTISED_10baseT_Half)
1407 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1408 if (bp->advertising & ADVERTISED_10baseT_Full)
1409 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1410 if (bp->advertising & ADVERTISED_100baseT_Half)
1411 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1412 if (bp->advertising & ADVERTISED_100baseT_Full)
1413 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1414 if (bp->advertising & ADVERTISED_1000baseT_Full)
1415 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1416 if (bp->advertising & ADVERTISED_2500baseX_Full)
1417 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1418 } else {
1419 if (bp->req_line_speed == SPEED_2500)
1420 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1421 else if (bp->req_line_speed == SPEED_1000)
1422 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1423 else if (bp->req_line_speed == SPEED_100) {
1424 if (bp->req_duplex == DUPLEX_FULL)
1425 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1426 else
1427 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1428 } else if (bp->req_line_speed == SPEED_10) {
1429 if (bp->req_duplex == DUPLEX_FULL)
1430 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1431 else
1432 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1433 }
1434 }
1435
1436 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1437 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
c26736ec 1438 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
0d8a6571
MC		 1439 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1440
1441 if (port == PORT_TP)
1442 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1443 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1444
2726d6e1 1445 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
0d8a6571
MC		 1446
1447 spin_unlock_bh(&bp->phy_lock);
1448 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 0);
1449 spin_lock_bh(&bp->phy_lock);
1450
1451 return 0;
1452}
1453
1454static int
1455bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
b6016b76 1456{
605a9e20 1457 u32 adv, bmcr;
b6016b76
MC		 1458 u32 new_adv = 0;
1459
583c28e5 1460 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 1461 return (bnx2_setup_remote_phy(bp, port));
1462
b6016b76
MC		 1463 if (!(bp->autoneg & AUTONEG_SPEED)) {
1464 u32 new_bmcr;
5b0c76ad
MC		 1465 int force_link_down = 0;
1466
605a9e20
MC		 1467 if (bp->req_line_speed == SPEED_2500) {
1468 if (!bnx2_test_and_enable_2g5(bp))
1469 force_link_down = 1;
1470 } else if (bp->req_line_speed == SPEED_1000) {
1471 if (bnx2_test_and_disable_2g5(bp))
1472 force_link_down = 1;
1473 }
ca58c3af 1474 bnx2_read_phy(bp, bp->mii_adv, &adv);
80be4434
MC		 1475 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1476
ca58c3af 1477 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
605a9e20 1478 new_bmcr = bmcr & ~BMCR_ANENABLE;
80be4434 1479 new_bmcr |= BMCR_SPEED1000;
605a9e20 1480
27a005b8
MC		 1481 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1482 if (bp->req_line_speed == SPEED_2500)
1483 bnx2_enable_forced_2g5(bp);
1484 else if (bp->req_line_speed == SPEED_1000) {
1485 bnx2_disable_forced_2g5(bp);
1486 new_bmcr &= ~0x2000;
1487 }
1488
1489 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
605a9e20
MC		 1490 if (bp->req_line_speed == SPEED_2500)
1491 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1492 else
1493 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
5b0c76ad
MC		 1494 }
1495
b6016b76 1496 if (bp->req_duplex == DUPLEX_FULL) {
5b0c76ad 1497 adv |= ADVERTISE_1000XFULL;
b6016b76
MC		 1498 new_bmcr |= BMCR_FULLDPLX;
1499 }
1500 else {
5b0c76ad 1501 adv |= ADVERTISE_1000XHALF;
b6016b76
MC		 1502 new_bmcr &= ~BMCR_FULLDPLX;
1503 }
5b0c76ad 1504 if ((new_bmcr != bmcr) || (force_link_down)) {
b6016b76
MC		 1505 /* Force a link down visible on the other side */
1506 if (bp->link_up) {
ca58c3af 1507 bnx2_write_phy(bp, bp->mii_adv, adv &
5b0c76ad
MC		 1508 ~(ADVERTISE_1000XFULL |
1509 ADVERTISE_1000XHALF));
ca58c3af 1510 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
b6016b76
MC		 1511 BMCR_ANRESTART | BMCR_ANENABLE);
1512
1513 bp->link_up = 0;
1514 netif_carrier_off(bp->dev);
ca58c3af 1515 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
80be4434 1516 bnx2_report_link(bp);
b6016b76 1517 }
ca58c3af
MC		 1518 bnx2_write_phy(bp, bp->mii_adv, adv);
1519 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
605a9e20
MC		 1520 } else {
1521 bnx2_resolve_flow_ctrl(bp);
1522 bnx2_set_mac_link(bp);
b6016b76
MC		 1523 }
1524 return 0;
1525 }
1526
605a9e20 1527 bnx2_test_and_enable_2g5(bp);
5b0c76ad 1528
b6016b76
MC		 1529 if (bp->advertising & ADVERTISED_1000baseT_Full)
1530 new_adv |= ADVERTISE_1000XFULL;
1531
1532 new_adv |= bnx2_phy_get_pause_adv(bp);
1533
ca58c3af
MC		 1534 bnx2_read_phy(bp, bp->mii_adv, &adv);
1535 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1536
1537 bp->serdes_an_pending = 0;
1538 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1539 /* Force a link down visible on the other side */
1540 if (bp->link_up) {
ca58c3af 1541 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
80be4434
MC		 1542 spin_unlock_bh(&bp->phy_lock);
1543 msleep(20);
1544 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 1545 }
1546
ca58c3af
MC		 1547 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1548 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
b6016b76 1549 BMCR_ANENABLE);
f8dd064e
MC		 1550 /* Speed up link-up time when the link partner
1551 * does not autonegotiate which is very common
1552 * in blade servers. Some blade servers use
1553 * IPMI for kerboard input and it's important
1554 * to minimize link disruptions. Autoneg. involves
1555 * exchanging base pages plus 3 next pages and
1556 * normally completes in about 120 msec.
1557 */
1558 bp->current_interval = SERDES_AN_TIMEOUT;
1559 bp->serdes_an_pending = 1;
1560 mod_timer(&bp->timer, jiffies + bp->current_interval);
605a9e20
MC		 1561 } else {
1562 bnx2_resolve_flow_ctrl(bp);
1563 bnx2_set_mac_link(bp);
b6016b76
MC		 1564 }
1565
1566 return 0;
1567}
1568
1569#define ETHTOOL_ALL_FIBRE_SPEED \
583c28e5 1570 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
deaf391b
MC		 1571 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1572 (ADVERTISED_1000baseT_Full)
b6016b76
MC		 1573
1574#define ETHTOOL_ALL_COPPER_SPEED \
1575 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1576 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1577 ADVERTISED_1000baseT_Full)
1578
1579#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1580 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
6aa20a22 1581
b6016b76
MC		 1582#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1583
0d8a6571
MC		 1584static void
1585bnx2_set_default_remote_link(struct bnx2 *bp)
1586{
1587 u32 link;
1588
1589 if (bp->phy_port == PORT_TP)
2726d6e1 1590 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
0d8a6571 1591 else
2726d6e1 1592 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
0d8a6571
MC		 1593
1594 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1595 bp->req_line_speed = 0;
1596 bp->autoneg |= AUTONEG_SPEED;
1597 bp->advertising = ADVERTISED_Autoneg;
1598 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1599 bp->advertising |= ADVERTISED_10baseT_Half;
1600 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1601 bp->advertising |= ADVERTISED_10baseT_Full;
1602 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1603 bp->advertising |= ADVERTISED_100baseT_Half;
1604 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1605 bp->advertising |= ADVERTISED_100baseT_Full;
1606 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1607 bp->advertising |= ADVERTISED_1000baseT_Full;
1608 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1609 bp->advertising |= ADVERTISED_2500baseX_Full;
1610 } else {
1611 bp->autoneg = 0;
1612 bp->advertising = 0;
1613 bp->req_duplex = DUPLEX_FULL;
1614 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1615 bp->req_line_speed = SPEED_10;
1616 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1617 bp->req_duplex = DUPLEX_HALF;
1618 }
1619 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1620 bp->req_line_speed = SPEED_100;
1621 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1622 bp->req_duplex = DUPLEX_HALF;
1623 }
1624 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1625 bp->req_line_speed = SPEED_1000;
1626 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1627 bp->req_line_speed = SPEED_2500;
1628 }
1629}
1630
deaf391b
MC		 1631static void
1632bnx2_set_default_link(struct bnx2 *bp)
1633{
ab59859d
HH		 1634 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1635 bnx2_set_default_remote_link(bp);
1636 return;
1637 }
0d8a6571 1638
deaf391b
MC		 1639 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1640 bp->req_line_speed = 0;
583c28e5 1641 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
deaf391b
MC		 1642 u32 reg;
1643
1644 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1645
2726d6e1 1646 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
deaf391b
MC		 1647 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1648 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1649 bp->autoneg = 0;
1650 bp->req_line_speed = bp->line_speed = SPEED_1000;
1651 bp->req_duplex = DUPLEX_FULL;
1652 }
1653 } else
1654 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1655}
1656
df149d70
MC		 1657static void
1658bnx2_send_heart_beat(struct bnx2 *bp)
1659{
1660 u32 msg;
1661 u32 addr;
1662
1663 spin_lock(&bp->indirect_lock);
1664 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1665 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1666 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1667 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1668 spin_unlock(&bp->indirect_lock);
1669}
1670
0d8a6571
MC		 1671static void
1672bnx2_remote_phy_event(struct bnx2 *bp)
1673{
1674 u32 msg;
1675 u8 link_up = bp->link_up;
1676 u8 old_port;
1677
2726d6e1 1678 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
0d8a6571 1679
df149d70
MC		 1680 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1681 bnx2_send_heart_beat(bp);
1682
1683 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1684
0d8a6571
MC		 1685 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1686 bp->link_up = 0;
1687 else {
1688 u32 speed;
1689
1690 bp->link_up = 1;
1691 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1692 bp->duplex = DUPLEX_FULL;
1693 switch (speed) {
1694 case BNX2_LINK_STATUS_10HALF:
1695 bp->duplex = DUPLEX_HALF;
1696 case BNX2_LINK_STATUS_10FULL:
1697 bp->line_speed = SPEED_10;
1698 break;
1699 case BNX2_LINK_STATUS_100HALF:
1700 bp->duplex = DUPLEX_HALF;
1701 case BNX2_LINK_STATUS_100BASE_T4:
1702 case BNX2_LINK_STATUS_100FULL:
1703 bp->line_speed = SPEED_100;
1704 break;
1705 case BNX2_LINK_STATUS_1000HALF:
1706 bp->duplex = DUPLEX_HALF;
1707 case BNX2_LINK_STATUS_1000FULL:
1708 bp->line_speed = SPEED_1000;
1709 break;
1710 case BNX2_LINK_STATUS_2500HALF:
1711 bp->duplex = DUPLEX_HALF;
1712 case BNX2_LINK_STATUS_2500FULL:
1713 bp->line_speed = SPEED_2500;
1714 break;
1715 default:
1716 bp->line_speed = 0;
1717 break;
1718 }
1719
0d8a6571
MC		 1720 bp->flow_ctrl = 0;
1721 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1722 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1723 if (bp->duplex == DUPLEX_FULL)
1724 bp->flow_ctrl = bp->req_flow_ctrl;
1725 } else {
1726 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
1727 bp->flow_ctrl |= FLOW_CTRL_TX;
1728 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
1729 bp->flow_ctrl |= FLOW_CTRL_RX;
1730 }
1731
1732 old_port = bp->phy_port;
1733 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
1734 bp->phy_port = PORT_FIBRE;
1735 else
1736 bp->phy_port = PORT_TP;
1737
1738 if (old_port != bp->phy_port)
1739 bnx2_set_default_link(bp);
1740
0d8a6571
MC		 1741 }
1742 if (bp->link_up != link_up)
1743 bnx2_report_link(bp);
1744
1745 bnx2_set_mac_link(bp);
1746}
1747
1748static int
1749bnx2_set_remote_link(struct bnx2 *bp)
1750{
1751 u32 evt_code;
1752
2726d6e1 1753 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
0d8a6571
MC		 1754 switch (evt_code) {
1755 case BNX2_FW_EVT_CODE_LINK_EVENT:
1756 bnx2_remote_phy_event(bp);
1757 break;
1758 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
1759 default:
df149d70 1760 bnx2_send_heart_beat(bp);
0d8a6571
MC		 1761 break;
1762 }
1763 return 0;
1764}
1765
b6016b76
MC		 1766static int
1767bnx2_setup_copper_phy(struct bnx2 *bp)
1768{
1769 u32 bmcr;
1770 u32 new_bmcr;
1771
ca58c3af 1772 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1773
1774 if (bp->autoneg & AUTONEG_SPEED) {
1775 u32 adv_reg, adv1000_reg;
1776 u32 new_adv_reg = 0;
1777 u32 new_adv1000_reg = 0;
1778
ca58c3af 1779 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
b6016b76
MC		 1780 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1781 ADVERTISE_PAUSE_ASYM);
1782
1783 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1784 adv1000_reg &= PHY_ALL_1000_SPEED;
1785
1786 if (bp->advertising & ADVERTISED_10baseT_Half)
1787 new_adv_reg |= ADVERTISE_10HALF;
1788 if (bp->advertising & ADVERTISED_10baseT_Full)
1789 new_adv_reg |= ADVERTISE_10FULL;
1790 if (bp->advertising & ADVERTISED_100baseT_Half)
1791 new_adv_reg |= ADVERTISE_100HALF;
1792 if (bp->advertising & ADVERTISED_100baseT_Full)
1793 new_adv_reg |= ADVERTISE_100FULL;
1794 if (bp->advertising & ADVERTISED_1000baseT_Full)
1795 new_adv1000_reg |= ADVERTISE_1000FULL;
6aa20a22 1796
b6016b76
MC		 1797 new_adv_reg |= ADVERTISE_CSMA;
1798
1799 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1800
1801 if ((adv1000_reg != new_adv1000_reg) ||
1802 (adv_reg != new_adv_reg) ||
1803 ((bmcr & BMCR_ANENABLE) == 0)) {
1804
ca58c3af 1805 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
b6016b76 1806 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
ca58c3af 1807 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
b6016b76
MC		 1808 BMCR_ANENABLE);
1809 }
1810 else if (bp->link_up) {
1811 /* Flow ctrl may have changed from auto to forced */
1812 /* or vice-versa. */
1813
1814 bnx2_resolve_flow_ctrl(bp);
1815 bnx2_set_mac_link(bp);
1816 }
1817 return 0;
1818 }
1819
1820 new_bmcr = 0;
1821 if (bp->req_line_speed == SPEED_100) {
1822 new_bmcr |= BMCR_SPEED100;
1823 }
1824 if (bp->req_duplex == DUPLEX_FULL) {
1825 new_bmcr |= BMCR_FULLDPLX;
1826 }
1827 if (new_bmcr != bmcr) {
1828 u32 bmsr;
b6016b76 1829
ca58c3af
MC		 1830 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1831 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
6aa20a22 1832
b6016b76
MC		 1833 if (bmsr & BMSR_LSTATUS) {
1834 /* Force link down */
ca58c3af 1835 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
a16dda0e
MC		 1836 spin_unlock_bh(&bp->phy_lock);
1837 msleep(50);
1838 spin_lock_bh(&bp->phy_lock);
1839
ca58c3af
MC		 1840 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1841 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
b6016b76
MC		 1842 }
1843
ca58c3af 1844 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
b6016b76
MC		 1845
1846 /* Normally, the new speed is setup after the link has
1847 * gone down and up again. In some cases, link will not go
1848 * down so we need to set up the new speed here.
1849 */
1850 if (bmsr & BMSR_LSTATUS) {
1851 bp->line_speed = bp->req_line_speed;
1852 bp->duplex = bp->req_duplex;
1853 bnx2_resolve_flow_ctrl(bp);
1854 bnx2_set_mac_link(bp);
1855 }
27a005b8
MC		 1856 } else {
1857 bnx2_resolve_flow_ctrl(bp);
1858 bnx2_set_mac_link(bp);
b6016b76
MC		 1859 }
1860 return 0;
1861}
1862
1863static int
0d8a6571 1864bnx2_setup_phy(struct bnx2 *bp, u8 port)
b6016b76
MC		 1865{
1866 if (bp->loopback == MAC_LOOPBACK)
1867 return 0;
1868
583c28e5 1869 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
0d8a6571 1870 return (bnx2_setup_serdes_phy(bp, port));
b6016b76
MC		 1871 }
1872 else {
1873 return (bnx2_setup_copper_phy(bp));
1874 }
1875}
1876
27a005b8
MC		 1877static int
1878bnx2_init_5709s_phy(struct bnx2 *bp)
1879{
1880 u32 val;
1881
1882 bp->mii_bmcr = MII_BMCR + 0x10;
1883 bp->mii_bmsr = MII_BMSR + 0x10;
1884 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
1885 bp->mii_adv = MII_ADVERTISE + 0x10;
1886 bp->mii_lpa = MII_LPA + 0x10;
1887 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
1888
1889 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
1890 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
1891
1892 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1893 bnx2_reset_phy(bp);
1894
1895 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
1896
1897 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
1898 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
1899 val |= MII_BNX2_SD_1000XCTL1_FIBER;
1900 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
1901
1902 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1903 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
583c28e5 1904 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
27a005b8
MC		 1905 val |= BCM5708S_UP1_2G5;
1906 else
1907 val &= ~BCM5708S_UP1_2G5;
1908 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
1909
1910 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
1911 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
1912 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
1913 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
1914
1915 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
1916
1917 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
1918 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
1919 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
1920
1921 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1922
1923 return 0;
1924}
1925
b6016b76 1926static int
5b0c76ad
MC		 1927bnx2_init_5708s_phy(struct bnx2 *bp)
1928{
1929 u32 val;
1930
27a005b8
MC		 1931 bnx2_reset_phy(bp);
1932
1933 bp->mii_up1 = BCM5708S_UP1;
1934
5b0c76ad
MC		 1935 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1936 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1937 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1938
1939 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1940 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1941 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1942
1943 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1944 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1945 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1946
583c28e5 1947 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
5b0c76ad
MC		 1948 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1949 val |= BCM5708S_UP1_2G5;
1950 bnx2_write_phy(bp, BCM5708S_UP1, val);
1951 }
1952
1953 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
dda1e390
MC		 1954 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
1955 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
5b0c76ad
MC		 1956 /* increase tx signal amplitude */
1957 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1958 BCM5708S_BLK_ADDR_TX_MISC);
1959 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1960 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1961 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1962 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1963 }
1964
2726d6e1 1965 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
5b0c76ad
MC		 1966 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1967
1968 if (val) {
1969 u32 is_backplane;
1970
2726d6e1 1971 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
5b0c76ad
MC		 1972 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1973 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1974 BCM5708S_BLK_ADDR_TX_MISC);
1975 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1976 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1977 BCM5708S_BLK_ADDR_DIG);
1978 }
1979 }
1980 return 0;
1981}
1982
1983static int
1984bnx2_init_5706s_phy(struct bnx2 *bp)
b6016b76 1985{
27a005b8
MC		 1986 bnx2_reset_phy(bp);
1987
583c28e5 1988 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
b6016b76 1989
59b47d8a
MC		 1990 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1991 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
b6016b76
MC		 1992
1993 if (bp->dev->mtu > 1500) {
1994 u32 val;
1995
1996 /* Set extended packet length bit */
1997 bnx2_write_phy(bp, 0x18, 0x7);
1998 bnx2_read_phy(bp, 0x18, &val);
1999 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2000
2001 bnx2_write_phy(bp, 0x1c, 0x6c00);
2002 bnx2_read_phy(bp, 0x1c, &val);
2003 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2004 }
2005 else {
2006 u32 val;
2007
2008 bnx2_write_phy(bp, 0x18, 0x7);
2009 bnx2_read_phy(bp, 0x18, &val);
2010 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2011
2012 bnx2_write_phy(bp, 0x1c, 0x6c00);
2013 bnx2_read_phy(bp, 0x1c, &val);
2014 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2015 }
2016
2017 return 0;
2018}
2019
2020static int
2021bnx2_init_copper_phy(struct bnx2 *bp)
2022{
5b0c76ad
MC		 2023 u32 val;
2024
27a005b8
MC		 2025 bnx2_reset_phy(bp);
2026
583c28e5 2027 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
b6016b76
MC		 2028 bnx2_write_phy(bp, 0x18, 0x0c00);
2029 bnx2_write_phy(bp, 0x17, 0x000a);
2030 bnx2_write_phy(bp, 0x15, 0x310b);
2031 bnx2_write_phy(bp, 0x17, 0x201f);
2032 bnx2_write_phy(bp, 0x15, 0x9506);
2033 bnx2_write_phy(bp, 0x17, 0x401f);
2034 bnx2_write_phy(bp, 0x15, 0x14e2);
2035 bnx2_write_phy(bp, 0x18, 0x0400);
2036 }
2037
583c28e5 2038 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
b659f44e
MC		 2039 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2040 MII_BNX2_DSP_EXPAND_REG | 0x8);
2041 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2042 val &= ~(1 << 8);
2043 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2044 }
2045
b6016b76 2046 if (bp->dev->mtu > 1500) {
b6016b76
MC		 2047 /* Set extended packet length bit */
2048 bnx2_write_phy(bp, 0x18, 0x7);
2049 bnx2_read_phy(bp, 0x18, &val);
2050 bnx2_write_phy(bp, 0x18, val | 0x4000);
2051
2052 bnx2_read_phy(bp, 0x10, &val);
2053 bnx2_write_phy(bp, 0x10, val | 0x1);
2054 }
2055 else {
b6016b76
MC		 2056 bnx2_write_phy(bp, 0x18, 0x7);
2057 bnx2_read_phy(bp, 0x18, &val);
2058 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2059
2060 bnx2_read_phy(bp, 0x10, &val);
2061 bnx2_write_phy(bp, 0x10, val & ~0x1);
2062 }
2063
5b0c76ad
MC		 2064 /* ethernet@wirespeed */
2065 bnx2_write_phy(bp, 0x18, 0x7007);
2066 bnx2_read_phy(bp, 0x18, &val);
2067 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
b6016b76
MC		 2068 return 0;
2069}
2070
2071
2072static int
2073bnx2_init_phy(struct bnx2 *bp)
2074{
2075 u32 val;
2076 int rc = 0;
2077
583c28e5
MC		 2078 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2079 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
b6016b76 2080
ca58c3af
MC		 2081 bp->mii_bmcr = MII_BMCR;
2082 bp->mii_bmsr = MII_BMSR;
27a005b8 2083 bp->mii_bmsr1 = MII_BMSR;
ca58c3af
MC		 2084 bp->mii_adv = MII_ADVERTISE;
2085 bp->mii_lpa = MII_LPA;
2086
b6016b76
MC		 2087 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2088
583c28e5 2089 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 2090 goto setup_phy;
2091
b6016b76
MC		 2092 bnx2_read_phy(bp, MII_PHYSID1, &val);
2093 bp->phy_id = val << 16;
2094 bnx2_read_phy(bp, MII_PHYSID2, &val);
2095 bp->phy_id |= val & 0xffff;
2096
583c28e5 2097 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5b0c76ad
MC		 2098 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2099 rc = bnx2_init_5706s_phy(bp);
2100 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2101 rc = bnx2_init_5708s_phy(bp);
27a005b8
MC		 2102 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2103 rc = bnx2_init_5709s_phy(bp);
b6016b76
MC		 2104 }
2105 else {
2106 rc = bnx2_init_copper_phy(bp);
2107 }
2108
0d8a6571
MC		 2109setup_phy:
2110 if (!rc)
2111 rc = bnx2_setup_phy(bp, bp->phy_port);
b6016b76
MC		 2112
2113 return rc;
2114}
2115
2116static int
2117bnx2_set_mac_loopback(struct bnx2 *bp)
2118{
2119 u32 mac_mode;
2120
2121 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2122 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2123 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2124 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2125 bp->link_up = 1;
2126 return 0;
2127}
2128
bc5a0690
MC		 2129static int bnx2_test_link(struct bnx2 *);
2130
2131static int
2132bnx2_set_phy_loopback(struct bnx2 *bp)
2133{
2134 u32 mac_mode;
2135 int rc, i;
2136
2137 spin_lock_bh(&bp->phy_lock);
ca58c3af 2138 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
bc5a0690
MC		 2139 BMCR_SPEED1000);
2140 spin_unlock_bh(&bp->phy_lock);
2141 if (rc)
2142 return rc;
2143
2144 for (i = 0; i < 10; i++) {
2145 if (bnx2_test_link(bp) == 0)
2146 break;
80be4434 2147 msleep(100);
bc5a0690
MC		 2148 }
2149
2150 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2151 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2152 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
59b47d8a 2153 BNX2_EMAC_MODE_25G_MODE);
bc5a0690
MC		 2154
2155 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2156 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2157 bp->link_up = 1;
2158 return 0;
2159}
2160
b6016b76 2161static int
b090ae2b 2162bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
b6016b76
MC		 2163{
2164 int i;
2165 u32 val;
2166
b6016b76
MC		 2167 bp->fw_wr_seq++;
2168 msg_data |= bp->fw_wr_seq;
2169
2726d6e1 2170 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
b6016b76
MC		 2171
2172 /* wait for an acknowledgement. */
b090ae2b
MC		 2173 for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
2174 msleep(10);
b6016b76 2175
2726d6e1 2176 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
b6016b76
MC		 2177
2178 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2179 break;
2180 }
b090ae2b
MC		 2181 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2182 return 0;
b6016b76
MC		 2183
2184 /* If we timed out, inform the firmware that this is the case. */
b090ae2b
MC		 2185 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2186 if (!silent)
2187 printk(KERN_ERR PFX "fw sync timeout, reset code = "
2188 "%x\n", msg_data);
b6016b76
MC		 2189
2190 msg_data &= ~BNX2_DRV_MSG_CODE;
2191 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2192
2726d6e1 2193 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
b6016b76 2194
b6016b76
MC		 2195 return -EBUSY;
2196 }
2197
b090ae2b
MC		 2198 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2199 return -EIO;
2200
b6016b76
MC		 2201 return 0;
2202}
2203
59b47d8a
MC		 2204static int
2205bnx2_init_5709_context(struct bnx2 *bp)
2206{
2207 int i, ret = 0;
2208 u32 val;
2209
2210 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2211 val |= (BCM_PAGE_BITS - 8) << 16;
2212 REG_WR(bp, BNX2_CTX_COMMAND, val);
641bdcd5
MC		 2213 for (i = 0; i < 10; i++) {
2214 val = REG_RD(bp, BNX2_CTX_COMMAND);
2215 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2216 break;
2217 udelay(2);
2218 }
2219 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2220 return -EBUSY;
2221
59b47d8a
MC		 2222 for (i = 0; i < bp->ctx_pages; i++) {
2223 int j;
2224
352f7687
MC		 2225 if (bp->ctx_blk[i])
2226 memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2227 else
2228 return -ENOMEM;
2229
59b47d8a
MC		 2230 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2231 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2232 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2233 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2234 (u64) bp->ctx_blk_mapping[i] >> 32);
2235 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2236 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2237 for (j = 0; j < 10; j++) {
2238
2239 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2240 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2241 break;
2242 udelay(5);
2243 }
2244 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2245 ret = -EBUSY;
2246 break;
2247 }
2248 }
2249 return ret;
2250}
2251
b6016b76
MC		 2252static void
2253bnx2_init_context(struct bnx2 *bp)
2254{
2255 u32 vcid;
2256
2257 vcid = 96;
2258 while (vcid) {
2259 u32 vcid_addr, pcid_addr, offset;
7947b20e 2260 int i;
b6016b76
MC		 2261
2262 vcid--;
2263
2264 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2265 u32 new_vcid;
2266
2267 vcid_addr = GET_PCID_ADDR(vcid);
2268 if (vcid & 0x8) {
2269 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2270 }
2271 else {
2272 new_vcid = vcid;
2273 }
2274 pcid_addr = GET_PCID_ADDR(new_vcid);
2275 }
2276 else {
2277 vcid_addr = GET_CID_ADDR(vcid);
2278 pcid_addr = vcid_addr;
2279 }
2280
7947b20e
MC		 2281 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2282 vcid_addr += (i << PHY_CTX_SHIFT);
2283 pcid_addr += (i << PHY_CTX_SHIFT);
b6016b76 2284
5d5d0015 2285 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
7947b20e 2286 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
b6016b76 2287
7947b20e
MC		 2288 /* Zero out the context. */
2289 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
62a8313c 2290 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
7947b20e 2291 }
b6016b76
MC		 2292 }
2293}
2294
2295static int
2296bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2297{
2298 u16 *good_mbuf;
2299 u32 good_mbuf_cnt;
2300 u32 val;
2301
2302 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2303 if (good_mbuf == NULL) {
2304 printk(KERN_ERR PFX "Failed to allocate memory in "
2305 "bnx2_alloc_bad_rbuf\n");
2306 return -ENOMEM;
2307 }
2308
2309 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2310 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2311
2312 good_mbuf_cnt = 0;
2313
2314 /* Allocate a bunch of mbufs and save the good ones in an array. */
2726d6e1 2315 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
b6016b76 2316 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2726d6e1
MC		 2317 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2318 BNX2_RBUF_COMMAND_ALLOC_REQ);
b6016b76 2319
2726d6e1 2320 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
b6016b76
MC		 2321
2322 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2323
2324 /* The addresses with Bit 9 set are bad memory blocks. */
2325 if (!(val & (1 << 9))) {
2326 good_mbuf[good_mbuf_cnt] = (u16) val;
2327 good_mbuf_cnt++;
2328 }
2329
2726d6e1 2330 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
b6016b76
MC		 2331 }
2332
2333 /* Free the good ones back to the mbuf pool thus discarding
2334 * all the bad ones. */
2335 while (good_mbuf_cnt) {
2336 good_mbuf_cnt--;
2337
2338 val = good_mbuf[good_mbuf_cnt];
2339 val = (val << 9) | val | 1;
2340
2726d6e1 2341 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
b6016b76
MC		 2342 }
2343 kfree(good_mbuf);
2344 return 0;
2345}
2346
2347static void
6aa20a22 2348bnx2_set_mac_addr(struct bnx2 *bp)
b6016b76
MC		 2349{
2350 u32 val;
2351 u8 *mac_addr = bp->dev->dev_addr;
2352
2353 val = (mac_addr[0] << 8) | mac_addr[1];
2354
2355 REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
2356
6aa20a22 2357 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
b6016b76
MC		 2358 (mac_addr[4] << 8) | mac_addr[5];
2359
2360 REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
2361}
2362
47bf4246
MC		 2363static inline int
2364bnx2_alloc_rx_page(struct bnx2 *bp, u16 index)
2365{
2366 dma_addr_t mapping;
2367 struct sw_pg *rx_pg = &bp->rx_pg_ring[index];
2368 struct rx_bd *rxbd =
2369 &bp->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2370 struct page *page = alloc_page(GFP_ATOMIC);
2371
2372 if (!page)
2373 return -ENOMEM;
2374 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2375 PCI_DMA_FROMDEVICE);
2376 rx_pg->page = page;
2377 pci_unmap_addr_set(rx_pg, mapping, mapping);
2378 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2379 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2380 return 0;
2381}
2382
2383static void
2384bnx2_free_rx_page(struct bnx2 *bp, u16 index)
2385{
2386 struct sw_pg *rx_pg = &bp->rx_pg_ring[index];
2387 struct page *page = rx_pg->page;
2388
2389 if (!page)
2390 return;
2391
2392 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2393 PCI_DMA_FROMDEVICE);
2394
2395 __free_page(page);
2396 rx_pg->page = NULL;
2397}
2398
b6016b76 2399static inline int
a1f60190 2400bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, u16 index)
b6016b76
MC		 2401{
2402 struct sk_buff *skb;
2403 struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
2404 dma_addr_t mapping;
13daffa2 2405 struct rx_bd *rxbd = &bp->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
b6016b76
MC		 2406 unsigned long align;
2407
932f3772 2408 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
b6016b76
MC		 2409 if (skb == NULL) {
2410 return -ENOMEM;
2411 }
2412
59b47d8a
MC		 2413 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2414 skb_reserve(skb, BNX2_RX_ALIGN - align);
b6016b76 2415
b6016b76
MC		 2416 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2417 PCI_DMA_FROMDEVICE);
2418
2419 rx_buf->skb = skb;
2420 pci_unmap_addr_set(rx_buf, mapping, mapping);
2421
2422 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2423 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2424
a1f60190 2425 bnapi->rx_prod_bseq += bp->rx_buf_use_size;
b6016b76
MC		 2426
2427 return 0;
2428}
2429
da3e4fbe 2430static int
35efa7c1 2431bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
b6016b76 2432{
35efa7c1 2433 struct status_block *sblk = bnapi->status_blk;
b6016b76 2434 u32 new_link_state, old_link_state;
da3e4fbe 2435 int is_set = 1;
b6016b76 2436
da3e4fbe
MC		 2437 new_link_state = sblk->status_attn_bits & event;
2438 old_link_state = sblk->status_attn_bits_ack & event;
b6016b76 2439 if (new_link_state != old_link_state) {
da3e4fbe
MC		 2440 if (new_link_state)
2441 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2442 else
2443 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2444 } else
2445 is_set = 0;
2446
2447 return is_set;
2448}
2449
2450static void
35efa7c1 2451bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
da3e4fbe 2452{
74ecc62d
MC		 2453 spin_lock(&bp->phy_lock);
2454
2455 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
b6016b76 2456 bnx2_set_link(bp);
35efa7c1 2457 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
0d8a6571
MC		 2458 bnx2_set_remote_link(bp);
2459
74ecc62d
MC		 2460 spin_unlock(&bp->phy_lock);
2461
b6016b76
MC		 2462}
2463
ead7270b 2464static inline u16
35efa7c1 2465bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
ead7270b
MC		 2466{
2467 u16 cons;
2468
c76c0475
MC		 2469 if (bnapi->int_num == 0)
2470 cons = bnapi->status_blk->status_tx_quick_consumer_index0;
2471 else
2472 cons = bnapi->status_blk_msix->status_tx_quick_consumer_index;
ead7270b
MC		 2473
2474 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2475 cons++;
2476 return cons;
2477}
2478
57851d84
MC		 2479static int
2480bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
b6016b76
MC		 2481{
2482 u16 hw_cons, sw_cons, sw_ring_cons;
57851d84 2483 int tx_pkt = 0;
b6016b76 2484
35efa7c1 2485 hw_cons = bnx2_get_hw_tx_cons(bnapi);
a550c99b 2486 sw_cons = bnapi->tx_cons;
b6016b76
MC		 2487
2488 while (sw_cons != hw_cons) {
2489 struct sw_bd *tx_buf;
2490 struct sk_buff *skb;
2491 int i, last;
2492
2493 sw_ring_cons = TX_RING_IDX(sw_cons);
2494
2495 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
2496 skb = tx_buf->skb;
1d39ed56 2497
b6016b76 2498 /* partial BD completions possible with TSO packets */
89114afd 2499 if (skb_is_gso(skb)) {
b6016b76
MC		 2500 u16 last_idx, last_ring_idx;
2501
2502 last_idx = sw_cons +
2503 skb_shinfo(skb)->nr_frags + 1;
2504 last_ring_idx = sw_ring_cons +
2505 skb_shinfo(skb)->nr_frags + 1;
2506 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2507 last_idx++;
2508 }
2509 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2510 break;
2511 }
2512 }
1d39ed56 2513
b6016b76
MC		 2514 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
2515 skb_headlen(skb), PCI_DMA_TODEVICE);
2516
2517 tx_buf->skb = NULL;
2518 last = skb_shinfo(skb)->nr_frags;
2519
2520 for (i = 0; i < last; i++) {
2521 sw_cons = NEXT_TX_BD(sw_cons);
2522
2523 pci_unmap_page(bp->pdev,
2524 pci_unmap_addr(
2525 &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
2526 mapping),
2527 skb_shinfo(skb)->frags[i].size,
2528 PCI_DMA_TODEVICE);
2529 }
2530
2531 sw_cons = NEXT_TX_BD(sw_cons);
2532
745720e5 2533 dev_kfree_skb(skb);
57851d84
MC		 2534 tx_pkt++;
2535 if (tx_pkt == budget)
2536 break;
b6016b76 2537
35efa7c1 2538 hw_cons = bnx2_get_hw_tx_cons(bnapi);
b6016b76
MC		 2539 }
2540
a550c99b
MC		 2541 bnapi->hw_tx_cons = hw_cons;
2542 bnapi->tx_cons = sw_cons;
2f8af120
MC		 2543 /* Need to make the tx_cons update visible to bnx2_start_xmit()
2544 * before checking for netif_queue_stopped(). Without the
2545 * memory barrier, there is a small possibility that bnx2_start_xmit()
2546 * will miss it and cause the queue to be stopped forever.
2547 */
2548 smp_mb();
b6016b76 2549
2f8af120 2550 if (unlikely(netif_queue_stopped(bp->dev)) &&
a550c99b 2551 (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh)) {
2f8af120 2552 netif_tx_lock(bp->dev);
b6016b76 2553 if ((netif_queue_stopped(bp->dev)) &&
a550c99b 2554 (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh))
b6016b76 2555 netif_wake_queue(bp->dev);
2f8af120 2556 netif_tx_unlock(bp->dev);
b6016b76 2557 }
57851d84 2558 return tx_pkt;
b6016b76
MC		 2559}
2560
1db82f2a 2561static void
a1f60190
MC		 2562bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_napi *bnapi,
2563 struct sk_buff *skb, int count)
1db82f2a
MC		 2564{
2565 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2566 struct rx_bd *cons_bd, *prod_bd;
2567 dma_addr_t mapping;
2568 int i;
a1f60190
MC		 2569 u16 hw_prod = bnapi->rx_pg_prod, prod;
2570 u16 cons = bnapi->rx_pg_cons;
1db82f2a
MC		 2571
2572 for (i = 0; i < count; i++) {
2573 prod = RX_PG_RING_IDX(hw_prod);
2574
2575 prod_rx_pg = &bp->rx_pg_ring[prod];
2576 cons_rx_pg = &bp->rx_pg_ring[cons];
2577 cons_bd = &bp->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2578 prod_bd = &bp->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2579
2580 if (i == 0 && skb) {
2581 struct page *page;
2582 struct skb_shared_info *shinfo;
2583
2584 shinfo = skb_shinfo(skb);
2585 shinfo->nr_frags--;
2586 page = shinfo->frags[shinfo->nr_frags].page;
2587 shinfo->frags[shinfo->nr_frags].page = NULL;
2588 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2589 PCI_DMA_FROMDEVICE);
2590 cons_rx_pg->page = page;
2591 pci_unmap_addr_set(cons_rx_pg, mapping, mapping);
2592 dev_kfree_skb(skb);
2593 }
2594 if (prod != cons) {
2595 prod_rx_pg->page = cons_rx_pg->page;
2596 cons_rx_pg->page = NULL;
2597 pci_unmap_addr_set(prod_rx_pg, mapping,
2598 pci_unmap_addr(cons_rx_pg, mapping));
2599
2600 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2601 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2602
2603 }
2604 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2605 hw_prod = NEXT_RX_BD(hw_prod);
2606 }
a1f60190
MC		 2607 bnapi->rx_pg_prod = hw_prod;
2608 bnapi->rx_pg_cons = cons;
1db82f2a
MC		 2609}
2610
b6016b76 2611static inline void
a1f60190 2612bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb,
b6016b76
MC		 2613 u16 cons, u16 prod)
2614{
236b6394
MC		 2615 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2616 struct rx_bd *cons_bd, *prod_bd;
2617
2618 cons_rx_buf = &bp->rx_buf_ring[cons];
2619 prod_rx_buf = &bp->rx_buf_ring[prod];
b6016b76
MC		 2620
2621 pci_dma_sync_single_for_device(bp->pdev,
2622 pci_unmap_addr(cons_rx_buf, mapping),
2623 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2624
a1f60190 2625 bnapi->rx_prod_bseq += bp->rx_buf_use_size;
b6016b76 2626
236b6394 2627 prod_rx_buf->skb = skb;
b6016b76 2628
236b6394
MC		 2629 if (cons == prod)
2630 return;
b6016b76 2631
236b6394
MC		 2632 pci_unmap_addr_set(prod_rx_buf, mapping,
2633 pci_unmap_addr(cons_rx_buf, mapping));
2634
3fdfcc2c
MC		 2635 cons_bd = &bp->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2636 prod_bd = &bp->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
236b6394
MC		 2637 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2638 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
b6016b76
MC		 2639}
2640
85833c62 2641static int
a1f60190
MC		 2642bnx2_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb,
2643 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2644 u32 ring_idx)
85833c62
MC		 2645{
2646 int err;
2647 u16 prod = ring_idx & 0xffff;
2648
a1f60190 2649 err = bnx2_alloc_rx_skb(bp, bnapi, prod);
85833c62 2650 if (unlikely(err)) {
a1f60190 2651 bnx2_reuse_rx_skb(bp, bnapi, skb, (u16) (ring_idx >> 16), prod);
1db82f2a
MC		 2652 if (hdr_len) {
2653 unsigned int raw_len = len + 4;
2654 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2655
a1f60190 2656 bnx2_reuse_rx_skb_pages(bp, bnapi, NULL, pages);
1db82f2a 2657 }
85833c62
MC		 2658 return err;
2659 }
2660
2661 skb_reserve(skb, bp->rx_offset);
2662 pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2663 PCI_DMA_FROMDEVICE);
2664
1db82f2a
MC		 2665 if (hdr_len == 0) {
2666 skb_put(skb, len);
2667 return 0;
2668 } else {
2669 unsigned int i, frag_len, frag_size, pages;
2670 struct sw_pg *rx_pg;
a1f60190
MC		 2671 u16 pg_cons = bnapi->rx_pg_cons;
2672 u16 pg_prod = bnapi->rx_pg_prod;
1db82f2a
MC		 2673
2674 frag_size = len + 4 - hdr_len;
2675 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2676 skb_put(skb, hdr_len);
2677
2678 for (i = 0; i < pages; i++) {
2679 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
2680 if (unlikely(frag_len <= 4)) {
2681 unsigned int tail = 4 - frag_len;
2682
a1f60190
MC		 2683 bnapi->rx_pg_cons = pg_cons;
2684 bnapi->rx_pg_prod = pg_prod;
2685 bnx2_reuse_rx_skb_pages(bp, bnapi, NULL,
2686 pages - i);
1db82f2a
MC		 2687 skb->len -= tail;
2688 if (i == 0) {
2689 skb->tail -= tail;
2690 } else {
2691 skb_frag_t *frag =
2692 &skb_shinfo(skb)->frags[i - 1];
2693 frag->size -= tail;
2694 skb->data_len -= tail;
2695 skb->truesize -= tail;
2696 }
2697 return 0;
2698 }
2699 rx_pg = &bp->rx_pg_ring[pg_cons];
2700
2701 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping),
2702 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2703
2704 if (i == pages - 1)
2705 frag_len -= 4;
2706
2707 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
2708 rx_pg->page = NULL;
2709
2710 err = bnx2_alloc_rx_page(bp, RX_PG_RING_IDX(pg_prod));
2711 if (unlikely(err)) {
a1f60190
MC		 2712 bnapi->rx_pg_cons = pg_cons;
2713 bnapi->rx_pg_prod = pg_prod;
2714 bnx2_reuse_rx_skb_pages(bp, bnapi, skb,
2715 pages - i);
1db82f2a
MC		 2716 return err;
2717 }
2718
2719 frag_size -= frag_len;
2720 skb->data_len += frag_len;
2721 skb->truesize += frag_len;
2722 skb->len += frag_len;
2723
2724 pg_prod = NEXT_RX_BD(pg_prod);
2725 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
2726 }
a1f60190
MC		 2727 bnapi->rx_pg_prod = pg_prod;
2728 bnapi->rx_pg_cons = pg_cons;
1db82f2a 2729 }
85833c62
MC		 2730 return 0;
2731}
2732
c09c2627 2733static inline u16
35efa7c1 2734bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
c09c2627 2735{
35efa7c1 2736 u16 cons = bnapi->status_blk->status_rx_quick_consumer_index0;
c09c2627
MC		 2737
2738 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
2739 cons++;
2740 return cons;
2741}
2742
b6016b76 2743static int
35efa7c1 2744bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
b6016b76
MC		 2745{
2746 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2747 struct l2_fhdr *rx_hdr;
1db82f2a 2748 int rx_pkt = 0, pg_ring_used = 0;
b6016b76 2749
35efa7c1 2750 hw_cons = bnx2_get_hw_rx_cons(bnapi);
a1f60190
MC		 2751 sw_cons = bnapi->rx_cons;
2752 sw_prod = bnapi->rx_prod;
b6016b76
MC		 2753
2754 /* Memory barrier necessary as speculative reads of the rx
2755 * buffer can be ahead of the index in the status block
2756 */
2757 rmb();
2758 while (sw_cons != hw_cons) {
1db82f2a 2759 unsigned int len, hdr_len;
ade2bfe7 2760 u32 status;
b6016b76
MC		 2761 struct sw_bd *rx_buf;
2762 struct sk_buff *skb;
236b6394 2763 dma_addr_t dma_addr;
b6016b76
MC		 2764
2765 sw_ring_cons = RX_RING_IDX(sw_cons);
2766 sw_ring_prod = RX_RING_IDX(sw_prod);
2767
2768 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
2769 skb = rx_buf->skb;
236b6394
MC		 2770
2771 rx_buf->skb = NULL;
2772
2773 dma_addr = pci_unmap_addr(rx_buf, mapping);
2774
2775 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
b6016b76
MC		 2776 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2777
2778 rx_hdr = (struct l2_fhdr *) skb->data;
1db82f2a 2779 len = rx_hdr->l2_fhdr_pkt_len;
b6016b76 2780
ade2bfe7 2781 if ((status = rx_hdr->l2_fhdr_status) &
b6016b76
MC		 2782 (L2_FHDR_ERRORS_BAD_CRC |
2783 L2_FHDR_ERRORS_PHY_DECODE |
2784 L2_FHDR_ERRORS_ALIGNMENT |
2785 L2_FHDR_ERRORS_TOO_SHORT |
2786 L2_FHDR_ERRORS_GIANT_FRAME)) {
2787
a1f60190
MC		 2788 bnx2_reuse_rx_skb(bp, bnapi, skb, sw_ring_cons,
2789 sw_ring_prod);
85833c62 2790 goto next_rx;
b6016b76 2791 }
1db82f2a
MC		 2792 hdr_len = 0;
2793 if (status & L2_FHDR_STATUS_SPLIT) {
2794 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
2795 pg_ring_used = 1;
2796 } else if (len > bp->rx_jumbo_thresh) {
2797 hdr_len = bp->rx_jumbo_thresh;
2798 pg_ring_used = 1;
2799 }
2800
2801 len -= 4;
b6016b76 2802
5d5d0015 2803 if (len <= bp->rx_copy_thresh) {
b6016b76
MC		 2804 struct sk_buff *new_skb;
2805
932f3772 2806 new_skb = netdev_alloc_skb(bp->dev, len + 2);
85833c62 2807 if (new_skb == NULL) {
a1f60190 2808 bnx2_reuse_rx_skb(bp, bnapi, skb, sw_ring_cons,
85833c62
MC		 2809 sw_ring_prod);
2810 goto next_rx;
2811 }
b6016b76
MC		 2812
2813 /* aligned copy */
d626f62b
ACM		 2814 skb_copy_from_linear_data_offset(skb, bp->rx_offset - 2,
2815 new_skb->data, len + 2);
b6016b76
MC		 2816 skb_reserve(new_skb, 2);
2817 skb_put(new_skb, len);
b6016b76 2818
a1f60190 2819 bnx2_reuse_rx_skb(bp, bnapi, skb,
b6016b76
MC		 2820 sw_ring_cons, sw_ring_prod);
2821
2822 skb = new_skb;
a1f60190
MC		 2823 } else if (unlikely(bnx2_rx_skb(bp, bnapi, skb, len, hdr_len,
2824 dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
b6016b76 2825 goto next_rx;
b6016b76
MC		 2826
2827 skb->protocol = eth_type_trans(skb, bp->dev);
2828
2829 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
d1e100ba 2830 (ntohs(skb->protocol) != 0x8100)) {
b6016b76 2831
745720e5 2832 dev_kfree_skb(skb);
b6016b76
MC		 2833 goto next_rx;
2834
2835 }
2836
b6016b76
MC		 2837 skb->ip_summed = CHECKSUM_NONE;
2838 if (bp->rx_csum &&
2839 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
2840 L2_FHDR_STATUS_UDP_DATAGRAM))) {
2841
ade2bfe7
MC		 2842 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
2843 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
b6016b76
MC		 2844 skb->ip_summed = CHECKSUM_UNNECESSARY;
2845 }
2846
2847#ifdef BCM_VLAN
79ea13ce 2848 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && bp->vlgrp) {
b6016b76
MC		 2849 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
2850 rx_hdr->l2_fhdr_vlan_tag);
2851 }
2852 else
2853#endif
2854 netif_receive_skb(skb);
2855
2856 bp->dev->last_rx = jiffies;
2857 rx_pkt++;
2858
2859next_rx:
b6016b76
MC		 2860 sw_cons = NEXT_RX_BD(sw_cons);
2861 sw_prod = NEXT_RX_BD(sw_prod);
2862
2863 if ((rx_pkt == budget))
2864 break;
f4e418f7
MC		 2865
2866 /* Refresh hw_cons to see if there is new work */
2867 if (sw_cons == hw_cons) {
35efa7c1 2868 hw_cons = bnx2_get_hw_rx_cons(bnapi);
f4e418f7
MC		 2869 rmb();
2870 }
b6016b76 2871 }
a1f60190
MC		 2872 bnapi->rx_cons = sw_cons;
2873 bnapi->rx_prod = sw_prod;
b6016b76 2874
1db82f2a
MC		 2875 if (pg_ring_used)
2876 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_PG_BDIDX,
a1f60190 2877 bnapi->rx_pg_prod);
1db82f2a 2878
b6016b76
MC		 2879 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
2880
a1f60190 2881 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bnapi->rx_prod_bseq);
b6016b76
MC		 2882
2883 mmiowb();
2884
2885 return rx_pkt;
2886
2887}
2888
2889/* MSI ISR - The only difference between this and the INTx ISR
2890 * is that the MSI interrupt is always serviced.
2891 */
2892static irqreturn_t
7d12e780 2893bnx2_msi(int irq, void *dev_instance)
b6016b76
MC		 2894{
2895 struct net_device *dev = dev_instance;
972ec0d4 2896 struct bnx2 *bp = netdev_priv(dev);
b4b36042 2897 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
b6016b76 2898
35efa7c1 2899 prefetch(bnapi->status_blk);
b6016b76
MC		 2900 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2901 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2902 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2903
2904 /* Return here if interrupt is disabled. */
73eef4cd
MC		 2905 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2906 return IRQ_HANDLED;
b6016b76 2907
35efa7c1 2908 netif_rx_schedule(dev, &bnapi->napi);
b6016b76 2909
73eef4cd 2910 return IRQ_HANDLED;
b6016b76
MC		 2911}
2912
8e6a72c4
MC		 2913static irqreturn_t
2914bnx2_msi_1shot(int irq, void *dev_instance)
2915{
2916 struct net_device *dev = dev_instance;
2917 struct bnx2 *bp = netdev_priv(dev);
b4b36042 2918 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
8e6a72c4 2919
35efa7c1 2920 prefetch(bnapi->status_blk);
8e6a72c4
MC		 2921
2922 /* Return here if interrupt is disabled. */
2923 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2924 return IRQ_HANDLED;
2925
35efa7c1 2926 netif_rx_schedule(dev, &bnapi->napi);
8e6a72c4
MC		 2927
2928 return IRQ_HANDLED;
2929}
2930
b6016b76 2931static irqreturn_t
7d12e780 2932bnx2_interrupt(int irq, void *dev_instance)
b6016b76
MC		 2933{
2934 struct net_device *dev = dev_instance;
972ec0d4 2935 struct bnx2 *bp = netdev_priv(dev);
b4b36042 2936 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
35efa7c1 2937 struct status_block *sblk = bnapi->status_blk;
b6016b76
MC		 2938
2939 /* When using INTx, it is possible for the interrupt to arrive
2940 * at the CPU before the status block posted prior to the
2941 * interrupt. Reading a register will flush the status block.
2942 * When using MSI, the MSI message will always complete after
2943 * the status block write.
2944 */
35efa7c1 2945 if ((sblk->status_idx == bnapi->last_status_idx) &&
b6016b76
MC		 2946 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
2947 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
73eef4cd 2948 return IRQ_NONE;
b6016b76
MC		 2949
2950 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2951 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2952 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2953
b8a7ce7b
MC		 2954 /* Read back to deassert IRQ immediately to avoid too many
2955 * spurious interrupts.
2956 */
2957 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
2958
b6016b76 2959 /* Return here if interrupt is shared and is disabled. */
73eef4cd
MC		 2960 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2961 return IRQ_HANDLED;
b6016b76 2962
35efa7c1
MC		 2963 if (netif_rx_schedule_prep(dev, &bnapi->napi)) {
2964 bnapi->last_status_idx = sblk->status_idx;
2965 __netif_rx_schedule(dev, &bnapi->napi);
b8a7ce7b 2966 }
b6016b76 2967
73eef4cd 2968 return IRQ_HANDLED;
b6016b76
MC		 2969}
2970
57851d84
MC		 2971static irqreturn_t
2972bnx2_tx_msix(int irq, void *dev_instance)
2973{
2974 struct net_device *dev = dev_instance;
2975 struct bnx2 *bp = netdev_priv(dev);
2976 struct bnx2_napi *bnapi = &bp->bnx2_napi[BNX2_TX_VEC];
2977
2978 prefetch(bnapi->status_blk_msix);
2979
2980 /* Return here if interrupt is disabled. */
2981 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2982 return IRQ_HANDLED;
2983
2984 netif_rx_schedule(dev, &bnapi->napi);
2985 return IRQ_HANDLED;
2986}
2987
0d8a6571
MC		 2988#define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
2989 STATUS_ATTN_BITS_TIMER_ABORT)
da3e4fbe 2990
f4e418f7 2991static inline int
35efa7c1 2992bnx2_has_work(struct bnx2_napi *bnapi)
f4e418f7 2993{
1097f5e9 2994 struct status_block *sblk = bnapi->status_blk;
f4e418f7 2995
a1f60190 2996 if ((bnx2_get_hw_rx_cons(bnapi) != bnapi->rx_cons) ||
a550c99b 2997 (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons))
f4e418f7
MC		 2998 return 1;
2999
da3e4fbe
MC		 3000 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3001 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
f4e418f7
MC		 3002 return 1;
3003
3004 return 0;
3005}
3006
57851d84
MC		 3007static int bnx2_tx_poll(struct napi_struct *napi, int budget)
3008{
3009 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3010 struct bnx2 *bp = bnapi->bp;
3011 int work_done = 0;
3012 struct status_block_msix *sblk = bnapi->status_blk_msix;
3013
3014 do {
3015 work_done += bnx2_tx_int(bp, bnapi, budget - work_done);
3016 if (unlikely(work_done >= budget))
3017 return work_done;
3018
3019 bnapi->last_status_idx = sblk->status_idx;
3020 rmb();
3021 } while (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons);
3022
3023 netif_rx_complete(bp->dev, napi);
3024 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3025 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3026 bnapi->last_status_idx);
3027 return work_done;
3028}
3029
35efa7c1
MC		 3030static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3031 int work_done, int budget)
b6016b76 3032{
35efa7c1 3033 struct status_block *sblk = bnapi->status_blk;
da3e4fbe
MC		 3034 u32 status_attn_bits = sblk->status_attn_bits;
3035 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
b6016b76 3036
da3e4fbe
MC		 3037 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3038 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
b6016b76 3039
35efa7c1 3040 bnx2_phy_int(bp, bnapi);
bf5295bb
MC		 3041
3042 /* This is needed to take care of transient status
3043 * during link changes.
3044 */
3045 REG_WR(bp, BNX2_HC_COMMAND,
3046 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3047 REG_RD(bp, BNX2_HC_COMMAND);
b6016b76
MC		 3048 }
3049
a550c99b 3050 if (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons)
57851d84 3051 bnx2_tx_int(bp, bnapi, 0);
b6016b76 3052
a1f60190 3053 if (bnx2_get_hw_rx_cons(bnapi) != bnapi->rx_cons)
35efa7c1 3054 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
6aa20a22 3055
6f535763
DM		 3056 return work_done;
3057}
3058
3059static int bnx2_poll(struct napi_struct *napi, int budget)
3060{
35efa7c1
MC		 3061 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3062 struct bnx2 *bp = bnapi->bp;
6f535763 3063 int work_done = 0;
35efa7c1 3064 struct status_block *sblk = bnapi->status_blk;
6f535763
DM		 3065
3066 while (1) {
35efa7c1 3067 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
f4e418f7 3068
6f535763
DM		 3069 if (unlikely(work_done >= budget))
3070 break;
3071
35efa7c1 3072 /* bnapi->last_status_idx is used below to tell the hw how
6dee6421
MC		 3073 * much work has been processed, so we must read it before
3074 * checking for more work.
3075 */
35efa7c1 3076 bnapi->last_status_idx = sblk->status_idx;
6dee6421 3077 rmb();
35efa7c1 3078 if (likely(!bnx2_has_work(bnapi))) {
6f535763 3079 netif_rx_complete(bp->dev, napi);
f86e82fb 3080 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
6f535763
DM		 3081 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3082 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
35efa7c1 3083 bnapi->last_status_idx);
6dee6421 3084 break;
6f535763 3085 }
1269a8a6
MC		 3086 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3087 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
6f535763 3088 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
35efa7c1 3089 bnapi->last_status_idx);
1269a8a6 3090
6f535763
DM		 3091 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3092 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
35efa7c1 3093 bnapi->last_status_idx);
6f535763
DM		 3094 break;
3095 }
b6016b76
MC		 3096 }
3097
bea3348e 3098 return work_done;
b6016b76
MC		 3099}
3100
932ff279 3101/* Called with rtnl_lock from vlan functions and also netif_tx_lock
b6016b76
MC		 3102 * from set_multicast.
3103 */
3104static void
3105bnx2_set_rx_mode(struct net_device *dev)
3106{
972ec0d4 3107 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 3108 u32 rx_mode, sort_mode;
3109 int i;
b6016b76 3110
c770a65c 3111 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 3112
3113 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3114 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3115 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3116#ifdef BCM_VLAN
f86e82fb 3117 if (!bp->vlgrp && !(bp->flags & BNX2_FLAG_ASF_ENABLE))
b6016b76 3118 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
b6016b76 3119#else
f86e82fb 3120 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
e29054f9 3121 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
b6016b76
MC		 3122#endif
3123 if (dev->flags & IFF_PROMISC) {
3124 /* Promiscuous mode. */
3125 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
7510873d
MC		 3126 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3127 BNX2_RPM_SORT_USER0_PROM_VLAN;
b6016b76
MC		 3128 }
3129 else if (dev->flags & IFF_ALLMULTI) {
3130 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3131 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3132 0xffffffff);
3133 }
3134 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3135 }
3136 else {
3137 /* Accept one or more multicast(s). */
3138 struct dev_mc_list *mclist;
3139 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3140 u32 regidx;
3141 u32 bit;
3142 u32 crc;
3143
3144 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3145
3146 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3147 i++, mclist = mclist->next) {
3148
3149 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
3150 bit = crc & 0xff;
3151 regidx = (bit & 0xe0) >> 5;
3152 bit &= 0x1f;
3153 mc_filter[regidx] |= (1 << bit);
3154 }
3155
3156 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3157 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3158 mc_filter[i]);
3159 }
3160
3161 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3162 }
3163
3164 if (rx_mode != bp->rx_mode) {
3165 bp->rx_mode = rx_mode;
3166 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3167 }
3168
3169 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3170 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3171 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3172
c770a65c 3173 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 3174}
3175
3176static void
b491edd5 3177load_rv2p_fw(struct bnx2 *bp, __le32 *rv2p_code, u32 rv2p_code_len,
b6016b76
MC		 3178 u32 rv2p_proc)
3179{
3180 int i;
3181 u32 val;
3182
3183
3184 for (i = 0; i < rv2p_code_len; i += 8) {
b491edd5 3185 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, le32_to_cpu(*rv2p_code));
b6016b76 3186 rv2p_code++;
b491edd5 3187 REG_WR(bp, BNX2_RV2P_INSTR_LOW, le32_to_cpu(*rv2p_code));
b6016b76
MC		 3188 rv2p_code++;
3189
3190 if (rv2p_proc == RV2P_PROC1) {
3191 val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3192 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
3193 }
3194 else {
3195 val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3196 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
3197 }
3198 }
3199
3200 /* Reset the processor, un-stall is done later. */
3201 if (rv2p_proc == RV2P_PROC1) {
3202 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3203 }
3204 else {
3205 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3206 }
3207}
3208
af3ee519 3209static int
b6016b76
MC		 3210load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
3211{
3212 u32 offset;
3213 u32 val;
af3ee519 3214 int rc;
b6016b76
MC		 3215
3216 /* Halt the CPU. */
2726d6e1 3217 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
b6016b76 3218 val |= cpu_reg->mode_value_halt;
2726d6e1
MC		 3219 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3220 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
b6016b76
MC		 3221
3222 /* Load the Text area. */
3223 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
af3ee519 3224 if (fw->gz_text) {
b6016b76
MC		 3225 int j;
3226
ea1f8d5c
MC		 3227 rc = zlib_inflate_blob(fw->text, FW_BUF_SIZE, fw->gz_text,
3228 fw->gz_text_len);
3229 if (rc < 0)
b3448b0b 3230 return rc;
ea1f8d5c 3231
b6016b76 3232 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
2726d6e1 3233 bnx2_reg_wr_ind(bp, offset, le32_to_cpu(fw->text[j]));
b6016b76
MC		 3234 }
3235 }
3236
3237 /* Load the Data area. */
3238 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
3239 if (fw->data) {
3240 int j;
3241
3242 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
2726d6e1 3243 bnx2_reg_wr_ind(bp, offset, fw->data[j]);
b6016b76
MC		 3244 }
3245 }
3246
3247 /* Load the SBSS area. */
3248 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
ea1f8d5c 3249 if (fw->sbss_len) {
b6016b76
MC		 3250 int j;
3251
3252 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
2726d6e1 3253 bnx2_reg_wr_ind(bp, offset, 0);
b6016b76
MC		 3254 }
3255 }
3256
3257 /* Load the BSS area. */
3258 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
ea1f8d5c 3259 if (fw->bss_len) {
b6016b76
MC		 3260 int j;
3261
3262 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
2726d6e1 3263 bnx2_reg_wr_ind(bp, offset, 0);
b6016b76
MC		 3264 }
3265 }
3266
3267 /* Load the Read-Only area. */
3268 offset = cpu_reg->spad_base +
3269 (fw->rodata_addr - cpu_reg->mips_view_base);
3270 if (fw->rodata) {
3271 int j;
3272
3273 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
2726d6e1 3274 bnx2_reg_wr_ind(bp, offset, fw->rodata[j]);
b6016b76
MC		 3275 }
3276 }
3277
3278 /* Clear the pre-fetch instruction. */
2726d6e1
MC		 3279 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3280 bnx2_reg_wr_ind(bp, cpu_reg->pc, fw->start_addr);
b6016b76
MC		 3281
3282 /* Start the CPU. */
2726d6e1 3283 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
b6016b76 3284 val &= ~cpu_reg->mode_value_halt;
2726d6e1
MC		 3285 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3286 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
af3ee519
MC		 3287
3288 return 0;
b6016b76
MC		 3289}
3290
fba9fe91 3291static int
b6016b76
MC		 3292bnx2_init_cpus(struct bnx2 *bp)
3293{
3294 struct cpu_reg cpu_reg;
af3ee519 3295 struct fw_info *fw;
110d0ef9
MC		 3296 int rc, rv2p_len;
3297 void *text, *rv2p;
b6016b76
MC		 3298
3299 /* Initialize the RV2P processor. */
b3448b0b
DV		 3300 text = vmalloc(FW_BUF_SIZE);
3301 if (!text)
3302 return -ENOMEM;
110d0ef9
MC		 3303 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3304 rv2p = bnx2_xi_rv2p_proc1;
3305 rv2p_len = sizeof(bnx2_xi_rv2p_proc1);
3306 } else {
3307 rv2p = bnx2_rv2p_proc1;
3308 rv2p_len = sizeof(bnx2_rv2p_proc1);
3309 }
3310 rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
ea1f8d5c 3311 if (rc < 0)
fba9fe91 3312 goto init_cpu_err;
ea1f8d5c 3313
b3448b0b 3314 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC1);
fba9fe91 3315
110d0ef9
MC		 3316 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3317 rv2p = bnx2_xi_rv2p_proc2;
3318 rv2p_len = sizeof(bnx2_xi_rv2p_proc2);
3319 } else {
3320 rv2p = bnx2_rv2p_proc2;
3321 rv2p_len = sizeof(bnx2_rv2p_proc2);
3322 }
3323 rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
ea1f8d5c 3324 if (rc < 0)
fba9fe91 3325 goto init_cpu_err;
ea1f8d5c 3326
b3448b0b 3327 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2);
b6016b76
MC		 3328
3329 /* Initialize the RX Processor. */
3330 cpu_reg.mode = BNX2_RXP_CPU_MODE;
3331 cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
3332 cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
3333 cpu_reg.state = BNX2_RXP_CPU_STATE;
3334 cpu_reg.state_value_clear = 0xffffff;
3335 cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
3336 cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
3337 cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
3338 cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
3339 cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
3340 cpu_reg.spad_base = BNX2_RXP_SCRATCH;
3341 cpu_reg.mips_view_base = 0x8000000;
6aa20a22 3342
d43584c8
MC		 3343 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3344 fw = &bnx2_rxp_fw_09;
3345 else
3346 fw = &bnx2_rxp_fw_06;
fba9fe91 3347
ea1f8d5c 3348 fw->text = text;
af3ee519 3349 rc = load_cpu_fw(bp, &cpu_reg, fw);
fba9fe91
MC		 3350 if (rc)
3351 goto init_cpu_err;
3352
b6016b76
MC		 3353 /* Initialize the TX Processor. */
3354 cpu_reg.mode = BNX2_TXP_CPU_MODE;
3355 cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
3356 cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
3357 cpu_reg.state = BNX2_TXP_CPU_STATE;
3358 cpu_reg.state_value_clear = 0xffffff;
3359 cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
3360 cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
3361 cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
3362 cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
3363 cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
3364 cpu_reg.spad_base = BNX2_TXP_SCRATCH;
3365 cpu_reg.mips_view_base = 0x8000000;
6aa20a22 3366
d43584c8
MC		 3367 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3368 fw = &bnx2_txp_fw_09;
3369 else
3370 fw = &bnx2_txp_fw_06;
fba9fe91 3371
ea1f8d5c 3372 fw->text = text;
af3ee519 3373 rc = load_cpu_fw(bp, &cpu_reg, fw);
fba9fe91
MC		 3374 if (rc)
3375 goto init_cpu_err;
3376
b6016b76
MC		 3377 /* Initialize the TX Patch-up Processor. */
3378 cpu_reg.mode = BNX2_TPAT_CPU_MODE;
3379 cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
3380 cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
3381 cpu_reg.state = BNX2_TPAT_CPU_STATE;
3382 cpu_reg.state_value_clear = 0xffffff;
3383 cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
3384 cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
3385 cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
3386 cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
3387 cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
3388 cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
3389 cpu_reg.mips_view_base = 0x8000000;
6aa20a22 3390
d43584c8
MC		 3391 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3392 fw = &bnx2_tpat_fw_09;
3393 else
3394 fw = &bnx2_tpat_fw_06;
fba9fe91 3395
ea1f8d5c 3396 fw->text = text;
af3ee519 3397 rc = load_cpu_fw(bp, &cpu_reg, fw);
fba9fe91
MC		 3398 if (rc)
3399 goto init_cpu_err;
3400
b6016b76
MC		 3401 /* Initialize the Completion Processor. */
3402 cpu_reg.mode = BNX2_COM_CPU_MODE;
3403 cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
3404 cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
3405 cpu_reg.state = BNX2_COM_CPU_STATE;
3406 cpu_reg.state_value_clear = 0xffffff;
3407 cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
3408 cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
3409 cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
3410 cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
3411 cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
3412 cpu_reg.spad_base = BNX2_COM_SCRATCH;
3413 cpu_reg.mips_view_base = 0x8000000;
6aa20a22 3414
d43584c8
MC		 3415 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3416 fw = &bnx2_com_fw_09;
3417 else
3418 fw = &bnx2_com_fw_06;
fba9fe91 3419
ea1f8d5c 3420 fw->text = text;
af3ee519 3421 rc = load_cpu_fw(bp, &cpu_reg, fw);
fba9fe91
MC		 3422 if (rc)
3423 goto init_cpu_err;
3424
d43584c8
MC		 3425 /* Initialize the Command Processor. */
3426 cpu_reg.mode = BNX2_CP_CPU_MODE;
3427 cpu_reg.mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT;
3428 cpu_reg.mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA;
3429 cpu_reg.state = BNX2_CP_CPU_STATE;
3430 cpu_reg.state_value_clear = 0xffffff;
3431 cpu_reg.gpr0 = BNX2_CP_CPU_REG_FILE;
3432 cpu_reg.evmask = BNX2_CP_CPU_EVENT_MASK;
3433 cpu_reg.pc = BNX2_CP_CPU_PROGRAM_COUNTER;
3434 cpu_reg.inst = BNX2_CP_CPU_INSTRUCTION;
3435 cpu_reg.bp = BNX2_CP_CPU_HW_BREAKPOINT;
3436 cpu_reg.spad_base = BNX2_CP_SCRATCH;
3437 cpu_reg.mips_view_base = 0x8000000;
b6016b76 3438
110d0ef9 3439 if (CHIP_NUM(bp) == CHIP_NUM_5709)
d43584c8 3440 fw = &bnx2_cp_fw_09;
110d0ef9
MC		 3441 else
3442 fw = &bnx2_cp_fw_06;
3443
3444 fw->text = text;
3445 rc = load_cpu_fw(bp, &cpu_reg, fw);
b6016b76 3446
fba9fe91 3447init_cpu_err:
ea1f8d5c 3448 vfree(text);
fba9fe91 3449 return rc;
b6016b76
MC		 3450}
3451
3452static int
829ca9a3 3453bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
b6016b76
MC		 3454{
3455 u16 pmcsr;
3456
3457 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3458
3459 switch (state) {
829ca9a3 3460 case PCI_D0: {
b6016b76
MC		 3461 u32 val;
3462
3463 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3464 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3465 PCI_PM_CTRL_PME_STATUS);
3466
3467 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3468 /* delay required during transition out of D3hot */
3469 msleep(20);
3470
3471 val = REG_RD(bp, BNX2_EMAC_MODE);
3472 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3473 val &= ~BNX2_EMAC_MODE_MPKT;
3474 REG_WR(bp, BNX2_EMAC_MODE, val);
3475
3476 val = REG_RD(bp, BNX2_RPM_CONFIG);
3477 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3478 REG_WR(bp, BNX2_RPM_CONFIG, val);
3479 break;
3480 }
829ca9a3 3481 case PCI_D3hot: {
b6016b76
MC		 3482 int i;
3483 u32 val, wol_msg;
3484
3485 if (bp->wol) {
3486 u32 advertising;
3487 u8 autoneg;
3488
3489 autoneg = bp->autoneg;
3490 advertising = bp->advertising;
3491
239cd343
MC		 3492 if (bp->phy_port == PORT_TP) {
3493 bp->autoneg = AUTONEG_SPEED;
3494 bp->advertising = ADVERTISED_10baseT_Half |
3495 ADVERTISED_10baseT_Full |
3496 ADVERTISED_100baseT_Half |
3497 ADVERTISED_100baseT_Full |
3498 ADVERTISED_Autoneg;
3499 }
b6016b76 3500
239cd343
MC		 3501 spin_lock_bh(&bp->phy_lock);
3502 bnx2_setup_phy(bp, bp->phy_port);
3503 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 3504
3505 bp->autoneg = autoneg;
3506 bp->advertising = advertising;
3507
3508 bnx2_set_mac_addr(bp);
3509
3510 val = REG_RD(bp, BNX2_EMAC_MODE);
3511
3512 /* Enable port mode. */
3513 val &= ~BNX2_EMAC_MODE_PORT;
239cd343 3514 val |= BNX2_EMAC_MODE_MPKT_RCVD |
b6016b76 3515 BNX2_EMAC_MODE_ACPI_RCVD |
b6016b76 3516 BNX2_EMAC_MODE_MPKT;
239cd343
MC		 3517 if (bp->phy_port == PORT_TP)
3518 val |= BNX2_EMAC_MODE_PORT_MII;
3519 else {
3520 val |= BNX2_EMAC_MODE_PORT_GMII;
3521 if (bp->line_speed == SPEED_2500)
3522 val |= BNX2_EMAC_MODE_25G_MODE;
3523 }
b6016b76
MC		 3524
3525 REG_WR(bp, BNX2_EMAC_MODE, val);
3526
3527 /* receive all multicast */
3528 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3529 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3530 0xffffffff);
3531 }
3532 REG_WR(bp, BNX2_EMAC_RX_MODE,
3533 BNX2_EMAC_RX_MODE_SORT_MODE);
3534
3535 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3536 BNX2_RPM_SORT_USER0_MC_EN;
3537 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3538 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3539 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3540 BNX2_RPM_SORT_USER0_ENA);
3541
3542 /* Need to enable EMAC and RPM for WOL. */
3543 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3544 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3545 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3546 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3547
3548 val = REG_RD(bp, BNX2_RPM_CONFIG);
3549 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3550 REG_WR(bp, BNX2_RPM_CONFIG, val);
3551
3552 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3553 }
3554 else {
3555 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3556 }
3557
f86e82fb 3558 if (!(bp->flags & BNX2_FLAG_NO_WOL))
dda1e390 3559 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
b6016b76
MC		 3560
3561 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3562 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3563 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3564
3565 if (bp->wol)
3566 pmcsr |= 3;
3567 }
3568 else {
3569 pmcsr |= 3;
3570 }
3571 if (bp->wol) {
3572 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3573 }
3574 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3575 pmcsr);
3576
3577 /* No more memory access after this point until
3578 * device is brought back to D0.
3579 */
3580 udelay(50);
3581 break;
3582 }
3583 default:
3584 return -EINVAL;
3585 }
3586 return 0;
3587}
3588
3589static int
3590bnx2_acquire_nvram_lock(struct bnx2 *bp)
3591{
3592 u32 val;
3593 int j;
3594
3595 /* Request access to the flash interface. */
3596 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
3597 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3598 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3599 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
3600 break;
3601
3602 udelay(5);
3603 }
3604
3605 if (j >= NVRAM_TIMEOUT_COUNT)
3606 return -EBUSY;
3607
3608 return 0;
3609}
3610
3611static int
3612bnx2_release_nvram_lock(struct bnx2 *bp)
3613{
3614 int j;
3615 u32 val;
3616
3617 /* Relinquish nvram interface. */
3618 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
3619
3620 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3621 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3622 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
3623 break;
3624
3625 udelay(5);
3626 }
3627
3628 if (j >= NVRAM_TIMEOUT_COUNT)
3629 return -EBUSY;
3630
3631 return 0;
3632}
3633
3634
3635static int
3636bnx2_enable_nvram_write(struct bnx2 *bp)
3637{
3638 u32 val;
3639
3640 val = REG_RD(bp, BNX2_MISC_CFG);
3641 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
3642
e30372c9 3643 if (bp->flash_info->flags & BNX2_NV_WREN) {
b6016b76
MC		 3644 int j;
3645
3646 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3647 REG_WR(bp, BNX2_NVM_COMMAND,
3648 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
3649
3650 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3651 udelay(5);
3652
3653 val = REG_RD(bp, BNX2_NVM_COMMAND);
3654 if (val & BNX2_NVM_COMMAND_DONE)
3655 break;
3656 }
3657
3658 if (j >= NVRAM_TIMEOUT_COUNT)
3659 return -EBUSY;
3660 }
3661 return 0;
3662}
3663
3664static void
3665bnx2_disable_nvram_write(struct bnx2 *bp)
3666{
3667 u32 val;
3668
3669 val = REG_RD(bp, BNX2_MISC_CFG);
3670 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
3671}
3672
3673
3674static void
3675bnx2_enable_nvram_access(struct bnx2 *bp)
3676{
3677 u32 val;
3678
3679 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3680 /* Enable both bits, even on read. */
6aa20a22 3681 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
b6016b76
MC		 3682 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
3683}
3684
3685static void
3686bnx2_disable_nvram_access(struct bnx2 *bp)
3687{
3688 u32 val;
3689
3690 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3691 /* Disable both bits, even after read. */
6aa20a22 3692 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
b6016b76
MC		 3693 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
3694 BNX2_NVM_ACCESS_ENABLE_WR_EN));
3695}
3696
3697static int
3698bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
3699{
3700 u32 cmd;
3701 int j;
3702
e30372c9 3703 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
b6016b76
MC		 3704 /* Buffered flash, no erase needed */
3705 return 0;
3706
3707 /* Build an erase command */
3708 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
3709 BNX2_NVM_COMMAND_DOIT;
3710
3711 /* Need to clear DONE bit separately. */
3712 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3713
3714 /* Address of the NVRAM to read from. */
3715 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3716
3717 /* Issue an erase command. */
3718 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3719
3720 /* Wait for completion. */
3721 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3722 u32 val;
3723
3724 udelay(5);
3725
3726 val = REG_RD(bp, BNX2_NVM_COMMAND);
3727 if (val & BNX2_NVM_COMMAND_DONE)
3728 break;
3729 }
3730
3731 if (j >= NVRAM_TIMEOUT_COUNT)
3732 return -EBUSY;
3733
3734 return 0;
3735}
3736
3737static int
3738bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
3739{
3740 u32 cmd;
3741 int j;
3742
3743 /* Build the command word. */
3744 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
3745
e30372c9
MC		 3746 /* Calculate an offset of a buffered flash, not needed for 5709. */
3747 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
b6016b76
MC		 3748 offset = ((offset / bp->flash_info->page_size) <<
3749 bp->flash_info->page_bits) +
3750 (offset % bp->flash_info->page_size);
3751 }
3752
3753 /* Need to clear DONE bit separately. */
3754 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3755
3756 /* Address of the NVRAM to read from. */
3757 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3758
3759 /* Issue a read command. */
3760 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3761
3762 /* Wait for completion. */
3763 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3764 u32 val;
3765
3766 udelay(5);
3767
3768 val = REG_RD(bp, BNX2_NVM_COMMAND);
3769 if (val & BNX2_NVM_COMMAND_DONE) {
b491edd5
AV		 3770 __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
3771 memcpy(ret_val, &v, 4);
b6016b76
MC		 3772 break;
3773 }
3774 }
3775 if (j >= NVRAM_TIMEOUT_COUNT)
3776 return -EBUSY;
3777
3778 return 0;
3779}
3780
3781
3782static int
3783bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
3784{
b491edd5
AV		 3785 u32 cmd;
3786 __be32 val32;
b6016b76
MC		 3787 int j;
3788
3789 /* Build the command word. */
3790 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
3791
e30372c9
MC		 3792 /* Calculate an offset of a buffered flash, not needed for 5709. */
3793 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
b6016b76
MC		 3794 offset = ((offset / bp->flash_info->page_size) <<
3795 bp->flash_info->page_bits) +
3796 (offset % bp->flash_info->page_size);
3797 }
3798
3799 /* Need to clear DONE bit separately. */
3800 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3801
3802 memcpy(&val32, val, 4);
b6016b76
MC		 3803
3804 /* Write the data. */
b491edd5 3805 REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
b6016b76
MC		 3806
3807 /* Address of the NVRAM to write to. */
3808 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3809
3810 /* Issue the write command. */
3811 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3812
3813 /* Wait for completion. */
3814 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3815 udelay(5);
3816
3817 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
3818 break;
3819 }
3820 if (j >= NVRAM_TIMEOUT_COUNT)
3821 return -EBUSY;
3822
3823 return 0;
3824}
3825
3826static int
3827bnx2_init_nvram(struct bnx2 *bp)
3828{
3829 u32 val;
e30372c9 3830 int j, entry_count, rc = 0;
b6016b76
MC		 3831 struct flash_spec *flash;
3832
e30372c9
MC		 3833 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3834 bp->flash_info = &flash_5709;
3835 goto get_flash_size;
3836 }
3837
b6016b76
MC		 3838 /* Determine the selected interface. */
3839 val = REG_RD(bp, BNX2_NVM_CFG1);
3840
ff8ac609 3841 entry_count = ARRAY_SIZE(flash_table);
b6016b76 3842
b6016b76
MC		 3843 if (val & 0x40000000) {
3844
3845 /* Flash interface has been reconfigured */
3846 for (j = 0, flash = &flash_table[0]; j < entry_count;
37137709
MC		 3847 j++, flash++) {
3848 if ((val & FLASH_BACKUP_STRAP_MASK) ==
3849 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
b6016b76
MC		 3850 bp->flash_info = flash;
3851 break;
3852 }
3853 }
3854 }
3855 else {
37137709 3856 u32 mask;
b6016b76
MC		 3857 /* Not yet been reconfigured */
3858
37137709
MC		 3859 if (val & (1 << 23))
3860 mask = FLASH_BACKUP_STRAP_MASK;
3861 else
3862 mask = FLASH_STRAP_MASK;
3863
b6016b76
MC		 3864 for (j = 0, flash = &flash_table[0]; j < entry_count;
3865 j++, flash++) {
3866
37137709 3867 if ((val & mask) == (flash->strapping & mask)) {
b6016b76
MC		 3868 bp->flash_info = flash;
3869
3870 /* Request access to the flash interface. */
3871 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3872 return rc;
3873
3874 /* Enable access to flash interface */
3875 bnx2_enable_nvram_access(bp);
3876
3877 /* Reconfigure the flash interface */
3878 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
3879 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
3880 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
3881 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
3882
3883 /* Disable access to flash interface */
3884 bnx2_disable_nvram_access(bp);
3885 bnx2_release_nvram_lock(bp);
3886
3887 break;
3888 }
3889 }
3890 } /* if (val & 0x40000000) */
3891
3892 if (j == entry_count) {
3893 bp->flash_info = NULL;
2f23c523 3894 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
1122db71 3895 return -ENODEV;
b6016b76
MC		 3896 }
3897
e30372c9 3898get_flash_size:
2726d6e1 3899 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
1122db71
MC		 3900 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
3901 if (val)
3902 bp->flash_size = val;
3903 else
3904 bp->flash_size = bp->flash_info->total_size;
3905
b6016b76
MC		 3906 return rc;
3907}
3908
3909static int
3910bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
3911 int buf_size)
3912{
3913 int rc = 0;
3914 u32 cmd_flags, offset32, len32, extra;
3915
3916 if (buf_size == 0)
3917 return 0;
3918
3919 /* Request access to the flash interface. */
3920 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3921 return rc;
3922
3923 /* Enable access to flash interface */
3924 bnx2_enable_nvram_access(bp);
3925
3926 len32 = buf_size;
3927 offset32 = offset;
3928 extra = 0;
3929
3930 cmd_flags = 0;
3931
3932 if (offset32 & 3) {
3933 u8 buf[4];
3934 u32 pre_len;
3935
3936 offset32 &= ~3;
3937 pre_len = 4 - (offset & 3);
3938
3939 if (pre_len >= len32) {
3940 pre_len = len32;
3941 cmd_flags = BNX2_NVM_COMMAND_FIRST |
3942 BNX2_NVM_COMMAND_LAST;
3943 }
3944 else {
3945 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3946 }
3947
3948 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3949
3950 if (rc)
3951 return rc;
3952
3953 memcpy(ret_buf, buf + (offset & 3), pre_len);
3954
3955 offset32 += 4;
3956 ret_buf += pre_len;
3957 len32 -= pre_len;
3958 }
3959 if (len32 & 3) {
3960 extra = 4 - (len32 & 3);
3961 len32 = (len32 + 4) & ~3;
3962 }
3963
3964 if (len32 == 4) {
3965 u8 buf[4];
3966
3967 if (cmd_flags)
3968 cmd_flags = BNX2_NVM_COMMAND_LAST;
3969 else
3970 cmd_flags = BNX2_NVM_COMMAND_FIRST |
3971 BNX2_NVM_COMMAND_LAST;
3972
3973 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3974
3975 memcpy(ret_buf, buf, 4 - extra);
3976 }
3977 else if (len32 > 0) {
3978 u8 buf[4];
3979
3980 /* Read the first word. */
3981 if (cmd_flags)
3982 cmd_flags = 0;
3983 else
3984 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3985
3986 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
3987
3988 /* Advance to the next dword. */
3989 offset32 += 4;
3990 ret_buf += 4;
3991 len32 -= 4;
3992
3993 while (len32 > 4 && rc == 0) {
3994 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
3995
3996 /* Advance to the next dword. */
3997 offset32 += 4;
3998 ret_buf += 4;
3999 len32 -= 4;
4000 }
4001
4002 if (rc)
4003 return rc;
4004
4005 cmd_flags = BNX2_NVM_COMMAND_LAST;
4006 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4007
4008 memcpy(ret_buf, buf, 4 - extra);
4009 }
4010
4011 /* Disable access to flash interface */
4012 bnx2_disable_nvram_access(bp);
4013
4014 bnx2_release_nvram_lock(bp);
4015
4016 return rc;
4017}
4018
4019static int
4020bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4021 int buf_size)
4022{
4023 u32 written, offset32, len32;
e6be763f 4024 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
b6016b76
MC		 4025 int rc = 0;
4026 int align_start, align_end;
4027
4028 buf = data_buf;
4029 offset32 = offset;
4030 len32 = buf_size;
4031 align_start = align_end = 0;
4032
4033 if ((align_start = (offset32 & 3))) {
4034 offset32 &= ~3;
c873879c
MC		 4035 len32 += align_start;
4036 if (len32 < 4)
4037 len32 = 4;
b6016b76
MC		 4038 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4039 return rc;
4040 }
4041
4042 if (len32 & 3) {
c873879c
MC		 4043 align_end = 4 - (len32 & 3);
4044 len32 += align_end;
4045 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4046 return rc;
b6016b76
MC		 4047 }
4048
4049 if (align_start || align_end) {
e6be763f
MC		 4050 align_buf = kmalloc(len32, GFP_KERNEL);
4051 if (align_buf == NULL)
b6016b76
MC		 4052 return -ENOMEM;
4053 if (align_start) {
e6be763f 4054 memcpy(align_buf, start, 4);
b6016b76
MC		 4055 }
4056 if (align_end) {
e6be763f 4057 memcpy(align_buf + len32 - 4, end, 4);
b6016b76 4058 }
e6be763f
MC		 4059 memcpy(align_buf + align_start, data_buf, buf_size);
4060 buf = align_buf;
b6016b76
MC		 4061 }
4062
e30372c9 4063 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
ae181bc4
MC		 4064 flash_buffer = kmalloc(264, GFP_KERNEL);
4065 if (flash_buffer == NULL) {
4066 rc = -ENOMEM;
4067 goto nvram_write_end;
4068 }
4069 }
4070
b6016b76
MC		 4071 written = 0;
4072 while ((written < len32) && (rc == 0)) {
4073 u32 page_start, page_end, data_start, data_end;
4074 u32 addr, cmd_flags;
4075 int i;
b6016b76
MC		 4076
4077 /* Find the page_start addr */
4078 page_start = offset32 + written;
4079 page_start -= (page_start % bp->flash_info->page_size);
4080 /* Find the page_end addr */
4081 page_end = page_start + bp->flash_info->page_size;
4082 /* Find the data_start addr */
4083 data_start = (written == 0) ? offset32 : page_start;
4084 /* Find the data_end addr */
6aa20a22 4085 data_end = (page_end > offset32 + len32) ?
b6016b76
MC		 4086 (offset32 + len32) : page_end;
4087
4088 /* Request access to the flash interface. */
4089 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4090 goto nvram_write_end;
4091
4092 /* Enable access to flash interface */
4093 bnx2_enable_nvram_access(bp);
4094
4095 cmd_flags = BNX2_NVM_COMMAND_FIRST;
e30372c9 4096 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
b6016b76
MC		 4097 int j;
4098
4099 /* Read the whole page into the buffer
4100 * (non-buffer flash only) */
4101 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4102 if (j == (bp->flash_info->page_size - 4)) {
4103 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4104 }
4105 rc = bnx2_nvram_read_dword(bp,
6aa20a22
JG		 4106 page_start + j,
4107 &flash_buffer[j],
b6016b76
MC		 4108 cmd_flags);
4109
4110 if (rc)
4111 goto nvram_write_end;
4112
4113 cmd_flags = 0;
4114 }
4115 }
4116
4117 /* Enable writes to flash interface (unlock write-protect) */
4118 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4119 goto nvram_write_end;
4120
b6016b76
MC		 4121 /* Loop to write back the buffer data from page_start to
4122 * data_start */
4123 i = 0;
e30372c9 4124 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
c873879c
MC		 4125 /* Erase the page */
4126 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4127 goto nvram_write_end;
4128
4129 /* Re-enable the write again for the actual write */
4130 bnx2_enable_nvram_write(bp);
4131
b6016b76
MC		 4132 for (addr = page_start; addr < data_start;
4133 addr += 4, i += 4) {
6aa20a22 4134
b6016b76
MC		 4135 rc = bnx2_nvram_write_dword(bp, addr,
4136 &flash_buffer[i], cmd_flags);
4137
4138 if (rc != 0)
4139 goto nvram_write_end;
4140
4141 cmd_flags = 0;
4142 }
4143 }
4144
4145 /* Loop to write the new data from data_start to data_end */
bae25761 4146 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
b6016b76 4147 if ((addr == page_end - 4) ||
e30372c9 4148 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
b6016b76
MC		 4149 (addr == data_end - 4))) {
4150
4151 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4152 }
4153 rc = bnx2_nvram_write_dword(bp, addr, buf,
4154 cmd_flags);
4155
4156 if (rc != 0)
4157 goto nvram_write_end;
4158
4159 cmd_flags = 0;
4160 buf += 4;
4161 }
4162
4163 /* Loop to write back the buffer data from data_end
4164 * to page_end */
e30372c9 4165 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
b6016b76
MC		 4166 for (addr = data_end; addr < page_end;
4167 addr += 4, i += 4) {
6aa20a22 4168
b6016b76
MC		 4169 if (addr == page_end-4) {
4170 cmd_flags = BNX2_NVM_COMMAND_LAST;
4171 }
4172 rc = bnx2_nvram_write_dword(bp, addr,
4173 &flash_buffer[i], cmd_flags);
4174
4175 if (rc != 0)
4176 goto nvram_write_end;
4177
4178 cmd_flags = 0;
4179 }
4180 }
4181
4182 /* Disable writes to flash interface (lock write-protect) */
4183 bnx2_disable_nvram_write(bp);
4184
4185 /* Disable access to flash interface */
4186 bnx2_disable_nvram_access(bp);
4187 bnx2_release_nvram_lock(bp);
4188
4189 /* Increment written */
4190 written += data_end - data_start;
4191 }
4192
4193nvram_write_end:
e6be763f
MC		 4194 kfree(flash_buffer);
4195 kfree(align_buf);
b6016b76
MC		 4196 return rc;
4197}
4198
0d8a6571
MC		 4199static void
4200bnx2_init_remote_phy(struct bnx2 *bp)
4201{
4202 u32 val;
4203
583c28e5
MC		 4204 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4205 if (!(bp->phy_flags & BNX2_PHY_FLAG_SERDES))
0d8a6571
MC		 4206 return;
4207
2726d6e1 4208 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
0d8a6571
MC		 4209 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4210 return;
4211
4212 if (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE) {
583c28e5 4213 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
0d8a6571 4214
2726d6e1 4215 val = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
0d8a6571
MC		 4216 if (val & BNX2_LINK_STATUS_SERDES_LINK)
4217 bp->phy_port = PORT_FIBRE;
4218 else
4219 bp->phy_port = PORT_TP;
489310a4
MC		 4220
4221 if (netif_running(bp->dev)) {
4222 u32 sig;
4223
489310a4
MC		 4224 sig = BNX2_DRV_ACK_CAP_SIGNATURE |
4225 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
2726d6e1 4226 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
489310a4 4227 }
0d8a6571
MC		 4228 }
4229}
4230
b4b36042
MC		 4231static void
4232bnx2_setup_msix_tbl(struct bnx2 *bp)
4233{
4234 REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4235
4236 REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4237 REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4238}
4239
b6016b76
MC		 4240static int
4241bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4242{
4243 u32 val;
4244 int i, rc = 0;
489310a4 4245 u8 old_port;
b6016b76
MC		 4246
4247 /* Wait for the current PCI transaction to complete before
4248 * issuing a reset. */
4249 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4250 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4251 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4252 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4253 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4254 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4255 udelay(5);
4256
b090ae2b
MC		 4257 /* Wait for the firmware to tell us it is ok to issue a reset. */
4258 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
4259
b6016b76
MC		 4260 /* Deposit a driver reset signature so the firmware knows that
4261 * this is a soft reset. */
2726d6e1
MC		 4262 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4263 BNX2_DRV_RESET_SIGNATURE_MAGIC);
b6016b76 4264
b6016b76
MC		 4265 /* Do a dummy read to force the chip to complete all current transaction
4266 * before we issue a reset. */
4267 val = REG_RD(bp, BNX2_MISC_ID);
4268
234754d5
MC		 4269 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4270 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4271 REG_RD(bp, BNX2_MISC_COMMAND);
4272 udelay(5);
b6016b76 4273
234754d5
MC		 4274 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4275 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
b6016b76 4276
234754d5 4277 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
b6016b76 4278
234754d5
MC		 4279 } else {
4280 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4281 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4282 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4283
4284 /* Chip reset. */
4285 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4286
594a9dfa
MC		 4287 /* Reading back any register after chip reset will hang the
4288 * bus on 5706 A0 and A1. The msleep below provides plenty
4289 * of margin for write posting.
4290 */
234754d5 4291 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
8e545881
AV		 4292 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4293 msleep(20);
b6016b76 4294
234754d5
MC		 4295 /* Reset takes approximate 30 usec */
4296 for (i = 0; i < 10; i++) {
4297 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4298 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4299 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4300 break;
4301 udelay(10);
4302 }
4303
4304 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4305 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4306 printk(KERN_ERR PFX "Chip reset did not complete\n");
4307 return -EBUSY;
4308 }
b6016b76
MC		 4309 }
4310
4311 /* Make sure byte swapping is properly configured. */
4312 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4313 if (val != 0x01020304) {
4314 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
4315 return -ENODEV;
4316 }
4317
b6016b76 4318 /* Wait for the firmware to finish its initialization. */
b090ae2b
MC		 4319 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
4320 if (rc)
4321 return rc;
b6016b76 4322
0d8a6571 4323 spin_lock_bh(&bp->phy_lock);
489310a4 4324 old_port = bp->phy_port;
0d8a6571 4325 bnx2_init_remote_phy(bp);
583c28e5
MC		 4326 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4327 old_port != bp->phy_port)
0d8a6571
MC		 4328 bnx2_set_default_remote_link(bp);
4329 spin_unlock_bh(&bp->phy_lock);
4330
b6016b76
MC		 4331 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4332 /* Adjust the voltage regular to two steps lower. The default
4333 * of this register is 0x0000000e. */
4334 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4335
4336 /* Remove bad rbuf memory from the free pool. */
4337 rc = bnx2_alloc_bad_rbuf(bp);
4338 }
4339
f86e82fb 4340 if (bp->flags & BNX2_FLAG_USING_MSIX)
b4b36042
MC		 4341 bnx2_setup_msix_tbl(bp);
4342
b6016b76
MC		 4343 return rc;
4344}
4345
4346static int
4347bnx2_init_chip(struct bnx2 *bp)
4348{
4349 u32 val;
b4b36042 4350 int rc, i;
b6016b76
MC		 4351
4352 /* Make sure the interrupt is not active. */
4353 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4354
4355 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4356 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4357#ifdef __BIG_ENDIAN
6aa20a22 4358 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
b6016b76 4359#endif
6aa20a22 4360 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
b6016b76
MC		 4361 DMA_READ_CHANS << 12 |
4362 DMA_WRITE_CHANS << 16;
4363
4364 val |= (0x2 << 20) | (1 << 11);
4365
f86e82fb 4366 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
b6016b76
MC		 4367 val |= (1 << 23);
4368
4369 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
f86e82fb 4370 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
b6016b76
MC		 4371 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4372
4373 REG_WR(bp, BNX2_DMA_CONFIG, val);
4374
4375 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4376 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4377 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4378 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4379 }
4380
f86e82fb 4381 if (bp->flags & BNX2_FLAG_PCIX) {
b6016b76
MC		 4382 u16 val16;
4383
4384 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4385 &val16);
4386 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4387 val16 & ~PCI_X_CMD_ERO);
4388 }
4389
4390 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4391 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4392 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4393 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4394
4395 /* Initialize context mapping and zero out the quick contexts. The
4396 * context block must have already been enabled. */
641bdcd5
MC		 4397 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4398 rc = bnx2_init_5709_context(bp);
4399 if (rc)
4400 return rc;
4401 } else
59b47d8a 4402 bnx2_init_context(bp);
b6016b76 4403
fba9fe91
MC		 4404 if ((rc = bnx2_init_cpus(bp)) != 0)
4405 return rc;
4406
b6016b76
MC		 4407 bnx2_init_nvram(bp);
4408
4409 bnx2_set_mac_addr(bp);
4410
4411 val = REG_RD(bp, BNX2_MQ_CONFIG);
4412 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4413 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
68c9f75a
MC		 4414 if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1)
4415 val |= BNX2_MQ_CONFIG_HALT_DIS;
4416
b6016b76
MC		 4417 REG_WR(bp, BNX2_MQ_CONFIG, val);
4418
4419 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4420 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4421 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4422
4423 val = (BCM_PAGE_BITS - 8) << 24;
4424 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4425
4426 /* Configure page size. */
4427 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4428 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4429 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4430 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4431
4432 val = bp->mac_addr[0] +
4433 (bp->mac_addr[1] << 8) +
4434 (bp->mac_addr[2] << 16) +
4435 bp->mac_addr[3] +
4436 (bp->mac_addr[4] << 8) +
4437 (bp->mac_addr[5] << 16);
4438 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4439
4440 /* Program the MTU. Also include 4 bytes for CRC32. */
4441 val = bp->dev->mtu + ETH_HLEN + 4;
4442 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4443 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4444 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4445
b4b36042
MC		 4446 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4447 bp->bnx2_napi[i].last_status_idx = 0;
4448
b6016b76
MC		 4449 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4450
4451 /* Set up how to generate a link change interrupt. */
4452 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4453
4454 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4455 (u64) bp->status_blk_mapping & 0xffffffff);
4456 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4457
4458 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4459 (u64) bp->stats_blk_mapping & 0xffffffff);
4460 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4461 (u64) bp->stats_blk_mapping >> 32);
4462
6aa20a22 4463 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
b6016b76
MC		 4464 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4465
4466 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4467 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4468
4469 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4470 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4471
4472 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4473
4474 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4475
4476 REG_WR(bp, BNX2_HC_COM_TICKS,
4477 (bp->com_ticks_int << 16) | bp->com_ticks);
4478
4479 REG_WR(bp, BNX2_HC_CMD_TICKS,
4480 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4481
02537b06
MC		 4482 if (CHIP_NUM(bp) == CHIP_NUM_5708)
4483 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4484 else
7ea6920e 4485 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
b6016b76
MC		 4486 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4487
4488 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
8e6a72c4 4489 val = BNX2_HC_CONFIG_COLLECT_STATS;
b6016b76 4490 else {
8e6a72c4
MC		 4491 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4492 BNX2_HC_CONFIG_COLLECT_STATS;
b6016b76
MC		 4493 }
4494
f86e82fb 4495 if (bp->flags & BNX2_FLAG_USING_MSIX) {
6f743ca0
MC		 4496 u32 base = ((BNX2_TX_VEC - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4497 BNX2_HC_SB_CONFIG_1;
4498
c76c0475
MC		 4499 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4500 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4501
6f743ca0 4502 REG_WR(bp, base,
c76c0475
MC		 4503 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
4504 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4505
6f743ca0 4506 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
c76c0475
MC		 4507 (bp->tx_quick_cons_trip_int << 16) |
4508 bp->tx_quick_cons_trip);
4509
6f743ca0 4510 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
c76c0475
MC		 4511 (bp->tx_ticks_int << 16) | bp->tx_ticks);
4512
4513 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4514 }
4515
f86e82fb 4516 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
8e6a72c4
MC		 4517 val |= BNX2_HC_CONFIG_ONE_SHOT;
4518
4519 REG_WR(bp, BNX2_HC_CONFIG, val);
4520
b6016b76
MC		 4521 /* Clear internal stats counters. */
4522 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4523
da3e4fbe 4524 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
b6016b76
MC		 4525
4526 /* Initialize the receive filter. */
4527 bnx2_set_rx_mode(bp->dev);
4528
0aa38df7
MC		 4529 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4530 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4531 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4532 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4533 }
b090ae2b
MC		 4534 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4535 0);
b6016b76 4536
df149d70 4537 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
b6016b76
MC		 4538 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4539
4540 udelay(20);
4541
bf5295bb
MC		 4542 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4543
b090ae2b 4544 return rc;
b6016b76
MC		 4545}
4546
c76c0475
MC		 4547static void
4548bnx2_clear_ring_states(struct bnx2 *bp)
4549{
4550 struct bnx2_napi *bnapi;
4551 int i;
4552
4553 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
4554 bnapi = &bp->bnx2_napi[i];
4555
4556 bnapi->tx_cons = 0;
4557 bnapi->hw_tx_cons = 0;
4558 bnapi->rx_prod_bseq = 0;
4559 bnapi->rx_prod = 0;
4560 bnapi->rx_cons = 0;
4561 bnapi->rx_pg_prod = 0;
4562 bnapi->rx_pg_cons = 0;
4563 }
4564}
4565
59b47d8a
MC		 4566static void
4567bnx2_init_tx_context(struct bnx2 *bp, u32 cid)
4568{
4569 u32 val, offset0, offset1, offset2, offset3;
62a8313c 4570 u32 cid_addr = GET_CID_ADDR(cid);
59b47d8a
MC		 4571
4572 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4573 offset0 = BNX2_L2CTX_TYPE_XI;
4574 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4575 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4576 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4577 } else {
4578 offset0 = BNX2_L2CTX_TYPE;
4579 offset1 = BNX2_L2CTX_CMD_TYPE;
4580 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4581 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4582 }
4583 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
62a8313c 4584 bnx2_ctx_wr(bp, cid_addr, offset0, val);
59b47d8a
MC		 4585
4586 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
62a8313c 4587 bnx2_ctx_wr(bp, cid_addr, offset1, val);
59b47d8a
MC		 4588
4589 val = (u64) bp->tx_desc_mapping >> 32;
62a8313c 4590 bnx2_ctx_wr(bp, cid_addr, offset2, val);
59b47d8a
MC		 4591
4592 val = (u64) bp->tx_desc_mapping & 0xffffffff;
62a8313c 4593 bnx2_ctx_wr(bp, cid_addr, offset3, val);
59b47d8a 4594}
b6016b76
MC		 4595
4596static void
4597bnx2_init_tx_ring(struct bnx2 *bp)
4598{
4599 struct tx_bd *txbd;
c76c0475
MC		 4600 u32 cid = TX_CID;
4601 struct bnx2_napi *bnapi;
4602
4603 bp->tx_vec = 0;
f86e82fb 4604 if (bp->flags & BNX2_FLAG_USING_MSIX) {
c76c0475
MC		 4605 cid = TX_TSS_CID;
4606 bp->tx_vec = BNX2_TX_VEC;
4607 REG_WR(bp, BNX2_TSCH_TSS_CFG, BNX2_TX_INT_NUM |
4608 (TX_TSS_CID << 7));
4609 }
4610 bnapi = &bp->bnx2_napi[bp->tx_vec];
b6016b76 4611
2f8af120
MC		 4612 bp->tx_wake_thresh = bp->tx_ring_size / 2;
4613
b6016b76 4614 txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
6aa20a22 4615
b6016b76
MC		 4616 txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
4617 txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
4618
4619 bp->tx_prod = 0;
b6016b76 4620 bp->tx_prod_bseq = 0;
6aa20a22 4621
59b47d8a
MC		 4622 bp->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
4623 bp->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
b6016b76 4624
59b47d8a 4625 bnx2_init_tx_context(bp, cid);
b6016b76
MC		 4626}
4627
4628static void
5d5d0015
MC		 4629bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
4630 int num_rings)
b6016b76 4631{
b6016b76 4632 int i;
5d5d0015 4633 struct rx_bd *rxbd;
6aa20a22 4634
5d5d0015 4635 for (i = 0; i < num_rings; i++) {
13daffa2 4636 int j;
b6016b76 4637
5d5d0015 4638 rxbd = &rx_ring[i][0];
13daffa2 4639 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
5d5d0015 4640 rxbd->rx_bd_len = buf_size;
13daffa2
MC		 4641 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4642 }
5d5d0015 4643 if (i == (num_rings - 1))
13daffa2
MC		 4644 j = 0;
4645 else
4646 j = i + 1;
5d5d0015
MC		 4647 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
4648 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
13daffa2 4649 }
5d5d0015
MC		 4650}
4651
4652static void
4653bnx2_init_rx_ring(struct bnx2 *bp)
4654{
4655 int i;
4656 u16 prod, ring_prod;
4657 u32 val, rx_cid_addr = GET_CID_ADDR(RX_CID);
b4b36042 4658 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
5d5d0015 4659
5d5d0015
MC		 4660 bnx2_init_rxbd_rings(bp->rx_desc_ring, bp->rx_desc_mapping,
4661 bp->rx_buf_use_size, bp->rx_max_ring);
4662
83e3fc89
MC		 4663 bnx2_init_rx_context0(bp);
4664
4665 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4666 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
4667 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
4668 }
4669
62a8313c 4670 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
47bf4246
MC		 4671 if (bp->rx_pg_ring_size) {
4672 bnx2_init_rxbd_rings(bp->rx_pg_desc_ring,
4673 bp->rx_pg_desc_mapping,
4674 PAGE_SIZE, bp->rx_max_pg_ring);
4675 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
62a8313c
MC		 4676 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
4677 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
47bf4246
MC		 4678 BNX2_L2CTX_RBDC_JUMBO_KEY);
4679
4680 val = (u64) bp->rx_pg_desc_mapping[0] >> 32;
62a8313c 4681 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
47bf4246
MC		 4682
4683 val = (u64) bp->rx_pg_desc_mapping[0] & 0xffffffff;
62a8313c 4684 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
47bf4246
MC		 4685
4686 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4687 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
4688 }
b6016b76 4689
13daffa2 4690 val = (u64) bp->rx_desc_mapping[0] >> 32;
62a8313c 4691 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
b6016b76 4692
13daffa2 4693 val = (u64) bp->rx_desc_mapping[0] & 0xffffffff;
62a8313c 4694 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
b6016b76 4695
a1f60190 4696 ring_prod = prod = bnapi->rx_pg_prod;
47bf4246
MC		 4697 for (i = 0; i < bp->rx_pg_ring_size; i++) {
4698 if (bnx2_alloc_rx_page(bp, ring_prod) < 0)
4699 break;
4700 prod = NEXT_RX_BD(prod);
4701 ring_prod = RX_PG_RING_IDX(prod);
4702 }
a1f60190 4703 bnapi->rx_pg_prod = prod;
47bf4246 4704
a1f60190 4705 ring_prod = prod = bnapi->rx_prod;
236b6394 4706 for (i = 0; i < bp->rx_ring_size; i++) {
a1f60190 4707 if (bnx2_alloc_rx_skb(bp, bnapi, ring_prod) < 0) {
b6016b76
MC		 4708 break;
4709 }
4710 prod = NEXT_RX_BD(prod);
4711 ring_prod = RX_RING_IDX(prod);
4712 }
a1f60190 4713 bnapi->rx_prod = prod;
b6016b76 4714
a1f60190
MC		 4715 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_PG_BDIDX,
4716 bnapi->rx_pg_prod);
b6016b76
MC		 4717 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
4718
a1f60190 4719 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bnapi->rx_prod_bseq);
b6016b76
MC		 4720}
4721
5d5d0015 4722static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
13daffa2 4723{
5d5d0015 4724 u32 max, num_rings = 1;
13daffa2 4725
5d5d0015
MC		 4726 while (ring_size > MAX_RX_DESC_CNT) {
4727 ring_size -= MAX_RX_DESC_CNT;
13daffa2
MC		 4728 num_rings++;
4729 }
4730 /* round to next power of 2 */
5d5d0015 4731 max = max_size;
13daffa2
MC		 4732 while ((max & num_rings) == 0)
4733 max >>= 1;
4734
4735 if (num_rings != max)
4736 max <<= 1;
4737
5d5d0015
MC		 4738 return max;
4739}
4740
4741static void
4742bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
4743{
84eaa187 4744 u32 rx_size, rx_space, jumbo_size;
5d5d0015
MC		 4745
4746 /* 8 for CRC and VLAN */
4747 rx_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
4748
84eaa187
MC		 4749 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
4750 sizeof(struct skb_shared_info);
4751
5d5d0015 4752 bp->rx_copy_thresh = RX_COPY_THRESH;
47bf4246
MC		 4753 bp->rx_pg_ring_size = 0;
4754 bp->rx_max_pg_ring = 0;
4755 bp->rx_max_pg_ring_idx = 0;
f86e82fb 4756 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
84eaa187
MC		 4757 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
4758
4759 jumbo_size = size * pages;
4760 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
4761 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
4762
4763 bp->rx_pg_ring_size = jumbo_size;
4764 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
4765 MAX_RX_PG_RINGS);
4766 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
4767 rx_size = RX_COPY_THRESH + bp->rx_offset;
4768 bp->rx_copy_thresh = 0;
4769 }
5d5d0015
MC		 4770
4771 bp->rx_buf_use_size = rx_size;
4772 /* hw alignment */
4773 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
1db82f2a 4774 bp->rx_jumbo_thresh = rx_size - bp->rx_offset;
5d5d0015
MC		 4775 bp->rx_ring_size = size;
4776 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
13daffa2
MC		 4777 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
4778}
4779
b6016b76
MC		 4780static void
4781bnx2_free_tx_skbs(struct bnx2 *bp)
4782{
4783 int i;
4784
4785 if (bp->tx_buf_ring == NULL)
4786 return;
4787
4788 for (i = 0; i < TX_DESC_CNT; ) {
4789 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
4790 struct sk_buff *skb = tx_buf->skb;
4791 int j, last;
4792
4793 if (skb == NULL) {
4794 i++;
4795 continue;
4796 }
4797
4798 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
4799 skb_headlen(skb), PCI_DMA_TODEVICE);
4800
4801 tx_buf->skb = NULL;
4802
4803 last = skb_shinfo(skb)->nr_frags;
4804 for (j = 0; j < last; j++) {
4805 tx_buf = &bp->tx_buf_ring[i + j + 1];
4806 pci_unmap_page(bp->pdev,
4807 pci_unmap_addr(tx_buf, mapping),
4808 skb_shinfo(skb)->frags[j].size,
4809 PCI_DMA_TODEVICE);
4810 }
745720e5 4811 dev_kfree_skb(skb);
b6016b76
MC		 4812 i += j + 1;
4813 }
4814
4815}
4816
4817static void
4818bnx2_free_rx_skbs(struct bnx2 *bp)
4819{
4820 int i;
4821
4822 if (bp->rx_buf_ring == NULL)
4823 return;
4824
13daffa2 4825 for (i = 0; i < bp->rx_max_ring_idx; i++) {
b6016b76
MC		 4826 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
4827 struct sk_buff *skb = rx_buf->skb;
4828
05d0f1cf 4829 if (skb == NULL)
b6016b76
MC		 4830 continue;
4831
4832 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
4833 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
4834
4835 rx_buf->skb = NULL;
4836
745720e5 4837 dev_kfree_skb(skb);
b6016b76 4838 }
47bf4246
MC		 4839 for (i = 0; i < bp->rx_max_pg_ring_idx; i++)
4840 bnx2_free_rx_page(bp, i);
b6016b76
MC		 4841}
4842
4843static void
4844bnx2_free_skbs(struct bnx2 *bp)
4845{
4846 bnx2_free_tx_skbs(bp);
4847 bnx2_free_rx_skbs(bp);
4848}
4849
4850static int
4851bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
4852{
4853 int rc;
4854
4855 rc = bnx2_reset_chip(bp, reset_code);
4856 bnx2_free_skbs(bp);
4857 if (rc)
4858 return rc;
4859
fba9fe91
MC		 4860 if ((rc = bnx2_init_chip(bp)) != 0)
4861 return rc;
4862
c76c0475 4863 bnx2_clear_ring_states(bp);
b6016b76
MC		 4864 bnx2_init_tx_ring(bp);
4865 bnx2_init_rx_ring(bp);
4866 return 0;
4867}
4868
4869static int
4870bnx2_init_nic(struct bnx2 *bp)
4871{
4872 int rc;
4873
4874 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
4875 return rc;
4876
80be4434 4877 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 4878 bnx2_init_phy(bp);
4879 bnx2_set_link(bp);
543a827d
MC		 4880 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
4881 bnx2_remote_phy_event(bp);
0d8a6571 4882 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 4883 return 0;
4884}
4885
4886static int
4887bnx2_test_registers(struct bnx2 *bp)
4888{
4889 int ret;
5bae30c9 4890 int i, is_5709;
f71e1309 4891 static const struct {
b6016b76
MC		 4892 u16 offset;
4893 u16 flags;
5bae30c9 4894#define BNX2_FL_NOT_5709 1
b6016b76
MC		 4895 u32 rw_mask;
4896 u32 ro_mask;
4897 } reg_tbl[] = {
4898 { 0x006c, 0, 0x00000000, 0x0000003f },
4899 { 0x0090, 0, 0xffffffff, 0x00000000 },
4900 { 0x0094, 0, 0x00000000, 0x00000000 },
4901
5bae30c9
MC		 4902 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
4903 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4904 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4905 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
4906 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
4907 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
4908 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
4909 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4910 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4911
4912 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4913 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4914 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4915 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4916 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4917 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4918
4919 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
4920 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
4921 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
b6016b76
MC		 4922
4923 { 0x1000, 0, 0x00000000, 0x00000001 },
15b169cc 4924 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
b6016b76
MC		 4925
4926 { 0x1408, 0, 0x01c00800, 0x00000000 },
4927 { 0x149c, 0, 0x8000ffff, 0x00000000 },
4928 { 0x14a8, 0, 0x00000000, 0x000001ff },
5b0c76ad 4929 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
b6016b76
MC		 4930 { 0x14b0, 0, 0x00000002, 0x00000001 },
4931 { 0x14b8, 0, 0x00000000, 0x00000000 },
4932 { 0x14c0, 0, 0x00000000, 0x00000009 },
4933 { 0x14c4, 0, 0x00003fff, 0x00000000 },
4934 { 0x14cc, 0, 0x00000000, 0x00000001 },
4935 { 0x14d0, 0, 0xffffffff, 0x00000000 },
b6016b76
MC		 4936
4937 { 0x1800, 0, 0x00000000, 0x00000001 },
4938 { 0x1804, 0, 0x00000000, 0x00000003 },
b6016b76
MC		 4939
4940 { 0x2800, 0, 0x00000000, 0x00000001 },
4941 { 0x2804, 0, 0x00000000, 0x00003f01 },
4942 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
4943 { 0x2810, 0, 0xffff0000, 0x00000000 },
4944 { 0x2814, 0, 0xffff0000, 0x00000000 },
4945 { 0x2818, 0, 0xffff0000, 0x00000000 },
4946 { 0x281c, 0, 0xffff0000, 0x00000000 },
4947 { 0x2834, 0, 0xffffffff, 0x00000000 },
4948 { 0x2840, 0, 0x00000000, 0xffffffff },
4949 { 0x2844, 0, 0x00000000, 0xffffffff },
4950 { 0x2848, 0, 0xffffffff, 0x00000000 },
4951 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
4952
4953 { 0x2c00, 0, 0x00000000, 0x00000011 },
4954 { 0x2c04, 0, 0x00000000, 0x00030007 },
4955
b6016b76
MC		 4956 { 0x3c00, 0, 0x00000000, 0x00000001 },
4957 { 0x3c04, 0, 0x00000000, 0x00070000 },
4958 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
4959 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
4960 { 0x3c10, 0, 0xffffffff, 0x00000000 },
4961 { 0x3c14, 0, 0x00000000, 0xffffffff },
4962 { 0x3c18, 0, 0x00000000, 0xffffffff },
4963 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
4964 { 0x3c20, 0, 0xffffff00, 0x00000000 },
b6016b76
MC		 4965
4966 { 0x5004, 0, 0x00000000, 0x0000007f },
4967 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
b6016b76 4968
b6016b76
MC		 4969 { 0x5c00, 0, 0x00000000, 0x00000001 },
4970 { 0x5c04, 0, 0x00000000, 0x0003000f },
4971 { 0x5c08, 0, 0x00000003, 0x00000000 },
4972 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
4973 { 0x5c10, 0, 0x00000000, 0xffffffff },
4974 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
4975 { 0x5c84, 0, 0x00000000, 0x0000f333 },
4976 { 0x5c88, 0, 0x00000000, 0x00077373 },
4977 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
4978
4979 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
4980 { 0x680c, 0, 0xffffffff, 0x00000000 },
4981 { 0x6810, 0, 0xffffffff, 0x00000000 },
4982 { 0x6814, 0, 0xffffffff, 0x00000000 },
4983 { 0x6818, 0, 0xffffffff, 0x00000000 },
4984 { 0x681c, 0, 0xffffffff, 0x00000000 },
4985 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
4986 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
4987 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
4988 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
4989 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
4990 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
4991 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
4992 { 0x683c, 0, 0x0000ffff, 0x00000000 },
4993 { 0x6840, 0, 0x00000ff0, 0x00000000 },
4994 { 0x6844, 0, 0x00ffff00, 0x00000000 },
4995 { 0x684c, 0, 0xffffffff, 0x00000000 },
4996 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
4997 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
4998 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
4999 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5000 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5001 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5002
5003 { 0xffff, 0, 0x00000000, 0x00000000 },
5004 };
5005
5006 ret = 0;
5bae30c9
MC		 5007 is_5709 = 0;
5008 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5009 is_5709 = 1;
5010
b6016b76
MC		 5011 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5012 u32 offset, rw_mask, ro_mask, save_val, val;
5bae30c9
MC		 5013 u16 flags = reg_tbl[i].flags;
5014
5015 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5016 continue;
b6016b76
MC		 5017
5018 offset = (u32) reg_tbl[i].offset;
5019 rw_mask = reg_tbl[i].rw_mask;
5020 ro_mask = reg_tbl[i].ro_mask;
5021
14ab9b86 5022 save_val = readl(bp->regview + offset);
b6016b76 5023
14ab9b86 5024 writel(0, bp->regview + offset);
b6016b76 5025
14ab9b86 5026 val = readl(bp->regview + offset);
b6016b76
MC		 5027 if ((val & rw_mask) != 0) {
5028 goto reg_test_err;
5029 }
5030
5031 if ((val & ro_mask) != (save_val & ro_mask)) {
5032 goto reg_test_err;
5033 }
5034
14ab9b86 5035 writel(0xffffffff, bp->regview + offset);
b6016b76 5036
14ab9b86 5037 val = readl(bp->regview + offset);
b6016b76
MC		 5038 if ((val & rw_mask) != rw_mask) {
5039 goto reg_test_err;
5040 }
5041
5042 if ((val & ro_mask) != (save_val & ro_mask)) {
5043 goto reg_test_err;
5044 }
5045
14ab9b86 5046 writel(save_val, bp->regview + offset);
b6016b76
MC		 5047 continue;
5048
5049reg_test_err:
14ab9b86 5050 writel(save_val, bp->regview + offset);
b6016b76
MC		 5051 ret = -ENODEV;
5052 break;
5053 }
5054 return ret;
5055}
5056
5057static int
5058bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5059{
f71e1309 5060 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
b6016b76
MC		 5061 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5062 int i;
5063
5064 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5065 u32 offset;
5066
5067 for (offset = 0; offset < size; offset += 4) {
5068
2726d6e1 5069 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
b6016b76 5070
2726d6e1 5071 if (bnx2_reg_rd_ind(bp, start + offset) !=
b6016b76
MC		 5072 test_pattern[i]) {
5073 return -ENODEV;
5074 }
5075 }
5076 }
5077 return 0;
5078}
5079
5080static int
5081bnx2_test_memory(struct bnx2 *bp)
5082{
5083 int ret = 0;
5084 int i;
5bae30c9 5085 static struct mem_entry {
b6016b76
MC		 5086 u32 offset;
5087 u32 len;
5bae30c9 5088 } mem_tbl_5706[] = {
b6016b76 5089 { 0x60000, 0x4000 },
5b0c76ad 5090 { 0xa0000, 0x3000 },
b6016b76
MC		 5091 { 0xe0000, 0x4000 },
5092 { 0x120000, 0x4000 },
5093 { 0x1a0000, 0x4000 },
5094 { 0x160000, 0x4000 },
5095 { 0xffffffff, 0 },
5bae30c9
MC		 5096 },
5097 mem_tbl_5709[] = {
5098 { 0x60000, 0x4000 },
5099 { 0xa0000, 0x3000 },
5100 { 0xe0000, 0x4000 },
5101 { 0x120000, 0x4000 },
5102 { 0x1a0000, 0x4000 },
5103 { 0xffffffff, 0 },
b6016b76 5104 };
5bae30c9
MC		 5105 struct mem_entry *mem_tbl;
5106
5107 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5108 mem_tbl = mem_tbl_5709;
5109 else
5110 mem_tbl = mem_tbl_5706;
b6016b76
MC		 5111
5112 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5113 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5114 mem_tbl[i].len)) != 0) {
5115 return ret;
5116 }
5117 }
6aa20a22 5118
b6016b76
MC		 5119 return ret;
5120}
5121
bc5a0690
MC		 5122#define BNX2_MAC_LOOPBACK 0
5123#define BNX2_PHY_LOOPBACK 1
5124
b6016b76 5125static int
bc5a0690 5126bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
b6016b76
MC		 5127{
5128 unsigned int pkt_size, num_pkts, i;
5129 struct sk_buff *skb, *rx_skb;
5130 unsigned char *packet;
bc5a0690 5131 u16 rx_start_idx, rx_idx;
b6016b76
MC		 5132 dma_addr_t map;
5133 struct tx_bd *txbd;
5134 struct sw_bd *rx_buf;
5135 struct l2_fhdr *rx_hdr;
5136 int ret = -ENODEV;
c76c0475
MC		 5137 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5138
5139 tx_napi = bnapi;
f86e82fb 5140 if (bp->flags & BNX2_FLAG_USING_MSIX)
c76c0475 5141 tx_napi = &bp->bnx2_napi[BNX2_TX_VEC];
b6016b76 5142
bc5a0690
MC		 5143 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5144 bp->loopback = MAC_LOOPBACK;
5145 bnx2_set_mac_loopback(bp);
5146 }
5147 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
583c28e5 5148 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
489310a4
MC		 5149 return 0;
5150
80be4434 5151 bp->loopback = PHY_LOOPBACK;
bc5a0690
MC		 5152 bnx2_set_phy_loopback(bp);
5153 }
5154 else
5155 return -EINVAL;
b6016b76 5156
84eaa187 5157 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
932f3772 5158 skb = netdev_alloc_skb(bp->dev, pkt_size);
b6cbc3b6
JL		 5159 if (!skb)
5160 return -ENOMEM;
b6016b76 5161 packet = skb_put(skb, pkt_size);
6634292b 5162 memcpy(packet, bp->dev->dev_addr, 6);
b6016b76
MC		 5163 memset(packet + 6, 0x0, 8);
5164 for (i = 14; i < pkt_size; i++)
5165 packet[i] = (unsigned char) (i & 0xff);
5166
5167 map = pci_map_single(bp->pdev, skb->data, pkt_size,
5168 PCI_DMA_TODEVICE);
5169
bf5295bb
MC		 5170 REG_WR(bp, BNX2_HC_COMMAND,
5171 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5172
b6016b76
MC		 5173 REG_RD(bp, BNX2_HC_COMMAND);
5174
5175 udelay(5);
35efa7c1 5176 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
b6016b76 5177
b6016b76
MC		 5178 num_pkts = 0;
5179
bc5a0690 5180 txbd = &bp->tx_desc_ring[TX_RING_IDX(bp->tx_prod)];
b6016b76
MC		 5181
5182 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5183 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5184 txbd->tx_bd_mss_nbytes = pkt_size;
5185 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5186
5187 num_pkts++;
bc5a0690
MC		 5188 bp->tx_prod = NEXT_TX_BD(bp->tx_prod);
5189 bp->tx_prod_bseq += pkt_size;
b6016b76 5190
234754d5
MC		 5191 REG_WR16(bp, bp->tx_bidx_addr, bp->tx_prod);
5192 REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
b6016b76
MC		 5193
5194 udelay(100);
5195
bf5295bb
MC		 5196 REG_WR(bp, BNX2_HC_COMMAND,
5197 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5198
b6016b76
MC		 5199 REG_RD(bp, BNX2_HC_COMMAND);
5200
5201 udelay(5);
5202
5203 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
745720e5 5204 dev_kfree_skb(skb);
b6016b76 5205
c76c0475 5206 if (bnx2_get_hw_tx_cons(tx_napi) != bp->tx_prod)
b6016b76 5207 goto loopback_test_done;
b6016b76 5208
35efa7c1 5209 rx_idx = bnx2_get_hw_rx_cons(bnapi);
b6016b76
MC		 5210 if (rx_idx != rx_start_idx + num_pkts) {
5211 goto loopback_test_done;
5212 }
5213
5214 rx_buf = &bp->rx_buf_ring[rx_start_idx];
5215 rx_skb = rx_buf->skb;
5216
5217 rx_hdr = (struct l2_fhdr *) rx_skb->data;
5218 skb_reserve(rx_skb, bp->rx_offset);
5219
5220 pci_dma_sync_single_for_cpu(bp->pdev,
5221 pci_unmap_addr(rx_buf, mapping),
5222 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5223
ade2bfe7 5224 if (rx_hdr->l2_fhdr_status &
b6016b76
MC		 5225 (L2_FHDR_ERRORS_BAD_CRC |
5226 L2_FHDR_ERRORS_PHY_DECODE |
5227 L2_FHDR_ERRORS_ALIGNMENT |
5228 L2_FHDR_ERRORS_TOO_SHORT |
5229 L2_FHDR_ERRORS_GIANT_FRAME)) {
5230
5231 goto loopback_test_done;
5232 }
5233
5234 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5235 goto loopback_test_done;
5236 }
5237
5238 for (i = 14; i < pkt_size; i++) {
5239 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5240 goto loopback_test_done;
5241 }
5242 }
5243
5244 ret = 0;
5245
5246loopback_test_done:
5247 bp->loopback = 0;
5248 return ret;
5249}
5250
bc5a0690
MC		 5251#define BNX2_MAC_LOOPBACK_FAILED 1
5252#define BNX2_PHY_LOOPBACK_FAILED 2
5253#define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5254 BNX2_PHY_LOOPBACK_FAILED)
5255
5256static int
5257bnx2_test_loopback(struct bnx2 *bp)
5258{
5259 int rc = 0;
5260
5261 if (!netif_running(bp->dev))
5262 return BNX2_LOOPBACK_FAILED;
5263
5264 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5265 spin_lock_bh(&bp->phy_lock);
5266 bnx2_init_phy(bp);
5267 spin_unlock_bh(&bp->phy_lock);
5268 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5269 rc |= BNX2_MAC_LOOPBACK_FAILED;
5270 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5271 rc |= BNX2_PHY_LOOPBACK_FAILED;
5272 return rc;
5273}
5274
b6016b76
MC		 5275#define NVRAM_SIZE 0x200
5276#define CRC32_RESIDUAL 0xdebb20e3
5277
5278static int
5279bnx2_test_nvram(struct bnx2 *bp)
5280{
b491edd5 5281 __be32 buf[NVRAM_SIZE / 4];
b6016b76
MC		 5282 u8 *data = (u8 *) buf;
5283 int rc = 0;
5284 u32 magic, csum;
5285
5286 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5287 goto test_nvram_done;
5288
5289 magic = be32_to_cpu(buf[0]);
5290 if (magic != 0x669955aa) {
5291 rc = -ENODEV;
5292 goto test_nvram_done;
5293 }
5294
5295 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5296 goto test_nvram_done;
5297
5298 csum = ether_crc_le(0x100, data);
5299 if (csum != CRC32_RESIDUAL) {
5300 rc = -ENODEV;
5301 goto test_nvram_done;
5302 }
5303
5304 csum = ether_crc_le(0x100, data + 0x100);
5305 if (csum != CRC32_RESIDUAL) {
5306 rc = -ENODEV;
5307 }
5308
5309test_nvram_done:
5310 return rc;
5311}
5312
5313static int
5314bnx2_test_link(struct bnx2 *bp)
5315{
5316 u32 bmsr;
5317
583c28e5 5318 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
489310a4
MC		 5319 if (bp->link_up)
5320 return 0;
5321 return -ENODEV;
5322 }
c770a65c 5323 spin_lock_bh(&bp->phy_lock);
27a005b8
MC		 5324 bnx2_enable_bmsr1(bp);
5325 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5326 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5327 bnx2_disable_bmsr1(bp);
c770a65c 5328 spin_unlock_bh(&bp->phy_lock);
6aa20a22 5329
b6016b76
MC		 5330 if (bmsr & BMSR_LSTATUS) {
5331 return 0;
5332 }
5333 return -ENODEV;
5334}
5335
5336static int
5337bnx2_test_intr(struct bnx2 *bp)
5338{
5339 int i;
b6016b76
MC		 5340 u16 status_idx;
5341
5342 if (!netif_running(bp->dev))
5343 return -ENODEV;
5344
5345 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5346
5347 /* This register is not touched during run-time. */
bf5295bb 5348 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
b6016b76
MC		 5349 REG_RD(bp, BNX2_HC_COMMAND);
5350
5351 for (i = 0; i < 10; i++) {
5352 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5353 status_idx) {
5354
5355 break;
5356 }
5357
5358 msleep_interruptible(10);
5359 }
5360 if (i < 10)
5361 return 0;
5362
5363 return -ENODEV;
5364}
5365
38ea3686 5366/* Determining link for parallel detection. */
b2fadeae
MC		 5367static int
5368bnx2_5706_serdes_has_link(struct bnx2 *bp)
5369{
5370 u32 mode_ctl, an_dbg, exp;
5371
38ea3686
MC		 5372 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5373 return 0;
5374
b2fadeae
MC		 5375 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5376 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5377
5378 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5379 return 0;
5380
5381 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5382 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5383 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5384
f3014c0c 5385 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
b2fadeae
MC		 5386 return 0;
5387
5388 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5389 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5390 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5391
5392 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
5393 return 0;
5394
5395 return 1;
5396}
5397
b6016b76 5398static void
48b01e2d 5399bnx2_5706_serdes_timer(struct bnx2 *bp)
b6016b76 5400{
b2fadeae
MC		 5401 int check_link = 1;
5402
48b01e2d 5403 spin_lock(&bp->phy_lock);
b2fadeae 5404 if (bp->serdes_an_pending) {
48b01e2d 5405 bp->serdes_an_pending--;
b2fadeae
MC		 5406 check_link = 0;
5407 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
48b01e2d 5408 u32 bmcr;
b6016b76 5409
48b01e2d 5410 bp->current_interval = bp->timer_interval;
cd339a0e 5411
ca58c3af 5412 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76 5413
48b01e2d 5414 if (bmcr & BMCR_ANENABLE) {
b2fadeae 5415 if (bnx2_5706_serdes_has_link(bp)) {
48b01e2d
MC		 5416 bmcr &= ~BMCR_ANENABLE;
5417 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
ca58c3af 5418 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
583c28e5 5419 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
48b01e2d 5420 }
b6016b76 5421 }
48b01e2d
MC		 5422 }
5423 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
583c28e5 5424 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
48b01e2d 5425 u32 phy2;
b6016b76 5426
48b01e2d
MC		 5427 bnx2_write_phy(bp, 0x17, 0x0f01);
5428 bnx2_read_phy(bp, 0x15, &phy2);
5429 if (phy2 & 0x20) {
5430 u32 bmcr;
cd339a0e 5431
ca58c3af 5432 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
48b01e2d 5433 bmcr |= BMCR_ANENABLE;
ca58c3af 5434 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
b6016b76 5435
583c28e5 5436 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
48b01e2d
MC		 5437 }
5438 } else
5439 bp->current_interval = bp->timer_interval;
b6016b76 5440
a2724e25 5441 if (check_link) {
b2fadeae
MC		 5442 u32 val;
5443
5444 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5445 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5446 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5447
a2724e25
MC		 5448 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
5449 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
5450 bnx2_5706s_force_link_dn(bp, 1);
5451 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
5452 } else
5453 bnx2_set_link(bp);
5454 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
5455 bnx2_set_link(bp);
b2fadeae 5456 }
48b01e2d
MC		 5457 spin_unlock(&bp->phy_lock);
5458}
b6016b76 5459
f8dd064e
MC		 5460static void
5461bnx2_5708_serdes_timer(struct bnx2 *bp)
5462{
583c28e5 5463 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 5464 return;
5465
583c28e5 5466 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
f8dd064e
MC		 5467 bp->serdes_an_pending = 0;
5468 return;
5469 }
b6016b76 5470
f8dd064e
MC		 5471 spin_lock(&bp->phy_lock);
5472 if (bp->serdes_an_pending)
5473 bp->serdes_an_pending--;
5474 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5475 u32 bmcr;
b6016b76 5476
ca58c3af 5477 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
f8dd064e 5478 if (bmcr & BMCR_ANENABLE) {
605a9e20 5479 bnx2_enable_forced_2g5(bp);
f8dd064e
MC		 5480 bp->current_interval = SERDES_FORCED_TIMEOUT;
5481 } else {
605a9e20 5482 bnx2_disable_forced_2g5(bp);
f8dd064e
MC		 5483 bp->serdes_an_pending = 2;
5484 bp->current_interval = bp->timer_interval;
b6016b76 5485 }
b6016b76 5486
f8dd064e
MC		 5487 } else
5488 bp->current_interval = bp->timer_interval;
b6016b76 5489
f8dd064e
MC		 5490 spin_unlock(&bp->phy_lock);
5491}
5492
48b01e2d
MC		 5493static void
5494bnx2_timer(unsigned long data)
5495{
5496 struct bnx2 *bp = (struct bnx2 *) data;
b6016b76 5497
48b01e2d
MC		 5498 if (!netif_running(bp->dev))
5499 return;
b6016b76 5500
48b01e2d
MC		 5501 if (atomic_read(&bp->intr_sem) != 0)
5502 goto bnx2_restart_timer;
b6016b76 5503
df149d70 5504 bnx2_send_heart_beat(bp);
b6016b76 5505
2726d6e1
MC		 5506 bp->stats_blk->stat_FwRxDrop =
5507 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
b6016b76 5508
02537b06
MC		 5509 /* workaround occasional corrupted counters */
5510 if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
5511 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
5512 BNX2_HC_COMMAND_STATS_NOW);
5513
583c28e5 5514 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
f8dd064e
MC		 5515 if (CHIP_NUM(bp) == CHIP_NUM_5706)
5516 bnx2_5706_serdes_timer(bp);
27a005b8 5517 else
f8dd064e 5518 bnx2_5708_serdes_timer(bp);
b6016b76
MC		 5519 }
5520
5521bnx2_restart_timer:
cd339a0e 5522 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 5523}
5524
8e6a72c4
MC		 5525static int
5526bnx2_request_irq(struct bnx2 *bp)
5527{
5528 struct net_device *dev = bp->dev;
6d866ffc 5529 unsigned long flags;
b4b36042
MC		 5530 struct bnx2_irq *irq;
5531 int rc = 0, i;
8e6a72c4 5532
f86e82fb 5533 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
6d866ffc
MC		 5534 flags = 0;
5535 else
5536 flags = IRQF_SHARED;
b4b36042
MC		 5537
5538 for (i = 0; i < bp->irq_nvecs; i++) {
5539 irq = &bp->irq_tbl[i];
c76c0475 5540 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
b4b36042
MC		 5541 dev);
5542 if (rc)
5543 break;
5544 irq->requested = 1;
5545 }
8e6a72c4
MC		 5546 return rc;
5547}
5548
5549static void
5550bnx2_free_irq(struct bnx2 *bp)
5551{
5552 struct net_device *dev = bp->dev;
b4b36042
MC		 5553 struct bnx2_irq *irq;
5554 int i;
8e6a72c4 5555
b4b36042
MC		 5556 for (i = 0; i < bp->irq_nvecs; i++) {
5557 irq = &bp->irq_tbl[i];
5558 if (irq->requested)
5559 free_irq(irq->vector, dev);
5560 irq->requested = 0;
6d866ffc 5561 }
f86e82fb 5562 if (bp->flags & BNX2_FLAG_USING_MSI)
b4b36042 5563 pci_disable_msi(bp->pdev);
f86e82fb 5564 else if (bp->flags & BNX2_FLAG_USING_MSIX)
b4b36042
MC		 5565 pci_disable_msix(bp->pdev);
5566
f86e82fb 5567 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
b4b36042
MC		 5568}
5569
5570static void
5571bnx2_enable_msix(struct bnx2 *bp)
5572{
57851d84
MC		 5573 int i, rc;
5574 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
5575
b4b36042
MC		 5576 bnx2_setup_msix_tbl(bp);
5577 REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
5578 REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
5579 REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
57851d84
MC		 5580
5581 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5582 msix_ent[i].entry = i;
5583 msix_ent[i].vector = 0;
5584 }
5585
5586 rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
5587 if (rc != 0)
5588 return;
5589
5590 bp->irq_tbl[BNX2_BASE_VEC].handler = bnx2_msi_1shot;
5591 bp->irq_tbl[BNX2_TX_VEC].handler = bnx2_tx_msix;
5592
5593 strcpy(bp->irq_tbl[BNX2_BASE_VEC].name, bp->dev->name);
5594 strcat(bp->irq_tbl[BNX2_BASE_VEC].name, "-base");
5595 strcpy(bp->irq_tbl[BNX2_TX_VEC].name, bp->dev->name);
5596 strcat(bp->irq_tbl[BNX2_TX_VEC].name, "-tx");
5597
5598 bp->irq_nvecs = BNX2_MAX_MSIX_VEC;
f86e82fb 5599 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
57851d84
MC		 5600 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
5601 bp->irq_tbl[i].vector = msix_ent[i].vector;
6d866ffc
MC		 5602}
5603
5604static void
5605bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
5606{
5607 bp->irq_tbl[0].handler = bnx2_interrupt;
5608 strcpy(bp->irq_tbl[0].name, bp->dev->name);
b4b36042
MC		 5609 bp->irq_nvecs = 1;
5610 bp->irq_tbl[0].vector = bp->pdev->irq;
5611
f86e82fb 5612 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi)
b4b36042 5613 bnx2_enable_msix(bp);
6d866ffc 5614
f86e82fb
DM		 5615 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
5616 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
6d866ffc 5617 if (pci_enable_msi(bp->pdev) == 0) {
f86e82fb 5618 bp->flags |= BNX2_FLAG_USING_MSI;
6d866ffc 5619 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
f86e82fb 5620 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
6d866ffc
MC		 5621 bp->irq_tbl[0].handler = bnx2_msi_1shot;
5622 } else
5623 bp->irq_tbl[0].handler = bnx2_msi;
b4b36042
MC		 5624
5625 bp->irq_tbl[0].vector = bp->pdev->irq;
6d866ffc
MC		 5626 }
5627 }
8e6a72c4
MC		 5628}
5629
b6016b76
MC		 5630/* Called with rtnl_lock */
5631static int
5632bnx2_open(struct net_device *dev)
5633{
972ec0d4 5634 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5635 int rc;
5636
1b2f922f
MC		 5637 netif_carrier_off(dev);
5638
829ca9a3 5639 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 5640 bnx2_disable_int(bp);
5641
5642 rc = bnx2_alloc_mem(bp);
5643 if (rc)
5644 return rc;
5645
6d866ffc 5646 bnx2_setup_int_mode(bp, disable_msi);
35efa7c1 5647 bnx2_napi_enable(bp);
8e6a72c4
MC		 5648 rc = bnx2_request_irq(bp);
5649
b6016b76 5650 if (rc) {
35efa7c1 5651 bnx2_napi_disable(bp);
b6016b76
MC		 5652 bnx2_free_mem(bp);
5653 return rc;
5654 }
5655
5656 rc = bnx2_init_nic(bp);
5657
5658 if (rc) {
35efa7c1 5659 bnx2_napi_disable(bp);
8e6a72c4 5660 bnx2_free_irq(bp);
b6016b76
MC		 5661 bnx2_free_skbs(bp);
5662 bnx2_free_mem(bp);
5663 return rc;
5664 }
6aa20a22 5665
cd339a0e 5666 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 5667
5668 atomic_set(&bp->intr_sem, 0);
5669
5670 bnx2_enable_int(bp);
5671
f86e82fb 5672 if (bp->flags & BNX2_FLAG_USING_MSI) {
b6016b76
MC		 5673 /* Test MSI to make sure it is working
5674 * If MSI test fails, go back to INTx mode
5675 */
5676 if (bnx2_test_intr(bp) != 0) {
5677 printk(KERN_WARNING PFX "%s: No interrupt was generated"
5678 " using MSI, switching to INTx mode. Please"
5679 " report this failure to the PCI maintainer"
5680 " and include system chipset information.\n",
5681 bp->dev->name);
5682
5683 bnx2_disable_int(bp);
8e6a72c4 5684 bnx2_free_irq(bp);
b6016b76 5685
6d866ffc
MC		 5686 bnx2_setup_int_mode(bp, 1);
5687
b6016b76
MC		 5688 rc = bnx2_init_nic(bp);
5689
8e6a72c4
MC		 5690 if (!rc)
5691 rc = bnx2_request_irq(bp);
5692
b6016b76 5693 if (rc) {
35efa7c1 5694 bnx2_napi_disable(bp);
b6016b76
MC		 5695 bnx2_free_skbs(bp);
5696 bnx2_free_mem(bp);
5697 del_timer_sync(&bp->timer);
5698 return rc;
5699 }
5700 bnx2_enable_int(bp);
5701 }
5702 }
f86e82fb 5703 if (bp->flags & BNX2_FLAG_USING_MSI)
b6016b76 5704 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
f86e82fb 5705 else if (bp->flags & BNX2_FLAG_USING_MSIX)
57851d84 5706 printk(KERN_INFO PFX "%s: using MSIX\n", dev->name);
b6016b76
MC		 5707
5708 netif_start_queue(dev);
5709
5710 return 0;
5711}
5712
5713static void
c4028958 5714bnx2_reset_task(struct work_struct *work)
b6016b76 5715{
c4028958 5716 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
b6016b76 5717
afdc08b9
MC		 5718 if (!netif_running(bp->dev))
5719 return;
5720
5721 bp->in_reset_task = 1;
b6016b76
MC		 5722 bnx2_netif_stop(bp);
5723
5724 bnx2_init_nic(bp);
5725
5726 atomic_set(&bp->intr_sem, 1);
5727 bnx2_netif_start(bp);
afdc08b9 5728 bp->in_reset_task = 0;
b6016b76
MC		 5729}
5730
5731static void
5732bnx2_tx_timeout(struct net_device *dev)
5733{
972ec0d4 5734 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5735
5736 /* This allows the netif to be shutdown gracefully before resetting */
5737 schedule_work(&bp->reset_task);
5738}
5739
5740#ifdef BCM_VLAN
5741/* Called with rtnl_lock */
5742static void
5743bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
5744{
972ec0d4 5745 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5746
5747 bnx2_netif_stop(bp);
5748
5749 bp->vlgrp = vlgrp;
5750 bnx2_set_rx_mode(dev);
5751
5752 bnx2_netif_start(bp);
5753}
b6016b76
MC		 5754#endif
5755
932ff279 5756/* Called with netif_tx_lock.
2f8af120
MC		 5757 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
5758 * netif_wake_queue().
b6016b76
MC		 5759 */
5760static int
5761bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
5762{
972ec0d4 5763 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5764 dma_addr_t mapping;
5765 struct tx_bd *txbd;
5766 struct sw_bd *tx_buf;
5767 u32 len, vlan_tag_flags, last_frag, mss;
5768 u16 prod, ring_prod;
5769 int i;
57851d84 5770 struct bnx2_napi *bnapi = &bp->bnx2_napi[bp->tx_vec];
b6016b76 5771
a550c99b
MC		 5772 if (unlikely(bnx2_tx_avail(bp, bnapi) <
5773 (skb_shinfo(skb)->nr_frags + 1))) {
b6016b76
MC		 5774 netif_stop_queue(dev);
5775 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
5776 dev->name);
5777
5778 return NETDEV_TX_BUSY;
5779 }
5780 len = skb_headlen(skb);
5781 prod = bp->tx_prod;
5782 ring_prod = TX_RING_IDX(prod);
5783
5784 vlan_tag_flags = 0;
84fa7933 5785 if (skb->ip_summed == CHECKSUM_PARTIAL) {
b6016b76
MC		 5786 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
5787 }
5788
79ea13ce 5789 if (bp->vlgrp && vlan_tx_tag_present(skb)) {
b6016b76
MC		 5790 vlan_tag_flags |=
5791 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
5792 }
fde82055 5793 if ((mss = skb_shinfo(skb)->gso_size)) {
b6016b76 5794 u32 tcp_opt_len, ip_tcp_len;
eddc9ec5 5795 struct iphdr *iph;
b6016b76 5796
b6016b76
MC		 5797 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
5798
4666f87a
MC		 5799 tcp_opt_len = tcp_optlen(skb);
5800
5801 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
5802 u32 tcp_off = skb_transport_offset(skb) -
5803 sizeof(struct ipv6hdr) - ETH_HLEN;
ab6a5bb6 5804
4666f87a
MC		 5805 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
5806 TX_BD_FLAGS_SW_FLAGS;
5807 if (likely(tcp_off == 0))
5808 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
5809 else {
5810 tcp_off >>= 3;
5811 vlan_tag_flags |= ((tcp_off & 0x3) <<
5812 TX_BD_FLAGS_TCP6_OFF0_SHL) |
5813 ((tcp_off & 0x10) <<
5814 TX_BD_FLAGS_TCP6_OFF4_SHL);
5815 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
5816 }
5817 } else {
5818 if (skb_header_cloned(skb) &&
5819 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5820 dev_kfree_skb(skb);
5821 return NETDEV_TX_OK;
5822 }
b6016b76 5823
4666f87a
MC		 5824 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5825
5826 iph = ip_hdr(skb);
5827 iph->check = 0;
5828 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5829 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5830 iph->daddr, 0,
5831 IPPROTO_TCP,
5832 0);
5833 if (tcp_opt_len || (iph->ihl > 5)) {
5834 vlan_tag_flags |= ((iph->ihl - 5) +
5835 (tcp_opt_len >> 2)) << 8;
5836 }
b6016b76 5837 }
4666f87a 5838 } else
b6016b76 5839 mss = 0;
b6016b76
MC		 5840
5841 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6aa20a22 5842
b6016b76
MC		 5843 tx_buf = &bp->tx_buf_ring[ring_prod];
5844 tx_buf->skb = skb;
5845 pci_unmap_addr_set(tx_buf, mapping, mapping);
5846
5847 txbd = &bp->tx_desc_ring[ring_prod];
5848
5849 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
5850 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
5851 txbd->tx_bd_mss_nbytes = len | (mss << 16);
5852 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
5853
5854 last_frag = skb_shinfo(skb)->nr_frags;
5855
5856 for (i = 0; i < last_frag; i++) {
5857 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5858
5859 prod = NEXT_TX_BD(prod);
5860 ring_prod = TX_RING_IDX(prod);
5861 txbd = &bp->tx_desc_ring[ring_prod];
5862
5863 len = frag->size;
5864 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
5865 len, PCI_DMA_TODEVICE);
5866 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
5867 mapping, mapping);
5868
5869 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
5870 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
5871 txbd->tx_bd_mss_nbytes = len | (mss << 16);
5872 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
5873
5874 }
5875 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
5876
5877 prod = NEXT_TX_BD(prod);
5878 bp->tx_prod_bseq += skb->len;
5879
234754d5
MC		 5880 REG_WR16(bp, bp->tx_bidx_addr, prod);
5881 REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
b6016b76
MC		 5882
5883 mmiowb();
5884
5885 bp->tx_prod = prod;
5886 dev->trans_start = jiffies;
5887
a550c99b 5888 if (unlikely(bnx2_tx_avail(bp, bnapi) <= MAX_SKB_FRAGS)) {
e89bbf10 5889 netif_stop_queue(dev);
a550c99b 5890 if (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh)
e89bbf10 5891 netif_wake_queue(dev);
b6016b76
MC		 5892 }
5893
5894 return NETDEV_TX_OK;
5895}
5896
5897/* Called with rtnl_lock */
5898static int
5899bnx2_close(struct net_device *dev)
5900{
972ec0d4 5901 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5902 u32 reset_code;
5903
afdc08b9
MC		 5904 /* Calling flush_scheduled_work() may deadlock because
5905 * linkwatch_event() may be on the workqueue and it will try to get
5906 * the rtnl_lock which we are holding.
5907 */
5908 while (bp->in_reset_task)
5909 msleep(1);
5910
bea3348e 5911 bnx2_disable_int_sync(bp);
35efa7c1 5912 bnx2_napi_disable(bp);
b6016b76 5913 del_timer_sync(&bp->timer);
f86e82fb 5914 if (bp->flags & BNX2_FLAG_NO_WOL)
6c4f095e 5915 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
dda1e390 5916 else if (bp->wol)
b6016b76
MC		 5917 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5918 else
5919 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5920 bnx2_reset_chip(bp, reset_code);
8e6a72c4 5921 bnx2_free_irq(bp);
b6016b76
MC		 5922 bnx2_free_skbs(bp);
5923 bnx2_free_mem(bp);
5924 bp->link_up = 0;
5925 netif_carrier_off(bp->dev);
829ca9a3 5926 bnx2_set_power_state(bp, PCI_D3hot);
b6016b76
MC		 5927 return 0;
5928}
5929
5930#define GET_NET_STATS64(ctr) \
5931 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
5932 (unsigned long) (ctr##_lo)
5933
5934#define GET_NET_STATS32(ctr) \
5935 (ctr##_lo)
5936
5937#if (BITS_PER_LONG == 64)
5938#define GET_NET_STATS GET_NET_STATS64
5939#else
5940#define GET_NET_STATS GET_NET_STATS32
5941#endif
5942
5943static struct net_device_stats *
5944bnx2_get_stats(struct net_device *dev)
5945{
972ec0d4 5946 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 5947 struct statistics_block *stats_blk = bp->stats_blk;
5948 struct net_device_stats *net_stats = &bp->net_stats;
5949
5950 if (bp->stats_blk == NULL) {
5951 return net_stats;
5952 }
5953 net_stats->rx_packets =
5954 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
5955 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
5956 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
5957
5958 net_stats->tx_packets =
5959 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
5960 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
5961 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
5962
5963 net_stats->rx_bytes =
5964 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
5965
5966 net_stats->tx_bytes =
5967 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
5968
6aa20a22 5969 net_stats->multicast =
b6016b76
MC		 5970 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
5971
6aa20a22 5972 net_stats->collisions =
b6016b76
MC		 5973 (unsigned long) stats_blk->stat_EtherStatsCollisions;
5974
6aa20a22 5975 net_stats->rx_length_errors =
b6016b76
MC		 5976 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
5977 stats_blk->stat_EtherStatsOverrsizePkts);
5978
6aa20a22 5979 net_stats->rx_over_errors =
b6016b76
MC		 5980 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
5981
6aa20a22 5982 net_stats->rx_frame_errors =
b6016b76
MC		 5983 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
5984
6aa20a22 5985 net_stats->rx_crc_errors =
b6016b76
MC		 5986 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
5987
5988 net_stats->rx_errors = net_stats->rx_length_errors +
5989 net_stats->rx_over_errors + net_stats->rx_frame_errors +
5990 net_stats->rx_crc_errors;
5991
5992 net_stats->tx_aborted_errors =
5993 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
5994 stats_blk->stat_Dot3StatsLateCollisions);
5995
5b0c76ad
MC		 5996 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
5997 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76
MC		 5998 net_stats->tx_carrier_errors = 0;
5999 else {
6000 net_stats->tx_carrier_errors =
6001 (unsigned long)
6002 stats_blk->stat_Dot3StatsCarrierSenseErrors;
6003 }
6004
6005 net_stats->tx_errors =
6aa20a22 6006 (unsigned long)
b6016b76
MC		 6007 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
6008 +
6009 net_stats->tx_aborted_errors +
6010 net_stats->tx_carrier_errors;
6011
cea94db9
MC		 6012 net_stats->rx_missed_errors =
6013 (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
6014 stats_blk->stat_FwRxDrop);
6015
b6016b76
MC		 6016 return net_stats;
6017}
6018
6019/* All ethtool functions called with rtnl_lock */
6020
6021static int
6022bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6023{
972ec0d4 6024 struct bnx2 *bp = netdev_priv(dev);
7b6b8347 6025 int support_serdes = 0, support_copper = 0;
b6016b76
MC		 6026
6027 cmd->supported = SUPPORTED_Autoneg;
583c28e5 6028 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
7b6b8347
MC		 6029 support_serdes = 1;
6030 support_copper = 1;
6031 } else if (bp->phy_port == PORT_FIBRE)
6032 support_serdes = 1;
6033 else
6034 support_copper = 1;
6035
6036 if (support_serdes) {
b6016b76
MC		 6037 cmd->supported |= SUPPORTED_1000baseT_Full |
6038 SUPPORTED_FIBRE;
583c28e5 6039 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
605a9e20 6040 cmd->supported |= SUPPORTED_2500baseX_Full;
b6016b76 6041
b6016b76 6042 }
7b6b8347 6043 if (support_copper) {
b6016b76
MC		 6044 cmd->supported |= SUPPORTED_10baseT_Half |
6045 SUPPORTED_10baseT_Full |
6046 SUPPORTED_100baseT_Half |
6047 SUPPORTED_100baseT_Full |
6048 SUPPORTED_1000baseT_Full |
6049 SUPPORTED_TP;
6050
b6016b76
MC		 6051 }
6052
7b6b8347
MC		 6053 spin_lock_bh(&bp->phy_lock);
6054 cmd->port = bp->phy_port;
b6016b76
MC		 6055 cmd->advertising = bp->advertising;
6056
6057 if (bp->autoneg & AUTONEG_SPEED) {
6058 cmd->autoneg = AUTONEG_ENABLE;
6059 }
6060 else {
6061 cmd->autoneg = AUTONEG_DISABLE;
6062 }
6063
6064 if (netif_carrier_ok(dev)) {
6065 cmd->speed = bp->line_speed;
6066 cmd->duplex = bp->duplex;
6067 }
6068 else {
6069 cmd->speed = -1;
6070 cmd->duplex = -1;
6071 }
7b6b8347 6072 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6073
6074 cmd->transceiver = XCVR_INTERNAL;
6075 cmd->phy_address = bp->phy_addr;
6076
6077 return 0;
6078}
6aa20a22 6079
b6016b76
MC		 6080static int
6081bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6082{
972ec0d4 6083 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6084 u8 autoneg = bp->autoneg;
6085 u8 req_duplex = bp->req_duplex;
6086 u16 req_line_speed = bp->req_line_speed;
6087 u32 advertising = bp->advertising;
7b6b8347
MC		 6088 int err = -EINVAL;
6089
6090 spin_lock_bh(&bp->phy_lock);
6091
6092 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6093 goto err_out_unlock;
6094
583c28e5
MC		 6095 if (cmd->port != bp->phy_port &&
6096 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
7b6b8347 6097 goto err_out_unlock;
b6016b76
MC		 6098
6099 if (cmd->autoneg == AUTONEG_ENABLE) {
6100 autoneg |= AUTONEG_SPEED;
6101
6aa20a22 6102 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
b6016b76
MC		 6103
6104 /* allow advertising 1 speed */
6105 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
6106 (cmd->advertising == ADVERTISED_10baseT_Full) ||
6107 (cmd->advertising == ADVERTISED_100baseT_Half) ||
6108 (cmd->advertising == ADVERTISED_100baseT_Full)) {
6109
7b6b8347
MC		 6110 if (cmd->port == PORT_FIBRE)
6111 goto err_out_unlock;
b6016b76
MC		 6112
6113 advertising = cmd->advertising;
6114
27a005b8 6115 } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
583c28e5 6116 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ||
7b6b8347
MC		 6117 (cmd->port == PORT_TP))
6118 goto err_out_unlock;
6119 } else if (cmd->advertising == ADVERTISED_1000baseT_Full)
b6016b76 6120 advertising = cmd->advertising;
7b6b8347
MC		 6121 else if (cmd->advertising == ADVERTISED_1000baseT_Half)
6122 goto err_out_unlock;
b6016b76 6123 else {
7b6b8347 6124 if (cmd->port == PORT_FIBRE)
b6016b76 6125 advertising = ETHTOOL_ALL_FIBRE_SPEED;
7b6b8347 6126 else
b6016b76 6127 advertising = ETHTOOL_ALL_COPPER_SPEED;
b6016b76
MC		 6128 }
6129 advertising |= ADVERTISED_Autoneg;
6130 }
6131 else {
7b6b8347 6132 if (cmd->port == PORT_FIBRE) {
80be4434
MC		 6133 if ((cmd->speed != SPEED_1000 &&
6134 cmd->speed != SPEED_2500) ||
6135 (cmd->duplex != DUPLEX_FULL))
7b6b8347 6136 goto err_out_unlock;
80be4434
MC		 6137
6138 if (cmd->speed == SPEED_2500 &&
583c28e5 6139 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
7b6b8347 6140 goto err_out_unlock;
b6016b76 6141 }
7b6b8347
MC		 6142 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6143 goto err_out_unlock;
6144
b6016b76
MC		 6145 autoneg &= ~AUTONEG_SPEED;
6146 req_line_speed = cmd->speed;
6147 req_duplex = cmd->duplex;
6148 advertising = 0;
6149 }
6150
6151 bp->autoneg = autoneg;
6152 bp->advertising = advertising;
6153 bp->req_line_speed = req_line_speed;
6154 bp->req_duplex = req_duplex;
6155
7b6b8347 6156 err = bnx2_setup_phy(bp, cmd->port);
b6016b76 6157
7b6b8347 6158err_out_unlock:
c770a65c 6159 spin_unlock_bh(&bp->phy_lock);
b6016b76 6160
7b6b8347 6161 return err;
b6016b76
MC		 6162}
6163
6164static void
6165bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6166{
972ec0d4 6167 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6168
6169 strcpy(info->driver, DRV_MODULE_NAME);
6170 strcpy(info->version, DRV_MODULE_VERSION);
6171 strcpy(info->bus_info, pci_name(bp->pdev));
58fc2ea4 6172 strcpy(info->fw_version, bp->fw_version);
b6016b76
MC		 6173}
6174
244ac4f4
MC		 6175#define BNX2_REGDUMP_LEN (32 * 1024)
6176
6177static int
6178bnx2_get_regs_len(struct net_device *dev)
6179{
6180 return BNX2_REGDUMP_LEN;
6181}
6182
6183static void
6184bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6185{
6186 u32 *p = _p, i, offset;
6187 u8 *orig_p = _p;
6188 struct bnx2 *bp = netdev_priv(dev);
6189 u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6190 0x0800, 0x0880, 0x0c00, 0x0c10,
6191 0x0c30, 0x0d08, 0x1000, 0x101c,
6192 0x1040, 0x1048, 0x1080, 0x10a4,
6193 0x1400, 0x1490, 0x1498, 0x14f0,
6194 0x1500, 0x155c, 0x1580, 0x15dc,
6195 0x1600, 0x1658, 0x1680, 0x16d8,
6196 0x1800, 0x1820, 0x1840, 0x1854,
6197 0x1880, 0x1894, 0x1900, 0x1984,
6198 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6199 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6200 0x2000, 0x2030, 0x23c0, 0x2400,
6201 0x2800, 0x2820, 0x2830, 0x2850,
6202 0x2b40, 0x2c10, 0x2fc0, 0x3058,
6203 0x3c00, 0x3c94, 0x4000, 0x4010,
6204 0x4080, 0x4090, 0x43c0, 0x4458,
6205 0x4c00, 0x4c18, 0x4c40, 0x4c54,
6206 0x4fc0, 0x5010, 0x53c0, 0x5444,
6207 0x5c00, 0x5c18, 0x5c80, 0x5c90,
6208 0x5fc0, 0x6000, 0x6400, 0x6428,
6209 0x6800, 0x6848, 0x684c, 0x6860,
6210 0x6888, 0x6910, 0x8000 };
6211
6212 regs->version = 0;
6213
6214 memset(p, 0, BNX2_REGDUMP_LEN);
6215
6216 if (!netif_running(bp->dev))
6217 return;
6218
6219 i = 0;
6220 offset = reg_boundaries[0];
6221 p += offset;
6222 while (offset < BNX2_REGDUMP_LEN) {
6223 *p++ = REG_RD(bp, offset);
6224 offset += 4;
6225 if (offset == reg_boundaries[i + 1]) {
6226 offset = reg_boundaries[i + 2];
6227 p = (u32 *) (orig_p + offset);
6228 i += 2;
6229 }
6230 }
6231}
6232
b6016b76
MC		 6233static void
6234bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6235{
972ec0d4 6236 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6237
f86e82fb 6238 if (bp->flags & BNX2_FLAG_NO_WOL) {
b6016b76
MC		 6239 wol->supported = 0;
6240 wol->wolopts = 0;
6241 }
6242 else {
6243 wol->supported = WAKE_MAGIC;
6244 if (bp->wol)
6245 wol->wolopts = WAKE_MAGIC;
6246 else
6247 wol->wolopts = 0;
6248 }
6249 memset(&wol->sopass, 0, sizeof(wol->sopass));
6250}
6251
6252static int
6253bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6254{
972ec0d4 6255 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6256
6257 if (wol->wolopts & ~WAKE_MAGIC)
6258 return -EINVAL;
6259
6260 if (wol->wolopts & WAKE_MAGIC) {
f86e82fb 6261 if (bp->flags & BNX2_FLAG_NO_WOL)
b6016b76
MC		 6262 return -EINVAL;
6263
6264 bp->wol = 1;
6265 }
6266 else {
6267 bp->wol = 0;
6268 }
6269 return 0;
6270}
6271
6272static int
6273bnx2_nway_reset(struct net_device *dev)
6274{
972ec0d4 6275 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6276 u32 bmcr;
6277
6278 if (!(bp->autoneg & AUTONEG_SPEED)) {
6279 return -EINVAL;
6280 }
6281
c770a65c 6282 spin_lock_bh(&bp->phy_lock);
b6016b76 6283
583c28e5 6284 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
7b6b8347
MC		 6285 int rc;
6286
6287 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6288 spin_unlock_bh(&bp->phy_lock);
6289 return rc;
6290 }
6291
b6016b76 6292 /* Force a link down visible on the other side */
583c28e5 6293 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
ca58c3af 6294 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
c770a65c 6295 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6296
6297 msleep(20);
6298
c770a65c 6299 spin_lock_bh(&bp->phy_lock);
f8dd064e
MC		 6300
6301 bp->current_interval = SERDES_AN_TIMEOUT;
6302 bp->serdes_an_pending = 1;
6303 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 6304 }
6305
ca58c3af 6306 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76 6307 bmcr &= ~BMCR_LOOPBACK;
ca58c3af 6308 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
b6016b76 6309
c770a65c 6310 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6311
6312 return 0;
6313}
6314
6315static int
6316bnx2_get_eeprom_len(struct net_device *dev)
6317{
972ec0d4 6318 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6319
1122db71 6320 if (bp->flash_info == NULL)
b6016b76
MC		 6321 return 0;
6322
1122db71 6323 return (int) bp->flash_size;
b6016b76
MC		 6324}
6325
6326static int
6327bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6328 u8 *eebuf)
6329{
972ec0d4 6330 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6331 int rc;
6332
1064e944 6333 /* parameters already validated in ethtool_get_eeprom */
b6016b76
MC		 6334
6335 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
6336
6337 return rc;
6338}
6339
6340static int
6341bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6342 u8 *eebuf)
6343{
972ec0d4 6344 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6345 int rc;
6346
1064e944 6347 /* parameters already validated in ethtool_set_eeprom */
b6016b76
MC		 6348
6349 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
6350
6351 return rc;
6352}
6353
6354static int
6355bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6356{
972ec0d4 6357 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6358
6359 memset(coal, 0, sizeof(struct ethtool_coalesce));
6360
6361 coal->rx_coalesce_usecs = bp->rx_ticks;
6362 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
6363 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
6364 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
6365
6366 coal->tx_coalesce_usecs = bp->tx_ticks;
6367 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
6368 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
6369 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
6370
6371 coal->stats_block_coalesce_usecs = bp->stats_ticks;
6372
6373 return 0;
6374}
6375
6376static int
6377bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6378{
972ec0d4 6379 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6380
6381 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
6382 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
6383
6aa20a22 6384 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
b6016b76
MC		 6385 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
6386
6387 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
6388 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
6389
6390 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
6391 if (bp->rx_quick_cons_trip_int > 0xff)
6392 bp->rx_quick_cons_trip_int = 0xff;
6393
6394 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
6395 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
6396
6397 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
6398 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
6399
6400 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
6401 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
6402
6403 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
6404 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
6405 0xff;
6406
6407 bp->stats_ticks = coal->stats_block_coalesce_usecs;
02537b06
MC		 6408 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
6409 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
6410 bp->stats_ticks = USEC_PER_SEC;
6411 }
7ea6920e
MC		 6412 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
6413 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6414 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
b6016b76
MC		 6415
6416 if (netif_running(bp->dev)) {
6417 bnx2_netif_stop(bp);
6418 bnx2_init_nic(bp);
6419 bnx2_netif_start(bp);
6420 }
6421
6422 return 0;
6423}
6424
6425static void
6426bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6427{
972ec0d4 6428 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6429
13daffa2 6430 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
b6016b76 6431 ering->rx_mini_max_pending = 0;
47bf4246 6432 ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
b6016b76
MC		 6433
6434 ering->rx_pending = bp->rx_ring_size;
6435 ering->rx_mini_pending = 0;
47bf4246 6436 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
b6016b76
MC		 6437
6438 ering->tx_max_pending = MAX_TX_DESC_CNT;
6439 ering->tx_pending = bp->tx_ring_size;
6440}
6441
6442static int
5d5d0015 6443bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
b6016b76 6444{
13daffa2
MC		 6445 if (netif_running(bp->dev)) {
6446 bnx2_netif_stop(bp);
6447 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6448 bnx2_free_skbs(bp);
6449 bnx2_free_mem(bp);
6450 }
6451
5d5d0015
MC		 6452 bnx2_set_rx_ring_size(bp, rx);
6453 bp->tx_ring_size = tx;
b6016b76
MC		 6454
6455 if (netif_running(bp->dev)) {
13daffa2
MC		 6456 int rc;
6457
6458 rc = bnx2_alloc_mem(bp);
6459 if (rc)
6460 return rc;
b6016b76
MC		 6461 bnx2_init_nic(bp);
6462 bnx2_netif_start(bp);
6463 }
b6016b76
MC		 6464 return 0;
6465}
6466
5d5d0015
MC		 6467static int
6468bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6469{
6470 struct bnx2 *bp = netdev_priv(dev);
6471 int rc;
6472
6473 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
6474 (ering->tx_pending > MAX_TX_DESC_CNT) ||
6475 (ering->tx_pending <= MAX_SKB_FRAGS)) {
6476
6477 return -EINVAL;
6478 }
6479 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
6480 return rc;
6481}
6482
b6016b76
MC		 6483static void
6484bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6485{
972ec0d4 6486 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6487
6488 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
6489 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
6490 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
6491}
6492
6493static int
6494bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6495{
972ec0d4 6496 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6497
6498 bp->req_flow_ctrl = 0;
6499 if (epause->rx_pause)
6500 bp->req_flow_ctrl |= FLOW_CTRL_RX;
6501 if (epause->tx_pause)
6502 bp->req_flow_ctrl |= FLOW_CTRL_TX;
6503
6504 if (epause->autoneg) {
6505 bp->autoneg |= AUTONEG_FLOW_CTRL;
6506 }
6507 else {
6508 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
6509 }
6510
c770a65c 6511 spin_lock_bh(&bp->phy_lock);
b6016b76 6512
0d8a6571 6513 bnx2_setup_phy(bp, bp->phy_port);
b6016b76 6514
c770a65c 6515 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6516
6517 return 0;
6518}
6519
6520static u32
6521bnx2_get_rx_csum(struct net_device *dev)
6522{
972ec0d4 6523 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6524
6525 return bp->rx_csum;
6526}
6527
6528static int
6529bnx2_set_rx_csum(struct net_device *dev, u32 data)
6530{
972ec0d4 6531 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6532
6533 bp->rx_csum = data;
6534 return 0;
6535}
6536
b11d6213
MC		 6537static int
6538bnx2_set_tso(struct net_device *dev, u32 data)
6539{
4666f87a
MC		 6540 struct bnx2 *bp = netdev_priv(dev);
6541
6542 if (data) {
b11d6213 6543 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
4666f87a
MC		 6544 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6545 dev->features |= NETIF_F_TSO6;
6546 } else
6547 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
6548 NETIF_F_TSO_ECN);
b11d6213
MC		 6549 return 0;
6550}
6551
cea94db9 6552#define BNX2_NUM_STATS 46
b6016b76 6553
14ab9b86 6554static struct {
b6016b76
MC		 6555 char string[ETH_GSTRING_LEN];
6556} bnx2_stats_str_arr[BNX2_NUM_STATS] = {
6557 { "rx_bytes" },
6558 { "rx_error_bytes" },
6559 { "tx_bytes" },
6560 { "tx_error_bytes" },
6561 { "rx_ucast_packets" },
6562 { "rx_mcast_packets" },
6563 { "rx_bcast_packets" },
6564 { "tx_ucast_packets" },
6565 { "tx_mcast_packets" },
6566 { "tx_bcast_packets" },
6567 { "tx_mac_errors" },
6568 { "tx_carrier_errors" },
6569 { "rx_crc_errors" },
6570 { "rx_align_errors" },
6571 { "tx_single_collisions" },
6572 { "tx_multi_collisions" },
6573 { "tx_deferred" },
6574 { "tx_excess_collisions" },
6575 { "tx_late_collisions" },
6576 { "tx_total_collisions" },
6577 { "rx_fragments" },
6578 { "rx_jabbers" },
6579 { "rx_undersize_packets" },
6580 { "rx_oversize_packets" },
6581 { "rx_64_byte_packets" },
6582 { "rx_65_to_127_byte_packets" },
6583 { "rx_128_to_255_byte_packets" },
6584 { "rx_256_to_511_byte_packets" },
6585 { "rx_512_to_1023_byte_packets" },
6586 { "rx_1024_to_1522_byte_packets" },
6587 { "rx_1523_to_9022_byte_packets" },
6588 { "tx_64_byte_packets" },
6589 { "tx_65_to_127_byte_packets" },
6590 { "tx_128_to_255_byte_packets" },
6591 { "tx_256_to_511_byte_packets" },
6592 { "tx_512_to_1023_byte_packets" },
6593 { "tx_1024_to_1522_byte_packets" },
6594 { "tx_1523_to_9022_byte_packets" },
6595 { "rx_xon_frames" },
6596 { "rx_xoff_frames" },
6597 { "tx_xon_frames" },
6598 { "tx_xoff_frames" },
6599 { "rx_mac_ctrl_frames" },
6600 { "rx_filtered_packets" },
6601 { "rx_discards" },
cea94db9 6602 { "rx_fw_discards" },
b6016b76
MC		 6603};
6604
6605#define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
6606
f71e1309 6607static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 6608 STATS_OFFSET32(stat_IfHCInOctets_hi),
6609 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
6610 STATS_OFFSET32(stat_IfHCOutOctets_hi),
6611 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
6612 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
6613 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
6614 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
6615 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
6616 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
6617 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
6618 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
6aa20a22
JG		 6619 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
6620 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
6621 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
6622 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
6623 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
6624 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
6625 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
6626 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
6627 STATS_OFFSET32(stat_EtherStatsCollisions),
6628 STATS_OFFSET32(stat_EtherStatsFragments),
6629 STATS_OFFSET32(stat_EtherStatsJabbers),
6630 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
6631 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
6632 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
6633 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
6634 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
6635 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
6636 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
6637 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
6638 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
6639 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
6640 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
6641 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
6642 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
6643 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
6644 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
6645 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
6646 STATS_OFFSET32(stat_XonPauseFramesReceived),
6647 STATS_OFFSET32(stat_XoffPauseFramesReceived),
6648 STATS_OFFSET32(stat_OutXonSent),
6649 STATS_OFFSET32(stat_OutXoffSent),
6650 STATS_OFFSET32(stat_MacControlFramesReceived),
6651 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
6652 STATS_OFFSET32(stat_IfInMBUFDiscards),
cea94db9 6653 STATS_OFFSET32(stat_FwRxDrop),
b6016b76
MC		 6654};
6655
6656/* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
6657 * skipped because of errata.
6aa20a22 6658 */
14ab9b86 6659static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 6660 8,0,8,8,8,8,8,8,8,8,
6661 4,0,4,4,4,4,4,4,4,4,
6662 4,4,4,4,4,4,4,4,4,4,
6663 4,4,4,4,4,4,4,4,4,4,
cea94db9 6664 4,4,4,4,4,4,
b6016b76
MC		 6665};
6666
5b0c76ad
MC		 6667static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
6668 8,0,8,8,8,8,8,8,8,8,
6669 4,4,4,4,4,4,4,4,4,4,
6670 4,4,4,4,4,4,4,4,4,4,
6671 4,4,4,4,4,4,4,4,4,4,
cea94db9 6672 4,4,4,4,4,4,
5b0c76ad
MC		 6673};
6674
b6016b76
MC		 6675#define BNX2_NUM_TESTS 6
6676
14ab9b86 6677static struct {
b6016b76
MC		 6678 char string[ETH_GSTRING_LEN];
6679} bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
6680 { "register_test (offline)" },
6681 { "memory_test (offline)" },
6682 { "loopback_test (offline)" },
6683 { "nvram_test (online)" },
6684 { "interrupt_test (online)" },
6685 { "link_test (online)" },
6686};
6687
6688static int
b9f2c044 6689bnx2_get_sset_count(struct net_device *dev, int sset)
b6016b76 6690{
b9f2c044
JG		 6691 switch (sset) {
6692 case ETH_SS_TEST:
6693 return BNX2_NUM_TESTS;
6694 case ETH_SS_STATS:
6695 return BNX2_NUM_STATS;
6696 default:
6697 return -EOPNOTSUPP;
6698 }
b6016b76
MC		 6699}
6700
6701static void
6702bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
6703{
972ec0d4 6704 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6705
6706 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
6707 if (etest->flags & ETH_TEST_FL_OFFLINE) {
80be4434
MC		 6708 int i;
6709
b6016b76
MC		 6710 bnx2_netif_stop(bp);
6711 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
6712 bnx2_free_skbs(bp);
6713
6714 if (bnx2_test_registers(bp) != 0) {
6715 buf[0] = 1;
6716 etest->flags |= ETH_TEST_FL_FAILED;
6717 }
6718 if (bnx2_test_memory(bp) != 0) {
6719 buf[1] = 1;
6720 etest->flags |= ETH_TEST_FL_FAILED;
6721 }
bc5a0690 6722 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
b6016b76 6723 etest->flags |= ETH_TEST_FL_FAILED;
b6016b76
MC		 6724
6725 if (!netif_running(bp->dev)) {
6726 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6727 }
6728 else {
6729 bnx2_init_nic(bp);
6730 bnx2_netif_start(bp);
6731 }
6732
6733 /* wait for link up */
80be4434
MC		 6734 for (i = 0; i < 7; i++) {
6735 if (bp->link_up)
6736 break;
6737 msleep_interruptible(1000);
6738 }
b6016b76
MC		 6739 }
6740
6741 if (bnx2_test_nvram(bp) != 0) {
6742 buf[3] = 1;
6743 etest->flags |= ETH_TEST_FL_FAILED;
6744 }
6745 if (bnx2_test_intr(bp) != 0) {
6746 buf[4] = 1;
6747 etest->flags |= ETH_TEST_FL_FAILED;
6748 }
6749
6750 if (bnx2_test_link(bp) != 0) {
6751 buf[5] = 1;
6752 etest->flags |= ETH_TEST_FL_FAILED;
6753
6754 }
6755}
6756
6757static void
6758bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
6759{
6760 switch (stringset) {
6761 case ETH_SS_STATS:
6762 memcpy(buf, bnx2_stats_str_arr,
6763 sizeof(bnx2_stats_str_arr));
6764 break;
6765 case ETH_SS_TEST:
6766 memcpy(buf, bnx2_tests_str_arr,
6767 sizeof(bnx2_tests_str_arr));
6768 break;
6769 }
6770}
6771
b6016b76
MC		 6772static void
6773bnx2_get_ethtool_stats(struct net_device *dev,
6774 struct ethtool_stats *stats, u64 *buf)
6775{
972ec0d4 6776 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6777 int i;
6778 u32 *hw_stats = (u32 *) bp->stats_blk;
14ab9b86 6779 u8 *stats_len_arr = NULL;
b6016b76
MC		 6780
6781 if (hw_stats == NULL) {
6782 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
6783 return;
6784 }
6785
5b0c76ad
MC		 6786 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
6787 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
6788 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
6789 (CHIP_ID(bp) == CHIP_ID_5708_A0))
b6016b76 6790 stats_len_arr = bnx2_5706_stats_len_arr;
5b0c76ad
MC		 6791 else
6792 stats_len_arr = bnx2_5708_stats_len_arr;
b6016b76
MC		 6793
6794 for (i = 0; i < BNX2_NUM_STATS; i++) {
6795 if (stats_len_arr[i] == 0) {
6796 /* skip this counter */
6797 buf[i] = 0;
6798 continue;
6799 }
6800 if (stats_len_arr[i] == 4) {
6801 /* 4-byte counter */
6802 buf[i] = (u64)
6803 *(hw_stats + bnx2_stats_offset_arr[i]);
6804 continue;
6805 }
6806 /* 8-byte counter */
6807 buf[i] = (((u64) *(hw_stats +
6808 bnx2_stats_offset_arr[i])) << 32) +
6809 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
6810 }
6811}
6812
6813static int
6814bnx2_phys_id(struct net_device *dev, u32 data)
6815{
972ec0d4 6816 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6817 int i;
6818 u32 save;
6819
6820 if (data == 0)
6821 data = 2;
6822
6823 save = REG_RD(bp, BNX2_MISC_CFG);
6824 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
6825
6826 for (i = 0; i < (data * 2); i++) {
6827 if ((i % 2) == 0) {
6828 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
6829 }
6830 else {
6831 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
6832 BNX2_EMAC_LED_1000MB_OVERRIDE |
6833 BNX2_EMAC_LED_100MB_OVERRIDE |
6834 BNX2_EMAC_LED_10MB_OVERRIDE |
6835 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
6836 BNX2_EMAC_LED_TRAFFIC);
6837 }
6838 msleep_interruptible(500);
6839 if (signal_pending(current))
6840 break;
6841 }
6842 REG_WR(bp, BNX2_EMAC_LED, 0);
6843 REG_WR(bp, BNX2_MISC_CFG, save);
6844 return 0;
6845}
6846
4666f87a
MC		 6847static int
6848bnx2_set_tx_csum(struct net_device *dev, u32 data)
6849{
6850 struct bnx2 *bp = netdev_priv(dev);
6851
6852 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6460d948 6853 return (ethtool_op_set_tx_ipv6_csum(dev, data));
4666f87a
MC		 6854 else
6855 return (ethtool_op_set_tx_csum(dev, data));
6856}
6857
7282d491 6858static const struct ethtool_ops bnx2_ethtool_ops = {
b6016b76
MC		 6859 .get_settings = bnx2_get_settings,
6860 .set_settings = bnx2_set_settings,
6861 .get_drvinfo = bnx2_get_drvinfo,
244ac4f4
MC		 6862 .get_regs_len = bnx2_get_regs_len,
6863 .get_regs = bnx2_get_regs,
b6016b76
MC		 6864 .get_wol = bnx2_get_wol,
6865 .set_wol = bnx2_set_wol,
6866 .nway_reset = bnx2_nway_reset,
6867 .get_link = ethtool_op_get_link,
6868 .get_eeprom_len = bnx2_get_eeprom_len,
6869 .get_eeprom = bnx2_get_eeprom,
6870 .set_eeprom = bnx2_set_eeprom,
6871 .get_coalesce = bnx2_get_coalesce,
6872 .set_coalesce = bnx2_set_coalesce,
6873 .get_ringparam = bnx2_get_ringparam,
6874 .set_ringparam = bnx2_set_ringparam,
6875 .get_pauseparam = bnx2_get_pauseparam,
6876 .set_pauseparam = bnx2_set_pauseparam,
6877 .get_rx_csum = bnx2_get_rx_csum,
6878 .set_rx_csum = bnx2_set_rx_csum,
4666f87a 6879 .set_tx_csum = bnx2_set_tx_csum,
b6016b76 6880 .set_sg = ethtool_op_set_sg,
b11d6213 6881 .set_tso = bnx2_set_tso,
b6016b76
MC		 6882 .self_test = bnx2_self_test,
6883 .get_strings = bnx2_get_strings,
6884 .phys_id = bnx2_phys_id,
b6016b76 6885 .get_ethtool_stats = bnx2_get_ethtool_stats,
b9f2c044 6886 .get_sset_count = bnx2_get_sset_count,
b6016b76
MC		 6887};
6888
6889/* Called with rtnl_lock */
6890static int
6891bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6892{
14ab9b86 6893 struct mii_ioctl_data *data = if_mii(ifr);
972ec0d4 6894 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6895 int err;
6896
6897 switch(cmd) {
6898 case SIOCGMIIPHY:
6899 data->phy_id = bp->phy_addr;
6900
6901 /* fallthru */
6902 case SIOCGMIIREG: {
6903 u32 mii_regval;
6904
583c28e5 6905 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7b6b8347
MC		 6906 return -EOPNOTSUPP;
6907
dad3e452
MC		 6908 if (!netif_running(dev))
6909 return -EAGAIN;
6910
c770a65c 6911 spin_lock_bh(&bp->phy_lock);
b6016b76 6912 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
c770a65c 6913 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6914
6915 data->val_out = mii_regval;
6916
6917 return err;
6918 }
6919
6920 case SIOCSMIIREG:
6921 if (!capable(CAP_NET_ADMIN))
6922 return -EPERM;
6923
583c28e5 6924 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7b6b8347
MC		 6925 return -EOPNOTSUPP;
6926
dad3e452
MC		 6927 if (!netif_running(dev))
6928 return -EAGAIN;
6929
c770a65c 6930 spin_lock_bh(&bp->phy_lock);
b6016b76 6931 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
c770a65c 6932 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6933
6934 return err;
6935
6936 default:
6937 /* do nothing */
6938 break;
6939 }
6940 return -EOPNOTSUPP;
6941}
6942
6943/* Called with rtnl_lock */
6944static int
6945bnx2_change_mac_addr(struct net_device *dev, void *p)
6946{
6947 struct sockaddr *addr = p;
972ec0d4 6948 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6949
73eef4cd
MC		 6950 if (!is_valid_ether_addr(addr->sa_data))
6951 return -EINVAL;
6952
b6016b76
MC		 6953 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6954 if (netif_running(dev))
6955 bnx2_set_mac_addr(bp);
6956
6957 return 0;
6958}
6959
6960/* Called with rtnl_lock */
6961static int
6962bnx2_change_mtu(struct net_device *dev, int new_mtu)
6963{
972ec0d4 6964 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6965
6966 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
6967 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
6968 return -EINVAL;
6969
6970 dev->mtu = new_mtu;
5d5d0015 6971 return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
b6016b76
MC		 6972}
6973
6974#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
6975static void
6976poll_bnx2(struct net_device *dev)
6977{
972ec0d4 6978 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6979
6980 disable_irq(bp->pdev->irq);
7d12e780 6981 bnx2_interrupt(bp->pdev->irq, dev);
b6016b76
MC		 6982 enable_irq(bp->pdev->irq);
6983}
6984#endif
6985
253c8b75
MC		 6986static void __devinit
6987bnx2_get_5709_media(struct bnx2 *bp)
6988{
6989 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
6990 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
6991 u32 strap;
6992
6993 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
6994 return;
6995 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
583c28e5 6996 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 6997 return;
6998 }
6999
7000 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7001 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7002 else
7003 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7004
7005 if (PCI_FUNC(bp->pdev->devfn) == 0) {
7006 switch (strap) {
7007 case 0x4:
7008 case 0x5:
7009 case 0x6:
583c28e5 7010 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7011 return;
7012 }
7013 } else {
7014 switch (strap) {
7015 case 0x1:
7016 case 0x2:
7017 case 0x4:
583c28e5 7018 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7019 return;
7020 }
7021 }
7022}
7023
883e5151
MC		 7024static void __devinit
7025bnx2_get_pci_speed(struct bnx2 *bp)
7026{
7027 u32 reg;
7028
7029 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7030 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7031 u32 clkreg;
7032
f86e82fb 7033 bp->flags |= BNX2_FLAG_PCIX;
883e5151
MC		 7034
7035 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7036
7037 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7038 switch (clkreg) {
7039 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7040 bp->bus_speed_mhz = 133;
7041 break;
7042
7043 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7044 bp->bus_speed_mhz = 100;
7045 break;
7046
7047 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7048 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7049 bp->bus_speed_mhz = 66;
7050 break;
7051
7052 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7053 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7054 bp->bus_speed_mhz = 50;
7055 break;
7056
7057 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7058 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7059 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7060 bp->bus_speed_mhz = 33;
7061 break;
7062 }
7063 }
7064 else {
7065 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7066 bp->bus_speed_mhz = 66;
7067 else
7068 bp->bus_speed_mhz = 33;
7069 }
7070
7071 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
f86e82fb 7072 bp->flags |= BNX2_FLAG_PCI_32BIT;
883e5151
MC		 7073
7074}
7075
b6016b76
MC		 7076static int __devinit
7077bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7078{
7079 struct bnx2 *bp;
7080 unsigned long mem_len;
58fc2ea4 7081 int rc, i, j;
b6016b76 7082 u32 reg;
40453c83 7083 u64 dma_mask, persist_dma_mask;
b6016b76 7084
b6016b76 7085 SET_NETDEV_DEV(dev, &pdev->dev);
972ec0d4 7086 bp = netdev_priv(dev);
b6016b76
MC		 7087
7088 bp->flags = 0;
7089 bp->phy_flags = 0;
7090
7091 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7092 rc = pci_enable_device(pdev);
7093 if (rc) {
898eb71c 7094 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
b6016b76
MC		 7095 goto err_out;
7096 }
7097
7098 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9b91cf9d 7099 dev_err(&pdev->dev,
2e8a538d 7100 "Cannot find PCI device base address, aborting.\n");
b6016b76
MC		 7101 rc = -ENODEV;
7102 goto err_out_disable;
7103 }
7104
7105 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7106 if (rc) {
9b91cf9d 7107 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
b6016b76
MC		 7108 goto err_out_disable;
7109 }
7110
7111 pci_set_master(pdev);
7112
7113 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7114 if (bp->pm_cap == 0) {
9b91cf9d 7115 dev_err(&pdev->dev,
2e8a538d 7116 "Cannot find power management capability, aborting.\n");
b6016b76
MC		 7117 rc = -EIO;
7118 goto err_out_release;
7119 }
7120
b6016b76
MC		 7121 bp->dev = dev;
7122 bp->pdev = pdev;
7123
7124 spin_lock_init(&bp->phy_lock);
1b8227c4 7125 spin_lock_init(&bp->indirect_lock);
c4028958 7126 INIT_WORK(&bp->reset_task, bnx2_reset_task);
b6016b76
MC		 7127
7128 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
59b47d8a 7129 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + 1);
b6016b76
MC		 7130 dev->mem_end = dev->mem_start + mem_len;
7131 dev->irq = pdev->irq;
7132
7133 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7134
7135 if (!bp->regview) {
9b91cf9d 7136 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
b6016b76
MC		 7137 rc = -ENOMEM;
7138 goto err_out_release;
7139 }
7140
7141 /* Configure byte swap and enable write to the reg_window registers.
7142 * Rely on CPU to do target byte swapping on big endian systems
7143 * The chip's target access swapping will not swap all accesses
7144 */
7145 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
7146 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7147 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7148
829ca9a3 7149 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 7150
7151 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7152
883e5151
MC		 7153 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7154 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7155 dev_err(&pdev->dev,
7156 "Cannot find PCIE capability, aborting.\n");
7157 rc = -EIO;
7158 goto err_out_unmap;
7159 }
f86e82fb 7160 bp->flags |= BNX2_FLAG_PCIE;
2dd201d7 7161 if (CHIP_REV(bp) == CHIP_REV_Ax)
f86e82fb 7162 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
883e5151 7163 } else {
59b47d8a
MC		 7164 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7165 if (bp->pcix_cap == 0) {
7166 dev_err(&pdev->dev,
7167 "Cannot find PCIX capability, aborting.\n");
7168 rc = -EIO;
7169 goto err_out_unmap;
7170 }
7171 }
7172
b4b36042
MC		 7173 if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7174 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
f86e82fb 7175 bp->flags |= BNX2_FLAG_MSIX_CAP;
b4b36042
MC		 7176 }
7177
8e6a72c4
MC		 7178 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7179 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
f86e82fb 7180 bp->flags |= BNX2_FLAG_MSI_CAP;
8e6a72c4
MC		 7181 }
7182
40453c83
MC		 7183 /* 5708 cannot support DMA addresses > 40-bit. */
7184 if (CHIP_NUM(bp) == CHIP_NUM_5708)
7185 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
7186 else
7187 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
7188
7189 /* Configure DMA attributes. */
7190 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
7191 dev->features |= NETIF_F_HIGHDMA;
7192 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
7193 if (rc) {
7194 dev_err(&pdev->dev,
7195 "pci_set_consistent_dma_mask failed, aborting.\n");
7196 goto err_out_unmap;
7197 }
7198 } else if ((rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) != 0) {
7199 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
7200 goto err_out_unmap;
7201 }
7202
f86e82fb 7203 if (!(bp->flags & BNX2_FLAG_PCIE))
883e5151 7204 bnx2_get_pci_speed(bp);
b6016b76
MC		 7205
7206 /* 5706A0 may falsely detect SERR and PERR. */
7207 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7208 reg = REG_RD(bp, PCI_COMMAND);
7209 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
7210 REG_WR(bp, PCI_COMMAND, reg);
7211 }
7212 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
f86e82fb 7213 !(bp->flags & BNX2_FLAG_PCIX)) {
b6016b76 7214
9b91cf9d 7215 dev_err(&pdev->dev,
2e8a538d 7216 "5706 A1 can only be used in a PCIX bus, aborting.\n");
b6016b76
MC		 7217 goto err_out_unmap;
7218 }
7219
7220 bnx2_init_nvram(bp);
7221
2726d6e1 7222 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
e3648b3d
MC		 7223
7224 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
24cb230b
MC		 7225 BNX2_SHM_HDR_SIGNATURE_SIG) {
7226 u32 off = PCI_FUNC(pdev->devfn) << 2;
7227
2726d6e1 7228 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
24cb230b 7229 } else
e3648b3d
MC		 7230 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
7231
b6016b76
MC		 7232 /* Get the permanent MAC address. First we need to make sure the
7233 * firmware is actually running.
7234 */
2726d6e1 7235 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
b6016b76
MC		 7236
7237 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
7238 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
9b91cf9d 7239 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
b6016b76
MC		 7240 rc = -ENODEV;
7241 goto err_out_unmap;
7242 }
7243
2726d6e1 7244 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
58fc2ea4
MC		 7245 for (i = 0, j = 0; i < 3; i++) {
7246 u8 num, k, skip0;
7247
7248 num = (u8) (reg >> (24 - (i * 8)));
7249 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
7250 if (num >= k || !skip0 || k == 1) {
7251 bp->fw_version[j++] = (num / k) + '0';
7252 skip0 = 0;
7253 }
7254 }
7255 if (i != 2)
7256 bp->fw_version[j++] = '.';
7257 }
2726d6e1 7258 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
846f5c62
MC		 7259 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
7260 bp->wol = 1;
7261
7262 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
f86e82fb 7263 bp->flags |= BNX2_FLAG_ASF_ENABLE;
c2d3db8c
MC		 7264
7265 for (i = 0; i < 30; i++) {
2726d6e1 7266 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
c2d3db8c
MC		 7267 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
7268 break;
7269 msleep(10);
7270 }
7271 }
2726d6e1 7272 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
58fc2ea4
MC		 7273 reg &= BNX2_CONDITION_MFW_RUN_MASK;
7274 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
7275 reg != BNX2_CONDITION_MFW_RUN_NONE) {
7276 int i;
2726d6e1 7277 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
58fc2ea4
MC		 7278
7279 bp->fw_version[j++] = ' ';
7280 for (i = 0; i < 3; i++) {
2726d6e1 7281 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
58fc2ea4
MC		 7282 reg = swab32(reg);
7283 memcpy(&bp->fw_version[j], &reg, 4);
7284 j += 4;
7285 }
7286 }
b6016b76 7287
2726d6e1 7288 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
b6016b76
MC		 7289 bp->mac_addr[0] = (u8) (reg >> 8);
7290 bp->mac_addr[1] = (u8) reg;
7291
2726d6e1 7292 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
b6016b76
MC		 7293 bp->mac_addr[2] = (u8) (reg >> 24);
7294 bp->mac_addr[3] = (u8) (reg >> 16);
7295 bp->mac_addr[4] = (u8) (reg >> 8);
7296 bp->mac_addr[5] = (u8) reg;
7297
5d5d0015
MC		 7298 bp->rx_offset = sizeof(struct l2_fhdr) + 2;
7299
b6016b76 7300 bp->tx_ring_size = MAX_TX_DESC_CNT;
932f3772 7301 bnx2_set_rx_ring_size(bp, 255);
b6016b76
MC		 7302
7303 bp->rx_csum = 1;
7304
b6016b76
MC		 7305 bp->tx_quick_cons_trip_int = 20;
7306 bp->tx_quick_cons_trip = 20;
7307 bp->tx_ticks_int = 80;
7308 bp->tx_ticks = 80;
6aa20a22 7309
b6016b76
MC		 7310 bp->rx_quick_cons_trip_int = 6;
7311 bp->rx_quick_cons_trip = 6;
7312 bp->rx_ticks_int = 18;
7313 bp->rx_ticks = 18;
7314
7ea6920e 7315 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
b6016b76
MC		 7316
7317 bp->timer_interval = HZ;
cd339a0e 7318 bp->current_interval = HZ;
b6016b76 7319
5b0c76ad
MC		 7320 bp->phy_addr = 1;
7321
b6016b76 7322 /* Disable WOL support if we are running on a SERDES chip. */
253c8b75
MC		 7323 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7324 bnx2_get_5709_media(bp);
7325 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
583c28e5 7326 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
bac0dff6 7327
0d8a6571 7328 bp->phy_port = PORT_TP;
583c28e5 7329 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
0d8a6571 7330 bp->phy_port = PORT_FIBRE;
2726d6e1 7331 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
846f5c62 7332 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
f86e82fb 7333 bp->flags |= BNX2_FLAG_NO_WOL;
846f5c62
MC		 7334 bp->wol = 0;
7335 }
38ea3686
MC		 7336 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
7337 /* Don't do parallel detect on this board because of
7338 * some board problems. The link will not go down
7339 * if we do parallel detect.
7340 */
7341 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
7342 pdev->subsystem_device == 0x310c)
7343 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
7344 } else {
5b0c76ad 7345 bp->phy_addr = 2;
5b0c76ad 7346 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
583c28e5 7347 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
5b0c76ad 7348 }
0d8a6571
MC		 7349 bnx2_init_remote_phy(bp);
7350
261dd5ca
MC		 7351 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
7352 CHIP_NUM(bp) == CHIP_NUM_5708)
583c28e5 7353 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
fb0c18bd
MC		 7354 else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
7355 (CHIP_REV(bp) == CHIP_REV_Ax ||
7356 CHIP_REV(bp) == CHIP_REV_Bx))
583c28e5 7357 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
b6016b76 7358
16088272
MC		 7359 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
7360 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
846f5c62 7361 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
f86e82fb 7362 bp->flags |= BNX2_FLAG_NO_WOL;
846f5c62
MC		 7363 bp->wol = 0;
7364 }
dda1e390 7365
b6016b76
MC		 7366 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7367 bp->tx_quick_cons_trip_int =
7368 bp->tx_quick_cons_trip;
7369 bp->tx_ticks_int = bp->tx_ticks;
7370 bp->rx_quick_cons_trip_int =
7371 bp->rx_quick_cons_trip;
7372 bp->rx_ticks_int = bp->rx_ticks;
7373 bp->comp_prod_trip_int = bp->comp_prod_trip;
7374 bp->com_ticks_int = bp->com_ticks;
7375 bp->cmd_ticks_int = bp->cmd_ticks;
7376 }
7377
f9317a40
MC		 7378 /* Disable MSI on 5706 if AMD 8132 bridge is found.
7379 *
7380 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
7381 * with byte enables disabled on the unused 32-bit word. This is legal
7382 * but causes problems on the AMD 8132 which will eventually stop
7383 * responding after a while.
7384 *
7385 * AMD believes this incompatibility is unique to the 5706, and
88187dfa 7386 * prefers to locally disable MSI rather than globally disabling it.
f9317a40
MC		 7387 */
7388 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
7389 struct pci_dev *amd_8132 = NULL;
7390
7391 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
7392 PCI_DEVICE_ID_AMD_8132_BRIDGE,
7393 amd_8132))) {
f9317a40 7394
44c10138
AK		 7395 if (amd_8132->revision >= 0x10 &&
7396 amd_8132->revision <= 0x13) {
f9317a40
MC		 7397 disable_msi = 1;
7398 pci_dev_put(amd_8132);
7399 break;
7400 }
7401 }
7402 }
7403
deaf391b 7404 bnx2_set_default_link(bp);
b6016b76
MC		 7405 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
7406
cd339a0e
MC		 7407 init_timer(&bp->timer);
7408 bp->timer.expires = RUN_AT(bp->timer_interval);
7409 bp->timer.data = (unsigned long) bp;
7410 bp->timer.function = bnx2_timer;
7411
b6016b76
MC		 7412 return 0;
7413
7414err_out_unmap:
7415 if (bp->regview) {
7416 iounmap(bp->regview);
73eef4cd 7417 bp->regview = NULL;
b6016b76
MC		 7418 }
7419
7420err_out_release:
7421 pci_release_regions(pdev);
7422
7423err_out_disable:
7424 pci_disable_device(pdev);
7425 pci_set_drvdata(pdev, NULL);
7426
7427err_out:
7428 return rc;
7429}
7430
883e5151
MC		 7431static char * __devinit
7432bnx2_bus_string(struct bnx2 *bp, char *str)
7433{
7434 char *s = str;
7435
f86e82fb 7436 if (bp->flags & BNX2_FLAG_PCIE) {
883e5151
MC		 7437 s += sprintf(s, "PCI Express");
7438 } else {
7439 s += sprintf(s, "PCI");
f86e82fb 7440 if (bp->flags & BNX2_FLAG_PCIX)
883e5151 7441 s += sprintf(s, "-X");
f86e82fb 7442 if (bp->flags & BNX2_FLAG_PCI_32BIT)
883e5151
MC		 7443 s += sprintf(s, " 32-bit");
7444 else
7445 s += sprintf(s, " 64-bit");
7446 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
7447 }
7448 return str;
7449}
7450
2ba582b7 7451static void __devinit
35efa7c1
MC		 7452bnx2_init_napi(struct bnx2 *bp)
7453{
b4b36042
MC		 7454 int i;
7455 struct bnx2_napi *bnapi;
35efa7c1 7456
b4b36042
MC		 7457 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
7458 bnapi = &bp->bnx2_napi[i];
7459 bnapi->bp = bp;
7460 }
7461 netif_napi_add(bp->dev, &bp->bnx2_napi[0].napi, bnx2_poll, 64);
57851d84
MC		 7462 netif_napi_add(bp->dev, &bp->bnx2_napi[BNX2_TX_VEC].napi, bnx2_tx_poll,
7463 64);
35efa7c1
MC		 7464}
7465
b6016b76
MC		 7466static int __devinit
7467bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7468{
7469 static int version_printed = 0;
7470 struct net_device *dev = NULL;
7471 struct bnx2 *bp;
0795af57 7472 int rc;
883e5151 7473 char str[40];
0795af57 7474 DECLARE_MAC_BUF(mac);
b6016b76
MC		 7475
7476 if (version_printed++ == 0)
7477 printk(KERN_INFO "%s", version);
7478
7479 /* dev zeroed in init_etherdev */
7480 dev = alloc_etherdev(sizeof(*bp));
7481
7482 if (!dev)
7483 return -ENOMEM;
7484
7485 rc = bnx2_init_board(pdev, dev);
7486 if (rc < 0) {
7487 free_netdev(dev);
7488 return rc;
7489 }
7490
7491 dev->open = bnx2_open;
7492 dev->hard_start_xmit = bnx2_start_xmit;
7493 dev->stop = bnx2_close;
7494 dev->get_stats = bnx2_get_stats;
7495 dev->set_multicast_list = bnx2_set_rx_mode;
7496 dev->do_ioctl = bnx2_ioctl;
7497 dev->set_mac_address = bnx2_change_mac_addr;
7498 dev->change_mtu = bnx2_change_mtu;
7499 dev->tx_timeout = bnx2_tx_timeout;
7500 dev->watchdog_timeo = TX_TIMEOUT;
7501#ifdef BCM_VLAN
7502 dev->vlan_rx_register = bnx2_vlan_rx_register;
b6016b76 7503#endif
b6016b76 7504 dev->ethtool_ops = &bnx2_ethtool_ops;
b6016b76 7505
972ec0d4 7506 bp = netdev_priv(dev);
35efa7c1 7507 bnx2_init_napi(bp);
b6016b76
MC		 7508
7509#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7510 dev->poll_controller = poll_bnx2;
7511#endif
7512
1b2f922f
MC		 7513 pci_set_drvdata(pdev, dev);
7514
7515 memcpy(dev->dev_addr, bp->mac_addr, 6);
7516 memcpy(dev->perm_addr, bp->mac_addr, 6);
7517 bp->name = board_info[ent->driver_data].name;
7518
d212f87b 7519 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
4666f87a 7520 if (CHIP_NUM(bp) == CHIP_NUM_5709)
d212f87b
SH		 7521 dev->features |= NETIF_F_IPV6_CSUM;
7522
1b2f922f
MC		 7523#ifdef BCM_VLAN
7524 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7525#endif
7526 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
4666f87a
MC		 7527 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7528 dev->features |= NETIF_F_TSO6;
1b2f922f 7529
b6016b76 7530 if ((rc = register_netdev(dev))) {
9b91cf9d 7531 dev_err(&pdev->dev, "Cannot register net device\n");
b6016b76
MC		 7532 if (bp->regview)
7533 iounmap(bp->regview);
7534 pci_release_regions(pdev);
7535 pci_disable_device(pdev);
7536 pci_set_drvdata(pdev, NULL);
7537 free_netdev(dev);
7538 return rc;
7539 }
7540
883e5151 7541 printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
0795af57 7542 "IRQ %d, node addr %s\n",
b6016b76
MC		 7543 dev->name,
7544 bp->name,
7545 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
7546 ((CHIP_ID(bp) & 0x0ff0) >> 4),
883e5151 7547 bnx2_bus_string(bp, str),
b6016b76 7548 dev->base_addr,
0795af57 7549 bp->pdev->irq, print_mac(mac, dev->dev_addr));
b6016b76 7550
b6016b76
MC		 7551 return 0;
7552}
7553
7554static void __devexit
7555bnx2_remove_one(struct pci_dev *pdev)
7556{
7557 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 7558 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7559
afdc08b9
MC		 7560 flush_scheduled_work();
7561
b6016b76
MC		 7562 unregister_netdev(dev);
7563
7564 if (bp->regview)
7565 iounmap(bp->regview);
7566
7567 free_netdev(dev);
7568 pci_release_regions(pdev);
7569 pci_disable_device(pdev);
7570 pci_set_drvdata(pdev, NULL);
7571}
7572
7573static int
829ca9a3 7574bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
b6016b76
MC		 7575{
7576 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 7577 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7578 u32 reset_code;
7579
6caebb02
MC		 7580 /* PCI register 4 needs to be saved whether netif_running() or not.
7581 * MSI address and data need to be saved if using MSI and
7582 * netif_running().
7583 */
7584 pci_save_state(pdev);
b6016b76
MC		 7585 if (!netif_running(dev))
7586 return 0;
7587
1d60290f 7588 flush_scheduled_work();
b6016b76
MC		 7589 bnx2_netif_stop(bp);
7590 netif_device_detach(dev);
7591 del_timer_sync(&bp->timer);
f86e82fb 7592 if (bp->flags & BNX2_FLAG_NO_WOL)
6c4f095e 7593 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
dda1e390 7594 else if (bp->wol)
b6016b76
MC		 7595 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
7596 else
7597 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
7598 bnx2_reset_chip(bp, reset_code);
7599 bnx2_free_skbs(bp);
829ca9a3 7600 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
b6016b76
MC		 7601 return 0;
7602}
7603
7604static int
7605bnx2_resume(struct pci_dev *pdev)
7606{
7607 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 7608 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7609
6caebb02 7610 pci_restore_state(pdev);
b6016b76
MC		 7611 if (!netif_running(dev))
7612 return 0;
7613
829ca9a3 7614 bnx2_set_power_state(bp, PCI_D0);
b6016b76
MC		 7615 netif_device_attach(dev);
7616 bnx2_init_nic(bp);
7617 bnx2_netif_start(bp);
7618 return 0;
7619}
7620
7621static struct pci_driver bnx2_pci_driver = {
14ab9b86
PH		 7622 .name = DRV_MODULE_NAME,
7623 .id_table = bnx2_pci_tbl,
7624 .probe = bnx2_init_one,
7625 .remove = __devexit_p(bnx2_remove_one),
7626 .suspend = bnx2_suspend,
7627 .resume = bnx2_resume,
b6016b76
MC		 7628};
7629
7630static int __init bnx2_init(void)
7631{
29917620 7632 return pci_register_driver(&bnx2_pci_driver);
b6016b76
MC		 7633}
7634
7635static void __exit bnx2_cleanup(void)
7636{
7637 pci_unregister_driver(&bnx2_pci_driver);
7638}
7639
7640module_init(bnx2_init);
7641module_exit(bnx2_cleanup);
7642
7643
7644
kernel source for telekom puls (alcatel/mediatek)