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IRQ: Maintain regs pointer globally rather than passing to IRQ handlers
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / bmac.c
CommitLineData
1da177e4
LT		 1/*
2 * Network device driver for the BMAC ethernet controller on
3 * Apple Powermacs. Assumes it's under a DBDMA controller.
4 *
5 * Copyright (C) 1998 Randy Gobbel.
6 *
7 * May 1999, Al Viro: proper release of /proc/net/bmac entry, switched to
8 * dynamic procfs inode.
9 */
1da177e4
LT		 10#include <linux/module.h>
11#include <linux/kernel.h>
12#include <linux/netdevice.h>
13#include <linux/etherdevice.h>
14#include <linux/delay.h>
15#include <linux/string.h>
16#include <linux/timer.h>
17#include <linux/proc_fs.h>
18#include <linux/init.h>
19#include <linux/spinlock.h>
20#include <linux/crc32.h>
21#include <asm/prom.h>
22#include <asm/dbdma.h>
23#include <asm/io.h>
24#include <asm/page.h>
25#include <asm/pgtable.h>
26#include <asm/machdep.h>
27#include <asm/pmac_feature.h>
28#include <asm/macio.h>
29#include <asm/irq.h>
30
31#include "bmac.h"
32
33#define trunc_page(x) ((void *)(((unsigned long)(x)) & ~((unsigned long)(PAGE_SIZE - 1))))
34#define round_page(x) trunc_page(((unsigned long)(x)) + ((unsigned long)(PAGE_SIZE - 1)))
35
36/*
37 * CRC polynomial - used in working out multicast filter bits.
38 */
39#define ENET_CRCPOLY 0x04c11db7
40
41/* switch to use multicast code lifted from sunhme driver */
42#define SUNHME_MULTICAST
43
44#define N_RX_RING 64
45#define N_TX_RING 32
46#define MAX_TX_ACTIVE 1
47#define ETHERCRC 4
48#define ETHERMINPACKET 64
49#define ETHERMTU 1500
50#define RX_BUFLEN (ETHERMTU + 14 + ETHERCRC + 2)
51#define TX_TIMEOUT HZ /* 1 second */
52
53/* Bits in transmit DMA status */
54#define TX_DMA_ERR 0x80
55
56#define XXDEBUG(args)
57
58struct bmac_data {
59 /* volatile struct bmac *bmac; */
60 struct sk_buff_head *queue;
61 volatile struct dbdma_regs __iomem *tx_dma;
62 int tx_dma_intr;
63 volatile struct dbdma_regs __iomem *rx_dma;
64 int rx_dma_intr;
65 volatile struct dbdma_cmd *tx_cmds; /* xmit dma command list */
66 volatile struct dbdma_cmd *rx_cmds; /* recv dma command list */
67 struct macio_dev *mdev;
68 int is_bmac_plus;
69 struct sk_buff *rx_bufs[N_RX_RING];
70 int rx_fill;
71 int rx_empty;
72 struct sk_buff *tx_bufs[N_TX_RING];
73 int tx_fill;
74 int tx_empty;
75 unsigned char tx_fullup;
76 struct net_device_stats stats;
77 struct timer_list tx_timeout;
78 int timeout_active;
79 int sleeping;
80 int opened;
81 unsigned short hash_use_count[64];
82 unsigned short hash_table_mask[4];
83 spinlock_t lock;
84};
85
86#if 0 /* Move that to ethtool */
87
88typedef struct bmac_reg_entry {
89 char *name;
90 unsigned short reg_offset;
91} bmac_reg_entry_t;
92
93#define N_REG_ENTRIES 31
94
95static bmac_reg_entry_t reg_entries[N_REG_ENTRIES] = {
96 {"MEMADD", MEMADD},
97 {"MEMDATAHI", MEMDATAHI},
98 {"MEMDATALO", MEMDATALO},
99 {"TXPNTR", TXPNTR},
100 {"RXPNTR", RXPNTR},
101 {"IPG1", IPG1},
102 {"IPG2", IPG2},
103 {"ALIMIT", ALIMIT},
104 {"SLOT", SLOT},
105 {"PALEN", PALEN},
106 {"PAPAT", PAPAT},
107 {"TXSFD", TXSFD},
108 {"JAM", JAM},
109 {"TXCFG", TXCFG},
110 {"TXMAX", TXMAX},
111 {"TXMIN", TXMIN},
112 {"PAREG", PAREG},
113 {"DCNT", DCNT},
114 {"NCCNT", NCCNT},
115 {"NTCNT", NTCNT},
116 {"EXCNT", EXCNT},
117 {"LTCNT", LTCNT},
118 {"TXSM", TXSM},
119 {"RXCFG", RXCFG},
120 {"RXMAX", RXMAX},
121 {"RXMIN", RXMIN},
122 {"FRCNT", FRCNT},
123 {"AECNT", AECNT},
124 {"FECNT", FECNT},
125 {"RXSM", RXSM},
126 {"RXCV", RXCV}
127};
128
129#endif
130
131static unsigned char *bmac_emergency_rxbuf;
132
133/*
134 * Number of bytes of private data per BMAC: allow enough for
135 * the rx and tx dma commands plus a branch dma command each,
136 * and another 16 bytes to allow us to align the dma command
137 * buffers on a 16 byte boundary.
138 */
139#define PRIV_BYTES (sizeof(struct bmac_data) \
140 + (N_RX_RING + N_TX_RING + 4) * sizeof(struct dbdma_cmd) \
141 + sizeof(struct sk_buff_head))
142
143static unsigned char bitrev(unsigned char b);
144static int bmac_open(struct net_device *dev);
145static int bmac_close(struct net_device *dev);
146static int bmac_transmit_packet(struct sk_buff *skb, struct net_device *dev);
147static struct net_device_stats *bmac_stats(struct net_device *dev);
148static void bmac_set_multicast(struct net_device *dev);
149static void bmac_reset_and_enable(struct net_device *dev);
150static void bmac_start_chip(struct net_device *dev);
151static void bmac_init_chip(struct net_device *dev);
152static void bmac_init_registers(struct net_device *dev);
153static void bmac_enable_and_reset_chip(struct net_device *dev);
154static int bmac_set_address(struct net_device *dev, void *addr);
7d12e780
DH		 155static irqreturn_t bmac_misc_intr(int irq, void *dev_id);
156static irqreturn_t bmac_txdma_intr(int irq, void *dev_id);
157static irqreturn_t bmac_rxdma_intr(int irq, void *dev_id);
1da177e4
LT		 158static void bmac_set_timeout(struct net_device *dev);
159static void bmac_tx_timeout(unsigned long data);
160static int bmac_output(struct sk_buff *skb, struct net_device *dev);
161static void bmac_start(struct net_device *dev);
162
163#define DBDMA_SET(x) ( ((x) | (x) << 16) )
164#define DBDMA_CLEAR(x) ( (x) << 16)
165
166static inline void
167dbdma_st32(volatile __u32 __iomem *a, unsigned long x)
168{
169 __asm__ volatile( "stwbrx %0,0,%1" : : "r" (x), "r" (a) : "memory");
170 return;
171}
172
173static inline unsigned long
174dbdma_ld32(volatile __u32 __iomem *a)
175{
176 __u32 swap;
177 __asm__ volatile ("lwbrx %0,0,%1" : "=r" (swap) : "r" (a));
178 return swap;
179}
180
181static void
182dbdma_continue(volatile struct dbdma_regs __iomem *dmap)
183{
184 dbdma_st32(&dmap->control,
185 DBDMA_SET(RUN|WAKE) | DBDMA_CLEAR(PAUSE|DEAD));
186 eieio();
187}
188
189static void
190dbdma_reset(volatile struct dbdma_regs __iomem *dmap)
191{
192 dbdma_st32(&dmap->control,
193 DBDMA_CLEAR(ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN));
194 eieio();
195 while (dbdma_ld32(&dmap->status) & RUN)
196 eieio();
197}
198
199static void
200dbdma_setcmd(volatile struct dbdma_cmd *cp,
201 unsigned short cmd, unsigned count, unsigned long addr,
202 unsigned long cmd_dep)
203{
204 out_le16(&cp->command, cmd);
205 out_le16(&cp->req_count, count);
206 out_le32(&cp->phy_addr, addr);
207 out_le32(&cp->cmd_dep, cmd_dep);
208 out_le16(&cp->xfer_status, 0);
209 out_le16(&cp->res_count, 0);
210}
211
212static inline
213void bmwrite(struct net_device *dev, unsigned long reg_offset, unsigned data )
214{
215 out_le16((void __iomem *)dev->base_addr + reg_offset, data);
216}
217
218
219static inline
66df3bbf 220unsigned short bmread(struct net_device *dev, unsigned long reg_offset )
1da177e4
LT		 221{
222 return in_le16((void __iomem *)dev->base_addr + reg_offset);
223}
224
225static void
226bmac_enable_and_reset_chip(struct net_device *dev)
227{
228 struct bmac_data *bp = netdev_priv(dev);
229 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
230 volatile struct dbdma_regs __iomem *td = bp->tx_dma;
231
232 if (rd)
233 dbdma_reset(rd);
234 if (td)
235 dbdma_reset(td);
236
237 pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 1);
238}
239
240#define MIFDELAY udelay(10)
241
242static unsigned int
243bmac_mif_readbits(struct net_device *dev, int nb)
244{
245 unsigned int val = 0;
246
247 while (--nb >= 0) {
248 bmwrite(dev, MIFCSR, 0);
249 MIFDELAY;
250 if (bmread(dev, MIFCSR) & 8)
251 val |= 1 << nb;
252 bmwrite(dev, MIFCSR, 1);
253 MIFDELAY;
254 }
255 bmwrite(dev, MIFCSR, 0);
256 MIFDELAY;
257 bmwrite(dev, MIFCSR, 1);
258 MIFDELAY;
259 return val;
260}
261
262static void
263bmac_mif_writebits(struct net_device *dev, unsigned int val, int nb)
264{
265 int b;
266
267 while (--nb >= 0) {
268 b = (val & (1 << nb))? 6: 4;
269 bmwrite(dev, MIFCSR, b);
270 MIFDELAY;
271 bmwrite(dev, MIFCSR, b|1);
272 MIFDELAY;
273 }
274}
275
276static unsigned int
277bmac_mif_read(struct net_device *dev, unsigned int addr)
278{
279 unsigned int val;
280
281 bmwrite(dev, MIFCSR, 4);
282 MIFDELAY;
283 bmac_mif_writebits(dev, ~0U, 32);
284 bmac_mif_writebits(dev, 6, 4);
285 bmac_mif_writebits(dev, addr, 10);
286 bmwrite(dev, MIFCSR, 2);
287 MIFDELAY;
288 bmwrite(dev, MIFCSR, 1);
289 MIFDELAY;
290 val = bmac_mif_readbits(dev, 17);
291 bmwrite(dev, MIFCSR, 4);
292 MIFDELAY;
293 return val;
294}
295
296static void
297bmac_mif_write(struct net_device *dev, unsigned int addr, unsigned int val)
298{
299 bmwrite(dev, MIFCSR, 4);
300 MIFDELAY;
301 bmac_mif_writebits(dev, ~0U, 32);
302 bmac_mif_writebits(dev, 5, 4);
303 bmac_mif_writebits(dev, addr, 10);
304 bmac_mif_writebits(dev, 2, 2);
305 bmac_mif_writebits(dev, val, 16);
306 bmac_mif_writebits(dev, 3, 2);
307}
308
309static void
310bmac_init_registers(struct net_device *dev)
311{
312 struct bmac_data *bp = netdev_priv(dev);
313 volatile unsigned short regValue;
314 unsigned short *pWord16;
315 int i;
316
317 /* XXDEBUG(("bmac: enter init_registers\n")); */
318
319 bmwrite(dev, RXRST, RxResetValue);
320 bmwrite(dev, TXRST, TxResetBit);
321
322 i = 100;
323 do {
324 --i;
325 udelay(10000);
326 regValue = bmread(dev, TXRST); /* wait for reset to clear..acknowledge */
327 } while ((regValue & TxResetBit) && i > 0);
328
329 if (!bp->is_bmac_plus) {
330 regValue = bmread(dev, XCVRIF);
331 regValue |= ClkBit | SerialMode | COLActiveLow;
332 bmwrite(dev, XCVRIF, regValue);
333 udelay(10000);
334 }
335
6aa20a22 336 bmwrite(dev, RSEED, (unsigned short)0x1968);
1da177e4
LT		 337
338 regValue = bmread(dev, XIFC);
339 regValue |= TxOutputEnable;
340 bmwrite(dev, XIFC, regValue);
341
342 bmread(dev, PAREG);
343
344 /* set collision counters to 0 */
345 bmwrite(dev, NCCNT, 0);
346 bmwrite(dev, NTCNT, 0);
347 bmwrite(dev, EXCNT, 0);
348 bmwrite(dev, LTCNT, 0);
349
350 /* set rx counters to 0 */
351 bmwrite(dev, FRCNT, 0);
352 bmwrite(dev, LECNT, 0);
353 bmwrite(dev, AECNT, 0);
354 bmwrite(dev, FECNT, 0);
355 bmwrite(dev, RXCV, 0);
356
357 /* set tx fifo information */
358 bmwrite(dev, TXTH, 4); /* 4 octets before tx starts */
359
360 bmwrite(dev, TXFIFOCSR, 0); /* first disable txFIFO */
361 bmwrite(dev, TXFIFOCSR, TxFIFOEnable );
362
363 /* set rx fifo information */
364 bmwrite(dev, RXFIFOCSR, 0); /* first disable rxFIFO */
365 bmwrite(dev, RXFIFOCSR, RxFIFOEnable );
366
367 //bmwrite(dev, TXCFG, TxMACEnable); /* TxNeverGiveUp maybe later */
368 bmread(dev, STATUS); /* read it just to clear it */
369
370 /* zero out the chip Hash Filter registers */
371 for (i=0; i<4; i++) bp->hash_table_mask[i] = 0;
372 bmwrite(dev, BHASH3, bp->hash_table_mask[0]); /* bits 15 - 0 */
373 bmwrite(dev, BHASH2, bp->hash_table_mask[1]); /* bits 31 - 16 */
374 bmwrite(dev, BHASH1, bp->hash_table_mask[2]); /* bits 47 - 32 */
375 bmwrite(dev, BHASH0, bp->hash_table_mask[3]); /* bits 63 - 48 */
6aa20a22 376
1da177e4
LT		 377 pWord16 = (unsigned short *)dev->dev_addr;
378 bmwrite(dev, MADD0, *pWord16++);
379 bmwrite(dev, MADD1, *pWord16++);
380 bmwrite(dev, MADD2, *pWord16);
381
382 bmwrite(dev, RXCFG, RxCRCNoStrip | RxHashFilterEnable | RxRejectOwnPackets);
383
384 bmwrite(dev, INTDISABLE, EnableNormal);
385
386 return;
387}
388
389#if 0
390static void
391bmac_disable_interrupts(struct net_device *dev)
392{
393 bmwrite(dev, INTDISABLE, DisableAll);
394}
395
396static void
397bmac_enable_interrupts(struct net_device *dev)
398{
399 bmwrite(dev, INTDISABLE, EnableNormal);
400}
401#endif
402
403
404static void
405bmac_start_chip(struct net_device *dev)
406{
407 struct bmac_data *bp = netdev_priv(dev);
408 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
409 unsigned short oldConfig;
410
411 /* enable rx dma channel */
412 dbdma_continue(rd);
413
6aa20a22 414 oldConfig = bmread(dev, TXCFG);
1da177e4
LT		 415 bmwrite(dev, TXCFG, oldConfig | TxMACEnable );
416
417 /* turn on rx plus any other bits already on (promiscuous possibly) */
6aa20a22 418 oldConfig = bmread(dev, RXCFG);
1da177e4
LT		 419 bmwrite(dev, RXCFG, oldConfig | RxMACEnable );
420 udelay(20000);
421}
422
423static void
424bmac_init_phy(struct net_device *dev)
425{
426 unsigned int addr;
427 struct bmac_data *bp = netdev_priv(dev);
428
429 printk(KERN_DEBUG "phy registers:");
430 for (addr = 0; addr < 32; ++addr) {
431 if ((addr & 7) == 0)
432 printk("\n" KERN_DEBUG);
433 printk(" %.4x", bmac_mif_read(dev, addr));
434 }
435 printk("\n");
436 if (bp->is_bmac_plus) {
437 unsigned int capable, ctrl;
438
439 ctrl = bmac_mif_read(dev, 0);
440 capable = ((bmac_mif_read(dev, 1) & 0xf800) >> 6) | 1;
441 if (bmac_mif_read(dev, 4) != capable
442 || (ctrl & 0x1000) == 0) {
443 bmac_mif_write(dev, 4, capable);
444 bmac_mif_write(dev, 0, 0x1200);
445 } else
446 bmac_mif_write(dev, 0, 0x1000);
447 }
448}
449
450static void bmac_init_chip(struct net_device *dev)
451{
452 bmac_init_phy(dev);
453 bmac_init_registers(dev);
454}
455
456#ifdef CONFIG_PM
05adc3b7 457static int bmac_suspend(struct macio_dev *mdev, pm_message_t state)
1da177e4 458{
6aa20a22 459 struct net_device* dev = macio_get_drvdata(mdev);
1da177e4
LT		 460 struct bmac_data *bp = netdev_priv(dev);
461 unsigned long flags;
462 unsigned short config;
463 int i;
6aa20a22 464
1da177e4
LT		 465 netif_device_detach(dev);
466 /* prolly should wait for dma to finish & turn off the chip */
467 spin_lock_irqsave(&bp->lock, flags);
468 if (bp->timeout_active) {
469 del_timer(&bp->tx_timeout);
470 bp->timeout_active = 0;
471 }
472 disable_irq(dev->irq);
473 disable_irq(bp->tx_dma_intr);
474 disable_irq(bp->rx_dma_intr);
475 bp->sleeping = 1;
476 spin_unlock_irqrestore(&bp->lock, flags);
477 if (bp->opened) {
478 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
479 volatile struct dbdma_regs __iomem *td = bp->tx_dma;
6aa20a22 480
1da177e4
LT		 481 config = bmread(dev, RXCFG);
482 bmwrite(dev, RXCFG, (config & ~RxMACEnable));
483 config = bmread(dev, TXCFG);
484 bmwrite(dev, TXCFG, (config & ~TxMACEnable));
485 bmwrite(dev, INTDISABLE, DisableAll); /* disable all intrs */
486 /* disable rx and tx dma */
487 st_le32(&rd->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */
488 st_le32(&td->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */
489 /* free some skb's */
490 for (i=0; i<N_RX_RING; i++) {
491 if (bp->rx_bufs[i] != NULL) {
492 dev_kfree_skb(bp->rx_bufs[i]);
493 bp->rx_bufs[i] = NULL;
494 }
495 }
496 for (i = 0; i<N_TX_RING; i++) {
497 if (bp->tx_bufs[i] != NULL) {
498 dev_kfree_skb(bp->tx_bufs[i]);
499 bp->tx_bufs[i] = NULL;
500 }
501 }
502 }
503 pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0);
504 return 0;
505}
506
507static int bmac_resume(struct macio_dev *mdev)
508{
6aa20a22 509 struct net_device* dev = macio_get_drvdata(mdev);
1da177e4
LT		 510 struct bmac_data *bp = netdev_priv(dev);
511
512 /* see if this is enough */
513 if (bp->opened)
514 bmac_reset_and_enable(dev);
515
516 enable_irq(dev->irq);
517 enable_irq(bp->tx_dma_intr);
518 enable_irq(bp->rx_dma_intr);
519 netif_device_attach(dev);
520
521 return 0;
522}
523#endif /* CONFIG_PM */
524
525static int bmac_set_address(struct net_device *dev, void *addr)
526{
527 struct bmac_data *bp = netdev_priv(dev);
528 unsigned char *p = addr;
529 unsigned short *pWord16;
530 unsigned long flags;
531 int i;
532
533 XXDEBUG(("bmac: enter set_address\n"));
534 spin_lock_irqsave(&bp->lock, flags);
535
536 for (i = 0; i < 6; ++i) {
537 dev->dev_addr[i] = p[i];
538 }
539 /* load up the hardware address */
540 pWord16 = (unsigned short *)dev->dev_addr;
541 bmwrite(dev, MADD0, *pWord16++);
542 bmwrite(dev, MADD1, *pWord16++);
543 bmwrite(dev, MADD2, *pWord16);
544
545 spin_unlock_irqrestore(&bp->lock, flags);
546 XXDEBUG(("bmac: exit set_address\n"));
547 return 0;
548}
549
550static inline void bmac_set_timeout(struct net_device *dev)
551{
552 struct bmac_data *bp = netdev_priv(dev);
553 unsigned long flags;
554
555 spin_lock_irqsave(&bp->lock, flags);
556 if (bp->timeout_active)
557 del_timer(&bp->tx_timeout);
558 bp->tx_timeout.expires = jiffies + TX_TIMEOUT;
559 bp->tx_timeout.function = bmac_tx_timeout;
560 bp->tx_timeout.data = (unsigned long) dev;
561 add_timer(&bp->tx_timeout);
562 bp->timeout_active = 1;
563 spin_unlock_irqrestore(&bp->lock, flags);
564}
565
566static void
567bmac_construct_xmt(struct sk_buff *skb, volatile struct dbdma_cmd *cp)
568{
569 void *vaddr;
570 unsigned long baddr;
571 unsigned long len;
572
573 len = skb->len;
574 vaddr = skb->data;
575 baddr = virt_to_bus(vaddr);
576
577 dbdma_setcmd(cp, (OUTPUT_LAST | INTR_ALWAYS | WAIT_IFCLR), len, baddr, 0);
578}
579
580static void
581bmac_construct_rxbuff(struct sk_buff *skb, volatile struct dbdma_cmd *cp)
582{
583 unsigned char *addr = skb? skb->data: bmac_emergency_rxbuf;
584
585 dbdma_setcmd(cp, (INPUT_LAST | INTR_ALWAYS), RX_BUFLEN,
586 virt_to_bus(addr), 0);
587}
588
589/* Bit-reverse one byte of an ethernet hardware address. */
590static unsigned char
591bitrev(unsigned char b)
592{
593 int d = 0, i;
594
595 for (i = 0; i < 8; ++i, b >>= 1)
596 d = (d << 1) | (b & 1);
597 return d;
598}
599
600
601static void
602bmac_init_tx_ring(struct bmac_data *bp)
603{
604 volatile struct dbdma_regs __iomem *td = bp->tx_dma;
605
606 memset((char *)bp->tx_cmds, 0, (N_TX_RING+1) * sizeof(struct dbdma_cmd));
607
608 bp->tx_empty = 0;
609 bp->tx_fill = 0;
610 bp->tx_fullup = 0;
611
612 /* put a branch at the end of the tx command list */
613 dbdma_setcmd(&bp->tx_cmds[N_TX_RING],
614 (DBDMA_NOP | BR_ALWAYS), 0, 0, virt_to_bus(bp->tx_cmds));
615
616 /* reset tx dma */
617 dbdma_reset(td);
618 out_le32(&td->wait_sel, 0x00200020);
619 out_le32(&td->cmdptr, virt_to_bus(bp->tx_cmds));
620}
621
622static int
623bmac_init_rx_ring(struct bmac_data *bp)
624{
625 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
626 int i;
627 struct sk_buff *skb;
628
629 /* initialize list of sk_buffs for receiving and set up recv dma */
630 memset((char *)bp->rx_cmds, 0,
631 (N_RX_RING + 1) * sizeof(struct dbdma_cmd));
632 for (i = 0; i < N_RX_RING; i++) {
633 if ((skb = bp->rx_bufs[i]) == NULL) {
634 bp->rx_bufs[i] = skb = dev_alloc_skb(RX_BUFLEN+2);
635 if (skb != NULL)
636 skb_reserve(skb, 2);
637 }
638 bmac_construct_rxbuff(skb, &bp->rx_cmds[i]);
639 }
640
641 bp->rx_empty = 0;
642 bp->rx_fill = i;
643
644 /* Put a branch back to the beginning of the receive command list */
645 dbdma_setcmd(&bp->rx_cmds[N_RX_RING],
646 (DBDMA_NOP | BR_ALWAYS), 0, 0, virt_to_bus(bp->rx_cmds));
647
648 /* start rx dma */
649 dbdma_reset(rd);
650 out_le32(&rd->cmdptr, virt_to_bus(bp->rx_cmds));
651
652 return 1;
653}
654
655
656static int bmac_transmit_packet(struct sk_buff *skb, struct net_device *dev)
657{
658 struct bmac_data *bp = netdev_priv(dev);
659 volatile struct dbdma_regs __iomem *td = bp->tx_dma;
660 int i;
661
662 /* see if there's a free slot in the tx ring */
663 /* XXDEBUG(("bmac_xmit_start: empty=%d fill=%d\n", */
664 /* bp->tx_empty, bp->tx_fill)); */
665 i = bp->tx_fill + 1;
666 if (i >= N_TX_RING)
667 i = 0;
668 if (i == bp->tx_empty) {
669 netif_stop_queue(dev);
670 bp->tx_fullup = 1;
671 XXDEBUG(("bmac_transmit_packet: tx ring full\n"));
672 return -1; /* can't take it at the moment */
673 }
674
675 dbdma_setcmd(&bp->tx_cmds[i], DBDMA_STOP, 0, 0, 0);
676
677 bmac_construct_xmt(skb, &bp->tx_cmds[bp->tx_fill]);
678
679 bp->tx_bufs[bp->tx_fill] = skb;
680 bp->tx_fill = i;
681
682 bp->stats.tx_bytes += skb->len;
683
684 dbdma_continue(td);
685
686 return 0;
687}
688
689static int rxintcount;
690
7d12e780 691static irqreturn_t bmac_rxdma_intr(int irq, void *dev_id)
1da177e4
LT		 692{
693 struct net_device *dev = (struct net_device *) dev_id;
694 struct bmac_data *bp = netdev_priv(dev);
695 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
696 volatile struct dbdma_cmd *cp;
697 int i, nb, stat;
698 struct sk_buff *skb;
699 unsigned int residual;
700 int last;
701 unsigned long flags;
702
703 spin_lock_irqsave(&bp->lock, flags);
704
705 if (++rxintcount < 10) {
706 XXDEBUG(("bmac_rxdma_intr\n"));
707 }
708
709 last = -1;
710 i = bp->rx_empty;
711
712 while (1) {
713 cp = &bp->rx_cmds[i];
714 stat = ld_le16(&cp->xfer_status);
715 residual = ld_le16(&cp->res_count);
716 if ((stat & ACTIVE) == 0)
717 break;
718 nb = RX_BUFLEN - residual - 2;
719 if (nb < (ETHERMINPACKET - ETHERCRC)) {
720 skb = NULL;
721 bp->stats.rx_length_errors++;
722 bp->stats.rx_errors++;
723 } else {
724 skb = bp->rx_bufs[i];
725 bp->rx_bufs[i] = NULL;
726 }
727 if (skb != NULL) {
728 nb -= ETHERCRC;
729 skb_put(skb, nb);
730 skb->dev = dev;
731 skb->protocol = eth_type_trans(skb, dev);
732 netif_rx(skb);
733 dev->last_rx = jiffies;
734 ++bp->stats.rx_packets;
735 bp->stats.rx_bytes += nb;
736 } else {
737 ++bp->stats.rx_dropped;
738 }
739 dev->last_rx = jiffies;
740 if ((skb = bp->rx_bufs[i]) == NULL) {
741 bp->rx_bufs[i] = skb = dev_alloc_skb(RX_BUFLEN+2);
742 if (skb != NULL)
743 skb_reserve(bp->rx_bufs[i], 2);
744 }
745 bmac_construct_rxbuff(skb, &bp->rx_cmds[i]);
746 st_le16(&cp->res_count, 0);
747 st_le16(&cp->xfer_status, 0);
748 last = i;
749 if (++i >= N_RX_RING) i = 0;
750 }
751
752 if (last != -1) {
753 bp->rx_fill = last;
754 bp->rx_empty = i;
755 }
756
757 dbdma_continue(rd);
758 spin_unlock_irqrestore(&bp->lock, flags);
759
760 if (rxintcount < 10) {
761 XXDEBUG(("bmac_rxdma_intr done\n"));
762 }
763 return IRQ_HANDLED;
764}
765
766static int txintcount;
767
7d12e780 768static irqreturn_t bmac_txdma_intr(int irq, void *dev_id)
1da177e4
LT		 769{
770 struct net_device *dev = (struct net_device *) dev_id;
771 struct bmac_data *bp = netdev_priv(dev);
772 volatile struct dbdma_cmd *cp;
773 int stat;
774 unsigned long flags;
775
776 spin_lock_irqsave(&bp->lock, flags);
777
778 if (txintcount++ < 10) {
779 XXDEBUG(("bmac_txdma_intr\n"));
780 }
781
782 /* del_timer(&bp->tx_timeout); */
783 /* bp->timeout_active = 0; */
784
785 while (1) {
786 cp = &bp->tx_cmds[bp->tx_empty];
787 stat = ld_le16(&cp->xfer_status);
788 if (txintcount < 10) {
789 XXDEBUG(("bmac_txdma_xfer_stat=%#0x\n", stat));
790 }
791 if (!(stat & ACTIVE)) {
792 /*
793 * status field might not have been filled by DBDMA
794 */
795 if (cp == bus_to_virt(in_le32(&bp->tx_dma->cmdptr)))
796 break;
797 }
798
799 if (bp->tx_bufs[bp->tx_empty]) {
800 ++bp->stats.tx_packets;
801 dev_kfree_skb_irq(bp->tx_bufs[bp->tx_empty]);
802 }
803 bp->tx_bufs[bp->tx_empty] = NULL;
804 bp->tx_fullup = 0;
805 netif_wake_queue(dev);
806 if (++bp->tx_empty >= N_TX_RING)
807 bp->tx_empty = 0;
808 if (bp->tx_empty == bp->tx_fill)
809 break;
810 }
811
812 spin_unlock_irqrestore(&bp->lock, flags);
813
814 if (txintcount < 10) {
815 XXDEBUG(("bmac_txdma_intr done->bmac_start\n"));
816 }
817
818 bmac_start(dev);
819 return IRQ_HANDLED;
820}
821
822static struct net_device_stats *bmac_stats(struct net_device *dev)
823{
824 struct bmac_data *p = netdev_priv(dev);
825
826 return &p->stats;
827}
828
829#ifndef SUNHME_MULTICAST
830/* Real fast bit-reversal algorithm, 6-bit values */
831static int reverse6[64] = {
832 0x0,0x20,0x10,0x30,0x8,0x28,0x18,0x38,
833 0x4,0x24,0x14,0x34,0xc,0x2c,0x1c,0x3c,
834 0x2,0x22,0x12,0x32,0xa,0x2a,0x1a,0x3a,
835 0x6,0x26,0x16,0x36,0xe,0x2e,0x1e,0x3e,
836 0x1,0x21,0x11,0x31,0x9,0x29,0x19,0x39,
837 0x5,0x25,0x15,0x35,0xd,0x2d,0x1d,0x3d,
838 0x3,0x23,0x13,0x33,0xb,0x2b,0x1b,0x3b,
839 0x7,0x27,0x17,0x37,0xf,0x2f,0x1f,0x3f
840};
841
842static unsigned int
843crc416(unsigned int curval, unsigned short nxtval)
844{
845 register unsigned int counter, cur = curval, next = nxtval;
846 register int high_crc_set, low_data_set;
847
848 /* Swap bytes */
849 next = ((next & 0x00FF) << 8) | (next >> 8);
850
851 /* Compute bit-by-bit */
852 for (counter = 0; counter < 16; ++counter) {
853 /* is high CRC bit set? */
854 if ((cur & 0x80000000) == 0) high_crc_set = 0;
855 else high_crc_set = 1;
856
857 cur = cur << 1;
6aa20a22 858
1da177e4
LT		 859 if ((next & 0x0001) == 0) low_data_set = 0;
860 else low_data_set = 1;
861
862 next = next >> 1;
6aa20a22 863
1da177e4
LT		 864 /* do the XOR */
865 if (high_crc_set ^ low_data_set) cur = cur ^ ENET_CRCPOLY;
866 }
867 return cur;
868}
869
870static unsigned int
871bmac_crc(unsigned short *address)
6aa20a22 872{
1da177e4
LT		 873 unsigned int newcrc;
874
875 XXDEBUG(("bmac_crc: addr=%#04x, %#04x, %#04x\n", *address, address[1], address[2]));
876 newcrc = crc416(0xffffffff, *address); /* address bits 47 - 32 */
877 newcrc = crc416(newcrc, address[1]); /* address bits 31 - 16 */
878 newcrc = crc416(newcrc, address[2]); /* address bits 15 - 0 */
879
880 return(newcrc);
881}
882
883/*
884 * Add requested mcast addr to BMac's hash table filter.
885 *
886 */
887
888static void
889bmac_addhash(struct bmac_data *bp, unsigned char *addr)
6aa20a22 890{
1da177e4
LT		 891 unsigned int crc;
892 unsigned short mask;
893
894 if (!(*addr)) return;
895 crc = bmac_crc((unsigned short *)addr) & 0x3f; /* Big-endian alert! */
896 crc = reverse6[crc]; /* Hyperfast bit-reversing algorithm */
897 if (bp->hash_use_count[crc]++) return; /* This bit is already set */
898 mask = crc % 16;
899 mask = (unsigned char)1 << mask;
900 bp->hash_use_count[crc/16] |= mask;
901}
902
903static void
904bmac_removehash(struct bmac_data *bp, unsigned char *addr)
6aa20a22 905{
1da177e4
LT		 906 unsigned int crc;
907 unsigned char mask;
908
909 /* Now, delete the address from the filter copy, as indicated */
910 crc = bmac_crc((unsigned short *)addr) & 0x3f; /* Big-endian alert! */
911 crc = reverse6[crc]; /* Hyperfast bit-reversing algorithm */
912 if (bp->hash_use_count[crc] == 0) return; /* That bit wasn't in use! */
913 if (--bp->hash_use_count[crc]) return; /* That bit is still in use */
914 mask = crc % 16;
915 mask = ((unsigned char)1 << mask) ^ 0xffff; /* To turn off bit */
916 bp->hash_table_mask[crc/16] &= mask;
917}
918
919/*
920 * Sync the adapter with the software copy of the multicast mask
921 * (logical address filter).
922 */
923
924static void
925bmac_rx_off(struct net_device *dev)
926{
927 unsigned short rx_cfg;
928
929 rx_cfg = bmread(dev, RXCFG);
930 rx_cfg &= ~RxMACEnable;
931 bmwrite(dev, RXCFG, rx_cfg);
932 do {
933 rx_cfg = bmread(dev, RXCFG);
934 } while (rx_cfg & RxMACEnable);
935}
936
937unsigned short
938bmac_rx_on(struct net_device *dev, int hash_enable, int promisc_enable)
939{
940 unsigned short rx_cfg;
941
942 rx_cfg = bmread(dev, RXCFG);
943 rx_cfg |= RxMACEnable;
944 if (hash_enable) rx_cfg |= RxHashFilterEnable;
945 else rx_cfg &= ~RxHashFilterEnable;
946 if (promisc_enable) rx_cfg |= RxPromiscEnable;
947 else rx_cfg &= ~RxPromiscEnable;
948 bmwrite(dev, RXRST, RxResetValue);
949 bmwrite(dev, RXFIFOCSR, 0); /* first disable rxFIFO */
950 bmwrite(dev, RXFIFOCSR, RxFIFOEnable );
951 bmwrite(dev, RXCFG, rx_cfg );
952 return rx_cfg;
953}
954
955static void
956bmac_update_hash_table_mask(struct net_device *dev, struct bmac_data *bp)
957{
958 bmwrite(dev, BHASH3, bp->hash_table_mask[0]); /* bits 15 - 0 */
959 bmwrite(dev, BHASH2, bp->hash_table_mask[1]); /* bits 31 - 16 */
960 bmwrite(dev, BHASH1, bp->hash_table_mask[2]); /* bits 47 - 32 */
961 bmwrite(dev, BHASH0, bp->hash_table_mask[3]); /* bits 63 - 48 */
962}
963
964#if 0
965static void
966bmac_add_multi(struct net_device *dev,
967 struct bmac_data *bp, unsigned char *addr)
968{
969 /* XXDEBUG(("bmac: enter bmac_add_multi\n")); */
970 bmac_addhash(bp, addr);
971 bmac_rx_off(dev);
972 bmac_update_hash_table_mask(dev, bp);
973 bmac_rx_on(dev, 1, (dev->flags & IFF_PROMISC)? 1 : 0);
974 /* XXDEBUG(("bmac: exit bmac_add_multi\n")); */
975}
976
977static void
978bmac_remove_multi(struct net_device *dev,
979 struct bmac_data *bp, unsigned char *addr)
980{
981 bmac_removehash(bp, addr);
982 bmac_rx_off(dev);
983 bmac_update_hash_table_mask(dev, bp);
984 bmac_rx_on(dev, 1, (dev->flags & IFF_PROMISC)? 1 : 0);
985}
986#endif
987
988/* Set or clear the multicast filter for this adaptor.
989 num_addrs == -1 Promiscuous mode, receive all packets
990 num_addrs == 0 Normal mode, clear multicast list
991 num_addrs > 0 Multicast mode, receive normal and MC packets, and do
992 best-effort filtering.
993 */
994static void bmac_set_multicast(struct net_device *dev)
995{
996 struct dev_mc_list *dmi;
997 struct bmac_data *bp = netdev_priv(dev);
998 int num_addrs = dev->mc_count;
999 unsigned short rx_cfg;
1000 int i;
1001
1002 if (bp->sleeping)
1003 return;
1004
1005 XXDEBUG(("bmac: enter bmac_set_multicast, n_addrs=%d\n", num_addrs));
1006
1007 if((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
1008 for (i=0; i<4; i++) bp->hash_table_mask[i] = 0xffff;
1009 bmac_update_hash_table_mask(dev, bp);
1010 rx_cfg = bmac_rx_on(dev, 1, 0);
1011 XXDEBUG(("bmac: all multi, rx_cfg=%#08x\n"));
1012 } else if ((dev->flags & IFF_PROMISC) || (num_addrs < 0)) {
1013 rx_cfg = bmread(dev, RXCFG);
1014 rx_cfg |= RxPromiscEnable;
1015 bmwrite(dev, RXCFG, rx_cfg);
1016 rx_cfg = bmac_rx_on(dev, 0, 1);
1017 XXDEBUG(("bmac: promisc mode enabled, rx_cfg=%#08x\n", rx_cfg));
1018 } else {
1019 for (i=0; i<4; i++) bp->hash_table_mask[i] = 0;
1020 for (i=0; i<64; i++) bp->hash_use_count[i] = 0;
1021 if (num_addrs == 0) {
1022 rx_cfg = bmac_rx_on(dev, 0, 0);
1023 XXDEBUG(("bmac: multi disabled, rx_cfg=%#08x\n", rx_cfg));
1024 } else {
1025 for (dmi=dev->mc_list; dmi!=NULL; dmi=dmi->next)
1026 bmac_addhash(bp, dmi->dmi_addr);
1027 bmac_update_hash_table_mask(dev, bp);
1028 rx_cfg = bmac_rx_on(dev, 1, 0);
1029 XXDEBUG(("bmac: multi enabled, rx_cfg=%#08x\n", rx_cfg));
1030 }
1031 }
1032 /* XXDEBUG(("bmac: exit bmac_set_multicast\n")); */
1033}
1034#else /* ifdef SUNHME_MULTICAST */
1035
1036/* The version of set_multicast below was lifted from sunhme.c */
1037
1038static void bmac_set_multicast(struct net_device *dev)
1039{
1040 struct dev_mc_list *dmi = dev->mc_list;
1041 char *addrs;
1042 int i;
1043 unsigned short rx_cfg;
1044 u32 crc;
1045
1046 if((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
1047 bmwrite(dev, BHASH0, 0xffff);
1048 bmwrite(dev, BHASH1, 0xffff);
1049 bmwrite(dev, BHASH2, 0xffff);
1050 bmwrite(dev, BHASH3, 0xffff);
1051 } else if(dev->flags & IFF_PROMISC) {
1052 rx_cfg = bmread(dev, RXCFG);
1053 rx_cfg |= RxPromiscEnable;
1054 bmwrite(dev, RXCFG, rx_cfg);
1055 } else {
1056 u16 hash_table[4];
6aa20a22 1057
1da177e4
LT		 1058 rx_cfg = bmread(dev, RXCFG);
1059 rx_cfg &= ~RxPromiscEnable;
1060 bmwrite(dev, RXCFG, rx_cfg);
1061
1062 for(i = 0; i < 4; i++) hash_table[i] = 0;
6aa20a22 1063
1da177e4
LT		 1064 for(i = 0; i < dev->mc_count; i++) {
1065 addrs = dmi->dmi_addr;
1066 dmi = dmi->next;
1067
1068 if(!(*addrs & 1))
1069 continue;
1070
1071 crc = ether_crc_le(6, addrs);
1072 crc >>= 26;
1073 hash_table[crc >> 4] |= 1 << (crc & 0xf);
1074 }
1075 bmwrite(dev, BHASH0, hash_table[0]);
1076 bmwrite(dev, BHASH1, hash_table[1]);
1077 bmwrite(dev, BHASH2, hash_table[2]);
1078 bmwrite(dev, BHASH3, hash_table[3]);
1079 }
1080}
1081#endif /* SUNHME_MULTICAST */
1082
1083static int miscintcount;
1084
7d12e780 1085static irqreturn_t bmac_misc_intr(int irq, void *dev_id)
1da177e4
LT		 1086{
1087 struct net_device *dev = (struct net_device *) dev_id;
1088 struct bmac_data *bp = netdev_priv(dev);
1089 unsigned int status = bmread(dev, STATUS);
1090 if (miscintcount++ < 10) {
1091 XXDEBUG(("bmac_misc_intr\n"));
1092 }
1093 /* XXDEBUG(("bmac_misc_intr, status=%#08x\n", status)); */
7d12e780 1094 /* bmac_txdma_intr_inner(irq, dev_id); */
1da177e4
LT		 1095 /* if (status & FrameReceived) bp->stats.rx_dropped++; */
1096 if (status & RxErrorMask) bp->stats.rx_errors++;
1097 if (status & RxCRCCntExp) bp->stats.rx_crc_errors++;
1098 if (status & RxLenCntExp) bp->stats.rx_length_errors++;
1099 if (status & RxOverFlow) bp->stats.rx_over_errors++;
1100 if (status & RxAlignCntExp) bp->stats.rx_frame_errors++;
1101
1102 /* if (status & FrameSent) bp->stats.tx_dropped++; */
1103 if (status & TxErrorMask) bp->stats.tx_errors++;
1104 if (status & TxUnderrun) bp->stats.tx_fifo_errors++;
1105 if (status & TxNormalCollExp) bp->stats.collisions++;
1106 return IRQ_HANDLED;
1107}
1108
1109/*
1110 * Procedure for reading EEPROM
1111 */
1112#define SROMAddressLength 5
1113#define DataInOn 0x0008
1114#define DataInOff 0x0000
1115#define Clk 0x0002
1116#define ChipSelect 0x0001
1117#define SDIShiftCount 3
1118#define SD0ShiftCount 2
1119#define DelayValue 1000 /* number of microseconds */
1120#define SROMStartOffset 10 /* this is in words */
1121#define SROMReadCount 3 /* number of words to read from SROM */
1122#define SROMAddressBits 6
1123#define EnetAddressOffset 20
1124
1125static unsigned char
1126bmac_clock_out_bit(struct net_device *dev)
1127{
1128 unsigned short data;
1129 unsigned short val;
1130
1131 bmwrite(dev, SROMCSR, ChipSelect | Clk);
1132 udelay(DelayValue);
1133
1134 data = bmread(dev, SROMCSR);
1135 udelay(DelayValue);
1136 val = (data >> SD0ShiftCount) & 1;
1137
1138 bmwrite(dev, SROMCSR, ChipSelect);
1139 udelay(DelayValue);
1140
1141 return val;
1142}
1143
1144static void
1145bmac_clock_in_bit(struct net_device *dev, unsigned int val)
1146{
1147 unsigned short data;
1148
1149 if (val != 0 && val != 1) return;
1150
1151 data = (val << SDIShiftCount);
1152 bmwrite(dev, SROMCSR, data | ChipSelect );
1153 udelay(DelayValue);
1154
1155 bmwrite(dev, SROMCSR, data | ChipSelect | Clk );
1156 udelay(DelayValue);
1157
1158 bmwrite(dev, SROMCSR, data | ChipSelect);
1159 udelay(DelayValue);
1160}
1161
1162static void
1163reset_and_select_srom(struct net_device *dev)
1164{
1165 /* first reset */
1166 bmwrite(dev, SROMCSR, 0);
1167 udelay(DelayValue);
1168
1169 /* send it the read command (110) */
1170 bmac_clock_in_bit(dev, 1);
1171 bmac_clock_in_bit(dev, 1);
1172 bmac_clock_in_bit(dev, 0);
1173}
1174
1175static unsigned short
1176read_srom(struct net_device *dev, unsigned int addr, unsigned int addr_len)
1177{
1178 unsigned short data, val;
1179 int i;
1180
1181 /* send out the address we want to read from */
1182 for (i = 0; i < addr_len; i++) {
1183 val = addr >> (addr_len-i-1);
1184 bmac_clock_in_bit(dev, val & 1);
1185 }
1186
1187 /* Now read in the 16-bit data */
1188 data = 0;
1189 for (i = 0; i < 16; i++) {
1190 val = bmac_clock_out_bit(dev);
1191 data <<= 1;
1192 data |= val;
1193 }
1194 bmwrite(dev, SROMCSR, 0);
1195
1196 return data;
1197}
1198
1199/*
1200 * It looks like Cogent and SMC use different methods for calculating
1201 * checksums. What a pain..
1202 */
1203
1204static int
1205bmac_verify_checksum(struct net_device *dev)
1206{
1207 unsigned short data, storedCS;
1208
1209 reset_and_select_srom(dev);
1210 data = read_srom(dev, 3, SROMAddressBits);
1211 storedCS = ((data >> 8) & 0x0ff) | ((data << 8) & 0xff00);
1212
1213 return 0;
1214}
1215
1216
1217static void
1218bmac_get_station_address(struct net_device *dev, unsigned char *ea)
1219{
1220 int i;
1221 unsigned short data;
1222
6aa20a22 1223 for (i = 0; i < 6; i++)
1da177e4
LT		 1224 {
1225 reset_and_select_srom(dev);
1226 data = read_srom(dev, i + EnetAddressOffset/2, SROMAddressBits);
1227 ea[2*i] = bitrev(data & 0x0ff);
1228 ea[2*i+1] = bitrev((data >> 8) & 0x0ff);
1229 }
1230}
1231
1232static void bmac_reset_and_enable(struct net_device *dev)
1233{
1234 struct bmac_data *bp = netdev_priv(dev);
1235 unsigned long flags;
1236 struct sk_buff *skb;
1237 unsigned char *data;
1238
1239 spin_lock_irqsave(&bp->lock, flags);
1240 bmac_enable_and_reset_chip(dev);
1241 bmac_init_tx_ring(bp);
1242 bmac_init_rx_ring(bp);
1243 bmac_init_chip(dev);
1244 bmac_start_chip(dev);
1245 bmwrite(dev, INTDISABLE, EnableNormal);
1246 bp->sleeping = 0;
6aa20a22 1247
1da177e4
LT		 1248 /*
1249 * It seems that the bmac can't receive until it's transmitted
1250 * a packet. So we give it a dummy packet to transmit.
1251 */
1252 skb = dev_alloc_skb(ETHERMINPACKET);
1253 if (skb != NULL) {
1254 data = skb_put(skb, ETHERMINPACKET);
1255 memset(data, 0, ETHERMINPACKET);
1256 memcpy(data, dev->dev_addr, 6);
1257 memcpy(data+6, dev->dev_addr, 6);
1258 bmac_transmit_packet(skb, dev);
1259 }
1260 spin_unlock_irqrestore(&bp->lock, flags);
1261}
1262
5e655772 1263static int __devinit bmac_probe(struct macio_dev *mdev, const struct of_device_id *match)
1da177e4
LT		 1264{
1265 int j, rev, ret;
1266 struct bmac_data *bp;
1a2509c9
JK		 1267 const unsigned char *prop_addr;
1268 unsigned char addr[6];
1da177e4
LT		 1269 struct net_device *dev;
1270 int is_bmac_plus = ((int)match->data) != 0;
1271
1272 if (macio_resource_count(mdev) != 3 || macio_irq_count(mdev) != 3) {
1273 printk(KERN_ERR "BMAC: can't use, need 3 addrs and 3 intrs\n");
1274 return -ENODEV;
1275 }
1a2509c9
JK		 1276 prop_addr = get_property(macio_get_of_node(mdev), "mac-address", NULL);
1277 if (prop_addr == NULL) {
1278 prop_addr = get_property(macio_get_of_node(mdev),
1279 "local-mac-address", NULL);
1280 if (prop_addr == NULL) {
1da177e4
LT		 1281 printk(KERN_ERR "BMAC: Can't get mac-address\n");
1282 return -ENODEV;
1283 }
1284 }
1a2509c9 1285 memcpy(addr, prop_addr, sizeof(addr));
1da177e4
LT		 1286
1287 dev = alloc_etherdev(PRIV_BYTES);
1288 if (!dev) {
1289 printk(KERN_ERR "BMAC: alloc_etherdev failed, out of memory\n");
1290 return -ENOMEM;
1291 }
6aa20a22 1292
1da177e4
LT		 1293 bp = netdev_priv(dev);
1294 SET_MODULE_OWNER(dev);
1295 SET_NETDEV_DEV(dev, &mdev->ofdev.dev);
1296 macio_set_drvdata(mdev, dev);
1297
1298 bp->mdev = mdev;
1299 spin_lock_init(&bp->lock);
1300
1301 if (macio_request_resources(mdev, "bmac")) {
1302 printk(KERN_ERR "BMAC: can't request IO resource !\n");
1303 goto out_free;
1304 }
1305
1306 dev->base_addr = (unsigned long)
1307 ioremap(macio_resource_start(mdev, 0), macio_resource_len(mdev, 0));
1308 if (dev->base_addr == 0)
1309 goto out_release;
1310
1311 dev->irq = macio_irq(mdev, 0);
1312
1313 bmac_enable_and_reset_chip(dev);
1314 bmwrite(dev, INTDISABLE, DisableAll);
1315
1316 rev = addr[0] == 0 && addr[1] == 0xA0;
1317 for (j = 0; j < 6; ++j)
1318 dev->dev_addr[j] = rev? bitrev(addr[j]): addr[j];
1319
1320 /* Enable chip without interrupts for now */
1321 bmac_enable_and_reset_chip(dev);
1322 bmwrite(dev, INTDISABLE, DisableAll);
1323
1324 dev->open = bmac_open;
1325 dev->stop = bmac_close;
1326 dev->hard_start_xmit = bmac_output;
1327 dev->get_stats = bmac_stats;
1328 dev->set_multicast_list = bmac_set_multicast;
1329 dev->set_mac_address = bmac_set_address;
1330
1331 bmac_get_station_address(dev, addr);
1332 if (bmac_verify_checksum(dev) != 0)
1333 goto err_out_iounmap;
1334
1335 bp->is_bmac_plus = is_bmac_plus;
1336 bp->tx_dma = ioremap(macio_resource_start(mdev, 1), macio_resource_len(mdev, 1));
1337 if (!bp->tx_dma)
1338 goto err_out_iounmap;
1339 bp->tx_dma_intr = macio_irq(mdev, 1);
1340 bp->rx_dma = ioremap(macio_resource_start(mdev, 2), macio_resource_len(mdev, 2));
1341 if (!bp->rx_dma)
1342 goto err_out_iounmap_tx;
1343 bp->rx_dma_intr = macio_irq(mdev, 2);
1344
1345 bp->tx_cmds = (volatile struct dbdma_cmd *) DBDMA_ALIGN(bp + 1);
1346 bp->rx_cmds = bp->tx_cmds + N_TX_RING + 1;
1347
1348 bp->queue = (struct sk_buff_head *)(bp->rx_cmds + N_RX_RING + 1);
1349 skb_queue_head_init(bp->queue);
1350
1351 init_timer(&bp->tx_timeout);
1352
1353 ret = request_irq(dev->irq, bmac_misc_intr, 0, "BMAC-misc", dev);
1354 if (ret) {
1355 printk(KERN_ERR "BMAC: can't get irq %d\n", dev->irq);
1356 goto err_out_iounmap_rx;
1357 }
1358 ret = request_irq(bp->tx_dma_intr, bmac_txdma_intr, 0, "BMAC-txdma", dev);
1359 if (ret) {
1360 printk(KERN_ERR "BMAC: can't get irq %d\n", bp->tx_dma_intr);
1361 goto err_out_irq0;
1362 }
1363 ret = request_irq(bp->rx_dma_intr, bmac_rxdma_intr, 0, "BMAC-rxdma", dev);
1364 if (ret) {
1365 printk(KERN_ERR "BMAC: can't get irq %d\n", bp->rx_dma_intr);
1366 goto err_out_irq1;
1367 }
1368
1369 /* Mask chip interrupts and disable chip, will be
1370 * re-enabled on open()
1371 */
1372 disable_irq(dev->irq);
1373 pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0);
1374
1375 if (register_netdev(dev) != 0) {
1376 printk(KERN_ERR "BMAC: Ethernet registration failed\n");
1377 goto err_out_irq2;
1378 }
1379
1380 printk(KERN_INFO "%s: BMAC%s at", dev->name, (is_bmac_plus? "+": ""));
1381 for (j = 0; j < 6; ++j)
1382 printk("%c%.2x", (j? ':': ' '), dev->dev_addr[j]);
1383 XXDEBUG((", base_addr=%#0lx", dev->base_addr));
1384 printk("\n");
6aa20a22 1385
1da177e4
LT		 1386 return 0;
1387
1388err_out_irq2:
1389 free_irq(bp->rx_dma_intr, dev);
1390err_out_irq1:
1391 free_irq(bp->tx_dma_intr, dev);
1392err_out_irq0:
1393 free_irq(dev->irq, dev);
1394err_out_iounmap_rx:
1395 iounmap(bp->rx_dma);
1396err_out_iounmap_tx:
1397 iounmap(bp->tx_dma);
1398err_out_iounmap:
1399 iounmap((void __iomem *)dev->base_addr);
1400out_release:
1401 macio_release_resources(mdev);
1402out_free:
1403 pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0);
1404 free_netdev(dev);
1405
1406 return -ENODEV;
1407}
1408
1409static int bmac_open(struct net_device *dev)
1410{
1411 struct bmac_data *bp = netdev_priv(dev);
1412 /* XXDEBUG(("bmac: enter open\n")); */
1413 /* reset the chip */
1414 bp->opened = 1;
1415 bmac_reset_and_enable(dev);
1416 enable_irq(dev->irq);
1da177e4
LT		 1417 return 0;
1418}
1419
1420static int bmac_close(struct net_device *dev)
1421{
1422 struct bmac_data *bp = netdev_priv(dev);
1423 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
1424 volatile struct dbdma_regs __iomem *td = bp->tx_dma;
1425 unsigned short config;
1426 int i;
1427
1428 bp->sleeping = 1;
1da177e4
LT		 1429
1430 /* disable rx and tx */
1431 config = bmread(dev, RXCFG);
1432 bmwrite(dev, RXCFG, (config & ~RxMACEnable));
1433
1434 config = bmread(dev, TXCFG);
1435 bmwrite(dev, TXCFG, (config & ~TxMACEnable));
1436
1437 bmwrite(dev, INTDISABLE, DisableAll); /* disable all intrs */
1438
1439 /* disable rx and tx dma */
1440 st_le32(&rd->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */
1441 st_le32(&td->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */
1442
1443 /* free some skb's */
1444 XXDEBUG(("bmac: free rx bufs\n"));
1445 for (i=0; i<N_RX_RING; i++) {
1446 if (bp->rx_bufs[i] != NULL) {
1447 dev_kfree_skb(bp->rx_bufs[i]);
1448 bp->rx_bufs[i] = NULL;
1449 }
1450 }
1451 XXDEBUG(("bmac: free tx bufs\n"));
1452 for (i = 0; i<N_TX_RING; i++) {
1453 if (bp->tx_bufs[i] != NULL) {
1454 dev_kfree_skb(bp->tx_bufs[i]);
1455 bp->tx_bufs[i] = NULL;
1456 }
1457 }
1458 XXDEBUG(("bmac: all bufs freed\n"));
1459
1460 bp->opened = 0;
1461 disable_irq(dev->irq);
1462 pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0);
1463
1464 return 0;
1465}
1466
1467static void
1468bmac_start(struct net_device *dev)
1469{
1470 struct bmac_data *bp = netdev_priv(dev);
1471 int i;
1472 struct sk_buff *skb;
1473 unsigned long flags;
1474
1475 if (bp->sleeping)
1476 return;
6aa20a22 1477
1da177e4
LT		 1478 spin_lock_irqsave(&bp->lock, flags);
1479 while (1) {
1480 i = bp->tx_fill + 1;
1481 if (i >= N_TX_RING)
1482 i = 0;
1483 if (i == bp->tx_empty)
1484 break;
1485 skb = skb_dequeue(bp->queue);
1486 if (skb == NULL)
1487 break;
1488 bmac_transmit_packet(skb, dev);
1489 }
1490 spin_unlock_irqrestore(&bp->lock, flags);
1491}
1492
1493static int
1494bmac_output(struct sk_buff *skb, struct net_device *dev)
1495{
1496 struct bmac_data *bp = netdev_priv(dev);
1497 skb_queue_tail(bp->queue, skb);
1498 bmac_start(dev);
1499 return 0;
1500}
1501
1502static void bmac_tx_timeout(unsigned long data)
1503{
1504 struct net_device *dev = (struct net_device *) data;
1505 struct bmac_data *bp = netdev_priv(dev);
1506 volatile struct dbdma_regs __iomem *td = bp->tx_dma;
1507 volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
1508 volatile struct dbdma_cmd *cp;
1509 unsigned long flags;
1510 unsigned short config, oldConfig;
1511 int i;
1512
1513 XXDEBUG(("bmac: tx_timeout called\n"));
1514 spin_lock_irqsave(&bp->lock, flags);
1515 bp->timeout_active = 0;
1516
1517 /* update various counters */
1518/* bmac_handle_misc_intrs(bp, 0); */
1519
1520 cp = &bp->tx_cmds[bp->tx_empty];
1521/* XXDEBUG((KERN_DEBUG "bmac: tx dmastat=%x %x runt=%d pr=%x fs=%x fc=%x\n", */
1522/* ld_le32(&td->status), ld_le16(&cp->xfer_status), bp->tx_bad_runt, */
1523/* mb->pr, mb->xmtfs, mb->fifofc)); */
1524
1525 /* turn off both tx and rx and reset the chip */
1526 config = bmread(dev, RXCFG);
1527 bmwrite(dev, RXCFG, (config & ~RxMACEnable));
1528 config = bmread(dev, TXCFG);
1529 bmwrite(dev, TXCFG, (config & ~TxMACEnable));
1530 out_le32(&td->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE|ACTIVE|DEAD));
1531 printk(KERN_ERR "bmac: transmit timeout - resetting\n");
1532 bmac_enable_and_reset_chip(dev);
1533
1534 /* restart rx dma */
1535 cp = bus_to_virt(ld_le32(&rd->cmdptr));
1536 out_le32(&rd->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE|ACTIVE|DEAD));
1537 out_le16(&cp->xfer_status, 0);
1538 out_le32(&rd->cmdptr, virt_to_bus(cp));
1539 out_le32(&rd->control, DBDMA_SET(RUN|WAKE));
1540
1541 /* fix up the transmit side */
1542 XXDEBUG((KERN_DEBUG "bmac: tx empty=%d fill=%d fullup=%d\n",
1543 bp->tx_empty, bp->tx_fill, bp->tx_fullup));
1544 i = bp->tx_empty;
1545 ++bp->stats.tx_errors;
1546 if (i != bp->tx_fill) {
1547 dev_kfree_skb(bp->tx_bufs[i]);
1548 bp->tx_bufs[i] = NULL;
1549 if (++i >= N_TX_RING) i = 0;
1550 bp->tx_empty = i;
1551 }
1552 bp->tx_fullup = 0;
1553 netif_wake_queue(dev);
1554 if (i != bp->tx_fill) {
1555 cp = &bp->tx_cmds[i];
1556 out_le16(&cp->xfer_status, 0);
1557 out_le16(&cp->command, OUTPUT_LAST);
1558 out_le32(&td->cmdptr, virt_to_bus(cp));
1559 out_le32(&td->control, DBDMA_SET(RUN));
1560 /* bmac_set_timeout(dev); */
1561 XXDEBUG((KERN_DEBUG "bmac: starting %d\n", i));
1562 }
1563
1564 /* turn it back on */
6aa20a22 1565 oldConfig = bmread(dev, RXCFG);
1da177e4 1566 bmwrite(dev, RXCFG, oldConfig | RxMACEnable );
6aa20a22 1567 oldConfig = bmread(dev, TXCFG);
1da177e4
LT		 1568 bmwrite(dev, TXCFG, oldConfig | TxMACEnable );
1569
1570 spin_unlock_irqrestore(&bp->lock, flags);
1571}
1572
1573#if 0
1574static void dump_dbdma(volatile struct dbdma_cmd *cp,int count)
1575{
1576 int i,*ip;
6aa20a22 1577
1da177e4
LT		 1578 for (i=0;i< count;i++) {
1579 ip = (int*)(cp+i);
6aa20a22 1580
1da177e4
LT		 1581 printk("dbdma req 0x%x addr 0x%x baddr 0x%x xfer/res 0x%x\n",
1582 ld_le32(ip+0),
1583 ld_le32(ip+1),
1584 ld_le32(ip+2),
1585 ld_le32(ip+3));
1586 }
1587
1588}
1589#endif
1590
1591#if 0
1592static int
1593bmac_proc_info(char *buffer, char **start, off_t offset, int length)
1594{
1595 int len = 0;
1596 off_t pos = 0;
1597 off_t begin = 0;
1598 int i;
1599
1600 if (bmac_devs == NULL)
1601 return (-ENOSYS);
1602
1603 len += sprintf(buffer, "BMAC counters & registers\n");
1604
1605 for (i = 0; i<N_REG_ENTRIES; i++) {
1606 len += sprintf(buffer + len, "%s: %#08x\n",
1607 reg_entries[i].name,
1608 bmread(bmac_devs, reg_entries[i].reg_offset));
1609 pos = begin + len;
1610
1611 if (pos < offset) {
1612 len = 0;
1613 begin = pos;
1614 }
1615
1616 if (pos > offset+length) break;
1617 }
1618
1619 *start = buffer + (offset - begin);
1620 len -= (offset - begin);
1621
1622 if (len > length) len = length;
1623
1624 return len;
1625}
1626#endif
1627
1628static int __devexit bmac_remove(struct macio_dev *mdev)
1629{
1630 struct net_device *dev = macio_get_drvdata(mdev);
1631 struct bmac_data *bp = netdev_priv(dev);
1632
1633 unregister_netdev(dev);
1634
1635 free_irq(dev->irq, dev);
6aa20a22 1636 free_irq(bp->tx_dma_intr, dev);
1da177e4
LT		 1637 free_irq(bp->rx_dma_intr, dev);
1638
1639 iounmap((void __iomem *)dev->base_addr);
1640 iounmap(bp->tx_dma);
1641 iounmap(bp->rx_dma);
1642
1643 macio_release_resources(mdev);
1644
1645 free_netdev(dev);
1646
1647 return 0;
1648}
1649
6aa20a22 1650static struct of_device_id bmac_match[] =
1da177e4
LT		 1651{
1652 {
1653 .name = "bmac",
1da177e4
LT		 1654 .data = (void *)0,
1655 },
1656 {
1da177e4
LT		 1657 .type = "network",
1658 .compatible = "bmac+",
1659 .data = (void *)1,
1660 },
1661 {},
1662};
8c9795ba 1663MODULE_DEVICE_TABLE (of, bmac_match);
1da177e4 1664
6aa20a22 1665static struct macio_driver bmac_driver =
1da177e4
LT		 1666{
1667 .name = "bmac",
1668 .match_table = bmac_match,
1669 .probe = bmac_probe,
1670 .remove = bmac_remove,
1671#ifdef CONFIG_PM
1672 .suspend = bmac_suspend,
1673 .resume = bmac_resume,
1674#endif
1675};
1676
1677
1678static int __init bmac_init(void)
1679{
1680 if (bmac_emergency_rxbuf == NULL) {
1681 bmac_emergency_rxbuf = kmalloc(RX_BUFLEN, GFP_KERNEL);
1682 if (bmac_emergency_rxbuf == NULL) {
1683 printk(KERN_ERR "BMAC: can't allocate emergency RX buffer\n");
1684 return -ENOMEM;
1685 }
1686 }
1687
1688 return macio_register_driver(&bmac_driver);
1689}
1690
1691static void __exit bmac_exit(void)
1692{
1693 macio_unregister_driver(&bmac_driver);
1694
b4558ea9
JJ		 1695 kfree(bmac_emergency_rxbuf);
1696 bmac_emergency_rxbuf = NULL;
1da177e4
LT		 1697}
1698
1699MODULE_AUTHOR("Randy Gobbel/Paul Mackerras");
1700MODULE_DESCRIPTION("PowerMac BMAC ethernet driver.");
1701MODULE_LICENSE("GPL");
1702
1703module_init(bmac_init);
1704module_exit(bmac_exit);
kernel source for telekom puls (alcatel/mediatek)