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[PATCH] b44: expose counters through ethtool
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / b44.c
CommitLineData
1da177e4
LT		 1/* b44.c: Broadcom 4400 device driver.
2 *
3 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
4 * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
5 *
6 * Distribute under GPL.
7 */
8
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/moduleparam.h>
12#include <linux/types.h>
13#include <linux/netdevice.h>
14#include <linux/ethtool.h>
15#include <linux/mii.h>
16#include <linux/if_ether.h>
17#include <linux/etherdevice.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <linux/init.h>
21#include <linux/version.h>
89358f90 22#include <linux/dma-mapping.h>
1da177e4
LT		 23
24#include <asm/uaccess.h>
25#include <asm/io.h>
26#include <asm/irq.h>
27
28#include "b44.h"
29
30#define DRV_MODULE_NAME "b44"
31#define PFX DRV_MODULE_NAME ": "
32#define DRV_MODULE_VERSION "0.95"
33#define DRV_MODULE_RELDATE "Aug 3, 2004"
34
35#define B44_DEF_MSG_ENABLE \
36 (NETIF_MSG_DRV | \
37 NETIF_MSG_PROBE | \
38 NETIF_MSG_LINK | \
39 NETIF_MSG_TIMER | \
40 NETIF_MSG_IFDOWN | \
41 NETIF_MSG_IFUP | \
42 NETIF_MSG_RX_ERR | \
43 NETIF_MSG_TX_ERR)
44
45/* length of time before we decide the hardware is borked,
46 * and dev->tx_timeout() should be called to fix the problem
47 */
48#define B44_TX_TIMEOUT (5 * HZ)
49
50/* hardware minimum and maximum for a single frame's data payload */
51#define B44_MIN_MTU 60
52#define B44_MAX_MTU 1500
53
54#define B44_RX_RING_SIZE 512
55#define B44_DEF_RX_RING_PENDING 200
56#define B44_RX_RING_BYTES (sizeof(struct dma_desc) * \
57 B44_RX_RING_SIZE)
58#define B44_TX_RING_SIZE 512
59#define B44_DEF_TX_RING_PENDING (B44_TX_RING_SIZE - 1)
60#define B44_TX_RING_BYTES (sizeof(struct dma_desc) * \
61 B44_TX_RING_SIZE)
62#define B44_DMA_MASK 0x3fffffff
63
64#define TX_RING_GAP(BP) \
65 (B44_TX_RING_SIZE - (BP)->tx_pending)
66#define TX_BUFFS_AVAIL(BP) \
67 (((BP)->tx_cons <= (BP)->tx_prod) ? \
68 (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod : \
69 (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
70#define NEXT_TX(N) (((N) + 1) & (B44_TX_RING_SIZE - 1))
71
72#define RX_PKT_BUF_SZ (1536 + bp->rx_offset + 64)
73#define TX_PKT_BUF_SZ (B44_MAX_MTU + ETH_HLEN + 8)
74
75/* minimum number of free TX descriptors required to wake up TX process */
76#define B44_TX_WAKEUP_THRESH (B44_TX_RING_SIZE / 4)
77
78static char version[] __devinitdata =
79 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
80
81MODULE_AUTHOR("Florian Schirmer, Pekka Pietikainen, David S. Miller");
82MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver");
83MODULE_LICENSE("GPL");
84MODULE_VERSION(DRV_MODULE_VERSION);
85
86static int b44_debug = -1; /* -1 == use B44_DEF_MSG_ENABLE as value */
87module_param(b44_debug, int, 0);
88MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
89
90static struct pci_device_id b44_pci_tbl[] = {
91 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401,
92 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
93 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B0,
94 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
95 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1,
96 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
97 { } /* terminate list with empty entry */
98};
99
100MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
101
102static void b44_halt(struct b44 *);
103static void b44_init_rings(struct b44 *);
104static void b44_init_hw(struct b44 *);
1da177e4 105
9f38c636
JL		 106static int dma_desc_align_mask;
107static int dma_desc_sync_size;
108
3353930d
FR		 109static const char b44_gstrings[][ETH_GSTRING_LEN] = {
110#define _B44(x...) # x,
111B44_STAT_REG_DECLARE
112#undef _B44
113};
114
9f38c636
JL		 115static inline void b44_sync_dma_desc_for_device(struct pci_dev *pdev,
116 dma_addr_t dma_base,
117 unsigned long offset,
118 enum dma_data_direction dir)
119{
120 dma_sync_single_range_for_device(&pdev->dev, dma_base,
121 offset & dma_desc_align_mask,
122 dma_desc_sync_size, dir);
123}
124
125static inline void b44_sync_dma_desc_for_cpu(struct pci_dev *pdev,
126 dma_addr_t dma_base,
127 unsigned long offset,
128 enum dma_data_direction dir)
129{
130 dma_sync_single_range_for_cpu(&pdev->dev, dma_base,
131 offset & dma_desc_align_mask,
132 dma_desc_sync_size, dir);
133}
134
1da177e4
LT		 135static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
136{
137 return readl(bp->regs + reg);
138}
139
140static inline void bw32(const struct b44 *bp,
141 unsigned long reg, unsigned long val)
142{
143 writel(val, bp->regs + reg);
144}
145
146static int b44_wait_bit(struct b44 *bp, unsigned long reg,
147 u32 bit, unsigned long timeout, const int clear)
148{
149 unsigned long i;
150
151 for (i = 0; i < timeout; i++) {
152 u32 val = br32(bp, reg);
153
154 if (clear && !(val & bit))
155 break;
156 if (!clear && (val & bit))
157 break;
158 udelay(10);
159 }
160 if (i == timeout) {
161 printk(KERN_ERR PFX "%s: BUG! Timeout waiting for bit %08x of register "
162 "%lx to %s.\n",
163 bp->dev->name,
164 bit, reg,
165 (clear ? "clear" : "set"));
166 return -ENODEV;
167 }
168 return 0;
169}
170
171/* Sonics SiliconBackplane support routines. ROFL, you should see all the
172 * buzz words used on this company's website :-)
173 *
174 * All of these routines must be invoked with bp->lock held and
175 * interrupts disabled.
176 */
177
178#define SB_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
179#define BCM4400_PCI_CORE_ADDR 0x18002000 /* Address of PCI core on BCM4400 cards */
180
181static u32 ssb_get_core_rev(struct b44 *bp)
182{
183 return (br32(bp, B44_SBIDHIGH) & SBIDHIGH_RC_MASK);
184}
185
186static u32 ssb_pci_setup(struct b44 *bp, u32 cores)
187{
188 u32 bar_orig, pci_rev, val;
189
190 pci_read_config_dword(bp->pdev, SSB_BAR0_WIN, &bar_orig);
191 pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, BCM4400_PCI_CORE_ADDR);
192 pci_rev = ssb_get_core_rev(bp);
193
194 val = br32(bp, B44_SBINTVEC);
195 val |= cores;
196 bw32(bp, B44_SBINTVEC, val);
197
198 val = br32(bp, SSB_PCI_TRANS_2);
199 val |= SSB_PCI_PREF | SSB_PCI_BURST;
200 bw32(bp, SSB_PCI_TRANS_2, val);
201
202 pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, bar_orig);
203
204 return pci_rev;
205}
206
207static void ssb_core_disable(struct b44 *bp)
208{
209 if (br32(bp, B44_SBTMSLOW) & SBTMSLOW_RESET)
210 return;
211
212 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK));
213 b44_wait_bit(bp, B44_SBTMSLOW, SBTMSLOW_REJECT, 100000, 0);
214 b44_wait_bit(bp, B44_SBTMSHIGH, SBTMSHIGH_BUSY, 100000, 1);
215 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK |
216 SBTMSLOW_REJECT | SBTMSLOW_RESET));
217 br32(bp, B44_SBTMSLOW);
218 udelay(1);
219 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_RESET));
220 br32(bp, B44_SBTMSLOW);
221 udelay(1);
222}
223
224static void ssb_core_reset(struct b44 *bp)
225{
226 u32 val;
227
228 ssb_core_disable(bp);
229 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_RESET | SBTMSLOW_CLOCK | SBTMSLOW_FGC));
230 br32(bp, B44_SBTMSLOW);
231 udelay(1);
232
233 /* Clear SERR if set, this is a hw bug workaround. */
234 if (br32(bp, B44_SBTMSHIGH) & SBTMSHIGH_SERR)
235 bw32(bp, B44_SBTMSHIGH, 0);
236
237 val = br32(bp, B44_SBIMSTATE);
238 if (val & (SBIMSTATE_IBE | SBIMSTATE_TO))
239 bw32(bp, B44_SBIMSTATE, val & ~(SBIMSTATE_IBE | SBIMSTATE_TO));
240
241 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC));
242 br32(bp, B44_SBTMSLOW);
243 udelay(1);
244
245 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK));
246 br32(bp, B44_SBTMSLOW);
247 udelay(1);
248}
249
250static int ssb_core_unit(struct b44 *bp)
251{
252#if 0
253 u32 val = br32(bp, B44_SBADMATCH0);
254 u32 base;
255
256 type = val & SBADMATCH0_TYPE_MASK;
257 switch (type) {
258 case 0:
259 base = val & SBADMATCH0_BS0_MASK;
260 break;
261
262 case 1:
263 base = val & SBADMATCH0_BS1_MASK;
264 break;
265
266 case 2:
267 default:
268 base = val & SBADMATCH0_BS2_MASK;
269 break;
270 };
271#endif
272 return 0;
273}
274
275static int ssb_is_core_up(struct b44 *bp)
276{
277 return ((br32(bp, B44_SBTMSLOW) & (SBTMSLOW_RESET | SBTMSLOW_REJECT | SBTMSLOW_CLOCK))
278 == SBTMSLOW_CLOCK);
279}
280
281static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
282{
283 u32 val;
284
285 val = ((u32) data[2]) << 24;
286 val |= ((u32) data[3]) << 16;
287 val |= ((u32) data[4]) << 8;
288 val |= ((u32) data[5]) << 0;
289 bw32(bp, B44_CAM_DATA_LO, val);
290 val = (CAM_DATA_HI_VALID |
291 (((u32) data[0]) << 8) |
292 (((u32) data[1]) << 0));
293 bw32(bp, B44_CAM_DATA_HI, val);
294 bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
295 (index << CAM_CTRL_INDEX_SHIFT)));
296 b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
297}
298
299static inline void __b44_disable_ints(struct b44 *bp)
300{
301 bw32(bp, B44_IMASK, 0);
302}
303
304static void b44_disable_ints(struct b44 *bp)
305{
306 __b44_disable_ints(bp);
307
308 /* Flush posted writes. */
309 br32(bp, B44_IMASK);
310}
311
312static void b44_enable_ints(struct b44 *bp)
313{
314 bw32(bp, B44_IMASK, bp->imask);
315}
316
317static int b44_readphy(struct b44 *bp, int reg, u32 *val)
318{
319 int err;
320
321 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
322 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
323 (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
324 (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
325 (reg << MDIO_DATA_RA_SHIFT) |
326 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
327 err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
328 *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;
329
330 return err;
331}
332
333static int b44_writephy(struct b44 *bp, int reg, u32 val)
334{
335 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
336 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
337 (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
338 (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
339 (reg << MDIO_DATA_RA_SHIFT) |
340 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
341 (val & MDIO_DATA_DATA)));
342 return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
343}
344
345/* miilib interface */
346/* FIXME FIXME: phy_id is ignored, bp->phy_addr use is unconditional
347 * due to code existing before miilib use was added to this driver.
348 * Someone should remove this artificial driver limitation in
349 * b44_{read,write}phy. bp->phy_addr itself is fine (and needed).
350 */
351static int b44_mii_read(struct net_device *dev, int phy_id, int location)
352{
353 u32 val;
354 struct b44 *bp = netdev_priv(dev);
355 int rc = b44_readphy(bp, location, &val);
356 if (rc)
357 return 0xffffffff;
358 return val;
359}
360
361static void b44_mii_write(struct net_device *dev, int phy_id, int location,
362 int val)
363{
364 struct b44 *bp = netdev_priv(dev);
365 b44_writephy(bp, location, val);
366}
367
368static int b44_phy_reset(struct b44 *bp)
369{
370 u32 val;
371 int err;
372
373 err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
374 if (err)
375 return err;
376 udelay(100);
377 err = b44_readphy(bp, MII_BMCR, &val);
378 if (!err) {
379 if (val & BMCR_RESET) {
380 printk(KERN_ERR PFX "%s: PHY Reset would not complete.\n",
381 bp->dev->name);
382 err = -ENODEV;
383 }
384 }
385
386 return 0;
387}
388
389static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
390{
391 u32 val;
392
393 bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE);
394 bp->flags |= pause_flags;
395
396 val = br32(bp, B44_RXCONFIG);
397 if (pause_flags & B44_FLAG_RX_PAUSE)
398 val |= RXCONFIG_FLOW;
399 else
400 val &= ~RXCONFIG_FLOW;
401 bw32(bp, B44_RXCONFIG, val);
402
403 val = br32(bp, B44_MAC_FLOW);
404 if (pause_flags & B44_FLAG_TX_PAUSE)
405 val |= (MAC_FLOW_PAUSE_ENAB |
406 (0xc0 & MAC_FLOW_RX_HI_WATER));
407 else
408 val &= ~MAC_FLOW_PAUSE_ENAB;
409 bw32(bp, B44_MAC_FLOW, val);
410}
411
412static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
413{
414 u32 pause_enab = bp->flags & (B44_FLAG_TX_PAUSE |
415 B44_FLAG_RX_PAUSE);
416
417 if (local & ADVERTISE_PAUSE_CAP) {
418 if (local & ADVERTISE_PAUSE_ASYM) {
419 if (remote & LPA_PAUSE_CAP)
420 pause_enab |= (B44_FLAG_TX_PAUSE |
421 B44_FLAG_RX_PAUSE);
422 else if (remote & LPA_PAUSE_ASYM)
423 pause_enab |= B44_FLAG_RX_PAUSE;
424 } else {
425 if (remote & LPA_PAUSE_CAP)
426 pause_enab |= (B44_FLAG_TX_PAUSE |
427 B44_FLAG_RX_PAUSE);
428 }
429 } else if (local & ADVERTISE_PAUSE_ASYM) {
430 if ((remote & LPA_PAUSE_CAP) &&
431 (remote & LPA_PAUSE_ASYM))
432 pause_enab |= B44_FLAG_TX_PAUSE;
433 }
434
435 __b44_set_flow_ctrl(bp, pause_enab);
436}
437
438static int b44_setup_phy(struct b44 *bp)
439{
440 u32 val;
441 int err;
442
443 if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
444 goto out;
445 if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
446 val & MII_ALEDCTRL_ALLMSK)) != 0)
447 goto out;
448 if ((err = b44_readphy(bp, B44_MII_TLEDCTRL, &val)) != 0)
449 goto out;
450 if ((err = b44_writephy(bp, B44_MII_TLEDCTRL,
451 val | MII_TLEDCTRL_ENABLE)) != 0)
452 goto out;
453
454 if (!(bp->flags & B44_FLAG_FORCE_LINK)) {
455 u32 adv = ADVERTISE_CSMA;
456
457 if (bp->flags & B44_FLAG_ADV_10HALF)
458 adv |= ADVERTISE_10HALF;
459 if (bp->flags & B44_FLAG_ADV_10FULL)
460 adv |= ADVERTISE_10FULL;
461 if (bp->flags & B44_FLAG_ADV_100HALF)
462 adv |= ADVERTISE_100HALF;
463 if (bp->flags & B44_FLAG_ADV_100FULL)
464 adv |= ADVERTISE_100FULL;
465
466 if (bp->flags & B44_FLAG_PAUSE_AUTO)
467 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
468
469 if ((err = b44_writephy(bp, MII_ADVERTISE, adv)) != 0)
470 goto out;
471 if ((err = b44_writephy(bp, MII_BMCR, (BMCR_ANENABLE |
472 BMCR_ANRESTART))) != 0)
473 goto out;
474 } else {
475 u32 bmcr;
476
477 if ((err = b44_readphy(bp, MII_BMCR, &bmcr)) != 0)
478 goto out;
479 bmcr &= ~(BMCR_FULLDPLX | BMCR_ANENABLE | BMCR_SPEED100);
480 if (bp->flags & B44_FLAG_100_BASE_T)
481 bmcr |= BMCR_SPEED100;
482 if (bp->flags & B44_FLAG_FULL_DUPLEX)
483 bmcr |= BMCR_FULLDPLX;
484 if ((err = b44_writephy(bp, MII_BMCR, bmcr)) != 0)
485 goto out;
486
487 /* Since we will not be negotiating there is no safe way
488 * to determine if the link partner supports flow control
489 * or not. So just disable it completely in this case.
490 */
491 b44_set_flow_ctrl(bp, 0, 0);
492 }
493
494out:
495 return err;
496}
497
498static void b44_stats_update(struct b44 *bp)
499{
500 unsigned long reg;
501 u32 *val;
502
503 val = &bp->hw_stats.tx_good_octets;
504 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
505 *val++ += br32(bp, reg);
506 }
3353930d
FR		 507
508 /* Pad */
509 reg += 8*4UL;
510
1da177e4
LT		 511 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
512 *val++ += br32(bp, reg);
513 }
514}
515
516static void b44_link_report(struct b44 *bp)
517{
518 if (!netif_carrier_ok(bp->dev)) {
519 printk(KERN_INFO PFX "%s: Link is down.\n", bp->dev->name);
520 } else {
521 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
522 bp->dev->name,
523 (bp->flags & B44_FLAG_100_BASE_T) ? 100 : 10,
524 (bp->flags & B44_FLAG_FULL_DUPLEX) ? "full" : "half");
525
526 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
527 "%s for RX.\n",
528 bp->dev->name,
529 (bp->flags & B44_FLAG_TX_PAUSE) ? "on" : "off",
530 (bp->flags & B44_FLAG_RX_PAUSE) ? "on" : "off");
531 }
532}
533
534static void b44_check_phy(struct b44 *bp)
535{
536 u32 bmsr, aux;
537
538 if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
539 !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
540 (bmsr != 0xffff)) {
541 if (aux & MII_AUXCTRL_SPEED)
542 bp->flags |= B44_FLAG_100_BASE_T;
543 else
544 bp->flags &= ~B44_FLAG_100_BASE_T;
545 if (aux & MII_AUXCTRL_DUPLEX)
546 bp->flags |= B44_FLAG_FULL_DUPLEX;
547 else
548 bp->flags &= ~B44_FLAG_FULL_DUPLEX;
549
550 if (!netif_carrier_ok(bp->dev) &&
551 (bmsr & BMSR_LSTATUS)) {
552 u32 val = br32(bp, B44_TX_CTRL);
553 u32 local_adv, remote_adv;
554
555 if (bp->flags & B44_FLAG_FULL_DUPLEX)
556 val |= TX_CTRL_DUPLEX;
557 else
558 val &= ~TX_CTRL_DUPLEX;
559 bw32(bp, B44_TX_CTRL, val);
560
561 if (!(bp->flags & B44_FLAG_FORCE_LINK) &&
562 !b44_readphy(bp, MII_ADVERTISE, &local_adv) &&
563 !b44_readphy(bp, MII_LPA, &remote_adv))
564 b44_set_flow_ctrl(bp, local_adv, remote_adv);
565
566 /* Link now up */
567 netif_carrier_on(bp->dev);
568 b44_link_report(bp);
569 } else if (netif_carrier_ok(bp->dev) && !(bmsr & BMSR_LSTATUS)) {
570 /* Link now down */
571 netif_carrier_off(bp->dev);
572 b44_link_report(bp);
573 }
574
575 if (bmsr & BMSR_RFAULT)
576 printk(KERN_WARNING PFX "%s: Remote fault detected in PHY\n",
577 bp->dev->name);
578 if (bmsr & BMSR_JCD)
579 printk(KERN_WARNING PFX "%s: Jabber detected in PHY\n",
580 bp->dev->name);
581 }
582}
583
584static void b44_timer(unsigned long __opaque)
585{
586 struct b44 *bp = (struct b44 *) __opaque;
587
588 spin_lock_irq(&bp->lock);
589
590 b44_check_phy(bp);
591
592 b44_stats_update(bp);
593
594 spin_unlock_irq(&bp->lock);
595
596 bp->timer.expires = jiffies + HZ;
597 add_timer(&bp->timer);
598}
599
600static void b44_tx(struct b44 *bp)
601{
602 u32 cur, cons;
603
604 cur = br32(bp, B44_DMATX_STAT) & DMATX_STAT_CDMASK;
605 cur /= sizeof(struct dma_desc);
606
607 /* XXX needs updating when NETIF_F_SG is supported */
608 for (cons = bp->tx_cons; cons != cur; cons = NEXT_TX(cons)) {
609 struct ring_info *rp = &bp->tx_buffers[cons];
610 struct sk_buff *skb = rp->skb;
611
612 if (unlikely(skb == NULL))
613 BUG();
614
615 pci_unmap_single(bp->pdev,
616 pci_unmap_addr(rp, mapping),
617 skb->len,
618 PCI_DMA_TODEVICE);
619 rp->skb = NULL;
620 dev_kfree_skb_irq(skb);
621 }
622
623 bp->tx_cons = cons;
624 if (netif_queue_stopped(bp->dev) &&
625 TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH)
626 netif_wake_queue(bp->dev);
627
628 bw32(bp, B44_GPTIMER, 0);
629}
630
631/* Works like this. This chip writes a 'struct rx_header" 30 bytes
632 * before the DMA address you give it. So we allocate 30 more bytes
633 * for the RX buffer, DMA map all of it, skb_reserve the 30 bytes, then
634 * point the chip at 30 bytes past where the rx_header will go.
635 */
636static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
637{
638 struct dma_desc *dp;
639 struct ring_info *src_map, *map;
640 struct rx_header *rh;
641 struct sk_buff *skb;
642 dma_addr_t mapping;
643 int dest_idx;
644 u32 ctrl;
645
646 src_map = NULL;
647 if (src_idx >= 0)
648 src_map = &bp->rx_buffers[src_idx];
649 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
650 map = &bp->rx_buffers[dest_idx];
651 skb = dev_alloc_skb(RX_PKT_BUF_SZ);
652 if (skb == NULL)
653 return -ENOMEM;
654
655 mapping = pci_map_single(bp->pdev, skb->data,
656 RX_PKT_BUF_SZ,
657 PCI_DMA_FROMDEVICE);
658
659 /* Hardware bug work-around, the chip is unable to do PCI DMA
660 to/from anything above 1GB :-( */
874a6214 661 if (mapping + RX_PKT_BUF_SZ > B44_DMA_MASK) {
1da177e4
LT		 662 /* Sigh... */
663 pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
664 dev_kfree_skb_any(skb);
665 skb = __dev_alloc_skb(RX_PKT_BUF_SZ,GFP_DMA);
666 if (skb == NULL)
667 return -ENOMEM;
668 mapping = pci_map_single(bp->pdev, skb->data,
669 RX_PKT_BUF_SZ,
670 PCI_DMA_FROMDEVICE);
874a6214 671 if (mapping + RX_PKT_BUF_SZ > B44_DMA_MASK) {
1da177e4
LT		 672 pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
673 dev_kfree_skb_any(skb);
674 return -ENOMEM;
675 }
676 }
677
678 skb->dev = bp->dev;
679 skb_reserve(skb, bp->rx_offset);
680
681 rh = (struct rx_header *)
682 (skb->data - bp->rx_offset);
683 rh->len = 0;
684 rh->flags = 0;
685
686 map->skb = skb;
687 pci_unmap_addr_set(map, mapping, mapping);
688
689 if (src_map != NULL)
690 src_map->skb = NULL;
691
692 ctrl = (DESC_CTRL_LEN & (RX_PKT_BUF_SZ - bp->rx_offset));
693 if (dest_idx == (B44_RX_RING_SIZE - 1))
694 ctrl |= DESC_CTRL_EOT;
695
696 dp = &bp->rx_ring[dest_idx];
697 dp->ctrl = cpu_to_le32(ctrl);
698 dp->addr = cpu_to_le32((u32) mapping + bp->rx_offset + bp->dma_offset);
699
9f38c636
JL		 700 if (bp->flags & B44_FLAG_RX_RING_HACK)
701 b44_sync_dma_desc_for_device(bp->pdev, bp->rx_ring_dma,
702 dest_idx * sizeof(dp),
703 DMA_BIDIRECTIONAL);
704
1da177e4
LT		 705 return RX_PKT_BUF_SZ;
706}
707
708static void b44_recycle_rx(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
709{
710 struct dma_desc *src_desc, *dest_desc;
711 struct ring_info *src_map, *dest_map;
712 struct rx_header *rh;
713 int dest_idx;
714 u32 ctrl;
715
716 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
717 dest_desc = &bp->rx_ring[dest_idx];
718 dest_map = &bp->rx_buffers[dest_idx];
719 src_desc = &bp->rx_ring[src_idx];
720 src_map = &bp->rx_buffers[src_idx];
721
722 dest_map->skb = src_map->skb;
723 rh = (struct rx_header *) src_map->skb->data;
724 rh->len = 0;
725 rh->flags = 0;
726 pci_unmap_addr_set(dest_map, mapping,
727 pci_unmap_addr(src_map, mapping));
728
9f38c636
JL		 729 if (bp->flags & B44_FLAG_RX_RING_HACK)
730 b44_sync_dma_desc_for_cpu(bp->pdev, bp->rx_ring_dma,
731 src_idx * sizeof(src_desc),
732 DMA_BIDIRECTIONAL);
733
1da177e4
LT		 734 ctrl = src_desc->ctrl;
735 if (dest_idx == (B44_RX_RING_SIZE - 1))
736 ctrl |= cpu_to_le32(DESC_CTRL_EOT);
737 else
738 ctrl &= cpu_to_le32(~DESC_CTRL_EOT);
739
740 dest_desc->ctrl = ctrl;
741 dest_desc->addr = src_desc->addr;
9f38c636 742
1da177e4
LT		 743 src_map->skb = NULL;
744
9f38c636
JL		 745 if (bp->flags & B44_FLAG_RX_RING_HACK)
746 b44_sync_dma_desc_for_device(bp->pdev, bp->rx_ring_dma,
747 dest_idx * sizeof(dest_desc),
748 DMA_BIDIRECTIONAL);
749
1da177e4
LT		 750 pci_dma_sync_single_for_device(bp->pdev, src_desc->addr,
751 RX_PKT_BUF_SZ,
752 PCI_DMA_FROMDEVICE);
753}
754
755static int b44_rx(struct b44 *bp, int budget)
756{
757 int received;
758 u32 cons, prod;
759
760 received = 0;
761 prod = br32(bp, B44_DMARX_STAT) & DMARX_STAT_CDMASK;
762 prod /= sizeof(struct dma_desc);
763 cons = bp->rx_cons;
764
765 while (cons != prod && budget > 0) {
766 struct ring_info *rp = &bp->rx_buffers[cons];
767 struct sk_buff *skb = rp->skb;
768 dma_addr_t map = pci_unmap_addr(rp, mapping);
769 struct rx_header *rh;
770 u16 len;
771
772 pci_dma_sync_single_for_cpu(bp->pdev, map,
773 RX_PKT_BUF_SZ,
774 PCI_DMA_FROMDEVICE);
775 rh = (struct rx_header *) skb->data;
776 len = cpu_to_le16(rh->len);
777 if ((len > (RX_PKT_BUF_SZ - bp->rx_offset)) ||
778 (rh->flags & cpu_to_le16(RX_FLAG_ERRORS))) {
779 drop_it:
780 b44_recycle_rx(bp, cons, bp->rx_prod);
781 drop_it_no_recycle:
782 bp->stats.rx_dropped++;
783 goto next_pkt;
784 }
785
786 if (len == 0) {
787 int i = 0;
788
789 do {
790 udelay(2);
791 barrier();
792 len = cpu_to_le16(rh->len);
793 } while (len == 0 && i++ < 5);
794 if (len == 0)
795 goto drop_it;
796 }
797
798 /* Omit CRC. */
799 len -= 4;
800
801 if (len > RX_COPY_THRESHOLD) {
802 int skb_size;
803 skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
804 if (skb_size < 0)
805 goto drop_it;
806 pci_unmap_single(bp->pdev, map,
807 skb_size, PCI_DMA_FROMDEVICE);
808 /* Leave out rx_header */
809 skb_put(skb, len+bp->rx_offset);
810 skb_pull(skb,bp->rx_offset);
811 } else {
812 struct sk_buff *copy_skb;
813
814 b44_recycle_rx(bp, cons, bp->rx_prod);
815 copy_skb = dev_alloc_skb(len + 2);
816 if (copy_skb == NULL)
817 goto drop_it_no_recycle;
818
819 copy_skb->dev = bp->dev;
820 skb_reserve(copy_skb, 2);
821 skb_put(copy_skb, len);
822 /* DMA sync done above, copy just the actual packet */
823 memcpy(copy_skb->data, skb->data+bp->rx_offset, len);
824
825 skb = copy_skb;
826 }
827 skb->ip_summed = CHECKSUM_NONE;
828 skb->protocol = eth_type_trans(skb, bp->dev);
829 netif_receive_skb(skb);
830 bp->dev->last_rx = jiffies;
831 received++;
832 budget--;
833 next_pkt:
834 bp->rx_prod = (bp->rx_prod + 1) &
835 (B44_RX_RING_SIZE - 1);
836 cons = (cons + 1) & (B44_RX_RING_SIZE - 1);
837 }
838
839 bp->rx_cons = cons;
840 bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc));
841
842 return received;
843}
844
845static int b44_poll(struct net_device *netdev, int *budget)
846{
847 struct b44 *bp = netdev_priv(netdev);
848 int done;
849
850 spin_lock_irq(&bp->lock);
851
852 if (bp->istat & (ISTAT_TX | ISTAT_TO)) {
853 /* spin_lock(&bp->tx_lock); */
854 b44_tx(bp);
855 /* spin_unlock(&bp->tx_lock); */
856 }
857 spin_unlock_irq(&bp->lock);
858
859 done = 1;
860 if (bp->istat & ISTAT_RX) {
861 int orig_budget = *budget;
862 int work_done;
863
864 if (orig_budget > netdev->quota)
865 orig_budget = netdev->quota;
866
867 work_done = b44_rx(bp, orig_budget);
868
869 *budget -= work_done;
870 netdev->quota -= work_done;
871
872 if (work_done >= orig_budget)
873 done = 0;
874 }
875
876 if (bp->istat & ISTAT_ERRORS) {
877 spin_lock_irq(&bp->lock);
878 b44_halt(bp);
879 b44_init_rings(bp);
880 b44_init_hw(bp);
881 netif_wake_queue(bp->dev);
882 spin_unlock_irq(&bp->lock);
883 done = 1;
884 }
885
886 if (done) {
887 netif_rx_complete(netdev);
888 b44_enable_ints(bp);
889 }
890
891 return (done ? 0 : 1);
892}
893
894static irqreturn_t b44_interrupt(int irq, void *dev_id, struct pt_regs *regs)
895{
896 struct net_device *dev = dev_id;
897 struct b44 *bp = netdev_priv(dev);
898 unsigned long flags;
899 u32 istat, imask;
900 int handled = 0;
901
902 spin_lock_irqsave(&bp->lock, flags);
903
904 istat = br32(bp, B44_ISTAT);
905 imask = br32(bp, B44_IMASK);
906
907 /* ??? What the fuck is the purpose of the interrupt mask
908 * ??? register if we have to mask it out by hand anyways?
909 */
910 istat &= imask;
911 if (istat) {
912 handled = 1;
913 if (netif_rx_schedule_prep(dev)) {
914 /* NOTE: These writes are posted by the readback of
915 * the ISTAT register below.
916 */
917 bp->istat = istat;
918 __b44_disable_ints(bp);
919 __netif_rx_schedule(dev);
920 } else {
921 printk(KERN_ERR PFX "%s: Error, poll already scheduled\n",
922 dev->name);
923 }
924
925 bw32(bp, B44_ISTAT, istat);
926 br32(bp, B44_ISTAT);
927 }
928 spin_unlock_irqrestore(&bp->lock, flags);
929 return IRQ_RETVAL(handled);
930}
931
932static void b44_tx_timeout(struct net_device *dev)
933{
934 struct b44 *bp = netdev_priv(dev);
935
936 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
937 dev->name);
938
939 spin_lock_irq(&bp->lock);
940
941 b44_halt(bp);
942 b44_init_rings(bp);
943 b44_init_hw(bp);
944
945 spin_unlock_irq(&bp->lock);
946
947 b44_enable_ints(bp);
948
949 netif_wake_queue(dev);
950}
951
952static int b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
953{
954 struct b44 *bp = netdev_priv(dev);
955 struct sk_buff *bounce_skb;
c7193693 956 int rc = NETDEV_TX_OK;
1da177e4
LT		 957 dma_addr_t mapping;
958 u32 len, entry, ctrl;
959
960 len = skb->len;
961 spin_lock_irq(&bp->lock);
962
963 /* This is a hard error, log it. */
964 if (unlikely(TX_BUFFS_AVAIL(bp) < 1)) {
965 netif_stop_queue(dev);
1da177e4
LT		 966 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
967 dev->name);
c7193693 968 goto err_out;
1da177e4
LT		 969 }
970
971 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
874a6214 972 if (mapping + len > B44_DMA_MASK) {
1da177e4
LT		 973 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
974 pci_unmap_single(bp->pdev, mapping, len, PCI_DMA_TODEVICE);
975
976 bounce_skb = __dev_alloc_skb(TX_PKT_BUF_SZ,
977 GFP_ATOMIC|GFP_DMA);
978 if (!bounce_skb)
c7193693 979 goto err_out;
1da177e4
LT		 980
981 mapping = pci_map_single(bp->pdev, bounce_skb->data,
982 len, PCI_DMA_TODEVICE);
874a6214 983 if (mapping + len > B44_DMA_MASK) {
1da177e4
LT		 984 pci_unmap_single(bp->pdev, mapping,
985 len, PCI_DMA_TODEVICE);
986 dev_kfree_skb_any(bounce_skb);
c7193693 987 goto err_out;
1da177e4
LT		 988 }
989
990 memcpy(skb_put(bounce_skb, len), skb->data, skb->len);
991 dev_kfree_skb_any(skb);
992 skb = bounce_skb;
993 }
994
995 entry = bp->tx_prod;
996 bp->tx_buffers[entry].skb = skb;
997 pci_unmap_addr_set(&bp->tx_buffers[entry], mapping, mapping);
998
999 ctrl = (len & DESC_CTRL_LEN);
1000 ctrl |= DESC_CTRL_IOC | DESC_CTRL_SOF | DESC_CTRL_EOF;
1001 if (entry == (B44_TX_RING_SIZE - 1))
1002 ctrl |= DESC_CTRL_EOT;
1003
1004 bp->tx_ring[entry].ctrl = cpu_to_le32(ctrl);
1005 bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset);
1006
9f38c636
JL		 1007 if (bp->flags & B44_FLAG_TX_RING_HACK)
1008 b44_sync_dma_desc_for_device(bp->pdev, bp->tx_ring_dma,
1009 entry * sizeof(bp->tx_ring[0]),
1010 DMA_TO_DEVICE);
1011
1da177e4
LT		 1012 entry = NEXT_TX(entry);
1013
1014 bp->tx_prod = entry;
1015
1016 wmb();
1017
1018 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1019 if (bp->flags & B44_FLAG_BUGGY_TXPTR)
1020 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1021 if (bp->flags & B44_FLAG_REORDER_BUG)
1022 br32(bp, B44_DMATX_PTR);
1023
1024 if (TX_BUFFS_AVAIL(bp) < 1)
1025 netif_stop_queue(dev);
1026
c7193693
FR		 1027 dev->trans_start = jiffies;
1028
1029out_unlock:
1da177e4
LT		 1030 spin_unlock_irq(&bp->lock);
1031
c7193693 1032 return rc;
1da177e4 1033
c7193693
FR		 1034err_out:
1035 rc = NETDEV_TX_BUSY;
1036 goto out_unlock;
1da177e4
LT		 1037}
1038
1039static int b44_change_mtu(struct net_device *dev, int new_mtu)
1040{
1041 struct b44 *bp = netdev_priv(dev);
1042
1043 if (new_mtu < B44_MIN_MTU || new_mtu > B44_MAX_MTU)
1044 return -EINVAL;
1045
1046 if (!netif_running(dev)) {
1047 /* We'll just catch it later when the
1048 * device is up'd.
1049 */
1050 dev->mtu = new_mtu;
1051 return 0;
1052 }
1053
1054 spin_lock_irq(&bp->lock);
1055 b44_halt(bp);
1056 dev->mtu = new_mtu;
1057 b44_init_rings(bp);
1058 b44_init_hw(bp);
1059 spin_unlock_irq(&bp->lock);
1060
1061 b44_enable_ints(bp);
1062
1063 return 0;
1064}
1065
1066/* Free up pending packets in all rx/tx rings.
1067 *
1068 * The chip has been shut down and the driver detached from
1069 * the networking, so no interrupts or new tx packets will
1070 * end up in the driver. bp->lock is not held and we are not
1071 * in an interrupt context and thus may sleep.
1072 */
1073static void b44_free_rings(struct b44 *bp)
1074{
1075 struct ring_info *rp;
1076 int i;
1077
1078 for (i = 0; i < B44_RX_RING_SIZE; i++) {
1079 rp = &bp->rx_buffers[i];
1080
1081 if (rp->skb == NULL)
1082 continue;
1083 pci_unmap_single(bp->pdev,
1084 pci_unmap_addr(rp, mapping),
1085 RX_PKT_BUF_SZ,
1086 PCI_DMA_FROMDEVICE);
1087 dev_kfree_skb_any(rp->skb);
1088 rp->skb = NULL;
1089 }
1090
1091 /* XXX needs changes once NETIF_F_SG is set... */
1092 for (i = 0; i < B44_TX_RING_SIZE; i++) {
1093 rp = &bp->tx_buffers[i];
1094
1095 if (rp->skb == NULL)
1096 continue;
1097 pci_unmap_single(bp->pdev,
1098 pci_unmap_addr(rp, mapping),
1099 rp->skb->len,
1100 PCI_DMA_TODEVICE);
1101 dev_kfree_skb_any(rp->skb);
1102 rp->skb = NULL;
1103 }
1104}
1105
1106/* Initialize tx/rx rings for packet processing.
1107 *
1108 * The chip has been shut down and the driver detached from
1109 * the networking, so no interrupts or new tx packets will
874a6214 1110 * end up in the driver.
1da177e4
LT		 1111 */
1112static void b44_init_rings(struct b44 *bp)
1113{
1114 int i;
1115
1116 b44_free_rings(bp);
1117
1118 memset(bp->rx_ring, 0, B44_RX_RING_BYTES);
1119 memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
1120
9f38c636
JL		 1121 if (bp->flags & B44_FLAG_RX_RING_HACK)
1122 dma_sync_single_for_device(&bp->pdev->dev, bp->rx_ring_dma,
1123 DMA_TABLE_BYTES,
1124 PCI_DMA_BIDIRECTIONAL);
1125
1126 if (bp->flags & B44_FLAG_TX_RING_HACK)
1127 dma_sync_single_for_device(&bp->pdev->dev, bp->tx_ring_dma,
1128 DMA_TABLE_BYTES,
1129 PCI_DMA_TODEVICE);
1130
1da177e4
LT		 1131 for (i = 0; i < bp->rx_pending; i++) {
1132 if (b44_alloc_rx_skb(bp, -1, i) < 0)
1133 break;
1134 }
1135}
1136
1137/*
1138 * Must not be invoked with interrupt sources disabled and
1139 * the hardware shutdown down.
1140 */
1141static void b44_free_consistent(struct b44 *bp)
1142{
b4558ea9
JJ		 1143 kfree(bp->rx_buffers);
1144 bp->rx_buffers = NULL;
1145 kfree(bp->tx_buffers);
1146 bp->tx_buffers = NULL;
1da177e4 1147 if (bp->rx_ring) {
9f38c636
JL		 1148 if (bp->flags & B44_FLAG_RX_RING_HACK) {
1149 dma_unmap_single(&bp->pdev->dev, bp->rx_ring_dma,
1150 DMA_TABLE_BYTES,
1151 DMA_BIDIRECTIONAL);
1152 kfree(bp->rx_ring);
1153 } else
1154 pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
1155 bp->rx_ring, bp->rx_ring_dma);
1da177e4 1156 bp->rx_ring = NULL;
9f38c636 1157 bp->flags &= ~B44_FLAG_RX_RING_HACK;
1da177e4
LT		 1158 }
1159 if (bp->tx_ring) {
9f38c636
JL		 1160 if (bp->flags & B44_FLAG_TX_RING_HACK) {
1161 dma_unmap_single(&bp->pdev->dev, bp->tx_ring_dma,
1162 DMA_TABLE_BYTES,
1163 DMA_TO_DEVICE);
1164 kfree(bp->tx_ring);
1165 } else
1166 pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
1167 bp->tx_ring, bp->tx_ring_dma);
1da177e4 1168 bp->tx_ring = NULL;
9f38c636 1169 bp->flags &= ~B44_FLAG_TX_RING_HACK;
1da177e4
LT		 1170 }
1171}
1172
1173/*
1174 * Must not be invoked with interrupt sources disabled and
1175 * the hardware shutdown down. Can sleep.
1176 */
1177static int b44_alloc_consistent(struct b44 *bp)
1178{
1179 int size;
1180
1181 size = B44_RX_RING_SIZE * sizeof(struct ring_info);
874a6214 1182 bp->rx_buffers = kzalloc(size, GFP_KERNEL);
1da177e4
LT		 1183 if (!bp->rx_buffers)
1184 goto out_err;
1da177e4
LT		 1185
1186 size = B44_TX_RING_SIZE * sizeof(struct ring_info);
874a6214 1187 bp->tx_buffers = kzalloc(size, GFP_KERNEL);
1da177e4
LT		 1188 if (!bp->tx_buffers)
1189 goto out_err;
1da177e4
LT		 1190
1191 size = DMA_TABLE_BYTES;
1192 bp->rx_ring = pci_alloc_consistent(bp->pdev, size, &bp->rx_ring_dma);
9f38c636
JL		 1193 if (!bp->rx_ring) {
1194 /* Allocation may have failed due to pci_alloc_consistent
1195 insisting on use of GFP_DMA, which is more restrictive
1196 than necessary... */
1197 struct dma_desc *rx_ring;
1198 dma_addr_t rx_ring_dma;
1199
874a6214
FR		 1200 rx_ring = kzalloc(size, GFP_KERNEL);
1201 if (!rx_ring)
9f38c636
JL		 1202 goto out_err;
1203
9f38c636
JL		 1204 rx_ring_dma = dma_map_single(&bp->pdev->dev, rx_ring,
1205 DMA_TABLE_BYTES,
1206 DMA_BIDIRECTIONAL);
1207
1208 if (rx_ring_dma + size > B44_DMA_MASK) {
1209 kfree(rx_ring);
1210 goto out_err;
1211 }
1212
1213 bp->rx_ring = rx_ring;
1214 bp->rx_ring_dma = rx_ring_dma;
1215 bp->flags |= B44_FLAG_RX_RING_HACK;
1216 }
1da177e4
LT		 1217
1218 bp->tx_ring = pci_alloc_consistent(bp->pdev, size, &bp->tx_ring_dma);
9f38c636
JL		 1219 if (!bp->tx_ring) {
1220 /* Allocation may have failed due to pci_alloc_consistent
1221 insisting on use of GFP_DMA, which is more restrictive
1222 than necessary... */
1223 struct dma_desc *tx_ring;
1224 dma_addr_t tx_ring_dma;
1225
874a6214
FR		 1226 tx_ring = kzalloc(size, GFP_KERNEL);
1227 if (!tx_ring)
9f38c636
JL		 1228 goto out_err;
1229
9f38c636
JL		 1230 tx_ring_dma = dma_map_single(&bp->pdev->dev, tx_ring,
1231 DMA_TABLE_BYTES,
1232 DMA_TO_DEVICE);
1233
1234 if (tx_ring_dma + size > B44_DMA_MASK) {
1235 kfree(tx_ring);
1236 goto out_err;
1237 }
1238
1239 bp->tx_ring = tx_ring;
1240 bp->tx_ring_dma = tx_ring_dma;
1241 bp->flags |= B44_FLAG_TX_RING_HACK;
1242 }
1da177e4
LT		 1243
1244 return 0;
1245
1246out_err:
1247 b44_free_consistent(bp);
1248 return -ENOMEM;
1249}
1250
1251/* bp->lock is held. */
1252static void b44_clear_stats(struct b44 *bp)
1253{
1254 unsigned long reg;
1255
1256 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1257 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL)
1258 br32(bp, reg);
1259 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL)
1260 br32(bp, reg);
1261}
1262
1263/* bp->lock is held. */
1264static void b44_chip_reset(struct b44 *bp)
1265{
1266 if (ssb_is_core_up(bp)) {
1267 bw32(bp, B44_RCV_LAZY, 0);
1268 bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
1269 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 100, 1);
1270 bw32(bp, B44_DMATX_CTRL, 0);
1271 bp->tx_prod = bp->tx_cons = 0;
1272 if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) {
1273 b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
1274 100, 0);
1275 }
1276 bw32(bp, B44_DMARX_CTRL, 0);
1277 bp->rx_prod = bp->rx_cons = 0;
1278 } else {
1279 ssb_pci_setup(bp, (bp->core_unit == 0 ?
1280 SBINTVEC_ENET0 :
1281 SBINTVEC_ENET1));
1282 }
1283
1284 ssb_core_reset(bp);
1285
1286 b44_clear_stats(bp);
1287
1288 /* Make PHY accessible. */
1289 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1290 (0x0d & MDIO_CTRL_MAXF_MASK)));
1291 br32(bp, B44_MDIO_CTRL);
1292
1293 if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
1294 bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);
1295 br32(bp, B44_ENET_CTRL);
1296 bp->flags &= ~B44_FLAG_INTERNAL_PHY;
1297 } else {
1298 u32 val = br32(bp, B44_DEVCTRL);
1299
1300 if (val & DEVCTRL_EPR) {
1301 bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
1302 br32(bp, B44_DEVCTRL);
1303 udelay(100);
1304 }
1305 bp->flags |= B44_FLAG_INTERNAL_PHY;
1306 }
1307}
1308
1309/* bp->lock is held. */
1310static void b44_halt(struct b44 *bp)
1311{
1312 b44_disable_ints(bp);
1313 b44_chip_reset(bp);
1314}
1315
1316/* bp->lock is held. */
1317static void __b44_set_mac_addr(struct b44 *bp)
1318{
1319 bw32(bp, B44_CAM_CTRL, 0);
1320 if (!(bp->dev->flags & IFF_PROMISC)) {
1321 u32 val;
1322
1323 __b44_cam_write(bp, bp->dev->dev_addr, 0);
1324 val = br32(bp, B44_CAM_CTRL);
1325 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1326 }
1327}
1328
1329static int b44_set_mac_addr(struct net_device *dev, void *p)
1330{
1331 struct b44 *bp = netdev_priv(dev);
1332 struct sockaddr *addr = p;
1333
1334 if (netif_running(dev))
1335 return -EBUSY;
1336
1337 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1338
1339 spin_lock_irq(&bp->lock);
1340 __b44_set_mac_addr(bp);
1341 spin_unlock_irq(&bp->lock);
1342
1343 return 0;
1344}
1345
1346/* Called at device open time to get the chip ready for
1347 * packet processing. Invoked with bp->lock held.
1348 */
1349static void __b44_set_rx_mode(struct net_device *);
1350static void b44_init_hw(struct b44 *bp)
1351{
1352 u32 val;
1353
1354 b44_chip_reset(bp);
1355 b44_phy_reset(bp);
1356 b44_setup_phy(bp);
1357
1358 /* Enable CRC32, set proper LED modes and power on PHY */
1359 bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
1360 bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
1361
1362 /* This sets the MAC address too. */
1363 __b44_set_rx_mode(bp->dev);
1364
1365 /* MTU + eth header + possible VLAN tag + struct rx_header */
1366 bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1367 bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1368
1369 bw32(bp, B44_TX_WMARK, 56); /* XXX magic */
1370 bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
1371 bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
1372 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1373 (bp->rx_offset << DMARX_CTRL_ROSHIFT)));
1374 bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
1375
1376 bw32(bp, B44_DMARX_PTR, bp->rx_pending);
1377 bp->rx_prod = bp->rx_pending;
1378
1379 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1380
1381 val = br32(bp, B44_ENET_CTRL);
1382 bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
1383}
1384
1385static int b44_open(struct net_device *dev)
1386{
1387 struct b44 *bp = netdev_priv(dev);
1388 int err;
1389
1390 err = b44_alloc_consistent(bp);
1391 if (err)
1392 return err;
1393
1394 err = request_irq(dev->irq, b44_interrupt, SA_SHIRQ, dev->name, dev);
1395 if (err)
1396 goto err_out_free;
1397
1398 spin_lock_irq(&bp->lock);
1399
1400 b44_init_rings(bp);
1401 b44_init_hw(bp);
1402 bp->flags |= B44_FLAG_INIT_COMPLETE;
1403
e254e9bf
JL		 1404 netif_carrier_off(dev);
1405 b44_check_phy(bp);
1406
1da177e4
LT		 1407 spin_unlock_irq(&bp->lock);
1408
1409 init_timer(&bp->timer);
1410 bp->timer.expires = jiffies + HZ;
1411 bp->timer.data = (unsigned long) bp;
1412 bp->timer.function = b44_timer;
1413 add_timer(&bp->timer);
1414
1415 b44_enable_ints(bp);
1416
1417 return 0;
1418
1419err_out_free:
1420 b44_free_consistent(bp);
1421 return err;
1422}
1423
1424#if 0
1425/*static*/ void b44_dump_state(struct b44 *bp)
1426{
1427 u32 val32, val32_2, val32_3, val32_4, val32_5;
1428 u16 val16;
1429
1430 pci_read_config_word(bp->pdev, PCI_STATUS, &val16);
1431 printk("DEBUG: PCI status [%04x] \n", val16);
1432
1433}
1434#endif
1435
1436#ifdef CONFIG_NET_POLL_CONTROLLER
1437/*
1438 * Polling receive - used by netconsole and other diagnostic tools
1439 * to allow network i/o with interrupts disabled.
1440 */
1441static void b44_poll_controller(struct net_device *dev)
1442{
1443 disable_irq(dev->irq);
1444 b44_interrupt(dev->irq, dev, NULL);
1445 enable_irq(dev->irq);
1446}
1447#endif
1448
1449static int b44_close(struct net_device *dev)
1450{
1451 struct b44 *bp = netdev_priv(dev);
1452
1453 netif_stop_queue(dev);
1454
1455 del_timer_sync(&bp->timer);
1456
1457 spin_lock_irq(&bp->lock);
1458
1459#if 0
1460 b44_dump_state(bp);
1461#endif
1462 b44_halt(bp);
1463 b44_free_rings(bp);
1464 bp->flags &= ~B44_FLAG_INIT_COMPLETE;
1465 netif_carrier_off(bp->dev);
1466
1467 spin_unlock_irq(&bp->lock);
1468
1469 free_irq(dev->irq, dev);
1470
1471 b44_free_consistent(bp);
1472
1473 return 0;
1474}
1475
1476static struct net_device_stats *b44_get_stats(struct net_device *dev)
1477{
1478 struct b44 *bp = netdev_priv(dev);
1479 struct net_device_stats *nstat = &bp->stats;
1480 struct b44_hw_stats *hwstat = &bp->hw_stats;
1481
1482 /* Convert HW stats into netdevice stats. */
1483 nstat->rx_packets = hwstat->rx_pkts;
1484 nstat->tx_packets = hwstat->tx_pkts;
1485 nstat->rx_bytes = hwstat->rx_octets;
1486 nstat->tx_bytes = hwstat->tx_octets;
1487 nstat->tx_errors = (hwstat->tx_jabber_pkts +
1488 hwstat->tx_oversize_pkts +
1489 hwstat->tx_underruns +
1490 hwstat->tx_excessive_cols +
1491 hwstat->tx_late_cols);
1492 nstat->multicast = hwstat->tx_multicast_pkts;
1493 nstat->collisions = hwstat->tx_total_cols;
1494
1495 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1496 hwstat->rx_undersize);
1497 nstat->rx_over_errors = hwstat->rx_missed_pkts;
1498 nstat->rx_frame_errors = hwstat->rx_align_errs;
1499 nstat->rx_crc_errors = hwstat->rx_crc_errs;
1500 nstat->rx_errors = (hwstat->rx_jabber_pkts +
1501 hwstat->rx_oversize_pkts +
1502 hwstat->rx_missed_pkts +
1503 hwstat->rx_crc_align_errs +
1504 hwstat->rx_undersize +
1505 hwstat->rx_crc_errs +
1506 hwstat->rx_align_errs +
1507 hwstat->rx_symbol_errs);
1508
1509 nstat->tx_aborted_errors = hwstat->tx_underruns;
1510#if 0
1511 /* Carrier lost counter seems to be broken for some devices */
1512 nstat->tx_carrier_errors = hwstat->tx_carrier_lost;
1513#endif
1514
1515 return nstat;
1516}
1517
1518static int __b44_load_mcast(struct b44 *bp, struct net_device *dev)
1519{
1520 struct dev_mc_list *mclist;
1521 int i, num_ents;
1522
1523 num_ents = min_t(int, dev->mc_count, B44_MCAST_TABLE_SIZE);
1524 mclist = dev->mc_list;
1525 for (i = 0; mclist && i < num_ents; i++, mclist = mclist->next) {
1526 __b44_cam_write(bp, mclist->dmi_addr, i + 1);
1527 }
1528 return i+1;
1529}
1530
1531static void __b44_set_rx_mode(struct net_device *dev)
1532{
1533 struct b44 *bp = netdev_priv(dev);
1534 u32 val;
1da177e4
LT		 1535
1536 val = br32(bp, B44_RXCONFIG);
1537 val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
1538 if (dev->flags & IFF_PROMISC) {
1539 val |= RXCONFIG_PROMISC;
1540 bw32(bp, B44_RXCONFIG, val);
1541 } else {
874a6214
FR		 1542 unsigned char zero[6] = {0, 0, 0, 0, 0, 0};
1543 int i = 0;
1544
1da177e4
LT		 1545 __b44_set_mac_addr(bp);
1546
1547 if (dev->flags & IFF_ALLMULTI)
1548 val |= RXCONFIG_ALLMULTI;
1549 else
874a6214 1550 i = __b44_load_mcast(bp, dev);
1da177e4 1551
874a6214 1552 for (; i < 64; i++) {
1da177e4
LT		 1553 __b44_cam_write(bp, zero, i);
1554 }
1555 bw32(bp, B44_RXCONFIG, val);
1556 val = br32(bp, B44_CAM_CTRL);
1557 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1558 }
1559}
1560
1561static void b44_set_rx_mode(struct net_device *dev)
1562{
1563 struct b44 *bp = netdev_priv(dev);
1564
1565 spin_lock_irq(&bp->lock);
1566 __b44_set_rx_mode(dev);
1567 spin_unlock_irq(&bp->lock);
1568}
1569
1570static u32 b44_get_msglevel(struct net_device *dev)
1571{
1572 struct b44 *bp = netdev_priv(dev);
1573 return bp->msg_enable;
1574}
1575
1576static void b44_set_msglevel(struct net_device *dev, u32 value)
1577{
1578 struct b44 *bp = netdev_priv(dev);
1579 bp->msg_enable = value;
1580}
1581
1582static void b44_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1583{
1584 struct b44 *bp = netdev_priv(dev);
1585 struct pci_dev *pci_dev = bp->pdev;
1586
1587 strcpy (info->driver, DRV_MODULE_NAME);
1588 strcpy (info->version, DRV_MODULE_VERSION);
1589 strcpy (info->bus_info, pci_name(pci_dev));
1590}
1591
1592static int b44_nway_reset(struct net_device *dev)
1593{
1594 struct b44 *bp = netdev_priv(dev);
1595 u32 bmcr;
1596 int r;
1597
1598 spin_lock_irq(&bp->lock);
1599 b44_readphy(bp, MII_BMCR, &bmcr);
1600 b44_readphy(bp, MII_BMCR, &bmcr);
1601 r = -EINVAL;
1602 if (bmcr & BMCR_ANENABLE) {
1603 b44_writephy(bp, MII_BMCR,
1604 bmcr | BMCR_ANRESTART);
1605 r = 0;
1606 }
1607 spin_unlock_irq(&bp->lock);
1608
1609 return r;
1610}
1611
1612static int b44_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1613{
1614 struct b44 *bp = netdev_priv(dev);
1615
1616 if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
1617 return -EAGAIN;
1618 cmd->supported = (SUPPORTED_Autoneg);
1619 cmd->supported |= (SUPPORTED_100baseT_Half |
1620 SUPPORTED_100baseT_Full |
1621 SUPPORTED_10baseT_Half |
1622 SUPPORTED_10baseT_Full |
1623 SUPPORTED_MII);
1624
1625 cmd->advertising = 0;
1626 if (bp->flags & B44_FLAG_ADV_10HALF)
adf6e000 1627 cmd->advertising |= ADVERTISED_10baseT_Half;
1da177e4 1628 if (bp->flags & B44_FLAG_ADV_10FULL)
adf6e000 1629 cmd->advertising |= ADVERTISED_10baseT_Full;
1da177e4 1630 if (bp->flags & B44_FLAG_ADV_100HALF)
adf6e000 1631 cmd->advertising |= ADVERTISED_100baseT_Half;
1da177e4 1632 if (bp->flags & B44_FLAG_ADV_100FULL)
adf6e000
MW		 1633 cmd->advertising |= ADVERTISED_100baseT_Full;
1634 cmd->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
1da177e4
LT		 1635 cmd->speed = (bp->flags & B44_FLAG_100_BASE_T) ?
1636 SPEED_100 : SPEED_10;
1637 cmd->duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
1638 DUPLEX_FULL : DUPLEX_HALF;
1639 cmd->port = 0;
1640 cmd->phy_address = bp->phy_addr;
1641 cmd->transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
1642 XCVR_INTERNAL : XCVR_EXTERNAL;
1643 cmd->autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
1644 AUTONEG_DISABLE : AUTONEG_ENABLE;
1645 cmd->maxtxpkt = 0;
1646 cmd->maxrxpkt = 0;
1647 return 0;
1648}
1649
1650static int b44_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1651{
1652 struct b44 *bp = netdev_priv(dev);
1653
1654 if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
1655 return -EAGAIN;
1656
1657 /* We do not support gigabit. */
1658 if (cmd->autoneg == AUTONEG_ENABLE) {
1659 if (cmd->advertising &
1660 (ADVERTISED_1000baseT_Half |
1661 ADVERTISED_1000baseT_Full))
1662 return -EINVAL;
1663 } else if ((cmd->speed != SPEED_100 &&
1664 cmd->speed != SPEED_10) ||
1665 (cmd->duplex != DUPLEX_HALF &&
1666 cmd->duplex != DUPLEX_FULL)) {
1667 return -EINVAL;
1668 }
1669
1670 spin_lock_irq(&bp->lock);
1671
1672 if (cmd->autoneg == AUTONEG_ENABLE) {
1673 bp->flags &= ~B44_FLAG_FORCE_LINK;
1674 bp->flags &= ~(B44_FLAG_ADV_10HALF |
1675 B44_FLAG_ADV_10FULL |
1676 B44_FLAG_ADV_100HALF |
1677 B44_FLAG_ADV_100FULL);
1678 if (cmd->advertising & ADVERTISE_10HALF)
1679 bp->flags |= B44_FLAG_ADV_10HALF;
1680 if (cmd->advertising & ADVERTISE_10FULL)
1681 bp->flags |= B44_FLAG_ADV_10FULL;
1682 if (cmd->advertising & ADVERTISE_100HALF)
1683 bp->flags |= B44_FLAG_ADV_100HALF;
1684 if (cmd->advertising & ADVERTISE_100FULL)
1685 bp->flags |= B44_FLAG_ADV_100FULL;
1686 } else {
1687 bp->flags |= B44_FLAG_FORCE_LINK;
1688 if (cmd->speed == SPEED_100)
1689 bp->flags |= B44_FLAG_100_BASE_T;
1690 if (cmd->duplex == DUPLEX_FULL)
1691 bp->flags |= B44_FLAG_FULL_DUPLEX;
1692 }
1693
1694 b44_setup_phy(bp);
1695
1696 spin_unlock_irq(&bp->lock);
1697
1698 return 0;
1699}
1700
1701static void b44_get_ringparam(struct net_device *dev,
1702 struct ethtool_ringparam *ering)
1703{
1704 struct b44 *bp = netdev_priv(dev);
1705
1706 ering->rx_max_pending = B44_RX_RING_SIZE - 1;
1707 ering->rx_pending = bp->rx_pending;
1708
1709 /* XXX ethtool lacks a tx_max_pending, oops... */
1710}
1711
1712static int b44_set_ringparam(struct net_device *dev,
1713 struct ethtool_ringparam *ering)
1714{
1715 struct b44 *bp = netdev_priv(dev);
1716
1717 if ((ering->rx_pending > B44_RX_RING_SIZE - 1) ||
1718 (ering->rx_mini_pending != 0) ||
1719 (ering->rx_jumbo_pending != 0) ||
1720 (ering->tx_pending > B44_TX_RING_SIZE - 1))
1721 return -EINVAL;
1722
1723 spin_lock_irq(&bp->lock);
1724
1725 bp->rx_pending = ering->rx_pending;
1726 bp->tx_pending = ering->tx_pending;
1727
1728 b44_halt(bp);
1729 b44_init_rings(bp);
1730 b44_init_hw(bp);
1731 netif_wake_queue(bp->dev);
1732 spin_unlock_irq(&bp->lock);
1733
1734 b44_enable_ints(bp);
1735
1736 return 0;
1737}
1738
1739static void b44_get_pauseparam(struct net_device *dev,
1740 struct ethtool_pauseparam *epause)
1741{
1742 struct b44 *bp = netdev_priv(dev);
1743
1744 epause->autoneg =
1745 (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
1746 epause->rx_pause =
1747 (bp->flags & B44_FLAG_RX_PAUSE) != 0;
1748 epause->tx_pause =
1749 (bp->flags & B44_FLAG_TX_PAUSE) != 0;
1750}
1751
1752static int b44_set_pauseparam(struct net_device *dev,
1753 struct ethtool_pauseparam *epause)
1754{
1755 struct b44 *bp = netdev_priv(dev);
1756
1757 spin_lock_irq(&bp->lock);
1758 if (epause->autoneg)
1759 bp->flags |= B44_FLAG_PAUSE_AUTO;
1760 else
1761 bp->flags &= ~B44_FLAG_PAUSE_AUTO;
1762 if (epause->rx_pause)
1763 bp->flags |= B44_FLAG_RX_PAUSE;
1764 else
1765 bp->flags &= ~B44_FLAG_RX_PAUSE;
1766 if (epause->tx_pause)
1767 bp->flags |= B44_FLAG_TX_PAUSE;
1768 else
1769 bp->flags &= ~B44_FLAG_TX_PAUSE;
1770 if (bp->flags & B44_FLAG_PAUSE_AUTO) {
1771 b44_halt(bp);
1772 b44_init_rings(bp);
1773 b44_init_hw(bp);
1774 } else {
1775 __b44_set_flow_ctrl(bp, bp->flags);
1776 }
1777 spin_unlock_irq(&bp->lock);
1778
1779 b44_enable_ints(bp);
1780
1781 return 0;
1782}
1783
3353930d
FR		 1784static void b44_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1785{
1786 switch(stringset) {
1787 case ETH_SS_STATS:
1788 memcpy(data, *b44_gstrings, sizeof(b44_gstrings));
1789 break;
1790 }
1791}
1792
1793static int b44_get_stats_count(struct net_device *dev)
1794{
1795 return ARRAY_SIZE(b44_gstrings);
1796}
1797
1798static void b44_get_ethtool_stats(struct net_device *dev,
1799 struct ethtool_stats *stats, u64 *data)
1800{
1801 struct b44 *bp = netdev_priv(dev);
1802 u32 *val = &bp->hw_stats.tx_good_octets;
1803 u32 i;
1804
1805 spin_lock_irq(&bp->lock);
1806
1807 b44_stats_update(bp);
1808
1809 for (i = 0; i < ARRAY_SIZE(b44_gstrings); i++)
1810 *data++ = *val++;
1811
1812 spin_unlock_irq(&bp->lock);
1813}
1814
1da177e4
LT		 1815static struct ethtool_ops b44_ethtool_ops = {
1816 .get_drvinfo = b44_get_drvinfo,
1817 .get_settings = b44_get_settings,
1818 .set_settings = b44_set_settings,
1819 .nway_reset = b44_nway_reset,
1820 .get_link = ethtool_op_get_link,
1821 .get_ringparam = b44_get_ringparam,
1822 .set_ringparam = b44_set_ringparam,
1823 .get_pauseparam = b44_get_pauseparam,
1824 .set_pauseparam = b44_set_pauseparam,
1825 .get_msglevel = b44_get_msglevel,
1826 .set_msglevel = b44_set_msglevel,
3353930d
FR		 1827 .get_strings = b44_get_strings,
1828 .get_stats_count = b44_get_stats_count,
1829 .get_ethtool_stats = b44_get_ethtool_stats,
2160de53 1830 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 1831};
1832
1833static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1834{
1835 struct mii_ioctl_data *data = if_mii(ifr);
1836 struct b44 *bp = netdev_priv(dev);
1837 int err;
1838
1839 spin_lock_irq(&bp->lock);
1840 err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
1841 spin_unlock_irq(&bp->lock);
1842
1843 return err;
1844}
1845
1846/* Read 128-bytes of EEPROM. */
1847static int b44_read_eeprom(struct b44 *bp, u8 *data)
1848{
1849 long i;
1850 u16 *ptr = (u16 *) data;
1851
1852 for (i = 0; i < 128; i += 2)
1853 ptr[i / 2] = readw(bp->regs + 4096 + i);
1854
1855 return 0;
1856}
1857
1858static int __devinit b44_get_invariants(struct b44 *bp)
1859{
1860 u8 eeprom[128];
1861 int err;
1862
1863 err = b44_read_eeprom(bp, &eeprom[0]);
1864 if (err)
1865 goto out;
1866
1867 bp->dev->dev_addr[0] = eeprom[79];
1868 bp->dev->dev_addr[1] = eeprom[78];
1869 bp->dev->dev_addr[2] = eeprom[81];
1870 bp->dev->dev_addr[3] = eeprom[80];
1871 bp->dev->dev_addr[4] = eeprom[83];
1872 bp->dev->dev_addr[5] = eeprom[82];
2160de53 1873 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
1da177e4
LT		 1874
1875 bp->phy_addr = eeprom[90] & 0x1f;
1876
1877 /* With this, plus the rx_header prepended to the data by the
1878 * hardware, we'll land the ethernet header on a 2-byte boundary.
1879 */
1880 bp->rx_offset = 30;
1881
1882 bp->imask = IMASK_DEF;
1883
1884 bp->core_unit = ssb_core_unit(bp);
1885 bp->dma_offset = SB_PCI_DMA;
1886
1887 /* XXX - really required?
1888 bp->flags |= B44_FLAG_BUGGY_TXPTR;
1889 */
1890out:
1891 return err;
1892}
1893
1894static int __devinit b44_init_one(struct pci_dev *pdev,
1895 const struct pci_device_id *ent)
1896{
1897 static int b44_version_printed = 0;
1898 unsigned long b44reg_base, b44reg_len;
1899 struct net_device *dev;
1900 struct b44 *bp;
1901 int err, i;
1902
1903 if (b44_version_printed++ == 0)
1904 printk(KERN_INFO "%s", version);
1905
1906 err = pci_enable_device(pdev);
1907 if (err) {
1908 printk(KERN_ERR PFX "Cannot enable PCI device, "
1909 "aborting.\n");
1910 return err;
1911 }
1912
1913 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1914 printk(KERN_ERR PFX "Cannot find proper PCI device "
1915 "base address, aborting.\n");
1916 err = -ENODEV;
1917 goto err_out_disable_pdev;
1918 }
1919
1920 err = pci_request_regions(pdev, DRV_MODULE_NAME);
1921 if (err) {
1922 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
1923 "aborting.\n");
1924 goto err_out_disable_pdev;
1925 }
1926
1927 pci_set_master(pdev);
1928
1929 err = pci_set_dma_mask(pdev, (u64) B44_DMA_MASK);
1930 if (err) {
1931 printk(KERN_ERR PFX "No usable DMA configuration, "
1932 "aborting.\n");
1933 goto err_out_free_res;
1934 }
1935
1936 err = pci_set_consistent_dma_mask(pdev, (u64) B44_DMA_MASK);
1937 if (err) {
874a6214
FR		 1938 printk(KERN_ERR PFX "No usable DMA configuration, "
1939 "aborting.\n");
1940 goto err_out_free_res;
1da177e4
LT		 1941 }
1942
1943 b44reg_base = pci_resource_start(pdev, 0);
1944 b44reg_len = pci_resource_len(pdev, 0);
1945
1946 dev = alloc_etherdev(sizeof(*bp));
1947 if (!dev) {
1948 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
1949 err = -ENOMEM;
1950 goto err_out_free_res;
1951 }
1952
1953 SET_MODULE_OWNER(dev);
1954 SET_NETDEV_DEV(dev,&pdev->dev);
1955
1956 /* No interesting netdevice features in this card... */
1957 dev->features |= 0;
1958
1959 bp = netdev_priv(dev);
1960 bp->pdev = pdev;
1961 bp->dev = dev;
874a6214
FR		 1962
1963 bp->msg_enable = netif_msg_init(b44_debug, B44_DEF_MSG_ENABLE);
1da177e4
LT		 1964
1965 spin_lock_init(&bp->lock);
1966
1967 bp->regs = ioremap(b44reg_base, b44reg_len);
1968 if (bp->regs == 0UL) {
1969 printk(KERN_ERR PFX "Cannot map device registers, "
1970 "aborting.\n");
1971 err = -ENOMEM;
1972 goto err_out_free_dev;
1973 }
1974
1975 bp->rx_pending = B44_DEF_RX_RING_PENDING;
1976 bp->tx_pending = B44_DEF_TX_RING_PENDING;
1977
1978 dev->open = b44_open;
1979 dev->stop = b44_close;
1980 dev->hard_start_xmit = b44_start_xmit;
1981 dev->get_stats = b44_get_stats;
1982 dev->set_multicast_list = b44_set_rx_mode;
1983 dev->set_mac_address = b44_set_mac_addr;
1984 dev->do_ioctl = b44_ioctl;
1985 dev->tx_timeout = b44_tx_timeout;
1986 dev->poll = b44_poll;
1987 dev->weight = 64;
1988 dev->watchdog_timeo = B44_TX_TIMEOUT;
1989#ifdef CONFIG_NET_POLL_CONTROLLER
1990 dev->poll_controller = b44_poll_controller;
1991#endif
1992 dev->change_mtu = b44_change_mtu;
1993 dev->irq = pdev->irq;
1994 SET_ETHTOOL_OPS(dev, &b44_ethtool_ops);
1995
1996 err = b44_get_invariants(bp);
1997 if (err) {
1998 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
1999 "aborting.\n");
2000 goto err_out_iounmap;
2001 }
2002
2003 bp->mii_if.dev = dev;
2004 bp->mii_if.mdio_read = b44_mii_read;
2005 bp->mii_if.mdio_write = b44_mii_write;
2006 bp->mii_if.phy_id = bp->phy_addr;
2007 bp->mii_if.phy_id_mask = 0x1f;
2008 bp->mii_if.reg_num_mask = 0x1f;
2009
2010 /* By default, advertise all speed/duplex settings. */
2011 bp->flags |= (B44_FLAG_ADV_10HALF | B44_FLAG_ADV_10FULL |
2012 B44_FLAG_ADV_100HALF | B44_FLAG_ADV_100FULL);
2013
2014 /* By default, auto-negotiate PAUSE. */
2015 bp->flags |= B44_FLAG_PAUSE_AUTO;
2016
2017 err = register_netdev(dev);
2018 if (err) {
2019 printk(KERN_ERR PFX "Cannot register net device, "
2020 "aborting.\n");
2021 goto err_out_iounmap;
2022 }
2023
2024 pci_set_drvdata(pdev, dev);
2025
2026 pci_save_state(bp->pdev);
2027
2028 printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
2029 for (i = 0; i < 6; i++)
2030 printk("%2.2x%c", dev->dev_addr[i],
2031 i == 5 ? '\n' : ':');
2032
2033 return 0;
2034
2035err_out_iounmap:
2036 iounmap(bp->regs);
2037
2038err_out_free_dev:
2039 free_netdev(dev);
2040
2041err_out_free_res:
2042 pci_release_regions(pdev);
2043
2044err_out_disable_pdev:
2045 pci_disable_device(pdev);
2046 pci_set_drvdata(pdev, NULL);
2047 return err;
2048}
2049
2050static void __devexit b44_remove_one(struct pci_dev *pdev)
2051{
2052 struct net_device *dev = pci_get_drvdata(pdev);
874a6214 2053 struct b44 *bp = netdev_priv(dev);
1da177e4 2054
874a6214
FR		 2055 unregister_netdev(dev);
2056 iounmap(bp->regs);
2057 free_netdev(dev);
2058 pci_release_regions(pdev);
2059 pci_disable_device(pdev);
2060 pci_set_drvdata(pdev, NULL);
1da177e4
LT		 2061}
2062
2063static int b44_suspend(struct pci_dev *pdev, pm_message_t state)
2064{
2065 struct net_device *dev = pci_get_drvdata(pdev);
2066 struct b44 *bp = netdev_priv(dev);
2067
2068 if (!netif_running(dev))
2069 return 0;
2070
2071 del_timer_sync(&bp->timer);
2072
2073 spin_lock_irq(&bp->lock);
2074
2075 b44_halt(bp);
2076 netif_carrier_off(bp->dev);
2077 netif_device_detach(bp->dev);
2078 b44_free_rings(bp);
2079
2080 spin_unlock_irq(&bp->lock);
46e17853
PM		 2081
2082 free_irq(dev->irq, dev);
d58da590 2083 pci_disable_device(pdev);
1da177e4
LT		 2084 return 0;
2085}
2086
2087static int b44_resume(struct pci_dev *pdev)
2088{
2089 struct net_device *dev = pci_get_drvdata(pdev);
2090 struct b44 *bp = netdev_priv(dev);
2091
2092 pci_restore_state(pdev);
d58da590
DSL		 2093 pci_enable_device(pdev);
2094 pci_set_master(pdev);
1da177e4
LT		 2095
2096 if (!netif_running(dev))
2097 return 0;
2098
46e17853
PM		 2099 if (request_irq(dev->irq, b44_interrupt, SA_SHIRQ, dev->name, dev))
2100 printk(KERN_ERR PFX "%s: request_irq failed\n", dev->name);
2101
1da177e4
LT		 2102 spin_lock_irq(&bp->lock);
2103
2104 b44_init_rings(bp);
2105 b44_init_hw(bp);
2106 netif_device_attach(bp->dev);
2107 spin_unlock_irq(&bp->lock);
2108
2109 bp->timer.expires = jiffies + HZ;
2110 add_timer(&bp->timer);
2111
2112 b44_enable_ints(bp);
2113 return 0;
2114}
2115
2116static struct pci_driver b44_driver = {
2117 .name = DRV_MODULE_NAME,
2118 .id_table = b44_pci_tbl,
2119 .probe = b44_init_one,
2120 .remove = __devexit_p(b44_remove_one),
2121 .suspend = b44_suspend,
2122 .resume = b44_resume,
2123};
2124
2125static int __init b44_init(void)
2126{
9f38c636
JL		 2127 unsigned int dma_desc_align_size = dma_get_cache_alignment();
2128
2129 /* Setup paramaters for syncing RX/TX DMA descriptors */
2130 dma_desc_align_mask = ~(dma_desc_align_size - 1);
2131 dma_desc_sync_size = max(dma_desc_align_size, sizeof(struct dma_desc));
2132
1da177e4
LT		 2133 return pci_module_init(&b44_driver);
2134}
2135
2136static void __exit b44_cleanup(void)
2137{
2138 pci_unregister_driver(&b44_driver);
2139}
2140
2141module_init(b44_init);
2142module_exit(b44_cleanup);
2143
kernel source for telekom puls (alcatel/mediatek)