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Merge branch 'master' into next
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / atl1c / atl1c_main.c
CommitLineData
43250ddd
JY		 1/*
2 * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
3 *
4 * Derived from Intel e1000 driver
5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#include "atl1c.h"
23
8f574b35 24#define ATL1C_DRV_VERSION "1.0.1.0-NAPI"
43250ddd
JY		 25char atl1c_driver_name[] = "atl1c";
26char atl1c_driver_version[] = ATL1C_DRV_VERSION;
27#define PCI_DEVICE_ID_ATTANSIC_L2C 0x1062
28#define PCI_DEVICE_ID_ATTANSIC_L1C 0x1063
496c185c
LR		 29#define PCI_DEVICE_ID_ATHEROS_L2C_B 0x2060 /* AR8152 v1.1 Fast 10/100 */
30#define PCI_DEVICE_ID_ATHEROS_L2C_B2 0x2062 /* AR8152 v2.0 Fast 10/100 */
31#define PCI_DEVICE_ID_ATHEROS_L1D 0x1073 /* AR8151 v1.0 Gigabit 1000 */
8f574b35 32#define PCI_DEVICE_ID_ATHEROS_L1D_2_0 0x1083 /* AR8151 v2.0 Gigabit 1000 */
496c185c
LR		 33#define L2CB_V10 0xc0
34#define L2CB_V11 0xc1
35
43250ddd
JY		 36/*
37 * atl1c_pci_tbl - PCI Device ID Table
38 *
39 * Wildcard entries (PCI_ANY_ID) should come last
40 * Last entry must be all 0s
41 *
42 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
43 * Class, Class Mask, private data (not used) }
44 */
a3aa1884 45static DEFINE_PCI_DEVICE_TABLE(atl1c_pci_tbl) = {
43250ddd
JY		 46 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1C)},
47 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2C)},
496c185c
LR		 48 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L2C_B)},
49 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L2C_B2)},
50 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L1D)},
94dde7e4 51 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L1D_2_0)},
43250ddd
JY		 52 /* required last entry */
53 { 0 }
54};
55MODULE_DEVICE_TABLE(pci, atl1c_pci_tbl);
56
57MODULE_AUTHOR("Jie Yang <jie.yang@atheros.com>");
58MODULE_DESCRIPTION("Atheros 1000M Ethernet Network Driver");
59MODULE_LICENSE("GPL");
60MODULE_VERSION(ATL1C_DRV_VERSION);
61
62static int atl1c_stop_mac(struct atl1c_hw *hw);
63static void atl1c_enable_rx_ctrl(struct atl1c_hw *hw);
64static void atl1c_enable_tx_ctrl(struct atl1c_hw *hw);
65static void atl1c_disable_l0s_l1(struct atl1c_hw *hw);
66static void atl1c_set_aspm(struct atl1c_hw *hw, bool linkup);
67static void atl1c_setup_mac_ctrl(struct atl1c_adapter *adapter);
68static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter, u8 que,
69 int *work_done, int work_to_do);
0fb1e54e 70static int atl1c_up(struct atl1c_adapter *adapter);
71static void atl1c_down(struct atl1c_adapter *adapter);
43250ddd
JY		 72
73static const u16 atl1c_pay_load_size[] = {
74 128, 256, 512, 1024, 2048, 4096,
75};
76
77static const u16 atl1c_rfd_prod_idx_regs[AT_MAX_RECEIVE_QUEUE] =
78{
79 REG_MB_RFD0_PROD_IDX,
80 REG_MB_RFD1_PROD_IDX,
81 REG_MB_RFD2_PROD_IDX,
82 REG_MB_RFD3_PROD_IDX
83};
84
85static const u16 atl1c_rfd_addr_lo_regs[AT_MAX_RECEIVE_QUEUE] =
86{
87 REG_RFD0_HEAD_ADDR_LO,
88 REG_RFD1_HEAD_ADDR_LO,
89 REG_RFD2_HEAD_ADDR_LO,
90 REG_RFD3_HEAD_ADDR_LO
91};
92
93static const u16 atl1c_rrd_addr_lo_regs[AT_MAX_RECEIVE_QUEUE] =
94{
95 REG_RRD0_HEAD_ADDR_LO,
96 REG_RRD1_HEAD_ADDR_LO,
97 REG_RRD2_HEAD_ADDR_LO,
98 REG_RRD3_HEAD_ADDR_LO
99};
100
101static const u32 atl1c_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE |
102 NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP;
8f574b35
JY		 103static void atl1c_pcie_patch(struct atl1c_hw *hw)
104{
105 u32 data;
43250ddd 106
8f574b35
JY		 107 AT_READ_REG(hw, REG_PCIE_PHYMISC, &data);
108 data |= PCIE_PHYMISC_FORCE_RCV_DET;
109 AT_WRITE_REG(hw, REG_PCIE_PHYMISC, data);
110
111 if (hw->nic_type == athr_l2c_b && hw->revision_id == L2CB_V10) {
112 AT_READ_REG(hw, REG_PCIE_PHYMISC2, &data);
113
114 data &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK <<
115 PCIE_PHYMISC2_SERDES_CDR_SHIFT);
116 data |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT;
117 data &= ~(PCIE_PHYMISC2_SERDES_TH_MASK <<
118 PCIE_PHYMISC2_SERDES_TH_SHIFT);
119 data |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT;
120 AT_WRITE_REG(hw, REG_PCIE_PHYMISC2, data);
121 }
122}
123
124/* FIXME: no need any more ? */
43250ddd
JY		 125/*
126 * atl1c_init_pcie - init PCIE module
127 */
128static void atl1c_reset_pcie(struct atl1c_hw *hw, u32 flag)
129{
130 u32 data;
131 u32 pci_cmd;
132 struct pci_dev *pdev = hw->adapter->pdev;
133
134 AT_READ_REG(hw, PCI_COMMAND, &pci_cmd);
135 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
136 pci_cmd |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
137 PCI_COMMAND_IO);
138 AT_WRITE_REG(hw, PCI_COMMAND, pci_cmd);
139
140 /*
141 * Clear any PowerSaveing Settings
142 */
143 pci_enable_wake(pdev, PCI_D3hot, 0);
144 pci_enable_wake(pdev, PCI_D3cold, 0);
145
146 /*
147 * Mask some pcie error bits
148 */
149 AT_READ_REG(hw, REG_PCIE_UC_SEVERITY, &data);
150 data &= ~PCIE_UC_SERVRITY_DLP;
151 data &= ~PCIE_UC_SERVRITY_FCP;
152 AT_WRITE_REG(hw, REG_PCIE_UC_SEVERITY, data);
153
8f574b35
JY		 154 AT_READ_REG(hw, REG_LTSSM_ID_CTRL, &data);
155 data &= ~LTSSM_ID_EN_WRO;
156 AT_WRITE_REG(hw, REG_LTSSM_ID_CTRL, data);
157
158 atl1c_pcie_patch(hw);
43250ddd
JY		 159 if (flag & ATL1C_PCIE_L0S_L1_DISABLE)
160 atl1c_disable_l0s_l1(hw);
161 if (flag & ATL1C_PCIE_PHY_RESET)
162 AT_WRITE_REG(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT);
163 else
164 AT_WRITE_REG(hw, REG_GPHY_CTRL,
165 GPHY_CTRL_DEFAULT | GPHY_CTRL_EXT_RESET);
166
8f574b35 167 msleep(5);
43250ddd
JY		 168}
169
170/*
171 * atl1c_irq_enable - Enable default interrupt generation settings
172 * @adapter: board private structure
173 */
174static inline void atl1c_irq_enable(struct atl1c_adapter *adapter)
175{
176 if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
177 AT_WRITE_REG(&adapter->hw, REG_ISR, 0x7FFFFFFF);
178 AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask);
179 AT_WRITE_FLUSH(&adapter->hw);
180 }
181}
182
183/*
184 * atl1c_irq_disable - Mask off interrupt generation on the NIC
185 * @adapter: board private structure
186 */
187static inline void atl1c_irq_disable(struct atl1c_adapter *adapter)
188{
189 atomic_inc(&adapter->irq_sem);
190 AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
8f574b35 191 AT_WRITE_REG(&adapter->hw, REG_ISR, ISR_DIS_INT);
43250ddd
JY		 192 AT_WRITE_FLUSH(&adapter->hw);
193 synchronize_irq(adapter->pdev->irq);
194}
195
196/*
197 * atl1c_irq_reset - reset interrupt confiure on the NIC
198 * @adapter: board private structure
199 */
200static inline void atl1c_irq_reset(struct atl1c_adapter *adapter)
201{
202 atomic_set(&adapter->irq_sem, 1);
203 atl1c_irq_enable(adapter);
204}
205
c930a662
JP		 206/*
207 * atl1c_wait_until_idle - wait up to AT_HW_MAX_IDLE_DELAY reads
208 * of the idle status register until the device is actually idle
209 */
210static u32 atl1c_wait_until_idle(struct atl1c_hw *hw)
211{
212 int timeout;
213 u32 data;
214
215 for (timeout = 0; timeout < AT_HW_MAX_IDLE_DELAY; timeout++) {
216 AT_READ_REG(hw, REG_IDLE_STATUS, &data);
217 if ((data & IDLE_STATUS_MASK) == 0)
218 return 0;
219 msleep(1);
220 }
221 return data;
222}
223
43250ddd
JY		 224/*
225 * atl1c_phy_config - Timer Call-back
226 * @data: pointer to netdev cast into an unsigned long
227 */
228static void atl1c_phy_config(unsigned long data)
229{
230 struct atl1c_adapter *adapter = (struct atl1c_adapter *) data;
231 struct atl1c_hw *hw = &adapter->hw;
232 unsigned long flags;
233
234 spin_lock_irqsave(&adapter->mdio_lock, flags);
235 atl1c_restart_autoneg(hw);
236 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
237}
238
239void atl1c_reinit_locked(struct atl1c_adapter *adapter)
240{
43250ddd
JY		 241 WARN_ON(in_interrupt());
242 atl1c_down(adapter);
243 atl1c_up(adapter);
244 clear_bit(__AT_RESETTING, &adapter->flags);
245}
246
43250ddd
JY		 247static void atl1c_check_link_status(struct atl1c_adapter *adapter)
248{
249 struct atl1c_hw *hw = &adapter->hw;
250 struct net_device *netdev = adapter->netdev;
251 struct pci_dev *pdev = adapter->pdev;
252 int err;
253 unsigned long flags;
254 u16 speed, duplex, phy_data;
255
256 spin_lock_irqsave(&adapter->mdio_lock, flags);
257 /* MII_BMSR must read twise */
258 atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
259 atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
260 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
261
262 if ((phy_data & BMSR_LSTATUS) == 0) {
263 /* link down */
8f574b35
JY		 264 hw->hibernate = true;
265 if (atl1c_stop_mac(hw) != 0)
266 if (netif_msg_hw(adapter))
267 dev_warn(&pdev->dev, "stop mac failed\n");
268 atl1c_set_aspm(hw, false);
43250ddd 269 netif_carrier_off(netdev);
8f574b35
JY		 270 netif_stop_queue(netdev);
271 atl1c_phy_reset(hw);
272 atl1c_phy_init(&adapter->hw);
43250ddd
JY		 273 } else {
274 /* Link Up */
275 hw->hibernate = false;
276 spin_lock_irqsave(&adapter->mdio_lock, flags);
277 err = atl1c_get_speed_and_duplex(hw, &speed, &duplex);
278 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
279 if (unlikely(err))
280 return;
281 /* link result is our setting */
282 if (adapter->link_speed != speed ||
283 adapter->link_duplex != duplex) {
284 adapter->link_speed = speed;
285 adapter->link_duplex = duplex;
52fbc100 286 atl1c_set_aspm(hw, true);
43250ddd
JY		 287 atl1c_enable_tx_ctrl(hw);
288 atl1c_enable_rx_ctrl(hw);
289 atl1c_setup_mac_ctrl(adapter);
43250ddd
JY		 290 if (netif_msg_link(adapter))
291 dev_info(&pdev->dev,
292 "%s: %s NIC Link is Up<%d Mbps %s>\n",
293 atl1c_driver_name, netdev->name,
294 adapter->link_speed,
295 adapter->link_duplex == FULL_DUPLEX ?
296 "Full Duplex" : "Half Duplex");
297 }
298 if (!netif_carrier_ok(netdev))
299 netif_carrier_on(netdev);
300 }
301}
302
43250ddd
JY		 303static void atl1c_link_chg_event(struct atl1c_adapter *adapter)
304{
305 struct net_device *netdev = adapter->netdev;
306 struct pci_dev *pdev = adapter->pdev;
307 u16 phy_data;
308 u16 link_up;
309
310 spin_lock(&adapter->mdio_lock);
311 atl1c_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
312 atl1c_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
313 spin_unlock(&adapter->mdio_lock);
314 link_up = phy_data & BMSR_LSTATUS;
315 /* notify upper layer link down ASAP */
316 if (!link_up) {
317 if (netif_carrier_ok(netdev)) {
318 /* old link state: Up */
319 netif_carrier_off(netdev);
320 if (netif_msg_link(adapter))
321 dev_info(&pdev->dev,
322 "%s: %s NIC Link is Down\n",
323 atl1c_driver_name, netdev->name);
324 adapter->link_speed = SPEED_0;
325 }
326 }
cb190546 327
cb771838 328 set_bit(ATL1C_WORK_EVENT_LINK_CHANGE, &adapter->work_event);
cb190546 329 schedule_work(&adapter->common_task);
43250ddd
JY		 330}
331
cb190546 332static void atl1c_common_task(struct work_struct *work)
43250ddd 333{
cb190546
JY		 334 struct atl1c_adapter *adapter;
335 struct net_device *netdev;
336
337 adapter = container_of(work, struct atl1c_adapter, common_task);
338 netdev = adapter->netdev;
339
cb771838 340 if (test_and_clear_bit(ATL1C_WORK_EVENT_RESET, &adapter->work_event)) {
cb190546
JY		 341 netif_device_detach(netdev);
342 atl1c_down(adapter);
343 atl1c_up(adapter);
344 netif_device_attach(netdev);
cb190546
JY		 345 }
346
cb771838
TG		 347 if (test_and_clear_bit(ATL1C_WORK_EVENT_LINK_CHANGE,
348 &adapter->work_event))
cb190546 349 atl1c_check_link_status(adapter);
43250ddd
JY		 350}
351
cb190546
JY		 352
353static void atl1c_del_timer(struct atl1c_adapter *adapter)
43250ddd 354{
cb190546 355 del_timer_sync(&adapter->phy_config_timer);
43250ddd
JY		 356}
357
cb190546 358
43250ddd
JY		 359/*
360 * atl1c_tx_timeout - Respond to a Tx Hang
361 * @netdev: network interface device structure
362 */
363static void atl1c_tx_timeout(struct net_device *netdev)
364{
365 struct atl1c_adapter *adapter = netdev_priv(netdev);
366
367 /* Do the reset outside of interrupt context */
cb771838 368 set_bit(ATL1C_WORK_EVENT_RESET, &adapter->work_event);
cb190546 369 schedule_work(&adapter->common_task);
43250ddd
JY		 370}
371
372/*
373 * atl1c_set_multi - Multicast and Promiscuous mode set
374 * @netdev: network interface device structure
375 *
376 * The set_multi entry point is called whenever the multicast address
377 * list or the network interface flags are updated. This routine is
378 * responsible for configuring the hardware for proper multicast,
379 * promiscuous mode, and all-multi behavior.
380 */
381static void atl1c_set_multi(struct net_device *netdev)
382{
383 struct atl1c_adapter *adapter = netdev_priv(netdev);
384 struct atl1c_hw *hw = &adapter->hw;
22bedad3 385 struct netdev_hw_addr *ha;
43250ddd
JY		 386 u32 mac_ctrl_data;
387 u32 hash_value;
388
389 /* Check for Promiscuous and All Multicast modes */
390 AT_READ_REG(hw, REG_MAC_CTRL, &mac_ctrl_data);
391
392 if (netdev->flags & IFF_PROMISC) {
393 mac_ctrl_data |= MAC_CTRL_PROMIS_EN;
394 } else if (netdev->flags & IFF_ALLMULTI) {
395 mac_ctrl_data |= MAC_CTRL_MC_ALL_EN;
396 mac_ctrl_data &= ~MAC_CTRL_PROMIS_EN;
397 } else {
398 mac_ctrl_data &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
399 }
400
401 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
402
403 /* clear the old settings from the multicast hash table */
404 AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
405 AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
406
407 /* comoute mc addresses' hash value ,and put it into hash table */
22bedad3
JP		 408 netdev_for_each_mc_addr(ha, netdev) {
409 hash_value = atl1c_hash_mc_addr(hw, ha->addr);
43250ddd
JY		 410 atl1c_hash_set(hw, hash_value);
411 }
412}
413
414static void atl1c_vlan_rx_register(struct net_device *netdev,
415 struct vlan_group *grp)
416{
417 struct atl1c_adapter *adapter = netdev_priv(netdev);
418 struct pci_dev *pdev = adapter->pdev;
419 u32 mac_ctrl_data = 0;
420
421 if (netif_msg_pktdata(adapter))
422 dev_dbg(&pdev->dev, "atl1c_vlan_rx_register\n");
423
424 atl1c_irq_disable(adapter);
425
426 adapter->vlgrp = grp;
427 AT_READ_REG(&adapter->hw, REG_MAC_CTRL, &mac_ctrl_data);
428
429 if (grp) {
430 /* enable VLAN tag insert/strip */
431 mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
432 } else {
433 /* disable VLAN tag insert/strip */
434 mac_ctrl_data &= ~MAC_CTRL_RMV_VLAN;
435 }
436
437 AT_WRITE_REG(&adapter->hw, REG_MAC_CTRL, mac_ctrl_data);
438 atl1c_irq_enable(adapter);
439}
440
441static void atl1c_restore_vlan(struct atl1c_adapter *adapter)
442{
443 struct pci_dev *pdev = adapter->pdev;
444
445 if (netif_msg_pktdata(adapter))
446 dev_dbg(&pdev->dev, "atl1c_restore_vlan !");
447 atl1c_vlan_rx_register(adapter->netdev, adapter->vlgrp);
448}
449/*
450 * atl1c_set_mac - Change the Ethernet Address of the NIC
451 * @netdev: network interface device structure
452 * @p: pointer to an address structure
453 *
454 * Returns 0 on success, negative on failure
455 */
456static int atl1c_set_mac_addr(struct net_device *netdev, void *p)
457{
458 struct atl1c_adapter *adapter = netdev_priv(netdev);
459 struct sockaddr *addr = p;
460
461 if (!is_valid_ether_addr(addr->sa_data))
462 return -EADDRNOTAVAIL;
463
464 if (netif_running(netdev))
465 return -EBUSY;
466
467 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
468 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
469
470 atl1c_hw_set_mac_addr(&adapter->hw);
471
472 return 0;
473}
474
475static void atl1c_set_rxbufsize(struct atl1c_adapter *adapter,
476 struct net_device *dev)
477{
478 int mtu = dev->mtu;
479
480 adapter->rx_buffer_len = mtu > AT_RX_BUF_SIZE ?
481 roundup(mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN, 8) : AT_RX_BUF_SIZE;
482}
483/*
484 * atl1c_change_mtu - Change the Maximum Transfer Unit
485 * @netdev: network interface device structure
486 * @new_mtu: new value for maximum frame size
487 *
488 * Returns 0 on success, negative on failure
489 */
490static int atl1c_change_mtu(struct net_device *netdev, int new_mtu)
491{
492 struct atl1c_adapter *adapter = netdev_priv(netdev);
493 int old_mtu = netdev->mtu;
494 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
495
496 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
497 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
498 if (netif_msg_link(adapter))
499 dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
500 return -EINVAL;
501 }
502 /* set MTU */
503 if (old_mtu != new_mtu && netif_running(netdev)) {
504 while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
505 msleep(1);
506 netdev->mtu = new_mtu;
507 adapter->hw.max_frame_size = new_mtu;
508 atl1c_set_rxbufsize(adapter, netdev);
8f574b35
JY		 509 if (new_mtu > MAX_TSO_FRAME_SIZE) {
510 adapter->netdev->features &= ~NETIF_F_TSO;
511 adapter->netdev->features &= ~NETIF_F_TSO6;
512 } else {
513 adapter->netdev->features |= NETIF_F_TSO;
514 adapter->netdev->features |= NETIF_F_TSO6;
515 }
43250ddd
JY		 516 atl1c_down(adapter);
517 atl1c_up(adapter);
518 clear_bit(__AT_RESETTING, &adapter->flags);
519 if (adapter->hw.ctrl_flags & ATL1C_FPGA_VERSION) {
520 u32 phy_data;
521
522 AT_READ_REG(&adapter->hw, 0x1414, &phy_data);
523 phy_data |= 0x10000000;
524 AT_WRITE_REG(&adapter->hw, 0x1414, phy_data);
525 }
526
527 }
528 return 0;
529}
530
531/*
532 * caller should hold mdio_lock
533 */
534static int atl1c_mdio_read(struct net_device *netdev, int phy_id, int reg_num)
535{
536 struct atl1c_adapter *adapter = netdev_priv(netdev);
537 u16 result;
538
539 atl1c_read_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, &result);
540 return result;
541}
542
543static void atl1c_mdio_write(struct net_device *netdev, int phy_id,
544 int reg_num, int val)
545{
546 struct atl1c_adapter *adapter = netdev_priv(netdev);
547
548 atl1c_write_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, val);
549}
550
551/*
552 * atl1c_mii_ioctl -
553 * @netdev:
554 * @ifreq:
555 * @cmd:
556 */
557static int atl1c_mii_ioctl(struct net_device *netdev,
558 struct ifreq *ifr, int cmd)
559{
560 struct atl1c_adapter *adapter = netdev_priv(netdev);
561 struct pci_dev *pdev = adapter->pdev;
562 struct mii_ioctl_data *data = if_mii(ifr);
563 unsigned long flags;
564 int retval = 0;
565
566 if (!netif_running(netdev))
567 return -EINVAL;
568
569 spin_lock_irqsave(&adapter->mdio_lock, flags);
570 switch (cmd) {
571 case SIOCGMIIPHY:
572 data->phy_id = 0;
573 break;
574
575 case SIOCGMIIREG:
43250ddd
JY		 576 if (atl1c_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
577 &data->val_out)) {
578 retval = -EIO;
579 goto out;
580 }
581 break;
582
583 case SIOCSMIIREG:
43250ddd
JY		 584 if (data->reg_num & ~(0x1F)) {
585 retval = -EFAULT;
586 goto out;
587 }
588
589 dev_dbg(&pdev->dev, "<atl1c_mii_ioctl> write %x %x",
590 data->reg_num, data->val_in);
591 if (atl1c_write_phy_reg(&adapter->hw,
592 data->reg_num, data->val_in)) {
593 retval = -EIO;
594 goto out;
595 }
596 break;
597
598 default:
599 retval = -EOPNOTSUPP;
600 break;
601 }
602out:
603 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
604 return retval;
605}
606
607/*
608 * atl1c_ioctl -
609 * @netdev:
610 * @ifreq:
611 * @cmd:
612 */
613static int atl1c_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
614{
615 switch (cmd) {
616 case SIOCGMIIPHY:
617 case SIOCGMIIREG:
618 case SIOCSMIIREG:
619 return atl1c_mii_ioctl(netdev, ifr, cmd);
620 default:
621 return -EOPNOTSUPP;
622 }
623}
624
625/*
626 * atl1c_alloc_queues - Allocate memory for all rings
627 * @adapter: board private structure to initialize
628 *
629 */
630static int __devinit atl1c_alloc_queues(struct atl1c_adapter *adapter)
631{
632 return 0;
633}
634
635static void atl1c_set_mac_type(struct atl1c_hw *hw)
636{
637 switch (hw->device_id) {
638 case PCI_DEVICE_ID_ATTANSIC_L2C:
639 hw->nic_type = athr_l2c;
640 break;
43250ddd
JY		 641 case PCI_DEVICE_ID_ATTANSIC_L1C:
642 hw->nic_type = athr_l1c;
643 break;
496c185c
LR		 644 case PCI_DEVICE_ID_ATHEROS_L2C_B:
645 hw->nic_type = athr_l2c_b;
646 break;
647 case PCI_DEVICE_ID_ATHEROS_L2C_B2:
648 hw->nic_type = athr_l2c_b2;
649 break;
650 case PCI_DEVICE_ID_ATHEROS_L1D:
651 hw->nic_type = athr_l1d;
652 break;
8f574b35
JY		 653 case PCI_DEVICE_ID_ATHEROS_L1D_2_0:
654 hw->nic_type = athr_l1d_2;
655 break;
43250ddd
JY		 656 default:
657 break;
658 }
659}
660
661static int atl1c_setup_mac_funcs(struct atl1c_hw *hw)
662{
663 u32 phy_status_data;
664 u32 link_ctrl_data;
665
666 atl1c_set_mac_type(hw);
667 AT_READ_REG(hw, REG_PHY_STATUS, &phy_status_data);
668 AT_READ_REG(hw, REG_LINK_CTRL, &link_ctrl_data);
669
8f574b35 670 hw->ctrl_flags = ATL1C_INTR_MODRT_ENABLE |
43250ddd
JY		 671 ATL1C_TXQ_MODE_ENHANCE;
672 if (link_ctrl_data & LINK_CTRL_L0S_EN)
673 hw->ctrl_flags |= ATL1C_ASPM_L0S_SUPPORT;
674 if (link_ctrl_data & LINK_CTRL_L1_EN)
675 hw->ctrl_flags |= ATL1C_ASPM_L1_SUPPORT;
496c185c
LR		 676 if (link_ctrl_data & LINK_CTRL_EXT_SYNC)
677 hw->ctrl_flags |= ATL1C_LINK_EXT_SYNC;
8f574b35 678 hw->ctrl_flags |= ATL1C_ASPM_CTRL_MON;
43250ddd 679
496c185c 680 if (hw->nic_type == athr_l1c ||
8f574b35
JY		 681 hw->nic_type == athr_l1d ||
682 hw->nic_type == athr_l1d_2)
496c185c 683 hw->link_cap_flags |= ATL1C_LINK_CAP_1000M;
43250ddd
JY		 684 return 0;
685}
686/*
687 * atl1c_sw_init - Initialize general software structures (struct atl1c_adapter)
688 * @adapter: board private structure to initialize
689 *
690 * atl1c_sw_init initializes the Adapter private data structure.
691 * Fields are initialized based on PCI device information and
692 * OS network device settings (MTU size).
693 */
694static int __devinit atl1c_sw_init(struct atl1c_adapter *adapter)
695{
696 struct atl1c_hw *hw = &adapter->hw;
697 struct pci_dev *pdev = adapter->pdev;
8f574b35
JY		 698 u32 revision;
699
43250ddd
JY		 700
701 adapter->wol = 0;
762e3023 702 device_set_wakeup_enable(&pdev->dev, false);
43250ddd
JY		 703 adapter->link_speed = SPEED_0;
704 adapter->link_duplex = FULL_DUPLEX;
705 adapter->num_rx_queues = AT_DEF_RECEIVE_QUEUE;
706 adapter->tpd_ring[0].count = 1024;
707 adapter->rfd_ring[0].count = 512;
708
709 hw->vendor_id = pdev->vendor;
710 hw->device_id = pdev->device;
711 hw->subsystem_vendor_id = pdev->subsystem_vendor;
712 hw->subsystem_id = pdev->subsystem_device;
8f574b35
JY		 713 AT_READ_REG(hw, PCI_CLASS_REVISION, &revision);
714 hw->revision_id = revision & 0xFF;
43250ddd
JY		 715 /* before link up, we assume hibernate is true */
716 hw->hibernate = true;
717 hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
718 if (atl1c_setup_mac_funcs(hw) != 0) {
719 dev_err(&pdev->dev, "set mac function pointers failed\n");
720 return -1;
721 }
722 hw->intr_mask = IMR_NORMAL_MASK;
723 hw->phy_configured = false;
724 hw->preamble_len = 7;
725 hw->max_frame_size = adapter->netdev->mtu;
726 if (adapter->num_rx_queues < 2) {
727 hw->rss_type = atl1c_rss_disable;
728 hw->rss_mode = atl1c_rss_mode_disable;
729 } else {
730 hw->rss_type = atl1c_rss_ipv4;
731 hw->rss_mode = atl1c_rss_mul_que_mul_int;
732 hw->rss_hash_bits = 16;
733 }
734 hw->autoneg_advertised = ADVERTISED_Autoneg;
735 hw->indirect_tab = 0xE4E4E4E4;
736 hw->base_cpu = 0;
737
738 hw->ict = 50000; /* 100ms */
739 hw->smb_timer = 200000; /* 400ms */
740 hw->cmb_tpd = 4;
741 hw->cmb_tx_timer = 1; /* 2 us */
742 hw->rx_imt = 200;
743 hw->tx_imt = 1000;
744
745 hw->tpd_burst = 5;
746 hw->rfd_burst = 8;
747 hw->dma_order = atl1c_dma_ord_out;
748 hw->dmar_block = atl1c_dma_req_1024;
749 hw->dmaw_block = atl1c_dma_req_1024;
750 hw->dmar_dly_cnt = 15;
751 hw->dmaw_dly_cnt = 4;
752
753 if (atl1c_alloc_queues(adapter)) {
754 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
755 return -ENOMEM;
756 }
757 /* TODO */
758 atl1c_set_rxbufsize(adapter, adapter->netdev);
759 atomic_set(&adapter->irq_sem, 1);
760 spin_lock_init(&adapter->mdio_lock);
761 spin_lock_init(&adapter->tx_lock);
762 set_bit(__AT_DOWN, &adapter->flags);
763
764 return 0;
765}
766
c6060be4
JY		 767static inline void atl1c_clean_buffer(struct pci_dev *pdev,
768 struct atl1c_buffer *buffer_info, int in_irq)
769{
4b45e342 770 u16 pci_driection;
c6060be4
JY		 771 if (buffer_info->flags & ATL1C_BUFFER_FREE)
772 return;
773 if (buffer_info->dma) {
4b45e342
JY		 774 if (buffer_info->flags & ATL1C_PCIMAP_FROMDEVICE)
775 pci_driection = PCI_DMA_FROMDEVICE;
776 else
777 pci_driection = PCI_DMA_TODEVICE;
778
c6060be4
JY		 779 if (buffer_info->flags & ATL1C_PCIMAP_SINGLE)
780 pci_unmap_single(pdev, buffer_info->dma,
4b45e342 781 buffer_info->length, pci_driection);
c6060be4
JY		 782 else if (buffer_info->flags & ATL1C_PCIMAP_PAGE)
783 pci_unmap_page(pdev, buffer_info->dma,
4b45e342 784 buffer_info->length, pci_driection);
c6060be4
JY		 785 }
786 if (buffer_info->skb) {
787 if (in_irq)
788 dev_kfree_skb_irq(buffer_info->skb);
789 else
790 dev_kfree_skb(buffer_info->skb);
791 }
792 buffer_info->dma = 0;
793 buffer_info->skb = NULL;
794 ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_FREE);
795}
43250ddd
JY		 796/*
797 * atl1c_clean_tx_ring - Free Tx-skb
798 * @adapter: board private structure
799 */
800static void atl1c_clean_tx_ring(struct atl1c_adapter *adapter,
801 enum atl1c_trans_queue type)
802{
803 struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
804 struct atl1c_buffer *buffer_info;
805 struct pci_dev *pdev = adapter->pdev;
806 u16 index, ring_count;
807
808 ring_count = tpd_ring->count;
809 for (index = 0; index < ring_count; index++) {
810 buffer_info = &tpd_ring->buffer_info[index];
c6060be4 811 atl1c_clean_buffer(pdev, buffer_info, 0);
43250ddd
JY		 812 }
813
814 /* Zero out Tx-buffers */
815 memset(tpd_ring->desc, 0, sizeof(struct atl1c_tpd_desc) *
c6060be4 816 ring_count);
43250ddd
JY		 817 atomic_set(&tpd_ring->next_to_clean, 0);
818 tpd_ring->next_to_use = 0;
819}
820
821/*
822 * atl1c_clean_rx_ring - Free rx-reservation skbs
823 * @adapter: board private structure
824 */
825static void atl1c_clean_rx_ring(struct atl1c_adapter *adapter)
826{
827 struct atl1c_rfd_ring *rfd_ring = adapter->rfd_ring;
828 struct atl1c_rrd_ring *rrd_ring = adapter->rrd_ring;
829 struct atl1c_buffer *buffer_info;
830 struct pci_dev *pdev = adapter->pdev;
831 int i, j;
832
833 for (i = 0; i < adapter->num_rx_queues; i++) {
834 for (j = 0; j < rfd_ring[i].count; j++) {
835 buffer_info = &rfd_ring[i].buffer_info[j];
c6060be4 836 atl1c_clean_buffer(pdev, buffer_info, 0);
43250ddd
JY		 837 }
838 /* zero out the descriptor ring */
839 memset(rfd_ring[i].desc, 0, rfd_ring[i].size);
840 rfd_ring[i].next_to_clean = 0;
841 rfd_ring[i].next_to_use = 0;
842 rrd_ring[i].next_to_use = 0;
843 rrd_ring[i].next_to_clean = 0;
844 }
845}
846
847/*
848 * Read / Write Ptr Initialize:
849 */
850static void atl1c_init_ring_ptrs(struct atl1c_adapter *adapter)
851{
852 struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
853 struct atl1c_rfd_ring *rfd_ring = adapter->rfd_ring;
854 struct atl1c_rrd_ring *rrd_ring = adapter->rrd_ring;
855 struct atl1c_buffer *buffer_info;
856 int i, j;
857
858 for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
859 tpd_ring[i].next_to_use = 0;
860 atomic_set(&tpd_ring[i].next_to_clean, 0);
861 buffer_info = tpd_ring[i].buffer_info;
862 for (j = 0; j < tpd_ring->count; j++)
c6060be4
JY		 863 ATL1C_SET_BUFFER_STATE(&buffer_info[i],
864 ATL1C_BUFFER_FREE);
43250ddd
JY		 865 }
866 for (i = 0; i < adapter->num_rx_queues; i++) {
867 rfd_ring[i].next_to_use = 0;
868 rfd_ring[i].next_to_clean = 0;
869 rrd_ring[i].next_to_use = 0;
870 rrd_ring[i].next_to_clean = 0;
871 for (j = 0; j < rfd_ring[i].count; j++) {
872 buffer_info = &rfd_ring[i].buffer_info[j];
c6060be4 873 ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_FREE);
43250ddd
JY		 874 }
875 }
876}
877
878/*
879 * atl1c_free_ring_resources - Free Tx / RX descriptor Resources
880 * @adapter: board private structure
881 *
882 * Free all transmit software resources
883 */
884static void atl1c_free_ring_resources(struct atl1c_adapter *adapter)
885{
886 struct pci_dev *pdev = adapter->pdev;
887
888 pci_free_consistent(pdev, adapter->ring_header.size,
889 adapter->ring_header.desc,
890 adapter->ring_header.dma);
891 adapter->ring_header.desc = NULL;
892
893 /* Note: just free tdp_ring.buffer_info,
894 * it contain rfd_ring.buffer_info, do not double free */
895 if (adapter->tpd_ring[0].buffer_info) {
896 kfree(adapter->tpd_ring[0].buffer_info);
897 adapter->tpd_ring[0].buffer_info = NULL;
898 }
899}
900
901/*
902 * atl1c_setup_mem_resources - allocate Tx / RX descriptor resources
903 * @adapter: board private structure
904 *
905 * Return 0 on success, negative on failure
906 */
907static int atl1c_setup_ring_resources(struct atl1c_adapter *adapter)
908{
909 struct pci_dev *pdev = adapter->pdev;
910 struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
911 struct atl1c_rfd_ring *rfd_ring = adapter->rfd_ring;
912 struct atl1c_rrd_ring *rrd_ring = adapter->rrd_ring;
913 struct atl1c_ring_header *ring_header = &adapter->ring_header;
914 int num_rx_queues = adapter->num_rx_queues;
915 int size;
916 int i;
917 int count = 0;
918 int rx_desc_count = 0;
919 u32 offset = 0;
920
921 rrd_ring[0].count = rfd_ring[0].count;
922 for (i = 1; i < AT_MAX_TRANSMIT_QUEUE; i++)
923 tpd_ring[i].count = tpd_ring[0].count;
924
925 for (i = 1; i < adapter->num_rx_queues; i++)
926 rfd_ring[i].count = rrd_ring[i].count = rfd_ring[0].count;
927
928 /* 2 tpd queue, one high priority queue,
929 * another normal priority queue */
930 size = sizeof(struct atl1c_buffer) * (tpd_ring->count * 2 +
931 rfd_ring->count * num_rx_queues);
932 tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL);
933 if (unlikely(!tpd_ring->buffer_info)) {
934 dev_err(&pdev->dev, "kzalloc failed, size = %d\n",
935 size);
936 goto err_nomem;
937 }
938 for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
939 tpd_ring[i].buffer_info =
940 (struct atl1c_buffer *) (tpd_ring->buffer_info + count);
941 count += tpd_ring[i].count;
942 }
943
944 for (i = 0; i < num_rx_queues; i++) {
945 rfd_ring[i].buffer_info =
946 (struct atl1c_buffer *) (tpd_ring->buffer_info + count);
947 count += rfd_ring[i].count;
948 rx_desc_count += rfd_ring[i].count;
949 }
950 /*
951 * real ring DMA buffer
952 * each ring/block may need up to 8 bytes for alignment, hence the
953 * additional bytes tacked onto the end.
954 */
955 ring_header->size = size =
956 sizeof(struct atl1c_tpd_desc) * tpd_ring->count * 2 +
957 sizeof(struct atl1c_rx_free_desc) * rx_desc_count +
958 sizeof(struct atl1c_recv_ret_status) * rx_desc_count +
959 sizeof(struct atl1c_hw_stats) +
960 8 * 4 + 8 * 2 * num_rx_queues;
961
962 ring_header->desc = pci_alloc_consistent(pdev, ring_header->size,
963 &ring_header->dma);
964 if (unlikely(!ring_header->desc)) {
965 dev_err(&pdev->dev, "pci_alloc_consistend failed\n");
966 goto err_nomem;
967 }
968 memset(ring_header->desc, 0, ring_header->size);
969 /* init TPD ring */
970
971 tpd_ring[0].dma = roundup(ring_header->dma, 8);
972 offset = tpd_ring[0].dma - ring_header->dma;
973 for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
974 tpd_ring[i].dma = ring_header->dma + offset;
975 tpd_ring[i].desc = (u8 *) ring_header->desc + offset;
976 tpd_ring[i].size =
977 sizeof(struct atl1c_tpd_desc) * tpd_ring[i].count;
978 offset += roundup(tpd_ring[i].size, 8);
979 }
980 /* init RFD ring */
981 for (i = 0; i < num_rx_queues; i++) {
982 rfd_ring[i].dma = ring_header->dma + offset;
983 rfd_ring[i].desc = (u8 *) ring_header->desc + offset;
984 rfd_ring[i].size = sizeof(struct atl1c_rx_free_desc) *
985 rfd_ring[i].count;
986 offset += roundup(rfd_ring[i].size, 8);
987 }
988
989 /* init RRD ring */
990 for (i = 0; i < num_rx_queues; i++) {
991 rrd_ring[i].dma = ring_header->dma + offset;
992 rrd_ring[i].desc = (u8 *) ring_header->desc + offset;
993 rrd_ring[i].size = sizeof(struct atl1c_recv_ret_status) *
994 rrd_ring[i].count;
995 offset += roundup(rrd_ring[i].size, 8);
996 }
997
998 adapter->smb.dma = ring_header->dma + offset;
999 adapter->smb.smb = (u8 *)ring_header->desc + offset;
1000 return 0;
1001
1002err_nomem:
1003 kfree(tpd_ring->buffer_info);
1004 return -ENOMEM;
1005}
1006
1007static void atl1c_configure_des_ring(struct atl1c_adapter *adapter)
1008{
1009 struct atl1c_hw *hw = &adapter->hw;
1010 struct atl1c_rfd_ring *rfd_ring = (struct atl1c_rfd_ring *)
1011 adapter->rfd_ring;
1012 struct atl1c_rrd_ring *rrd_ring = (struct atl1c_rrd_ring *)
1013 adapter->rrd_ring;
1014 struct atl1c_tpd_ring *tpd_ring = (struct atl1c_tpd_ring *)
1015 adapter->tpd_ring;
1016 struct atl1c_cmb *cmb = (struct atl1c_cmb *) &adapter->cmb;
1017 struct atl1c_smb *smb = (struct atl1c_smb *) &adapter->smb;
1018 int i;
8f574b35 1019 u32 data;
43250ddd
JY		 1020
1021 /* TPD */
1022 AT_WRITE_REG(hw, REG_TX_BASE_ADDR_HI,
1023 (u32)((tpd_ring[atl1c_trans_normal].dma &
1024 AT_DMA_HI_ADDR_MASK) >> 32));
1025 /* just enable normal priority TX queue */
1026 AT_WRITE_REG(hw, REG_NTPD_HEAD_ADDR_LO,
1027 (u32)(tpd_ring[atl1c_trans_normal].dma &
1028 AT_DMA_LO_ADDR_MASK));
1029 AT_WRITE_REG(hw, REG_HTPD_HEAD_ADDR_LO,
1030 (u32)(tpd_ring[atl1c_trans_high].dma &
1031 AT_DMA_LO_ADDR_MASK));
1032 AT_WRITE_REG(hw, REG_TPD_RING_SIZE,
1033 (u32)(tpd_ring[0].count & TPD_RING_SIZE_MASK));
1034
1035
1036 /* RFD */
1037 AT_WRITE_REG(hw, REG_RX_BASE_ADDR_HI,
1038 (u32)((rfd_ring[0].dma & AT_DMA_HI_ADDR_MASK) >> 32));
1039 for (i = 0; i < adapter->num_rx_queues; i++)
1040 AT_WRITE_REG(hw, atl1c_rfd_addr_lo_regs[i],
1041 (u32)(rfd_ring[i].dma & AT_DMA_LO_ADDR_MASK));
1042
1043 AT_WRITE_REG(hw, REG_RFD_RING_SIZE,
1044 rfd_ring[0].count & RFD_RING_SIZE_MASK);
1045 AT_WRITE_REG(hw, REG_RX_BUF_SIZE,
1046 adapter->rx_buffer_len & RX_BUF_SIZE_MASK);
1047
1048 /* RRD */
1049 for (i = 0; i < adapter->num_rx_queues; i++)
1050 AT_WRITE_REG(hw, atl1c_rrd_addr_lo_regs[i],
1051 (u32)(rrd_ring[i].dma & AT_DMA_LO_ADDR_MASK));
1052 AT_WRITE_REG(hw, REG_RRD_RING_SIZE,
1053 (rrd_ring[0].count & RRD_RING_SIZE_MASK));
1054
1055 /* CMB */
1056 AT_WRITE_REG(hw, REG_CMB_BASE_ADDR_LO, cmb->dma & AT_DMA_LO_ADDR_MASK);
1057
1058 /* SMB */
1059 AT_WRITE_REG(hw, REG_SMB_BASE_ADDR_HI,
1060 (u32)((smb->dma & AT_DMA_HI_ADDR_MASK) >> 32));
1061 AT_WRITE_REG(hw, REG_SMB_BASE_ADDR_LO,
1062 (u32)(smb->dma & AT_DMA_LO_ADDR_MASK));
8f574b35
JY		 1063 if (hw->nic_type == athr_l2c_b) {
1064 AT_WRITE_REG(hw, REG_SRAM_RXF_LEN, 0x02a0L);
1065 AT_WRITE_REG(hw, REG_SRAM_TXF_LEN, 0x0100L);
1066 AT_WRITE_REG(hw, REG_SRAM_RXF_ADDR, 0x029f0000L);
1067 AT_WRITE_REG(hw, REG_SRAM_RFD0_INFO, 0x02bf02a0L);
1068 AT_WRITE_REG(hw, REG_SRAM_TXF_ADDR, 0x03bf02c0L);
1069 AT_WRITE_REG(hw, REG_SRAM_TRD_ADDR, 0x03df03c0L);
1070 AT_WRITE_REG(hw, REG_TXF_WATER_MARK, 0); /* TX watermark, to enter l1 state.*/
1071 AT_WRITE_REG(hw, REG_RXD_DMA_CTRL, 0); /* RXD threshold.*/
1072 }
1073 if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d_2) {
1074 /* Power Saving for L2c_B */
1075 AT_READ_REG(hw, REG_SERDES_LOCK, &data);
1076 data |= SERDES_MAC_CLK_SLOWDOWN;
1077 data |= SERDES_PYH_CLK_SLOWDOWN;
1078 AT_WRITE_REG(hw, REG_SERDES_LOCK, data);
1079 }
43250ddd
JY		 1080 /* Load all of base address above */
1081 AT_WRITE_REG(hw, REG_LOAD_PTR, 1);
1082}
1083
1084static void atl1c_configure_tx(struct atl1c_adapter *adapter)
1085{
1086 struct atl1c_hw *hw = &adapter->hw;
1087 u32 dev_ctrl_data;
1088 u32 max_pay_load;
1089 u16 tx_offload_thresh;
1090 u32 txq_ctrl_data;
1091 u32 extra_size = 0; /* Jumbo frame threshold in QWORD unit */
8f574b35 1092 u32 max_pay_load_data;
43250ddd
JY		 1093
1094 extra_size = ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN;
1095 tx_offload_thresh = MAX_TX_OFFLOAD_THRESH;
1096 AT_WRITE_REG(hw, REG_TX_TSO_OFFLOAD_THRESH,
1097 (tx_offload_thresh >> 3) & TX_TSO_OFFLOAD_THRESH_MASK);
1098 AT_READ_REG(hw, REG_DEVICE_CTRL, &dev_ctrl_data);
1099 max_pay_load = (dev_ctrl_data >> DEVICE_CTRL_MAX_PAYLOAD_SHIFT) &
1100 DEVICE_CTRL_MAX_PAYLOAD_MASK;
81b504b8 1101 hw->dmaw_block = min_t(u32, max_pay_load, hw->dmaw_block);
43250ddd
JY		 1102 max_pay_load = (dev_ctrl_data >> DEVICE_CTRL_MAX_RREQ_SZ_SHIFT) &
1103 DEVICE_CTRL_MAX_RREQ_SZ_MASK;
81b504b8 1104 hw->dmar_block = min_t(u32, max_pay_load, hw->dmar_block);
43250ddd
JY		 1105
1106 txq_ctrl_data = (hw->tpd_burst & TXQ_NUM_TPD_BURST_MASK) <<
1107 TXQ_NUM_TPD_BURST_SHIFT;
1108 if (hw->ctrl_flags & ATL1C_TXQ_MODE_ENHANCE)
1109 txq_ctrl_data |= TXQ_CTRL_ENH_MODE;
8f574b35 1110 max_pay_load_data = (atl1c_pay_load_size[hw->dmar_block] &
43250ddd 1111 TXQ_TXF_BURST_NUM_MASK) << TXQ_TXF_BURST_NUM_SHIFT;
8f574b35
JY		 1112 if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2)
1113 max_pay_load_data >>= 1;
1114 txq_ctrl_data |= max_pay_load_data;
43250ddd
JY		 1115
1116 AT_WRITE_REG(hw, REG_TXQ_CTRL, txq_ctrl_data);
1117}
1118
1119static void atl1c_configure_rx(struct atl1c_adapter *adapter)
1120{
1121 struct atl1c_hw *hw = &adapter->hw;
1122 u32 rxq_ctrl_data;
1123
1124 rxq_ctrl_data = (hw->rfd_burst & RXQ_RFD_BURST_NUM_MASK) <<
1125 RXQ_RFD_BURST_NUM_SHIFT;
1126
1127 if (hw->ctrl_flags & ATL1C_RX_IPV6_CHKSUM)
1128 rxq_ctrl_data |= IPV6_CHKSUM_CTRL_EN;
1129 if (hw->rss_type == atl1c_rss_ipv4)
1130 rxq_ctrl_data |= RSS_HASH_IPV4;
1131 if (hw->rss_type == atl1c_rss_ipv4_tcp)
1132 rxq_ctrl_data |= RSS_HASH_IPV4_TCP;
1133 if (hw->rss_type == atl1c_rss_ipv6)
1134 rxq_ctrl_data |= RSS_HASH_IPV6;
1135 if (hw->rss_type == atl1c_rss_ipv6_tcp)
1136 rxq_ctrl_data |= RSS_HASH_IPV6_TCP;
1137 if (hw->rss_type != atl1c_rss_disable)
1138 rxq_ctrl_data |= RRS_HASH_CTRL_EN;
1139
1140 rxq_ctrl_data |= (hw->rss_mode & RSS_MODE_MASK) <<
1141 RSS_MODE_SHIFT;
1142 rxq_ctrl_data |= (hw->rss_hash_bits & RSS_HASH_BITS_MASK) <<
1143 RSS_HASH_BITS_SHIFT;
1144 if (hw->ctrl_flags & ATL1C_ASPM_CTRL_MON)
8f574b35 1145 rxq_ctrl_data |= (ASPM_THRUPUT_LIMIT_1M &
43250ddd
JY		 1146 ASPM_THRUPUT_LIMIT_MASK) << ASPM_THRUPUT_LIMIT_SHIFT;
1147
1148 AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq_ctrl_data);
1149}
1150
1151static void atl1c_configure_rss(struct atl1c_adapter *adapter)
1152{
1153 struct atl1c_hw *hw = &adapter->hw;
1154
1155 AT_WRITE_REG(hw, REG_IDT_TABLE, hw->indirect_tab);
1156 AT_WRITE_REG(hw, REG_BASE_CPU_NUMBER, hw->base_cpu);
1157}
1158
1159static void atl1c_configure_dma(struct atl1c_adapter *adapter)
1160{
1161 struct atl1c_hw *hw = &adapter->hw;
1162 u32 dma_ctrl_data;
1163
1164 dma_ctrl_data = DMA_CTRL_DMAR_REQ_PRI;
1165 if (hw->ctrl_flags & ATL1C_CMB_ENABLE)
1166 dma_ctrl_data |= DMA_CTRL_CMB_EN;
1167 if (hw->ctrl_flags & ATL1C_SMB_ENABLE)
1168 dma_ctrl_data |= DMA_CTRL_SMB_EN;
1169 else
1170 dma_ctrl_data |= MAC_CTRL_SMB_DIS;
1171
1172 switch (hw->dma_order) {
1173 case atl1c_dma_ord_in:
1174 dma_ctrl_data |= DMA_CTRL_DMAR_IN_ORDER;
1175 break;
1176 case atl1c_dma_ord_enh:
1177 dma_ctrl_data |= DMA_CTRL_DMAR_ENH_ORDER;
1178 break;
1179 case atl1c_dma_ord_out:
1180 dma_ctrl_data |= DMA_CTRL_DMAR_OUT_ORDER;
1181 break;
1182 default:
1183 break;
1184 }
1185
1186 dma_ctrl_data |= (((u32)hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
1187 << DMA_CTRL_DMAR_BURST_LEN_SHIFT;
1188 dma_ctrl_data |= (((u32)hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK)
1189 << DMA_CTRL_DMAW_BURST_LEN_SHIFT;
1190 dma_ctrl_data |= (((u32)hw->dmar_dly_cnt) & DMA_CTRL_DMAR_DLY_CNT_MASK)
1191 << DMA_CTRL_DMAR_DLY_CNT_SHIFT;
1192 dma_ctrl_data |= (((u32)hw->dmaw_dly_cnt) & DMA_CTRL_DMAW_DLY_CNT_MASK)
1193 << DMA_CTRL_DMAW_DLY_CNT_SHIFT;
1194
1195 AT_WRITE_REG(hw, REG_DMA_CTRL, dma_ctrl_data);
1196}
1197
1198/*
1199 * Stop the mac, transmit and receive units
1200 * hw - Struct containing variables accessed by shared code
1201 * return : 0 or idle status (if error)
1202 */
1203static int atl1c_stop_mac(struct atl1c_hw *hw)
1204{
1205 u32 data;
43250ddd
JY		 1206
1207 AT_READ_REG(hw, REG_RXQ_CTRL, &data);
1208 data &= ~(RXQ1_CTRL_EN | RXQ2_CTRL_EN |
1209 RXQ3_CTRL_EN | RXQ_CTRL_EN);
1210 AT_WRITE_REG(hw, REG_RXQ_CTRL, data);
1211
1212 AT_READ_REG(hw, REG_TXQ_CTRL, &data);
1213 data &= ~TXQ_CTRL_EN;
1214 AT_WRITE_REG(hw, REG_TWSI_CTRL, data);
1215
c930a662 1216 atl1c_wait_until_idle(hw);
43250ddd
JY		 1217
1218 AT_READ_REG(hw, REG_MAC_CTRL, &data);
1219 data &= ~(MAC_CTRL_TX_EN | MAC_CTRL_RX_EN);
1220 AT_WRITE_REG(hw, REG_MAC_CTRL, data);
1221
c930a662 1222 return (int)atl1c_wait_until_idle(hw);
43250ddd
JY		 1223}
1224
1225static void atl1c_enable_rx_ctrl(struct atl1c_hw *hw)
1226{
1227 u32 data;
1228
1229 AT_READ_REG(hw, REG_RXQ_CTRL, &data);
1230 switch (hw->adapter->num_rx_queues) {
1231 case 4:
1232 data |= (RXQ3_CTRL_EN | RXQ2_CTRL_EN | RXQ1_CTRL_EN);
1233 break;
1234 case 3:
1235 data |= (RXQ2_CTRL_EN | RXQ1_CTRL_EN);
1236 break;
1237 case 2:
1238 data |= RXQ1_CTRL_EN;
1239 break;
1240 default:
1241 break;
1242 }
1243 data |= RXQ_CTRL_EN;
1244 AT_WRITE_REG(hw, REG_RXQ_CTRL, data);
1245}
1246
1247static void atl1c_enable_tx_ctrl(struct atl1c_hw *hw)
1248{
1249 u32 data;
1250
1251 AT_READ_REG(hw, REG_TXQ_CTRL, &data);
1252 data |= TXQ_CTRL_EN;
1253 AT_WRITE_REG(hw, REG_TXQ_CTRL, data);
1254}
1255
1256/*
1257 * Reset the transmit and receive units; mask and clear all interrupts.
1258 * hw - Struct containing variables accessed by shared code
1259 * return : 0 or idle status (if error)
1260 */
1261static int atl1c_reset_mac(struct atl1c_hw *hw)
1262{
1263 struct atl1c_adapter *adapter = (struct atl1c_adapter *)hw->adapter;
1264 struct pci_dev *pdev = adapter->pdev;
8f574b35 1265 u32 master_ctrl_data = 0;
43250ddd
JY		 1266
1267 AT_WRITE_REG(hw, REG_IMR, 0);
1268 AT_WRITE_REG(hw, REG_ISR, ISR_DIS_INT);
1269
8f574b35 1270 atl1c_stop_mac(hw);
43250ddd
JY		 1271 /*
1272 * Issue Soft Reset to the MAC. This will reset the chip's
1273 * transmit, receive, DMA. It will not effect
1274 * the current PCI configuration. The global reset bit is self-
1275 * clearing, and should clear within a microsecond.
1276 */
8f574b35
JY		 1277 AT_READ_REG(hw, REG_MASTER_CTRL, &master_ctrl_data);
1278 master_ctrl_data |= MASTER_CTRL_OOB_DIS_OFF;
1279 AT_WRITE_REGW(hw, REG_MASTER_CTRL, ((master_ctrl_data | MASTER_CTRL_SOFT_RST)
1280 & 0xFFFF));
1281
43250ddd
JY		 1282 AT_WRITE_FLUSH(hw);
1283 msleep(10);
1284 /* Wait at least 10ms for All module to be Idle */
c930a662
JP		 1285
1286 if (atl1c_wait_until_idle(hw)) {
43250ddd 1287 dev_err(&pdev->dev,
c930a662 1288 "MAC state machine can't be idle since"
43250ddd
JY		 1289 " disabled for 10ms second\n");
1290 return -1;
1291 }
1292 return 0;
1293}
1294
1295static void atl1c_disable_l0s_l1(struct atl1c_hw *hw)
1296{
1297 u32 pm_ctrl_data;
1298
1299 AT_READ_REG(hw, REG_PM_CTRL, &pm_ctrl_data);
1300 pm_ctrl_data &= ~(PM_CTRL_L1_ENTRY_TIMER_MASK <<
1301 PM_CTRL_L1_ENTRY_TIMER_SHIFT);
1302 pm_ctrl_data &= ~PM_CTRL_CLK_SWH_L1;
1303 pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
1304 pm_ctrl_data &= ~PM_CTRL_ASPM_L1_EN;
1305 pm_ctrl_data &= ~PM_CTRL_MAC_ASPM_CHK;
1306 pm_ctrl_data &= ~PM_CTRL_SERDES_PD_EX_L1;
1307
1308 pm_ctrl_data |= PM_CTRL_SERDES_BUDS_RX_L1_EN;
1309 pm_ctrl_data |= PM_CTRL_SERDES_PLL_L1_EN;
1310 pm_ctrl_data |= PM_CTRL_SERDES_L1_EN;
1311 AT_WRITE_REG(hw, REG_PM_CTRL, pm_ctrl_data);
1312}
1313
1314/*
1315 * Set ASPM state.
1316 * Enable/disable L0s/L1 depend on link state.
1317 */
1318static void atl1c_set_aspm(struct atl1c_hw *hw, bool linkup)
1319{
1320 u32 pm_ctrl_data;
496c185c 1321 u32 link_ctrl_data;
8f574b35 1322 u32 link_l1_timer = 0xF;
43250ddd
JY		 1323
1324 AT_READ_REG(hw, REG_PM_CTRL, &pm_ctrl_data);
496c185c 1325 AT_READ_REG(hw, REG_LINK_CTRL, &link_ctrl_data);
496c185c 1326
8f574b35 1327 pm_ctrl_data &= ~PM_CTRL_SERDES_PD_EX_L1;
43250ddd
JY		 1328 pm_ctrl_data &= ~(PM_CTRL_L1_ENTRY_TIMER_MASK <<
1329 PM_CTRL_L1_ENTRY_TIMER_SHIFT);
496c185c 1330 pm_ctrl_data &= ~(PM_CTRL_LCKDET_TIMER_MASK <<
8f574b35
JY		 1331 PM_CTRL_LCKDET_TIMER_SHIFT);
1332 pm_ctrl_data |= AT_LCKDET_TIMER << PM_CTRL_LCKDET_TIMER_SHIFT;
496c185c 1333
8f574b35
JY		 1334 if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d ||
1335 hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) {
496c185c
LR		 1336 link_ctrl_data &= ~LINK_CTRL_EXT_SYNC;
1337 if (!(hw->ctrl_flags & ATL1C_APS_MODE_ENABLE)) {
8f574b35 1338 if (hw->nic_type == athr_l2c_b && hw->revision_id == L2CB_V10)
496c185c
LR		 1339 link_ctrl_data |= LINK_CTRL_EXT_SYNC;
1340 }
1341
1342 AT_WRITE_REG(hw, REG_LINK_CTRL, link_ctrl_data);
1343
8f574b35
JY		 1344 pm_ctrl_data |= PM_CTRL_RCVR_WT_TIMER;
1345 pm_ctrl_data &= ~(PM_CTRL_PM_REQ_TIMER_MASK <<
1346 PM_CTRL_PM_REQ_TIMER_SHIFT);
1347 pm_ctrl_data |= AT_ASPM_L1_TIMER <<
1348 PM_CTRL_PM_REQ_TIMER_SHIFT;
496c185c
LR		 1349 pm_ctrl_data &= ~PM_CTRL_SA_DLY_EN;
1350 pm_ctrl_data &= ~PM_CTRL_HOTRST;
1351 pm_ctrl_data |= 1 << PM_CTRL_L1_ENTRY_TIMER_SHIFT;
1352 pm_ctrl_data |= PM_CTRL_SERDES_PD_EX_L1;
1353 }
8f574b35 1354 pm_ctrl_data |= PM_CTRL_MAC_ASPM_CHK;
43250ddd 1355 if (linkup) {
496c185c
LR		 1356 pm_ctrl_data &= ~PM_CTRL_ASPM_L1_EN;
1357 pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
1358 if (hw->ctrl_flags & ATL1C_ASPM_L1_SUPPORT)
1359 pm_ctrl_data |= PM_CTRL_ASPM_L1_EN;
1360 if (hw->ctrl_flags & ATL1C_ASPM_L0S_SUPPORT)
1361 pm_ctrl_data |= PM_CTRL_ASPM_L0S_EN;
1362
8f574b35
JY		 1363 if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d ||
1364 hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) {
496c185c
LR		 1365 if (hw->nic_type == athr_l2c_b)
1366 if (!(hw->ctrl_flags & ATL1C_APS_MODE_ENABLE))
8f574b35 1367 pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
496c185c
LR		 1368 pm_ctrl_data &= ~PM_CTRL_SERDES_L1_EN;
1369 pm_ctrl_data &= ~PM_CTRL_SERDES_PLL_L1_EN;
1370 pm_ctrl_data &= ~PM_CTRL_SERDES_BUDS_RX_L1_EN;
1371 pm_ctrl_data |= PM_CTRL_CLK_SWH_L1;
8f574b35
JY		 1372 if (hw->adapter->link_speed == SPEED_100 ||
1373 hw->adapter->link_speed == SPEED_1000) {
1374 pm_ctrl_data &= ~(PM_CTRL_L1_ENTRY_TIMER_MASK <<
1375 PM_CTRL_L1_ENTRY_TIMER_SHIFT);
1376 if (hw->nic_type == athr_l2c_b)
1377 link_l1_timer = 7;
1378 else if (hw->nic_type == athr_l2c_b2 ||
1379 hw->nic_type == athr_l1d_2)
1380 link_l1_timer = 4;
1381 pm_ctrl_data |= link_l1_timer <<
1382 PM_CTRL_L1_ENTRY_TIMER_SHIFT;
496c185c
LR		 1383 }
1384 } else {
1385 pm_ctrl_data |= PM_CTRL_SERDES_L1_EN;
1386 pm_ctrl_data |= PM_CTRL_SERDES_PLL_L1_EN;
1387 pm_ctrl_data |= PM_CTRL_SERDES_BUDS_RX_L1_EN;
1388 pm_ctrl_data &= ~PM_CTRL_CLK_SWH_L1;
1389 pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
1390 pm_ctrl_data &= ~PM_CTRL_ASPM_L1_EN;
43250ddd 1391
8f574b35 1392 }
43250ddd 1393 } else {
52fbc100 1394 pm_ctrl_data &= ~PM_CTRL_SERDES_L1_EN;
43250ddd
JY		 1395 pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
1396 pm_ctrl_data &= ~PM_CTRL_SERDES_PLL_L1_EN;
43250ddd
JY		 1397 pm_ctrl_data |= PM_CTRL_CLK_SWH_L1;
1398
1399 if (hw->ctrl_flags & ATL1C_ASPM_L1_SUPPORT)
1400 pm_ctrl_data |= PM_CTRL_ASPM_L1_EN;
1401 else
1402 pm_ctrl_data &= ~PM_CTRL_ASPM_L1_EN;
1403 }
43250ddd 1404 AT_WRITE_REG(hw, REG_PM_CTRL, pm_ctrl_data);
8f574b35
JY		 1405
1406 return;
43250ddd
JY		 1407}
1408
1409static void atl1c_setup_mac_ctrl(struct atl1c_adapter *adapter)
1410{
1411 struct atl1c_hw *hw = &adapter->hw;
1412 struct net_device *netdev = adapter->netdev;
1413 u32 mac_ctrl_data;
1414
1415 mac_ctrl_data = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN;
1416 mac_ctrl_data |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1417
1418 if (adapter->link_duplex == FULL_DUPLEX) {
1419 hw->mac_duplex = true;
1420 mac_ctrl_data |= MAC_CTRL_DUPLX;
1421 }
1422
1423 if (adapter->link_speed == SPEED_1000)
1424 hw->mac_speed = atl1c_mac_speed_1000;
1425 else
1426 hw->mac_speed = atl1c_mac_speed_10_100;
1427
1428 mac_ctrl_data |= (hw->mac_speed & MAC_CTRL_SPEED_MASK) <<
1429 MAC_CTRL_SPEED_SHIFT;
1430
1431 mac_ctrl_data |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1432 mac_ctrl_data |= ((hw->preamble_len & MAC_CTRL_PRMLEN_MASK) <<
1433 MAC_CTRL_PRMLEN_SHIFT);
1434
1435 if (adapter->vlgrp)
1436 mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
1437
1438 mac_ctrl_data |= MAC_CTRL_BC_EN;
1439 if (netdev->flags & IFF_PROMISC)
1440 mac_ctrl_data |= MAC_CTRL_PROMIS_EN;
1441 if (netdev->flags & IFF_ALLMULTI)
1442 mac_ctrl_data |= MAC_CTRL_MC_ALL_EN;
1443
1444 mac_ctrl_data |= MAC_CTRL_SINGLE_PAUSE_EN;
8f574b35
JY		 1445 if (hw->nic_type == athr_l1d || hw->nic_type == athr_l2c_b2 ||
1446 hw->nic_type == athr_l1d_2) {
496c185c
LR		 1447 mac_ctrl_data |= MAC_CTRL_SPEED_MODE_SW;
1448 mac_ctrl_data |= MAC_CTRL_HASH_ALG_CRC32;
1449 }
43250ddd
JY		 1450 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
1451}
1452
1453/*
1454 * atl1c_configure - Configure Transmit&Receive Unit after Reset
1455 * @adapter: board private structure
1456 *
1457 * Configure the Tx /Rx unit of the MAC after a reset.
1458 */
1459static int atl1c_configure(struct atl1c_adapter *adapter)
1460{
1461 struct atl1c_hw *hw = &adapter->hw;
1462 u32 master_ctrl_data = 0;
1463 u32 intr_modrt_data;
8f574b35 1464 u32 data;
43250ddd
JY		 1465
1466 /* clear interrupt status */
1467 AT_WRITE_REG(hw, REG_ISR, 0xFFFFFFFF);
1468 /* Clear any WOL status */
1469 AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
1470 /* set Interrupt Clear Timer
1471 * HW will enable self to assert interrupt event to system after
1472 * waiting x-time for software to notify it accept interrupt.
1473 */
8f574b35
JY		 1474
1475 data = CLK_GATING_EN_ALL;
1476 if (hw->ctrl_flags & ATL1C_CLK_GATING_EN) {
1477 if (hw->nic_type == athr_l2c_b)
1478 data &= ~CLK_GATING_RXMAC_EN;
1479 } else
1480 data = 0;
1481 AT_WRITE_REG(hw, REG_CLK_GATING_CTRL, data);
1482
43250ddd
JY		 1483 AT_WRITE_REG(hw, REG_INT_RETRIG_TIMER,
1484 hw->ict & INT_RETRIG_TIMER_MASK);
1485
1486 atl1c_configure_des_ring(adapter);
1487
1488 if (hw->ctrl_flags & ATL1C_INTR_MODRT_ENABLE) {
1489 intr_modrt_data = (hw->tx_imt & IRQ_MODRT_TIMER_MASK) <<
1490 IRQ_MODRT_TX_TIMER_SHIFT;
1491 intr_modrt_data |= (hw->rx_imt & IRQ_MODRT_TIMER_MASK) <<
1492 IRQ_MODRT_RX_TIMER_SHIFT;
1493 AT_WRITE_REG(hw, REG_IRQ_MODRT_TIMER_INIT, intr_modrt_data);
1494 master_ctrl_data |=
1495 MASTER_CTRL_TX_ITIMER_EN | MASTER_CTRL_RX_ITIMER_EN;
1496 }
1497
1498 if (hw->ctrl_flags & ATL1C_INTR_CLEAR_ON_READ)
1499 master_ctrl_data |= MASTER_CTRL_INT_RDCLR;
1500
8f574b35 1501 master_ctrl_data |= MASTER_CTRL_SA_TIMER_EN;
43250ddd
JY		 1502 AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
1503
1504 if (hw->ctrl_flags & ATL1C_CMB_ENABLE) {
1505 AT_WRITE_REG(hw, REG_CMB_TPD_THRESH,
1506 hw->cmb_tpd & CMB_TPD_THRESH_MASK);
1507 AT_WRITE_REG(hw, REG_CMB_TX_TIMER,
1508 hw->cmb_tx_timer & CMB_TX_TIMER_MASK);
1509 }
1510
1511 if (hw->ctrl_flags & ATL1C_SMB_ENABLE)
1512 AT_WRITE_REG(hw, REG_SMB_STAT_TIMER,
1513 hw->smb_timer & SMB_STAT_TIMER_MASK);
1514 /* set MTU */
1515 AT_WRITE_REG(hw, REG_MTU, hw->max_frame_size + ETH_HLEN +
1516 VLAN_HLEN + ETH_FCS_LEN);
1517 /* HDS, disable */
1518 AT_WRITE_REG(hw, REG_HDS_CTRL, 0);
1519
1520 atl1c_configure_tx(adapter);
1521 atl1c_configure_rx(adapter);
1522 atl1c_configure_rss(adapter);
1523 atl1c_configure_dma(adapter);
1524
1525 return 0;
1526}
1527
1528static void atl1c_update_hw_stats(struct atl1c_adapter *adapter)
1529{
1530 u16 hw_reg_addr = 0;
1531 unsigned long *stats_item = NULL;
1532 u32 data;
1533
1534 /* update rx status */
1535 hw_reg_addr = REG_MAC_RX_STATUS_BIN;
1536 stats_item = &adapter->hw_stats.rx_ok;
1537 while (hw_reg_addr <= REG_MAC_RX_STATUS_END) {
1538 AT_READ_REG(&adapter->hw, hw_reg_addr, &data);
1539 *stats_item += data;
1540 stats_item++;
1541 hw_reg_addr += 4;
1542 }
1543/* update tx status */
1544 hw_reg_addr = REG_MAC_TX_STATUS_BIN;
1545 stats_item = &adapter->hw_stats.tx_ok;
1546 while (hw_reg_addr <= REG_MAC_TX_STATUS_END) {
1547 AT_READ_REG(&adapter->hw, hw_reg_addr, &data);
1548 *stats_item += data;
1549 stats_item++;
1550 hw_reg_addr += 4;
1551 }
1552}
1553
1554/*
1555 * atl1c_get_stats - Get System Network Statistics
1556 * @netdev: network interface device structure
1557 *
1558 * Returns the address of the device statistics structure.
1559 * The statistics are actually updated from the timer callback.
1560 */
1561static struct net_device_stats *atl1c_get_stats(struct net_device *netdev)
1562{
1563 struct atl1c_adapter *adapter = netdev_priv(netdev);
1564 struct atl1c_hw_stats *hw_stats = &adapter->hw_stats;
a2c483a1 1565 struct net_device_stats *net_stats = &netdev->stats;
43250ddd
JY		 1566
1567 atl1c_update_hw_stats(adapter);
1568 net_stats->rx_packets = hw_stats->rx_ok;
1569 net_stats->tx_packets = hw_stats->tx_ok;
1570 net_stats->rx_bytes = hw_stats->rx_byte_cnt;
1571 net_stats->tx_bytes = hw_stats->tx_byte_cnt;
1572 net_stats->multicast = hw_stats->rx_mcast;
1573 net_stats->collisions = hw_stats->tx_1_col +
1574 hw_stats->tx_2_col * 2 +
1575 hw_stats->tx_late_col + hw_stats->tx_abort_col;
1576 net_stats->rx_errors = hw_stats->rx_frag + hw_stats->rx_fcs_err +
1577 hw_stats->rx_len_err + hw_stats->rx_sz_ov +
1578 hw_stats->rx_rrd_ov + hw_stats->rx_align_err;
1579 net_stats->rx_fifo_errors = hw_stats->rx_rxf_ov;
1580 net_stats->rx_length_errors = hw_stats->rx_len_err;
1581 net_stats->rx_crc_errors = hw_stats->rx_fcs_err;
1582 net_stats->rx_frame_errors = hw_stats->rx_align_err;
1583 net_stats->rx_over_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov;
1584
1585 net_stats->rx_missed_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov;
1586
1587 net_stats->tx_errors = hw_stats->tx_late_col + hw_stats->tx_abort_col +
1588 hw_stats->tx_underrun + hw_stats->tx_trunc;
1589 net_stats->tx_fifo_errors = hw_stats->tx_underrun;
1590 net_stats->tx_aborted_errors = hw_stats->tx_abort_col;
1591 net_stats->tx_window_errors = hw_stats->tx_late_col;
1592
a2c483a1 1593 return net_stats;
43250ddd
JY		 1594}
1595
1596static inline void atl1c_clear_phy_int(struct atl1c_adapter *adapter)
1597{
1598 u16 phy_data;
1599
1600 spin_lock(&adapter->mdio_lock);
1601 atl1c_read_phy_reg(&adapter->hw, MII_ISR, &phy_data);
1602 spin_unlock(&adapter->mdio_lock);
1603}
1604
1605static bool atl1c_clean_tx_irq(struct atl1c_adapter *adapter,
1606 enum atl1c_trans_queue type)
1607{
1608 struct atl1c_tpd_ring *tpd_ring = (struct atl1c_tpd_ring *)
1609 &adapter->tpd_ring[type];
1610 struct atl1c_buffer *buffer_info;
c6060be4 1611 struct pci_dev *pdev = adapter->pdev;
43250ddd
JY		 1612 u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean);
1613 u16 hw_next_to_clean;
1614 u16 shift;
1615 u32 data;
1616
1617 if (type == atl1c_trans_high)
1618 shift = MB_HTPD_CONS_IDX_SHIFT;
1619 else
1620 shift = MB_NTPD_CONS_IDX_SHIFT;
1621
1622 AT_READ_REG(&adapter->hw, REG_MB_PRIO_CONS_IDX, &data);
1623 hw_next_to_clean = (data >> shift) & MB_PRIO_PROD_IDX_MASK;
1624
1625 while (next_to_clean != hw_next_to_clean) {
1626 buffer_info = &tpd_ring->buffer_info[next_to_clean];
c6060be4 1627 atl1c_clean_buffer(pdev, buffer_info, 1);
43250ddd
JY		 1628 if (++next_to_clean == tpd_ring->count)
1629 next_to_clean = 0;
1630 atomic_set(&tpd_ring->next_to_clean, next_to_clean);
1631 }
1632
1633 if (netif_queue_stopped(adapter->netdev) &&
1634 netif_carrier_ok(adapter->netdev)) {
1635 netif_wake_queue(adapter->netdev);
1636 }
1637
1638 return true;
1639}
1640
1641/*
1642 * atl1c_intr - Interrupt Handler
1643 * @irq: interrupt number
1644 * @data: pointer to a network interface device structure
1645 * @pt_regs: CPU registers structure
1646 */
1647static irqreturn_t atl1c_intr(int irq, void *data)
1648{
1649 struct net_device *netdev = data;
1650 struct atl1c_adapter *adapter = netdev_priv(netdev);
1651 struct pci_dev *pdev = adapter->pdev;
1652 struct atl1c_hw *hw = &adapter->hw;
1653 int max_ints = AT_MAX_INT_WORK;
1654 int handled = IRQ_NONE;
1655 u32 status;
1656 u32 reg_data;
1657
1658 do {
1659 AT_READ_REG(hw, REG_ISR, &reg_data);
1660 status = reg_data & hw->intr_mask;
1661
1662 if (status == 0 || (status & ISR_DIS_INT) != 0) {
1663 if (max_ints != AT_MAX_INT_WORK)
1664 handled = IRQ_HANDLED;
1665 break;
1666 }
1667 /* link event */
1668 if (status & ISR_GPHY)
1669 atl1c_clear_phy_int(adapter);
1670 /* Ack ISR */
1671 AT_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
1672 if (status & ISR_RX_PKT) {
1673 if (likely(napi_schedule_prep(&adapter->napi))) {
1674 hw->intr_mask &= ~ISR_RX_PKT;
1675 AT_WRITE_REG(hw, REG_IMR, hw->intr_mask);
1676 __napi_schedule(&adapter->napi);
1677 }
1678 }
1679 if (status & ISR_TX_PKT)
1680 atl1c_clean_tx_irq(adapter, atl1c_trans_normal);
1681
1682 handled = IRQ_HANDLED;
1683 /* check if PCIE PHY Link down */
1684 if (status & ISR_ERROR) {
1685 if (netif_msg_hw(adapter))
1686 dev_err(&pdev->dev,
1687 "atl1c hardware error (status = 0x%x)\n",
1688 status & ISR_ERROR);
1689 /* reset MAC */
cb190546
JY		 1690 adapter->work_event |= ATL1C_WORK_EVENT_RESET;
1691 schedule_work(&adapter->common_task);
8f574b35 1692 return IRQ_HANDLED;
43250ddd
JY		 1693 }
1694
1695 if (status & ISR_OVER)
1696 if (netif_msg_intr(adapter))
1697 dev_warn(&pdev->dev,
af901ca1 1698 "TX/RX overflow (status = 0x%x)\n",
43250ddd
JY		 1699 status & ISR_OVER);
1700
1701 /* link event */
1702 if (status & (ISR_GPHY | ISR_MANUAL)) {
a2c483a1 1703 netdev->stats.tx_carrier_errors++;
43250ddd
JY		 1704 atl1c_link_chg_event(adapter);
1705 break;
1706 }
1707
1708 } while (--max_ints > 0);
1709 /* re-enable Interrupt*/
1710 AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
1711 return handled;
1712}
1713
1714static inline void atl1c_rx_checksum(struct atl1c_adapter *adapter,
1715 struct sk_buff *skb, struct atl1c_recv_ret_status *prrs)
1716{
1717 /*
1718 * The pid field in RRS in not correct sometimes, so we
1719 * cannot figure out if the packet is fragmented or not,
1720 * so we tell the KERNEL CHECKSUM_NONE
1721 */
bc8acf2c 1722 skb_checksum_none_assert(skb);
43250ddd
JY		 1723}
1724
1725static int atl1c_alloc_rx_buffer(struct atl1c_adapter *adapter, const int ringid)
1726{
1727 struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring[ringid];
1728 struct pci_dev *pdev = adapter->pdev;
1729 struct atl1c_buffer *buffer_info, *next_info;
1730 struct sk_buff *skb;
1731 void *vir_addr = NULL;
1732 u16 num_alloc = 0;
1733 u16 rfd_next_to_use, next_next;
1734 struct atl1c_rx_free_desc *rfd_desc;
1735
1736 next_next = rfd_next_to_use = rfd_ring->next_to_use;
1737 if (++next_next == rfd_ring->count)
1738 next_next = 0;
1739 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
1740 next_info = &rfd_ring->buffer_info[next_next];
1741
c6060be4 1742 while (next_info->flags & ATL1C_BUFFER_FREE) {
43250ddd
JY		 1743 rfd_desc = ATL1C_RFD_DESC(rfd_ring, rfd_next_to_use);
1744
1745 skb = dev_alloc_skb(adapter->rx_buffer_len);
1746 if (unlikely(!skb)) {
1747 if (netif_msg_rx_err(adapter))
1748 dev_warn(&pdev->dev, "alloc rx buffer failed\n");
1749 break;
1750 }
1751
1752 /*
1753 * Make buffer alignment 2 beyond a 16 byte boundary
1754 * this will result in a 16 byte aligned IP header after
1755 * the 14 byte MAC header is removed
1756 */
1757 vir_addr = skb->data;
c6060be4 1758 ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
43250ddd
JY		 1759 buffer_info->skb = skb;
1760 buffer_info->length = adapter->rx_buffer_len;
1761 buffer_info->dma = pci_map_single(pdev, vir_addr,
1762 buffer_info->length,
1763 PCI_DMA_FROMDEVICE);
4b45e342
JY		 1764 ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
1765 ATL1C_PCIMAP_FROMDEVICE);
43250ddd
JY		 1766 rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
1767 rfd_next_to_use = next_next;
1768 if (++next_next == rfd_ring->count)
1769 next_next = 0;
1770 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
1771 next_info = &rfd_ring->buffer_info[next_next];
1772 num_alloc++;
1773 }
1774
1775 if (num_alloc) {
1776 /* TODO: update mailbox here */
1777 wmb();
1778 rfd_ring->next_to_use = rfd_next_to_use;
1779 AT_WRITE_REG(&adapter->hw, atl1c_rfd_prod_idx_regs[ringid],
1780 rfd_ring->next_to_use & MB_RFDX_PROD_IDX_MASK);
1781 }
1782
1783 return num_alloc;
1784}
1785
1786static void atl1c_clean_rrd(struct atl1c_rrd_ring *rrd_ring,
1787 struct atl1c_recv_ret_status *rrs, u16 num)
1788{
1789 u16 i;
1790 /* the relationship between rrd and rfd is one map one */
1791 for (i = 0; i < num; i++, rrs = ATL1C_RRD_DESC(rrd_ring,
1792 rrd_ring->next_to_clean)) {
1793 rrs->word3 &= ~RRS_RXD_UPDATED;
1794 if (++rrd_ring->next_to_clean == rrd_ring->count)
1795 rrd_ring->next_to_clean = 0;
1796 }
1797}
1798
1799static void atl1c_clean_rfd(struct atl1c_rfd_ring *rfd_ring,
1800 struct atl1c_recv_ret_status *rrs, u16 num)
1801{
1802 u16 i;
1803 u16 rfd_index;
1804 struct atl1c_buffer *buffer_info = rfd_ring->buffer_info;
1805
1806 rfd_index = (rrs->word0 >> RRS_RX_RFD_INDEX_SHIFT) &
1807 RRS_RX_RFD_INDEX_MASK;
1808 for (i = 0; i < num; i++) {
1809 buffer_info[rfd_index].skb = NULL;
c6060be4
JY		 1810 ATL1C_SET_BUFFER_STATE(&buffer_info[rfd_index],
1811 ATL1C_BUFFER_FREE);
43250ddd
JY		 1812 if (++rfd_index == rfd_ring->count)
1813 rfd_index = 0;
1814 }
1815 rfd_ring->next_to_clean = rfd_index;
1816}
1817
1818static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter, u8 que,
1819 int *work_done, int work_to_do)
1820{
1821 u16 rfd_num, rfd_index;
1822 u16 count = 0;
1823 u16 length;
1824 struct pci_dev *pdev = adapter->pdev;
1825 struct net_device *netdev = adapter->netdev;
1826 struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring[que];
1827 struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring[que];
1828 struct sk_buff *skb;
1829 struct atl1c_recv_ret_status *rrs;
1830 struct atl1c_buffer *buffer_info;
1831
1832 while (1) {
1833 if (*work_done >= work_to_do)
1834 break;
1835 rrs = ATL1C_RRD_DESC(rrd_ring, rrd_ring->next_to_clean);
1836 if (likely(RRS_RXD_IS_VALID(rrs->word3))) {
1837 rfd_num = (rrs->word0 >> RRS_RX_RFD_CNT_SHIFT) &
1838 RRS_RX_RFD_CNT_MASK;
37b76c69 1839 if (unlikely(rfd_num != 1))
43250ddd
JY		 1840 /* TODO support mul rfd*/
1841 if (netif_msg_rx_err(adapter))
1842 dev_warn(&pdev->dev,
1843 "Multi rfd not support yet!\n");
1844 goto rrs_checked;
1845 } else {
1846 break;
1847 }
1848rrs_checked:
1849 atl1c_clean_rrd(rrd_ring, rrs, rfd_num);
1850 if (rrs->word3 & (RRS_RX_ERR_SUM | RRS_802_3_LEN_ERR)) {
1851 atl1c_clean_rfd(rfd_ring, rrs, rfd_num);
1852 if (netif_msg_rx_err(adapter))
1853 dev_warn(&pdev->dev,
1854 "wrong packet! rrs word3 is %x\n",
1855 rrs->word3);
1856 continue;
1857 }
1858
1859 length = le16_to_cpu((rrs->word3 >> RRS_PKT_SIZE_SHIFT) &
1860 RRS_PKT_SIZE_MASK);
1861 /* Good Receive */
1862 if (likely(rfd_num == 1)) {
1863 rfd_index = (rrs->word0 >> RRS_RX_RFD_INDEX_SHIFT) &
1864 RRS_RX_RFD_INDEX_MASK;
1865 buffer_info = &rfd_ring->buffer_info[rfd_index];
1866 pci_unmap_single(pdev, buffer_info->dma,
1867 buffer_info->length, PCI_DMA_FROMDEVICE);
1868 skb = buffer_info->skb;
1869 } else {
1870 /* TODO */
1871 if (netif_msg_rx_err(adapter))
1872 dev_warn(&pdev->dev,
1873 "Multi rfd not support yet!\n");
1874 break;
1875 }
1876 atl1c_clean_rfd(rfd_ring, rrs, rfd_num);
1877 skb_put(skb, length - ETH_FCS_LEN);
1878 skb->protocol = eth_type_trans(skb, netdev);
43250ddd
JY		 1879 atl1c_rx_checksum(adapter, skb, rrs);
1880 if (unlikely(adapter->vlgrp) && rrs->word3 & RRS_VLAN_INS) {
1881 u16 vlan;
1882
1883 AT_TAG_TO_VLAN(rrs->vlan_tag, vlan);
1884 vlan = le16_to_cpu(vlan);
1885 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, vlan);
1886 } else
1887 netif_receive_skb(skb);
1888
43250ddd
JY		 1889 (*work_done)++;
1890 count++;
1891 }
1892 if (count)
1893 atl1c_alloc_rx_buffer(adapter, que);
1894}
1895
1896/*
1897 * atl1c_clean - NAPI Rx polling callback
1898 * @adapter: board private structure
1899 */
1900static int atl1c_clean(struct napi_struct *napi, int budget)
1901{
1902 struct atl1c_adapter *adapter =
1903 container_of(napi, struct atl1c_adapter, napi);
1904 int work_done = 0;
1905
1906 /* Keep link state information with original netdev */
1907 if (!netif_carrier_ok(adapter->netdev))
1908 goto quit_polling;
1909 /* just enable one RXQ */
1910 atl1c_clean_rx_irq(adapter, 0, &work_done, budget);
1911
1912 if (work_done < budget) {
1913quit_polling:
1914 napi_complete(napi);
1915 adapter->hw.intr_mask |= ISR_RX_PKT;
1916 AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask);
1917 }
1918 return work_done;
1919}
1920
1921#ifdef CONFIG_NET_POLL_CONTROLLER
1922
1923/*
1924 * Polling 'interrupt' - used by things like netconsole to send skbs
1925 * without having to re-enable interrupts. It's not called while
1926 * the interrupt routine is executing.
1927 */
1928static void atl1c_netpoll(struct net_device *netdev)
1929{
1930 struct atl1c_adapter *adapter = netdev_priv(netdev);
1931
1932 disable_irq(adapter->pdev->irq);
1933 atl1c_intr(adapter->pdev->irq, netdev);
1934 enable_irq(adapter->pdev->irq);
1935}
1936#endif
1937
1938static inline u16 atl1c_tpd_avail(struct atl1c_adapter *adapter, enum atl1c_trans_queue type)
1939{
1940 struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
1941 u16 next_to_use = 0;
1942 u16 next_to_clean = 0;
1943
1944 next_to_clean = atomic_read(&tpd_ring->next_to_clean);
1945 next_to_use = tpd_ring->next_to_use;
1946
1947 return (u16)(next_to_clean > next_to_use) ?
1948 (next_to_clean - next_to_use - 1) :
1949 (tpd_ring->count + next_to_clean - next_to_use - 1);
1950}
1951
1952/*
1953 * get next usable tpd
1954 * Note: should call atl1c_tdp_avail to make sure
1955 * there is enough tpd to use
1956 */
1957static struct atl1c_tpd_desc *atl1c_get_tpd(struct atl1c_adapter *adapter,
1958 enum atl1c_trans_queue type)
1959{
1960 struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
1961 struct atl1c_tpd_desc *tpd_desc;
1962 u16 next_to_use = 0;
1963
1964 next_to_use = tpd_ring->next_to_use;
1965 if (++tpd_ring->next_to_use == tpd_ring->count)
1966 tpd_ring->next_to_use = 0;
1967 tpd_desc = ATL1C_TPD_DESC(tpd_ring, next_to_use);
1968 memset(tpd_desc, 0, sizeof(struct atl1c_tpd_desc));
1969 return tpd_desc;
1970}
1971
1972static struct atl1c_buffer *
1973atl1c_get_tx_buffer(struct atl1c_adapter *adapter, struct atl1c_tpd_desc *tpd)
1974{
1975 struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
1976
1977 return &tpd_ring->buffer_info[tpd -
1978 (struct atl1c_tpd_desc *)tpd_ring->desc];
1979}
1980
1981/* Calculate the transmit packet descript needed*/
1982static u16 atl1c_cal_tpd_req(const struct sk_buff *skb)
1983{
1984 u16 tpd_req;
1985 u16 proto_hdr_len = 0;
1986
1987 tpd_req = skb_shinfo(skb)->nr_frags + 1;
1988
1989 if (skb_is_gso(skb)) {
1990 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1991 if (proto_hdr_len < skb_headlen(skb))
1992 tpd_req++;
1993 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
1994 tpd_req++;
1995 }
1996 return tpd_req;
1997}
1998
1999static int atl1c_tso_csum(struct atl1c_adapter *adapter,
2000 struct sk_buff *skb,
2001 struct atl1c_tpd_desc **tpd,
2002 enum atl1c_trans_queue type)
2003{
2004 struct pci_dev *pdev = adapter->pdev;
2005 u8 hdr_len;
2006 u32 real_len;
2007 unsigned short offload_type;
2008 int err;
2009
2010 if (skb_is_gso(skb)) {
2011 if (skb_header_cloned(skb)) {
2012 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2013 if (unlikely(err))
2014 return -1;
2015 }
2016 offload_type = skb_shinfo(skb)->gso_type;
2017
2018 if (offload_type & SKB_GSO_TCPV4) {
2019 real_len = (((unsigned char *)ip_hdr(skb) - skb->data)
2020 + ntohs(ip_hdr(skb)->tot_len));
2021
2022 if (real_len < skb->len)
2023 pskb_trim(skb, real_len);
2024
2025 hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
2026 if (unlikely(skb->len == hdr_len)) {
2027 /* only xsum need */
2028 if (netif_msg_tx_queued(adapter))
2029 dev_warn(&pdev->dev,
2030 "IPV4 tso with zero data??\n");
2031 goto check_sum;
2032 } else {
2033 ip_hdr(skb)->check = 0;
2034 tcp_hdr(skb)->check = ~csum_tcpudp_magic(
2035 ip_hdr(skb)->saddr,
2036 ip_hdr(skb)->daddr,
2037 0, IPPROTO_TCP, 0);
2038 (*tpd)->word1 |= 1 << TPD_IPV4_PACKET_SHIFT;
2039 }
2040 }
2041
2042 if (offload_type & SKB_GSO_TCPV6) {
2043 struct atl1c_tpd_ext_desc *etpd =
2044 *(struct atl1c_tpd_ext_desc **)(tpd);
2045
2046 memset(etpd, 0, sizeof(struct atl1c_tpd_ext_desc));
2047 *tpd = atl1c_get_tpd(adapter, type);
2048 ipv6_hdr(skb)->payload_len = 0;
2049 /* check payload == 0 byte ? */
2050 hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
2051 if (unlikely(skb->len == hdr_len)) {
2052 /* only xsum need */
2053 if (netif_msg_tx_queued(adapter))
2054 dev_warn(&pdev->dev,
2055 "IPV6 tso with zero data??\n");
2056 goto check_sum;
2057 } else
2058 tcp_hdr(skb)->check = ~csum_ipv6_magic(
2059 &ipv6_hdr(skb)->saddr,
2060 &ipv6_hdr(skb)->daddr,
2061 0, IPPROTO_TCP, 0);
2062 etpd->word1 |= 1 << TPD_LSO_EN_SHIFT;
2063 etpd->word1 |= 1 << TPD_LSO_VER_SHIFT;
2064 etpd->pkt_len = cpu_to_le32(skb->len);
2065 (*tpd)->word1 |= 1 << TPD_LSO_VER_SHIFT;
2066 }
2067
2068 (*tpd)->word1 |= 1 << TPD_LSO_EN_SHIFT;
2069 (*tpd)->word1 |= (skb_transport_offset(skb) & TPD_TCPHDR_OFFSET_MASK) <<
2070 TPD_TCPHDR_OFFSET_SHIFT;
2071 (*tpd)->word1 |= (skb_shinfo(skb)->gso_size & TPD_MSS_MASK) <<
2072 TPD_MSS_SHIFT;
2073 return 0;
2074 }
2075
2076check_sum:
2077 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
2078 u8 css, cso;
0d0b1672 2079 cso = skb_checksum_start_offset(skb);
43250ddd
JY		 2080
2081 if (unlikely(cso & 0x1)) {
2082 if (netif_msg_tx_err(adapter))
2083 dev_err(&adapter->pdev->dev,
2084 "payload offset should not an event number\n");
2085 return -1;
2086 } else {
2087 css = cso + skb->csum_offset;
2088
2089 (*tpd)->word1 |= ((cso >> 1) & TPD_PLOADOFFSET_MASK) <<
2090 TPD_PLOADOFFSET_SHIFT;
2091 (*tpd)->word1 |= ((css >> 1) & TPD_CCSUM_OFFSET_MASK) <<
2092 TPD_CCSUM_OFFSET_SHIFT;
2093 (*tpd)->word1 |= 1 << TPD_CCSUM_EN_SHIFT;
2094 }
2095 }
2096 return 0;
2097}
2098
2099static void atl1c_tx_map(struct atl1c_adapter *adapter,
2100 struct sk_buff *skb, struct atl1c_tpd_desc *tpd,
2101 enum atl1c_trans_queue type)
2102{
2103 struct atl1c_tpd_desc *use_tpd = NULL;
2104 struct atl1c_buffer *buffer_info = NULL;
2105 u16 buf_len = skb_headlen(skb);
2106 u16 map_len = 0;
2107 u16 mapped_len = 0;
2108 u16 hdr_len = 0;
2109 u16 nr_frags;
2110 u16 f;
2111 int tso;
2112
2113 nr_frags = skb_shinfo(skb)->nr_frags;
2114 tso = (tpd->word1 >> TPD_LSO_EN_SHIFT) & TPD_LSO_EN_MASK;
2115 if (tso) {
2116 /* TSO */
2117 map_len = hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2118 use_tpd = tpd;
2119
2120 buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
2121 buffer_info->length = map_len;
2122 buffer_info->dma = pci_map_single(adapter->pdev,
2123 skb->data, hdr_len, PCI_DMA_TODEVICE);
c6060be4 2124 ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
4b45e342
JY		 2125 ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
2126 ATL1C_PCIMAP_TODEVICE);
43250ddd
JY		 2127 mapped_len += map_len;
2128 use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
2129 use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
2130 }
2131
2132 if (mapped_len < buf_len) {
2133 /* mapped_len == 0, means we should use the first tpd,
2134 which is given by caller */
2135 if (mapped_len == 0)
2136 use_tpd = tpd;
2137 else {
2138 use_tpd = atl1c_get_tpd(adapter, type);
43250ddd
JY		 2139 memcpy(use_tpd, tpd, sizeof(struct atl1c_tpd_desc));
2140 }
2141 buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
2142 buffer_info->length = buf_len - mapped_len;
2143 buffer_info->dma =
2144 pci_map_single(adapter->pdev, skb->data + mapped_len,
2145 buffer_info->length, PCI_DMA_TODEVICE);
c6060be4 2146 ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
4b45e342
JY		 2147 ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
2148 ATL1C_PCIMAP_TODEVICE);
43250ddd
JY		 2149 use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
2150 use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
2151 }
2152
2153 for (f = 0; f < nr_frags; f++) {
2154 struct skb_frag_struct *frag;
2155
2156 frag = &skb_shinfo(skb)->frags[f];
2157
2158 use_tpd = atl1c_get_tpd(adapter, type);
2159 memcpy(use_tpd, tpd, sizeof(struct atl1c_tpd_desc));
2160
2161 buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
2162 buffer_info->length = frag->size;
2163 buffer_info->dma =
2164 pci_map_page(adapter->pdev, frag->page,
2165 frag->page_offset,
2166 buffer_info->length,
2167 PCI_DMA_TODEVICE);
c6060be4 2168 ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
4b45e342
JY		 2169 ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_PAGE,
2170 ATL1C_PCIMAP_TODEVICE);
43250ddd
JY		 2171 use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
2172 use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
2173 }
2174
2175 /* The last tpd */
2176 use_tpd->word1 |= 1 << TPD_EOP_SHIFT;
2177 /* The last buffer info contain the skb address,
2178 so it will be free after unmap */
2179 buffer_info->skb = skb;
2180}
2181
2182static void atl1c_tx_queue(struct atl1c_adapter *adapter, struct sk_buff *skb,
2183 struct atl1c_tpd_desc *tpd, enum atl1c_trans_queue type)
2184{
2185 struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
2186 u32 prod_data;
2187
2188 AT_READ_REG(&adapter->hw, REG_MB_PRIO_PROD_IDX, &prod_data);
2189 switch (type) {
2190 case atl1c_trans_high:
2191 prod_data &= 0xFFFF0000;
2192 prod_data |= tpd_ring->next_to_use & 0xFFFF;
2193 break;
2194 case atl1c_trans_normal:
2195 prod_data &= 0x0000FFFF;
2196 prod_data |= (tpd_ring->next_to_use & 0xFFFF) << 16;
2197 break;
2198 default:
2199 break;
2200 }
2201 wmb();
2202 AT_WRITE_REG(&adapter->hw, REG_MB_PRIO_PROD_IDX, prod_data);
2203}
2204
61357325
SH		 2205static netdev_tx_t atl1c_xmit_frame(struct sk_buff *skb,
2206 struct net_device *netdev)
43250ddd
JY		 2207{
2208 struct atl1c_adapter *adapter = netdev_priv(netdev);
2209 unsigned long flags;
2210 u16 tpd_req = 1;
2211 struct atl1c_tpd_desc *tpd;
2212 enum atl1c_trans_queue type = atl1c_trans_normal;
2213
2214 if (test_bit(__AT_DOWN, &adapter->flags)) {
2215 dev_kfree_skb_any(skb);
2216 return NETDEV_TX_OK;
2217 }
2218
2219 tpd_req = atl1c_cal_tpd_req(skb);
2220 if (!spin_trylock_irqsave(&adapter->tx_lock, flags)) {
2221 if (netif_msg_pktdata(adapter))
2222 dev_info(&adapter->pdev->dev, "tx locked\n");
2223 return NETDEV_TX_LOCKED;
2224 }
2225 if (skb->mark == 0x01)
2226 type = atl1c_trans_high;
2227 else
2228 type = atl1c_trans_normal;
2229
2230 if (atl1c_tpd_avail(adapter, type) < tpd_req) {
2231 /* no enough descriptor, just stop queue */
2232 netif_stop_queue(netdev);
2233 spin_unlock_irqrestore(&adapter->tx_lock, flags);
2234 return NETDEV_TX_BUSY;
2235 }
2236
2237 tpd = atl1c_get_tpd(adapter, type);
2238
2239 /* do TSO and check sum */
2240 if (atl1c_tso_csum(adapter, skb, &tpd, type) != 0) {
2241 spin_unlock_irqrestore(&adapter->tx_lock, flags);
2242 dev_kfree_skb_any(skb);
2243 return NETDEV_TX_OK;
2244 }
2245
eab6d18d 2246 if (unlikely(vlan_tx_tag_present(skb))) {
43250ddd
JY		 2247 u16 vlan = vlan_tx_tag_get(skb);
2248 __le16 tag;
2249
2250 vlan = cpu_to_le16(vlan);
2251 AT_VLAN_TO_TAG(vlan, tag);
2252 tpd->word1 |= 1 << TPD_INS_VTAG_SHIFT;
2253 tpd->vlan_tag = tag;
2254 }
2255
2256 if (skb_network_offset(skb) != ETH_HLEN)
2257 tpd->word1 |= 1 << TPD_ETH_TYPE_SHIFT; /* Ethernet frame */
2258
2259 atl1c_tx_map(adapter, skb, tpd, type);
2260 atl1c_tx_queue(adapter, skb, tpd, type);
2261
43250ddd
JY		 2262 spin_unlock_irqrestore(&adapter->tx_lock, flags);
2263 return NETDEV_TX_OK;
2264}
2265
2266static void atl1c_free_irq(struct atl1c_adapter *adapter)
2267{
2268 struct net_device *netdev = adapter->netdev;
2269
2270 free_irq(adapter->pdev->irq, netdev);
2271
2272 if (adapter->have_msi)
2273 pci_disable_msi(adapter->pdev);
2274}
2275
2276static int atl1c_request_irq(struct atl1c_adapter *adapter)
2277{
2278 struct pci_dev *pdev = adapter->pdev;
2279 struct net_device *netdev = adapter->netdev;
2280 int flags = 0;
2281 int err = 0;
2282
2283 adapter->have_msi = true;
2284 err = pci_enable_msi(adapter->pdev);
2285 if (err) {
2286 if (netif_msg_ifup(adapter))
2287 dev_err(&pdev->dev,
2288 "Unable to allocate MSI interrupt Error: %d\n",
2289 err);
2290 adapter->have_msi = false;
2291 } else
2292 netdev->irq = pdev->irq;
2293
2294 if (!adapter->have_msi)
2295 flags |= IRQF_SHARED;
9aff7e92 2296 err = request_irq(adapter->pdev->irq, atl1c_intr, flags,
43250ddd
JY		 2297 netdev->name, netdev);
2298 if (err) {
2299 if (netif_msg_ifup(adapter))
2300 dev_err(&pdev->dev,
2301 "Unable to allocate interrupt Error: %d\n",
2302 err);
2303 if (adapter->have_msi)
2304 pci_disable_msi(adapter->pdev);
2305 return err;
2306 }
2307 if (netif_msg_ifup(adapter))
2308 dev_dbg(&pdev->dev, "atl1c_request_irq OK\n");
2309 return err;
2310}
2311
0fb1e54e 2312static int atl1c_up(struct atl1c_adapter *adapter)
43250ddd
JY		 2313{
2314 struct net_device *netdev = adapter->netdev;
2315 int num;
2316 int err;
2317 int i;
2318
2319 netif_carrier_off(netdev);
2320 atl1c_init_ring_ptrs(adapter);
2321 atl1c_set_multi(netdev);
2322 atl1c_restore_vlan(adapter);
2323
2324 for (i = 0; i < adapter->num_rx_queues; i++) {
2325 num = atl1c_alloc_rx_buffer(adapter, i);
2326 if (unlikely(num == 0)) {
2327 err = -ENOMEM;
2328 goto err_alloc_rx;
2329 }
2330 }
2331
2332 if (atl1c_configure(adapter)) {
2333 err = -EIO;
2334 goto err_up;
2335 }
2336
2337 err = atl1c_request_irq(adapter);
2338 if (unlikely(err))
2339 goto err_up;
2340
2341 clear_bit(__AT_DOWN, &adapter->flags);
2342 napi_enable(&adapter->napi);
2343 atl1c_irq_enable(adapter);
2344 atl1c_check_link_status(adapter);
2345 netif_start_queue(netdev);
2346 return err;
2347
2348err_up:
2349err_alloc_rx:
2350 atl1c_clean_rx_ring(adapter);
2351 return err;
2352}
2353
0fb1e54e 2354static void atl1c_down(struct atl1c_adapter *adapter)
43250ddd
JY		 2355{
2356 struct net_device *netdev = adapter->netdev;
2357
2358 atl1c_del_timer(adapter);
cb190546 2359 adapter->work_event = 0; /* clear all event */
43250ddd
JY		 2360 /* signal that we're down so the interrupt handler does not
2361 * reschedule our watchdog timer */
2362 set_bit(__AT_DOWN, &adapter->flags);
2363 netif_carrier_off(netdev);
2364 napi_disable(&adapter->napi);
2365 atl1c_irq_disable(adapter);
2366 atl1c_free_irq(adapter);
43250ddd
JY		 2367 /* reset MAC to disable all RX/TX */
2368 atl1c_reset_mac(&adapter->hw);
2369 msleep(1);
2370
2371 adapter->link_speed = SPEED_0;
2372 adapter->link_duplex = -1;
2373 atl1c_clean_tx_ring(adapter, atl1c_trans_normal);
2374 atl1c_clean_tx_ring(adapter, atl1c_trans_high);
2375 atl1c_clean_rx_ring(adapter);
2376}
2377
2378/*
2379 * atl1c_open - Called when a network interface is made active
2380 * @netdev: network interface device structure
2381 *
2382 * Returns 0 on success, negative value on failure
2383 *
2384 * The open entry point is called when a network interface is made
2385 * active by the system (IFF_UP). At this point all resources needed
2386 * for transmit and receive operations are allocated, the interrupt
2387 * handler is registered with the OS, the watchdog timer is started,
2388 * and the stack is notified that the interface is ready.
2389 */
2390static int atl1c_open(struct net_device *netdev)
2391{
2392 struct atl1c_adapter *adapter = netdev_priv(netdev);
2393 int err;
2394
2395 /* disallow open during test */
2396 if (test_bit(__AT_TESTING, &adapter->flags))
2397 return -EBUSY;
2398
2399 /* allocate rx/tx dma buffer & descriptors */
2400 err = atl1c_setup_ring_resources(adapter);
2401 if (unlikely(err))
2402 return err;
2403
2404 err = atl1c_up(adapter);
2405 if (unlikely(err))
2406 goto err_up;
2407
2408 if (adapter->hw.ctrl_flags & ATL1C_FPGA_VERSION) {
2409 u32 phy_data;
2410
2411 AT_READ_REG(&adapter->hw, REG_MDIO_CTRL, &phy_data);
2412 phy_data |= MDIO_AP_EN;
2413 AT_WRITE_REG(&adapter->hw, REG_MDIO_CTRL, phy_data);
2414 }
2415 return 0;
2416
2417err_up:
2418 atl1c_free_irq(adapter);
2419 atl1c_free_ring_resources(adapter);
2420 atl1c_reset_mac(&adapter->hw);
2421 return err;
2422}
2423
2424/*
2425 * atl1c_close - Disables a network interface
2426 * @netdev: network interface device structure
2427 *
2428 * Returns 0, this is not allowed to fail
2429 *
2430 * The close entry point is called when an interface is de-activated
2431 * by the OS. The hardware is still under the drivers control, but
2432 * needs to be disabled. A global MAC reset is issued to stop the
2433 * hardware, and all transmit and receive resources are freed.
2434 */
2435static int atl1c_close(struct net_device *netdev)
2436{
2437 struct atl1c_adapter *adapter = netdev_priv(netdev);
2438
2439 WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
2440 atl1c_down(adapter);
2441 atl1c_free_ring_resources(adapter);
2442 return 0;
2443}
2444
762e3023 2445static int atl1c_suspend(struct device *dev)
43250ddd 2446{
762e3023 2447 struct pci_dev *pdev = to_pci_dev(dev);
43250ddd
JY		 2448 struct net_device *netdev = pci_get_drvdata(pdev);
2449 struct atl1c_adapter *adapter = netdev_priv(netdev);
2450 struct atl1c_hw *hw = &adapter->hw;
8f574b35
JY		 2451 u32 mac_ctrl_data = 0;
2452 u32 master_ctrl_data = 0;
55865c66 2453 u32 wol_ctrl_data = 0;
8f574b35 2454 u16 mii_intr_status_data = 0;
43250ddd 2455 u32 wufc = adapter->wol;
43250ddd 2456
8f574b35 2457 atl1c_disable_l0s_l1(hw);
43250ddd
JY		 2458 if (netif_running(netdev)) {
2459 WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
2460 atl1c_down(adapter);
2461 }
2462 netif_device_detach(netdev);
8f574b35
JY		 2463
2464 if (wufc)
2465 if (atl1c_phy_power_saving(hw) != 0)
2466 dev_dbg(&pdev->dev, "phy power saving failed");
2467
2468 AT_READ_REG(hw, REG_MASTER_CTRL, &master_ctrl_data);
2469 AT_READ_REG(hw, REG_MAC_CTRL, &mac_ctrl_data);
2470
2471 master_ctrl_data &= ~MASTER_CTRL_CLK_SEL_DIS;
2472 mac_ctrl_data &= ~(MAC_CTRL_PRMLEN_MASK << MAC_CTRL_PRMLEN_SHIFT);
2473 mac_ctrl_data |= (((u32)adapter->hw.preamble_len &
2474 MAC_CTRL_PRMLEN_MASK) <<
2475 MAC_CTRL_PRMLEN_SHIFT);
2476 mac_ctrl_data &= ~(MAC_CTRL_SPEED_MASK << MAC_CTRL_SPEED_SHIFT);
2477 mac_ctrl_data &= ~MAC_CTRL_DUPLX;
2478
43250ddd 2479 if (wufc) {
8f574b35
JY		 2480 mac_ctrl_data |= MAC_CTRL_RX_EN;
2481 if (adapter->link_speed == SPEED_1000 ||
2482 adapter->link_speed == SPEED_0) {
2483 mac_ctrl_data |= atl1c_mac_speed_1000 <<
2484 MAC_CTRL_SPEED_SHIFT;
2485 mac_ctrl_data |= MAC_CTRL_DUPLX;
2486 } else
2487 mac_ctrl_data |= atl1c_mac_speed_10_100 <<
2488 MAC_CTRL_SPEED_SHIFT;
2489
2490 if (adapter->link_duplex == DUPLEX_FULL)
2491 mac_ctrl_data |= MAC_CTRL_DUPLX;
2492
43250ddd
JY		 2493 /* turn on magic packet wol */
2494 if (wufc & AT_WUFC_MAG)
8f574b35 2495 wol_ctrl_data |= WOL_MAGIC_EN | WOL_MAGIC_PME_EN;
43250ddd
JY		 2496
2497 if (wufc & AT_WUFC_LNKC) {
43250ddd
JY		 2498 wol_ctrl_data |= WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN;
2499 /* only link up can wake up */
2500 if (atl1c_write_phy_reg(hw, MII_IER, IER_LINK_UP) != 0) {
8f574b35
JY		 2501 dev_dbg(&pdev->dev, "%s: read write phy "
2502 "register failed.\n",
2503 atl1c_driver_name);
43250ddd
JY		 2504 }
2505 }
2506 /* clear phy interrupt */
2507 atl1c_read_phy_reg(hw, MII_ISR, &mii_intr_status_data);
2508 /* Config MAC Ctrl register */
43250ddd
JY		 2509 if (adapter->vlgrp)
2510 mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
2511
2512 /* magic packet maybe Broadcast&multicast&Unicast frame */
2513 if (wufc & AT_WUFC_MAG)
2514 mac_ctrl_data |= MAC_CTRL_BC_EN;
2515
8f574b35
JY		 2516 dev_dbg(&pdev->dev,
2517 "%s: suspend MAC=0x%x\n",
2518 atl1c_driver_name, mac_ctrl_data);
43250ddd
JY		 2519 AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
2520 AT_WRITE_REG(hw, REG_WOL_CTRL, wol_ctrl_data);
2521 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
2522
8f574b35
JY		 2523 AT_WRITE_REG(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT |
2524 GPHY_CTRL_EXT_RESET);
8f574b35
JY		 2525 } else {
2526 AT_WRITE_REG(hw, REG_GPHY_CTRL, GPHY_CTRL_POWER_SAVING);
2527 master_ctrl_data |= MASTER_CTRL_CLK_SEL_DIS;
2528 mac_ctrl_data |= atl1c_mac_speed_10_100 << MAC_CTRL_SPEED_SHIFT;
2529 mac_ctrl_data |= MAC_CTRL_DUPLX;
2530 AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
2531 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
2532 AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
2533 hw->phy_configured = false; /* re-init PHY when resume */
43250ddd 2534 }
43250ddd 2535
43250ddd
JY		 2536 return 0;
2537}
2538
762e3023 2539static int atl1c_resume(struct device *dev)
43250ddd 2540{
762e3023 2541 struct pci_dev *pdev = to_pci_dev(dev);
43250ddd
JY		 2542 struct net_device *netdev = pci_get_drvdata(pdev);
2543 struct atl1c_adapter *adapter = netdev_priv(netdev);
2544
43250ddd 2545 AT_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
8f574b35
JY		 2546 atl1c_reset_pcie(&adapter->hw, ATL1C_PCIE_L0S_L1_DISABLE |
2547 ATL1C_PCIE_PHY_RESET);
43250ddd
JY		 2548
2549 atl1c_phy_reset(&adapter->hw);
2550 atl1c_reset_mac(&adapter->hw);
8f574b35
JY		 2551 atl1c_phy_init(&adapter->hw);
2552
2553#if 0
2554 AT_READ_REG(&adapter->hw, REG_PM_CTRLSTAT, &pm_data);
2555 pm_data &= ~PM_CTRLSTAT_PME_EN;
2556 AT_WRITE_REG(&adapter->hw, REG_PM_CTRLSTAT, pm_data);
2557#endif
2558
43250ddd
JY		 2559 netif_device_attach(netdev);
2560 if (netif_running(netdev))
2561 atl1c_up(adapter);
2562
2563 return 0;
2564}
2565
2566static void atl1c_shutdown(struct pci_dev *pdev)
2567{
762e3023
RW		 2568 struct net_device *netdev = pci_get_drvdata(pdev);
2569 struct atl1c_adapter *adapter = netdev_priv(netdev);
2570
2571 atl1c_suspend(&pdev->dev);
2572 pci_wake_from_d3(pdev, adapter->wol);
2573 pci_set_power_state(pdev, PCI_D3hot);
43250ddd
JY		 2574}
2575
2576static const struct net_device_ops atl1c_netdev_ops = {
2577 .ndo_open = atl1c_open,
2578 .ndo_stop = atl1c_close,
2579 .ndo_validate_addr = eth_validate_addr,
2580 .ndo_start_xmit = atl1c_xmit_frame,
2581 .ndo_set_mac_address = atl1c_set_mac_addr,
2582 .ndo_set_multicast_list = atl1c_set_multi,
2583 .ndo_change_mtu = atl1c_change_mtu,
2584 .ndo_do_ioctl = atl1c_ioctl,
2585 .ndo_tx_timeout = atl1c_tx_timeout,
2586 .ndo_get_stats = atl1c_get_stats,
2587 .ndo_vlan_rx_register = atl1c_vlan_rx_register,
2588#ifdef CONFIG_NET_POLL_CONTROLLER
2589 .ndo_poll_controller = atl1c_netpoll,
2590#endif
2591};
2592
2593static int atl1c_init_netdev(struct net_device *netdev, struct pci_dev *pdev)
2594{
2595 SET_NETDEV_DEV(netdev, &pdev->dev);
2596 pci_set_drvdata(pdev, netdev);
2597
2598 netdev->irq = pdev->irq;
2599 netdev->netdev_ops = &atl1c_netdev_ops;
2600 netdev->watchdog_timeo = AT_TX_WATCHDOG;
2601 atl1c_set_ethtool_ops(netdev);
2602
2603 /* TODO: add when ready */
2604 netdev->features = NETIF_F_SG |
2605 NETIF_F_HW_CSUM |
2606 NETIF_F_HW_VLAN_TX |
2607 NETIF_F_HW_VLAN_RX |
2608 NETIF_F_TSO |
2609 NETIF_F_TSO6;
2610 return 0;
2611}
2612
2613/*
2614 * atl1c_probe - Device Initialization Routine
2615 * @pdev: PCI device information struct
2616 * @ent: entry in atl1c_pci_tbl
2617 *
2618 * Returns 0 on success, negative on failure
2619 *
2620 * atl1c_probe initializes an adapter identified by a pci_dev structure.
2621 * The OS initialization, configuring of the adapter private structure,
2622 * and a hardware reset occur.
2623 */
2624static int __devinit atl1c_probe(struct pci_dev *pdev,
2625 const struct pci_device_id *ent)
2626{
2627 struct net_device *netdev;
2628 struct atl1c_adapter *adapter;
2629 static int cards_found;
2630
2631 int err = 0;
2632
2633 /* enable device (incl. PCI PM wakeup and hotplug setup) */
2634 err = pci_enable_device_mem(pdev);
2635 if (err) {
2636 dev_err(&pdev->dev, "cannot enable PCI device\n");
2637 return err;
2638 }
2639
2640 /*
2641 * The atl1c chip can DMA to 64-bit addresses, but it uses a single
2642 * shared register for the high 32 bits, so only a single, aligned,
2643 * 4 GB physical address range can be used at a time.
2644 *
2645 * Supporting 64-bit DMA on this hardware is more trouble than it's
2646 * worth. It is far easier to limit to 32-bit DMA than update
2647 * various kernel subsystems to support the mechanics required by a
2648 * fixed-high-32-bit system.
2649 */
e930438c
YH		 2650 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
2651 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
43250ddd
JY		 2652 dev_err(&pdev->dev, "No usable DMA configuration,aborting\n");
2653 goto err_dma;
2654 }
2655
2656 err = pci_request_regions(pdev, atl1c_driver_name);
2657 if (err) {
2658 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
2659 goto err_pci_reg;
2660 }
2661
2662 pci_set_master(pdev);
2663
2664 netdev = alloc_etherdev(sizeof(struct atl1c_adapter));
2665 if (netdev == NULL) {
2666 err = -ENOMEM;
2667 dev_err(&pdev->dev, "etherdev alloc failed\n");
2668 goto err_alloc_etherdev;
2669 }
2670
2671 err = atl1c_init_netdev(netdev, pdev);
2672 if (err) {
2673 dev_err(&pdev->dev, "init netdevice failed\n");
2674 goto err_init_netdev;
2675 }
2676 adapter = netdev_priv(netdev);
2677 adapter->bd_number = cards_found;
2678 adapter->netdev = netdev;
2679 adapter->pdev = pdev;
2680 adapter->hw.adapter = adapter;
2681 adapter->msg_enable = netif_msg_init(-1, atl1c_default_msg);
2682 adapter->hw.hw_addr = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
2683 if (!adapter->hw.hw_addr) {
2684 err = -EIO;
2685 dev_err(&pdev->dev, "cannot map device registers\n");
2686 goto err_ioremap;
2687 }
2688 netdev->base_addr = (unsigned long)adapter->hw.hw_addr;
2689
2690 /* init mii data */
2691 adapter->mii.dev = netdev;
2692 adapter->mii.mdio_read = atl1c_mdio_read;
2693 adapter->mii.mdio_write = atl1c_mdio_write;
2694 adapter->mii.phy_id_mask = 0x1f;
2695 adapter->mii.reg_num_mask = MDIO_REG_ADDR_MASK;
2696 netif_napi_add(netdev, &adapter->napi, atl1c_clean, 64);
2697 setup_timer(&adapter->phy_config_timer, atl1c_phy_config,
2698 (unsigned long)adapter);
2699 /* setup the private structure */
2700 err = atl1c_sw_init(adapter);
2701 if (err) {
2702 dev_err(&pdev->dev, "net device private data init failed\n");
2703 goto err_sw_init;
2704 }
2705 atl1c_reset_pcie(&adapter->hw, ATL1C_PCIE_L0S_L1_DISABLE |
2706 ATL1C_PCIE_PHY_RESET);
2707
2708 /* Init GPHY as early as possible due to power saving issue */
2709 atl1c_phy_reset(&adapter->hw);
2710
2711 err = atl1c_reset_mac(&adapter->hw);
2712 if (err) {
2713 err = -EIO;
2714 goto err_reset;
2715 }
2716
43250ddd
JY		 2717 /* reset the controller to
2718 * put the device in a known good starting state */
2719 err = atl1c_phy_init(&adapter->hw);
2720 if (err) {
2721 err = -EIO;
2722 goto err_reset;
2723 }
2724 if (atl1c_read_mac_addr(&adapter->hw) != 0) {
2725 err = -EIO;
2726 dev_err(&pdev->dev, "get mac address failed\n");
2727 goto err_eeprom;
2728 }
2729 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
2730 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
2731 if (netif_msg_probe(adapter))
82991172 2732 dev_dbg(&pdev->dev, "mac address : %pM\n",
2733 adapter->hw.mac_addr);
43250ddd
JY		 2734
2735 atl1c_hw_set_mac_addr(&adapter->hw);
cb190546
JY		 2736 INIT_WORK(&adapter->common_task, atl1c_common_task);
2737 adapter->work_event = 0;
43250ddd
JY		 2738 err = register_netdev(netdev);
2739 if (err) {
2740 dev_err(&pdev->dev, "register netdevice failed\n");
2741 goto err_register;
2742 }
2743
2744 if (netif_msg_probe(adapter))
2745 dev_info(&pdev->dev, "version %s\n", ATL1C_DRV_VERSION);
2746 cards_found++;
2747 return 0;
2748
2749err_reset:
2750err_register:
2751err_sw_init:
2752err_eeprom:
2753 iounmap(adapter->hw.hw_addr);
2754err_init_netdev:
2755err_ioremap:
2756 free_netdev(netdev);
2757err_alloc_etherdev:
2758 pci_release_regions(pdev);
2759err_pci_reg:
2760err_dma:
2761 pci_disable_device(pdev);
2762 return err;
2763}
2764
2765/*
2766 * atl1c_remove - Device Removal Routine
2767 * @pdev: PCI device information struct
2768 *
2769 * atl1c_remove is called by the PCI subsystem to alert the driver
2770 * that it should release a PCI device. The could be caused by a
2771 * Hot-Plug event, or because the driver is going to be removed from
2772 * memory.
2773 */
2774static void __devexit atl1c_remove(struct pci_dev *pdev)
2775{
2776 struct net_device *netdev = pci_get_drvdata(pdev);
2777 struct atl1c_adapter *adapter = netdev_priv(netdev);
2778
2779 unregister_netdev(netdev);
2780 atl1c_phy_disable(&adapter->hw);
2781
2782 iounmap(adapter->hw.hw_addr);
2783
2784 pci_release_regions(pdev);
2785 pci_disable_device(pdev);
2786 free_netdev(netdev);
2787}
2788
2789/*
2790 * atl1c_io_error_detected - called when PCI error is detected
2791 * @pdev: Pointer to PCI device
2792 * @state: The current pci connection state
2793 *
2794 * This function is called after a PCI bus error affecting
2795 * this device has been detected.
2796 */
2797static pci_ers_result_t atl1c_io_error_detected(struct pci_dev *pdev,
2798 pci_channel_state_t state)
2799{
2800 struct net_device *netdev = pci_get_drvdata(pdev);
2801 struct atl1c_adapter *adapter = netdev_priv(netdev);
2802
2803 netif_device_detach(netdev);
2804
005fb4f0
DN		 2805 if (state == pci_channel_io_perm_failure)
2806 return PCI_ERS_RESULT_DISCONNECT;
2807
43250ddd
JY		 2808 if (netif_running(netdev))
2809 atl1c_down(adapter);
2810
2811 pci_disable_device(pdev);
2812
2813 /* Request a slot slot reset. */
2814 return PCI_ERS_RESULT_NEED_RESET;
2815}
2816
2817/*
2818 * atl1c_io_slot_reset - called after the pci bus has been reset.
2819 * @pdev: Pointer to PCI device
2820 *
2821 * Restart the card from scratch, as if from a cold-boot. Implementation
2822 * resembles the first-half of the e1000_resume routine.
2823 */
2824static pci_ers_result_t atl1c_io_slot_reset(struct pci_dev *pdev)
2825{
2826 struct net_device *netdev = pci_get_drvdata(pdev);
2827 struct atl1c_adapter *adapter = netdev_priv(netdev);
2828
2829 if (pci_enable_device(pdev)) {
2830 if (netif_msg_hw(adapter))
2831 dev_err(&pdev->dev,
2832 "Cannot re-enable PCI device after reset\n");
2833 return PCI_ERS_RESULT_DISCONNECT;
2834 }
2835 pci_set_master(pdev);
2836
2837 pci_enable_wake(pdev, PCI_D3hot, 0);
2838 pci_enable_wake(pdev, PCI_D3cold, 0);
2839
2840 atl1c_reset_mac(&adapter->hw);
2841
2842 return PCI_ERS_RESULT_RECOVERED;
2843}
2844
2845/*
2846 * atl1c_io_resume - called when traffic can start flowing again.
2847 * @pdev: Pointer to PCI device
2848 *
2849 * This callback is called when the error recovery driver tells us that
2850 * its OK to resume normal operation. Implementation resembles the
2851 * second-half of the atl1c_resume routine.
2852 */
2853static void atl1c_io_resume(struct pci_dev *pdev)
2854{
2855 struct net_device *netdev = pci_get_drvdata(pdev);
2856 struct atl1c_adapter *adapter = netdev_priv(netdev);
2857
2858 if (netif_running(netdev)) {
2859 if (atl1c_up(adapter)) {
2860 if (netif_msg_hw(adapter))
2861 dev_err(&pdev->dev,
2862 "Cannot bring device back up after reset\n");
2863 return;
2864 }
2865 }
2866
2867 netif_device_attach(netdev);
2868}
2869
2870static struct pci_error_handlers atl1c_err_handler = {
2871 .error_detected = atl1c_io_error_detected,
2872 .slot_reset = atl1c_io_slot_reset,
2873 .resume = atl1c_io_resume,
2874};
2875
762e3023
RW		 2876static SIMPLE_DEV_PM_OPS(atl1c_pm_ops, atl1c_suspend, atl1c_resume);
2877
43250ddd
JY		 2878static struct pci_driver atl1c_driver = {
2879 .name = atl1c_driver_name,
2880 .id_table = atl1c_pci_tbl,
2881 .probe = atl1c_probe,
2882 .remove = __devexit_p(atl1c_remove),
43250ddd 2883 .shutdown = atl1c_shutdown,
762e3023
RW		 2884 .err_handler = &atl1c_err_handler,
2885 .driver.pm = &atl1c_pm_ops,
43250ddd
JY		 2886};
2887
2888/*
2889 * atl1c_init_module - Driver Registration Routine
2890 *
2891 * atl1c_init_module is the first routine called when the driver is
2892 * loaded. All it does is register with the PCI subsystem.
2893 */
2894static int __init atl1c_init_module(void)
2895{
2896 return pci_register_driver(&atl1c_driver);
2897}
2898
2899/*
2900 * atl1c_exit_module - Driver Exit Cleanup Routine
2901 *
2902 * atl1c_exit_module is called just before the driver is removed
2903 * from memory.
2904 */
2905static void __exit atl1c_exit_module(void)
2906{
2907 pci_unregister_driver(&atl1c_driver);
2908}
2909
2910module_init(atl1c_init_module);
2911module_exit(atl1c_exit_module);
kernel source for telekom puls (alcatel/mediatek)