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[NET]: Nuke SET_MODULE_OWNER macro.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / amd8111e.c
CommitLineData
1da177e4 1
6aa20a22
JG		 2/* Advanced Micro Devices Inc. AMD8111E Linux Network Driver
3 * Copyright (C) 2004 Advanced Micro Devices
4 *
1da177e4 5 *
1da177e4
LT		 6 * Copyright 2001,2002 Jeff Garzik <jgarzik@mandrakesoft.com> [ 8139cp.c,tg3.c ]
7 * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)[ tg3.c]
8 * Copyright 1996-1999 Thomas Bogendoerfer [ pcnet32.c ]
9 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
10 * Copyright 1993 United States Government as represented by the
11 * Director, National Security Agency.[ pcnet32.c ]
12 * Carsten Langgaard, carstenl@mips.com [ pcnet32.c ]
13 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
14 *
6aa20a22 15 *
1da177e4
LT		 16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
6aa20a22 28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
1da177e4 29 * USA
6aa20a22 30
1da177e4
LT		 31Module Name:
32
33 amd8111e.c
34
35Abstract:
6aa20a22
JG		 36
37 AMD8111 based 10/100 Ethernet Controller Driver.
1da177e4
LT		 38
39Environment:
40
41 Kernel Mode
42
43Revision History:
44 3.0.0
45 Initial Revision.
46 3.0.1
47 1. Dynamic interrupt coalescing.
48 2. Removed prev_stats.
49 3. MII support.
50 4. Dynamic IPG support
51 3.0.2 05/29/2003
52 1. Bug fix: Fixed failure to send jumbo packets larger than 4k.
53 2. Bug fix: Fixed VLAN support failure.
54 3. Bug fix: Fixed receive interrupt coalescing bug.
55 4. Dynamic IPG support is disabled by default.
56 3.0.3 06/05/2003
57 1. Bug fix: Fixed failure to close the interface if SMP is enabled.
58 3.0.4 12/09/2003
59 1. Added set_mac_address routine for bonding driver support.
60 2. Tested the driver for bonding support
6aa20a22 61 3. Bug fix: Fixed mismach in actual receive buffer lenth and lenth
1da177e4 62 indicated to the h/w.
6aa20a22 63 4. Modified amd8111e_rx() routine to receive all the received packets
1da177e4
LT		 64 in the first interrupt.
65 5. Bug fix: Corrected rx_errors reported in get_stats() function.
66 3.0.5 03/22/2004
6aa20a22 67 1. Added NAPI support
1da177e4
LT		 68
69*/
70
71
1da177e4
LT		 72#include <linux/module.h>
73#include <linux/kernel.h>
74#include <linux/types.h>
75#include <linux/compiler.h>
76#include <linux/slab.h>
77#include <linux/delay.h>
78#include <linux/init.h>
79#include <linux/ioport.h>
80#include <linux/pci.h>
81#include <linux/netdevice.h>
82#include <linux/etherdevice.h>
83#include <linux/skbuff.h>
84#include <linux/ethtool.h>
85#include <linux/mii.h>
86#include <linux/if_vlan.h>
6aa20a22 87#include <linux/ctype.h>
1da177e4 88#include <linux/crc32.h>
cac8c81a 89#include <linux/dma-mapping.h>
1da177e4
LT		 90
91#include <asm/system.h>
92#include <asm/io.h>
93#include <asm/byteorder.h>
94#include <asm/uaccess.h>
95
96#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
97#define AMD8111E_VLAN_TAG_USED 1
98#else
99#define AMD8111E_VLAN_TAG_USED 0
100#endif
101
102#include "amd8111e.h"
103#define MODULE_NAME "amd8111e"
d5b20697 104#define MODULE_VERS "3.0.6"
1da177e4 105MODULE_AUTHOR("Advanced Micro Devices, Inc.");
d5b20697 106MODULE_DESCRIPTION ("AMD8111 based 10/100 Ethernet Controller. Driver Version 3.0.6");
1da177e4
LT		 107MODULE_LICENSE("GPL");
108MODULE_DEVICE_TABLE(pci, amd8111e_pci_tbl);
109module_param_array(speed_duplex, int, NULL, 0);
110MODULE_PARM_DESC(speed_duplex, "Set device speed and duplex modes, 0: Auto Negotitate, 1: 10Mbps Half Duplex, 2: 10Mbps Full Duplex, 3: 100Mbps Half Duplex, 4: 100Mbps Full Duplex");
111module_param_array(coalesce, bool, NULL, 0);
112MODULE_PARM_DESC(coalesce, "Enable or Disable interrupt coalescing, 1: Enable, 0: Disable");
113module_param_array(dynamic_ipg, bool, NULL, 0);
114MODULE_PARM_DESC(dynamic_ipg, "Enable or Disable dynamic IPG, 1: Enable, 0: Disable");
115
116static struct pci_device_id amd8111e_pci_tbl[] = {
6aa20a22 117
1da177e4
LT		 118 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD8111E_7462,
119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
120 { 0, }
121
122};
6aa20a22 123/*
1da177e4
LT		 124This function will read the PHY registers.
125*/
126static int amd8111e_read_phy(struct amd8111e_priv* lp, int phy_id, int reg, u32* val)
127{
128 void __iomem *mmio = lp->mmio;
129 unsigned int reg_val;
130 unsigned int repeat= REPEAT_CNT;
131
132 reg_val = readl(mmio + PHY_ACCESS);
133 while (reg_val & PHY_CMD_ACTIVE)
134 reg_val = readl( mmio + PHY_ACCESS );
135
136 writel( PHY_RD_CMD | ((phy_id & 0x1f) << 21) |
137 ((reg & 0x1f) << 16), mmio +PHY_ACCESS);
138 do{
139 reg_val = readl(mmio + PHY_ACCESS);
140 udelay(30); /* It takes 30 us to read/write data */
141 } while (--repeat && (reg_val & PHY_CMD_ACTIVE));
142 if(reg_val & PHY_RD_ERR)
143 goto err_phy_read;
6aa20a22 144
1da177e4
LT		 145 *val = reg_val & 0xffff;
146 return 0;
6aa20a22 147err_phy_read:
1da177e4
LT		 148 *val = 0;
149 return -EINVAL;
6aa20a22 150
1da177e4
LT		 151}
152
6aa20a22
JG		 153/*
154This function will write into PHY registers.
1da177e4
LT		 155*/
156static int amd8111e_write_phy(struct amd8111e_priv* lp,int phy_id, int reg, u32 val)
157{
632155e6 158 unsigned int repeat = REPEAT_CNT;
1da177e4
LT		 159 void __iomem *mmio = lp->mmio;
160 unsigned int reg_val;
161
162 reg_val = readl(mmio + PHY_ACCESS);
163 while (reg_val & PHY_CMD_ACTIVE)
164 reg_val = readl( mmio + PHY_ACCESS );
165
166 writel( PHY_WR_CMD | ((phy_id & 0x1f) << 21) |
167 ((reg & 0x1f) << 16)|val, mmio + PHY_ACCESS);
168
169 do{
170 reg_val = readl(mmio + PHY_ACCESS);
171 udelay(30); /* It takes 30 us to read/write the data */
172 } while (--repeat && (reg_val & PHY_CMD_ACTIVE));
6aa20a22 173
1da177e4
LT		 174 if(reg_val & PHY_RD_ERR)
175 goto err_phy_write;
6aa20a22 176
1da177e4
LT		 177 return 0;
178
6aa20a22 179err_phy_write:
1da177e4 180 return -EINVAL;
6aa20a22 181
1da177e4 182}
6aa20a22 183/*
1da177e4 184This is the mii register read function provided to the mii interface.
6aa20a22 185*/
1da177e4
LT		 186static int amd8111e_mdio_read(struct net_device * dev, int phy_id, int reg_num)
187{
188 struct amd8111e_priv* lp = netdev_priv(dev);
189 unsigned int reg_val;
190
191 amd8111e_read_phy(lp,phy_id,reg_num,&reg_val);
192 return reg_val;
6aa20a22 193
1da177e4
LT		 194}
195
6aa20a22 196/*
1da177e4 197This is the mii register write function provided to the mii interface.
6aa20a22 198*/
1da177e4
LT		 199static void amd8111e_mdio_write(struct net_device * dev, int phy_id, int reg_num, int val)
200{
201 struct amd8111e_priv* lp = netdev_priv(dev);
202
203 amd8111e_write_phy(lp, phy_id, reg_num, val);
204}
205
206/*
207This function will set PHY speed. During initialization sets the original speed to 100 full.
208*/
209static void amd8111e_set_ext_phy(struct net_device *dev)
210{
211 struct amd8111e_priv *lp = netdev_priv(dev);
212 u32 bmcr,advert,tmp;
6aa20a22 213
1da177e4
LT		 214 /* Determine mii register values to set the speed */
215 advert = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_ADVERTISE);
216 tmp = advert & ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
217 switch (lp->ext_phy_option){
218
219 default:
220 case SPEED_AUTONEG: /* advertise all values */
221 tmp |= ( ADVERTISE_10HALF|ADVERTISE_10FULL|
222 ADVERTISE_100HALF|ADVERTISE_100FULL) ;
223 break;
224 case SPEED10_HALF:
225 tmp |= ADVERTISE_10HALF;
226 break;
227 case SPEED10_FULL:
228 tmp |= ADVERTISE_10FULL;
229 break;
6aa20a22 230 case SPEED100_HALF:
1da177e4
LT		 231 tmp |= ADVERTISE_100HALF;
232 break;
233 case SPEED100_FULL:
234 tmp |= ADVERTISE_100FULL;
235 break;
236 }
237
238 if(advert != tmp)
239 amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_ADVERTISE, tmp);
240 /* Restart auto negotiation */
241 bmcr = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_BMCR);
242 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
243 amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_BMCR, bmcr);
244
245}
246
6aa20a22
JG		 247/*
248This function will unmap skb->data space and will free
1da177e4
LT		 249all transmit and receive skbuffs.
250*/
251static int amd8111e_free_skbs(struct net_device *dev)
252{
253 struct amd8111e_priv *lp = netdev_priv(dev);
254 struct sk_buff* rx_skbuff;
255 int i;
256
257 /* Freeing transmit skbs */
258 for(i = 0; i < NUM_TX_BUFFERS; i++){
259 if(lp->tx_skbuff[i]){
260 pci_unmap_single(lp->pci_dev,lp->tx_dma_addr[i], lp->tx_skbuff[i]->len,PCI_DMA_TODEVICE);
261 dev_kfree_skb (lp->tx_skbuff[i]);
262 lp->tx_skbuff[i] = NULL;
263 lp->tx_dma_addr[i] = 0;
264 }
265 }
266 /* Freeing previously allocated receive buffers */
267 for (i = 0; i < NUM_RX_BUFFERS; i++){
268 rx_skbuff = lp->rx_skbuff[i];
269 if(rx_skbuff != NULL){
270 pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[i],
271 lp->rx_buff_len - 2,PCI_DMA_FROMDEVICE);
272 dev_kfree_skb(lp->rx_skbuff[i]);
273 lp->rx_skbuff[i] = NULL;
274 lp->rx_dma_addr[i] = 0;
275 }
276 }
6aa20a22 277
1da177e4
LT		 278 return 0;
279}
280
281/*
282This will set the receive buffer length corresponding to the mtu size of networkinterface.
283*/
284static inline void amd8111e_set_rx_buff_len(struct net_device* dev)
285{
286 struct amd8111e_priv* lp = netdev_priv(dev);
287 unsigned int mtu = dev->mtu;
6aa20a22 288
1da177e4
LT		 289 if (mtu > ETH_DATA_LEN){
290 /* MTU + ethernet header + FCS
291 + optional VLAN tag + skb reserve space 2 */
292
293 lp->rx_buff_len = mtu + ETH_HLEN + 10;
294 lp->options |= OPTION_JUMBO_ENABLE;
295 } else{
296 lp->rx_buff_len = PKT_BUFF_SZ;
297 lp->options &= ~OPTION_JUMBO_ENABLE;
298 }
299}
300
6aa20a22 301/*
1da177e4
LT		 302This function will free all the previously allocated buffers, determine new receive buffer length and will allocate new receive buffers. This function also allocates and initializes both the transmitter and receive hardware descriptors.
303 */
304static int amd8111e_init_ring(struct net_device *dev)
305{
306 struct amd8111e_priv *lp = netdev_priv(dev);
307 int i;
308
309 lp->rx_idx = lp->tx_idx = 0;
310 lp->tx_complete_idx = 0;
311 lp->tx_ring_idx = 0;
6aa20a22 312
1da177e4
LT		 313
314 if(lp->opened)
315 /* Free previously allocated transmit and receive skbs */
6aa20a22 316 amd8111e_free_skbs(dev);
1da177e4
LT		 317
318 else{
319 /* allocate the tx and rx descriptors */
6aa20a22 320 if((lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
1da177e4
LT		 321 sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,
322 &lp->tx_ring_dma_addr)) == NULL)
6aa20a22 323
1da177e4 324 goto err_no_mem;
6aa20a22
JG		 325
326 if((lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
1da177e4
LT		 327 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,
328 &lp->rx_ring_dma_addr)) == NULL)
6aa20a22 329
1da177e4
LT		 330 goto err_free_tx_ring;
331
332 }
333 /* Set new receive buff size */
334 amd8111e_set_rx_buff_len(dev);
335
336 /* Allocating receive skbs */
337 for (i = 0; i < NUM_RX_BUFFERS; i++) {
338
339 if (!(lp->rx_skbuff[i] = dev_alloc_skb(lp->rx_buff_len))) {
340 /* Release previos allocated skbs */
341 for(--i; i >= 0 ;i--)
342 dev_kfree_skb(lp->rx_skbuff[i]);
343 goto err_free_rx_ring;
344 }
345 skb_reserve(lp->rx_skbuff[i],2);
346 }
347 /* Initilaizing receive descriptors */
348 for (i = 0; i < NUM_RX_BUFFERS; i++) {
6aa20a22 349 lp->rx_dma_addr[i] = pci_map_single(lp->pci_dev,
1da177e4
LT		 350 lp->rx_skbuff[i]->data,lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
351
352 lp->rx_ring[i].buff_phy_addr = cpu_to_le32(lp->rx_dma_addr[i]);
353 lp->rx_ring[i].buff_count = cpu_to_le16(lp->rx_buff_len-2);
354 wmb();
355 lp->rx_ring[i].rx_flags = cpu_to_le16(OWN_BIT);
356 }
357
358 /* Initializing transmit descriptors */
359 for (i = 0; i < NUM_TX_RING_DR; i++) {
360 lp->tx_ring[i].buff_phy_addr = 0;
361 lp->tx_ring[i].tx_flags = 0;
362 lp->tx_ring[i].buff_count = 0;
363 }
364
365 return 0;
366
367err_free_rx_ring:
6aa20a22
JG		 368
369 pci_free_consistent(lp->pci_dev,
1da177e4
LT		 370 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,lp->rx_ring,
371 lp->rx_ring_dma_addr);
372
373err_free_tx_ring:
6aa20a22 374
1da177e4 375 pci_free_consistent(lp->pci_dev,
6aa20a22 376 sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,lp->tx_ring,
1da177e4
LT		 377 lp->tx_ring_dma_addr);
378
379err_no_mem:
380 return -ENOMEM;
381}
382/* This function will set the interrupt coalescing according to the input arguments */
383static int amd8111e_set_coalesce(struct net_device * dev, enum coal_mode cmod)
384{
385 unsigned int timeout;
386 unsigned int event_count;
387
388 struct amd8111e_priv *lp = netdev_priv(dev);
389 void __iomem *mmio = lp->mmio;
390 struct amd8111e_coalesce_conf * coal_conf = &lp->coal_conf;
391
392
393 switch(cmod)
394 {
395 case RX_INTR_COAL :
396 timeout = coal_conf->rx_timeout;
397 event_count = coal_conf->rx_event_count;
6aa20a22
JG		 398 if( timeout > MAX_TIMEOUT ||
399 event_count > MAX_EVENT_COUNT )
1da177e4
LT		 400 return -EINVAL;
401
6aa20a22 402 timeout = timeout * DELAY_TIMER_CONV;
1da177e4
LT		 403 writel(VAL0|STINTEN, mmio+INTEN0);
404 writel((u32)DLY_INT_A_R0|( event_count<< 16 )|timeout,
405 mmio+DLY_INT_A);
406 break;
407
408 case TX_INTR_COAL :
409 timeout = coal_conf->tx_timeout;
410 event_count = coal_conf->tx_event_count;
6aa20a22
JG		 411 if( timeout > MAX_TIMEOUT ||
412 event_count > MAX_EVENT_COUNT )
1da177e4
LT		 413 return -EINVAL;
414
6aa20a22
JG		 415
416 timeout = timeout * DELAY_TIMER_CONV;
1da177e4
LT		 417 writel(VAL0|STINTEN,mmio+INTEN0);
418 writel((u32)DLY_INT_B_T0|( event_count<< 16 )|timeout,
419 mmio+DLY_INT_B);
420 break;
421
422 case DISABLE_COAL:
423 writel(0,mmio+STVAL);
424 writel(STINTEN, mmio+INTEN0);
425 writel(0, mmio +DLY_INT_B);
426 writel(0, mmio+DLY_INT_A);
427 break;
6aa20a22 428 case ENABLE_COAL:
1da177e4
LT		 429 /* Start the timer */
430 writel((u32)SOFT_TIMER_FREQ, mmio+STVAL); /* 0.5 sec */
431 writel(VAL0|STINTEN, mmio+INTEN0);
432 break;
433 default:
434 break;
435
436 }
437 return 0;
438
439}
440
6aa20a22
JG		 441/*
442This function initializes the device registers and starts the device.
1da177e4
LT		 443*/
444static int amd8111e_restart(struct net_device *dev)
445{
446 struct amd8111e_priv *lp = netdev_priv(dev);
447 void __iomem *mmio = lp->mmio;
448 int i,reg_val;
449
450 /* stop the chip */
451 writel(RUN, mmio + CMD0);
452
453 if(amd8111e_init_ring(dev))
454 return -ENOMEM;
455
456 /* enable the port manager and set auto negotiation always */
457 writel((u32) VAL1|EN_PMGR, mmio + CMD3 );
6aa20a22
JG		 458 writel((u32)XPHYANE|XPHYRST , mmio + CTRL2);
459
1da177e4
LT		 460 amd8111e_set_ext_phy(dev);
461
462 /* set control registers */
463 reg_val = readl(mmio + CTRL1);
464 reg_val &= ~XMTSP_MASK;
465 writel( reg_val| XMTSP_128 | CACHE_ALIGN, mmio + CTRL1 );
466
467 /* enable interrupt */
6aa20a22 468 writel( APINT5EN | APINT4EN | APINT3EN | APINT2EN | APINT1EN |
1da177e4
LT		 469 APINT0EN | MIIPDTINTEN | MCCIINTEN | MCCINTEN | MREINTEN |
470 SPNDINTEN | MPINTEN | SINTEN | STINTEN, mmio + INTEN0);
471
472 writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0);
473
474 /* initialize tx and rx ring base addresses */
475 writel((u32)lp->tx_ring_dma_addr,mmio + XMT_RING_BASE_ADDR0);
476 writel((u32)lp->rx_ring_dma_addr,mmio+ RCV_RING_BASE_ADDR0);
477
478 writew((u32)NUM_TX_RING_DR, mmio + XMT_RING_LEN0);
479 writew((u16)NUM_RX_RING_DR, mmio + RCV_RING_LEN0);
6aa20a22 480
1da177e4
LT		 481 /* set default IPG to 96 */
482 writew((u32)DEFAULT_IPG,mmio+IPG);
6aa20a22 483 writew((u32)(DEFAULT_IPG-IFS1_DELTA), mmio + IFS1);
1da177e4
LT		 484
485 if(lp->options & OPTION_JUMBO_ENABLE){
486 writel((u32)VAL2|JUMBO, mmio + CMD3);
487 /* Reset REX_UFLO */
488 writel( REX_UFLO, mmio + CMD2);
489 /* Should not set REX_UFLO for jumbo frames */
490 writel( VAL0 | APAD_XMT|REX_RTRY , mmio + CMD2);
491 }else{
492 writel( VAL0 | APAD_XMT | REX_RTRY|REX_UFLO, mmio + CMD2);
493 writel((u32)JUMBO, mmio + CMD3);
494 }
495
496#if AMD8111E_VLAN_TAG_USED
497 writel((u32) VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3);
498#endif
499 writel( VAL0 | APAD_XMT | REX_RTRY, mmio + CMD2 );
6aa20a22 500
1da177e4
LT		 501 /* Setting the MAC address to the device */
502 for(i = 0; i < ETH_ADDR_LEN; i++)
6aa20a22 503 writeb( dev->dev_addr[i], mmio + PADR + i );
1da177e4
LT		 504
505 /* Enable interrupt coalesce */
506 if(lp->options & OPTION_INTR_COAL_ENABLE){
507 printk(KERN_INFO "%s: Interrupt Coalescing Enabled.\n",
508 dev->name);
509 amd8111e_set_coalesce(dev,ENABLE_COAL);
510 }
6aa20a22 511
1da177e4
LT		 512 /* set RUN bit to start the chip */
513 writel(VAL2 | RDMD0, mmio + CMD0);
514 writel(VAL0 | INTREN | RUN, mmio + CMD0);
6aa20a22 515
1da177e4
LT		 516 /* To avoid PCI posting bug */
517 readl(mmio+CMD0);
518 return 0;
519}
6aa20a22
JG		 520/*
521This function clears necessary the device registers.
522*/
1da177e4
LT		 523static void amd8111e_init_hw_default( struct amd8111e_priv* lp)
524{
525 unsigned int reg_val;
526 unsigned int logic_filter[2] ={0,};
527 void __iomem *mmio = lp->mmio;
528
529
530 /* stop the chip */
531 writel(RUN, mmio + CMD0);
532
533 /* AUTOPOLL0 Register *//*TBD default value is 8100 in FPS */
534 writew( 0x8100 | lp->ext_phy_addr, mmio + AUTOPOLL0);
535
536 /* Clear RCV_RING_BASE_ADDR */
537 writel(0, mmio + RCV_RING_BASE_ADDR0);
538
539 /* Clear XMT_RING_BASE_ADDR */
540 writel(0, mmio + XMT_RING_BASE_ADDR0);
541 writel(0, mmio + XMT_RING_BASE_ADDR1);
542 writel(0, mmio + XMT_RING_BASE_ADDR2);
543 writel(0, mmio + XMT_RING_BASE_ADDR3);
544
545 /* Clear CMD0 */
546 writel(CMD0_CLEAR,mmio + CMD0);
6aa20a22 547
1da177e4
LT		 548 /* Clear CMD2 */
549 writel(CMD2_CLEAR, mmio +CMD2);
550
551 /* Clear CMD7 */
552 writel(CMD7_CLEAR , mmio + CMD7);
553
554 /* Clear DLY_INT_A and DLY_INT_B */
555 writel(0x0, mmio + DLY_INT_A);
556 writel(0x0, mmio + DLY_INT_B);
557
558 /* Clear FLOW_CONTROL */
559 writel(0x0, mmio + FLOW_CONTROL);
560
561 /* Clear INT0 write 1 to clear register */
562 reg_val = readl(mmio + INT0);
563 writel(reg_val, mmio + INT0);
564
565 /* Clear STVAL */
566 writel(0x0, mmio + STVAL);
567
568 /* Clear INTEN0 */
569 writel( INTEN0_CLEAR, mmio + INTEN0);
570
571 /* Clear LADRF */
572 writel(0x0 , mmio + LADRF);
573
574 /* Set SRAM_SIZE & SRAM_BOUNDARY registers */
575 writel( 0x80010,mmio + SRAM_SIZE);
576
577 /* Clear RCV_RING0_LEN */
578 writel(0x0, mmio + RCV_RING_LEN0);
579
580 /* Clear XMT_RING0/1/2/3_LEN */
581 writel(0x0, mmio + XMT_RING_LEN0);
582 writel(0x0, mmio + XMT_RING_LEN1);
583 writel(0x0, mmio + XMT_RING_LEN2);
584 writel(0x0, mmio + XMT_RING_LEN3);
585
586 /* Clear XMT_RING_LIMIT */
587 writel(0x0, mmio + XMT_RING_LIMIT);
588
589 /* Clear MIB */
590 writew(MIB_CLEAR, mmio + MIB_ADDR);
591
592 /* Clear LARF */
593 amd8111e_writeq(*(u64*)logic_filter,mmio+LADRF);
594
595 /* SRAM_SIZE register */
596 reg_val = readl(mmio + SRAM_SIZE);
6aa20a22 597
1da177e4
LT		 598 if(lp->options & OPTION_JUMBO_ENABLE)
599 writel( VAL2|JUMBO, mmio + CMD3);
600#if AMD8111E_VLAN_TAG_USED
601 writel(VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3 );
602#endif
603 /* Set default value to CTRL1 Register */
604 writel(CTRL1_DEFAULT, mmio + CTRL1);
605
606 /* To avoid PCI posting bug */
607 readl(mmio + CMD2);
608
609}
610
6aa20a22
JG		 611/*
612This function disables the interrupt and clears all the pending
1da177e4
LT		 613interrupts in INT0
614 */
615static void amd8111e_disable_interrupt(struct amd8111e_priv* lp)
6aa20a22 616{
1da177e4
LT		 617 u32 intr0;
618
619 /* Disable interrupt */
620 writel(INTREN, lp->mmio + CMD0);
6aa20a22 621
1da177e4
LT		 622 /* Clear INT0 */
623 intr0 = readl(lp->mmio + INT0);
624 writel(intr0, lp->mmio + INT0);
6aa20a22 625
1da177e4
LT		 626 /* To avoid PCI posting bug */
627 readl(lp->mmio + INT0);
628
629}
630
631/*
6aa20a22 632This function stops the chip.
1da177e4
LT		 633*/
634static void amd8111e_stop_chip(struct amd8111e_priv* lp)
635{
636 writel(RUN, lp->mmio + CMD0);
6aa20a22 637
1da177e4
LT		 638 /* To avoid PCI posting bug */
639 readl(lp->mmio + CMD0);
640}
641
6aa20a22 642/*
1da177e4
LT		 643This function frees the transmiter and receiver descriptor rings.
644*/
645static void amd8111e_free_ring(struct amd8111e_priv* lp)
6aa20a22 646{
1da177e4
LT		 647
648 /* Free transmit and receive skbs */
649 amd8111e_free_skbs(lp->amd8111e_net_dev);
650
651 /* Free transmit and receive descriptor rings */
652 if(lp->rx_ring){
6aa20a22 653 pci_free_consistent(lp->pci_dev,
1da177e4
LT		 654 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,
655 lp->rx_ring, lp->rx_ring_dma_addr);
656 lp->rx_ring = NULL;
657 }
6aa20a22 658
1da177e4 659 if(lp->tx_ring){
6aa20a22 660 pci_free_consistent(lp->pci_dev,
1da177e4
LT		 661 sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,
662 lp->tx_ring, lp->tx_ring_dma_addr);
663
664 lp->tx_ring = NULL;
665 }
666
667}
6aa20a22
JG		 668#if AMD8111E_VLAN_TAG_USED
669/*
1da177e4 670This is the receive indication function for packets with vlan tag.
6aa20a22 671*/
1da177e4
LT		 672static int amd8111e_vlan_rx(struct amd8111e_priv *lp, struct sk_buff *skb, u16 vlan_tag)
673{
674#ifdef CONFIG_AMD8111E_NAPI
675 return vlan_hwaccel_receive_skb(skb, lp->vlgrp,vlan_tag);
676#else
677 return vlan_hwaccel_rx(skb, lp->vlgrp, vlan_tag);
678#endif /* CONFIG_AMD8111E_NAPI */
679}
680#endif
681
682/*
6aa20a22 683This function will free all the transmit skbs that are actually transmitted by the device. It will check the ownership of the skb before freeing the skb.
1da177e4
LT		 684*/
685static int amd8111e_tx(struct net_device *dev)
686{
687 struct amd8111e_priv* lp = netdev_priv(dev);
688 int tx_index = lp->tx_complete_idx & TX_RING_DR_MOD_MASK;
689 int status;
690 /* Complete all the transmit packet */
691 while (lp->tx_complete_idx != lp->tx_idx){
692 tx_index = lp->tx_complete_idx & TX_RING_DR_MOD_MASK;
693 status = le16_to_cpu(lp->tx_ring[tx_index].tx_flags);
694
695 if(status & OWN_BIT)
696 break; /* It still hasn't been Txed */
697
698 lp->tx_ring[tx_index].buff_phy_addr = 0;
699
700 /* We must free the original skb */
701 if (lp->tx_skbuff[tx_index]) {
702 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[tx_index],
703 lp->tx_skbuff[tx_index]->len,
704 PCI_DMA_TODEVICE);
705 dev_kfree_skb_irq (lp->tx_skbuff[tx_index]);
706 lp->tx_skbuff[tx_index] = NULL;
707 lp->tx_dma_addr[tx_index] = 0;
708 }
709 lp->tx_complete_idx++;
710 /*COAL update tx coalescing parameters */
711 lp->coal_conf.tx_packets++;
6aa20a22 712 lp->coal_conf.tx_bytes += lp->tx_ring[tx_index].buff_count;
1da177e4
LT		 713
714 if (netif_queue_stopped(dev) &&
715 lp->tx_complete_idx > lp->tx_idx - NUM_TX_BUFFERS +2){
716 /* The ring is no longer full, clear tbusy. */
717 /* lp->tx_full = 0; */
718 netif_wake_queue (dev);
719 }
720 }
721 return 0;
722}
723
724#ifdef CONFIG_AMD8111E_NAPI
725/* This function handles the driver receive operation in polling mode */
bea3348e 726static int amd8111e_rx_poll(struct napi_struct *napi, int budget)
1da177e4 727{
bea3348e
SH		 728 struct amd8111e_priv *lp = container_of(napi, struct amd8111e_priv, napi);
729 struct net_device *dev = lp->amd8111e_net_dev;
1da177e4
LT		 730 int rx_index = lp->rx_idx & RX_RING_DR_MOD_MASK;
731 void __iomem *mmio = lp->mmio;
732 struct sk_buff *skb,*new_skb;
733 int min_pkt_len, status;
734 unsigned int intr0;
735 int num_rx_pkt = 0;
736 /*int max_rx_pkt = NUM_RX_BUFFERS;*/
737 short pkt_len;
6aa20a22 738#if AMD8111E_VLAN_TAG_USED
1da177e4
LT		 739 short vtag;
740#endif
bea3348e 741 int rx_pkt_limit = budget;
dfa1b73f 742 unsigned long flags;
6aa20a22
JG		 743
744 do{
1da177e4
LT		 745 /* process receive packets until we use the quota*/
746 /* If we own the next entry, it's a new packet. Send it up. */
747 while(1) {
748 status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags);
749 if (status & OWN_BIT)
750 break;
751
6aa20a22 752 /*
1da177e4
LT		 753 * There is a tricky error noted by John Murphy,
754 * <murf@perftech.com> to Russ Nelson: Even with
6aa20a22
JG		 755 * full-sized * buffers it's possible for a
756 * jabber packet to use two buffers, with only
1da177e4
LT		 757 * the last correctly noting the error.
758 */
759
760 if(status & ERR_BIT) {
761 /* reseting flags */
762 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
763 goto err_next_pkt;
764 }
765 /* check for STP and ENP */
766 if(!((status & STP_BIT) && (status & ENP_BIT))){
767 /* reseting flags */
768 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
769 goto err_next_pkt;
770 }
771 pkt_len = le16_to_cpu(lp->rx_ring[rx_index].msg_count) - 4;
772
6aa20a22 773#if AMD8111E_VLAN_TAG_USED
1da177e4 774 vtag = status & TT_MASK;
6aa20a22 775 /*MAC will strip vlan tag*/
1da177e4
LT		 776 if(lp->vlgrp != NULL && vtag !=0)
777 min_pkt_len =MIN_PKT_LEN - 4;
778 else
779#endif
780 min_pkt_len =MIN_PKT_LEN;
781
782 if (pkt_len < min_pkt_len) {
783 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
784 lp->drv_rx_errors++;
785 goto err_next_pkt;
786 }
787 if(--rx_pkt_limit < 0)
788 goto rx_not_empty;
789 if(!(new_skb = dev_alloc_skb(lp->rx_buff_len))){
6aa20a22 790 /* if allocation fail,
1da177e4
LT		 791 ignore that pkt and go to next one */
792 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
793 lp->drv_rx_errors++;
794 goto err_next_pkt;
795 }
6aa20a22 796
1da177e4
LT		 797 skb_reserve(new_skb, 2);
798 skb = lp->rx_skbuff[rx_index];
799 pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[rx_index],
800 lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
801 skb_put(skb, pkt_len);
1da177e4 802 lp->rx_skbuff[rx_index] = new_skb;
1da177e4
LT		 803 lp->rx_dma_addr[rx_index] = pci_map_single(lp->pci_dev,
804 new_skb->data,
805 lp->rx_buff_len-2,
806 PCI_DMA_FROMDEVICE);
6aa20a22 807
1da177e4
LT		 808 skb->protocol = eth_type_trans(skb, dev);
809
6aa20a22 810#if AMD8111E_VLAN_TAG_USED
1da177e4
LT		 811 if(lp->vlgrp != NULL && (vtag == TT_VLAN_TAGGED)){
812 amd8111e_vlan_rx(lp, skb,
813 le16_to_cpu(lp->rx_ring[rx_index].tag_ctrl_info));
814 } else
815#endif
816 netif_receive_skb(skb);
817 /*COAL update rx coalescing parameters*/
818 lp->coal_conf.rx_packets++;
6aa20a22 819 lp->coal_conf.rx_bytes += pkt_len;
1da177e4
LT		 820 num_rx_pkt++;
821 dev->last_rx = jiffies;
6aa20a22
JG		 822
823 err_next_pkt:
1da177e4
LT		 824 lp->rx_ring[rx_index].buff_phy_addr
825 = cpu_to_le32(lp->rx_dma_addr[rx_index]);
6aa20a22 826 lp->rx_ring[rx_index].buff_count =
1da177e4
LT		 827 cpu_to_le16(lp->rx_buff_len-2);
828 wmb();
829 lp->rx_ring[rx_index].rx_flags |= cpu_to_le16(OWN_BIT);
830 rx_index = (++lp->rx_idx) & RX_RING_DR_MOD_MASK;
831 }
6aa20a22 832 /* Check the interrupt status register for more packets in the
1da177e4
LT		 833 mean time. Process them since we have not used up our quota.*/
834
835 intr0 = readl(mmio + INT0);
836 /*Ack receive packets */
837 writel(intr0 & RINT0,mmio + INT0);
838
839 } while(intr0 & RINT0);
840
841 /* Receive descriptor is empty now */
dfa1b73f 842 spin_lock_irqsave(&lp->lock, flags);
bea3348e 843 __netif_rx_complete(dev, napi);
1da177e4
LT		 844 writel(VAL0|RINTEN0, mmio + INTEN0);
845 writel(VAL2 | RDMD0, mmio + CMD0);
dfa1b73f 846 spin_unlock_irqrestore(&lp->lock, flags);
dfa1b73f 847
1da177e4 848rx_not_empty:
bea3348e 849 return num_rx_pkt;
1da177e4
LT		 850}
851
852#else
6aa20a22 853/*
1da177e4
LT		 854This function will check the ownership of receive buffers and descriptors. It will indicate to kernel up to half the number of maximum receive buffers in the descriptor ring, in a single receive interrupt. It will also replenish the descriptors with new skbs.
855*/
856static int amd8111e_rx(struct net_device *dev)
857{
858 struct amd8111e_priv *lp = netdev_priv(dev);
859 struct sk_buff *skb,*new_skb;
860 int rx_index = lp->rx_idx & RX_RING_DR_MOD_MASK;
861 int min_pkt_len, status;
862 int num_rx_pkt = 0;
863 int max_rx_pkt = NUM_RX_BUFFERS;
864 short pkt_len;
6aa20a22 865#if AMD8111E_VLAN_TAG_USED
1da177e4
LT		 866 short vtag;
867#endif
6aa20a22 868
1da177e4
LT		 869 /* If we own the next entry, it's a new packet. Send it up. */
870 while(++num_rx_pkt <= max_rx_pkt){
871 status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags);
872 if(status & OWN_BIT)
873 return 0;
6aa20a22
JG		 874
875 /* check if err summary bit is set */
1da177e4 876 if(status & ERR_BIT){
6aa20a22 877 /*
1da177e4
LT		 878 * There is a tricky error noted by John Murphy,
879 * <murf@perftech.com> to Russ Nelson: Even with full-sized
880 * buffers it's possible for a jabber packet to use two
881 * buffers, with only the last correctly noting the error. */
882 /* reseting flags */
883 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
884 goto err_next_pkt;
885 }
886 /* check for STP and ENP */
887 if(!((status & STP_BIT) && (status & ENP_BIT))){
888 /* reseting flags */
889 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
890 goto err_next_pkt;
891 }
892 pkt_len = le16_to_cpu(lp->rx_ring[rx_index].msg_count) - 4;
893
6aa20a22 894#if AMD8111E_VLAN_TAG_USED
1da177e4 895 vtag = status & TT_MASK;
6aa20a22 896 /*MAC will strip vlan tag*/
1da177e4
LT		 897 if(lp->vlgrp != NULL && vtag !=0)
898 min_pkt_len =MIN_PKT_LEN - 4;
899 else
900#endif
901 min_pkt_len =MIN_PKT_LEN;
902
903 if (pkt_len < min_pkt_len) {
904 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
905 lp->drv_rx_errors++;
906 goto err_next_pkt;
907 }
908 if(!(new_skb = dev_alloc_skb(lp->rx_buff_len))){
6aa20a22 909 /* if allocation fail,
1da177e4
LT		 910 ignore that pkt and go to next one */
911 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
912 lp->drv_rx_errors++;
913 goto err_next_pkt;
914 }
6aa20a22 915
1da177e4
LT		 916 skb_reserve(new_skb, 2);
917 skb = lp->rx_skbuff[rx_index];
918 pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[rx_index],
919 lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
920 skb_put(skb, pkt_len);
1da177e4 921 lp->rx_skbuff[rx_index] = new_skb;
1da177e4
LT		 922 lp->rx_dma_addr[rx_index] = pci_map_single(lp->pci_dev,
923 new_skb->data, lp->rx_buff_len-2,PCI_DMA_FROMDEVICE);
6aa20a22 924
1da177e4
LT		 925 skb->protocol = eth_type_trans(skb, dev);
926
6aa20a22 927#if AMD8111E_VLAN_TAG_USED
1da177e4
LT		 928 if(lp->vlgrp != NULL && (vtag == TT_VLAN_TAGGED)){
929 amd8111e_vlan_rx(lp, skb,
930 le16_to_cpu(lp->rx_ring[rx_index].tag_ctrl_info));
931 } else
932#endif
6aa20a22 933
1da177e4
LT		 934 netif_rx (skb);
935 /*COAL update rx coalescing parameters*/
936 lp->coal_conf.rx_packets++;
6aa20a22 937 lp->coal_conf.rx_bytes += pkt_len;
1da177e4
LT		 938
939 dev->last_rx = jiffies;
6aa20a22 940
1da177e4
LT		 941err_next_pkt:
942 lp->rx_ring[rx_index].buff_phy_addr
943 = cpu_to_le32(lp->rx_dma_addr[rx_index]);
6aa20a22 944 lp->rx_ring[rx_index].buff_count =
1da177e4
LT		 945 cpu_to_le16(lp->rx_buff_len-2);
946 wmb();
947 lp->rx_ring[rx_index].rx_flags |= cpu_to_le16(OWN_BIT);
948 rx_index = (++lp->rx_idx) & RX_RING_DR_MOD_MASK;
949 }
950
951 return 0;
952}
953#endif /* CONFIG_AMD8111E_NAPI */
6aa20a22 954/*
1da177e4
LT		 955This function will indicate the link status to the kernel.
956*/
957static int amd8111e_link_change(struct net_device* dev)
6aa20a22 958{
1da177e4
LT		 959 struct amd8111e_priv *lp = netdev_priv(dev);
960 int status0,speed;
961
962 /* read the link change */
963 status0 = readl(lp->mmio + STAT0);
6aa20a22 964
1da177e4
LT		 965 if(status0 & LINK_STATS){
966 if(status0 & AUTONEG_COMPLETE)
967 lp->link_config.autoneg = AUTONEG_ENABLE;
6aa20a22 968 else
1da177e4
LT		 969 lp->link_config.autoneg = AUTONEG_DISABLE;
970
971 if(status0 & FULL_DPLX)
972 lp->link_config.duplex = DUPLEX_FULL;
6aa20a22 973 else
1da177e4
LT		 974 lp->link_config.duplex = DUPLEX_HALF;
975 speed = (status0 & SPEED_MASK) >> 7;
976 if(speed == PHY_SPEED_10)
977 lp->link_config.speed = SPEED_10;
978 else if(speed == PHY_SPEED_100)
979 lp->link_config.speed = SPEED_100;
980
981 printk(KERN_INFO "%s: Link is Up. Speed is %s Mbps %s Duplex\n", dev->name,
6aa20a22
JG		 982 (lp->link_config.speed == SPEED_100) ? "100": "10",
983 (lp->link_config.duplex == DUPLEX_FULL)? "Full": "Half");
1da177e4
LT		 984 netif_carrier_on(dev);
985 }
6aa20a22 986 else{
1da177e4
LT		 987 lp->link_config.speed = SPEED_INVALID;
988 lp->link_config.duplex = DUPLEX_INVALID;
989 lp->link_config.autoneg = AUTONEG_INVALID;
990 printk(KERN_INFO "%s: Link is Down.\n",dev->name);
991 netif_carrier_off(dev);
992 }
6aa20a22 993
1da177e4
LT		 994 return 0;
995}
996/*
6aa20a22 997This function reads the mib counters.
1da177e4
LT		 998*/
999static int amd8111e_read_mib(void __iomem *mmio, u8 MIB_COUNTER)
1000{
1001 unsigned int status;
1002 unsigned int data;
1003 unsigned int repeat = REPEAT_CNT;
1004
1005 writew( MIB_RD_CMD | MIB_COUNTER, mmio + MIB_ADDR);
1006 do {
1007 status = readw(mmio + MIB_ADDR);
1008 udelay(2); /* controller takes MAX 2 us to get mib data */
1009 }
1010 while (--repeat && (status & MIB_CMD_ACTIVE));
1011
1012 data = readl(mmio + MIB_DATA);
1013 return data;
1014}
1015
1016/*
1017This function reads the mib registers and returns the hardware statistics. It updates previous internal driver statistics with new values.
6aa20a22 1018*/
1da177e4
LT		 1019static struct net_device_stats *amd8111e_get_stats(struct net_device * dev)
1020{
1021 struct amd8111e_priv *lp = netdev_priv(dev);
1022 void __iomem *mmio = lp->mmio;
1023 unsigned long flags;
1024 /* struct net_device_stats *prev_stats = &lp->prev_stats; */
1025 struct net_device_stats* new_stats = &lp->stats;
6aa20a22 1026
1da177e4 1027 if(!lp->opened)
6aa20a22 1028 return &lp->stats;
1da177e4
LT		 1029 spin_lock_irqsave (&lp->lock, flags);
1030
1031 /* stats.rx_packets */
1032 new_stats->rx_packets = amd8111e_read_mib(mmio, rcv_broadcast_pkts)+
1033 amd8111e_read_mib(mmio, rcv_multicast_pkts)+
1034 amd8111e_read_mib(mmio, rcv_unicast_pkts);
1035
1036 /* stats.tx_packets */
1037 new_stats->tx_packets = amd8111e_read_mib(mmio, xmt_packets);
1038
1039 /*stats.rx_bytes */
1040 new_stats->rx_bytes = amd8111e_read_mib(mmio, rcv_octets);
1041
1042 /* stats.tx_bytes */
1043 new_stats->tx_bytes = amd8111e_read_mib(mmio, xmt_octets);
1044
1045 /* stats.rx_errors */
1046 /* hw errors + errors driver reported */
1047 new_stats->rx_errors = amd8111e_read_mib(mmio, rcv_undersize_pkts)+
1048 amd8111e_read_mib(mmio, rcv_fragments)+
1049 amd8111e_read_mib(mmio, rcv_jabbers)+
1050 amd8111e_read_mib(mmio, rcv_alignment_errors)+
1051 amd8111e_read_mib(mmio, rcv_fcs_errors)+
1052 amd8111e_read_mib(mmio, rcv_miss_pkts)+
1053 lp->drv_rx_errors;
1054
1055 /* stats.tx_errors */
1056 new_stats->tx_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
1057
1058 /* stats.rx_dropped*/
1059 new_stats->rx_dropped = amd8111e_read_mib(mmio, rcv_miss_pkts);
1060
1061 /* stats.tx_dropped*/
1062 new_stats->tx_dropped = amd8111e_read_mib(mmio, xmt_underrun_pkts);
1063
1064 /* stats.multicast*/
1065 new_stats->multicast = amd8111e_read_mib(mmio, rcv_multicast_pkts);
1066
1067 /* stats.collisions*/
1068 new_stats->collisions = amd8111e_read_mib(mmio, xmt_collisions);
1069
1070 /* stats.rx_length_errors*/
6aa20a22 1071 new_stats->rx_length_errors =
1da177e4
LT		 1072 amd8111e_read_mib(mmio, rcv_undersize_pkts)+
1073 amd8111e_read_mib(mmio, rcv_oversize_pkts);
1074
1075 /* stats.rx_over_errors*/
1076 new_stats->rx_over_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
1077
1078 /* stats.rx_crc_errors*/
1079 new_stats->rx_crc_errors = amd8111e_read_mib(mmio, rcv_fcs_errors);
1080
1081 /* stats.rx_frame_errors*/
1082 new_stats->rx_frame_errors =
1083 amd8111e_read_mib(mmio, rcv_alignment_errors);
1084
1085 /* stats.rx_fifo_errors */
1086 new_stats->rx_fifo_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
1087
1088 /* stats.rx_missed_errors */
1089 new_stats->rx_missed_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
1090
1091 /* stats.tx_aborted_errors*/
6aa20a22 1092 new_stats->tx_aborted_errors =
1da177e4
LT		 1093 amd8111e_read_mib(mmio, xmt_excessive_collision);
1094
1095 /* stats.tx_carrier_errors*/
6aa20a22 1096 new_stats->tx_carrier_errors =
1da177e4
LT		 1097 amd8111e_read_mib(mmio, xmt_loss_carrier);
1098
1099 /* stats.tx_fifo_errors*/
1100 new_stats->tx_fifo_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
1101
1102 /* stats.tx_window_errors*/
1103 new_stats->tx_window_errors =
1104 amd8111e_read_mib(mmio, xmt_late_collision);
1105
1106 /* Reset the mibs for collecting new statistics */
1107 /* writew(MIB_CLEAR, mmio + MIB_ADDR);*/
6aa20a22 1108
1da177e4
LT		 1109 spin_unlock_irqrestore (&lp->lock, flags);
1110
1111 return new_stats;
1112}
6aa20a22 1113/* This function recalculate the interupt coalescing mode on every interrupt
1da177e4
LT		 1114according to the datarate and the packet rate.
1115*/
1116static int amd8111e_calc_coalesce(struct net_device *dev)
1117{
1118 struct amd8111e_priv *lp = netdev_priv(dev);
1119 struct amd8111e_coalesce_conf * coal_conf = &lp->coal_conf;
1120 int tx_pkt_rate;
1121 int rx_pkt_rate;
1122 int tx_data_rate;
1123 int rx_data_rate;
1124 int rx_pkt_size;
1125 int tx_pkt_size;
1126
1127 tx_pkt_rate = coal_conf->tx_packets - coal_conf->tx_prev_packets;
1128 coal_conf->tx_prev_packets = coal_conf->tx_packets;
6aa20a22 1129
1da177e4
LT		 1130 tx_data_rate = coal_conf->tx_bytes - coal_conf->tx_prev_bytes;
1131 coal_conf->tx_prev_bytes = coal_conf->tx_bytes;
6aa20a22 1132
1da177e4
LT		 1133 rx_pkt_rate = coal_conf->rx_packets - coal_conf->rx_prev_packets;
1134 coal_conf->rx_prev_packets = coal_conf->rx_packets;
6aa20a22 1135
1da177e4
LT		 1136 rx_data_rate = coal_conf->rx_bytes - coal_conf->rx_prev_bytes;
1137 coal_conf->rx_prev_bytes = coal_conf->rx_bytes;
6aa20a22 1138
1da177e4
LT		 1139 if(rx_pkt_rate < 800){
1140 if(coal_conf->rx_coal_type != NO_COALESCE){
6aa20a22 1141
1da177e4
LT		 1142 coal_conf->rx_timeout = 0x0;
1143 coal_conf->rx_event_count = 0;
1144 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1145 coal_conf->rx_coal_type = NO_COALESCE;
1146 }
1147 }
1148 else{
6aa20a22 1149
1da177e4
LT		 1150 rx_pkt_size = rx_data_rate/rx_pkt_rate;
1151 if (rx_pkt_size < 128){
1152 if(coal_conf->rx_coal_type != NO_COALESCE){
6aa20a22 1153
1da177e4
LT		 1154 coal_conf->rx_timeout = 0;
1155 coal_conf->rx_event_count = 0;
1156 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1157 coal_conf->rx_coal_type = NO_COALESCE;
1158 }
1159
1160 }
1161 else if ( (rx_pkt_size >= 128) && (rx_pkt_size < 512) ){
6aa20a22 1162
1da177e4
LT		 1163 if(coal_conf->rx_coal_type != LOW_COALESCE){
1164 coal_conf->rx_timeout = 1;
1165 coal_conf->rx_event_count = 4;
1166 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1167 coal_conf->rx_coal_type = LOW_COALESCE;
1168 }
1169 }
1170 else if ((rx_pkt_size >= 512) && (rx_pkt_size < 1024)){
6aa20a22 1171
1da177e4
LT		 1172 if(coal_conf->rx_coal_type != MEDIUM_COALESCE){
1173 coal_conf->rx_timeout = 1;
1174 coal_conf->rx_event_count = 4;
1175 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1176 coal_conf->rx_coal_type = MEDIUM_COALESCE;
6aa20a22
JG		 1177 }
1178
1da177e4
LT		 1179 }
1180 else if(rx_pkt_size >= 1024){
1181 if(coal_conf->rx_coal_type != HIGH_COALESCE){
1182 coal_conf->rx_timeout = 2;
1183 coal_conf->rx_event_count = 3;
1184 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1185 coal_conf->rx_coal_type = HIGH_COALESCE;
6aa20a22 1186 }
1da177e4
LT		 1187 }
1188 }
1189 /* NOW FOR TX INTR COALESC */
1190 if(tx_pkt_rate < 800){
1191 if(coal_conf->tx_coal_type != NO_COALESCE){
6aa20a22 1192
1da177e4
LT		 1193 coal_conf->tx_timeout = 0x0;
1194 coal_conf->tx_event_count = 0;
1195 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1196 coal_conf->tx_coal_type = NO_COALESCE;
1197 }
1198 }
1199 else{
6aa20a22 1200
1da177e4
LT		 1201 tx_pkt_size = tx_data_rate/tx_pkt_rate;
1202 if (tx_pkt_size < 128){
6aa20a22 1203
1da177e4 1204 if(coal_conf->tx_coal_type != NO_COALESCE){
6aa20a22 1205
1da177e4
LT		 1206 coal_conf->tx_timeout = 0;
1207 coal_conf->tx_event_count = 0;
1208 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1209 coal_conf->tx_coal_type = NO_COALESCE;
1210 }
1211
1212 }
1213 else if ( (tx_pkt_size >= 128) && (tx_pkt_size < 512) ){
6aa20a22 1214
1da177e4
LT		 1215 if(coal_conf->tx_coal_type != LOW_COALESCE){
1216 coal_conf->tx_timeout = 1;
1217 coal_conf->tx_event_count = 2;
1218 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1219 coal_conf->tx_coal_type = LOW_COALESCE;
1220
1221 }
1222 }
1223 else if ((tx_pkt_size >= 512) && (tx_pkt_size < 1024)){
6aa20a22 1224
1da177e4
LT		 1225 if(coal_conf->tx_coal_type != MEDIUM_COALESCE){
1226 coal_conf->tx_timeout = 2;
1227 coal_conf->tx_event_count = 5;
1228 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1229 coal_conf->tx_coal_type = MEDIUM_COALESCE;
6aa20a22
JG		 1230 }
1231
1da177e4
LT		 1232 }
1233 else if(tx_pkt_size >= 1024){
1234 if (tx_pkt_size >= 1024){
1235 if(coal_conf->tx_coal_type != HIGH_COALESCE){
1236 coal_conf->tx_timeout = 4;
1237 coal_conf->tx_event_count = 8;
1238 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1239 coal_conf->tx_coal_type = HIGH_COALESCE;
6aa20a22 1240 }
1da177e4
LT		 1241 }
1242 }
1243 }
1244 return 0;
1245
1246}
1247/*
1248This is device interrupt function. It handles transmit, receive,link change and hardware timer interrupts.
1249*/
7d12e780 1250static irqreturn_t amd8111e_interrupt(int irq, void *dev_id)
1da177e4
LT		 1251{
1252
1253 struct net_device * dev = (struct net_device *) dev_id;
1254 struct amd8111e_priv *lp = netdev_priv(dev);
1255 void __iomem *mmio = lp->mmio;
dfa1b73f 1256 unsigned int intr0, intren0;
1da177e4
LT		 1257 unsigned int handled = 1;
1258
dfa1b73f 1259 if(unlikely(dev == NULL))
1da177e4
LT		 1260 return IRQ_NONE;
1261
dfa1b73f
LT		 1262 spin_lock(&lp->lock);
1263
1da177e4
LT		 1264 /* disabling interrupt */
1265 writel(INTREN, mmio + CMD0);
1266
1267 /* Read interrupt status */
1268 intr0 = readl(mmio + INT0);
dfa1b73f 1269 intren0 = readl(mmio + INTEN0);
1da177e4
LT		 1270
1271 /* Process all the INT event until INTR bit is clear. */
1272
1273 if (!(intr0 & INTR)){
1274 handled = 0;
1275 goto err_no_interrupt;
1276 }
6aa20a22 1277
1da177e4
LT		 1278 /* Current driver processes 4 interrupts : RINT,TINT,LCINT,STINT */
1279 writel(intr0, mmio + INT0);
1280
1281 /* Check if Receive Interrupt has occurred. */
44456d37 1282#ifdef CONFIG_AMD8111E_NAPI
1da177e4 1283 if(intr0 & RINT0){
bea3348e 1284 if(netif_rx_schedule_prep(dev, &lp->napi)){
1da177e4
LT		 1285 /* Disable receive interupts */
1286 writel(RINTEN0, mmio + INTEN0);
1287 /* Schedule a polling routine */
bea3348e 1288 __netif_rx_schedule(dev, &lp->napi);
1da177e4 1289 }
dfa1b73f 1290 else if (intren0 & RINTEN0) {
1da177e4
LT		 1291 printk("************Driver bug! \
1292 interrupt while in poll\n");
dfa1b73f
LT		 1293 /* Fix by disable receive interrupts */
1294 writel(RINTEN0, mmio + INTEN0);
1da177e4
LT		 1295 }
1296 }
1297#else
1298 if(intr0 & RINT0){
1299 amd8111e_rx(dev);
1300 writel(VAL2 | RDMD0, mmio + CMD0);
1301 }
1302#endif /* CONFIG_AMD8111E_NAPI */
1303 /* Check if Transmit Interrupt has occurred. */
1304 if(intr0 & TINT0)
1305 amd8111e_tx(dev);
6aa20a22 1306
1da177e4
LT		 1307 /* Check if Link Change Interrupt has occurred. */
1308 if (intr0 & LCINT)
1309 amd8111e_link_change(dev);
1310
1311 /* Check if Hardware Timer Interrupt has occurred. */
1312 if (intr0 & STINT)
1313 amd8111e_calc_coalesce(dev);
1314
1315err_no_interrupt:
1316 writel( VAL0 | INTREN,mmio + CMD0);
6aa20a22 1317
dfa1b73f 1318 spin_unlock(&lp->lock);
6aa20a22 1319
1da177e4
LT		 1320 return IRQ_RETVAL(handled);
1321}
1322
1323#ifdef CONFIG_NET_POLL_CONTROLLER
1324static void amd8111e_poll(struct net_device *dev)
6aa20a22 1325{
1da177e4 1326 unsigned long flags;
b7e36bfa 1327 local_irq_save(flags);
7d12e780 1328 amd8111e_interrupt(0, dev);
6aa20a22
JG		 1329 local_irq_restore(flags);
1330}
1da177e4
LT		 1331#endif
1332
1333
1334/*
1335This function closes the network interface and updates the statistics so that most recent statistics will be available after the interface is down.
1336*/
1337static int amd8111e_close(struct net_device * dev)
1338{
1339 struct amd8111e_priv *lp = netdev_priv(dev);
1340 netif_stop_queue(dev);
6aa20a22 1341
bea3348e
SH		 1342 napi_disable(&lp->napi);
1343
1da177e4 1344 spin_lock_irq(&lp->lock);
6aa20a22 1345
1da177e4
LT		 1346 amd8111e_disable_interrupt(lp);
1347 amd8111e_stop_chip(lp);
1348 amd8111e_free_ring(lp);
6aa20a22 1349
1da177e4
LT		 1350 netif_carrier_off(lp->amd8111e_net_dev);
1351
1352 /* Delete ipg timer */
6aa20a22 1353 if(lp->options & OPTION_DYN_IPG_ENABLE)
1da177e4
LT		 1354 del_timer_sync(&lp->ipg_data.ipg_timer);
1355
1356 spin_unlock_irq(&lp->lock);
1357 free_irq(dev->irq, dev);
6aa20a22 1358
1da177e4
LT		 1359 /* Update the statistics before closing */
1360 amd8111e_get_stats(dev);
1361 lp->opened = 0;
1362 return 0;
1363}
6aa20a22 1364/* This function opens new interface.It requests irq for the device, initializes the device,buffers and descriptors, and starts the device.
1da177e4
LT		 1365*/
1366static int amd8111e_open(struct net_device * dev )
1367{
1368 struct amd8111e_priv *lp = netdev_priv(dev);
1369
1fb9df5d 1370 if(dev->irq ==0 || request_irq(dev->irq, amd8111e_interrupt, IRQF_SHARED,
6aa20a22 1371 dev->name, dev))
1da177e4
LT		 1372 return -EAGAIN;
1373
bea3348e
SH		 1374 napi_enable(&lp->napi);
1375
1da177e4
LT		 1376 spin_lock_irq(&lp->lock);
1377
1378 amd8111e_init_hw_default(lp);
1379
1380 if(amd8111e_restart(dev)){
1381 spin_unlock_irq(&lp->lock);
bea3348e 1382 napi_disable(&lp->napi);
1da177e4
LT		 1383 if (dev->irq)
1384 free_irq(dev->irq, dev);
1385 return -ENOMEM;
1386 }
1387 /* Start ipg timer */
6aa20a22 1388 if(lp->options & OPTION_DYN_IPG_ENABLE){
1da177e4
LT		 1389 add_timer(&lp->ipg_data.ipg_timer);
1390 printk(KERN_INFO "%s: Dynamic IPG Enabled.\n",dev->name);
1391 }
1392
1393 lp->opened = 1;
1394
1395 spin_unlock_irq(&lp->lock);
1396
1397 netif_start_queue(dev);
1398
6aa20a22 1399 return 0;
1da177e4 1400}
6aa20a22 1401/*
1da177e4
LT		 1402This function checks if there is any transmit descriptors available to queue more packet.
1403*/
1404static int amd8111e_tx_queue_avail(struct amd8111e_priv* lp )
6aa20a22 1405{
1da177e4
LT		 1406 int tx_index = lp->tx_idx & TX_BUFF_MOD_MASK;
1407 if(lp->tx_skbuff[tx_index] != 0)
1408 return -1;
1409 else
1410 return 0;
6aa20a22 1411
1da177e4 1412}
6aa20a22 1413/*
1da177e4
LT		 1414This function will queue the transmit packets to the descriptors and will trigger the send operation. It also initializes the transmit descriptors with buffer physical address, byte count, ownership to hardware etc.
1415*/
1416
1417static int amd8111e_start_xmit(struct sk_buff *skb, struct net_device * dev)
1418{
1419 struct amd8111e_priv *lp = netdev_priv(dev);
1420 int tx_index;
1421 unsigned long flags;
1422
1423 spin_lock_irqsave(&lp->lock, flags);
1424
1425 tx_index = lp->tx_idx & TX_RING_DR_MOD_MASK;
1426
1427 lp->tx_ring[tx_index].buff_count = cpu_to_le16(skb->len);
1428
1429 lp->tx_skbuff[tx_index] = skb;
1430 lp->tx_ring[tx_index].tx_flags = 0;
1431
1432#if AMD8111E_VLAN_TAG_USED
1433 if((lp->vlgrp != NULL) && vlan_tx_tag_present(skb)){
6aa20a22
JG		 1434 lp->tx_ring[tx_index].tag_ctrl_cmd |=
1435 cpu_to_le16(TCC_VLAN_INSERT);
1436 lp->tx_ring[tx_index].tag_ctrl_info =
1da177e4
LT		 1437 cpu_to_le16(vlan_tx_tag_get(skb));
1438
1439 }
1440#endif
1441 lp->tx_dma_addr[tx_index] =
1442 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
1443 lp->tx_ring[tx_index].buff_phy_addr =
1444 (u32) cpu_to_le32(lp->tx_dma_addr[tx_index]);
1445
1446 /* Set FCS and LTINT bits */
1447 wmb();
1448 lp->tx_ring[tx_index].tx_flags |=
1449 cpu_to_le16(OWN_BIT | STP_BIT | ENP_BIT|ADD_FCS_BIT|LTINT_BIT);
1450
1451 lp->tx_idx++;
1452
1453 /* Trigger an immediate send poll. */
1454 writel( VAL1 | TDMD0, lp->mmio + CMD0);
1455 writel( VAL2 | RDMD0,lp->mmio + CMD0);
1456
1457 dev->trans_start = jiffies;
1458
1459 if(amd8111e_tx_queue_avail(lp) < 0){
1460 netif_stop_queue(dev);
1461 }
1462 spin_unlock_irqrestore(&lp->lock, flags);
1463 return 0;
1464}
1465/*
1466This function returns all the memory mapped registers of the device.
1467*/
1468static void amd8111e_read_regs(struct amd8111e_priv *lp, u32 *buf)
1469{
1470 void __iomem *mmio = lp->mmio;
1471 /* Read only necessary registers */
1472 buf[0] = readl(mmio + XMT_RING_BASE_ADDR0);
1473 buf[1] = readl(mmio + XMT_RING_LEN0);
1474 buf[2] = readl(mmio + RCV_RING_BASE_ADDR0);
1475 buf[3] = readl(mmio + RCV_RING_LEN0);
1476 buf[4] = readl(mmio + CMD0);
1477 buf[5] = readl(mmio + CMD2);
1478 buf[6] = readl(mmio + CMD3);
1479 buf[7] = readl(mmio + CMD7);
1480 buf[8] = readl(mmio + INT0);
1481 buf[9] = readl(mmio + INTEN0);
1482 buf[10] = readl(mmio + LADRF);
1483 buf[11] = readl(mmio + LADRF+4);
1484 buf[12] = readl(mmio + STAT0);
1485}
1486
6aa20a22 1487
1da177e4 1488/*
6aa20a22 1489This function sets promiscuos mode, all-multi mode or the multicast address
1da177e4
LT		 1490list to the device.
1491*/
1492static void amd8111e_set_multicast_list(struct net_device *dev)
1493{
1494 struct dev_mc_list* mc_ptr;
1495 struct amd8111e_priv *lp = netdev_priv(dev);
1496 u32 mc_filter[2] ;
1497 int i,bit_num;
1498 if(dev->flags & IFF_PROMISC){
1da177e4
LT		 1499 writel( VAL2 | PROM, lp->mmio + CMD2);
1500 return;
1501 }
1502 else
1503 writel( PROM, lp->mmio + CMD2);
1504 if(dev->flags & IFF_ALLMULTI || dev->mc_count > MAX_FILTER_SIZE){
1505 /* get all multicast packet */
1506 mc_filter[1] = mc_filter[0] = 0xffffffff;
1507 lp->mc_list = dev->mc_list;
1508 lp->options |= OPTION_MULTICAST_ENABLE;
1509 amd8111e_writeq(*(u64*)mc_filter,lp->mmio + LADRF);
1510 return;
1511 }
1512 if( dev->mc_count == 0 ){
1513 /* get only own packets */
1514 mc_filter[1] = mc_filter[0] = 0;
1515 lp->mc_list = NULL;
1516 lp->options &= ~OPTION_MULTICAST_ENABLE;
1517 amd8111e_writeq(*(u64*)mc_filter,lp->mmio + LADRF);
1518 /* disable promiscous mode */
1519 writel(PROM, lp->mmio + CMD2);
1520 return;
1521 }
1522 /* load all the multicast addresses in the logic filter */
1523 lp->options |= OPTION_MULTICAST_ENABLE;
1524 lp->mc_list = dev->mc_list;
1525 mc_filter[1] = mc_filter[0] = 0;
1526 for (i = 0, mc_ptr = dev->mc_list; mc_ptr && i < dev->mc_count;
1527 i++, mc_ptr = mc_ptr->next) {
6b4bdde6 1528 bit_num = (ether_crc_le(ETH_ALEN, mc_ptr->dmi_addr) >> 26) & 0x3f;
1da177e4 1529 mc_filter[bit_num >> 5] |= 1 << (bit_num & 31);
6aa20a22 1530 }
1da177e4
LT		 1531 amd8111e_writeq(*(u64*)mc_filter,lp->mmio+ LADRF);
1532
1533 /* To eliminate PCI posting bug */
1534 readl(lp->mmio + CMD2);
1535
1536}
1537
1538static void amd8111e_get_drvinfo(struct net_device* dev, struct ethtool_drvinfo *info)
1539{
1540 struct amd8111e_priv *lp = netdev_priv(dev);
1541 struct pci_dev *pci_dev = lp->pci_dev;
1542 strcpy (info->driver, MODULE_NAME);
1543 strcpy (info->version, MODULE_VERS);
1544 sprintf(info->fw_version,"%u",chip_version);
1545 strcpy (info->bus_info, pci_name(pci_dev));
1546}
1547
1548static int amd8111e_get_regs_len(struct net_device *dev)
1549{
1550 return AMD8111E_REG_DUMP_LEN;
1551}
1552
1553static void amd8111e_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
1554{
1555 struct amd8111e_priv *lp = netdev_priv(dev);
1556 regs->version = 0;
1557 amd8111e_read_regs(lp, buf);
1558}
1559
1560static int amd8111e_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1561{
1562 struct amd8111e_priv *lp = netdev_priv(dev);
1563 spin_lock_irq(&lp->lock);
1564 mii_ethtool_gset(&lp->mii_if, ecmd);
1565 spin_unlock_irq(&lp->lock);
1566 return 0;
1567}
1568
1569static int amd8111e_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1570{
1571 struct amd8111e_priv *lp = netdev_priv(dev);
1572 int res;
1573 spin_lock_irq(&lp->lock);
1574 res = mii_ethtool_sset(&lp->mii_if, ecmd);
1575 spin_unlock_irq(&lp->lock);
1576 return res;
1577}
1578
1579static int amd8111e_nway_reset(struct net_device *dev)
1580{
1581 struct amd8111e_priv *lp = netdev_priv(dev);
1582 return mii_nway_restart(&lp->mii_if);
1583}
1584
1585static u32 amd8111e_get_link(struct net_device *dev)
1586{
1587 struct amd8111e_priv *lp = netdev_priv(dev);
1588 return mii_link_ok(&lp->mii_if);
1589}
1590
1591static void amd8111e_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info)
1592{
1593 struct amd8111e_priv *lp = netdev_priv(dev);
1594 wol_info->supported = WAKE_MAGIC|WAKE_PHY;
1595 if (lp->options & OPTION_WOL_ENABLE)
1596 wol_info->wolopts = WAKE_MAGIC;
1597}
1598
1599static int amd8111e_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info)
1600{
1601 struct amd8111e_priv *lp = netdev_priv(dev);
1602 if (wol_info->wolopts & ~(WAKE_MAGIC|WAKE_PHY))
1603 return -EINVAL;
1604 spin_lock_irq(&lp->lock);
1605 if (wol_info->wolopts & WAKE_MAGIC)
6aa20a22 1606 lp->options |=
1da177e4
LT		 1607 (OPTION_WOL_ENABLE | OPTION_WAKE_MAGIC_ENABLE);
1608 else if(wol_info->wolopts & WAKE_PHY)
6aa20a22 1609 lp->options |=
1da177e4
LT		 1610 (OPTION_WOL_ENABLE | OPTION_WAKE_PHY_ENABLE);
1611 else
6aa20a22 1612 lp->options &= ~OPTION_WOL_ENABLE;
1da177e4
LT		 1613 spin_unlock_irq(&lp->lock);
1614 return 0;
1615}
1616
7282d491 1617static const struct ethtool_ops ops = {
1da177e4
LT		 1618 .get_drvinfo = amd8111e_get_drvinfo,
1619 .get_regs_len = amd8111e_get_regs_len,
1620 .get_regs = amd8111e_get_regs,
1621 .get_settings = amd8111e_get_settings,
1622 .set_settings = amd8111e_set_settings,
1623 .nway_reset = amd8111e_nway_reset,
1624 .get_link = amd8111e_get_link,
1625 .get_wol = amd8111e_get_wol,
1626 .set_wol = amd8111e_set_wol,
1627};
1628
1629/*
6aa20a22 1630This function handles all the ethtool ioctls. It gives driver info, gets/sets driver speed, gets memory mapped register values, forces auto negotiation, sets/gets WOL options for ethtool application.
1da177e4 1631*/
6aa20a22 1632
1da177e4
LT		 1633static int amd8111e_ioctl(struct net_device * dev , struct ifreq *ifr, int cmd)
1634{
1635 struct mii_ioctl_data *data = if_mii(ifr);
1636 struct amd8111e_priv *lp = netdev_priv(dev);
1637 int err;
1638 u32 mii_regval;
1639
1640 if (!capable(CAP_NET_ADMIN))
1641 return -EPERM;
1642
1643 switch(cmd) {
1644 case SIOCGMIIPHY:
1645 data->phy_id = lp->ext_phy_addr;
1646
1647 /* fallthru */
6aa20a22 1648 case SIOCGMIIREG:
1da177e4
LT		 1649
1650 spin_lock_irq(&lp->lock);
1651 err = amd8111e_read_phy(lp, data->phy_id,
1652 data->reg_num & PHY_REG_ADDR_MASK, &mii_regval);
1653 spin_unlock_irq(&lp->lock);
1654
1655 data->val_out = mii_regval;
1656 return err;
1657
1658 case SIOCSMIIREG:
1659
1660 spin_lock_irq(&lp->lock);
1661 err = amd8111e_write_phy(lp, data->phy_id,
1662 data->reg_num & PHY_REG_ADDR_MASK, data->val_in);
1663 spin_unlock_irq(&lp->lock);
1664
1665 return err;
1666
1667 default:
1668 /* do nothing */
1669 break;
1670 }
1671 return -EOPNOTSUPP;
1672}
1673static int amd8111e_set_mac_address(struct net_device *dev, void *p)
1674{
1675 struct amd8111e_priv *lp = netdev_priv(dev);
1676 int i;
1677 struct sockaddr *addr = p;
1678
1679 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1680 spin_lock_irq(&lp->lock);
1681 /* Setting the MAC address to the device */
1682 for(i = 0; i < ETH_ADDR_LEN; i++)
6aa20a22
JG		 1683 writeb( dev->dev_addr[i], lp->mmio + PADR + i );
1684
1da177e4
LT		 1685 spin_unlock_irq(&lp->lock);
1686
1687 return 0;
1688}
1689
6aa20a22 1690/*
1da177e4 1691This function changes the mtu of the device. It restarts the device to initialize the descriptor with new receive buffers.
6aa20a22 1692*/
1da177e4
LT		 1693static int amd8111e_change_mtu(struct net_device *dev, int new_mtu)
1694{
1695 struct amd8111e_priv *lp = netdev_priv(dev);
1696 int err;
1697
1698 if ((new_mtu < AMD8111E_MIN_MTU) || (new_mtu > AMD8111E_MAX_MTU))
1699 return -EINVAL;
1700
1701 if (!netif_running(dev)) {
1702 /* new_mtu will be used
6aa20a22 1703 when device starts netxt time */
1da177e4
LT		 1704 dev->mtu = new_mtu;
1705 return 0;
1706 }
1707
1708 spin_lock_irq(&lp->lock);
1709
1710 /* stop the chip */
1711 writel(RUN, lp->mmio + CMD0);
1712
1713 dev->mtu = new_mtu;
1714
1715 err = amd8111e_restart(dev);
1716 spin_unlock_irq(&lp->lock);
1717 if(!err)
1718 netif_start_queue(dev);
1719 return err;
1720}
1721
1722#if AMD8111E_VLAN_TAG_USED
1723static void amd8111e_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1724{
1725 struct amd8111e_priv *lp = netdev_priv(dev);
1726 spin_lock_irq(&lp->lock);
1727 lp->vlgrp = grp;
1728 spin_unlock_irq(&lp->lock);
1729}
1da177e4 1730#endif
25805dcf 1731
1da177e4
LT		 1732static int amd8111e_enable_magicpkt(struct amd8111e_priv* lp)
1733{
1734 writel( VAL1|MPPLBA, lp->mmio + CMD3);
1735 writel( VAL0|MPEN_SW, lp->mmio + CMD7);
1736
1737 /* To eliminate PCI posting bug */
1738 readl(lp->mmio + CMD7);
1739 return 0;
1740}
1741
1742static int amd8111e_enable_link_change(struct amd8111e_priv* lp)
1743{
1744
1745 /* Adapter is already stoped/suspended/interrupt-disabled */
1746 writel(VAL0|LCMODE_SW,lp->mmio + CMD7);
6aa20a22 1747
1da177e4
LT		 1748 /* To eliminate PCI posting bug */
1749 readl(lp->mmio + CMD7);
1750 return 0;
6aa20a22 1751}
1da177e4
LT		 1752/* This function is called when a packet transmission fails to complete within a resonable period, on the assumption that an interrupts have been failed or the interface is locked up. This function will reinitialize the hardware */
1753
1754static void amd8111e_tx_timeout(struct net_device *dev)
1755{
1756 struct amd8111e_priv* lp = netdev_priv(dev);
1757 int err;
1758
1759 printk(KERN_ERR "%s: transmit timed out, resetting\n",
1760 dev->name);
1761 spin_lock_irq(&lp->lock);
1762 err = amd8111e_restart(dev);
1763 spin_unlock_irq(&lp->lock);
1764 if(!err)
1765 netif_wake_queue(dev);
1766}
1767static int amd8111e_suspend(struct pci_dev *pci_dev, pm_message_t state)
6aa20a22 1768{
1da177e4
LT		 1769 struct net_device *dev = pci_get_drvdata(pci_dev);
1770 struct amd8111e_priv *lp = netdev_priv(dev);
6aa20a22 1771
1da177e4
LT		 1772 if (!netif_running(dev))
1773 return 0;
1774
1775 /* disable the interrupt */
1776 spin_lock_irq(&lp->lock);
1777 amd8111e_disable_interrupt(lp);
1778 spin_unlock_irq(&lp->lock);
1779
1780 netif_device_detach(dev);
6aa20a22 1781
1da177e4
LT		 1782 /* stop chip */
1783 spin_lock_irq(&lp->lock);
6aa20a22 1784 if(lp->options & OPTION_DYN_IPG_ENABLE)
1da177e4
LT		 1785 del_timer_sync(&lp->ipg_data.ipg_timer);
1786 amd8111e_stop_chip(lp);
1787 spin_unlock_irq(&lp->lock);
1788
1789 if(lp->options & OPTION_WOL_ENABLE){
1790 /* enable wol */
1791 if(lp->options & OPTION_WAKE_MAGIC_ENABLE)
6aa20a22 1792 amd8111e_enable_magicpkt(lp);
1da177e4 1793 if(lp->options & OPTION_WAKE_PHY_ENABLE)
6aa20a22
JG		 1794 amd8111e_enable_link_change(lp);
1795
1da177e4
LT		 1796 pci_enable_wake(pci_dev, PCI_D3hot, 1);
1797 pci_enable_wake(pci_dev, PCI_D3cold, 1);
1798
1799 }
6aa20a22 1800 else{
1da177e4
LT		 1801 pci_enable_wake(pci_dev, PCI_D3hot, 0);
1802 pci_enable_wake(pci_dev, PCI_D3cold, 0);
1803 }
6aa20a22 1804
1da177e4
LT		 1805 pci_save_state(pci_dev);
1806 pci_set_power_state(pci_dev, PCI_D3hot);
1807
1808 return 0;
1809}
1810static int amd8111e_resume(struct pci_dev *pci_dev)
1811{
1812 struct net_device *dev = pci_get_drvdata(pci_dev);
1813 struct amd8111e_priv *lp = netdev_priv(dev);
6aa20a22 1814
1da177e4
LT		 1815 if (!netif_running(dev))
1816 return 0;
1817
1818 pci_set_power_state(pci_dev, PCI_D0);
1819 pci_restore_state(pci_dev);
1820
1821 pci_enable_wake(pci_dev, PCI_D3hot, 0);
1822 pci_enable_wake(pci_dev, PCI_D3cold, 0); /* D3 cold */
1823
1824 netif_device_attach(dev);
1825
1826 spin_lock_irq(&lp->lock);
1827 amd8111e_restart(dev);
1828 /* Restart ipg timer */
6aa20a22
JG		 1829 if(lp->options & OPTION_DYN_IPG_ENABLE)
1830 mod_timer(&lp->ipg_data.ipg_timer,
1da177e4
LT		 1831 jiffies + IPG_CONVERGE_JIFFIES);
1832 spin_unlock_irq(&lp->lock);
1833
1834 return 0;
1835}
1836
1837
1838static void __devexit amd8111e_remove_one(struct pci_dev *pdev)
1839{
1840 struct net_device *dev = pci_get_drvdata(pdev);
1841 if (dev) {
1842 unregister_netdev(dev);
1843 iounmap(((struct amd8111e_priv *)netdev_priv(dev))->mmio);
1844 free_netdev(dev);
1845 pci_release_regions(pdev);
1846 pci_disable_device(pdev);
1847 pci_set_drvdata(pdev, NULL);
1848 }
1849}
1850static void amd8111e_config_ipg(struct net_device* dev)
1851{
1852 struct amd8111e_priv *lp = netdev_priv(dev);
1853 struct ipg_info* ipg_data = &lp->ipg_data;
1854 void __iomem *mmio = lp->mmio;
1855 unsigned int prev_col_cnt = ipg_data->col_cnt;
1856 unsigned int total_col_cnt;
1857 unsigned int tmp_ipg;
6aa20a22 1858
1da177e4
LT		 1859 if(lp->link_config.duplex == DUPLEX_FULL){
1860 ipg_data->ipg = DEFAULT_IPG;
1861 return;
1862 }
1863
1864 if(ipg_data->ipg_state == SSTATE){
6aa20a22 1865
1da177e4 1866 if(ipg_data->timer_tick == IPG_STABLE_TIME){
6aa20a22 1867
1da177e4
LT		 1868 ipg_data->timer_tick = 0;
1869 ipg_data->ipg = MIN_IPG - IPG_STEP;
1870 ipg_data->current_ipg = MIN_IPG;
1871 ipg_data->diff_col_cnt = 0xFFFFFFFF;
1872 ipg_data->ipg_state = CSTATE;
1873 }
1874 else
1875 ipg_data->timer_tick++;
1876 }
1877
1878 if(ipg_data->ipg_state == CSTATE){
6aa20a22 1879
1da177e4
LT		 1880 /* Get the current collision count */
1881
6aa20a22 1882 total_col_cnt = ipg_data->col_cnt =
1da177e4
LT		 1883 amd8111e_read_mib(mmio, xmt_collisions);
1884
6aa20a22 1885 if ((total_col_cnt - prev_col_cnt) <
1da177e4 1886 (ipg_data->diff_col_cnt)){
6aa20a22 1887
1da177e4
LT		 1888 ipg_data->diff_col_cnt =
1889 total_col_cnt - prev_col_cnt ;
1890
1891 ipg_data->ipg = ipg_data->current_ipg;
1892 }
1893
1894 ipg_data->current_ipg += IPG_STEP;
1895
1896 if (ipg_data->current_ipg <= MAX_IPG)
1897 tmp_ipg = ipg_data->current_ipg;
1898 else{
1899 tmp_ipg = ipg_data->ipg;
1900 ipg_data->ipg_state = SSTATE;
1901 }
6aa20a22
JG		 1902 writew((u32)tmp_ipg, mmio + IPG);
1903 writew((u32)(tmp_ipg - IFS1_DELTA), mmio + IFS1);
1da177e4
LT		 1904 }
1905 mod_timer(&lp->ipg_data.ipg_timer, jiffies + IPG_CONVERGE_JIFFIES);
1906 return;
1907
1908}
1909
1910static void __devinit amd8111e_probe_ext_phy(struct net_device* dev)
1911{
1912 struct amd8111e_priv *lp = netdev_priv(dev);
1913 int i;
1914
1915 for (i = 0x1e; i >= 0; i--) {
1916 u32 id1, id2;
1917
1918 if (amd8111e_read_phy(lp, i, MII_PHYSID1, &id1))
1919 continue;
1920 if (amd8111e_read_phy(lp, i, MII_PHYSID2, &id2))
1921 continue;
1922 lp->ext_phy_id = (id1 << 16) | id2;
1923 lp->ext_phy_addr = i;
1924 return;
1925 }
1926 lp->ext_phy_id = 0;
1927 lp->ext_phy_addr = 1;
1928}
1929
1930static int __devinit amd8111e_probe_one(struct pci_dev *pdev,
1931 const struct pci_device_id *ent)
1932{
1933 int err,i,pm_cap;
1934 unsigned long reg_addr,reg_len;
1935 struct amd8111e_priv* lp;
1936 struct net_device* dev;
1937
1938 err = pci_enable_device(pdev);
1939 if(err){
1940 printk(KERN_ERR "amd8111e: Cannot enable new PCI device,"
1941 "exiting.\n");
1942 return err;
1943 }
1944
1945 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)){
1946 printk(KERN_ERR "amd8111e: Cannot find PCI base address"
1947 "exiting.\n");
1948 err = -ENODEV;
1949 goto err_disable_pdev;
1950 }
1951
1952 err = pci_request_regions(pdev, MODULE_NAME);
1953 if(err){
1954 printk(KERN_ERR "amd8111e: Cannot obtain PCI resources, "
1955 "exiting.\n");
1956 goto err_disable_pdev;
1957 }
1958
1959 pci_set_master(pdev);
1960
1961 /* Find power-management capability. */
1962 if((pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM))==0){
1963 printk(KERN_ERR "amd8111e: No Power Management capability, "
1964 "exiting.\n");
1965 goto err_free_reg;
1966 }
1967
1968 /* Initialize DMA */
cac8c81a 1969 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) < 0) {
1da177e4
LT		 1970 printk(KERN_ERR "amd8111e: DMA not supported,"
1971 "exiting.\n");
cac8c81a
TK		 1972 goto err_free_reg;
1973 }
6aa20a22 1974
1da177e4
LT		 1975 reg_addr = pci_resource_start(pdev, 0);
1976 reg_len = pci_resource_len(pdev, 0);
1977
1978 dev = alloc_etherdev(sizeof(struct amd8111e_priv));
1979 if (!dev) {
1980 printk(KERN_ERR "amd8111e: Etherdev alloc failed, exiting.\n");
1981 err = -ENOMEM;
1982 goto err_free_reg;
1983 }
1984
1da177e4
LT		 1985 SET_NETDEV_DEV(dev, &pdev->dev);
1986
1987#if AMD8111E_VLAN_TAG_USED
1988 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX ;
1989 dev->vlan_rx_register =amd8111e_vlan_rx_register;
6aa20a22
JG		 1990#endif
1991
1da177e4
LT		 1992 lp = netdev_priv(dev);
1993 lp->pci_dev = pdev;
1994 lp->amd8111e_net_dev = dev;
1995 lp->pm_cap = pm_cap;
1996
1997 spin_lock_init(&lp->lock);
1998
1999 lp->mmio = ioremap(reg_addr, reg_len);
2000 if (lp->mmio == 0) {
2001 printk(KERN_ERR "amd8111e: Cannot map device registers, "
2002 "exiting\n");
2003 err = -ENOMEM;
2004 goto err_free_dev;
2005 }
6aa20a22 2006
1da177e4
LT		 2007 /* Initializing MAC address */
2008 for(i = 0; i < ETH_ADDR_LEN; i++)
2009 dev->dev_addr[i] =readb(lp->mmio + PADR + i);
6aa20a22 2010
1da177e4
LT		 2011 /* Setting user defined parametrs */
2012 lp->ext_phy_option = speed_duplex[card_idx];
2013 if(coalesce[card_idx])
6aa20a22 2014 lp->options |= OPTION_INTR_COAL_ENABLE;
1da177e4 2015 if(dynamic_ipg[card_idx++])
6aa20a22 2016 lp->options |= OPTION_DYN_IPG_ENABLE;
1da177e4
LT		 2017
2018 /* Initialize driver entry points */
2019 dev->open = amd8111e_open;
2020 dev->hard_start_xmit = amd8111e_start_xmit;
2021 dev->stop = amd8111e_close;
2022 dev->get_stats = amd8111e_get_stats;
2023 dev->set_multicast_list = amd8111e_set_multicast_list;
2024 dev->set_mac_address = amd8111e_set_mac_address;
2025 dev->do_ioctl = amd8111e_ioctl;
2026 dev->change_mtu = amd8111e_change_mtu;
2027 SET_ETHTOOL_OPS(dev, &ops);
2028 dev->irq =pdev->irq;
6aa20a22
JG		 2029 dev->tx_timeout = amd8111e_tx_timeout;
2030 dev->watchdog_timeo = AMD8111E_TX_TIMEOUT;
1da177e4 2031#ifdef CONFIG_AMD8111E_NAPI
bea3348e 2032 netif_napi_add(dev, &lp->napi, amd8111e_rx_poll, 32);
1da177e4
LT		 2033#endif
2034#ifdef CONFIG_NET_POLL_CONTROLLER
6aa20a22 2035 dev->poll_controller = amd8111e_poll;
1da177e4
LT		 2036#endif
2037
2038#if AMD8111E_VLAN_TAG_USED
2039 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2040 dev->vlan_rx_register =amd8111e_vlan_rx_register;
6aa20a22 2041#endif
1da177e4
LT		 2042 /* Probe the external PHY */
2043 amd8111e_probe_ext_phy(dev);
2044
2045 /* setting mii default values */
2046 lp->mii_if.dev = dev;
2047 lp->mii_if.mdio_read = amd8111e_mdio_read;
2048 lp->mii_if.mdio_write = amd8111e_mdio_write;
2049 lp->mii_if.phy_id = lp->ext_phy_addr;
2050
2051 /* Set receive buffer length and set jumbo option*/
2052 amd8111e_set_rx_buff_len(dev);
2053
2054
2055 err = register_netdev(dev);
2056 if (err) {
2057 printk(KERN_ERR "amd8111e: Cannot register net device, "
2058 "exiting.\n");
2059 goto err_iounmap;
2060 }
2061
2062 pci_set_drvdata(pdev, dev);
6aa20a22 2063
1da177e4 2064 /* Initialize software ipg timer */
6aa20a22 2065 if(lp->options & OPTION_DYN_IPG_ENABLE){
1da177e4
LT		 2066 init_timer(&lp->ipg_data.ipg_timer);
2067 lp->ipg_data.ipg_timer.data = (unsigned long) dev;
2068 lp->ipg_data.ipg_timer.function = (void *)&amd8111e_config_ipg;
6aa20a22 2069 lp->ipg_data.ipg_timer.expires = jiffies +
1da177e4
LT		 2070 IPG_CONVERGE_JIFFIES;
2071 lp->ipg_data.ipg = DEFAULT_IPG;
2072 lp->ipg_data.ipg_state = CSTATE;
2073 };
2074
2075 /* display driver and device information */
2076
2077 chip_version = (readl(lp->mmio + CHIPID) & 0xf0000000)>>28;
2078 printk(KERN_INFO "%s: AMD-8111e Driver Version: %s\n", dev->name,MODULE_VERS);
2079 printk(KERN_INFO "%s: [ Rev %x ] PCI 10/100BaseT Ethernet ", dev->name, chip_version);
2080 for (i = 0; i < 6; i++)
2081 printk("%2.2x%c",dev->dev_addr[i],i == 5 ? ' ' : ':');
6aa20a22 2082 printk( "\n");
1da177e4
LT		 2083 if (lp->ext_phy_id)
2084 printk(KERN_INFO "%s: Found MII PHY ID 0x%08x at address 0x%02x\n",
2085 dev->name, lp->ext_phy_id, lp->ext_phy_addr);
2086 else
2087 printk(KERN_INFO "%s: Couldn't detect MII PHY, assuming address 0x01\n",
2088 dev->name);
2089 return 0;
2090err_iounmap:
2091 iounmap(lp->mmio);
2092
2093err_free_dev:
2094 free_netdev(dev);
2095
2096err_free_reg:
2097 pci_release_regions(pdev);
2098
2099err_disable_pdev:
2100 pci_disable_device(pdev);
2101 pci_set_drvdata(pdev, NULL);
2102 return err;
2103
2104}
2105
2106static struct pci_driver amd8111e_driver = {
2107 .name = MODULE_NAME,
2108 .id_table = amd8111e_pci_tbl,
2109 .probe = amd8111e_probe_one,
2110 .remove = __devexit_p(amd8111e_remove_one),
2111 .suspend = amd8111e_suspend,
2112 .resume = amd8111e_resume
2113};
2114
2115static int __init amd8111e_init(void)
2116{
29917620 2117 return pci_register_driver(&amd8111e_driver);
1da177e4
LT		 2118}
2119
2120static void __exit amd8111e_cleanup(void)
2121{
2122 pci_unregister_driver(&amd8111e_driver);
2123}
2124
2125module_init(amd8111e_init);
2126module_exit(amd8111e_cleanup);
kernel source for telekom puls (alcatel/mediatek)