projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / amd8111e.c
CommitLineData
1da177e4 1
6aa20a22
JG		 2/* Advanced Micro Devices Inc. AMD8111E Linux Network Driver
3 * Copyright (C) 2004 Advanced Micro Devices
4 *
1da177e4 5 *
1da177e4
LT		 6 * Copyright 2001,2002 Jeff Garzik <jgarzik@mandrakesoft.com> [ 8139cp.c,tg3.c ]
7 * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)[ tg3.c]
8 * Copyright 1996-1999 Thomas Bogendoerfer [ pcnet32.c ]
9 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
10 * Copyright 1993 United States Government as represented by the
11 * Director, National Security Agency.[ pcnet32.c ]
12 * Carsten Langgaard, carstenl@mips.com [ pcnet32.c ]
13 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
14 *
6aa20a22 15 *
1da177e4
LT		 16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
6aa20a22 28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
1da177e4 29 * USA
6aa20a22 30
1da177e4
LT		 31Module Name:
32
33 amd8111e.c
34
35Abstract:
6aa20a22
JG		 36
37 AMD8111 based 10/100 Ethernet Controller Driver.
1da177e4
LT		 38
39Environment:
40
41 Kernel Mode
42
43Revision History:
44 3.0.0
45 Initial Revision.
46 3.0.1
47 1. Dynamic interrupt coalescing.
48 2. Removed prev_stats.
49 3. MII support.
50 4. Dynamic IPG support
51 3.0.2 05/29/2003
52 1. Bug fix: Fixed failure to send jumbo packets larger than 4k.
53 2. Bug fix: Fixed VLAN support failure.
54 3. Bug fix: Fixed receive interrupt coalescing bug.
55 4. Dynamic IPG support is disabled by default.
56 3.0.3 06/05/2003
57 1. Bug fix: Fixed failure to close the interface if SMP is enabled.
58 3.0.4 12/09/2003
59 1. Added set_mac_address routine for bonding driver support.
60 2. Tested the driver for bonding support
6aa20a22 61 3. Bug fix: Fixed mismach in actual receive buffer lenth and lenth
1da177e4 62 indicated to the h/w.
6aa20a22 63 4. Modified amd8111e_rx() routine to receive all the received packets
1da177e4
LT		 64 in the first interrupt.
65 5. Bug fix: Corrected rx_errors reported in get_stats() function.
66 3.0.5 03/22/2004
6aa20a22 67 1. Added NAPI support
1da177e4
LT		 68
69*/
70
71
1da177e4
LT		 72#include <linux/module.h>
73#include <linux/kernel.h>
74#include <linux/types.h>
75#include <linux/compiler.h>
1da177e4
LT		 76#include <linux/delay.h>
77#include <linux/init.h>
78#include <linux/ioport.h>
79#include <linux/pci.h>
80#include <linux/netdevice.h>
81#include <linux/etherdevice.h>
82#include <linux/skbuff.h>
83#include <linux/ethtool.h>
84#include <linux/mii.h>
85#include <linux/if_vlan.h>
6aa20a22 86#include <linux/ctype.h>
1da177e4 87#include <linux/crc32.h>
cac8c81a 88#include <linux/dma-mapping.h>
1da177e4
LT		 89
90#include <asm/system.h>
91#include <asm/io.h>
92#include <asm/byteorder.h>
93#include <asm/uaccess.h>
94
95#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
96#define AMD8111E_VLAN_TAG_USED 1
97#else
98#define AMD8111E_VLAN_TAG_USED 0
99#endif
100
101#include "amd8111e.h"
102#define MODULE_NAME "amd8111e"
6ba33ac8 103#define MODULE_VERS "3.0.7"
1da177e4 104MODULE_AUTHOR("Advanced Micro Devices, Inc.");
6ba33ac8 105MODULE_DESCRIPTION ("AMD8111 based 10/100 Ethernet Controller. Driver Version "MODULE_VERS);
1da177e4
LT		 106MODULE_LICENSE("GPL");
107MODULE_DEVICE_TABLE(pci, amd8111e_pci_tbl);
108module_param_array(speed_duplex, int, NULL, 0);
109MODULE_PARM_DESC(speed_duplex, "Set device speed and duplex modes, 0: Auto Negotitate, 1: 10Mbps Half Duplex, 2: 10Mbps Full Duplex, 3: 100Mbps Half Duplex, 4: 100Mbps Full Duplex");
110module_param_array(coalesce, bool, NULL, 0);
111MODULE_PARM_DESC(coalesce, "Enable or Disable interrupt coalescing, 1: Enable, 0: Disable");
112module_param_array(dynamic_ipg, bool, NULL, 0);
113MODULE_PARM_DESC(dynamic_ipg, "Enable or Disable dynamic IPG, 1: Enable, 0: Disable");
114
a3aa1884 115static DEFINE_PCI_DEVICE_TABLE(amd8111e_pci_tbl) = {
6aa20a22 116
1da177e4
LT		 117 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD8111E_7462,
118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
119 { 0, }
120
121};
6aa20a22 122/*
1da177e4
LT		 123This function will read the PHY registers.
124*/
125static int amd8111e_read_phy(struct amd8111e_priv* lp, int phy_id, int reg, u32* val)
126{
127 void __iomem *mmio = lp->mmio;
128 unsigned int reg_val;
129 unsigned int repeat= REPEAT_CNT;
130
131 reg_val = readl(mmio + PHY_ACCESS);
132 while (reg_val & PHY_CMD_ACTIVE)
133 reg_val = readl( mmio + PHY_ACCESS );
134
135 writel( PHY_RD_CMD | ((phy_id & 0x1f) << 21) |
136 ((reg & 0x1f) << 16), mmio +PHY_ACCESS);
137 do{
138 reg_val = readl(mmio + PHY_ACCESS);
139 udelay(30); /* It takes 30 us to read/write data */
140 } while (--repeat && (reg_val & PHY_CMD_ACTIVE));
141 if(reg_val & PHY_RD_ERR)
142 goto err_phy_read;
6aa20a22 143
1da177e4
LT		 144 *val = reg_val & 0xffff;
145 return 0;
6aa20a22 146err_phy_read:
1da177e4
LT		 147 *val = 0;
148 return -EINVAL;
6aa20a22 149
1da177e4
LT		 150}
151
6aa20a22
JG		 152/*
153This function will write into PHY registers.
1da177e4
LT		 154*/
155static int amd8111e_write_phy(struct amd8111e_priv* lp,int phy_id, int reg, u32 val)
156{
632155e6 157 unsigned int repeat = REPEAT_CNT;
1da177e4
LT		 158 void __iomem *mmio = lp->mmio;
159 unsigned int reg_val;
160
161 reg_val = readl(mmio + PHY_ACCESS);
162 while (reg_val & PHY_CMD_ACTIVE)
163 reg_val = readl( mmio + PHY_ACCESS );
164
165 writel( PHY_WR_CMD | ((phy_id & 0x1f) << 21) |
166 ((reg & 0x1f) << 16)|val, mmio + PHY_ACCESS);
167
168 do{
169 reg_val = readl(mmio + PHY_ACCESS);
170 udelay(30); /* It takes 30 us to read/write the data */
171 } while (--repeat && (reg_val & PHY_CMD_ACTIVE));
6aa20a22 172
1da177e4
LT		 173 if(reg_val & PHY_RD_ERR)
174 goto err_phy_write;
6aa20a22 175
1da177e4
LT		 176 return 0;
177
6aa20a22 178err_phy_write:
1da177e4 179 return -EINVAL;
6aa20a22 180
1da177e4 181}
6aa20a22 182/*
1da177e4 183This is the mii register read function provided to the mii interface.
6aa20a22 184*/
1da177e4
LT		 185static int amd8111e_mdio_read(struct net_device * dev, int phy_id, int reg_num)
186{
187 struct amd8111e_priv* lp = netdev_priv(dev);
188 unsigned int reg_val;
189
190 amd8111e_read_phy(lp,phy_id,reg_num,&reg_val);
191 return reg_val;
6aa20a22 192
1da177e4
LT		 193}
194
6aa20a22 195/*
1da177e4 196This is the mii register write function provided to the mii interface.
6aa20a22 197*/
1da177e4
LT		 198static void amd8111e_mdio_write(struct net_device * dev, int phy_id, int reg_num, int val)
199{
200 struct amd8111e_priv* lp = netdev_priv(dev);
201
202 amd8111e_write_phy(lp, phy_id, reg_num, val);
203}
204
205/*
206This function will set PHY speed. During initialization sets the original speed to 100 full.
207*/
208static void amd8111e_set_ext_phy(struct net_device *dev)
209{
210 struct amd8111e_priv *lp = netdev_priv(dev);
211 u32 bmcr,advert,tmp;
6aa20a22 212
1da177e4
LT		 213 /* Determine mii register values to set the speed */
214 advert = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_ADVERTISE);
215 tmp = advert & ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
216 switch (lp->ext_phy_option){
217
218 default:
219 case SPEED_AUTONEG: /* advertise all values */
220 tmp |= ( ADVERTISE_10HALF|ADVERTISE_10FULL|
221 ADVERTISE_100HALF|ADVERTISE_100FULL) ;
222 break;
223 case SPEED10_HALF:
224 tmp |= ADVERTISE_10HALF;
225 break;
226 case SPEED10_FULL:
227 tmp |= ADVERTISE_10FULL;
228 break;
6aa20a22 229 case SPEED100_HALF:
1da177e4
LT		 230 tmp |= ADVERTISE_100HALF;
231 break;
232 case SPEED100_FULL:
233 tmp |= ADVERTISE_100FULL;
234 break;
235 }
236
237 if(advert != tmp)
238 amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_ADVERTISE, tmp);
239 /* Restart auto negotiation */
240 bmcr = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_BMCR);
241 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
242 amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_BMCR, bmcr);
243
244}
245
6aa20a22
JG		 246/*
247This function will unmap skb->data space and will free
1da177e4
LT		 248all transmit and receive skbuffs.
249*/
250static int amd8111e_free_skbs(struct net_device *dev)
251{
252 struct amd8111e_priv *lp = netdev_priv(dev);
253 struct sk_buff* rx_skbuff;
254 int i;
255
256 /* Freeing transmit skbs */
257 for(i = 0; i < NUM_TX_BUFFERS; i++){
258 if(lp->tx_skbuff[i]){
259 pci_unmap_single(lp->pci_dev,lp->tx_dma_addr[i], lp->tx_skbuff[i]->len,PCI_DMA_TODEVICE);
260 dev_kfree_skb (lp->tx_skbuff[i]);
261 lp->tx_skbuff[i] = NULL;
262 lp->tx_dma_addr[i] = 0;
263 }
264 }
265 /* Freeing previously allocated receive buffers */
266 for (i = 0; i < NUM_RX_BUFFERS; i++){
267 rx_skbuff = lp->rx_skbuff[i];
268 if(rx_skbuff != NULL){
269 pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[i],
270 lp->rx_buff_len - 2,PCI_DMA_FROMDEVICE);
271 dev_kfree_skb(lp->rx_skbuff[i]);
272 lp->rx_skbuff[i] = NULL;
273 lp->rx_dma_addr[i] = 0;
274 }
275 }
6aa20a22 276
1da177e4
LT		 277 return 0;
278}
279
280/*
281This will set the receive buffer length corresponding to the mtu size of networkinterface.
282*/
283static inline void amd8111e_set_rx_buff_len(struct net_device* dev)
284{
285 struct amd8111e_priv* lp = netdev_priv(dev);
286 unsigned int mtu = dev->mtu;
6aa20a22 287
1da177e4
LT		 288 if (mtu > ETH_DATA_LEN){
289 /* MTU + ethernet header + FCS
290 + optional VLAN tag + skb reserve space 2 */
291
292 lp->rx_buff_len = mtu + ETH_HLEN + 10;
293 lp->options |= OPTION_JUMBO_ENABLE;
294 } else{
295 lp->rx_buff_len = PKT_BUFF_SZ;
296 lp->options &= ~OPTION_JUMBO_ENABLE;
297 }
298}
299
6aa20a22 300/*
1da177e4
LT		 301This function will free all the previously allocated buffers, determine new receive buffer length and will allocate new receive buffers. This function also allocates and initializes both the transmitter and receive hardware descriptors.
302 */
303static int amd8111e_init_ring(struct net_device *dev)
304{
305 struct amd8111e_priv *lp = netdev_priv(dev);
306 int i;
307
308 lp->rx_idx = lp->tx_idx = 0;
309 lp->tx_complete_idx = 0;
310 lp->tx_ring_idx = 0;
6aa20a22 311
1da177e4
LT		 312
313 if(lp->opened)
314 /* Free previously allocated transmit and receive skbs */
6aa20a22 315 amd8111e_free_skbs(dev);
1da177e4
LT		 316
317 else{
318 /* allocate the tx and rx descriptors */
6aa20a22 319 if((lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
1da177e4
LT		 320 sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,
321 &lp->tx_ring_dma_addr)) == NULL)
6aa20a22 322
1da177e4 323 goto err_no_mem;
6aa20a22
JG		 324
325 if((lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
1da177e4
LT		 326 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,
327 &lp->rx_ring_dma_addr)) == NULL)
6aa20a22 328
1da177e4
LT		 329 goto err_free_tx_ring;
330
331 }
332 /* Set new receive buff size */
333 amd8111e_set_rx_buff_len(dev);
334
335 /* Allocating receive skbs */
336 for (i = 0; i < NUM_RX_BUFFERS; i++) {
337
338 if (!(lp->rx_skbuff[i] = dev_alloc_skb(lp->rx_buff_len))) {
339 /* Release previos allocated skbs */
340 for(--i; i >= 0 ;i--)
341 dev_kfree_skb(lp->rx_skbuff[i]);
342 goto err_free_rx_ring;
343 }
344 skb_reserve(lp->rx_skbuff[i],2);
345 }
346 /* Initilaizing receive descriptors */
347 for (i = 0; i < NUM_RX_BUFFERS; i++) {
6aa20a22 348 lp->rx_dma_addr[i] = pci_map_single(lp->pci_dev,
1da177e4
LT		 349 lp->rx_skbuff[i]->data,lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
350
351 lp->rx_ring[i].buff_phy_addr = cpu_to_le32(lp->rx_dma_addr[i]);
352 lp->rx_ring[i].buff_count = cpu_to_le16(lp->rx_buff_len-2);
353 wmb();
354 lp->rx_ring[i].rx_flags = cpu_to_le16(OWN_BIT);
355 }
356
357 /* Initializing transmit descriptors */
358 for (i = 0; i < NUM_TX_RING_DR; i++) {
359 lp->tx_ring[i].buff_phy_addr = 0;
360 lp->tx_ring[i].tx_flags = 0;
361 lp->tx_ring[i].buff_count = 0;
362 }
363
364 return 0;
365
366err_free_rx_ring:
6aa20a22
JG		 367
368 pci_free_consistent(lp->pci_dev,
1da177e4
LT		 369 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,lp->rx_ring,
370 lp->rx_ring_dma_addr);
371
372err_free_tx_ring:
6aa20a22 373
1da177e4 374 pci_free_consistent(lp->pci_dev,
6aa20a22 375 sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,lp->tx_ring,
1da177e4
LT		 376 lp->tx_ring_dma_addr);
377
378err_no_mem:
379 return -ENOMEM;
380}
381/* This function will set the interrupt coalescing according to the input arguments */
382static int amd8111e_set_coalesce(struct net_device * dev, enum coal_mode cmod)
383{
384 unsigned int timeout;
385 unsigned int event_count;
386
387 struct amd8111e_priv *lp = netdev_priv(dev);
388 void __iomem *mmio = lp->mmio;
389 struct amd8111e_coalesce_conf * coal_conf = &lp->coal_conf;
390
391
392 switch(cmod)
393 {
394 case RX_INTR_COAL :
395 timeout = coal_conf->rx_timeout;
396 event_count = coal_conf->rx_event_count;
6aa20a22
JG		 397 if( timeout > MAX_TIMEOUT ||
398 event_count > MAX_EVENT_COUNT )
1da177e4
LT		 399 return -EINVAL;
400
6aa20a22 401 timeout = timeout * DELAY_TIMER_CONV;
1da177e4
LT		 402 writel(VAL0|STINTEN, mmio+INTEN0);
403 writel((u32)DLY_INT_A_R0|( event_count<< 16 )|timeout,
404 mmio+DLY_INT_A);
405 break;
406
407 case TX_INTR_COAL :
408 timeout = coal_conf->tx_timeout;
409 event_count = coal_conf->tx_event_count;
6aa20a22
JG		 410 if( timeout > MAX_TIMEOUT ||
411 event_count > MAX_EVENT_COUNT )
1da177e4
LT		 412 return -EINVAL;
413
6aa20a22
JG		 414
415 timeout = timeout * DELAY_TIMER_CONV;
1da177e4
LT		 416 writel(VAL0|STINTEN,mmio+INTEN0);
417 writel((u32)DLY_INT_B_T0|( event_count<< 16 )|timeout,
418 mmio+DLY_INT_B);
419 break;
420
421 case DISABLE_COAL:
422 writel(0,mmio+STVAL);
423 writel(STINTEN, mmio+INTEN0);
424 writel(0, mmio +DLY_INT_B);
425 writel(0, mmio+DLY_INT_A);
426 break;
6aa20a22 427 case ENABLE_COAL:
1da177e4
LT		 428 /* Start the timer */
429 writel((u32)SOFT_TIMER_FREQ, mmio+STVAL); /* 0.5 sec */
430 writel(VAL0|STINTEN, mmio+INTEN0);
431 break;
432 default:
433 break;
434
435 }
436 return 0;
437
438}
439
6aa20a22
JG		 440/*
441This function initializes the device registers and starts the device.
1da177e4
LT		 442*/
443static int amd8111e_restart(struct net_device *dev)
444{
445 struct amd8111e_priv *lp = netdev_priv(dev);
446 void __iomem *mmio = lp->mmio;
447 int i,reg_val;
448
449 /* stop the chip */
450 writel(RUN, mmio + CMD0);
451
452 if(amd8111e_init_ring(dev))
453 return -ENOMEM;
454
455 /* enable the port manager and set auto negotiation always */
456 writel((u32) VAL1|EN_PMGR, mmio + CMD3 );
6aa20a22
JG		 457 writel((u32)XPHYANE|XPHYRST , mmio + CTRL2);
458
1da177e4
LT		 459 amd8111e_set_ext_phy(dev);
460
461 /* set control registers */
462 reg_val = readl(mmio + CTRL1);
463 reg_val &= ~XMTSP_MASK;
464 writel( reg_val| XMTSP_128 | CACHE_ALIGN, mmio + CTRL1 );
465
466 /* enable interrupt */
6aa20a22 467 writel( APINT5EN | APINT4EN | APINT3EN | APINT2EN | APINT1EN |
1da177e4
LT		 468 APINT0EN | MIIPDTINTEN | MCCIINTEN | MCCINTEN | MREINTEN |
469 SPNDINTEN | MPINTEN | SINTEN | STINTEN, mmio + INTEN0);
470
471 writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0);
472
473 /* initialize tx and rx ring base addresses */
474 writel((u32)lp->tx_ring_dma_addr,mmio + XMT_RING_BASE_ADDR0);
475 writel((u32)lp->rx_ring_dma_addr,mmio+ RCV_RING_BASE_ADDR0);
476
477 writew((u32)NUM_TX_RING_DR, mmio + XMT_RING_LEN0);
478 writew((u16)NUM_RX_RING_DR, mmio + RCV_RING_LEN0);
6aa20a22 479
1da177e4
LT		 480 /* set default IPG to 96 */
481 writew((u32)DEFAULT_IPG,mmio+IPG);
6aa20a22 482 writew((u32)(DEFAULT_IPG-IFS1_DELTA), mmio + IFS1);
1da177e4
LT		 483
484 if(lp->options & OPTION_JUMBO_ENABLE){
485 writel((u32)VAL2|JUMBO, mmio + CMD3);
486 /* Reset REX_UFLO */
487 writel( REX_UFLO, mmio + CMD2);
488 /* Should not set REX_UFLO for jumbo frames */
489 writel( VAL0 | APAD_XMT|REX_RTRY , mmio + CMD2);
490 }else{
491 writel( VAL0 | APAD_XMT | REX_RTRY|REX_UFLO, mmio + CMD2);
492 writel((u32)JUMBO, mmio + CMD3);
493 }
494
495#if AMD8111E_VLAN_TAG_USED
496 writel((u32) VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3);
497#endif
498 writel( VAL0 | APAD_XMT | REX_RTRY, mmio + CMD2 );
6aa20a22 499
1da177e4
LT		 500 /* Setting the MAC address to the device */
501 for(i = 0; i < ETH_ADDR_LEN; i++)
6aa20a22 502 writeb( dev->dev_addr[i], mmio + PADR + i );
1da177e4
LT		 503
504 /* Enable interrupt coalesce */
505 if(lp->options & OPTION_INTR_COAL_ENABLE){
506 printk(KERN_INFO "%s: Interrupt Coalescing Enabled.\n",
507 dev->name);
508 amd8111e_set_coalesce(dev,ENABLE_COAL);
509 }
6aa20a22 510
1da177e4
LT		 511 /* set RUN bit to start the chip */
512 writel(VAL2 | RDMD0, mmio + CMD0);
513 writel(VAL0 | INTREN | RUN, mmio + CMD0);
6aa20a22 514
1da177e4
LT		 515 /* To avoid PCI posting bug */
516 readl(mmio+CMD0);
517 return 0;
518}
6aa20a22
JG		 519/*
520This function clears necessary the device registers.
521*/
1da177e4
LT		 522static void amd8111e_init_hw_default( struct amd8111e_priv* lp)
523{
524 unsigned int reg_val;
525 unsigned int logic_filter[2] ={0,};
526 void __iomem *mmio = lp->mmio;
527
528
529 /* stop the chip */
530 writel(RUN, mmio + CMD0);
531
532 /* AUTOPOLL0 Register *//*TBD default value is 8100 in FPS */
533 writew( 0x8100 | lp->ext_phy_addr, mmio + AUTOPOLL0);
534
535 /* Clear RCV_RING_BASE_ADDR */
536 writel(0, mmio + RCV_RING_BASE_ADDR0);
537
538 /* Clear XMT_RING_BASE_ADDR */
539 writel(0, mmio + XMT_RING_BASE_ADDR0);
540 writel(0, mmio + XMT_RING_BASE_ADDR1);
541 writel(0, mmio + XMT_RING_BASE_ADDR2);
542 writel(0, mmio + XMT_RING_BASE_ADDR3);
543
544 /* Clear CMD0 */
545 writel(CMD0_CLEAR,mmio + CMD0);
6aa20a22 546
1da177e4
LT		 547 /* Clear CMD2 */
548 writel(CMD2_CLEAR, mmio +CMD2);
549
550 /* Clear CMD7 */
551 writel(CMD7_CLEAR , mmio + CMD7);
552
553 /* Clear DLY_INT_A and DLY_INT_B */
554 writel(0x0, mmio + DLY_INT_A);
555 writel(0x0, mmio + DLY_INT_B);
556
557 /* Clear FLOW_CONTROL */
558 writel(0x0, mmio + FLOW_CONTROL);
559
560 /* Clear INT0 write 1 to clear register */
561 reg_val = readl(mmio + INT0);
562 writel(reg_val, mmio + INT0);
563
564 /* Clear STVAL */
565 writel(0x0, mmio + STVAL);
566
567 /* Clear INTEN0 */
568 writel( INTEN0_CLEAR, mmio + INTEN0);
569
570 /* Clear LADRF */
571 writel(0x0 , mmio + LADRF);
572
573 /* Set SRAM_SIZE & SRAM_BOUNDARY registers */
574 writel( 0x80010,mmio + SRAM_SIZE);
575
576 /* Clear RCV_RING0_LEN */
577 writel(0x0, mmio + RCV_RING_LEN0);
578
579 /* Clear XMT_RING0/1/2/3_LEN */
580 writel(0x0, mmio + XMT_RING_LEN0);
581 writel(0x0, mmio + XMT_RING_LEN1);
582 writel(0x0, mmio + XMT_RING_LEN2);
583 writel(0x0, mmio + XMT_RING_LEN3);
584
585 /* Clear XMT_RING_LIMIT */
586 writel(0x0, mmio + XMT_RING_LIMIT);
587
588 /* Clear MIB */
589 writew(MIB_CLEAR, mmio + MIB_ADDR);
590
591 /* Clear LARF */
592 amd8111e_writeq(*(u64*)logic_filter,mmio+LADRF);
593
594 /* SRAM_SIZE register */
595 reg_val = readl(mmio + SRAM_SIZE);
6aa20a22 596
1da177e4
LT		 597 if(lp->options & OPTION_JUMBO_ENABLE)
598 writel( VAL2|JUMBO, mmio + CMD3);
599#if AMD8111E_VLAN_TAG_USED
600 writel(VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3 );
601#endif
602 /* Set default value to CTRL1 Register */
603 writel(CTRL1_DEFAULT, mmio + CTRL1);
604
605 /* To avoid PCI posting bug */
606 readl(mmio + CMD2);
607
608}
609
6aa20a22
JG		 610/*
611This function disables the interrupt and clears all the pending
1da177e4
LT		 612interrupts in INT0
613 */
614static void amd8111e_disable_interrupt(struct amd8111e_priv* lp)
6aa20a22 615{
1da177e4
LT		 616 u32 intr0;
617
618 /* Disable interrupt */
619 writel(INTREN, lp->mmio + CMD0);
6aa20a22 620
1da177e4
LT		 621 /* Clear INT0 */
622 intr0 = readl(lp->mmio + INT0);
623 writel(intr0, lp->mmio + INT0);
6aa20a22 624
1da177e4
LT		 625 /* To avoid PCI posting bug */
626 readl(lp->mmio + INT0);
627
628}
629
630/*
6aa20a22 631This function stops the chip.
1da177e4
LT		 632*/
633static void amd8111e_stop_chip(struct amd8111e_priv* lp)
634{
635 writel(RUN, lp->mmio + CMD0);
6aa20a22 636
1da177e4
LT		 637 /* To avoid PCI posting bug */
638 readl(lp->mmio + CMD0);
639}
640
6aa20a22 641/*
1da177e4
LT		 642This function frees the transmiter and receiver descriptor rings.
643*/
644static void amd8111e_free_ring(struct amd8111e_priv* lp)
6aa20a22 645{
1da177e4
LT		 646 /* Free transmit and receive descriptor rings */
647 if(lp->rx_ring){
6aa20a22 648 pci_free_consistent(lp->pci_dev,
1da177e4
LT		 649 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,
650 lp->rx_ring, lp->rx_ring_dma_addr);
651 lp->rx_ring = NULL;
652 }
6aa20a22 653
1da177e4 654 if(lp->tx_ring){
6aa20a22 655 pci_free_consistent(lp->pci_dev,
1da177e4
LT		 656 sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,
657 lp->tx_ring, lp->tx_ring_dma_addr);
658
659 lp->tx_ring = NULL;
660 }
661
662}
6aa20a22
JG		 663#if AMD8111E_VLAN_TAG_USED
664/*
1da177e4 665This is the receive indication function for packets with vlan tag.
6aa20a22 666*/
1da177e4
LT		 667static int amd8111e_vlan_rx(struct amd8111e_priv *lp, struct sk_buff *skb, u16 vlan_tag)
668{
1da177e4 669 return vlan_hwaccel_receive_skb(skb, lp->vlgrp,vlan_tag);
1da177e4
LT		 670}
671#endif
672
673/*
6aa20a22 674This function will free all the transmit skbs that are actually transmitted by the device. It will check the ownership of the skb before freeing the skb.
1da177e4
LT		 675*/
676static int amd8111e_tx(struct net_device *dev)
677{
678 struct amd8111e_priv* lp = netdev_priv(dev);
679 int tx_index = lp->tx_complete_idx & TX_RING_DR_MOD_MASK;
680 int status;
681 /* Complete all the transmit packet */
682 while (lp->tx_complete_idx != lp->tx_idx){
683 tx_index = lp->tx_complete_idx & TX_RING_DR_MOD_MASK;
684 status = le16_to_cpu(lp->tx_ring[tx_index].tx_flags);
685
686 if(status & OWN_BIT)
687 break; /* It still hasn't been Txed */
688
689 lp->tx_ring[tx_index].buff_phy_addr = 0;
690
691 /* We must free the original skb */
692 if (lp->tx_skbuff[tx_index]) {
693 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[tx_index],
694 lp->tx_skbuff[tx_index]->len,
695 PCI_DMA_TODEVICE);
696 dev_kfree_skb_irq (lp->tx_skbuff[tx_index]);
697 lp->tx_skbuff[tx_index] = NULL;
698 lp->tx_dma_addr[tx_index] = 0;
699 }
700 lp->tx_complete_idx++;
701 /*COAL update tx coalescing parameters */
702 lp->coal_conf.tx_packets++;
05d2fec9
AV		 703 lp->coal_conf.tx_bytes +=
704 le16_to_cpu(lp->tx_ring[tx_index].buff_count);
1da177e4
LT		 705
706 if (netif_queue_stopped(dev) &&
707 lp->tx_complete_idx > lp->tx_idx - NUM_TX_BUFFERS +2){
708 /* The ring is no longer full, clear tbusy. */
709 /* lp->tx_full = 0; */
710 netif_wake_queue (dev);
711 }
712 }
713 return 0;
714}
715
1da177e4 716/* This function handles the driver receive operation in polling mode */
bea3348e 717static int amd8111e_rx_poll(struct napi_struct *napi, int budget)
1da177e4 718{
bea3348e
SH		 719 struct amd8111e_priv *lp = container_of(napi, struct amd8111e_priv, napi);
720 struct net_device *dev = lp->amd8111e_net_dev;
1da177e4
LT		 721 int rx_index = lp->rx_idx & RX_RING_DR_MOD_MASK;
722 void __iomem *mmio = lp->mmio;
723 struct sk_buff *skb,*new_skb;
724 int min_pkt_len, status;
725 unsigned int intr0;
726 int num_rx_pkt = 0;
1da177e4 727 short pkt_len;
6aa20a22 728#if AMD8111E_VLAN_TAG_USED
1da177e4
LT		 729 short vtag;
730#endif
bea3348e 731 int rx_pkt_limit = budget;
dfa1b73f 732 unsigned long flags;
6aa20a22
JG		 733
734 do{
1da177e4
LT		 735 /* process receive packets until we use the quota*/
736 /* If we own the next entry, it's a new packet. Send it up. */
737 while(1) {
738 status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags);
739 if (status & OWN_BIT)
740 break;
741
6aa20a22 742 /*
1da177e4
LT		 743 * There is a tricky error noted by John Murphy,
744 * <murf@perftech.com> to Russ Nelson: Even with
6aa20a22
JG		 745 * full-sized * buffers it's possible for a
746 * jabber packet to use two buffers, with only
1da177e4
LT		 747 * the last correctly noting the error.
748 */
749
750 if(status & ERR_BIT) {
751 /* reseting flags */
752 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
753 goto err_next_pkt;
754 }
755 /* check for STP and ENP */
756 if(!((status & STP_BIT) && (status & ENP_BIT))){
757 /* reseting flags */
758 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
759 goto err_next_pkt;
760 }
761 pkt_len = le16_to_cpu(lp->rx_ring[rx_index].msg_count) - 4;
762
6aa20a22 763#if AMD8111E_VLAN_TAG_USED
1da177e4 764 vtag = status & TT_MASK;
6aa20a22 765 /*MAC will strip vlan tag*/
1da177e4
LT		 766 if(lp->vlgrp != NULL && vtag !=0)
767 min_pkt_len =MIN_PKT_LEN - 4;
768 else
769#endif
770 min_pkt_len =MIN_PKT_LEN;
771
772 if (pkt_len < min_pkt_len) {
773 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
774 lp->drv_rx_errors++;
775 goto err_next_pkt;
776 }
777 if(--rx_pkt_limit < 0)
778 goto rx_not_empty;
779 if(!(new_skb = dev_alloc_skb(lp->rx_buff_len))){
6aa20a22 780 /* if allocation fail,
1da177e4
LT		 781 ignore that pkt and go to next one */
782 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
783 lp->drv_rx_errors++;
784 goto err_next_pkt;
785 }
6aa20a22 786
1da177e4
LT		 787 skb_reserve(new_skb, 2);
788 skb = lp->rx_skbuff[rx_index];
789 pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[rx_index],
790 lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
791 skb_put(skb, pkt_len);
1da177e4 792 lp->rx_skbuff[rx_index] = new_skb;
1da177e4
LT		 793 lp->rx_dma_addr[rx_index] = pci_map_single(lp->pci_dev,
794 new_skb->data,
795 lp->rx_buff_len-2,
796 PCI_DMA_FROMDEVICE);
6aa20a22 797
1da177e4
LT		 798 skb->protocol = eth_type_trans(skb, dev);
799
6aa20a22 800#if AMD8111E_VLAN_TAG_USED
1da177e4
LT		 801 if(lp->vlgrp != NULL && (vtag == TT_VLAN_TAGGED)){
802 amd8111e_vlan_rx(lp, skb,
803 le16_to_cpu(lp->rx_ring[rx_index].tag_ctrl_info));
804 } else
805#endif
806 netif_receive_skb(skb);
807 /*COAL update rx coalescing parameters*/
808 lp->coal_conf.rx_packets++;
6aa20a22 809 lp->coal_conf.rx_bytes += pkt_len;
1da177e4 810 num_rx_pkt++;
6aa20a22
JG		 811
812 err_next_pkt:
1da177e4
LT		 813 lp->rx_ring[rx_index].buff_phy_addr
814 = cpu_to_le32(lp->rx_dma_addr[rx_index]);
6aa20a22 815 lp->rx_ring[rx_index].buff_count =
1da177e4
LT		 816 cpu_to_le16(lp->rx_buff_len-2);
817 wmb();
818 lp->rx_ring[rx_index].rx_flags |= cpu_to_le16(OWN_BIT);
819 rx_index = (++lp->rx_idx) & RX_RING_DR_MOD_MASK;
820 }
6aa20a22 821 /* Check the interrupt status register for more packets in the
1da177e4
LT		 822 mean time. Process them since we have not used up our quota.*/
823
824 intr0 = readl(mmio + INT0);
825 /*Ack receive packets */
826 writel(intr0 & RINT0,mmio + INT0);
827
828 } while(intr0 & RINT0);
829
48e5ecae
CF		 830 if (rx_pkt_limit > 0) {
831 /* Receive descriptor is empty now */
832 spin_lock_irqsave(&lp->lock, flags);
288379f0 833 __napi_complete(napi);
48e5ecae
CF		 834 writel(VAL0|RINTEN0, mmio + INTEN0);
835 writel(VAL2 | RDMD0, mmio + CMD0);
836 spin_unlock_irqrestore(&lp->lock, flags);
837 }
dfa1b73f 838
1da177e4 839rx_not_empty:
bea3348e 840 return num_rx_pkt;
1da177e4
LT		 841}
842
6aa20a22 843/*
1da177e4
LT		 844This function will indicate the link status to the kernel.
845*/
846static int amd8111e_link_change(struct net_device* dev)
6aa20a22 847{
1da177e4
LT		 848 struct amd8111e_priv *lp = netdev_priv(dev);
849 int status0,speed;
850
851 /* read the link change */
852 status0 = readl(lp->mmio + STAT0);
6aa20a22 853
1da177e4
LT		 854 if(status0 & LINK_STATS){
855 if(status0 & AUTONEG_COMPLETE)
856 lp->link_config.autoneg = AUTONEG_ENABLE;
6aa20a22 857 else
1da177e4
LT		 858 lp->link_config.autoneg = AUTONEG_DISABLE;
859
860 if(status0 & FULL_DPLX)
861 lp->link_config.duplex = DUPLEX_FULL;
6aa20a22 862 else
1da177e4
LT		 863 lp->link_config.duplex = DUPLEX_HALF;
864 speed = (status0 & SPEED_MASK) >> 7;
865 if(speed == PHY_SPEED_10)
866 lp->link_config.speed = SPEED_10;
867 else if(speed == PHY_SPEED_100)
868 lp->link_config.speed = SPEED_100;
869
870 printk(KERN_INFO "%s: Link is Up. Speed is %s Mbps %s Duplex\n", dev->name,
6aa20a22
JG		 871 (lp->link_config.speed == SPEED_100) ? "100": "10",
872 (lp->link_config.duplex == DUPLEX_FULL)? "Full": "Half");
1da177e4
LT		 873 netif_carrier_on(dev);
874 }
6aa20a22 875 else{
1da177e4
LT		 876 lp->link_config.speed = SPEED_INVALID;
877 lp->link_config.duplex = DUPLEX_INVALID;
878 lp->link_config.autoneg = AUTONEG_INVALID;
879 printk(KERN_INFO "%s: Link is Down.\n",dev->name);
880 netif_carrier_off(dev);
881 }
6aa20a22 882
1da177e4
LT		 883 return 0;
884}
885/*
6aa20a22 886This function reads the mib counters.
1da177e4
LT		 887*/
888static int amd8111e_read_mib(void __iomem *mmio, u8 MIB_COUNTER)
889{
890 unsigned int status;
891 unsigned int data;
892 unsigned int repeat = REPEAT_CNT;
893
894 writew( MIB_RD_CMD | MIB_COUNTER, mmio + MIB_ADDR);
895 do {
896 status = readw(mmio + MIB_ADDR);
897 udelay(2); /* controller takes MAX 2 us to get mib data */
898 }
899 while (--repeat && (status & MIB_CMD_ACTIVE));
900
901 data = readl(mmio + MIB_DATA);
902 return data;
903}
904
905/*
906This function reads the mib registers and returns the hardware statistics. It updates previous internal driver statistics with new values.
6aa20a22 907*/
1da177e4
LT		 908static struct net_device_stats *amd8111e_get_stats(struct net_device * dev)
909{
910 struct amd8111e_priv *lp = netdev_priv(dev);
911 void __iomem *mmio = lp->mmio;
912 unsigned long flags;
913 /* struct net_device_stats *prev_stats = &lp->prev_stats; */
914 struct net_device_stats* new_stats = &lp->stats;
6aa20a22 915
1da177e4 916 if(!lp->opened)
6aa20a22 917 return &lp->stats;
1da177e4
LT		 918 spin_lock_irqsave (&lp->lock, flags);
919
920 /* stats.rx_packets */
921 new_stats->rx_packets = amd8111e_read_mib(mmio, rcv_broadcast_pkts)+
922 amd8111e_read_mib(mmio, rcv_multicast_pkts)+
923 amd8111e_read_mib(mmio, rcv_unicast_pkts);
924
925 /* stats.tx_packets */
926 new_stats->tx_packets = amd8111e_read_mib(mmio, xmt_packets);
927
928 /*stats.rx_bytes */
929 new_stats->rx_bytes = amd8111e_read_mib(mmio, rcv_octets);
930
931 /* stats.tx_bytes */
932 new_stats->tx_bytes = amd8111e_read_mib(mmio, xmt_octets);
933
934 /* stats.rx_errors */
935 /* hw errors + errors driver reported */
936 new_stats->rx_errors = amd8111e_read_mib(mmio, rcv_undersize_pkts)+
937 amd8111e_read_mib(mmio, rcv_fragments)+
938 amd8111e_read_mib(mmio, rcv_jabbers)+
939 amd8111e_read_mib(mmio, rcv_alignment_errors)+
940 amd8111e_read_mib(mmio, rcv_fcs_errors)+
941 amd8111e_read_mib(mmio, rcv_miss_pkts)+
942 lp->drv_rx_errors;
943
944 /* stats.tx_errors */
945 new_stats->tx_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
946
947 /* stats.rx_dropped*/
948 new_stats->rx_dropped = amd8111e_read_mib(mmio, rcv_miss_pkts);
949
950 /* stats.tx_dropped*/
951 new_stats->tx_dropped = amd8111e_read_mib(mmio, xmt_underrun_pkts);
952
953 /* stats.multicast*/
954 new_stats->multicast = amd8111e_read_mib(mmio, rcv_multicast_pkts);
955
956 /* stats.collisions*/
957 new_stats->collisions = amd8111e_read_mib(mmio, xmt_collisions);
958
959 /* stats.rx_length_errors*/
6aa20a22 960 new_stats->rx_length_errors =
1da177e4
LT		 961 amd8111e_read_mib(mmio, rcv_undersize_pkts)+
962 amd8111e_read_mib(mmio, rcv_oversize_pkts);
963
964 /* stats.rx_over_errors*/
965 new_stats->rx_over_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
966
967 /* stats.rx_crc_errors*/
968 new_stats->rx_crc_errors = amd8111e_read_mib(mmio, rcv_fcs_errors);
969
970 /* stats.rx_frame_errors*/
971 new_stats->rx_frame_errors =
972 amd8111e_read_mib(mmio, rcv_alignment_errors);
973
974 /* stats.rx_fifo_errors */
975 new_stats->rx_fifo_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
976
977 /* stats.rx_missed_errors */
978 new_stats->rx_missed_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
979
980 /* stats.tx_aborted_errors*/
6aa20a22 981 new_stats->tx_aborted_errors =
1da177e4
LT		 982 amd8111e_read_mib(mmio, xmt_excessive_collision);
983
984 /* stats.tx_carrier_errors*/
6aa20a22 985 new_stats->tx_carrier_errors =
1da177e4
LT		 986 amd8111e_read_mib(mmio, xmt_loss_carrier);
987
988 /* stats.tx_fifo_errors*/
989 new_stats->tx_fifo_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
990
991 /* stats.tx_window_errors*/
992 new_stats->tx_window_errors =
993 amd8111e_read_mib(mmio, xmt_late_collision);
994
995 /* Reset the mibs for collecting new statistics */
996 /* writew(MIB_CLEAR, mmio + MIB_ADDR);*/
6aa20a22 997
1da177e4
LT		 998 spin_unlock_irqrestore (&lp->lock, flags);
999
1000 return new_stats;
1001}
3a4fa0a2 1002/* This function recalculate the interrupt coalescing mode on every interrupt
1da177e4
LT		 1003according to the datarate and the packet rate.
1004*/
1005static int amd8111e_calc_coalesce(struct net_device *dev)
1006{
1007 struct amd8111e_priv *lp = netdev_priv(dev);
1008 struct amd8111e_coalesce_conf * coal_conf = &lp->coal_conf;
1009 int tx_pkt_rate;
1010 int rx_pkt_rate;
1011 int tx_data_rate;
1012 int rx_data_rate;
1013 int rx_pkt_size;
1014 int tx_pkt_size;
1015
1016 tx_pkt_rate = coal_conf->tx_packets - coal_conf->tx_prev_packets;
1017 coal_conf->tx_prev_packets = coal_conf->tx_packets;
6aa20a22 1018
1da177e4
LT		 1019 tx_data_rate = coal_conf->tx_bytes - coal_conf->tx_prev_bytes;
1020 coal_conf->tx_prev_bytes = coal_conf->tx_bytes;
6aa20a22 1021
1da177e4
LT		 1022 rx_pkt_rate = coal_conf->rx_packets - coal_conf->rx_prev_packets;
1023 coal_conf->rx_prev_packets = coal_conf->rx_packets;
6aa20a22 1024
1da177e4
LT		 1025 rx_data_rate = coal_conf->rx_bytes - coal_conf->rx_prev_bytes;
1026 coal_conf->rx_prev_bytes = coal_conf->rx_bytes;
6aa20a22 1027
1da177e4
LT		 1028 if(rx_pkt_rate < 800){
1029 if(coal_conf->rx_coal_type != NO_COALESCE){
6aa20a22 1030
1da177e4
LT		 1031 coal_conf->rx_timeout = 0x0;
1032 coal_conf->rx_event_count = 0;
1033 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1034 coal_conf->rx_coal_type = NO_COALESCE;
1035 }
1036 }
1037 else{
6aa20a22 1038
1da177e4
LT		 1039 rx_pkt_size = rx_data_rate/rx_pkt_rate;
1040 if (rx_pkt_size < 128){
1041 if(coal_conf->rx_coal_type != NO_COALESCE){
6aa20a22 1042
1da177e4
LT		 1043 coal_conf->rx_timeout = 0;
1044 coal_conf->rx_event_count = 0;
1045 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1046 coal_conf->rx_coal_type = NO_COALESCE;
1047 }
1048
1049 }
1050 else if ( (rx_pkt_size >= 128) && (rx_pkt_size < 512) ){
6aa20a22 1051
1da177e4
LT		 1052 if(coal_conf->rx_coal_type != LOW_COALESCE){
1053 coal_conf->rx_timeout = 1;
1054 coal_conf->rx_event_count = 4;
1055 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1056 coal_conf->rx_coal_type = LOW_COALESCE;
1057 }
1058 }
1059 else if ((rx_pkt_size >= 512) && (rx_pkt_size < 1024)){
6aa20a22 1060
1da177e4
LT		 1061 if(coal_conf->rx_coal_type != MEDIUM_COALESCE){
1062 coal_conf->rx_timeout = 1;
1063 coal_conf->rx_event_count = 4;
1064 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1065 coal_conf->rx_coal_type = MEDIUM_COALESCE;
6aa20a22
JG		 1066 }
1067
1da177e4
LT		 1068 }
1069 else if(rx_pkt_size >= 1024){
1070 if(coal_conf->rx_coal_type != HIGH_COALESCE){
1071 coal_conf->rx_timeout = 2;
1072 coal_conf->rx_event_count = 3;
1073 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1074 coal_conf->rx_coal_type = HIGH_COALESCE;
6aa20a22 1075 }
1da177e4
LT		 1076 }
1077 }
1078 /* NOW FOR TX INTR COALESC */
1079 if(tx_pkt_rate < 800){
1080 if(coal_conf->tx_coal_type != NO_COALESCE){
6aa20a22 1081
1da177e4
LT		 1082 coal_conf->tx_timeout = 0x0;
1083 coal_conf->tx_event_count = 0;
1084 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1085 coal_conf->tx_coal_type = NO_COALESCE;
1086 }
1087 }
1088 else{
6aa20a22 1089
1da177e4
LT		 1090 tx_pkt_size = tx_data_rate/tx_pkt_rate;
1091 if (tx_pkt_size < 128){
6aa20a22 1092
1da177e4 1093 if(coal_conf->tx_coal_type != NO_COALESCE){
6aa20a22 1094
1da177e4
LT		 1095 coal_conf->tx_timeout = 0;
1096 coal_conf->tx_event_count = 0;
1097 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1098 coal_conf->tx_coal_type = NO_COALESCE;
1099 }
1100
1101 }
1102 else if ( (tx_pkt_size >= 128) && (tx_pkt_size < 512) ){
6aa20a22 1103
1da177e4
LT		 1104 if(coal_conf->tx_coal_type != LOW_COALESCE){
1105 coal_conf->tx_timeout = 1;
1106 coal_conf->tx_event_count = 2;
1107 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1108 coal_conf->tx_coal_type = LOW_COALESCE;
1109
1110 }
1111 }
1112 else if ((tx_pkt_size >= 512) && (tx_pkt_size < 1024)){
6aa20a22 1113
1da177e4
LT		 1114 if(coal_conf->tx_coal_type != MEDIUM_COALESCE){
1115 coal_conf->tx_timeout = 2;
1116 coal_conf->tx_event_count = 5;
1117 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1118 coal_conf->tx_coal_type = MEDIUM_COALESCE;
6aa20a22
JG		 1119 }
1120
1da177e4
LT		 1121 }
1122 else if(tx_pkt_size >= 1024){
1123 if (tx_pkt_size >= 1024){
1124 if(coal_conf->tx_coal_type != HIGH_COALESCE){
1125 coal_conf->tx_timeout = 4;
1126 coal_conf->tx_event_count = 8;
1127 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1128 coal_conf->tx_coal_type = HIGH_COALESCE;
6aa20a22 1129 }
1da177e4
LT		 1130 }
1131 }
1132 }
1133 return 0;
1134
1135}
1136/*
1137This is device interrupt function. It handles transmit, receive,link change and hardware timer interrupts.
1138*/
7d12e780 1139static irqreturn_t amd8111e_interrupt(int irq, void *dev_id)
1da177e4
LT		 1140{
1141
1142 struct net_device * dev = (struct net_device *) dev_id;
1143 struct amd8111e_priv *lp = netdev_priv(dev);
1144 void __iomem *mmio = lp->mmio;
dfa1b73f 1145 unsigned int intr0, intren0;
1da177e4
LT		 1146 unsigned int handled = 1;
1147
dfa1b73f 1148 if(unlikely(dev == NULL))
1da177e4
LT		 1149 return IRQ_NONE;
1150
dfa1b73f
LT		 1151 spin_lock(&lp->lock);
1152
1da177e4
LT		 1153 /* disabling interrupt */
1154 writel(INTREN, mmio + CMD0);
1155
1156 /* Read interrupt status */
1157 intr0 = readl(mmio + INT0);
dfa1b73f 1158 intren0 = readl(mmio + INTEN0);
1da177e4
LT		 1159
1160 /* Process all the INT event until INTR bit is clear. */
1161
1162 if (!(intr0 & INTR)){
1163 handled = 0;
1164 goto err_no_interrupt;
1165 }
6aa20a22 1166
1da177e4
LT		 1167 /* Current driver processes 4 interrupts : RINT,TINT,LCINT,STINT */
1168 writel(intr0, mmio + INT0);
1169
1170 /* Check if Receive Interrupt has occurred. */
6ba33ac8 1171 if (intr0 & RINT0) {
288379f0 1172 if (napi_schedule_prep(&lp->napi)) {
1da177e4
LT		 1173 /* Disable receive interupts */
1174 writel(RINTEN0, mmio + INTEN0);
1175 /* Schedule a polling routine */
288379f0 1176 __napi_schedule(&lp->napi);
6ba33ac8 1177 } else if (intren0 & RINTEN0) {
91e83432 1178 printk("************Driver bug! interrupt while in poll\n");
dfa1b73f
LT		 1179 /* Fix by disable receive interrupts */
1180 writel(RINTEN0, mmio + INTEN0);
1da177e4
LT		 1181 }
1182 }
6ba33ac8 1183
1da177e4 1184 /* Check if Transmit Interrupt has occurred. */
6ba33ac8 1185 if (intr0 & TINT0)
1da177e4 1186 amd8111e_tx(dev);
6aa20a22 1187
1da177e4
LT		 1188 /* Check if Link Change Interrupt has occurred. */
1189 if (intr0 & LCINT)
1190 amd8111e_link_change(dev);
1191
1192 /* Check if Hardware Timer Interrupt has occurred. */
1193 if (intr0 & STINT)
1194 amd8111e_calc_coalesce(dev);
1195
1196err_no_interrupt:
1197 writel( VAL0 | INTREN,mmio + CMD0);
6aa20a22 1198
dfa1b73f 1199 spin_unlock(&lp->lock);
6aa20a22 1200
1da177e4
LT		 1201 return IRQ_RETVAL(handled);
1202}
1203
1204#ifdef CONFIG_NET_POLL_CONTROLLER
1205static void amd8111e_poll(struct net_device *dev)
6aa20a22 1206{
1da177e4 1207 unsigned long flags;
b7e36bfa 1208 local_irq_save(flags);
7d12e780 1209 amd8111e_interrupt(0, dev);
6aa20a22
JG		 1210 local_irq_restore(flags);
1211}
1da177e4
LT		 1212#endif
1213
1214
1215/*
1216This function closes the network interface and updates the statistics so that most recent statistics will be available after the interface is down.
1217*/
1218static int amd8111e_close(struct net_device * dev)
1219{
1220 struct amd8111e_priv *lp = netdev_priv(dev);
1221 netif_stop_queue(dev);
6aa20a22 1222
bea3348e
SH		 1223 napi_disable(&lp->napi);
1224
1da177e4 1225 spin_lock_irq(&lp->lock);
6aa20a22 1226
1da177e4
LT		 1227 amd8111e_disable_interrupt(lp);
1228 amd8111e_stop_chip(lp);
e83603fd
CL		 1229
1230 /* Free transmit and receive skbs */
1231 amd8111e_free_skbs(lp->amd8111e_net_dev);
6aa20a22 1232
1da177e4
LT		 1233 netif_carrier_off(lp->amd8111e_net_dev);
1234
1235 /* Delete ipg timer */
6aa20a22 1236 if(lp->options & OPTION_DYN_IPG_ENABLE)
1da177e4
LT		 1237 del_timer_sync(&lp->ipg_data.ipg_timer);
1238
1239 spin_unlock_irq(&lp->lock);
1240 free_irq(dev->irq, dev);
e83603fd 1241 amd8111e_free_ring(lp);
6aa20a22 1242
1da177e4
LT		 1243 /* Update the statistics before closing */
1244 amd8111e_get_stats(dev);
1245 lp->opened = 0;
1246 return 0;
1247}
6aa20a22 1248/* This function opens new interface.It requests irq for the device, initializes the device,buffers and descriptors, and starts the device.
1da177e4
LT		 1249*/
1250static int amd8111e_open(struct net_device * dev )
1251{
1252 struct amd8111e_priv *lp = netdev_priv(dev);
1253
1fb9df5d 1254 if(dev->irq ==0 || request_irq(dev->irq, amd8111e_interrupt, IRQF_SHARED,
6aa20a22 1255 dev->name, dev))
1da177e4
LT		 1256 return -EAGAIN;
1257
bea3348e
SH		 1258 napi_enable(&lp->napi);
1259
1da177e4
LT		 1260 spin_lock_irq(&lp->lock);
1261
1262 amd8111e_init_hw_default(lp);
1263
1264 if(amd8111e_restart(dev)){
1265 spin_unlock_irq(&lp->lock);
bea3348e 1266 napi_disable(&lp->napi);
1da177e4
LT		 1267 if (dev->irq)
1268 free_irq(dev->irq, dev);
1269 return -ENOMEM;
1270 }
1271 /* Start ipg timer */
6aa20a22 1272 if(lp->options & OPTION_DYN_IPG_ENABLE){
1da177e4
LT		 1273 add_timer(&lp->ipg_data.ipg_timer);
1274 printk(KERN_INFO "%s: Dynamic IPG Enabled.\n",dev->name);
1275 }
1276
1277 lp->opened = 1;
1278
1279 spin_unlock_irq(&lp->lock);
1280
1281 netif_start_queue(dev);
1282
6aa20a22 1283 return 0;
1da177e4 1284}
6aa20a22 1285/*
1da177e4
LT		 1286This function checks if there is any transmit descriptors available to queue more packet.
1287*/
1288static int amd8111e_tx_queue_avail(struct amd8111e_priv* lp )
6aa20a22 1289{
1da177e4 1290 int tx_index = lp->tx_idx & TX_BUFF_MOD_MASK;
ee41a82f 1291 if (lp->tx_skbuff[tx_index])
1da177e4
LT		 1292 return -1;
1293 else
1294 return 0;
6aa20a22 1295
1da177e4 1296}
6aa20a22 1297/*
1da177e4
LT		 1298This function will queue the transmit packets to the descriptors and will trigger the send operation. It also initializes the transmit descriptors with buffer physical address, byte count, ownership to hardware etc.
1299*/
1300
61357325
SH		 1301static netdev_tx_t amd8111e_start_xmit(struct sk_buff *skb,
1302 struct net_device * dev)
1da177e4
LT		 1303{
1304 struct amd8111e_priv *lp = netdev_priv(dev);
1305 int tx_index;
1306 unsigned long flags;
1307
1308 spin_lock_irqsave(&lp->lock, flags);
1309
1310 tx_index = lp->tx_idx & TX_RING_DR_MOD_MASK;
1311
1312 lp->tx_ring[tx_index].buff_count = cpu_to_le16(skb->len);
1313
1314 lp->tx_skbuff[tx_index] = skb;
1315 lp->tx_ring[tx_index].tx_flags = 0;
1316
1317#if AMD8111E_VLAN_TAG_USED
1318 if((lp->vlgrp != NULL) && vlan_tx_tag_present(skb)){
6aa20a22
JG		 1319 lp->tx_ring[tx_index].tag_ctrl_cmd |=
1320 cpu_to_le16(TCC_VLAN_INSERT);
1321 lp->tx_ring[tx_index].tag_ctrl_info =
1da177e4
LT		 1322 cpu_to_le16(vlan_tx_tag_get(skb));
1323
1324 }
1325#endif
1326 lp->tx_dma_addr[tx_index] =
1327 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
1328 lp->tx_ring[tx_index].buff_phy_addr =
ee41a82f 1329 cpu_to_le32(lp->tx_dma_addr[tx_index]);
1da177e4
LT		 1330
1331 /* Set FCS and LTINT bits */
1332 wmb();
1333 lp->tx_ring[tx_index].tx_flags |=
1334 cpu_to_le16(OWN_BIT | STP_BIT | ENP_BIT|ADD_FCS_BIT|LTINT_BIT);
1335
1336 lp->tx_idx++;
1337
1338 /* Trigger an immediate send poll. */
1339 writel( VAL1 | TDMD0, lp->mmio + CMD0);
1340 writel( VAL2 | RDMD0,lp->mmio + CMD0);
1341
1342 dev->trans_start = jiffies;
1343
1344 if(amd8111e_tx_queue_avail(lp) < 0){
1345 netif_stop_queue(dev);
1346 }
1347 spin_unlock_irqrestore(&lp->lock, flags);
6ed10654 1348 return NETDEV_TX_OK;
1da177e4
LT		 1349}
1350/*
1351This function returns all the memory mapped registers of the device.
1352*/
1353static void amd8111e_read_regs(struct amd8111e_priv *lp, u32 *buf)
1354{
1355 void __iomem *mmio = lp->mmio;
1356 /* Read only necessary registers */
1357 buf[0] = readl(mmio + XMT_RING_BASE_ADDR0);
1358 buf[1] = readl(mmio + XMT_RING_LEN0);
1359 buf[2] = readl(mmio + RCV_RING_BASE_ADDR0);
1360 buf[3] = readl(mmio + RCV_RING_LEN0);
1361 buf[4] = readl(mmio + CMD0);
1362 buf[5] = readl(mmio + CMD2);
1363 buf[6] = readl(mmio + CMD3);
1364 buf[7] = readl(mmio + CMD7);
1365 buf[8] = readl(mmio + INT0);
1366 buf[9] = readl(mmio + INTEN0);
1367 buf[10] = readl(mmio + LADRF);
1368 buf[11] = readl(mmio + LADRF+4);
1369 buf[12] = readl(mmio + STAT0);
1370}
1371
6aa20a22 1372
1da177e4 1373/*
6aa20a22 1374This function sets promiscuos mode, all-multi mode or the multicast address
1da177e4
LT		 1375list to the device.
1376*/
1377static void amd8111e_set_multicast_list(struct net_device *dev)
1378{
0ddf477b 1379 struct dev_mc_list *mc_ptr;
1da177e4
LT		 1380 struct amd8111e_priv *lp = netdev_priv(dev);
1381 u32 mc_filter[2] ;
0ddf477b
JP		 1382 int bit_num;
1383
1da177e4 1384 if(dev->flags & IFF_PROMISC){
1da177e4
LT		 1385 writel( VAL2 | PROM, lp->mmio + CMD2);
1386 return;
1387 }
1388 else
1389 writel( PROM, lp->mmio + CMD2);
4cd24eaf
JP		 1390 if (dev->flags & IFF_ALLMULTI ||
1391 netdev_mc_count(dev) > MAX_FILTER_SIZE) {
1da177e4
LT		 1392 /* get all multicast packet */
1393 mc_filter[1] = mc_filter[0] = 0xffffffff;
1da177e4
LT		 1394 lp->options |= OPTION_MULTICAST_ENABLE;
1395 amd8111e_writeq(*(u64*)mc_filter,lp->mmio + LADRF);
1396 return;
1397 }
4cd24eaf 1398 if (netdev_mc_empty(dev)) {
1da177e4
LT		 1399 /* get only own packets */
1400 mc_filter[1] = mc_filter[0] = 0;
1da177e4
LT		 1401 lp->options &= ~OPTION_MULTICAST_ENABLE;
1402 amd8111e_writeq(*(u64*)mc_filter,lp->mmio + LADRF);
1403 /* disable promiscous mode */
1404 writel(PROM, lp->mmio + CMD2);
1405 return;
1406 }
1407 /* load all the multicast addresses in the logic filter */
1408 lp->options |= OPTION_MULTICAST_ENABLE;
1da177e4 1409 mc_filter[1] = mc_filter[0] = 0;
0ddf477b 1410 netdev_for_each_mc_addr(mc_ptr, dev) {
6b4bdde6 1411 bit_num = (ether_crc_le(ETH_ALEN, mc_ptr->dmi_addr) >> 26) & 0x3f;
1da177e4 1412 mc_filter[bit_num >> 5] |= 1 << (bit_num & 31);
6aa20a22 1413 }
1da177e4
LT		 1414 amd8111e_writeq(*(u64*)mc_filter,lp->mmio+ LADRF);
1415
1416 /* To eliminate PCI posting bug */
1417 readl(lp->mmio + CMD2);
1418
1419}
1420
1421static void amd8111e_get_drvinfo(struct net_device* dev, struct ethtool_drvinfo *info)
1422{
1423 struct amd8111e_priv *lp = netdev_priv(dev);
1424 struct pci_dev *pci_dev = lp->pci_dev;
1425 strcpy (info->driver, MODULE_NAME);
1426 strcpy (info->version, MODULE_VERS);
1427 sprintf(info->fw_version,"%u",chip_version);
1428 strcpy (info->bus_info, pci_name(pci_dev));
1429}
1430
1431static int amd8111e_get_regs_len(struct net_device *dev)
1432{
1433 return AMD8111E_REG_DUMP_LEN;
1434}
1435
1436static void amd8111e_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
1437{
1438 struct amd8111e_priv *lp = netdev_priv(dev);
1439 regs->version = 0;
1440 amd8111e_read_regs(lp, buf);
1441}
1442
1443static int amd8111e_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1444{
1445 struct amd8111e_priv *lp = netdev_priv(dev);
1446 spin_lock_irq(&lp->lock);
1447 mii_ethtool_gset(&lp->mii_if, ecmd);
1448 spin_unlock_irq(&lp->lock);
1449 return 0;
1450}
1451
1452static int amd8111e_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1453{
1454 struct amd8111e_priv *lp = netdev_priv(dev);
1455 int res;
1456 spin_lock_irq(&lp->lock);
1457 res = mii_ethtool_sset(&lp->mii_if, ecmd);
1458 spin_unlock_irq(&lp->lock);
1459 return res;
1460}
1461
1462static int amd8111e_nway_reset(struct net_device *dev)
1463{
1464 struct amd8111e_priv *lp = netdev_priv(dev);
1465 return mii_nway_restart(&lp->mii_if);
1466}
1467
1468static u32 amd8111e_get_link(struct net_device *dev)
1469{
1470 struct amd8111e_priv *lp = netdev_priv(dev);
1471 return mii_link_ok(&lp->mii_if);
1472}
1473
1474static void amd8111e_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info)
1475{
1476 struct amd8111e_priv *lp = netdev_priv(dev);
1477 wol_info->supported = WAKE_MAGIC|WAKE_PHY;
1478 if (lp->options & OPTION_WOL_ENABLE)
1479 wol_info->wolopts = WAKE_MAGIC;
1480}
1481
1482static int amd8111e_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info)
1483{
1484 struct amd8111e_priv *lp = netdev_priv(dev);
1485 if (wol_info->wolopts & ~(WAKE_MAGIC|WAKE_PHY))
1486 return -EINVAL;
1487 spin_lock_irq(&lp->lock);
1488 if (wol_info->wolopts & WAKE_MAGIC)
6aa20a22 1489 lp->options |=
1da177e4
LT		 1490 (OPTION_WOL_ENABLE | OPTION_WAKE_MAGIC_ENABLE);
1491 else if(wol_info->wolopts & WAKE_PHY)
6aa20a22 1492 lp->options |=
1da177e4
LT		 1493 (OPTION_WOL_ENABLE | OPTION_WAKE_PHY_ENABLE);
1494 else
6aa20a22 1495 lp->options &= ~OPTION_WOL_ENABLE;
1da177e4
LT		 1496 spin_unlock_irq(&lp->lock);
1497 return 0;
1498}
1499
7282d491 1500static const struct ethtool_ops ops = {
1da177e4
LT		 1501 .get_drvinfo = amd8111e_get_drvinfo,
1502 .get_regs_len = amd8111e_get_regs_len,
1503 .get_regs = amd8111e_get_regs,
1504 .get_settings = amd8111e_get_settings,
1505 .set_settings = amd8111e_set_settings,
1506 .nway_reset = amd8111e_nway_reset,
1507 .get_link = amd8111e_get_link,
1508 .get_wol = amd8111e_get_wol,
1509 .set_wol = amd8111e_set_wol,
1510};
1511
1512/*
6aa20a22 1513This function handles all the ethtool ioctls. It gives driver info, gets/sets driver speed, gets memory mapped register values, forces auto negotiation, sets/gets WOL options for ethtool application.
1da177e4 1514*/
6aa20a22 1515
1da177e4
LT		 1516static int amd8111e_ioctl(struct net_device * dev , struct ifreq *ifr, int cmd)
1517{
1518 struct mii_ioctl_data *data = if_mii(ifr);
1519 struct amd8111e_priv *lp = netdev_priv(dev);
1520 int err;
1521 u32 mii_regval;
1522
1da177e4
LT		 1523 switch(cmd) {
1524 case SIOCGMIIPHY:
1525 data->phy_id = lp->ext_phy_addr;
1526
1527 /* fallthru */
6aa20a22 1528 case SIOCGMIIREG:
1da177e4
LT		 1529
1530 spin_lock_irq(&lp->lock);
1531 err = amd8111e_read_phy(lp, data->phy_id,
1532 data->reg_num & PHY_REG_ADDR_MASK, &mii_regval);
1533 spin_unlock_irq(&lp->lock);
1534
1535 data->val_out = mii_regval;
1536 return err;
1537
1538 case SIOCSMIIREG:
1539
1540 spin_lock_irq(&lp->lock);
1541 err = amd8111e_write_phy(lp, data->phy_id,
1542 data->reg_num & PHY_REG_ADDR_MASK, data->val_in);
1543 spin_unlock_irq(&lp->lock);
1544
1545 return err;
1546
1547 default:
1548 /* do nothing */
1549 break;
1550 }
1551 return -EOPNOTSUPP;
1552}
1553static int amd8111e_set_mac_address(struct net_device *dev, void *p)
1554{
1555 struct amd8111e_priv *lp = netdev_priv(dev);
1556 int i;
1557 struct sockaddr *addr = p;
1558
1559 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1560 spin_lock_irq(&lp->lock);
1561 /* Setting the MAC address to the device */
1562 for(i = 0; i < ETH_ADDR_LEN; i++)
6aa20a22
JG		 1563 writeb( dev->dev_addr[i], lp->mmio + PADR + i );
1564
1da177e4
LT		 1565 spin_unlock_irq(&lp->lock);
1566
1567 return 0;
1568}
1569
6aa20a22 1570/*
1da177e4 1571This function changes the mtu of the device. It restarts the device to initialize the descriptor with new receive buffers.
6aa20a22 1572*/
1da177e4
LT		 1573static int amd8111e_change_mtu(struct net_device *dev, int new_mtu)
1574{
1575 struct amd8111e_priv *lp = netdev_priv(dev);
1576 int err;
1577
1578 if ((new_mtu < AMD8111E_MIN_MTU) || (new_mtu > AMD8111E_MAX_MTU))
1579 return -EINVAL;
1580
1581 if (!netif_running(dev)) {
1582 /* new_mtu will be used
6aa20a22 1583 when device starts netxt time */
1da177e4
LT		 1584 dev->mtu = new_mtu;
1585 return 0;
1586 }
1587
1588 spin_lock_irq(&lp->lock);
1589
1590 /* stop the chip */
1591 writel(RUN, lp->mmio + CMD0);
1592
1593 dev->mtu = new_mtu;
1594
1595 err = amd8111e_restart(dev);
1596 spin_unlock_irq(&lp->lock);
1597 if(!err)
1598 netif_start_queue(dev);
1599 return err;
1600}
1601
1602#if AMD8111E_VLAN_TAG_USED
1603static void amd8111e_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1604{
1605 struct amd8111e_priv *lp = netdev_priv(dev);
1606 spin_lock_irq(&lp->lock);
1607 lp->vlgrp = grp;
1608 spin_unlock_irq(&lp->lock);
1609}
1da177e4 1610#endif
25805dcf 1611
1da177e4
LT		 1612static int amd8111e_enable_magicpkt(struct amd8111e_priv* lp)
1613{
1614 writel( VAL1|MPPLBA, lp->mmio + CMD3);
1615 writel( VAL0|MPEN_SW, lp->mmio + CMD7);
1616
1617 /* To eliminate PCI posting bug */
1618 readl(lp->mmio + CMD7);
1619 return 0;
1620}
1621
1622static int amd8111e_enable_link_change(struct amd8111e_priv* lp)
1623{
1624
1625 /* Adapter is already stoped/suspended/interrupt-disabled */
1626 writel(VAL0|LCMODE_SW,lp->mmio + CMD7);
6aa20a22 1627
1da177e4
LT		 1628 /* To eliminate PCI posting bug */
1629 readl(lp->mmio + CMD7);
1630 return 0;
6aa20a22 1631}
1da177e4 1632
af901ca1
AGR		 1633/*
1634 * This function is called when a packet transmission fails to complete
1635 * within a reasonable period, on the assumption that an interrupt have
1636 * failed or the interface is locked up. This function will reinitialize
1637 * the hardware.
1638 */
1da177e4
LT		 1639static void amd8111e_tx_timeout(struct net_device *dev)
1640{
1641 struct amd8111e_priv* lp = netdev_priv(dev);
1642 int err;
1643
1644 printk(KERN_ERR "%s: transmit timed out, resetting\n",
1645 dev->name);
1646 spin_lock_irq(&lp->lock);
1647 err = amd8111e_restart(dev);
1648 spin_unlock_irq(&lp->lock);
1649 if(!err)
1650 netif_wake_queue(dev);
1651}
1652static int amd8111e_suspend(struct pci_dev *pci_dev, pm_message_t state)
6aa20a22 1653{
1da177e4
LT		 1654 struct net_device *dev = pci_get_drvdata(pci_dev);
1655 struct amd8111e_priv *lp = netdev_priv(dev);
6aa20a22 1656
1da177e4
LT		 1657 if (!netif_running(dev))
1658 return 0;
1659
1660 /* disable the interrupt */
1661 spin_lock_irq(&lp->lock);
1662 amd8111e_disable_interrupt(lp);
1663 spin_unlock_irq(&lp->lock);
1664
1665 netif_device_detach(dev);
6aa20a22 1666
1da177e4
LT		 1667 /* stop chip */
1668 spin_lock_irq(&lp->lock);
6aa20a22 1669 if(lp->options & OPTION_DYN_IPG_ENABLE)
1da177e4
LT		 1670 del_timer_sync(&lp->ipg_data.ipg_timer);
1671 amd8111e_stop_chip(lp);
1672 spin_unlock_irq(&lp->lock);
1673
1674 if(lp->options & OPTION_WOL_ENABLE){
1675 /* enable wol */
1676 if(lp->options & OPTION_WAKE_MAGIC_ENABLE)
6aa20a22 1677 amd8111e_enable_magicpkt(lp);
1da177e4 1678 if(lp->options & OPTION_WAKE_PHY_ENABLE)
6aa20a22
JG		 1679 amd8111e_enable_link_change(lp);
1680
1da177e4
LT		 1681 pci_enable_wake(pci_dev, PCI_D3hot, 1);
1682 pci_enable_wake(pci_dev, PCI_D3cold, 1);
1683
1684 }
6aa20a22 1685 else{
1da177e4
LT		 1686 pci_enable_wake(pci_dev, PCI_D3hot, 0);
1687 pci_enable_wake(pci_dev, PCI_D3cold, 0);
1688 }
6aa20a22 1689
1da177e4
LT		 1690 pci_save_state(pci_dev);
1691 pci_set_power_state(pci_dev, PCI_D3hot);
1692
1693 return 0;
1694}
1695static int amd8111e_resume(struct pci_dev *pci_dev)
1696{
1697 struct net_device *dev = pci_get_drvdata(pci_dev);
1698 struct amd8111e_priv *lp = netdev_priv(dev);
6aa20a22 1699
1da177e4
LT		 1700 if (!netif_running(dev))
1701 return 0;
1702
1703 pci_set_power_state(pci_dev, PCI_D0);
1704 pci_restore_state(pci_dev);
1705
1706 pci_enable_wake(pci_dev, PCI_D3hot, 0);
1707 pci_enable_wake(pci_dev, PCI_D3cold, 0); /* D3 cold */
1708
1709 netif_device_attach(dev);
1710
1711 spin_lock_irq(&lp->lock);
1712 amd8111e_restart(dev);
1713 /* Restart ipg timer */
6aa20a22
JG		 1714 if(lp->options & OPTION_DYN_IPG_ENABLE)
1715 mod_timer(&lp->ipg_data.ipg_timer,
1da177e4
LT		 1716 jiffies + IPG_CONVERGE_JIFFIES);
1717 spin_unlock_irq(&lp->lock);
1718
1719 return 0;
1720}
1721
1722
1723static void __devexit amd8111e_remove_one(struct pci_dev *pdev)
1724{
1725 struct net_device *dev = pci_get_drvdata(pdev);
1726 if (dev) {
1727 unregister_netdev(dev);
1728 iounmap(((struct amd8111e_priv *)netdev_priv(dev))->mmio);
1729 free_netdev(dev);
1730 pci_release_regions(pdev);
1731 pci_disable_device(pdev);
1732 pci_set_drvdata(pdev, NULL);
1733 }
1734}
1735static void amd8111e_config_ipg(struct net_device* dev)
1736{
1737 struct amd8111e_priv *lp = netdev_priv(dev);
1738 struct ipg_info* ipg_data = &lp->ipg_data;
1739 void __iomem *mmio = lp->mmio;
1740 unsigned int prev_col_cnt = ipg_data->col_cnt;
1741 unsigned int total_col_cnt;
1742 unsigned int tmp_ipg;
6aa20a22 1743
1da177e4
LT		 1744 if(lp->link_config.duplex == DUPLEX_FULL){
1745 ipg_data->ipg = DEFAULT_IPG;
1746 return;
1747 }
1748
1749 if(ipg_data->ipg_state == SSTATE){
6aa20a22 1750
1da177e4 1751 if(ipg_data->timer_tick == IPG_STABLE_TIME){
6aa20a22 1752
1da177e4
LT		 1753 ipg_data->timer_tick = 0;
1754 ipg_data->ipg = MIN_IPG - IPG_STEP;
1755 ipg_data->current_ipg = MIN_IPG;
1756 ipg_data->diff_col_cnt = 0xFFFFFFFF;
1757 ipg_data->ipg_state = CSTATE;
1758 }
1759 else
1760 ipg_data->timer_tick++;
1761 }
1762
1763 if(ipg_data->ipg_state == CSTATE){
6aa20a22 1764
1da177e4
LT		 1765 /* Get the current collision count */
1766
6aa20a22 1767 total_col_cnt = ipg_data->col_cnt =
1da177e4
LT		 1768 amd8111e_read_mib(mmio, xmt_collisions);
1769
6aa20a22 1770 if ((total_col_cnt - prev_col_cnt) <
1da177e4 1771 (ipg_data->diff_col_cnt)){
6aa20a22 1772
1da177e4
LT		 1773 ipg_data->diff_col_cnt =
1774 total_col_cnt - prev_col_cnt ;
1775
1776 ipg_data->ipg = ipg_data->current_ipg;
1777 }
1778
1779 ipg_data->current_ipg += IPG_STEP;
1780
1781 if (ipg_data->current_ipg <= MAX_IPG)
1782 tmp_ipg = ipg_data->current_ipg;
1783 else{
1784 tmp_ipg = ipg_data->ipg;
1785 ipg_data->ipg_state = SSTATE;
1786 }
6aa20a22
JG		 1787 writew((u32)tmp_ipg, mmio + IPG);
1788 writew((u32)(tmp_ipg - IFS1_DELTA), mmio + IFS1);
1da177e4
LT		 1789 }
1790 mod_timer(&lp->ipg_data.ipg_timer, jiffies + IPG_CONVERGE_JIFFIES);
1791 return;
1792
1793}
1794
1795static void __devinit amd8111e_probe_ext_phy(struct net_device* dev)
1796{
1797 struct amd8111e_priv *lp = netdev_priv(dev);
1798 int i;
1799
1800 for (i = 0x1e; i >= 0; i--) {
1801 u32 id1, id2;
1802
1803 if (amd8111e_read_phy(lp, i, MII_PHYSID1, &id1))
1804 continue;
1805 if (amd8111e_read_phy(lp, i, MII_PHYSID2, &id2))
1806 continue;
1807 lp->ext_phy_id = (id1 << 16) | id2;
1808 lp->ext_phy_addr = i;
1809 return;
1810 }
1811 lp->ext_phy_id = 0;
1812 lp->ext_phy_addr = 1;
1813}
1814
887e53d2
SH		 1815static const struct net_device_ops amd8111e_netdev_ops = {
1816 .ndo_open = amd8111e_open,
1817 .ndo_stop = amd8111e_close,
1818 .ndo_start_xmit = amd8111e_start_xmit,
1819 .ndo_tx_timeout = amd8111e_tx_timeout,
1820 .ndo_get_stats = amd8111e_get_stats,
1821 .ndo_set_multicast_list = amd8111e_set_multicast_list,
1822 .ndo_validate_addr = eth_validate_addr,
1823 .ndo_set_mac_address = amd8111e_set_mac_address,
1824 .ndo_do_ioctl = amd8111e_ioctl,
1825 .ndo_change_mtu = amd8111e_change_mtu,
1826#if AMD8111E_VLAN_TAG_USED
1827 .ndo_vlan_rx_register = amd8111e_vlan_rx_register,
1828#endif
1829#ifdef CONFIG_NET_POLL_CONTROLLER
1830 .ndo_poll_controller = amd8111e_poll,
1831#endif
1832};
1833
1da177e4
LT		 1834static int __devinit amd8111e_probe_one(struct pci_dev *pdev,
1835 const struct pci_device_id *ent)
1836{
1837 int err,i,pm_cap;
1838 unsigned long reg_addr,reg_len;
1839 struct amd8111e_priv* lp;
1840 struct net_device* dev;
1841
1842 err = pci_enable_device(pdev);
1843 if(err){
2450022a 1844 printk(KERN_ERR "amd8111e: Cannot enable new PCI device, "
1da177e4
LT		 1845 "exiting.\n");
1846 return err;
1847 }
1848
1849 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)){
2450022a 1850 printk(KERN_ERR "amd8111e: Cannot find PCI base address, "
1da177e4
LT		 1851 "exiting.\n");
1852 err = -ENODEV;
1853 goto err_disable_pdev;
1854 }
1855
1856 err = pci_request_regions(pdev, MODULE_NAME);
1857 if(err){
1858 printk(KERN_ERR "amd8111e: Cannot obtain PCI resources, "
1859 "exiting.\n");
1860 goto err_disable_pdev;
1861 }
1862
1863 pci_set_master(pdev);
1864
1865 /* Find power-management capability. */
1866 if((pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM))==0){
1867 printk(KERN_ERR "amd8111e: No Power Management capability, "
1868 "exiting.\n");
1869 goto err_free_reg;
1870 }
1871
1872 /* Initialize DMA */
284901a9 1873 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) < 0) {
1da177e4
LT		 1874 printk(KERN_ERR "amd8111e: DMA not supported,"
1875 "exiting.\n");
cac8c81a
TK		 1876 goto err_free_reg;
1877 }
6aa20a22 1878
1da177e4
LT		 1879 reg_addr = pci_resource_start(pdev, 0);
1880 reg_len = pci_resource_len(pdev, 0);
1881
1882 dev = alloc_etherdev(sizeof(struct amd8111e_priv));
1883 if (!dev) {
1884 printk(KERN_ERR "amd8111e: Etherdev alloc failed, exiting.\n");
1885 err = -ENOMEM;
1886 goto err_free_reg;
1887 }
1888
1da177e4
LT		 1889 SET_NETDEV_DEV(dev, &pdev->dev);
1890
1891#if AMD8111E_VLAN_TAG_USED
1892 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX ;
6aa20a22
JG		 1893#endif
1894
1da177e4
LT		 1895 lp = netdev_priv(dev);
1896 lp->pci_dev = pdev;
1897 lp->amd8111e_net_dev = dev;
1898 lp->pm_cap = pm_cap;
1899
1900 spin_lock_init(&lp->lock);
1901
1902 lp->mmio = ioremap(reg_addr, reg_len);
ee41a82f 1903 if (!lp->mmio) {
1da177e4
LT		 1904 printk(KERN_ERR "amd8111e: Cannot map device registers, "
1905 "exiting\n");
1906 err = -ENOMEM;
1907 goto err_free_dev;
1908 }
6aa20a22 1909
1da177e4
LT		 1910 /* Initializing MAC address */
1911 for(i = 0; i < ETH_ADDR_LEN; i++)
0795af57 1912 dev->dev_addr[i] = readb(lp->mmio + PADR + i);
6aa20a22 1913
1da177e4
LT		 1914 /* Setting user defined parametrs */
1915 lp->ext_phy_option = speed_duplex[card_idx];
1916 if(coalesce[card_idx])
6aa20a22 1917 lp->options |= OPTION_INTR_COAL_ENABLE;
1da177e4 1918 if(dynamic_ipg[card_idx++])
6aa20a22 1919 lp->options |= OPTION_DYN_IPG_ENABLE;
1da177e4 1920
887e53d2 1921
1da177e4 1922 /* Initialize driver entry points */
887e53d2 1923 dev->netdev_ops = &amd8111e_netdev_ops;
1da177e4
LT		 1924 SET_ETHTOOL_OPS(dev, &ops);
1925 dev->irq =pdev->irq;
6aa20a22 1926 dev->watchdog_timeo = AMD8111E_TX_TIMEOUT;
bea3348e 1927 netif_napi_add(dev, &lp->napi, amd8111e_rx_poll, 32);
1da177e4
LT		 1928
1929#if AMD8111E_VLAN_TAG_USED
1930 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6aa20a22 1931#endif
1da177e4
LT		 1932 /* Probe the external PHY */
1933 amd8111e_probe_ext_phy(dev);
1934
1935 /* setting mii default values */
1936 lp->mii_if.dev = dev;
1937 lp->mii_if.mdio_read = amd8111e_mdio_read;
1938 lp->mii_if.mdio_write = amd8111e_mdio_write;
1939 lp->mii_if.phy_id = lp->ext_phy_addr;
1940
1941 /* Set receive buffer length and set jumbo option*/
1942 amd8111e_set_rx_buff_len(dev);
1943
1944
1945 err = register_netdev(dev);
1946 if (err) {
1947 printk(KERN_ERR "amd8111e: Cannot register net device, "
1948 "exiting.\n");
1949 goto err_iounmap;
1950 }
1951
1952 pci_set_drvdata(pdev, dev);
6aa20a22 1953
1da177e4 1954 /* Initialize software ipg timer */
6aa20a22 1955 if(lp->options & OPTION_DYN_IPG_ENABLE){
1da177e4
LT		 1956 init_timer(&lp->ipg_data.ipg_timer);
1957 lp->ipg_data.ipg_timer.data = (unsigned long) dev;
1958 lp->ipg_data.ipg_timer.function = (void *)&amd8111e_config_ipg;
6aa20a22 1959 lp->ipg_data.ipg_timer.expires = jiffies +
1da177e4
LT		 1960 IPG_CONVERGE_JIFFIES;
1961 lp->ipg_data.ipg = DEFAULT_IPG;
1962 lp->ipg_data.ipg_state = CSTATE;
1963 };
1964
1965 /* display driver and device information */
1966
1967 chip_version = (readl(lp->mmio + CHIPID) & 0xf0000000)>>28;
0795af57
JP		 1968 printk(KERN_INFO "%s: AMD-8111e Driver Version: %s\n",
1969 dev->name,MODULE_VERS);
e174961c
JB		 1970 printk(KERN_INFO "%s: [ Rev %x ] PCI 10/100BaseT Ethernet %pM\n",
1971 dev->name, chip_version, dev->dev_addr);
1da177e4
LT		 1972 if (lp->ext_phy_id)
1973 printk(KERN_INFO "%s: Found MII PHY ID 0x%08x at address 0x%02x\n",
1974 dev->name, lp->ext_phy_id, lp->ext_phy_addr);
1975 else
1976 printk(KERN_INFO "%s: Couldn't detect MII PHY, assuming address 0x01\n",
1977 dev->name);
1978 return 0;
1979err_iounmap:
1980 iounmap(lp->mmio);
1981
1982err_free_dev:
1983 free_netdev(dev);
1984
1985err_free_reg:
1986 pci_release_regions(pdev);
1987
1988err_disable_pdev:
1989 pci_disable_device(pdev);
1990 pci_set_drvdata(pdev, NULL);
1991 return err;
1992
1993}
1994
1995static struct pci_driver amd8111e_driver = {
1996 .name = MODULE_NAME,
1997 .id_table = amd8111e_pci_tbl,
1998 .probe = amd8111e_probe_one,
1999 .remove = __devexit_p(amd8111e_remove_one),
2000 .suspend = amd8111e_suspend,
2001 .resume = amd8111e_resume
2002};
2003
2004static int __init amd8111e_init(void)
2005{
29917620 2006 return pci_register_driver(&amd8111e_driver);
1da177e4
LT		 2007}
2008
2009static void __exit amd8111e_cleanup(void)
2010{
2011 pci_unregister_driver(&amd8111e_driver);
2012}
2013
2014module_init(amd8111e_init);
2015module_exit(amd8111e_cleanup);
kernel source for telekom puls (alcatel/mediatek)