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drivers/net: Kill now superfluous ->last_rx stores.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / acenic.c
CommitLineData
1da177e4
LT		 1/*
2 * acenic.c: Linux driver for the Alteon AceNIC Gigabit Ethernet card
3 * and other Tigon based cards.
4 *
5 * Copyright 1998-2002 by Jes Sorensen, <jes@trained-monkey.org>.
6 *
7 * Thanks to Alteon and 3Com for providing hardware and documentation
8 * enabling me to write this driver.
9 *
10 * A mailing list for discussing the use of this driver has been
11 * setup, please subscribe to the lists if you have any questions
12 * about the driver. Send mail to linux-acenic-help@sunsite.auc.dk to
13 * see how to subscribe.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * Additional credits:
21 * Pete Wyckoff <wyckoff@ca.sandia.gov>: Initial Linux/Alpha and trace
22 * dump support. The trace dump support has not been
23 * integrated yet however.
24 * Troy Benjegerdes: Big Endian (PPC) patches.
25 * Nate Stahl: Better out of memory handling and stats support.
26 * Aman Singla: Nasty race between interrupt handler and tx code dealing
27 * with 'testing the tx_ret_csm and setting tx_full'
28 * David S. Miller <davem@redhat.com>: conversion to new PCI dma mapping
29 * infrastructure and Sparc support
30 * Pierrick Pinasseau (CERN): For lending me an Ultra 5 to test the
31 * driver under Linux/Sparc64
32 * Matt Domsch <Matt_Domsch@dell.com>: Detect Alteon 1000baseT cards
33 * ETHTOOL_GDRVINFO support
34 * Chip Salzenberg <chip@valinux.com>: Fix race condition between tx
35 * handler and close() cleanup.
36 * Ken Aaker <kdaaker@rchland.vnet.ibm.com>: Correct check for whether
37 * memory mapped IO is enabled to
38 * make the driver work on RS/6000.
39 * Takayoshi Kouchi <kouchi@hpc.bs1.fc.nec.co.jp>: Identifying problem
40 * where the driver would disable
41 * bus master mode if it had to disable
42 * write and invalidate.
43 * Stephen Hack <stephen_hack@hp.com>: Fixed ace_set_mac_addr for little
44 * endian systems.
45 * Val Henson <vhenson@esscom.com>: Reset Jumbo skb producer and
46 * rx producer index when
47 * flushing the Jumbo ring.
48 * Hans Grobler <grobh@sun.ac.za>: Memory leak fixes in the
49 * driver init path.
50 * Grant Grundler <grundler@cup.hp.com>: PCI write posting fixes.
51 */
52
1da177e4
LT		 53#include <linux/module.h>
54#include <linux/moduleparam.h>
1da177e4
LT		 55#include <linux/types.h>
56#include <linux/errno.h>
57#include <linux/ioport.h>
58#include <linux/pci.h>
1e7f0bd8 59#include <linux/dma-mapping.h>
1da177e4
LT		 60#include <linux/kernel.h>
61#include <linux/netdevice.h>
62#include <linux/etherdevice.h>
63#include <linux/skbuff.h>
64#include <linux/init.h>
65#include <linux/delay.h>
66#include <linux/mm.h>
67#include <linux/highmem.h>
68#include <linux/sockios.h>
69
70#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
71#include <linux/if_vlan.h>
72#endif
73
74#ifdef SIOCETHTOOL
75#include <linux/ethtool.h>
76#endif
77
78#include <net/sock.h>
79#include <net/ip.h>
80
81#include <asm/system.h>
82#include <asm/io.h>
83#include <asm/irq.h>
84#include <asm/byteorder.h>
85#include <asm/uaccess.h>
86
87
88#define DRV_NAME "acenic"
89
90#undef INDEX_DEBUG
91
92#ifdef CONFIG_ACENIC_OMIT_TIGON_I
93#define ACE_IS_TIGON_I(ap) 0
94#define ACE_TX_RING_ENTRIES(ap) MAX_TX_RING_ENTRIES
95#else
96#define ACE_IS_TIGON_I(ap) (ap->version == 1)
97#define ACE_TX_RING_ENTRIES(ap) ap->tx_ring_entries
98#endif
99
100#ifndef PCI_VENDOR_ID_ALTEON
6aa20a22 101#define PCI_VENDOR_ID_ALTEON 0x12ae
1da177e4
LT		 102#endif
103#ifndef PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE
104#define PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE 0x0001
105#define PCI_DEVICE_ID_ALTEON_ACENIC_COPPER 0x0002
106#endif
107#ifndef PCI_DEVICE_ID_3COM_3C985
108#define PCI_DEVICE_ID_3COM_3C985 0x0001
109#endif
110#ifndef PCI_VENDOR_ID_NETGEAR
111#define PCI_VENDOR_ID_NETGEAR 0x1385
112#define PCI_DEVICE_ID_NETGEAR_GA620 0x620a
113#endif
114#ifndef PCI_DEVICE_ID_NETGEAR_GA620T
115#define PCI_DEVICE_ID_NETGEAR_GA620T 0x630a
116#endif
117
118
119/*
120 * Farallon used the DEC vendor ID by mistake and they seem not
121 * to care - stinky!
122 */
123#ifndef PCI_DEVICE_ID_FARALLON_PN9000SX
124#define PCI_DEVICE_ID_FARALLON_PN9000SX 0x1a
125#endif
126#ifndef PCI_DEVICE_ID_FARALLON_PN9100T
127#define PCI_DEVICE_ID_FARALLON_PN9100T 0xfa
128#endif
129#ifndef PCI_VENDOR_ID_SGI
130#define PCI_VENDOR_ID_SGI 0x10a9
131#endif
132#ifndef PCI_DEVICE_ID_SGI_ACENIC
133#define PCI_DEVICE_ID_SGI_ACENIC 0x0009
134#endif
135
136static struct pci_device_id acenic_pci_tbl[] = {
137 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE,
138 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
139 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_COPPER,
140 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
141 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C985,
142 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
143 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620,
144 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
145 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620T,
146 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
147 /*
148 * Farallon used the DEC vendor ID on their cards incorrectly,
149 * then later Alteon's ID.
150 */
151 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_FARALLON_PN9000SX,
152 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
153 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_FARALLON_PN9100T,
154 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
155 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_ACENIC,
156 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
157 { }
158};
159MODULE_DEVICE_TABLE(pci, acenic_pci_tbl);
160
1da177e4 161#define ace_sync_irq(irq) synchronize_irq(irq)
1da177e4
LT		 162
163#ifndef offset_in_page
164#define offset_in_page(ptr) ((unsigned long)(ptr) & ~PAGE_MASK)
165#endif
166
167#define ACE_MAX_MOD_PARMS 8
168#define BOARD_IDX_STATIC 0
169#define BOARD_IDX_OVERFLOW -1
170
171#if (defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)) && \
172 defined(NETIF_F_HW_VLAN_RX)
173#define ACENIC_DO_VLAN 1
174#define ACE_RCB_VLAN_FLAG RCB_FLG_VLAN_ASSIST
175#else
176#define ACENIC_DO_VLAN 0
177#define ACE_RCB_VLAN_FLAG 0
178#endif
179
180#include "acenic.h"
181
182/*
183 * These must be defined before the firmware is included.
184 */
185#define MAX_TEXT_LEN 96*1024
186#define MAX_RODATA_LEN 8*1024
187#define MAX_DATA_LEN 2*1024
188
189#include "acenic_firmware.h"
190
191#ifndef tigon2FwReleaseLocal
192#define tigon2FwReleaseLocal 0
193#endif
194
195/*
196 * This driver currently supports Tigon I and Tigon II based cards
197 * including the Alteon AceNIC, the 3Com 3C985[B] and NetGear
198 * GA620. The driver should also work on the SGI, DEC and Farallon
199 * versions of the card, however I have not been able to test that
200 * myself.
201 *
202 * This card is really neat, it supports receive hardware checksumming
203 * and jumbo frames (up to 9000 bytes) and does a lot of work in the
204 * firmware. Also the programming interface is quite neat, except for
205 * the parts dealing with the i2c eeprom on the card ;-)
206 *
207 * Using jumbo frames:
208 *
209 * To enable jumbo frames, simply specify an mtu between 1500 and 9000
210 * bytes to ifconfig. Jumbo frames can be enabled or disabled at any time
211 * by running `ifconfig eth<X> mtu <MTU>' with <X> being the Ethernet
212 * interface number and <MTU> being the MTU value.
213 *
214 * Module parameters:
215 *
216 * When compiled as a loadable module, the driver allows for a number
217 * of module parameters to be specified. The driver supports the
218 * following module parameters:
219 *
220 * trace=<val> - Firmware trace level. This requires special traced
221 * firmware to replace the firmware supplied with
222 * the driver - for debugging purposes only.
223 *
224 * link=<val> - Link state. Normally you want to use the default link
225 * parameters set by the driver. This can be used to
226 * override these in case your switch doesn't negotiate
227 * the link properly. Valid values are:
228 * 0x0001 - Force half duplex link.
229 * 0x0002 - Do not negotiate line speed with the other end.
230 * 0x0010 - 10Mbit/sec link.
231 * 0x0020 - 100Mbit/sec link.
232 * 0x0040 - 1000Mbit/sec link.
233 * 0x0100 - Do not negotiate flow control.
234 * 0x0200 - Enable RX flow control Y
235 * 0x0400 - Enable TX flow control Y (Tigon II NICs only).
236 * Default value is 0x0270, ie. enable link+flow
237 * control negotiation. Negotiating the highest
238 * possible link speed with RX flow control enabled.
239 *
240 * When disabling link speed negotiation, only one link
241 * speed is allowed to be specified!
242 *
243 * tx_coal_tick=<val> - number of coalescing clock ticks (us) allowed
244 * to wait for more packets to arive before
245 * interrupting the host, from the time the first
246 * packet arrives.
247 *
248 * rx_coal_tick=<val> - number of coalescing clock ticks (us) allowed
249 * to wait for more packets to arive in the transmit ring,
250 * before interrupting the host, after transmitting the
251 * first packet in the ring.
252 *
253 * max_tx_desc=<val> - maximum number of transmit descriptors
254 * (packets) transmitted before interrupting the host.
255 *
256 * max_rx_desc=<val> - maximum number of receive descriptors
257 * (packets) received before interrupting the host.
258 *
259 * tx_ratio=<val> - 7 bit value (0 - 63) specifying the split in 64th
260 * increments of the NIC's on board memory to be used for
261 * transmit and receive buffers. For the 1MB NIC app. 800KB
262 * is available, on the 1/2MB NIC app. 300KB is available.
263 * 68KB will always be available as a minimum for both
264 * directions. The default value is a 50/50 split.
265 * dis_pci_mem_inval=<val> - disable PCI memory write and invalidate
266 * operations, default (1) is to always disable this as
267 * that is what Alteon does on NT. I have not been able
268 * to measure any real performance differences with
269 * this on my systems. Set <val>=0 if you want to
270 * enable these operations.
271 *
272 * If you use more than one NIC, specify the parameters for the
273 * individual NICs with a comma, ie. trace=0,0x00001fff,0 you want to
274 * run tracing on NIC #2 but not on NIC #1 and #3.
275 *
276 * TODO:
277 *
278 * - Proper multicast support.
279 * - NIC dump support.
280 * - More tuning parameters.
281 *
282 * The mini ring is not used under Linux and I am not sure it makes sense
283 * to actually use it.
284 *
285 * New interrupt handler strategy:
286 *
287 * The old interrupt handler worked using the traditional method of
288 * replacing an skbuff with a new one when a packet arrives. However
289 * the rx rings do not need to contain a static number of buffer
290 * descriptors, thus it makes sense to move the memory allocation out
291 * of the main interrupt handler and do it in a bottom half handler
292 * and only allocate new buffers when the number of buffers in the
293 * ring is below a certain threshold. In order to avoid starving the
294 * NIC under heavy load it is however necessary to force allocation
295 * when hitting a minimum threshold. The strategy for alloction is as
296 * follows:
297 *
298 * RX_LOW_BUF_THRES - allocate buffers in the bottom half
299 * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
300 * the buffers in the interrupt handler
301 * RX_RING_THRES - maximum number of buffers in the rx ring
302 * RX_MINI_THRES - maximum number of buffers in the mini ring
303 * RX_JUMBO_THRES - maximum number of buffers in the jumbo ring
304 *
305 * One advantagous side effect of this allocation approach is that the
306 * entire rx processing can be done without holding any spin lock
307 * since the rx rings and registers are totally independent of the tx
308 * ring and its registers. This of course includes the kmalloc's of
309 * new skb's. Thus start_xmit can run in parallel with rx processing
310 * and the memory allocation on SMP systems.
311 *
312 * Note that running the skb reallocation in a bottom half opens up
313 * another can of races which needs to be handled properly. In
314 * particular it can happen that the interrupt handler tries to run
315 * the reallocation while the bottom half is either running on another
316 * CPU or was interrupted on the same CPU. To get around this the
317 * driver uses bitops to prevent the reallocation routines from being
318 * reentered.
319 *
320 * TX handling can also be done without holding any spin lock, wheee
321 * this is fun! since tx_ret_csm is only written to by the interrupt
322 * handler. The case to be aware of is when shutting down the device
323 * and cleaning up where it is necessary to make sure that
324 * start_xmit() is not running while this is happening. Well DaveM
325 * informs me that this case is already protected against ... bye bye
326 * Mr. Spin Lock, it was nice to know you.
327 *
328 * TX interrupts are now partly disabled so the NIC will only generate
329 * TX interrupts for the number of coal ticks, not for the number of
330 * TX packets in the queue. This should reduce the number of TX only,
331 * ie. when no RX processing is done, interrupts seen.
332 */
333
334/*
335 * Threshold values for RX buffer allocation - the low water marks for
336 * when to start refilling the rings are set to 75% of the ring
337 * sizes. It seems to make sense to refill the rings entirely from the
338 * intrrupt handler once it gets below the panic threshold, that way
339 * we don't risk that the refilling is moved to another CPU when the
340 * one running the interrupt handler just got the slab code hot in its
341 * cache.
342 */
343#define RX_RING_SIZE 72
344#define RX_MINI_SIZE 64
345#define RX_JUMBO_SIZE 48
346
347#define RX_PANIC_STD_THRES 16
348#define RX_PANIC_STD_REFILL (3*RX_PANIC_STD_THRES)/2
349#define RX_LOW_STD_THRES (3*RX_RING_SIZE)/4
350#define RX_PANIC_MINI_THRES 12
351#define RX_PANIC_MINI_REFILL (3*RX_PANIC_MINI_THRES)/2
352#define RX_LOW_MINI_THRES (3*RX_MINI_SIZE)/4
353#define RX_PANIC_JUMBO_THRES 6
354#define RX_PANIC_JUMBO_REFILL (3*RX_PANIC_JUMBO_THRES)/2
355#define RX_LOW_JUMBO_THRES (3*RX_JUMBO_SIZE)/4
356
357
358/*
359 * Size of the mini ring entries, basically these just should be big
360 * enough to take TCP ACKs
361 */
362#define ACE_MINI_SIZE 100
363
364#define ACE_MINI_BUFSIZE ACE_MINI_SIZE
365#define ACE_STD_BUFSIZE (ACE_STD_MTU + ETH_HLEN + 4)
366#define ACE_JUMBO_BUFSIZE (ACE_JUMBO_MTU + ETH_HLEN + 4)
367
368/*
369 * There seems to be a magic difference in the effect between 995 and 996
370 * but little difference between 900 and 995 ... no idea why.
371 *
372 * There is now a default set of tuning parameters which is set, depending
373 * on whether or not the user enables Jumbo frames. It's assumed that if
374 * Jumbo frames are enabled, the user wants optimal tuning for that case.
375 */
376#define DEF_TX_COAL 400 /* 996 */
377#define DEF_TX_MAX_DESC 60 /* was 40 */
378#define DEF_RX_COAL 120 /* 1000 */
379#define DEF_RX_MAX_DESC 25
380#define DEF_TX_RATIO 21 /* 24 */
381
382#define DEF_JUMBO_TX_COAL 20
383#define DEF_JUMBO_TX_MAX_DESC 60
384#define DEF_JUMBO_RX_COAL 30
385#define DEF_JUMBO_RX_MAX_DESC 6
386#define DEF_JUMBO_TX_RATIO 21
387
388#if tigon2FwReleaseLocal < 20001118
389/*
390 * Standard firmware and early modifications duplicate
391 * IRQ load without this flag (coal timer is never reset).
392 * Note that with this flag tx_coal should be less than
393 * time to xmit full tx ring.
394 * 400usec is not so bad for tx ring size of 128.
395 */
396#define TX_COAL_INTS_ONLY 1 /* worth it */
397#else
398/*
399 * With modified firmware, this is not necessary, but still useful.
400 */
401#define TX_COAL_INTS_ONLY 1
402#endif
403
404#define DEF_TRACE 0
405#define DEF_STAT (2 * TICKS_PER_SEC)
406
407
ddfce6bb 408static int link_state[ACE_MAX_MOD_PARMS];
1da177e4
LT		 409static int trace[ACE_MAX_MOD_PARMS];
410static int tx_coal_tick[ACE_MAX_MOD_PARMS];
411static int rx_coal_tick[ACE_MAX_MOD_PARMS];
412static int max_tx_desc[ACE_MAX_MOD_PARMS];
413static int max_rx_desc[ACE_MAX_MOD_PARMS];
414static int tx_ratio[ACE_MAX_MOD_PARMS];
415static int dis_pci_mem_inval[ACE_MAX_MOD_PARMS] = {1, 1, 1, 1, 1, 1, 1, 1};
416
417MODULE_AUTHOR("Jes Sorensen <jes@trained-monkey.org>");
418MODULE_LICENSE("GPL");
419MODULE_DESCRIPTION("AceNIC/3C985/GA620 Gigabit Ethernet driver");
420
ddfce6bb 421module_param_array_named(link, link_state, int, NULL, 0);
1da177e4
LT		 422module_param_array(trace, int, NULL, 0);
423module_param_array(tx_coal_tick, int, NULL, 0);
424module_param_array(max_tx_desc, int, NULL, 0);
425module_param_array(rx_coal_tick, int, NULL, 0);
426module_param_array(max_rx_desc, int, NULL, 0);
427module_param_array(tx_ratio, int, NULL, 0);
428MODULE_PARM_DESC(link, "AceNIC/3C985/NetGear link state");
429MODULE_PARM_DESC(trace, "AceNIC/3C985/NetGear firmware trace level");
430MODULE_PARM_DESC(tx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first tx descriptor arrives");
431MODULE_PARM_DESC(max_tx_desc, "AceNIC/3C985/GA620 max number of transmit descriptors to wait");
432MODULE_PARM_DESC(rx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first rx descriptor arrives");
433MODULE_PARM_DESC(max_rx_desc, "AceNIC/3C985/GA620 max number of receive descriptors to wait");
434MODULE_PARM_DESC(tx_ratio, "AceNIC/3C985/GA620 ratio of NIC memory used for TX/RX descriptors (range 0-63)");
435
436
6aa20a22 437static char version[] __devinitdata =
1da177e4
LT		 438 "acenic.c: v0.92 08/05/2002 Jes Sorensen, linux-acenic@SunSITE.dk\n"
439 " http://home.cern.ch/~jes/gige/acenic.html\n";
440
441static int ace_get_settings(struct net_device *, struct ethtool_cmd *);
442static int ace_set_settings(struct net_device *, struct ethtool_cmd *);
443static void ace_get_drvinfo(struct net_device *, struct ethtool_drvinfo *);
444
7282d491 445static const struct ethtool_ops ace_ethtool_ops = {
1da177e4
LT		 446 .get_settings = ace_get_settings,
447 .set_settings = ace_set_settings,
448 .get_drvinfo = ace_get_drvinfo,
449};
450
451static void ace_watchdog(struct net_device *dev);
452
453static int __devinit acenic_probe_one(struct pci_dev *pdev,
454 const struct pci_device_id *id)
455{
456 struct net_device *dev;
457 struct ace_private *ap;
458 static int boards_found;
459
460 dev = alloc_etherdev(sizeof(struct ace_private));
461 if (dev == NULL) {
462 printk(KERN_ERR "acenic: Unable to allocate "
463 "net_device structure!\n");
464 return -ENOMEM;
465 }
466
1da177e4
LT		 467 SET_NETDEV_DEV(dev, &pdev->dev);
468
469 ap = dev->priv;
470 ap->pdev = pdev;
471 ap->name = pci_name(pdev);
472
473 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
474#if ACENIC_DO_VLAN
475 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
476 dev->vlan_rx_register = ace_vlan_rx_register;
1da177e4 477#endif
25805dcf
SH		 478
479 dev->tx_timeout = &ace_watchdog;
480 dev->watchdog_timeo = 5*HZ;
1da177e4
LT		 481
482 dev->open = &ace_open;
483 dev->stop = &ace_close;
484 dev->hard_start_xmit = &ace_start_xmit;
485 dev->get_stats = &ace_get_stats;
486 dev->set_multicast_list = &ace_set_multicast_list;
487 SET_ETHTOOL_OPS(dev, &ace_ethtool_ops);
488 dev->set_mac_address = &ace_set_mac_addr;
489 dev->change_mtu = &ace_change_mtu;
490
491 /* we only display this string ONCE */
492 if (!boards_found)
493 printk(version);
494
495 if (pci_enable_device(pdev))
496 goto fail_free_netdev;
497
498 /*
499 * Enable master mode before we start playing with the
500 * pci_command word since pci_set_master() will modify
501 * it.
502 */
503 pci_set_master(pdev);
504
505 pci_read_config_word(pdev, PCI_COMMAND, &ap->pci_command);
506
6aa20a22 507 /* OpenFirmware on Mac's does not set this - DOH.. */
1da177e4
LT		 508 if (!(ap->pci_command & PCI_COMMAND_MEMORY)) {
509 printk(KERN_INFO "%s: Enabling PCI Memory Mapped "
510 "access - was not enabled by BIOS/Firmware\n",
511 ap->name);
512 ap->pci_command = ap->pci_command | PCI_COMMAND_MEMORY;
513 pci_write_config_word(ap->pdev, PCI_COMMAND,
514 ap->pci_command);
515 wmb();
516 }
517
518 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &ap->pci_latency);
519 if (ap->pci_latency <= 0x40) {
520 ap->pci_latency = 0x40;
521 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, ap->pci_latency);
522 }
523
524 /*
525 * Remap the regs into kernel space - this is abuse of
526 * dev->base_addr since it was means for I/O port
527 * addresses but who gives a damn.
528 */
529 dev->base_addr = pci_resource_start(pdev, 0);
530 ap->regs = ioremap(dev->base_addr, 0x4000);
531 if (!ap->regs) {
532 printk(KERN_ERR "%s: Unable to map I/O register, "
533 "AceNIC %i will be disabled.\n",
534 ap->name, boards_found);
535 goto fail_free_netdev;
536 }
537
538 switch(pdev->vendor) {
539 case PCI_VENDOR_ID_ALTEON:
540 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9100T) {
541 printk(KERN_INFO "%s: Farallon PN9100-T ",
542 ap->name);
543 } else {
544 printk(KERN_INFO "%s: Alteon AceNIC ",
545 ap->name);
546 }
547 break;
548 case PCI_VENDOR_ID_3COM:
549 printk(KERN_INFO "%s: 3Com 3C985 ", ap->name);
550 break;
551 case PCI_VENDOR_ID_NETGEAR:
552 printk(KERN_INFO "%s: NetGear GA620 ", ap->name);
553 break;
554 case PCI_VENDOR_ID_DEC:
555 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9000SX) {
556 printk(KERN_INFO "%s: Farallon PN9000-SX ",
557 ap->name);
558 break;
559 }
560 case PCI_VENDOR_ID_SGI:
561 printk(KERN_INFO "%s: SGI AceNIC ", ap->name);
562 break;
563 default:
564 printk(KERN_INFO "%s: Unknown AceNIC ", ap->name);
565 break;
566 }
567
568 printk("Gigabit Ethernet at 0x%08lx, ", dev->base_addr);
c6387a48 569 printk("irq %d\n", pdev->irq);
1da177e4
LT		 570
571#ifdef CONFIG_ACENIC_OMIT_TIGON_I
572 if ((readl(&ap->regs->HostCtrl) >> 28) == 4) {
573 printk(KERN_ERR "%s: Driver compiled without Tigon I"
574 " support - NIC disabled\n", dev->name);
575 goto fail_uninit;
576 }
577#endif
578
579 if (ace_allocate_descriptors(dev))
580 goto fail_free_netdev;
581
582#ifdef MODULE
583 if (boards_found >= ACE_MAX_MOD_PARMS)
584 ap->board_idx = BOARD_IDX_OVERFLOW;
585 else
586 ap->board_idx = boards_found;
587#else
588 ap->board_idx = BOARD_IDX_STATIC;
589#endif
590
591 if (ace_init(dev))
592 goto fail_free_netdev;
593
594 if (register_netdev(dev)) {
595 printk(KERN_ERR "acenic: device registration failed\n");
596 goto fail_uninit;
597 }
598 ap->name = dev->name;
599
600 if (ap->pci_using_dac)
601 dev->features |= NETIF_F_HIGHDMA;
602
603 pci_set_drvdata(pdev, dev);
604
605 boards_found++;
606 return 0;
607
608 fail_uninit:
609 ace_init_cleanup(dev);
610 fail_free_netdev:
611 free_netdev(dev);
612 return -ENODEV;
613}
614
615static void __devexit acenic_remove_one(struct pci_dev *pdev)
616{
617 struct net_device *dev = pci_get_drvdata(pdev);
618 struct ace_private *ap = netdev_priv(dev);
619 struct ace_regs __iomem *regs = ap->regs;
620 short i;
621
622 unregister_netdev(dev);
623
624 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
625 if (ap->version >= 2)
626 writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl);
6aa20a22 627
1da177e4
LT		 628 /*
629 * This clears any pending interrupts
630 */
631 writel(1, &regs->Mb0Lo);
632 readl(&regs->CpuCtrl); /* flush */
633
634 /*
635 * Make sure no other CPUs are processing interrupts
636 * on the card before the buffers are being released.
637 * Otherwise one might experience some `interesting'
638 * effects.
639 *
640 * Then release the RX buffers - jumbo buffers were
641 * already released in ace_close().
642 */
643 ace_sync_irq(dev->irq);
644
645 for (i = 0; i < RX_STD_RING_ENTRIES; i++) {
646 struct sk_buff *skb = ap->skb->rx_std_skbuff[i].skb;
647
648 if (skb) {
649 struct ring_info *ringp;
650 dma_addr_t mapping;
651
652 ringp = &ap->skb->rx_std_skbuff[i];
653 mapping = pci_unmap_addr(ringp, mapping);
654 pci_unmap_page(ap->pdev, mapping,
655 ACE_STD_BUFSIZE,
656 PCI_DMA_FROMDEVICE);
657
658 ap->rx_std_ring[i].size = 0;
659 ap->skb->rx_std_skbuff[i].skb = NULL;
660 dev_kfree_skb(skb);
661 }
662 }
663
664 if (ap->version >= 2) {
665 for (i = 0; i < RX_MINI_RING_ENTRIES; i++) {
666 struct sk_buff *skb = ap->skb->rx_mini_skbuff[i].skb;
667
668 if (skb) {
669 struct ring_info *ringp;
670 dma_addr_t mapping;
671
672 ringp = &ap->skb->rx_mini_skbuff[i];
673 mapping = pci_unmap_addr(ringp,mapping);
674 pci_unmap_page(ap->pdev, mapping,
675 ACE_MINI_BUFSIZE,
676 PCI_DMA_FROMDEVICE);
677
678 ap->rx_mini_ring[i].size = 0;
679 ap->skb->rx_mini_skbuff[i].skb = NULL;
680 dev_kfree_skb(skb);
681 }
682 }
683 }
684
685 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
686 struct sk_buff *skb = ap->skb->rx_jumbo_skbuff[i].skb;
687 if (skb) {
688 struct ring_info *ringp;
689 dma_addr_t mapping;
690
691 ringp = &ap->skb->rx_jumbo_skbuff[i];
692 mapping = pci_unmap_addr(ringp, mapping);
693 pci_unmap_page(ap->pdev, mapping,
694 ACE_JUMBO_BUFSIZE,
695 PCI_DMA_FROMDEVICE);
696
697 ap->rx_jumbo_ring[i].size = 0;
698 ap->skb->rx_jumbo_skbuff[i].skb = NULL;
699 dev_kfree_skb(skb);
700 }
701 }
702
703 ace_init_cleanup(dev);
704 free_netdev(dev);
705}
706
707static struct pci_driver acenic_pci_driver = {
708 .name = "acenic",
709 .id_table = acenic_pci_tbl,
710 .probe = acenic_probe_one,
711 .remove = __devexit_p(acenic_remove_one),
712};
713
714static int __init acenic_init(void)
715{
29917620 716 return pci_register_driver(&acenic_pci_driver);
1da177e4
LT		 717}
718
719static void __exit acenic_exit(void)
720{
721 pci_unregister_driver(&acenic_pci_driver);
722}
723
724module_init(acenic_init);
725module_exit(acenic_exit);
726
727static void ace_free_descriptors(struct net_device *dev)
728{
729 struct ace_private *ap = netdev_priv(dev);
730 int size;
731
732 if (ap->rx_std_ring != NULL) {
733 size = (sizeof(struct rx_desc) *
734 (RX_STD_RING_ENTRIES +
735 RX_JUMBO_RING_ENTRIES +
736 RX_MINI_RING_ENTRIES +
737 RX_RETURN_RING_ENTRIES));
738 pci_free_consistent(ap->pdev, size, ap->rx_std_ring,
739 ap->rx_ring_base_dma);
740 ap->rx_std_ring = NULL;
741 ap->rx_jumbo_ring = NULL;
742 ap->rx_mini_ring = NULL;
743 ap->rx_return_ring = NULL;
744 }
745 if (ap->evt_ring != NULL) {
746 size = (sizeof(struct event) * EVT_RING_ENTRIES);
747 pci_free_consistent(ap->pdev, size, ap->evt_ring,
748 ap->evt_ring_dma);
749 ap->evt_ring = NULL;
750 }
751 if (ap->tx_ring != NULL && !ACE_IS_TIGON_I(ap)) {
752 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
753 pci_free_consistent(ap->pdev, size, ap->tx_ring,
754 ap->tx_ring_dma);
755 }
756 ap->tx_ring = NULL;
757
758 if (ap->evt_prd != NULL) {
759 pci_free_consistent(ap->pdev, sizeof(u32),
760 (void *)ap->evt_prd, ap->evt_prd_dma);
761 ap->evt_prd = NULL;
762 }
763 if (ap->rx_ret_prd != NULL) {
764 pci_free_consistent(ap->pdev, sizeof(u32),
765 (void *)ap->rx_ret_prd,
766 ap->rx_ret_prd_dma);
767 ap->rx_ret_prd = NULL;
768 }
769 if (ap->tx_csm != NULL) {
770 pci_free_consistent(ap->pdev, sizeof(u32),
771 (void *)ap->tx_csm, ap->tx_csm_dma);
772 ap->tx_csm = NULL;
773 }
774}
775
776
777static int ace_allocate_descriptors(struct net_device *dev)
778{
779 struct ace_private *ap = netdev_priv(dev);
780 int size;
781
782 size = (sizeof(struct rx_desc) *
783 (RX_STD_RING_ENTRIES +
784 RX_JUMBO_RING_ENTRIES +
785 RX_MINI_RING_ENTRIES +
786 RX_RETURN_RING_ENTRIES));
787
788 ap->rx_std_ring = pci_alloc_consistent(ap->pdev, size,
789 &ap->rx_ring_base_dma);
790 if (ap->rx_std_ring == NULL)
791 goto fail;
792
793 ap->rx_jumbo_ring = ap->rx_std_ring + RX_STD_RING_ENTRIES;
794 ap->rx_mini_ring = ap->rx_jumbo_ring + RX_JUMBO_RING_ENTRIES;
795 ap->rx_return_ring = ap->rx_mini_ring + RX_MINI_RING_ENTRIES;
796
797 size = (sizeof(struct event) * EVT_RING_ENTRIES);
798
799 ap->evt_ring = pci_alloc_consistent(ap->pdev, size, &ap->evt_ring_dma);
800
801 if (ap->evt_ring == NULL)
802 goto fail;
803
804 /*
805 * Only allocate a host TX ring for the Tigon II, the Tigon I
806 * has to use PCI registers for this ;-(
807 */
808 if (!ACE_IS_TIGON_I(ap)) {
809 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
810
811 ap->tx_ring = pci_alloc_consistent(ap->pdev, size,
812 &ap->tx_ring_dma);
813
814 if (ap->tx_ring == NULL)
815 goto fail;
816 }
817
818 ap->evt_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
819 &ap->evt_prd_dma);
820 if (ap->evt_prd == NULL)
821 goto fail;
822
823 ap->rx_ret_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
824 &ap->rx_ret_prd_dma);
825 if (ap->rx_ret_prd == NULL)
826 goto fail;
827
828 ap->tx_csm = pci_alloc_consistent(ap->pdev, sizeof(u32),
829 &ap->tx_csm_dma);
830 if (ap->tx_csm == NULL)
831 goto fail;
832
833 return 0;
834
835fail:
836 /* Clean up. */
837 ace_init_cleanup(dev);
838 return 1;
839}
840
841
842/*
843 * Generic cleanup handling data allocated during init. Used when the
844 * module is unloaded or if an error occurs during initialization
845 */
846static void ace_init_cleanup(struct net_device *dev)
847{
848 struct ace_private *ap;
849
850 ap = netdev_priv(dev);
851
852 ace_free_descriptors(dev);
853
854 if (ap->info)
855 pci_free_consistent(ap->pdev, sizeof(struct ace_info),
856 ap->info, ap->info_dma);
b4558ea9
JJ		 857 kfree(ap->skb);
858 kfree(ap->trace_buf);
1da177e4
LT		 859
860 if (dev->irq)
861 free_irq(dev->irq, dev);
862
863 iounmap(ap->regs);
864}
865
866
867/*
868 * Commands are considered to be slow.
869 */
870static inline void ace_issue_cmd(struct ace_regs __iomem *regs, struct cmd *cmd)
871{
872 u32 idx;
873
874 idx = readl(&regs->CmdPrd);
875
876 writel(*(u32 *)(cmd), &regs->CmdRng[idx]);
877 idx = (idx + 1) % CMD_RING_ENTRIES;
878
879 writel(idx, &regs->CmdPrd);
880}
881
882
883static int __devinit ace_init(struct net_device *dev)
884{
885 struct ace_private *ap;
886 struct ace_regs __iomem *regs;
887 struct ace_info *info = NULL;
888 struct pci_dev *pdev;
889 unsigned long myjif;
890 u64 tmp_ptr;
891 u32 tig_ver, mac1, mac2, tmp, pci_state;
892 int board_idx, ecode = 0;
893 short i;
894 unsigned char cache_size;
895
896 ap = netdev_priv(dev);
897 regs = ap->regs;
898
899 board_idx = ap->board_idx;
900
901 /*
902 * aman@sgi.com - its useful to do a NIC reset here to
903 * address the `Firmware not running' problem subsequent
904 * to any crashes involving the NIC
905 */
906 writel(HW_RESET | (HW_RESET << 24), &regs->HostCtrl);
907 readl(&regs->HostCtrl); /* PCI write posting */
908 udelay(5);
909
910 /*
911 * Don't access any other registers before this point!
912 */
913#ifdef __BIG_ENDIAN
914 /*
915 * This will most likely need BYTE_SWAP once we switch
916 * to using __raw_writel()
917 */
918 writel((WORD_SWAP | CLR_INT | ((WORD_SWAP | CLR_INT) << 24)),
919 &regs->HostCtrl);
920#else
921 writel((CLR_INT | WORD_SWAP | ((CLR_INT | WORD_SWAP) << 24)),
922 &regs->HostCtrl);
923#endif
924 readl(&regs->HostCtrl); /* PCI write posting */
925
926 /*
927 * Stop the NIC CPU and clear pending interrupts
928 */
929 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
930 readl(&regs->CpuCtrl); /* PCI write posting */
931 writel(0, &regs->Mb0Lo);
932
933 tig_ver = readl(&regs->HostCtrl) >> 28;
934
935 switch(tig_ver){
936#ifndef CONFIG_ACENIC_OMIT_TIGON_I
937 case 4:
938 case 5:
939 printk(KERN_INFO " Tigon I (Rev. %i), Firmware: %i.%i.%i, ",
940 tig_ver, tigonFwReleaseMajor, tigonFwReleaseMinor,
941 tigonFwReleaseFix);
942 writel(0, &regs->LocalCtrl);
943 ap->version = 1;
944 ap->tx_ring_entries = TIGON_I_TX_RING_ENTRIES;
945 break;
946#endif
947 case 6:
948 printk(KERN_INFO " Tigon II (Rev. %i), Firmware: %i.%i.%i, ",
949 tig_ver, tigon2FwReleaseMajor, tigon2FwReleaseMinor,
950 tigon2FwReleaseFix);
951 writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl);
952 readl(&regs->CpuBCtrl); /* PCI write posting */
953 /*
954 * The SRAM bank size does _not_ indicate the amount
955 * of memory on the card, it controls the _bank_ size!
956 * Ie. a 1MB AceNIC will have two banks of 512KB.
957 */
958 writel(SRAM_BANK_512K, &regs->LocalCtrl);
959 writel(SYNC_SRAM_TIMING, &regs->MiscCfg);
960 ap->version = 2;
961 ap->tx_ring_entries = MAX_TX_RING_ENTRIES;
962 break;
963 default:
964 printk(KERN_WARNING " Unsupported Tigon version detected "
965 "(%i)\n", tig_ver);
966 ecode = -ENODEV;
967 goto init_error;
968 }
969
970 /*
971 * ModeStat _must_ be set after the SRAM settings as this change
972 * seems to corrupt the ModeStat and possible other registers.
973 * The SRAM settings survive resets and setting it to the same
974 * value a second time works as well. This is what caused the
975 * `Firmware not running' problem on the Tigon II.
976 */
977#ifdef __BIG_ENDIAN
978 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL | ACE_BYTE_SWAP_BD |
979 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, &regs->ModeStat);
980#else
981 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL |
982 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, &regs->ModeStat);
983#endif
984 readl(&regs->ModeStat); /* PCI write posting */
985
986 mac1 = 0;
987 for(i = 0; i < 4; i++) {
ddfce6bb 988 int t;
6f9d4722 989
1da177e4 990 mac1 = mac1 << 8;
ddfce6bb
SH		 991 t = read_eeprom_byte(dev, 0x8c+i);
992 if (t < 0) {
1da177e4
LT		 993 ecode = -EIO;
994 goto init_error;
995 } else
ddfce6bb 996 mac1 |= (t & 0xff);
1da177e4
LT		 997 }
998 mac2 = 0;
999 for(i = 4; i < 8; i++) {
ddfce6bb 1000 int t;
6f9d4722 1001
1da177e4 1002 mac2 = mac2 << 8;
ddfce6bb
SH		 1003 t = read_eeprom_byte(dev, 0x8c+i);
1004 if (t < 0) {
1da177e4
LT		 1005 ecode = -EIO;
1006 goto init_error;
1007 } else
ddfce6bb 1008 mac2 |= (t & 0xff);
1da177e4
LT		 1009 }
1010
1011 writel(mac1, &regs->MacAddrHi);
1012 writel(mac2, &regs->MacAddrLo);
1013
1da177e4
LT		 1014 dev->dev_addr[0] = (mac1 >> 8) & 0xff;
1015 dev->dev_addr[1] = mac1 & 0xff;
1016 dev->dev_addr[2] = (mac2 >> 24) & 0xff;
1017 dev->dev_addr[3] = (mac2 >> 16) & 0xff;
1018 dev->dev_addr[4] = (mac2 >> 8) & 0xff;
1019 dev->dev_addr[5] = mac2 & 0xff;
1020
e174961c 1021 printk("MAC: %pM\n", dev->dev_addr);
0795af57 1022
1da177e4
LT		 1023 /*
1024 * Looks like this is necessary to deal with on all architectures,
1025 * even this %$#%$# N440BX Intel based thing doesn't get it right.
1026 * Ie. having two NICs in the machine, one will have the cache
1027 * line set at boot time, the other will not.
1028 */
1029 pdev = ap->pdev;
1030 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_size);
1031 cache_size <<= 2;
1032 if (cache_size != SMP_CACHE_BYTES) {
1033 printk(KERN_INFO " PCI cache line size set incorrectly "
1034 "(%i bytes) by BIOS/FW, ", cache_size);
1035 if (cache_size > SMP_CACHE_BYTES)
1036 printk("expecting %i\n", SMP_CACHE_BYTES);
1037 else {
1038 printk("correcting to %i\n", SMP_CACHE_BYTES);
1039 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
1040 SMP_CACHE_BYTES >> 2);
1041 }
1042 }
1043
1044 pci_state = readl(&regs->PciState);
1045 printk(KERN_INFO " PCI bus width: %i bits, speed: %iMHz, "
1046 "latency: %i clks\n",
1047 (pci_state & PCI_32BIT) ? 32 : 64,
6aa20a22 1048 (pci_state & PCI_66MHZ) ? 66 : 33,
1da177e4
LT		 1049 ap->pci_latency);
1050
1051 /*
1052 * Set the max DMA transfer size. Seems that for most systems
1053 * the performance is better when no MAX parameter is
1054 * set. However for systems enabling PCI write and invalidate,
1055 * DMA writes must be set to the L1 cache line size to get
1056 * optimal performance.
1057 *
1058 * The default is now to turn the PCI write and invalidate off
1059 * - that is what Alteon does for NT.
1060 */
1061 tmp = READ_CMD_MEM | WRITE_CMD_MEM;
1062 if (ap->version >= 2) {
1063 tmp |= (MEM_READ_MULTIPLE | (pci_state & PCI_66MHZ));
1064 /*
1065 * Tuning parameters only supported for 8 cards
1066 */
1067 if (board_idx == BOARD_IDX_OVERFLOW ||
1068 dis_pci_mem_inval[board_idx]) {
1069 if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1070 ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1071 pci_write_config_word(pdev, PCI_COMMAND,
1072 ap->pci_command);
1073 printk(KERN_INFO " Disabling PCI memory "
1074 "write and invalidate\n");
1075 }
1076 } else if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1077 printk(KERN_INFO " PCI memory write & invalidate "
1078 "enabled by BIOS, enabling counter measures\n");
1079
1080 switch(SMP_CACHE_BYTES) {
1081 case 16:
1082 tmp |= DMA_WRITE_MAX_16;
1083 break;
1084 case 32:
1085 tmp |= DMA_WRITE_MAX_32;
1086 break;
1087 case 64:
1088 tmp |= DMA_WRITE_MAX_64;
1089 break;
1090 case 128:
1091 tmp |= DMA_WRITE_MAX_128;
1092 break;
1093 default:
1094 printk(KERN_INFO " Cache line size %i not "
1095 "supported, PCI write and invalidate "
1096 "disabled\n", SMP_CACHE_BYTES);
1097 ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1098 pci_write_config_word(pdev, PCI_COMMAND,
1099 ap->pci_command);
1100 }
1101 }
1102 }
1103
1104#ifdef __sparc__
1105 /*
1106 * On this platform, we know what the best dma settings
1107 * are. We use 64-byte maximum bursts, because if we
1108 * burst larger than the cache line size (or even cross
1109 * a 64byte boundary in a single burst) the UltraSparc
1110 * PCI controller will disconnect at 64-byte multiples.
1111 *
1112 * Read-multiple will be properly enabled above, and when
1113 * set will give the PCI controller proper hints about
1114 * prefetching.
1115 */
1116 tmp &= ~DMA_READ_WRITE_MASK;
1117 tmp |= DMA_READ_MAX_64;
1118 tmp |= DMA_WRITE_MAX_64;
1119#endif
1120#ifdef __alpha__
1121 tmp &= ~DMA_READ_WRITE_MASK;
1122 tmp |= DMA_READ_MAX_128;
1123 /*
1124 * All the docs say MUST NOT. Well, I did.
1125 * Nothing terrible happens, if we load wrong size.
1126 * Bit w&i still works better!
1127 */
1128 tmp |= DMA_WRITE_MAX_128;
1129#endif
1130 writel(tmp, &regs->PciState);
1131
1132#if 0
1133 /*
1134 * The Host PCI bus controller driver has to set FBB.
1135 * If all devices on that PCI bus support FBB, then the controller
1136 * can enable FBB support in the Host PCI Bus controller (or on
1137 * the PCI-PCI bridge if that applies).
1138 * -ggg
1139 */
1140 /*
1141 * I have received reports from people having problems when this
1142 * bit is enabled.
1143 */
1144 if (!(ap->pci_command & PCI_COMMAND_FAST_BACK)) {
1145 printk(KERN_INFO " Enabling PCI Fast Back to Back\n");
1146 ap->pci_command |= PCI_COMMAND_FAST_BACK;
1147 pci_write_config_word(pdev, PCI_COMMAND, ap->pci_command);
1148 }
1149#endif
6aa20a22 1150
1da177e4
LT		 1151 /*
1152 * Configure DMA attributes.
1153 */
1e7f0bd8 1154 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1da177e4 1155 ap->pci_using_dac = 1;
1e7f0bd8 1156 } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1da177e4
LT		 1157 ap->pci_using_dac = 0;
1158 } else {
1159 ecode = -ENODEV;
1160 goto init_error;
1161 }
1162
1163 /*
1164 * Initialize the generic info block and the command+event rings
1165 * and the control blocks for the transmit and receive rings
1166 * as they need to be setup once and for all.
1167 */
1168 if (!(info = pci_alloc_consistent(ap->pdev, sizeof(struct ace_info),
1169 &ap->info_dma))) {
1170 ecode = -EAGAIN;
1171 goto init_error;
1172 }
1173 ap->info = info;
1174
1175 /*
1176 * Get the memory for the skb rings.
1177 */
1178 if (!(ap->skb = kmalloc(sizeof(struct ace_skb), GFP_KERNEL))) {
1179 ecode = -EAGAIN;
1180 goto init_error;
1181 }
1182
1fb9df5d 1183 ecode = request_irq(pdev->irq, ace_interrupt, IRQF_SHARED,
1da177e4
LT		 1184 DRV_NAME, dev);
1185 if (ecode) {
1186 printk(KERN_WARNING "%s: Requested IRQ %d is busy\n",
1187 DRV_NAME, pdev->irq);
1188 goto init_error;
1189 } else
1190 dev->irq = pdev->irq;
1191
1192#ifdef INDEX_DEBUG
1193 spin_lock_init(&ap->debug_lock);
1194 ap->last_tx = ACE_TX_RING_ENTRIES(ap) - 1;
1195 ap->last_std_rx = 0;
1196 ap->last_mini_rx = 0;
1197#endif
1198
1199 memset(ap->info, 0, sizeof(struct ace_info));
1200 memset(ap->skb, 0, sizeof(struct ace_skb));
1201
1202 ace_load_firmware(dev);
1203 ap->fw_running = 0;
1204
1205 tmp_ptr = ap->info_dma;
1206 writel(tmp_ptr >> 32, &regs->InfoPtrHi);
1207 writel(tmp_ptr & 0xffffffff, &regs->InfoPtrLo);
1208
1209 memset(ap->evt_ring, 0, EVT_RING_ENTRIES * sizeof(struct event));
1210
1211 set_aceaddr(&info->evt_ctrl.rngptr, ap->evt_ring_dma);
1212 info->evt_ctrl.flags = 0;
1213
1214 *(ap->evt_prd) = 0;
1215 wmb();
1216 set_aceaddr(&info->evt_prd_ptr, ap->evt_prd_dma);
1217 writel(0, &regs->EvtCsm);
1218
1219 set_aceaddr(&info->cmd_ctrl.rngptr, 0x100);
1220 info->cmd_ctrl.flags = 0;
1221 info->cmd_ctrl.max_len = 0;
1222
1223 for (i = 0; i < CMD_RING_ENTRIES; i++)
1224 writel(0, &regs->CmdRng[i]);
1225
1226 writel(0, &regs->CmdPrd);
1227 writel(0, &regs->CmdCsm);
1228
1229 tmp_ptr = ap->info_dma;
1230 tmp_ptr += (unsigned long) &(((struct ace_info *)0)->s.stats);
1231 set_aceaddr(&info->stats2_ptr, (dma_addr_t) tmp_ptr);
1232
1233 set_aceaddr(&info->rx_std_ctrl.rngptr, ap->rx_ring_base_dma);
1234 info->rx_std_ctrl.max_len = ACE_STD_BUFSIZE;
1235 info->rx_std_ctrl.flags =
1236 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1237
1238 memset(ap->rx_std_ring, 0,
1239 RX_STD_RING_ENTRIES * sizeof(struct rx_desc));
1240
1241 for (i = 0; i < RX_STD_RING_ENTRIES; i++)
1242 ap->rx_std_ring[i].flags = BD_FLG_TCP_UDP_SUM;
1243
1244 ap->rx_std_skbprd = 0;
1245 atomic_set(&ap->cur_rx_bufs, 0);
1246
1247 set_aceaddr(&info->rx_jumbo_ctrl.rngptr,
1248 (ap->rx_ring_base_dma +
1249 (sizeof(struct rx_desc) * RX_STD_RING_ENTRIES)));
1250 info->rx_jumbo_ctrl.max_len = 0;
1251 info->rx_jumbo_ctrl.flags =
1252 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1253
1254 memset(ap->rx_jumbo_ring, 0,
1255 RX_JUMBO_RING_ENTRIES * sizeof(struct rx_desc));
1256
1257 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++)
1258 ap->rx_jumbo_ring[i].flags = BD_FLG_TCP_UDP_SUM | BD_FLG_JUMBO;
1259
1260 ap->rx_jumbo_skbprd = 0;
1261 atomic_set(&ap->cur_jumbo_bufs, 0);
1262
1263 memset(ap->rx_mini_ring, 0,
1264 RX_MINI_RING_ENTRIES * sizeof(struct rx_desc));
1265
1266 if (ap->version >= 2) {
1267 set_aceaddr(&info->rx_mini_ctrl.rngptr,
1268 (ap->rx_ring_base_dma +
1269 (sizeof(struct rx_desc) *
1270 (RX_STD_RING_ENTRIES +
1271 RX_JUMBO_RING_ENTRIES))));
1272 info->rx_mini_ctrl.max_len = ACE_MINI_SIZE;
6aa20a22 1273 info->rx_mini_ctrl.flags =
1da177e4
LT		 1274 RCB_FLG_TCP_UDP_SUM|RCB_FLG_NO_PSEUDO_HDR|ACE_RCB_VLAN_FLAG;
1275
1276 for (i = 0; i < RX_MINI_RING_ENTRIES; i++)
1277 ap->rx_mini_ring[i].flags =
1278 BD_FLG_TCP_UDP_SUM | BD_FLG_MINI;
1279 } else {
1280 set_aceaddr(&info->rx_mini_ctrl.rngptr, 0);
1281 info->rx_mini_ctrl.flags = RCB_FLG_RNG_DISABLE;
1282 info->rx_mini_ctrl.max_len = 0;
1283 }
1284
1285 ap->rx_mini_skbprd = 0;
1286 atomic_set(&ap->cur_mini_bufs, 0);
1287
1288 set_aceaddr(&info->rx_return_ctrl.rngptr,
1289 (ap->rx_ring_base_dma +
1290 (sizeof(struct rx_desc) *
1291 (RX_STD_RING_ENTRIES +
1292 RX_JUMBO_RING_ENTRIES +
1293 RX_MINI_RING_ENTRIES))));
1294 info->rx_return_ctrl.flags = 0;
1295 info->rx_return_ctrl.max_len = RX_RETURN_RING_ENTRIES;
1296
1297 memset(ap->rx_return_ring, 0,
1298 RX_RETURN_RING_ENTRIES * sizeof(struct rx_desc));
1299
1300 set_aceaddr(&info->rx_ret_prd_ptr, ap->rx_ret_prd_dma);
1301 *(ap->rx_ret_prd) = 0;
1302
1303 writel(TX_RING_BASE, &regs->WinBase);
1304
1305 if (ACE_IS_TIGON_I(ap)) {
ddfce6bb 1306 ap->tx_ring = (__force struct tx_desc *) regs->Window;
6aa20a22 1307 for (i = 0; i < (TIGON_I_TX_RING_ENTRIES
1da177e4 1308 * sizeof(struct tx_desc)) / sizeof(u32); i++)
ddfce6bb 1309 writel(0, (__force void __iomem *)ap->tx_ring + i * 4);
1da177e4
LT		 1310
1311 set_aceaddr(&info->tx_ctrl.rngptr, TX_RING_BASE);
1312 } else {
1313 memset(ap->tx_ring, 0,
1314 MAX_TX_RING_ENTRIES * sizeof(struct tx_desc));
1315
1316 set_aceaddr(&info->tx_ctrl.rngptr, ap->tx_ring_dma);
1317 }
1318
1319 info->tx_ctrl.max_len = ACE_TX_RING_ENTRIES(ap);
1320 tmp = RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1321
1322 /*
1323 * The Tigon I does not like having the TX ring in host memory ;-(
1324 */
1325 if (!ACE_IS_TIGON_I(ap))
1326 tmp |= RCB_FLG_TX_HOST_RING;
1327#if TX_COAL_INTS_ONLY
1328 tmp |= RCB_FLG_COAL_INT_ONLY;
1329#endif
1330 info->tx_ctrl.flags = tmp;
1331
1332 set_aceaddr(&info->tx_csm_ptr, ap->tx_csm_dma);
1333
1334 /*
1335 * Potential item for tuning parameter
1336 */
1337#if 0 /* NO */
1338 writel(DMA_THRESH_16W, &regs->DmaReadCfg);
1339 writel(DMA_THRESH_16W, &regs->DmaWriteCfg);
1340#else
1341 writel(DMA_THRESH_8W, &regs->DmaReadCfg);
1342 writel(DMA_THRESH_8W, &regs->DmaWriteCfg);
1343#endif
1344
1345 writel(0, &regs->MaskInt);
1346 writel(1, &regs->IfIdx);
1347#if 0
1348 /*
1349 * McKinley boxes do not like us fiddling with AssistState
1350 * this early
1351 */
1352 writel(1, &regs->AssistState);
1353#endif
1354
1355 writel(DEF_STAT, &regs->TuneStatTicks);
1356 writel(DEF_TRACE, &regs->TuneTrace);
1357
1358 ace_set_rxtx_parms(dev, 0);
1359
1360 if (board_idx == BOARD_IDX_OVERFLOW) {
1361 printk(KERN_WARNING "%s: more than %i NICs detected, "
1362 "ignoring module parameters!\n",
1363 ap->name, ACE_MAX_MOD_PARMS);
1364 } else if (board_idx >= 0) {
1365 if (tx_coal_tick[board_idx])
1366 writel(tx_coal_tick[board_idx],
1367 &regs->TuneTxCoalTicks);
1368 if (max_tx_desc[board_idx])
1369 writel(max_tx_desc[board_idx], &regs->TuneMaxTxDesc);
1370
1371 if (rx_coal_tick[board_idx])
1372 writel(rx_coal_tick[board_idx],
1373 &regs->TuneRxCoalTicks);
1374 if (max_rx_desc[board_idx])
1375 writel(max_rx_desc[board_idx], &regs->TuneMaxRxDesc);
1376
1377 if (trace[board_idx])
1378 writel(trace[board_idx], &regs->TuneTrace);
1379
1380 if ((tx_ratio[board_idx] > 0) && (tx_ratio[board_idx] < 64))
1381 writel(tx_ratio[board_idx], &regs->TxBufRat);
1382 }
1383
1384 /*
1385 * Default link parameters
1386 */
1387 tmp = LNK_ENABLE | LNK_FULL_DUPLEX | LNK_1000MB | LNK_100MB |
1388 LNK_10MB | LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL | LNK_NEGOTIATE;
1389 if(ap->version >= 2)
1390 tmp |= LNK_TX_FLOW_CTL_Y;
1391
1392 /*
1393 * Override link default parameters
1394 */
ddfce6bb
SH		 1395 if ((board_idx >= 0) && link_state[board_idx]) {
1396 int option = link_state[board_idx];
1da177e4
LT		 1397
1398 tmp = LNK_ENABLE;
1399
1400 if (option & 0x01) {
1401 printk(KERN_INFO "%s: Setting half duplex link\n",
1402 ap->name);
1403 tmp &= ~LNK_FULL_DUPLEX;
1404 }
1405 if (option & 0x02)
1406 tmp &= ~LNK_NEGOTIATE;
1407 if (option & 0x10)
1408 tmp |= LNK_10MB;
1409 if (option & 0x20)
1410 tmp |= LNK_100MB;
1411 if (option & 0x40)
1412 tmp |= LNK_1000MB;
1413 if ((option & 0x70) == 0) {
1414 printk(KERN_WARNING "%s: No media speed specified, "
1415 "forcing auto negotiation\n", ap->name);
1416 tmp |= LNK_NEGOTIATE | LNK_1000MB |
1417 LNK_100MB | LNK_10MB;
1418 }
1419 if ((option & 0x100) == 0)
1420 tmp |= LNK_NEG_FCTL;
1421 else
1422 printk(KERN_INFO "%s: Disabling flow control "
1423 "negotiation\n", ap->name);
1424 if (option & 0x200)
1425 tmp |= LNK_RX_FLOW_CTL_Y;
1426 if ((option & 0x400) && (ap->version >= 2)) {
1427 printk(KERN_INFO "%s: Enabling TX flow control\n",
1428 ap->name);
1429 tmp |= LNK_TX_FLOW_CTL_Y;
1430 }
1431 }
1432
1433 ap->link = tmp;
1434 writel(tmp, &regs->TuneLink);
1435 if (ap->version >= 2)
1436 writel(tmp, &regs->TuneFastLink);
1437
1438 if (ACE_IS_TIGON_I(ap))
1439 writel(tigonFwStartAddr, &regs->Pc);
1440 if (ap->version == 2)
1441 writel(tigon2FwStartAddr, &regs->Pc);
1442
1443 writel(0, &regs->Mb0Lo);
1444
1445 /*
1446 * Set tx_csm before we start receiving interrupts, otherwise
1447 * the interrupt handler might think it is supposed to process
1448 * tx ints before we are up and running, which may cause a null
1449 * pointer access in the int handler.
1450 */
1451 ap->cur_rx = 0;
1452 ap->tx_prd = *(ap->tx_csm) = ap->tx_ret_csm = 0;
1453
1454 wmb();
1455 ace_set_txprd(regs, ap, 0);
1456 writel(0, &regs->RxRetCsm);
1457
1da177e4
LT		 1458 /*
1459 * Enable DMA engine now.
1460 * If we do this sooner, Mckinley box pukes.
1461 * I assume it's because Tigon II DMA engine wants to check
1462 * *something* even before the CPU is started.
1463 */
1464 writel(1, &regs->AssistState); /* enable DMA */
1465
1466 /*
1467 * Start the NIC CPU
1468 */
1469 writel(readl(&regs->CpuCtrl) & ~(CPU_HALT|CPU_TRACE), &regs->CpuCtrl);
1470 readl(&regs->CpuCtrl);
1471
1472 /*
1473 * Wait for the firmware to spin up - max 3 seconds.
1474 */
1475 myjif = jiffies + 3 * HZ;
1476 while (time_before(jiffies, myjif) && !ap->fw_running)
1477 cpu_relax();
1478
1479 if (!ap->fw_running) {
1480 printk(KERN_ERR "%s: Firmware NOT running!\n", ap->name);
1481
1482 ace_dump_trace(ap);
1483 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
1484 readl(&regs->CpuCtrl);
1485
1486 /* aman@sgi.com - account for badly behaving firmware/NIC:
1487 * - have observed that the NIC may continue to generate
1488 * interrupts for some reason; attempt to stop it - halt
1489 * second CPU for Tigon II cards, and also clear Mb0
1490 * - if we're a module, we'll fail to load if this was
1491 * the only GbE card in the system => if the kernel does
1492 * see an interrupt from the NIC, code to handle it is
1493 * gone and OOps! - so free_irq also
1494 */
1495 if (ap->version >= 2)
1496 writel(readl(&regs->CpuBCtrl) | CPU_HALT,
1497 &regs->CpuBCtrl);
1498 writel(0, &regs->Mb0Lo);
1499 readl(&regs->Mb0Lo);
1500
1501 ecode = -EBUSY;
1502 goto init_error;
1503 }
1504
1505 /*
1506 * We load the ring here as there seem to be no way to tell the
1507 * firmware to wipe the ring without re-initializing it.
1508 */
1509 if (!test_and_set_bit(0, &ap->std_refill_busy))
1510 ace_load_std_rx_ring(ap, RX_RING_SIZE);
1511 else
1512 printk(KERN_ERR "%s: Someone is busy refilling the RX ring\n",
1513 ap->name);
1514 if (ap->version >= 2) {
1515 if (!test_and_set_bit(0, &ap->mini_refill_busy))
1516 ace_load_mini_rx_ring(ap, RX_MINI_SIZE);
1517 else
1518 printk(KERN_ERR "%s: Someone is busy refilling "
1519 "the RX mini ring\n", ap->name);
1520 }
1521 return 0;
1522
1523 init_error:
1524 ace_init_cleanup(dev);
1525 return ecode;
1526}
1527
1528
1529static void ace_set_rxtx_parms(struct net_device *dev, int jumbo)
1530{
1531 struct ace_private *ap = netdev_priv(dev);
1532 struct ace_regs __iomem *regs = ap->regs;
1533 int board_idx = ap->board_idx;
1534
1535 if (board_idx >= 0) {
1536 if (!jumbo) {
1537 if (!tx_coal_tick[board_idx])
1538 writel(DEF_TX_COAL, &regs->TuneTxCoalTicks);
1539 if (!max_tx_desc[board_idx])
1540 writel(DEF_TX_MAX_DESC, &regs->TuneMaxTxDesc);
1541 if (!rx_coal_tick[board_idx])
1542 writel(DEF_RX_COAL, &regs->TuneRxCoalTicks);
1543 if (!max_rx_desc[board_idx])
1544 writel(DEF_RX_MAX_DESC, &regs->TuneMaxRxDesc);
1545 if (!tx_ratio[board_idx])
1546 writel(DEF_TX_RATIO, &regs->TxBufRat);
1547 } else {
1548 if (!tx_coal_tick[board_idx])
1549 writel(DEF_JUMBO_TX_COAL,
1550 &regs->TuneTxCoalTicks);
1551 if (!max_tx_desc[board_idx])
1552 writel(DEF_JUMBO_TX_MAX_DESC,
1553 &regs->TuneMaxTxDesc);
1554 if (!rx_coal_tick[board_idx])
1555 writel(DEF_JUMBO_RX_COAL,
1556 &regs->TuneRxCoalTicks);
1557 if (!max_rx_desc[board_idx])
1558 writel(DEF_JUMBO_RX_MAX_DESC,
1559 &regs->TuneMaxRxDesc);
1560 if (!tx_ratio[board_idx])
1561 writel(DEF_JUMBO_TX_RATIO, &regs->TxBufRat);
1562 }
1563 }
1564}
1565
1566
1567static void ace_watchdog(struct net_device *data)
1568{
1569 struct net_device *dev = data;
1570 struct ace_private *ap = netdev_priv(dev);
1571 struct ace_regs __iomem *regs = ap->regs;
1572
1573 /*
1574 * We haven't received a stats update event for more than 2.5
1575 * seconds and there is data in the transmit queue, thus we
1576 * asume the card is stuck.
1577 */
1578 if (*ap->tx_csm != ap->tx_ret_csm) {
1579 printk(KERN_WARNING "%s: Transmitter is stuck, %08x\n",
1580 dev->name, (unsigned int)readl(&regs->HostCtrl));
1581 /* This can happen due to ieee flow control. */
1582 } else {
1583 printk(KERN_DEBUG "%s: BUG... transmitter died. Kicking it.\n",
1584 dev->name);
1585#if 0
1586 netif_wake_queue(dev);
1587#endif
1588 }
1589}
1590
1591
1592static void ace_tasklet(unsigned long dev)
1593{
1594 struct ace_private *ap = netdev_priv((struct net_device *)dev);
1595 int cur_size;
1596
1597 cur_size = atomic_read(&ap->cur_rx_bufs);
1598 if ((cur_size < RX_LOW_STD_THRES) &&
1599 !test_and_set_bit(0, &ap->std_refill_busy)) {
1600#ifdef DEBUG
1601 printk("refilling buffers (current %i)\n", cur_size);
1602#endif
1603 ace_load_std_rx_ring(ap, RX_RING_SIZE - cur_size);
1604 }
1605
1606 if (ap->version >= 2) {
1607 cur_size = atomic_read(&ap->cur_mini_bufs);
1608 if ((cur_size < RX_LOW_MINI_THRES) &&
1609 !test_and_set_bit(0, &ap->mini_refill_busy)) {
1610#ifdef DEBUG
1611 printk("refilling mini buffers (current %i)\n",
1612 cur_size);
1613#endif
1614 ace_load_mini_rx_ring(ap, RX_MINI_SIZE - cur_size);
1615 }
1616 }
1617
1618 cur_size = atomic_read(&ap->cur_jumbo_bufs);
1619 if (ap->jumbo && (cur_size < RX_LOW_JUMBO_THRES) &&
1620 !test_and_set_bit(0, &ap->jumbo_refill_busy)) {
1621#ifdef DEBUG
1622 printk("refilling jumbo buffers (current %i)\n", cur_size);
1623#endif
1624 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE - cur_size);
1625 }
1626 ap->tasklet_pending = 0;
1627}
1628
1629
1630/*
1631 * Copy the contents of the NIC's trace buffer to kernel memory.
1632 */
1633static void ace_dump_trace(struct ace_private *ap)
1634{
1635#if 0
1636 if (!ap->trace_buf)
1637 if (!(ap->trace_buf = kmalloc(ACE_TRACE_SIZE, GFP_KERNEL)))
1638 return;
1639#endif
1640}
1641
1642
1643/*
1644 * Load the standard rx ring.
1645 *
1646 * Loading rings is safe without holding the spin lock since this is
1647 * done only before the device is enabled, thus no interrupts are
1648 * generated and by the interrupt handler/tasklet handler.
1649 */
1650static void ace_load_std_rx_ring(struct ace_private *ap, int nr_bufs)
1651{
1652 struct ace_regs __iomem *regs = ap->regs;
1653 short i, idx;
6aa20a22 1654
1da177e4
LT		 1655
1656 prefetchw(&ap->cur_rx_bufs);
1657
1658 idx = ap->rx_std_skbprd;
1659
1660 for (i = 0; i < nr_bufs; i++) {
1661 struct sk_buff *skb;
1662 struct rx_desc *rd;
1663 dma_addr_t mapping;
1664
1665 skb = alloc_skb(ACE_STD_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
1666 if (!skb)
1667 break;
1668
1669 skb_reserve(skb, NET_IP_ALIGN);
1670 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1671 offset_in_page(skb->data),
1672 ACE_STD_BUFSIZE,
1673 PCI_DMA_FROMDEVICE);
1674 ap->skb->rx_std_skbuff[idx].skb = skb;
1675 pci_unmap_addr_set(&ap->skb->rx_std_skbuff[idx],
1676 mapping, mapping);
1677
1678 rd = &ap->rx_std_ring[idx];
1679 set_aceaddr(&rd->addr, mapping);
1680 rd->size = ACE_STD_BUFSIZE;
1681 rd->idx = idx;
1682 idx = (idx + 1) % RX_STD_RING_ENTRIES;
1683 }
1684
1685 if (!i)
1686 goto error_out;
1687
1688 atomic_add(i, &ap->cur_rx_bufs);
1689 ap->rx_std_skbprd = idx;
1690
1691 if (ACE_IS_TIGON_I(ap)) {
1692 struct cmd cmd;
1693 cmd.evt = C_SET_RX_PRD_IDX;
1694 cmd.code = 0;
1695 cmd.idx = ap->rx_std_skbprd;
1696 ace_issue_cmd(regs, &cmd);
1697 } else {
1698 writel(idx, &regs->RxStdPrd);
1699 wmb();
1700 }
1701
1702 out:
1703 clear_bit(0, &ap->std_refill_busy);
1704 return;
1705
1706 error_out:
1707 printk(KERN_INFO "Out of memory when allocating "
1708 "standard receive buffers\n");
1709 goto out;
1710}
1711
1712
1713static void ace_load_mini_rx_ring(struct ace_private *ap, int nr_bufs)
1714{
1715 struct ace_regs __iomem *regs = ap->regs;
1716 short i, idx;
1717
1718 prefetchw(&ap->cur_mini_bufs);
1719
1720 idx = ap->rx_mini_skbprd;
1721 for (i = 0; i < nr_bufs; i++) {
1722 struct sk_buff *skb;
1723 struct rx_desc *rd;
1724 dma_addr_t mapping;
1725
1726 skb = alloc_skb(ACE_MINI_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
1727 if (!skb)
1728 break;
1729
1730 skb_reserve(skb, NET_IP_ALIGN);
1731 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1732 offset_in_page(skb->data),
1733 ACE_MINI_BUFSIZE,
1734 PCI_DMA_FROMDEVICE);
1735 ap->skb->rx_mini_skbuff[idx].skb = skb;
1736 pci_unmap_addr_set(&ap->skb->rx_mini_skbuff[idx],
1737 mapping, mapping);
1738
1739 rd = &ap->rx_mini_ring[idx];
1740 set_aceaddr(&rd->addr, mapping);
1741 rd->size = ACE_MINI_BUFSIZE;
1742 rd->idx = idx;
1743 idx = (idx + 1) % RX_MINI_RING_ENTRIES;
1744 }
1745
1746 if (!i)
1747 goto error_out;
1748
1749 atomic_add(i, &ap->cur_mini_bufs);
1750
1751 ap->rx_mini_skbprd = idx;
1752
1753 writel(idx, &regs->RxMiniPrd);
1754 wmb();
1755
1756 out:
1757 clear_bit(0, &ap->mini_refill_busy);
1758 return;
1759 error_out:
1760 printk(KERN_INFO "Out of memory when allocating "
1761 "mini receive buffers\n");
1762 goto out;
1763}
1764
1765
1766/*
1767 * Load the jumbo rx ring, this may happen at any time if the MTU
1768 * is changed to a value > 1500.
1769 */
1770static void ace_load_jumbo_rx_ring(struct ace_private *ap, int nr_bufs)
1771{
1772 struct ace_regs __iomem *regs = ap->regs;
1773 short i, idx;
1774
1775 idx = ap->rx_jumbo_skbprd;
1776
1777 for (i = 0; i < nr_bufs; i++) {
1778 struct sk_buff *skb;
1779 struct rx_desc *rd;
1780 dma_addr_t mapping;
1781
1782 skb = alloc_skb(ACE_JUMBO_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
1783 if (!skb)
1784 break;
1785
1786 skb_reserve(skb, NET_IP_ALIGN);
1787 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1788 offset_in_page(skb->data),
1789 ACE_JUMBO_BUFSIZE,
1790 PCI_DMA_FROMDEVICE);
1791 ap->skb->rx_jumbo_skbuff[idx].skb = skb;
1792 pci_unmap_addr_set(&ap->skb->rx_jumbo_skbuff[idx],
1793 mapping, mapping);
1794
1795 rd = &ap->rx_jumbo_ring[idx];
1796 set_aceaddr(&rd->addr, mapping);
1797 rd->size = ACE_JUMBO_BUFSIZE;
1798 rd->idx = idx;
1799 idx = (idx + 1) % RX_JUMBO_RING_ENTRIES;
1800 }
1801
1802 if (!i)
1803 goto error_out;
1804
1805 atomic_add(i, &ap->cur_jumbo_bufs);
1806 ap->rx_jumbo_skbprd = idx;
1807
1808 if (ACE_IS_TIGON_I(ap)) {
1809 struct cmd cmd;
1810 cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
1811 cmd.code = 0;
1812 cmd.idx = ap->rx_jumbo_skbprd;
1813 ace_issue_cmd(regs, &cmd);
1814 } else {
1815 writel(idx, &regs->RxJumboPrd);
1816 wmb();
1817 }
1818
1819 out:
1820 clear_bit(0, &ap->jumbo_refill_busy);
1821 return;
1822 error_out:
1823 if (net_ratelimit())
1824 printk(KERN_INFO "Out of memory when allocating "
1825 "jumbo receive buffers\n");
1826 goto out;
1827}
1828
1829
1830/*
1831 * All events are considered to be slow (RX/TX ints do not generate
1832 * events) and are handled here, outside the main interrupt handler,
1833 * to reduce the size of the handler.
1834 */
1835static u32 ace_handle_event(struct net_device *dev, u32 evtcsm, u32 evtprd)
1836{
1837 struct ace_private *ap;
1838
1839 ap = netdev_priv(dev);
1840
1841 while (evtcsm != evtprd) {
1842 switch (ap->evt_ring[evtcsm].evt) {
1843 case E_FW_RUNNING:
1844 printk(KERN_INFO "%s: Firmware up and running\n",
1845 ap->name);
1846 ap->fw_running = 1;
1847 wmb();
1848 break;
1849 case E_STATS_UPDATED:
1850 break;
1851 case E_LNK_STATE:
1852 {
1853 u16 code = ap->evt_ring[evtcsm].code;
1854 switch (code) {
1855 case E_C_LINK_UP:
1856 {
1857 u32 state = readl(&ap->regs->GigLnkState);
1858 printk(KERN_WARNING "%s: Optical link UP "
1859 "(%s Duplex, Flow Control: %s%s)\n",
1860 ap->name,
1861 state & LNK_FULL_DUPLEX ? "Full":"Half",
1862 state & LNK_TX_FLOW_CTL_Y ? "TX " : "",
1863 state & LNK_RX_FLOW_CTL_Y ? "RX" : "");
1864 break;
1865 }
1866 case E_C_LINK_DOWN:
1867 printk(KERN_WARNING "%s: Optical link DOWN\n",
1868 ap->name);
1869 break;
1870 case E_C_LINK_10_100:
1871 printk(KERN_WARNING "%s: 10/100BaseT link "
1872 "UP\n", ap->name);
1873 break;
1874 default:
1875 printk(KERN_ERR "%s: Unknown optical link "
1876 "state %02x\n", ap->name, code);
1877 }
1878 break;
1879 }
1880 case E_ERROR:
1881 switch(ap->evt_ring[evtcsm].code) {
1882 case E_C_ERR_INVAL_CMD:
1883 printk(KERN_ERR "%s: invalid command error\n",
1884 ap->name);
1885 break;
1886 case E_C_ERR_UNIMP_CMD:
1887 printk(KERN_ERR "%s: unimplemented command "
1888 "error\n", ap->name);
1889 break;
1890 case E_C_ERR_BAD_CFG:
1891 printk(KERN_ERR "%s: bad config error\n",
1892 ap->name);
1893 break;
1894 default:
1895 printk(KERN_ERR "%s: unknown error %02x\n",
1896 ap->name, ap->evt_ring[evtcsm].code);
1897 }
1898 break;
1899 case E_RESET_JUMBO_RNG:
1900 {
1901 int i;
1902 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
1903 if (ap->skb->rx_jumbo_skbuff[i].skb) {
1904 ap->rx_jumbo_ring[i].size = 0;
1905 set_aceaddr(&ap->rx_jumbo_ring[i].addr, 0);
1906 dev_kfree_skb(ap->skb->rx_jumbo_skbuff[i].skb);
1907 ap->skb->rx_jumbo_skbuff[i].skb = NULL;
1908 }
1909 }
1910
1911 if (ACE_IS_TIGON_I(ap)) {
1912 struct cmd cmd;
1913 cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
1914 cmd.code = 0;
1915 cmd.idx = 0;
1916 ace_issue_cmd(ap->regs, &cmd);
1917 } else {
1918 writel(0, &((ap->regs)->RxJumboPrd));
1919 wmb();
1920 }
1921
1922 ap->jumbo = 0;
1923 ap->rx_jumbo_skbprd = 0;
1924 printk(KERN_INFO "%s: Jumbo ring flushed\n",
1925 ap->name);
1926 clear_bit(0, &ap->jumbo_refill_busy);
1927 break;
1928 }
1929 default:
1930 printk(KERN_ERR "%s: Unhandled event 0x%02x\n",
1931 ap->name, ap->evt_ring[evtcsm].evt);
1932 }
1933 evtcsm = (evtcsm + 1) % EVT_RING_ENTRIES;
1934 }
1935
1936 return evtcsm;
1937}
1938
1939
1940static void ace_rx_int(struct net_device *dev, u32 rxretprd, u32 rxretcsm)
1941{
1942 struct ace_private *ap = netdev_priv(dev);
1943 u32 idx;
1944 int mini_count = 0, std_count = 0;
1945
1946 idx = rxretcsm;
1947
1948 prefetchw(&ap->cur_rx_bufs);
1949 prefetchw(&ap->cur_mini_bufs);
6aa20a22 1950
1da177e4
LT		 1951 while (idx != rxretprd) {
1952 struct ring_info *rip;
1953 struct sk_buff *skb;
1954 struct rx_desc *rxdesc, *retdesc;
1955 u32 skbidx;
1956 int bd_flags, desc_type, mapsize;
1957 u16 csum;
1958
1959
1960 /* make sure the rx descriptor isn't read before rxretprd */
6aa20a22 1961 if (idx == rxretcsm)
1da177e4
LT		 1962 rmb();
1963
1964 retdesc = &ap->rx_return_ring[idx];
1965 skbidx = retdesc->idx;
1966 bd_flags = retdesc->flags;
1967 desc_type = bd_flags & (BD_FLG_JUMBO | BD_FLG_MINI);
1968
1969 switch(desc_type) {
1970 /*
1971 * Normal frames do not have any flags set
1972 *
1973 * Mini and normal frames arrive frequently,
1974 * so use a local counter to avoid doing
1975 * atomic operations for each packet arriving.
1976 */
1977 case 0:
1978 rip = &ap->skb->rx_std_skbuff[skbidx];
1979 mapsize = ACE_STD_BUFSIZE;
1980 rxdesc = &ap->rx_std_ring[skbidx];
1981 std_count++;
1982 break;
1983 case BD_FLG_JUMBO:
1984 rip = &ap->skb->rx_jumbo_skbuff[skbidx];
1985 mapsize = ACE_JUMBO_BUFSIZE;
1986 rxdesc = &ap->rx_jumbo_ring[skbidx];
1987 atomic_dec(&ap->cur_jumbo_bufs);
1988 break;
1989 case BD_FLG_MINI:
1990 rip = &ap->skb->rx_mini_skbuff[skbidx];
1991 mapsize = ACE_MINI_BUFSIZE;
1992 rxdesc = &ap->rx_mini_ring[skbidx];
6aa20a22 1993 mini_count++;
1da177e4
LT		 1994 break;
1995 default:
1996 printk(KERN_INFO "%s: unknown frame type (0x%02x) "
1997 "returned by NIC\n", dev->name,
1998 retdesc->flags);
1999 goto error;
2000 }
2001
2002 skb = rip->skb;
2003 rip->skb = NULL;
2004 pci_unmap_page(ap->pdev,
2005 pci_unmap_addr(rip, mapping),
2006 mapsize,
2007 PCI_DMA_FROMDEVICE);
2008 skb_put(skb, retdesc->size);
2009
2010 /*
2011 * Fly baby, fly!
2012 */
2013 csum = retdesc->tcp_udp_csum;
2014
1da177e4
LT		 2015 skb->protocol = eth_type_trans(skb, dev);
2016
2017 /*
2018 * Instead of forcing the poor tigon mips cpu to calculate
2019 * pseudo hdr checksum, we do this ourselves.
2020 */
2021 if (bd_flags & BD_FLG_TCP_UDP_SUM) {
2022 skb->csum = htons(csum);
84fa7933 2023 skb->ip_summed = CHECKSUM_COMPLETE;
1da177e4
LT		 2024 } else {
2025 skb->ip_summed = CHECKSUM_NONE;
2026 }
2027
2028 /* send it up */
2029#if ACENIC_DO_VLAN
2030 if (ap->vlgrp && (bd_flags & BD_FLG_VLAN_TAG)) {
2031 vlan_hwaccel_rx(skb, ap->vlgrp, retdesc->vlan);
2032 } else
2033#endif
2034 netif_rx(skb);
2035
966e37bc
PZ		 2036 dev->stats.rx_packets++;
2037 dev->stats.rx_bytes += retdesc->size;
1da177e4
LT		 2038
2039 idx = (idx + 1) % RX_RETURN_RING_ENTRIES;
2040 }
2041
2042 atomic_sub(std_count, &ap->cur_rx_bufs);
2043 if (!ACE_IS_TIGON_I(ap))
2044 atomic_sub(mini_count, &ap->cur_mini_bufs);
2045
2046 out:
2047 /*
2048 * According to the documentation RxRetCsm is obsolete with
2049 * the 12.3.x Firmware - my Tigon I NICs seem to disagree!
2050 */
2051 if (ACE_IS_TIGON_I(ap)) {
2052 writel(idx, &ap->regs->RxRetCsm);
2053 }
2054 ap->cur_rx = idx;
2055
2056 return;
2057 error:
2058 idx = rxretprd;
2059 goto out;
2060}
2061
2062
2063static inline void ace_tx_int(struct net_device *dev,
2064 u32 txcsm, u32 idx)
2065{
2066 struct ace_private *ap = netdev_priv(dev);
2067
2068 do {
2069 struct sk_buff *skb;
2070 dma_addr_t mapping;
2071 struct tx_ring_info *info;
2072
2073 info = ap->skb->tx_skbuff + idx;
2074 skb = info->skb;
2075 mapping = pci_unmap_addr(info, mapping);
2076
2077 if (mapping) {
2078 pci_unmap_page(ap->pdev, mapping,
2079 pci_unmap_len(info, maplen),
2080 PCI_DMA_TODEVICE);
2081 pci_unmap_addr_set(info, mapping, 0);
2082 }
2083
2084 if (skb) {
966e37bc
PZ		 2085 dev->stats.tx_packets++;
2086 dev->stats.tx_bytes += skb->len;
1da177e4
LT		 2087 dev_kfree_skb_irq(skb);
2088 info->skb = NULL;
2089 }
2090
2091 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2092 } while (idx != txcsm);
2093
2094 if (netif_queue_stopped(dev))
2095 netif_wake_queue(dev);
2096
2097 wmb();
2098 ap->tx_ret_csm = txcsm;
2099
2100 /* So... tx_ret_csm is advanced _after_ check for device wakeup.
2101 *
2102 * We could try to make it before. In this case we would get
2103 * the following race condition: hard_start_xmit on other cpu
2104 * enters after we advanced tx_ret_csm and fills space,
2105 * which we have just freed, so that we make illegal device wakeup.
2106 * There is no good way to workaround this (at entry
2107 * to ace_start_xmit detects this condition and prevents
2108 * ring corruption, but it is not a good workaround.)
2109 *
2110 * When tx_ret_csm is advanced after, we wake up device _only_
2111 * if we really have some space in ring (though the core doing
2112 * hard_start_xmit can see full ring for some period and has to
2113 * synchronize.) Superb.
2114 * BUT! We get another subtle race condition. hard_start_xmit
2115 * may think that ring is full between wakeup and advancing
2116 * tx_ret_csm and will stop device instantly! It is not so bad.
2117 * We are guaranteed that there is something in ring, so that
2118 * the next irq will resume transmission. To speedup this we could
2119 * mark descriptor, which closes ring with BD_FLG_COAL_NOW
2120 * (see ace_start_xmit).
2121 *
2122 * Well, this dilemma exists in all lock-free devices.
2123 * We, following scheme used in drivers by Donald Becker,
2124 * select the least dangerous.
2125 * --ANK
2126 */
2127}
2128
2129
7d12e780 2130static irqreturn_t ace_interrupt(int irq, void *dev_id)
1da177e4
LT		 2131{
2132 struct net_device *dev = (struct net_device *)dev_id;
2133 struct ace_private *ap = netdev_priv(dev);
2134 struct ace_regs __iomem *regs = ap->regs;
2135 u32 idx;
2136 u32 txcsm, rxretcsm, rxretprd;
2137 u32 evtcsm, evtprd;
2138
2139 /*
2140 * In case of PCI shared interrupts or spurious interrupts,
2141 * we want to make sure it is actually our interrupt before
2142 * spending any time in here.
2143 */
2144 if (!(readl(&regs->HostCtrl) & IN_INT))
2145 return IRQ_NONE;
2146
2147 /*
2148 * ACK intr now. Otherwise we will lose updates to rx_ret_prd,
2149 * which happened _after_ rxretprd = *ap->rx_ret_prd; but before
2150 * writel(0, &regs->Mb0Lo).
2151 *
2152 * "IRQ avoidance" recommended in docs applies to IRQs served
2153 * threads and it is wrong even for that case.
2154 */
2155 writel(0, &regs->Mb0Lo);
2156 readl(&regs->Mb0Lo);
2157
2158 /*
2159 * There is no conflict between transmit handling in
2160 * start_xmit and receive processing, thus there is no reason
2161 * to take a spin lock for RX handling. Wait until we start
2162 * working on the other stuff - hey we don't need a spin lock
2163 * anymore.
2164 */
2165 rxretprd = *ap->rx_ret_prd;
2166 rxretcsm = ap->cur_rx;
2167
2168 if (rxretprd != rxretcsm)
2169 ace_rx_int(dev, rxretprd, rxretcsm);
2170
2171 txcsm = *ap->tx_csm;
2172 idx = ap->tx_ret_csm;
2173
2174 if (txcsm != idx) {
2175 /*
2176 * If each skb takes only one descriptor this check degenerates
2177 * to identity, because new space has just been opened.
2178 * But if skbs are fragmented we must check that this index
2179 * update releases enough of space, otherwise we just
2180 * wait for device to make more work.
2181 */
2182 if (!tx_ring_full(ap, txcsm, ap->tx_prd))
2183 ace_tx_int(dev, txcsm, idx);
2184 }
2185
2186 evtcsm = readl(&regs->EvtCsm);
2187 evtprd = *ap->evt_prd;
2188
2189 if (evtcsm != evtprd) {
2190 evtcsm = ace_handle_event(dev, evtcsm, evtprd);
2191 writel(evtcsm, &regs->EvtCsm);
2192 }
2193
2194 /*
2195 * This has to go last in the interrupt handler and run with
2196 * the spin lock released ... what lock?
2197 */
2198 if (netif_running(dev)) {
2199 int cur_size;
2200 int run_tasklet = 0;
2201
2202 cur_size = atomic_read(&ap->cur_rx_bufs);
2203 if (cur_size < RX_LOW_STD_THRES) {
2204 if ((cur_size < RX_PANIC_STD_THRES) &&
2205 !test_and_set_bit(0, &ap->std_refill_busy)) {
2206#ifdef DEBUG
2207 printk("low on std buffers %i\n", cur_size);
2208#endif
2209 ace_load_std_rx_ring(ap,
2210 RX_RING_SIZE - cur_size);
2211 } else
2212 run_tasklet = 1;
2213 }
2214
2215 if (!ACE_IS_TIGON_I(ap)) {
2216 cur_size = atomic_read(&ap->cur_mini_bufs);
2217 if (cur_size < RX_LOW_MINI_THRES) {
2218 if ((cur_size < RX_PANIC_MINI_THRES) &&
2219 !test_and_set_bit(0,
2220 &ap->mini_refill_busy)) {
2221#ifdef DEBUG
2222 printk("low on mini buffers %i\n",
2223 cur_size);
2224#endif
2225 ace_load_mini_rx_ring(ap, RX_MINI_SIZE - cur_size);
2226 } else
2227 run_tasklet = 1;
2228 }
2229 }
2230
2231 if (ap->jumbo) {
2232 cur_size = atomic_read(&ap->cur_jumbo_bufs);
2233 if (cur_size < RX_LOW_JUMBO_THRES) {
2234 if ((cur_size < RX_PANIC_JUMBO_THRES) &&
2235 !test_and_set_bit(0,
2236 &ap->jumbo_refill_busy)){
2237#ifdef DEBUG
2238 printk("low on jumbo buffers %i\n",
2239 cur_size);
2240#endif
2241 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE - cur_size);
2242 } else
2243 run_tasklet = 1;
2244 }
2245 }
2246 if (run_tasklet && !ap->tasklet_pending) {
2247 ap->tasklet_pending = 1;
2248 tasklet_schedule(&ap->ace_tasklet);
2249 }
2250 }
2251
2252 return IRQ_HANDLED;
2253}
2254
2255
2256#if ACENIC_DO_VLAN
2257static void ace_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
2258{
2259 struct ace_private *ap = netdev_priv(dev);
2260 unsigned long flags;
2261
2262 local_irq_save(flags);
2263 ace_mask_irq(dev);
2264
2265 ap->vlgrp = grp;
2266
2267 ace_unmask_irq(dev);
2268 local_irq_restore(flags);
2269}
1da177e4
LT		 2270#endif /* ACENIC_DO_VLAN */
2271
2272
2273static int ace_open(struct net_device *dev)
2274{
2275 struct ace_private *ap = netdev_priv(dev);
2276 struct ace_regs __iomem *regs = ap->regs;
2277 struct cmd cmd;
2278
2279 if (!(ap->fw_running)) {
2280 printk(KERN_WARNING "%s: Firmware not running!\n", dev->name);
2281 return -EBUSY;
2282 }
2283
2284 writel(dev->mtu + ETH_HLEN + 4, &regs->IfMtu);
2285
2286 cmd.evt = C_CLEAR_STATS;
2287 cmd.code = 0;
2288 cmd.idx = 0;
2289 ace_issue_cmd(regs, &cmd);
2290
2291 cmd.evt = C_HOST_STATE;
2292 cmd.code = C_C_STACK_UP;
2293 cmd.idx = 0;
2294 ace_issue_cmd(regs, &cmd);
2295
2296 if (ap->jumbo &&
2297 !test_and_set_bit(0, &ap->jumbo_refill_busy))
2298 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE);
2299
2300 if (dev->flags & IFF_PROMISC) {
2301 cmd.evt = C_SET_PROMISC_MODE;
2302 cmd.code = C_C_PROMISC_ENABLE;
2303 cmd.idx = 0;
2304 ace_issue_cmd(regs, &cmd);
2305
2306 ap->promisc = 1;
2307 }else
2308 ap->promisc = 0;
2309 ap->mcast_all = 0;
2310
2311#if 0
2312 cmd.evt = C_LNK_NEGOTIATION;
2313 cmd.code = 0;
2314 cmd.idx = 0;
2315 ace_issue_cmd(regs, &cmd);
2316#endif
2317
2318 netif_start_queue(dev);
2319
2320 /*
2321 * Setup the bottom half rx ring refill handler
2322 */
2323 tasklet_init(&ap->ace_tasklet, ace_tasklet, (unsigned long)dev);
2324 return 0;
2325}
2326
2327
2328static int ace_close(struct net_device *dev)
2329{
2330 struct ace_private *ap = netdev_priv(dev);
2331 struct ace_regs __iomem *regs = ap->regs;
2332 struct cmd cmd;
2333 unsigned long flags;
2334 short i;
2335
2336 /*
2337 * Without (or before) releasing irq and stopping hardware, this
2338 * is an absolute non-sense, by the way. It will be reset instantly
2339 * by the first irq.
2340 */
2341 netif_stop_queue(dev);
2342
6aa20a22 2343
1da177e4
LT		 2344 if (ap->promisc) {
2345 cmd.evt = C_SET_PROMISC_MODE;
2346 cmd.code = C_C_PROMISC_DISABLE;
2347 cmd.idx = 0;
2348 ace_issue_cmd(regs, &cmd);
2349 ap->promisc = 0;
2350 }
2351
2352 cmd.evt = C_HOST_STATE;
2353 cmd.code = C_C_STACK_DOWN;
2354 cmd.idx = 0;
2355 ace_issue_cmd(regs, &cmd);
2356
2357 tasklet_kill(&ap->ace_tasklet);
2358
2359 /*
2360 * Make sure one CPU is not processing packets while
2361 * buffers are being released by another.
2362 */
2363
2364 local_irq_save(flags);
2365 ace_mask_irq(dev);
2366
2367 for (i = 0; i < ACE_TX_RING_ENTRIES(ap); i++) {
2368 struct sk_buff *skb;
2369 dma_addr_t mapping;
2370 struct tx_ring_info *info;
2371
2372 info = ap->skb->tx_skbuff + i;
2373 skb = info->skb;
2374 mapping = pci_unmap_addr(info, mapping);
2375
2376 if (mapping) {
2377 if (ACE_IS_TIGON_I(ap)) {
ddfce6bb
SH		 2378 /* NB: TIGON_1 is special, tx_ring is in io space */
2379 struct tx_desc __iomem *tx;
2380 tx = (__force struct tx_desc __iomem *) &ap->tx_ring[i];
1da177e4
LT		 2381 writel(0, &tx->addr.addrhi);
2382 writel(0, &tx->addr.addrlo);
2383 writel(0, &tx->flagsize);
2384 } else
2385 memset(ap->tx_ring + i, 0,
2386 sizeof(struct tx_desc));
2387 pci_unmap_page(ap->pdev, mapping,
2388 pci_unmap_len(info, maplen),
2389 PCI_DMA_TODEVICE);
2390 pci_unmap_addr_set(info, mapping, 0);
2391 }
2392 if (skb) {
2393 dev_kfree_skb(skb);
2394 info->skb = NULL;
2395 }
2396 }
2397
2398 if (ap->jumbo) {
2399 cmd.evt = C_RESET_JUMBO_RNG;
2400 cmd.code = 0;
2401 cmd.idx = 0;
2402 ace_issue_cmd(regs, &cmd);
2403 }
2404
2405 ace_unmask_irq(dev);
2406 local_irq_restore(flags);
2407
2408 return 0;
2409}
2410
2411
2412static inline dma_addr_t
2413ace_map_tx_skb(struct ace_private *ap, struct sk_buff *skb,
2414 struct sk_buff *tail, u32 idx)
2415{
2416 dma_addr_t mapping;
2417 struct tx_ring_info *info;
2418
2419 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
2420 offset_in_page(skb->data),
2421 skb->len, PCI_DMA_TODEVICE);
2422
2423 info = ap->skb->tx_skbuff + idx;
2424 info->skb = tail;
2425 pci_unmap_addr_set(info, mapping, mapping);
2426 pci_unmap_len_set(info, maplen, skb->len);
2427 return mapping;
2428}
2429
2430
2431static inline void
2432ace_load_tx_bd(struct ace_private *ap, struct tx_desc *desc, u64 addr,
2433 u32 flagsize, u32 vlan_tag)
2434{
2435#if !USE_TX_COAL_NOW
2436 flagsize &= ~BD_FLG_COAL_NOW;
2437#endif
2438
2439 if (ACE_IS_TIGON_I(ap)) {
ddfce6bb 2440 struct tx_desc __iomem *io = (__force struct tx_desc __iomem *) desc;
1da177e4
LT		 2441 writel(addr >> 32, &io->addr.addrhi);
2442 writel(addr & 0xffffffff, &io->addr.addrlo);
2443 writel(flagsize, &io->flagsize);
2444#if ACENIC_DO_VLAN
2445 writel(vlan_tag, &io->vlanres);
2446#endif
2447 } else {
2448 desc->addr.addrhi = addr >> 32;
2449 desc->addr.addrlo = addr;
2450 desc->flagsize = flagsize;
2451#if ACENIC_DO_VLAN
2452 desc->vlanres = vlan_tag;
2453#endif
2454 }
2455}
2456
2457
2458static int ace_start_xmit(struct sk_buff *skb, struct net_device *dev)
2459{
2460 struct ace_private *ap = netdev_priv(dev);
2461 struct ace_regs __iomem *regs = ap->regs;
2462 struct tx_desc *desc;
2463 u32 idx, flagsize;
2464 unsigned long maxjiff = jiffies + 3*HZ;
2465
2466restart:
2467 idx = ap->tx_prd;
2468
2469 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2470 goto overflow;
2471
2472 if (!skb_shinfo(skb)->nr_frags) {
2473 dma_addr_t mapping;
2474 u32 vlan_tag = 0;
2475
2476 mapping = ace_map_tx_skb(ap, skb, skb, idx);
2477 flagsize = (skb->len << 16) | (BD_FLG_END);
84fa7933 2478 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4
LT		 2479 flagsize |= BD_FLG_TCP_UDP_SUM;
2480#if ACENIC_DO_VLAN
2481 if (vlan_tx_tag_present(skb)) {
2482 flagsize |= BD_FLG_VLAN_TAG;
2483 vlan_tag = vlan_tx_tag_get(skb);
2484 }
2485#endif
2486 desc = ap->tx_ring + idx;
2487 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2488
2489 /* Look at ace_tx_int for explanations. */
2490 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2491 flagsize |= BD_FLG_COAL_NOW;
2492
2493 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2494 } else {
2495 dma_addr_t mapping;
2496 u32 vlan_tag = 0;
2497 int i, len = 0;
2498
2499 mapping = ace_map_tx_skb(ap, skb, NULL, idx);
2500 flagsize = (skb_headlen(skb) << 16);
84fa7933 2501 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4
LT		 2502 flagsize |= BD_FLG_TCP_UDP_SUM;
2503#if ACENIC_DO_VLAN
2504 if (vlan_tx_tag_present(skb)) {
2505 flagsize |= BD_FLG_VLAN_TAG;
2506 vlan_tag = vlan_tx_tag_get(skb);
2507 }
2508#endif
2509
2510 ace_load_tx_bd(ap, ap->tx_ring + idx, mapping, flagsize, vlan_tag);
2511
2512 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2513
2514 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2515 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2516 struct tx_ring_info *info;
2517
2518 len += frag->size;
2519 info = ap->skb->tx_skbuff + idx;
2520 desc = ap->tx_ring + idx;
2521
2522 mapping = pci_map_page(ap->pdev, frag->page,
2523 frag->page_offset, frag->size,
2524 PCI_DMA_TODEVICE);
2525
2526 flagsize = (frag->size << 16);
84fa7933 2527 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4
LT		 2528 flagsize |= BD_FLG_TCP_UDP_SUM;
2529 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2530
2531 if (i == skb_shinfo(skb)->nr_frags - 1) {
2532 flagsize |= BD_FLG_END;
2533 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2534 flagsize |= BD_FLG_COAL_NOW;
2535
2536 /*
2537 * Only the last fragment frees
2538 * the skb!
2539 */
2540 info->skb = skb;
2541 } else {
2542 info->skb = NULL;
2543 }
2544 pci_unmap_addr_set(info, mapping, mapping);
2545 pci_unmap_len_set(info, maplen, frag->size);
2546 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2547 }
2548 }
2549
2550 wmb();
2551 ap->tx_prd = idx;
2552 ace_set_txprd(regs, ap, idx);
2553
2554 if (flagsize & BD_FLG_COAL_NOW) {
2555 netif_stop_queue(dev);
2556
2557 /*
2558 * A TX-descriptor producer (an IRQ) might have gotten
2559 * inbetween, making the ring free again. Since xmit is
2560 * serialized, this is the only situation we have to
2561 * re-test.
2562 */
2563 if (!tx_ring_full(ap, ap->tx_ret_csm, idx))
2564 netif_wake_queue(dev);
2565 }
2566
2567 dev->trans_start = jiffies;
2568 return NETDEV_TX_OK;
2569
2570overflow:
2571 /*
2572 * This race condition is unavoidable with lock-free drivers.
2573 * We wake up the queue _before_ tx_prd is advanced, so that we can
2574 * enter hard_start_xmit too early, while tx ring still looks closed.
2575 * This happens ~1-4 times per 100000 packets, so that we can allow
2576 * to loop syncing to other CPU. Probably, we need an additional
2577 * wmb() in ace_tx_intr as well.
2578 *
2579 * Note that this race is relieved by reserving one more entry
2580 * in tx ring than it is necessary (see original non-SG driver).
2581 * However, with SG we need to reserve 2*MAX_SKB_FRAGS+1, which
2582 * is already overkill.
2583 *
2584 * Alternative is to return with 1 not throttling queue. In this
2585 * case loop becomes longer, no more useful effects.
2586 */
2587 if (time_before(jiffies, maxjiff)) {
2588 barrier();
2589 cpu_relax();
2590 goto restart;
2591 }
6aa20a22 2592
1da177e4
LT		 2593 /* The ring is stuck full. */
2594 printk(KERN_WARNING "%s: Transmit ring stuck full\n", dev->name);
2595 return NETDEV_TX_BUSY;
2596}
2597
2598
2599static int ace_change_mtu(struct net_device *dev, int new_mtu)
2600{
2601 struct ace_private *ap = netdev_priv(dev);
2602 struct ace_regs __iomem *regs = ap->regs;
2603
2604 if (new_mtu > ACE_JUMBO_MTU)
2605 return -EINVAL;
2606
2607 writel(new_mtu + ETH_HLEN + 4, &regs->IfMtu);
2608 dev->mtu = new_mtu;
2609
2610 if (new_mtu > ACE_STD_MTU) {
2611 if (!(ap->jumbo)) {
2612 printk(KERN_INFO "%s: Enabling Jumbo frame "
2613 "support\n", dev->name);
2614 ap->jumbo = 1;
2615 if (!test_and_set_bit(0, &ap->jumbo_refill_busy))
2616 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE);
2617 ace_set_rxtx_parms(dev, 1);
2618 }
2619 } else {
2620 while (test_and_set_bit(0, &ap->jumbo_refill_busy));
2621 ace_sync_irq(dev->irq);
2622 ace_set_rxtx_parms(dev, 0);
2623 if (ap->jumbo) {
2624 struct cmd cmd;
2625
2626 cmd.evt = C_RESET_JUMBO_RNG;
2627 cmd.code = 0;
2628 cmd.idx = 0;
2629 ace_issue_cmd(regs, &cmd);
2630 }
2631 }
2632
2633 return 0;
2634}
2635
2636static int ace_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2637{
2638 struct ace_private *ap = netdev_priv(dev);
2639 struct ace_regs __iomem *regs = ap->regs;
2640 u32 link;
2641
2642 memset(ecmd, 0, sizeof(struct ethtool_cmd));
2643 ecmd->supported =
2644 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2645 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2646 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full |
2647 SUPPORTED_Autoneg | SUPPORTED_FIBRE);
2648
2649 ecmd->port = PORT_FIBRE;
2650 ecmd->transceiver = XCVR_INTERNAL;
2651
2652 link = readl(&regs->GigLnkState);
2653 if (link & LNK_1000MB)
2654 ecmd->speed = SPEED_1000;
2655 else {
2656 link = readl(&regs->FastLnkState);
2657 if (link & LNK_100MB)
2658 ecmd->speed = SPEED_100;
2659 else if (link & LNK_10MB)
2660 ecmd->speed = SPEED_10;
2661 else
2662 ecmd->speed = 0;
2663 }
2664 if (link & LNK_FULL_DUPLEX)
2665 ecmd->duplex = DUPLEX_FULL;
2666 else
2667 ecmd->duplex = DUPLEX_HALF;
2668
2669 if (link & LNK_NEGOTIATE)
2670 ecmd->autoneg = AUTONEG_ENABLE;
2671 else
2672 ecmd->autoneg = AUTONEG_DISABLE;
2673
2674#if 0
2675 /*
2676 * Current struct ethtool_cmd is insufficient
2677 */
2678 ecmd->trace = readl(&regs->TuneTrace);
2679
2680 ecmd->txcoal = readl(&regs->TuneTxCoalTicks);
2681 ecmd->rxcoal = readl(&regs->TuneRxCoalTicks);
2682#endif
2683 ecmd->maxtxpkt = readl(&regs->TuneMaxTxDesc);
2684 ecmd->maxrxpkt = readl(&regs->TuneMaxRxDesc);
2685
2686 return 0;
2687}
2688
2689static int ace_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2690{
2691 struct ace_private *ap = netdev_priv(dev);
2692 struct ace_regs __iomem *regs = ap->regs;
2693 u32 link, speed;
2694
2695 link = readl(&regs->GigLnkState);
2696 if (link & LNK_1000MB)
2697 speed = SPEED_1000;
2698 else {
2699 link = readl(&regs->FastLnkState);
2700 if (link & LNK_100MB)
2701 speed = SPEED_100;
2702 else if (link & LNK_10MB)
2703 speed = SPEED_10;
2704 else
2705 speed = SPEED_100;
2706 }
2707
2708 link = LNK_ENABLE | LNK_1000MB | LNK_100MB | LNK_10MB |
2709 LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL;
2710 if (!ACE_IS_TIGON_I(ap))
2711 link |= LNK_TX_FLOW_CTL_Y;
2712 if (ecmd->autoneg == AUTONEG_ENABLE)
2713 link |= LNK_NEGOTIATE;
2714 if (ecmd->speed != speed) {
2715 link &= ~(LNK_1000MB | LNK_100MB | LNK_10MB);
2716 switch (speed) {
2717 case SPEED_1000:
2718 link |= LNK_1000MB;
2719 break;
2720 case SPEED_100:
2721 link |= LNK_100MB;
2722 break;
2723 case SPEED_10:
2724 link |= LNK_10MB;
2725 break;
2726 }
2727 }
2728
2729 if (ecmd->duplex == DUPLEX_FULL)
2730 link |= LNK_FULL_DUPLEX;
2731
2732 if (link != ap->link) {
2733 struct cmd cmd;
2734 printk(KERN_INFO "%s: Renegotiating link state\n",
2735 dev->name);
2736
2737 ap->link = link;
2738 writel(link, &regs->TuneLink);
2739 if (!ACE_IS_TIGON_I(ap))
2740 writel(link, &regs->TuneFastLink);
2741 wmb();
2742
2743 cmd.evt = C_LNK_NEGOTIATION;
2744 cmd.code = 0;
2745 cmd.idx = 0;
2746 ace_issue_cmd(regs, &cmd);
2747 }
2748 return 0;
2749}
2750
6aa20a22 2751static void ace_get_drvinfo(struct net_device *dev,
1da177e4
LT		 2752 struct ethtool_drvinfo *info)
2753{
2754 struct ace_private *ap = netdev_priv(dev);
2755
2756 strlcpy(info->driver, "acenic", sizeof(info->driver));
6aa20a22 2757 snprintf(info->version, sizeof(info->version), "%i.%i.%i",
1da177e4
LT		 2758 tigonFwReleaseMajor, tigonFwReleaseMinor,
2759 tigonFwReleaseFix);
2760
2761 if (ap->pdev)
6aa20a22 2762 strlcpy(info->bus_info, pci_name(ap->pdev),
1da177e4
LT		 2763 sizeof(info->bus_info));
2764
2765}
2766
2767/*
2768 * Set the hardware MAC address.
2769 */
2770static int ace_set_mac_addr(struct net_device *dev, void *p)
2771{
2772 struct ace_private *ap = netdev_priv(dev);
2773 struct ace_regs __iomem *regs = ap->regs;
2774 struct sockaddr *addr=p;
2775 u8 *da;
2776 struct cmd cmd;
2777
2778 if(netif_running(dev))
2779 return -EBUSY;
2780
2781 memcpy(dev->dev_addr, addr->sa_data,dev->addr_len);
2782
2783 da = (u8 *)dev->dev_addr;
2784
2785 writel(da[0] << 8 | da[1], &regs->MacAddrHi);
2786 writel((da[2] << 24) | (da[3] << 16) | (da[4] << 8) | da[5],
2787 &regs->MacAddrLo);
2788
2789 cmd.evt = C_SET_MAC_ADDR;
2790 cmd.code = 0;
2791 cmd.idx = 0;
2792 ace_issue_cmd(regs, &cmd);
2793
2794 return 0;
2795}
2796
2797
2798static void ace_set_multicast_list(struct net_device *dev)
2799{
2800 struct ace_private *ap = netdev_priv(dev);
2801 struct ace_regs __iomem *regs = ap->regs;
2802 struct cmd cmd;
2803
2804 if ((dev->flags & IFF_ALLMULTI) && !(ap->mcast_all)) {
2805 cmd.evt = C_SET_MULTICAST_MODE;
2806 cmd.code = C_C_MCAST_ENABLE;
2807 cmd.idx = 0;
2808 ace_issue_cmd(regs, &cmd);
2809 ap->mcast_all = 1;
2810 } else if (ap->mcast_all) {
2811 cmd.evt = C_SET_MULTICAST_MODE;
2812 cmd.code = C_C_MCAST_DISABLE;
2813 cmd.idx = 0;
2814 ace_issue_cmd(regs, &cmd);
2815 ap->mcast_all = 0;
2816 }
2817
2818 if ((dev->flags & IFF_PROMISC) && !(ap->promisc)) {
2819 cmd.evt = C_SET_PROMISC_MODE;
2820 cmd.code = C_C_PROMISC_ENABLE;
2821 cmd.idx = 0;
2822 ace_issue_cmd(regs, &cmd);
2823 ap->promisc = 1;
2824 }else if (!(dev->flags & IFF_PROMISC) && (ap->promisc)) {
2825 cmd.evt = C_SET_PROMISC_MODE;
2826 cmd.code = C_C_PROMISC_DISABLE;
2827 cmd.idx = 0;
2828 ace_issue_cmd(regs, &cmd);
2829 ap->promisc = 0;
2830 }
2831
2832 /*
2833 * For the time being multicast relies on the upper layers
2834 * filtering it properly. The Firmware does not allow one to
2835 * set the entire multicast list at a time and keeping track of
2836 * it here is going to be messy.
2837 */
2838 if ((dev->mc_count) && !(ap->mcast_all)) {
2839 cmd.evt = C_SET_MULTICAST_MODE;
2840 cmd.code = C_C_MCAST_ENABLE;
2841 cmd.idx = 0;
2842 ace_issue_cmd(regs, &cmd);
2843 }else if (!ap->mcast_all) {
2844 cmd.evt = C_SET_MULTICAST_MODE;
2845 cmd.code = C_C_MCAST_DISABLE;
2846 cmd.idx = 0;
2847 ace_issue_cmd(regs, &cmd);
2848 }
2849}
2850
2851
2852static struct net_device_stats *ace_get_stats(struct net_device *dev)
2853{
2854 struct ace_private *ap = netdev_priv(dev);
2855 struct ace_mac_stats __iomem *mac_stats =
2856 (struct ace_mac_stats __iomem *)ap->regs->Stats;
2857
966e37bc
PZ		 2858 dev->stats.rx_missed_errors = readl(&mac_stats->drop_space);
2859 dev->stats.multicast = readl(&mac_stats->kept_mc);
2860 dev->stats.collisions = readl(&mac_stats->coll);
1da177e4 2861
966e37bc 2862 return &dev->stats;
1da177e4
LT		 2863}
2864
2865
2866static void __devinit ace_copy(struct ace_regs __iomem *regs, void *src,
2867 u32 dest, int size)
2868{
2869 void __iomem *tdest;
2870 u32 *wsrc;
2871 short tsize, i;
2872
2873 if (size <= 0)
2874 return;
2875
2876 while (size > 0) {
2877 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
2878 min_t(u32, size, ACE_WINDOW_SIZE));
6aa20a22 2879 tdest = (void __iomem *) &regs->Window +
1da177e4
LT		 2880 (dest & (ACE_WINDOW_SIZE - 1));
2881 writel(dest & ~(ACE_WINDOW_SIZE - 1), &regs->WinBase);
2882 /*
2883 * This requires byte swapping on big endian, however
2884 * writel does that for us
2885 */
2886 wsrc = src;
2887 for (i = 0; i < (tsize / 4); i++) {
2888 writel(wsrc[i], tdest + i*4);
2889 }
2890 dest += tsize;
2891 src += tsize;
2892 size -= tsize;
2893 }
2894
2895 return;
2896}
2897
2898
2899static void __devinit ace_clear(struct ace_regs __iomem *regs, u32 dest, int size)
2900{
2901 void __iomem *tdest;
2902 short tsize = 0, i;
2903
2904 if (size <= 0)
2905 return;
2906
2907 while (size > 0) {
2908 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
2909 min_t(u32, size, ACE_WINDOW_SIZE));
6aa20a22 2910 tdest = (void __iomem *) &regs->Window +
1da177e4
LT		 2911 (dest & (ACE_WINDOW_SIZE - 1));
2912 writel(dest & ~(ACE_WINDOW_SIZE - 1), &regs->WinBase);
2913
2914 for (i = 0; i < (tsize / 4); i++) {
2915 writel(0, tdest + i*4);
2916 }
2917
2918 dest += tsize;
2919 size -= tsize;
2920 }
2921
2922 return;
2923}
2924
2925
2926/*
2927 * Download the firmware into the SRAM on the NIC
2928 *
2929 * This operation requires the NIC to be halted and is performed with
2930 * interrupts disabled and with the spinlock hold.
2931 */
ddfce6bb 2932static int __devinit ace_load_firmware(struct net_device *dev)
1da177e4
LT		 2933{
2934 struct ace_private *ap = netdev_priv(dev);
2935 struct ace_regs __iomem *regs = ap->regs;
2936
2937 if (!(readl(&regs->CpuCtrl) & CPU_HALTED)) {
2938 printk(KERN_ERR "%s: trying to download firmware while the "
2939 "CPU is running!\n", ap->name);
2940 return -EFAULT;
2941 }
2942
2943 /*
2944 * Do not try to clear more than 512KB or we end up seeing
2945 * funny things on NICs with only 512KB SRAM
2946 */
2947 ace_clear(regs, 0x2000, 0x80000-0x2000);
2948 if (ACE_IS_TIGON_I(ap)) {
2949 ace_copy(regs, tigonFwText, tigonFwTextAddr, tigonFwTextLen);
2950 ace_copy(regs, tigonFwData, tigonFwDataAddr, tigonFwDataLen);
2951 ace_copy(regs, tigonFwRodata, tigonFwRodataAddr,
2952 tigonFwRodataLen);
2953 ace_clear(regs, tigonFwBssAddr, tigonFwBssLen);
2954 ace_clear(regs, tigonFwSbssAddr, tigonFwSbssLen);
2955 }else if (ap->version == 2) {
2956 ace_clear(regs, tigon2FwBssAddr, tigon2FwBssLen);
2957 ace_clear(regs, tigon2FwSbssAddr, tigon2FwSbssLen);
2958 ace_copy(regs, tigon2FwText, tigon2FwTextAddr,tigon2FwTextLen);
2959 ace_copy(regs, tigon2FwRodata, tigon2FwRodataAddr,
2960 tigon2FwRodataLen);
2961 ace_copy(regs, tigon2FwData, tigon2FwDataAddr,tigon2FwDataLen);
2962 }
2963
2964 return 0;
2965}
2966
2967
2968/*
2969 * The eeprom on the AceNIC is an Atmel i2c EEPROM.
2970 *
2971 * Accessing the EEPROM is `interesting' to say the least - don't read
2972 * this code right after dinner.
2973 *
2974 * This is all about black magic and bit-banging the device .... I
2975 * wonder in what hospital they have put the guy who designed the i2c
2976 * specs.
2977 *
2978 * Oh yes, this is only the beginning!
2979 *
2980 * Thanks to Stevarino Webinski for helping tracking down the bugs in the
2981 * code i2c readout code by beta testing all my hacks.
2982 */
2983static void __devinit eeprom_start(struct ace_regs __iomem *regs)
2984{
2985 u32 local;
2986
2987 readl(&regs->LocalCtrl);
2988 udelay(ACE_SHORT_DELAY);
2989 local = readl(&regs->LocalCtrl);
2990 local |= EEPROM_DATA_OUT | EEPROM_WRITE_ENABLE;
2991 writel(local, &regs->LocalCtrl);
2992 readl(&regs->LocalCtrl);
2993 mb();
2994 udelay(ACE_SHORT_DELAY);
2995 local |= EEPROM_CLK_OUT;
2996 writel(local, &regs->LocalCtrl);
2997 readl(&regs->LocalCtrl);
2998 mb();
2999 udelay(ACE_SHORT_DELAY);
3000 local &= ~EEPROM_DATA_OUT;
3001 writel(local, &regs->LocalCtrl);
3002 readl(&regs->LocalCtrl);
3003 mb();
3004 udelay(ACE_SHORT_DELAY);
3005 local &= ~EEPROM_CLK_OUT;
3006 writel(local, &regs->LocalCtrl);
3007 readl(&regs->LocalCtrl);
3008 mb();
3009}
3010
3011
3012static void __devinit eeprom_prep(struct ace_regs __iomem *regs, u8 magic)
3013{
3014 short i;
3015 u32 local;
3016
3017 udelay(ACE_SHORT_DELAY);
3018 local = readl(&regs->LocalCtrl);
3019 local &= ~EEPROM_DATA_OUT;
3020 local |= EEPROM_WRITE_ENABLE;
3021 writel(local, &regs->LocalCtrl);
3022 readl(&regs->LocalCtrl);
3023 mb();
3024
3025 for (i = 0; i < 8; i++, magic <<= 1) {
3026 udelay(ACE_SHORT_DELAY);
6aa20a22 3027 if (magic & 0x80)
1da177e4
LT		 3028 local |= EEPROM_DATA_OUT;
3029 else
3030 local &= ~EEPROM_DATA_OUT;
3031 writel(local, &regs->LocalCtrl);
3032 readl(&regs->LocalCtrl);
3033 mb();
3034
3035 udelay(ACE_SHORT_DELAY);
3036 local |= EEPROM_CLK_OUT;
3037 writel(local, &regs->LocalCtrl);
3038 readl(&regs->LocalCtrl);
3039 mb();
3040 udelay(ACE_SHORT_DELAY);
3041 local &= ~(EEPROM_CLK_OUT | EEPROM_DATA_OUT);
3042 writel(local, &regs->LocalCtrl);
3043 readl(&regs->LocalCtrl);
3044 mb();
3045 }
3046}
3047
3048
3049static int __devinit eeprom_check_ack(struct ace_regs __iomem *regs)
3050{
3051 int state;
3052 u32 local;
3053
3054 local = readl(&regs->LocalCtrl);
3055 local &= ~EEPROM_WRITE_ENABLE;
3056 writel(local, &regs->LocalCtrl);
3057 readl(&regs->LocalCtrl);
3058 mb();
3059 udelay(ACE_LONG_DELAY);
3060 local |= EEPROM_CLK_OUT;
3061 writel(local, &regs->LocalCtrl);
3062 readl(&regs->LocalCtrl);
3063 mb();
3064 udelay(ACE_SHORT_DELAY);
3065 /* sample data in middle of high clk */
3066 state = (readl(&regs->LocalCtrl) & EEPROM_DATA_IN) != 0;
3067 udelay(ACE_SHORT_DELAY);
3068 mb();
3069 writel(readl(&regs->LocalCtrl) & ~EEPROM_CLK_OUT, &regs->LocalCtrl);
3070 readl(&regs->LocalCtrl);
3071 mb();
3072
3073 return state;
3074}
3075
3076
3077static void __devinit eeprom_stop(struct ace_regs __iomem *regs)
3078{
3079 u32 local;
3080
3081 udelay(ACE_SHORT_DELAY);
3082 local = readl(&regs->LocalCtrl);
3083 local |= EEPROM_WRITE_ENABLE;
3084 writel(local, &regs->LocalCtrl);
3085 readl(&regs->LocalCtrl);
3086 mb();
3087 udelay(ACE_SHORT_DELAY);
3088 local &= ~EEPROM_DATA_OUT;
3089 writel(local, &regs->LocalCtrl);
3090 readl(&regs->LocalCtrl);
3091 mb();
3092 udelay(ACE_SHORT_DELAY);
3093 local |= EEPROM_CLK_OUT;
3094 writel(local, &regs->LocalCtrl);
3095 readl(&regs->LocalCtrl);
3096 mb();
3097 udelay(ACE_SHORT_DELAY);
3098 local |= EEPROM_DATA_OUT;
3099 writel(local, &regs->LocalCtrl);
3100 readl(&regs->LocalCtrl);
3101 mb();
3102 udelay(ACE_LONG_DELAY);
3103 local &= ~EEPROM_CLK_OUT;
3104 writel(local, &regs->LocalCtrl);
3105 mb();
3106}
3107
3108
3109/*
3110 * Read a whole byte from the EEPROM.
3111 */
3112static int __devinit read_eeprom_byte(struct net_device *dev,
3113 unsigned long offset)
3114{
3115 struct ace_private *ap = netdev_priv(dev);
3116 struct ace_regs __iomem *regs = ap->regs;
3117 unsigned long flags;
3118 u32 local;
3119 int result = 0;
3120 short i;
3121
1da177e4
LT		 3122 /*
3123 * Don't take interrupts on this CPU will bit banging
3124 * the %#%#@$ I2C device
3125 */
3126 local_irq_save(flags);
3127
3128 eeprom_start(regs);
3129
3130 eeprom_prep(regs, EEPROM_WRITE_SELECT);
3131 if (eeprom_check_ack(regs)) {
3132 local_irq_restore(flags);
3133 printk(KERN_ERR "%s: Unable to sync eeprom\n", ap->name);
3134 result = -EIO;
3135 goto eeprom_read_error;
3136 }
3137
3138 eeprom_prep(regs, (offset >> 8) & 0xff);
3139 if (eeprom_check_ack(regs)) {
3140 local_irq_restore(flags);
3141 printk(KERN_ERR "%s: Unable to set address byte 0\n",
3142 ap->name);
3143 result = -EIO;
3144 goto eeprom_read_error;
3145 }
3146
3147 eeprom_prep(regs, offset & 0xff);
3148 if (eeprom_check_ack(regs)) {
3149 local_irq_restore(flags);
3150 printk(KERN_ERR "%s: Unable to set address byte 1\n",
3151 ap->name);
3152 result = -EIO;
3153 goto eeprom_read_error;
3154 }
3155
3156 eeprom_start(regs);
3157 eeprom_prep(regs, EEPROM_READ_SELECT);
3158 if (eeprom_check_ack(regs)) {
3159 local_irq_restore(flags);
3160 printk(KERN_ERR "%s: Unable to set READ_SELECT\n",
3161 ap->name);
3162 result = -EIO;
3163 goto eeprom_read_error;
3164 }
3165
3166 for (i = 0; i < 8; i++) {
3167 local = readl(&regs->LocalCtrl);
3168 local &= ~EEPROM_WRITE_ENABLE;
3169 writel(local, &regs->LocalCtrl);
3170 readl(&regs->LocalCtrl);
3171 udelay(ACE_LONG_DELAY);
3172 mb();
3173 local |= EEPROM_CLK_OUT;
3174 writel(local, &regs->LocalCtrl);
3175 readl(&regs->LocalCtrl);
3176 mb();
3177 udelay(ACE_SHORT_DELAY);
3178 /* sample data mid high clk */
3179 result = (result << 1) |
3180 ((readl(&regs->LocalCtrl) & EEPROM_DATA_IN) != 0);
3181 udelay(ACE_SHORT_DELAY);
3182 mb();
3183 local = readl(&regs->LocalCtrl);
3184 local &= ~EEPROM_CLK_OUT;
3185 writel(local, &regs->LocalCtrl);
3186 readl(&regs->LocalCtrl);
3187 udelay(ACE_SHORT_DELAY);
3188 mb();
3189 if (i == 7) {
3190 local |= EEPROM_WRITE_ENABLE;
3191 writel(local, &regs->LocalCtrl);
3192 readl(&regs->LocalCtrl);
3193 mb();
3194 udelay(ACE_SHORT_DELAY);
3195 }
3196 }
3197
3198 local |= EEPROM_DATA_OUT;
3199 writel(local, &regs->LocalCtrl);
3200 readl(&regs->LocalCtrl);
3201 mb();
3202 udelay(ACE_SHORT_DELAY);
3203 writel(readl(&regs->LocalCtrl) | EEPROM_CLK_OUT, &regs->LocalCtrl);
3204 readl(&regs->LocalCtrl);
3205 udelay(ACE_LONG_DELAY);
3206 writel(readl(&regs->LocalCtrl) & ~EEPROM_CLK_OUT, &regs->LocalCtrl);
3207 readl(&regs->LocalCtrl);
3208 mb();
3209 udelay(ACE_SHORT_DELAY);
3210 eeprom_stop(regs);
3211
3212 local_irq_restore(flags);
3213 out:
3214 return result;
3215
3216 eeprom_read_error:
3217 printk(KERN_ERR "%s: Unable to read eeprom byte 0x%02lx\n",
3218 ap->name, offset);
3219 goto out;
3220}
3221
3222
3223/*
3224 * Local variables:
3225 * compile-command: "gcc -D__SMP__ -D__KERNEL__ -DMODULE -I../../include -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer -pipe -fno-strength-reduce -DMODVERSIONS -include ../../include/linux/modversions.h -c -o acenic.o acenic.c"
3226 * End:
3227 */
kernel source for telekom puls (alcatel/mediatek)