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1da177e4 LT |
1 | /* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */ |
2 | /* | |
3 | Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com> | |
4 | ||
5 | Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c] | |
6 | Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c] | |
7 | Copyright 2001 Manfred Spraul [natsemi.c] | |
8 | Copyright 1999-2001 by Donald Becker. [natsemi.c] | |
9 | Written 1997-2001 by Donald Becker. [8139too.c] | |
10 | Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c] | |
11 | ||
12 | This software may be used and distributed according to the terms of | |
13 | the GNU General Public License (GPL), incorporated herein by reference. | |
14 | Drivers based on or derived from this code fall under the GPL and must | |
15 | retain the authorship, copyright and license notice. This file is not | |
16 | a complete program and may only be used when the entire operating | |
17 | system is licensed under the GPL. | |
18 | ||
19 | See the file COPYING in this distribution for more information. | |
20 | ||
21 | Contributors: | |
f3b197ac | 22 | |
1da177e4 LT |
23 | Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br> |
24 | PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br> | |
25 | LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br> | |
f3b197ac | 26 | |
1da177e4 LT |
27 | TODO: |
28 | * Test Tx checksumming thoroughly | |
29 | * Implement dev->tx_timeout | |
30 | ||
31 | Low priority TODO: | |
32 | * Complete reset on PciErr | |
33 | * Consider Rx interrupt mitigation using TimerIntr | |
34 | * Investigate using skb->priority with h/w VLAN priority | |
35 | * Investigate using High Priority Tx Queue with skb->priority | |
36 | * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error | |
37 | * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error | |
38 | * Implement Tx software interrupt mitigation via | |
39 | Tx descriptor bit | |
40 | * The real minimum of CP_MIN_MTU is 4 bytes. However, | |
41 | for this to be supported, one must(?) turn on packet padding. | |
42 | * Support external MII transceivers (patch available) | |
43 | ||
44 | NOTES: | |
45 | * TX checksumming is considered experimental. It is off by | |
46 | default, use ethtool to turn it on. | |
47 | ||
48 | */ | |
49 | ||
50 | #define DRV_NAME "8139cp" | |
d5b20697 | 51 | #define DRV_VERSION "1.3" |
1da177e4 LT |
52 | #define DRV_RELDATE "Mar 22, 2004" |
53 | ||
54 | ||
1da177e4 | 55 | #include <linux/module.h> |
e21ba282 | 56 | #include <linux/moduleparam.h> |
1da177e4 LT |
57 | #include <linux/kernel.h> |
58 | #include <linux/compiler.h> | |
59 | #include <linux/netdevice.h> | |
60 | #include <linux/etherdevice.h> | |
61 | #include <linux/init.h> | |
62 | #include <linux/pci.h> | |
8662d061 | 63 | #include <linux/dma-mapping.h> |
1da177e4 LT |
64 | #include <linux/delay.h> |
65 | #include <linux/ethtool.h> | |
66 | #include <linux/mii.h> | |
67 | #include <linux/if_vlan.h> | |
68 | #include <linux/crc32.h> | |
69 | #include <linux/in.h> | |
70 | #include <linux/ip.h> | |
71 | #include <linux/tcp.h> | |
72 | #include <linux/udp.h> | |
73 | #include <linux/cache.h> | |
74 | #include <asm/io.h> | |
75 | #include <asm/irq.h> | |
76 | #include <asm/uaccess.h> | |
77 | ||
78 | /* VLAN tagging feature enable/disable */ | |
79 | #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) | |
80 | #define CP_VLAN_TAG_USED 1 | |
81 | #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \ | |
82 | do { (tx_desc)->opts2 = (vlan_tag_value); } while (0) | |
83 | #else | |
84 | #define CP_VLAN_TAG_USED 0 | |
85 | #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \ | |
86 | do { (tx_desc)->opts2 = 0; } while (0) | |
87 | #endif | |
88 | ||
89 | /* These identify the driver base version and may not be removed. */ | |
90 | static char version[] = | |
91 | KERN_INFO DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n"; | |
92 | ||
93 | MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>"); | |
94 | MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver"); | |
a78d8927 | 95 | MODULE_VERSION(DRV_VERSION); |
1da177e4 LT |
96 | MODULE_LICENSE("GPL"); |
97 | ||
98 | static int debug = -1; | |
e21ba282 | 99 | module_param(debug, int, 0); |
1da177e4 LT |
100 | MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number"); |
101 | ||
102 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). | |
103 | The RTL chips use a 64 element hash table based on the Ethernet CRC. */ | |
104 | static int multicast_filter_limit = 32; | |
e21ba282 | 105 | module_param(multicast_filter_limit, int, 0); |
1da177e4 LT |
106 | MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses"); |
107 | ||
108 | #define PFX DRV_NAME ": " | |
109 | ||
1da177e4 LT |
110 | #define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \ |
111 | NETIF_MSG_PROBE | \ | |
112 | NETIF_MSG_LINK) | |
113 | #define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */ | |
114 | #define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */ | |
115 | #define CP_REGS_SIZE (0xff + 1) | |
116 | #define CP_REGS_VER 1 /* version 1 */ | |
117 | #define CP_RX_RING_SIZE 64 | |
118 | #define CP_TX_RING_SIZE 64 | |
119 | #define CP_RING_BYTES \ | |
120 | ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \ | |
121 | (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \ | |
122 | CP_STATS_SIZE) | |
123 | #define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1)) | |
124 | #define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1)) | |
125 | #define TX_BUFFS_AVAIL(CP) \ | |
126 | (((CP)->tx_tail <= (CP)->tx_head) ? \ | |
127 | (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \ | |
128 | (CP)->tx_tail - (CP)->tx_head - 1) | |
129 | ||
130 | #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/ | |
131 | #define RX_OFFSET 2 | |
132 | #define CP_INTERNAL_PHY 32 | |
133 | ||
134 | /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */ | |
135 | #define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */ | |
136 | #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */ | |
137 | #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ | |
138 | #define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */ | |
139 | ||
140 | /* Time in jiffies before concluding the transmitter is hung. */ | |
141 | #define TX_TIMEOUT (6*HZ) | |
142 | ||
143 | /* hardware minimum and maximum for a single frame's data payload */ | |
144 | #define CP_MIN_MTU 60 /* TODO: allow lower, but pad */ | |
145 | #define CP_MAX_MTU 4096 | |
146 | ||
147 | enum { | |
148 | /* NIC register offsets */ | |
149 | MAC0 = 0x00, /* Ethernet hardware address. */ | |
150 | MAR0 = 0x08, /* Multicast filter. */ | |
151 | StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */ | |
152 | TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */ | |
153 | HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */ | |
154 | Cmd = 0x37, /* Command register */ | |
155 | IntrMask = 0x3C, /* Interrupt mask */ | |
156 | IntrStatus = 0x3E, /* Interrupt status */ | |
157 | TxConfig = 0x40, /* Tx configuration */ | |
158 | ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */ | |
159 | RxConfig = 0x44, /* Rx configuration */ | |
160 | RxMissed = 0x4C, /* 24 bits valid, write clears */ | |
161 | Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */ | |
162 | Config1 = 0x52, /* Config1 */ | |
163 | Config3 = 0x59, /* Config3 */ | |
164 | Config4 = 0x5A, /* Config4 */ | |
165 | MultiIntr = 0x5C, /* Multiple interrupt select */ | |
166 | BasicModeCtrl = 0x62, /* MII BMCR */ | |
167 | BasicModeStatus = 0x64, /* MII BMSR */ | |
168 | NWayAdvert = 0x66, /* MII ADVERTISE */ | |
169 | NWayLPAR = 0x68, /* MII LPA */ | |
170 | NWayExpansion = 0x6A, /* MII Expansion */ | |
171 | Config5 = 0xD8, /* Config5 */ | |
172 | TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */ | |
173 | RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */ | |
174 | CpCmd = 0xE0, /* C+ Command register (C+ mode only) */ | |
175 | IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */ | |
176 | RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */ | |
177 | TxThresh = 0xEC, /* Early Tx threshold */ | |
178 | OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */ | |
179 | OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */ | |
180 | ||
181 | /* Tx and Rx status descriptors */ | |
182 | DescOwn = (1 << 31), /* Descriptor is owned by NIC */ | |
183 | RingEnd = (1 << 30), /* End of descriptor ring */ | |
184 | FirstFrag = (1 << 29), /* First segment of a packet */ | |
185 | LastFrag = (1 << 28), /* Final segment of a packet */ | |
fcec3456 JG |
186 | LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */ |
187 | MSSShift = 16, /* MSS value position */ | |
188 | MSSMask = 0xfff, /* MSS value: 11 bits */ | |
1da177e4 LT |
189 | TxError = (1 << 23), /* Tx error summary */ |
190 | RxError = (1 << 20), /* Rx error summary */ | |
191 | IPCS = (1 << 18), /* Calculate IP checksum */ | |
192 | UDPCS = (1 << 17), /* Calculate UDP/IP checksum */ | |
193 | TCPCS = (1 << 16), /* Calculate TCP/IP checksum */ | |
194 | TxVlanTag = (1 << 17), /* Add VLAN tag */ | |
195 | RxVlanTagged = (1 << 16), /* Rx VLAN tag available */ | |
196 | IPFail = (1 << 15), /* IP checksum failed */ | |
197 | UDPFail = (1 << 14), /* UDP/IP checksum failed */ | |
198 | TCPFail = (1 << 13), /* TCP/IP checksum failed */ | |
199 | NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */ | |
200 | PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */ | |
201 | PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */ | |
202 | RxProtoTCP = 1, | |
203 | RxProtoUDP = 2, | |
204 | RxProtoIP = 3, | |
205 | TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */ | |
206 | TxOWC = (1 << 22), /* Tx Out-of-window collision */ | |
207 | TxLinkFail = (1 << 21), /* Link failed during Tx of packet */ | |
208 | TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */ | |
209 | TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */ | |
210 | TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */ | |
211 | RxErrFrame = (1 << 27), /* Rx frame alignment error */ | |
212 | RxMcast = (1 << 26), /* Rx multicast packet rcv'd */ | |
213 | RxErrCRC = (1 << 18), /* Rx CRC error */ | |
214 | RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */ | |
215 | RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */ | |
216 | RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */ | |
217 | ||
218 | /* StatsAddr register */ | |
219 | DumpStats = (1 << 3), /* Begin stats dump */ | |
220 | ||
221 | /* RxConfig register */ | |
222 | RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */ | |
223 | RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */ | |
224 | AcceptErr = 0x20, /* Accept packets with CRC errors */ | |
225 | AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */ | |
226 | AcceptBroadcast = 0x08, /* Accept broadcast packets */ | |
227 | AcceptMulticast = 0x04, /* Accept multicast packets */ | |
228 | AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */ | |
229 | AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */ | |
230 | ||
231 | /* IntrMask / IntrStatus registers */ | |
232 | PciErr = (1 << 15), /* System error on the PCI bus */ | |
233 | TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */ | |
234 | LenChg = (1 << 13), /* Cable length change */ | |
235 | SWInt = (1 << 8), /* Software-requested interrupt */ | |
236 | TxEmpty = (1 << 7), /* No Tx descriptors available */ | |
237 | RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */ | |
238 | LinkChg = (1 << 5), /* Packet underrun, or link change */ | |
239 | RxEmpty = (1 << 4), /* No Rx descriptors available */ | |
240 | TxErr = (1 << 3), /* Tx error */ | |
241 | TxOK = (1 << 2), /* Tx packet sent */ | |
242 | RxErr = (1 << 1), /* Rx error */ | |
243 | RxOK = (1 << 0), /* Rx packet received */ | |
244 | IntrResvd = (1 << 10), /* reserved, according to RealTek engineers, | |
245 | but hardware likes to raise it */ | |
246 | ||
247 | IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty | | |
248 | RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK | | |
249 | RxErr | RxOK | IntrResvd, | |
250 | ||
251 | /* C mode command register */ | |
252 | CmdReset = (1 << 4), /* Enable to reset; self-clearing */ | |
253 | RxOn = (1 << 3), /* Rx mode enable */ | |
254 | TxOn = (1 << 2), /* Tx mode enable */ | |
255 | ||
256 | /* C+ mode command register */ | |
257 | RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */ | |
258 | RxChkSum = (1 << 5), /* Rx checksum offload enable */ | |
259 | PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */ | |
260 | PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */ | |
261 | CpRxOn = (1 << 1), /* Rx mode enable */ | |
262 | CpTxOn = (1 << 0), /* Tx mode enable */ | |
263 | ||
264 | /* Cfg9436 EEPROM control register */ | |
265 | Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */ | |
266 | Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */ | |
267 | ||
268 | /* TxConfig register */ | |
269 | IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */ | |
270 | TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ | |
271 | ||
272 | /* Early Tx Threshold register */ | |
273 | TxThreshMask = 0x3f, /* Mask bits 5-0 */ | |
274 | TxThreshMax = 2048, /* Max early Tx threshold */ | |
275 | ||
276 | /* Config1 register */ | |
277 | DriverLoaded = (1 << 5), /* Software marker, driver is loaded */ | |
278 | LWACT = (1 << 4), /* LWAKE active mode */ | |
279 | PMEnable = (1 << 0), /* Enable various PM features of chip */ | |
280 | ||
281 | /* Config3 register */ | |
282 | PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */ | |
283 | MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ | |
284 | LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ | |
285 | ||
286 | /* Config4 register */ | |
287 | LWPTN = (1 << 1), /* LWAKE Pattern */ | |
288 | LWPME = (1 << 4), /* LANWAKE vs PMEB */ | |
289 | ||
290 | /* Config5 register */ | |
291 | BWF = (1 << 6), /* Accept Broadcast wakeup frame */ | |
292 | MWF = (1 << 5), /* Accept Multicast wakeup frame */ | |
293 | UWF = (1 << 4), /* Accept Unicast wakeup frame */ | |
294 | LANWake = (1 << 1), /* Enable LANWake signal */ | |
295 | PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ | |
296 | ||
297 | cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty, | |
298 | cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr, | |
299 | cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask, | |
300 | }; | |
301 | ||
302 | static const unsigned int cp_rx_config = | |
303 | (RX_FIFO_THRESH << RxCfgFIFOShift) | | |
304 | (RX_DMA_BURST << RxCfgDMAShift); | |
305 | ||
306 | struct cp_desc { | |
307 | u32 opts1; | |
308 | u32 opts2; | |
309 | u64 addr; | |
310 | }; | |
311 | ||
1da177e4 LT |
312 | struct cp_dma_stats { |
313 | u64 tx_ok; | |
314 | u64 rx_ok; | |
315 | u64 tx_err; | |
316 | u32 rx_err; | |
317 | u16 rx_fifo; | |
318 | u16 frame_align; | |
319 | u32 tx_ok_1col; | |
320 | u32 tx_ok_mcol; | |
321 | u64 rx_ok_phys; | |
322 | u64 rx_ok_bcast; | |
323 | u32 rx_ok_mcast; | |
324 | u16 tx_abort; | |
325 | u16 tx_underrun; | |
326 | } __attribute__((packed)); | |
327 | ||
328 | struct cp_extra_stats { | |
329 | unsigned long rx_frags; | |
330 | }; | |
331 | ||
332 | struct cp_private { | |
333 | void __iomem *regs; | |
334 | struct net_device *dev; | |
335 | spinlock_t lock; | |
336 | u32 msg_enable; | |
337 | ||
338 | struct pci_dev *pdev; | |
339 | u32 rx_config; | |
340 | u16 cpcmd; | |
341 | ||
342 | struct net_device_stats net_stats; | |
343 | struct cp_extra_stats cp_stats; | |
1da177e4 | 344 | |
d03d376d FR |
345 | unsigned rx_head ____cacheline_aligned; |
346 | unsigned rx_tail; | |
1da177e4 | 347 | struct cp_desc *rx_ring; |
0ba894d4 | 348 | struct sk_buff *rx_skb[CP_RX_RING_SIZE]; |
1da177e4 LT |
349 | |
350 | unsigned tx_head ____cacheline_aligned; | |
351 | unsigned tx_tail; | |
1da177e4 | 352 | struct cp_desc *tx_ring; |
48907e39 | 353 | struct sk_buff *tx_skb[CP_TX_RING_SIZE]; |
d03d376d FR |
354 | |
355 | unsigned rx_buf_sz; | |
356 | unsigned wol_enabled : 1; /* Is Wake-on-LAN enabled? */ | |
1da177e4 LT |
357 | |
358 | #if CP_VLAN_TAG_USED | |
359 | struct vlan_group *vlgrp; | |
360 | #endif | |
d03d376d | 361 | dma_addr_t ring_dma; |
1da177e4 LT |
362 | |
363 | struct mii_if_info mii_if; | |
364 | }; | |
365 | ||
366 | #define cpr8(reg) readb(cp->regs + (reg)) | |
367 | #define cpr16(reg) readw(cp->regs + (reg)) | |
368 | #define cpr32(reg) readl(cp->regs + (reg)) | |
369 | #define cpw8(reg,val) writeb((val), cp->regs + (reg)) | |
370 | #define cpw16(reg,val) writew((val), cp->regs + (reg)) | |
371 | #define cpw32(reg,val) writel((val), cp->regs + (reg)) | |
372 | #define cpw8_f(reg,val) do { \ | |
373 | writeb((val), cp->regs + (reg)); \ | |
374 | readb(cp->regs + (reg)); \ | |
375 | } while (0) | |
376 | #define cpw16_f(reg,val) do { \ | |
377 | writew((val), cp->regs + (reg)); \ | |
378 | readw(cp->regs + (reg)); \ | |
379 | } while (0) | |
380 | #define cpw32_f(reg,val) do { \ | |
381 | writel((val), cp->regs + (reg)); \ | |
382 | readl(cp->regs + (reg)); \ | |
383 | } while (0) | |
384 | ||
385 | ||
386 | static void __cp_set_rx_mode (struct net_device *dev); | |
387 | static void cp_tx (struct cp_private *cp); | |
388 | static void cp_clean_rings (struct cp_private *cp); | |
7502cd10 SK |
389 | #ifdef CONFIG_NET_POLL_CONTROLLER |
390 | static void cp_poll_controller(struct net_device *dev); | |
391 | #endif | |
722fdb33 PC |
392 | static int cp_get_eeprom_len(struct net_device *dev); |
393 | static int cp_get_eeprom(struct net_device *dev, | |
394 | struct ethtool_eeprom *eeprom, u8 *data); | |
395 | static int cp_set_eeprom(struct net_device *dev, | |
396 | struct ethtool_eeprom *eeprom, u8 *data); | |
1da177e4 LT |
397 | |
398 | static struct pci_device_id cp_pci_tbl[] = { | |
cccb20d3 FR |
399 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139), }, |
400 | { PCI_DEVICE(PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322), }, | |
1da177e4 LT |
401 | { }, |
402 | }; | |
403 | MODULE_DEVICE_TABLE(pci, cp_pci_tbl); | |
404 | ||
405 | static struct { | |
406 | const char str[ETH_GSTRING_LEN]; | |
407 | } ethtool_stats_keys[] = { | |
408 | { "tx_ok" }, | |
409 | { "rx_ok" }, | |
410 | { "tx_err" }, | |
411 | { "rx_err" }, | |
412 | { "rx_fifo" }, | |
413 | { "frame_align" }, | |
414 | { "tx_ok_1col" }, | |
415 | { "tx_ok_mcol" }, | |
416 | { "rx_ok_phys" }, | |
417 | { "rx_ok_bcast" }, | |
418 | { "rx_ok_mcast" }, | |
419 | { "tx_abort" }, | |
420 | { "tx_underrun" }, | |
421 | { "rx_frags" }, | |
422 | }; | |
423 | ||
424 | ||
425 | #if CP_VLAN_TAG_USED | |
426 | static void cp_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) | |
427 | { | |
428 | struct cp_private *cp = netdev_priv(dev); | |
429 | unsigned long flags; | |
430 | ||
431 | spin_lock_irqsave(&cp->lock, flags); | |
432 | cp->vlgrp = grp; | |
7b332244 SH |
433 | if (grp) |
434 | cp->cpcmd |= RxVlanOn; | |
435 | else | |
436 | cp->cpcmd &= ~RxVlanOn; | |
1da177e4 | 437 | |
1da177e4 | 438 | cpw16(CpCmd, cp->cpcmd); |
1da177e4 LT |
439 | spin_unlock_irqrestore(&cp->lock, flags); |
440 | } | |
441 | #endif /* CP_VLAN_TAG_USED */ | |
442 | ||
443 | static inline void cp_set_rxbufsize (struct cp_private *cp) | |
444 | { | |
445 | unsigned int mtu = cp->dev->mtu; | |
f3b197ac | 446 | |
1da177e4 LT |
447 | if (mtu > ETH_DATA_LEN) |
448 | /* MTU + ethernet header + FCS + optional VLAN tag */ | |
449 | cp->rx_buf_sz = mtu + ETH_HLEN + 8; | |
450 | else | |
451 | cp->rx_buf_sz = PKT_BUF_SZ; | |
452 | } | |
453 | ||
454 | static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb, | |
455 | struct cp_desc *desc) | |
456 | { | |
457 | skb->protocol = eth_type_trans (skb, cp->dev); | |
458 | ||
459 | cp->net_stats.rx_packets++; | |
460 | cp->net_stats.rx_bytes += skb->len; | |
461 | cp->dev->last_rx = jiffies; | |
462 | ||
463 | #if CP_VLAN_TAG_USED | |
464 | if (cp->vlgrp && (desc->opts2 & RxVlanTagged)) { | |
465 | vlan_hwaccel_receive_skb(skb, cp->vlgrp, | |
466 | be16_to_cpu(desc->opts2 & 0xffff)); | |
467 | } else | |
468 | #endif | |
469 | netif_receive_skb(skb); | |
470 | } | |
471 | ||
472 | static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail, | |
473 | u32 status, u32 len) | |
474 | { | |
475 | if (netif_msg_rx_err (cp)) | |
476 | printk (KERN_DEBUG | |
477 | "%s: rx err, slot %d status 0x%x len %d\n", | |
478 | cp->dev->name, rx_tail, status, len); | |
479 | cp->net_stats.rx_errors++; | |
480 | if (status & RxErrFrame) | |
481 | cp->net_stats.rx_frame_errors++; | |
482 | if (status & RxErrCRC) | |
483 | cp->net_stats.rx_crc_errors++; | |
484 | if ((status & RxErrRunt) || (status & RxErrLong)) | |
485 | cp->net_stats.rx_length_errors++; | |
486 | if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) | |
487 | cp->net_stats.rx_length_errors++; | |
488 | if (status & RxErrFIFO) | |
489 | cp->net_stats.rx_fifo_errors++; | |
490 | } | |
491 | ||
492 | static inline unsigned int cp_rx_csum_ok (u32 status) | |
493 | { | |
494 | unsigned int protocol = (status >> 16) & 0x3; | |
f3b197ac | 495 | |
1da177e4 LT |
496 | if (likely((protocol == RxProtoTCP) && (!(status & TCPFail)))) |
497 | return 1; | |
498 | else if ((protocol == RxProtoUDP) && (!(status & UDPFail))) | |
499 | return 1; | |
500 | else if ((protocol == RxProtoIP) && (!(status & IPFail))) | |
501 | return 1; | |
502 | return 0; | |
503 | } | |
504 | ||
505 | static int cp_rx_poll (struct net_device *dev, int *budget) | |
506 | { | |
507 | struct cp_private *cp = netdev_priv(dev); | |
508 | unsigned rx_tail = cp->rx_tail; | |
509 | unsigned rx_work = dev->quota; | |
510 | unsigned rx; | |
511 | ||
512 | rx_status_loop: | |
513 | rx = 0; | |
514 | cpw16(IntrStatus, cp_rx_intr_mask); | |
515 | ||
516 | while (1) { | |
517 | u32 status, len; | |
518 | dma_addr_t mapping; | |
519 | struct sk_buff *skb, *new_skb; | |
520 | struct cp_desc *desc; | |
521 | unsigned buflen; | |
522 | ||
0ba894d4 | 523 | skb = cp->rx_skb[rx_tail]; |
5d9428de | 524 | BUG_ON(!skb); |
1da177e4 LT |
525 | |
526 | desc = &cp->rx_ring[rx_tail]; | |
527 | status = le32_to_cpu(desc->opts1); | |
528 | if (status & DescOwn) | |
529 | break; | |
530 | ||
531 | len = (status & 0x1fff) - 4; | |
3598b57b | 532 | mapping = le64_to_cpu(desc->addr); |
1da177e4 LT |
533 | |
534 | if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) { | |
535 | /* we don't support incoming fragmented frames. | |
536 | * instead, we attempt to ensure that the | |
537 | * pre-allocated RX skbs are properly sized such | |
538 | * that RX fragments are never encountered | |
539 | */ | |
540 | cp_rx_err_acct(cp, rx_tail, status, len); | |
541 | cp->net_stats.rx_dropped++; | |
542 | cp->cp_stats.rx_frags++; | |
543 | goto rx_next; | |
544 | } | |
545 | ||
546 | if (status & (RxError | RxErrFIFO)) { | |
547 | cp_rx_err_acct(cp, rx_tail, status, len); | |
548 | goto rx_next; | |
549 | } | |
550 | ||
551 | if (netif_msg_rx_status(cp)) | |
552 | printk(KERN_DEBUG "%s: rx slot %d status 0x%x len %d\n", | |
c48e9399 | 553 | dev->name, rx_tail, status, len); |
1da177e4 LT |
554 | |
555 | buflen = cp->rx_buf_sz + RX_OFFSET; | |
556 | new_skb = dev_alloc_skb (buflen); | |
557 | if (!new_skb) { | |
558 | cp->net_stats.rx_dropped++; | |
559 | goto rx_next; | |
560 | } | |
561 | ||
562 | skb_reserve(new_skb, RX_OFFSET); | |
1da177e4 LT |
563 | |
564 | pci_unmap_single(cp->pdev, mapping, | |
565 | buflen, PCI_DMA_FROMDEVICE); | |
566 | ||
567 | /* Handle checksum offloading for incoming packets. */ | |
568 | if (cp_rx_csum_ok(status)) | |
569 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
570 | else | |
571 | skb->ip_summed = CHECKSUM_NONE; | |
572 | ||
573 | skb_put(skb, len); | |
574 | ||
3598b57b FR |
575 | mapping = pci_map_single(cp->pdev, new_skb->data, buflen, |
576 | PCI_DMA_FROMDEVICE); | |
0ba894d4 | 577 | cp->rx_skb[rx_tail] = new_skb; |
1da177e4 LT |
578 | |
579 | cp_rx_skb(cp, skb, desc); | |
580 | rx++; | |
581 | ||
582 | rx_next: | |
583 | cp->rx_ring[rx_tail].opts2 = 0; | |
584 | cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping); | |
585 | if (rx_tail == (CP_RX_RING_SIZE - 1)) | |
586 | desc->opts1 = cpu_to_le32(DescOwn | RingEnd | | |
587 | cp->rx_buf_sz); | |
588 | else | |
589 | desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz); | |
590 | rx_tail = NEXT_RX(rx_tail); | |
591 | ||
592 | if (!rx_work--) | |
593 | break; | |
594 | } | |
595 | ||
596 | cp->rx_tail = rx_tail; | |
597 | ||
598 | dev->quota -= rx; | |
599 | *budget -= rx; | |
600 | ||
601 | /* if we did not reach work limit, then we're done with | |
602 | * this round of polling | |
603 | */ | |
604 | if (rx_work) { | |
d15e9c4d FR |
605 | unsigned long flags; |
606 | ||
1da177e4 LT |
607 | if (cpr16(IntrStatus) & cp_rx_intr_mask) |
608 | goto rx_status_loop; | |
609 | ||
d15e9c4d | 610 | local_irq_save(flags); |
1da177e4 LT |
611 | cpw16_f(IntrMask, cp_intr_mask); |
612 | __netif_rx_complete(dev); | |
d15e9c4d | 613 | local_irq_restore(flags); |
1da177e4 LT |
614 | |
615 | return 0; /* done */ | |
616 | } | |
617 | ||
618 | return 1; /* not done */ | |
619 | } | |
620 | ||
7d12e780 | 621 | static irqreturn_t cp_interrupt (int irq, void *dev_instance) |
1da177e4 LT |
622 | { |
623 | struct net_device *dev = dev_instance; | |
624 | struct cp_private *cp; | |
625 | u16 status; | |
626 | ||
627 | if (unlikely(dev == NULL)) | |
628 | return IRQ_NONE; | |
629 | cp = netdev_priv(dev); | |
630 | ||
631 | status = cpr16(IntrStatus); | |
632 | if (!status || (status == 0xFFFF)) | |
633 | return IRQ_NONE; | |
634 | ||
635 | if (netif_msg_intr(cp)) | |
636 | printk(KERN_DEBUG "%s: intr, status %04x cmd %02x cpcmd %04x\n", | |
637 | dev->name, status, cpr8(Cmd), cpr16(CpCmd)); | |
638 | ||
639 | cpw16(IntrStatus, status & ~cp_rx_intr_mask); | |
640 | ||
641 | spin_lock(&cp->lock); | |
642 | ||
643 | /* close possible race's with dev_close */ | |
644 | if (unlikely(!netif_running(dev))) { | |
645 | cpw16(IntrMask, 0); | |
646 | spin_unlock(&cp->lock); | |
647 | return IRQ_HANDLED; | |
648 | } | |
649 | ||
650 | if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr)) | |
651 | if (netif_rx_schedule_prep(dev)) { | |
652 | cpw16_f(IntrMask, cp_norx_intr_mask); | |
653 | __netif_rx_schedule(dev); | |
654 | } | |
655 | ||
656 | if (status & (TxOK | TxErr | TxEmpty | SWInt)) | |
657 | cp_tx(cp); | |
658 | if (status & LinkChg) | |
2501f843 | 659 | mii_check_media(&cp->mii_if, netif_msg_link(cp), false); |
1da177e4 LT |
660 | |
661 | spin_unlock(&cp->lock); | |
662 | ||
663 | if (status & PciErr) { | |
664 | u16 pci_status; | |
665 | ||
666 | pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status); | |
667 | pci_write_config_word(cp->pdev, PCI_STATUS, pci_status); | |
668 | printk(KERN_ERR "%s: PCI bus error, status=%04x, PCI status=%04x\n", | |
669 | dev->name, status, pci_status); | |
670 | ||
671 | /* TODO: reset hardware */ | |
672 | } | |
673 | ||
674 | return IRQ_HANDLED; | |
675 | } | |
676 | ||
7502cd10 SK |
677 | #ifdef CONFIG_NET_POLL_CONTROLLER |
678 | /* | |
679 | * Polling receive - used by netconsole and other diagnostic tools | |
680 | * to allow network i/o with interrupts disabled. | |
681 | */ | |
682 | static void cp_poll_controller(struct net_device *dev) | |
683 | { | |
684 | disable_irq(dev->irq); | |
7d12e780 | 685 | cp_interrupt(dev->irq, dev); |
7502cd10 SK |
686 | enable_irq(dev->irq); |
687 | } | |
688 | #endif | |
689 | ||
1da177e4 LT |
690 | static void cp_tx (struct cp_private *cp) |
691 | { | |
692 | unsigned tx_head = cp->tx_head; | |
693 | unsigned tx_tail = cp->tx_tail; | |
694 | ||
695 | while (tx_tail != tx_head) { | |
3598b57b | 696 | struct cp_desc *txd = cp->tx_ring + tx_tail; |
1da177e4 LT |
697 | struct sk_buff *skb; |
698 | u32 status; | |
699 | ||
700 | rmb(); | |
3598b57b | 701 | status = le32_to_cpu(txd->opts1); |
1da177e4 LT |
702 | if (status & DescOwn) |
703 | break; | |
704 | ||
48907e39 | 705 | skb = cp->tx_skb[tx_tail]; |
5d9428de | 706 | BUG_ON(!skb); |
1da177e4 | 707 | |
3598b57b | 708 | pci_unmap_single(cp->pdev, le64_to_cpu(txd->addr), |
48907e39 FR |
709 | le32_to_cpu(txd->opts1) & 0xffff, |
710 | PCI_DMA_TODEVICE); | |
1da177e4 LT |
711 | |
712 | if (status & LastFrag) { | |
713 | if (status & (TxError | TxFIFOUnder)) { | |
714 | if (netif_msg_tx_err(cp)) | |
715 | printk(KERN_DEBUG "%s: tx err, status 0x%x\n", | |
716 | cp->dev->name, status); | |
717 | cp->net_stats.tx_errors++; | |
718 | if (status & TxOWC) | |
719 | cp->net_stats.tx_window_errors++; | |
720 | if (status & TxMaxCol) | |
721 | cp->net_stats.tx_aborted_errors++; | |
722 | if (status & TxLinkFail) | |
723 | cp->net_stats.tx_carrier_errors++; | |
724 | if (status & TxFIFOUnder) | |
725 | cp->net_stats.tx_fifo_errors++; | |
726 | } else { | |
727 | cp->net_stats.collisions += | |
728 | ((status >> TxColCntShift) & TxColCntMask); | |
729 | cp->net_stats.tx_packets++; | |
730 | cp->net_stats.tx_bytes += skb->len; | |
731 | if (netif_msg_tx_done(cp)) | |
732 | printk(KERN_DEBUG "%s: tx done, slot %d\n", cp->dev->name, tx_tail); | |
733 | } | |
734 | dev_kfree_skb_irq(skb); | |
735 | } | |
736 | ||
48907e39 | 737 | cp->tx_skb[tx_tail] = NULL; |
1da177e4 LT |
738 | |
739 | tx_tail = NEXT_TX(tx_tail); | |
740 | } | |
741 | ||
742 | cp->tx_tail = tx_tail; | |
743 | ||
744 | if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1)) | |
745 | netif_wake_queue(cp->dev); | |
746 | } | |
747 | ||
748 | static int cp_start_xmit (struct sk_buff *skb, struct net_device *dev) | |
749 | { | |
750 | struct cp_private *cp = netdev_priv(dev); | |
751 | unsigned entry; | |
fcec3456 | 752 | u32 eor, flags; |
553af567 | 753 | unsigned long intr_flags; |
1da177e4 LT |
754 | #if CP_VLAN_TAG_USED |
755 | u32 vlan_tag = 0; | |
756 | #endif | |
fcec3456 | 757 | int mss = 0; |
1da177e4 | 758 | |
553af567 | 759 | spin_lock_irqsave(&cp->lock, intr_flags); |
1da177e4 LT |
760 | |
761 | /* This is a hard error, log it. */ | |
762 | if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) { | |
763 | netif_stop_queue(dev); | |
553af567 | 764 | spin_unlock_irqrestore(&cp->lock, intr_flags); |
1da177e4 LT |
765 | printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n", |
766 | dev->name); | |
767 | return 1; | |
768 | } | |
769 | ||
770 | #if CP_VLAN_TAG_USED | |
771 | if (cp->vlgrp && vlan_tx_tag_present(skb)) | |
772 | vlan_tag = TxVlanTag | cpu_to_be16(vlan_tx_tag_get(skb)); | |
773 | #endif | |
774 | ||
775 | entry = cp->tx_head; | |
776 | eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0; | |
fcec3456 | 777 | if (dev->features & NETIF_F_TSO) |
7967168c | 778 | mss = skb_shinfo(skb)->gso_size; |
fcec3456 | 779 | |
1da177e4 LT |
780 | if (skb_shinfo(skb)->nr_frags == 0) { |
781 | struct cp_desc *txd = &cp->tx_ring[entry]; | |
782 | u32 len; | |
783 | dma_addr_t mapping; | |
784 | ||
785 | len = skb->len; | |
786 | mapping = pci_map_single(cp->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
787 | CP_VLAN_TX_TAG(txd, vlan_tag); | |
788 | txd->addr = cpu_to_le64(mapping); | |
789 | wmb(); | |
790 | ||
fcec3456 JG |
791 | flags = eor | len | DescOwn | FirstFrag | LastFrag; |
792 | ||
793 | if (mss) | |
794 | flags |= LargeSend | ((mss & MSSMask) << MSSShift); | |
84fa7933 | 795 | else if (skb->ip_summed == CHECKSUM_PARTIAL) { |
eddc9ec5 | 796 | const struct iphdr *ip = ip_hdr(skb); |
1da177e4 | 797 | if (ip->protocol == IPPROTO_TCP) |
fcec3456 | 798 | flags |= IPCS | TCPCS; |
1da177e4 | 799 | else if (ip->protocol == IPPROTO_UDP) |
fcec3456 | 800 | flags |= IPCS | UDPCS; |
1da177e4 | 801 | else |
5734418d | 802 | WARN_ON(1); /* we need a WARN() */ |
fcec3456 JG |
803 | } |
804 | ||
805 | txd->opts1 = cpu_to_le32(flags); | |
1da177e4 LT |
806 | wmb(); |
807 | ||
48907e39 | 808 | cp->tx_skb[entry] = skb; |
1da177e4 LT |
809 | entry = NEXT_TX(entry); |
810 | } else { | |
811 | struct cp_desc *txd; | |
812 | u32 first_len, first_eor; | |
813 | dma_addr_t first_mapping; | |
814 | int frag, first_entry = entry; | |
eddc9ec5 | 815 | const struct iphdr *ip = ip_hdr(skb); |
1da177e4 LT |
816 | |
817 | /* We must give this initial chunk to the device last. | |
818 | * Otherwise we could race with the device. | |
819 | */ | |
820 | first_eor = eor; | |
821 | first_len = skb_headlen(skb); | |
822 | first_mapping = pci_map_single(cp->pdev, skb->data, | |
823 | first_len, PCI_DMA_TODEVICE); | |
48907e39 | 824 | cp->tx_skb[entry] = skb; |
1da177e4 LT |
825 | entry = NEXT_TX(entry); |
826 | ||
827 | for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { | |
828 | skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag]; | |
829 | u32 len; | |
830 | u32 ctrl; | |
831 | dma_addr_t mapping; | |
832 | ||
833 | len = this_frag->size; | |
834 | mapping = pci_map_single(cp->pdev, | |
835 | ((void *) page_address(this_frag->page) + | |
836 | this_frag->page_offset), | |
837 | len, PCI_DMA_TODEVICE); | |
838 | eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0; | |
839 | ||
fcec3456 JG |
840 | ctrl = eor | len | DescOwn; |
841 | ||
842 | if (mss) | |
843 | ctrl |= LargeSend | | |
844 | ((mss & MSSMask) << MSSShift); | |
84fa7933 | 845 | else if (skb->ip_summed == CHECKSUM_PARTIAL) { |
1da177e4 | 846 | if (ip->protocol == IPPROTO_TCP) |
fcec3456 | 847 | ctrl |= IPCS | TCPCS; |
1da177e4 | 848 | else if (ip->protocol == IPPROTO_UDP) |
fcec3456 | 849 | ctrl |= IPCS | UDPCS; |
1da177e4 LT |
850 | else |
851 | BUG(); | |
fcec3456 | 852 | } |
1da177e4 LT |
853 | |
854 | if (frag == skb_shinfo(skb)->nr_frags - 1) | |
855 | ctrl |= LastFrag; | |
856 | ||
857 | txd = &cp->tx_ring[entry]; | |
858 | CP_VLAN_TX_TAG(txd, vlan_tag); | |
859 | txd->addr = cpu_to_le64(mapping); | |
860 | wmb(); | |
861 | ||
862 | txd->opts1 = cpu_to_le32(ctrl); | |
863 | wmb(); | |
864 | ||
48907e39 | 865 | cp->tx_skb[entry] = skb; |
1da177e4 LT |
866 | entry = NEXT_TX(entry); |
867 | } | |
868 | ||
869 | txd = &cp->tx_ring[first_entry]; | |
870 | CP_VLAN_TX_TAG(txd, vlan_tag); | |
871 | txd->addr = cpu_to_le64(first_mapping); | |
872 | wmb(); | |
873 | ||
84fa7933 | 874 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
1da177e4 LT |
875 | if (ip->protocol == IPPROTO_TCP) |
876 | txd->opts1 = cpu_to_le32(first_eor | first_len | | |
877 | FirstFrag | DescOwn | | |
878 | IPCS | TCPCS); | |
879 | else if (ip->protocol == IPPROTO_UDP) | |
880 | txd->opts1 = cpu_to_le32(first_eor | first_len | | |
881 | FirstFrag | DescOwn | | |
882 | IPCS | UDPCS); | |
883 | else | |
884 | BUG(); | |
885 | } else | |
886 | txd->opts1 = cpu_to_le32(first_eor | first_len | | |
887 | FirstFrag | DescOwn); | |
888 | wmb(); | |
889 | } | |
890 | cp->tx_head = entry; | |
891 | if (netif_msg_tx_queued(cp)) | |
892 | printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n", | |
893 | dev->name, entry, skb->len); | |
894 | if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1)) | |
895 | netif_stop_queue(dev); | |
896 | ||
553af567 | 897 | spin_unlock_irqrestore(&cp->lock, intr_flags); |
1da177e4 LT |
898 | |
899 | cpw8(TxPoll, NormalTxPoll); | |
900 | dev->trans_start = jiffies; | |
901 | ||
902 | return 0; | |
903 | } | |
904 | ||
905 | /* Set or clear the multicast filter for this adaptor. | |
906 | This routine is not state sensitive and need not be SMP locked. */ | |
907 | ||
908 | static void __cp_set_rx_mode (struct net_device *dev) | |
909 | { | |
910 | struct cp_private *cp = netdev_priv(dev); | |
911 | u32 mc_filter[2]; /* Multicast hash filter */ | |
912 | int i, rx_mode; | |
913 | u32 tmp; | |
914 | ||
915 | /* Note: do not reorder, GCC is clever about common statements. */ | |
916 | if (dev->flags & IFF_PROMISC) { | |
917 | /* Unconditionally log net taps. */ | |
1da177e4 LT |
918 | rx_mode = |
919 | AcceptBroadcast | AcceptMulticast | AcceptMyPhys | | |
920 | AcceptAllPhys; | |
921 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
922 | } else if ((dev->mc_count > multicast_filter_limit) | |
923 | || (dev->flags & IFF_ALLMULTI)) { | |
924 | /* Too many to filter perfectly -- accept all multicasts. */ | |
925 | rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; | |
926 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
927 | } else { | |
928 | struct dev_mc_list *mclist; | |
929 | rx_mode = AcceptBroadcast | AcceptMyPhys; | |
930 | mc_filter[1] = mc_filter[0] = 0; | |
931 | for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; | |
932 | i++, mclist = mclist->next) { | |
933 | int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26; | |
934 | ||
935 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); | |
936 | rx_mode |= AcceptMulticast; | |
937 | } | |
938 | } | |
939 | ||
940 | /* We can safely update without stopping the chip. */ | |
941 | tmp = cp_rx_config | rx_mode; | |
942 | if (cp->rx_config != tmp) { | |
943 | cpw32_f (RxConfig, tmp); | |
944 | cp->rx_config = tmp; | |
945 | } | |
946 | cpw32_f (MAR0 + 0, mc_filter[0]); | |
947 | cpw32_f (MAR0 + 4, mc_filter[1]); | |
948 | } | |
949 | ||
950 | static void cp_set_rx_mode (struct net_device *dev) | |
951 | { | |
952 | unsigned long flags; | |
953 | struct cp_private *cp = netdev_priv(dev); | |
954 | ||
955 | spin_lock_irqsave (&cp->lock, flags); | |
956 | __cp_set_rx_mode(dev); | |
957 | spin_unlock_irqrestore (&cp->lock, flags); | |
958 | } | |
959 | ||
960 | static void __cp_get_stats(struct cp_private *cp) | |
961 | { | |
962 | /* only lower 24 bits valid; write any value to clear */ | |
963 | cp->net_stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff); | |
964 | cpw32 (RxMissed, 0); | |
965 | } | |
966 | ||
967 | static struct net_device_stats *cp_get_stats(struct net_device *dev) | |
968 | { | |
969 | struct cp_private *cp = netdev_priv(dev); | |
970 | unsigned long flags; | |
971 | ||
972 | /* The chip only need report frame silently dropped. */ | |
973 | spin_lock_irqsave(&cp->lock, flags); | |
974 | if (netif_running(dev) && netif_device_present(dev)) | |
975 | __cp_get_stats(cp); | |
976 | spin_unlock_irqrestore(&cp->lock, flags); | |
977 | ||
978 | return &cp->net_stats; | |
979 | } | |
980 | ||
981 | static void cp_stop_hw (struct cp_private *cp) | |
982 | { | |
983 | cpw16(IntrStatus, ~(cpr16(IntrStatus))); | |
984 | cpw16_f(IntrMask, 0); | |
985 | cpw8(Cmd, 0); | |
986 | cpw16_f(CpCmd, 0); | |
987 | cpw16_f(IntrStatus, ~(cpr16(IntrStatus))); | |
988 | ||
989 | cp->rx_tail = 0; | |
990 | cp->tx_head = cp->tx_tail = 0; | |
991 | } | |
992 | ||
993 | static void cp_reset_hw (struct cp_private *cp) | |
994 | { | |
995 | unsigned work = 1000; | |
996 | ||
997 | cpw8(Cmd, CmdReset); | |
998 | ||
999 | while (work--) { | |
1000 | if (!(cpr8(Cmd) & CmdReset)) | |
1001 | return; | |
1002 | ||
3173c890 | 1003 | schedule_timeout_uninterruptible(10); |
1da177e4 LT |
1004 | } |
1005 | ||
1006 | printk(KERN_ERR "%s: hardware reset timeout\n", cp->dev->name); | |
1007 | } | |
1008 | ||
1009 | static inline void cp_start_hw (struct cp_private *cp) | |
1010 | { | |
1011 | cpw16(CpCmd, cp->cpcmd); | |
1012 | cpw8(Cmd, RxOn | TxOn); | |
1013 | } | |
1014 | ||
1015 | static void cp_init_hw (struct cp_private *cp) | |
1016 | { | |
1017 | struct net_device *dev = cp->dev; | |
1018 | dma_addr_t ring_dma; | |
1019 | ||
1020 | cp_reset_hw(cp); | |
1021 | ||
1022 | cpw8_f (Cfg9346, Cfg9346_Unlock); | |
1023 | ||
1024 | /* Restore our idea of the MAC address. */ | |
1025 | cpw32_f (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0))); | |
1026 | cpw32_f (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4))); | |
1027 | ||
1028 | cp_start_hw(cp); | |
1029 | cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */ | |
1030 | ||
1031 | __cp_set_rx_mode(dev); | |
1032 | cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift)); | |
1033 | ||
1034 | cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable); | |
1035 | /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */ | |
1036 | cpw8(Config3, PARMEnable); | |
1037 | cp->wol_enabled = 0; | |
1038 | ||
f3b197ac | 1039 | cpw8(Config5, cpr8(Config5) & PMEStatus); |
1da177e4 LT |
1040 | |
1041 | cpw32_f(HiTxRingAddr, 0); | |
1042 | cpw32_f(HiTxRingAddr + 4, 0); | |
1043 | ||
1044 | ring_dma = cp->ring_dma; | |
1045 | cpw32_f(RxRingAddr, ring_dma & 0xffffffff); | |
1046 | cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16); | |
1047 | ||
1048 | ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE; | |
1049 | cpw32_f(TxRingAddr, ring_dma & 0xffffffff); | |
1050 | cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16); | |
1051 | ||
1052 | cpw16(MultiIntr, 0); | |
1053 | ||
1054 | cpw16_f(IntrMask, cp_intr_mask); | |
1055 | ||
1056 | cpw8_f(Cfg9346, Cfg9346_Lock); | |
1057 | } | |
1058 | ||
1059 | static int cp_refill_rx (struct cp_private *cp) | |
1060 | { | |
1061 | unsigned i; | |
1062 | ||
1063 | for (i = 0; i < CP_RX_RING_SIZE; i++) { | |
1064 | struct sk_buff *skb; | |
3598b57b | 1065 | dma_addr_t mapping; |
1da177e4 LT |
1066 | |
1067 | skb = dev_alloc_skb(cp->rx_buf_sz + RX_OFFSET); | |
1068 | if (!skb) | |
1069 | goto err_out; | |
1070 | ||
1da177e4 LT |
1071 | skb_reserve(skb, RX_OFFSET); |
1072 | ||
3598b57b FR |
1073 | mapping = pci_map_single(cp->pdev, skb->data, cp->rx_buf_sz, |
1074 | PCI_DMA_FROMDEVICE); | |
0ba894d4 | 1075 | cp->rx_skb[i] = skb; |
1da177e4 LT |
1076 | |
1077 | cp->rx_ring[i].opts2 = 0; | |
3598b57b | 1078 | cp->rx_ring[i].addr = cpu_to_le64(mapping); |
1da177e4 LT |
1079 | if (i == (CP_RX_RING_SIZE - 1)) |
1080 | cp->rx_ring[i].opts1 = | |
1081 | cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz); | |
1082 | else | |
1083 | cp->rx_ring[i].opts1 = | |
1084 | cpu_to_le32(DescOwn | cp->rx_buf_sz); | |
1085 | } | |
1086 | ||
1087 | return 0; | |
1088 | ||
1089 | err_out: | |
1090 | cp_clean_rings(cp); | |
1091 | return -ENOMEM; | |
1092 | } | |
1093 | ||
576cfa93 FR |
1094 | static void cp_init_rings_index (struct cp_private *cp) |
1095 | { | |
1096 | cp->rx_tail = 0; | |
1097 | cp->tx_head = cp->tx_tail = 0; | |
1098 | } | |
1099 | ||
1da177e4 LT |
1100 | static int cp_init_rings (struct cp_private *cp) |
1101 | { | |
1102 | memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE); | |
1103 | cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd); | |
1104 | ||
576cfa93 | 1105 | cp_init_rings_index(cp); |
1da177e4 LT |
1106 | |
1107 | return cp_refill_rx (cp); | |
1108 | } | |
1109 | ||
1110 | static int cp_alloc_rings (struct cp_private *cp) | |
1111 | { | |
1112 | void *mem; | |
1113 | ||
1114 | mem = pci_alloc_consistent(cp->pdev, CP_RING_BYTES, &cp->ring_dma); | |
1115 | if (!mem) | |
1116 | return -ENOMEM; | |
1117 | ||
1118 | cp->rx_ring = mem; | |
1119 | cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE]; | |
1120 | ||
1da177e4 LT |
1121 | return cp_init_rings(cp); |
1122 | } | |
1123 | ||
1124 | static void cp_clean_rings (struct cp_private *cp) | |
1125 | { | |
3598b57b | 1126 | struct cp_desc *desc; |
1da177e4 LT |
1127 | unsigned i; |
1128 | ||
1da177e4 | 1129 | for (i = 0; i < CP_RX_RING_SIZE; i++) { |
0ba894d4 | 1130 | if (cp->rx_skb[i]) { |
3598b57b FR |
1131 | desc = cp->rx_ring + i; |
1132 | pci_unmap_single(cp->pdev, le64_to_cpu(desc->addr), | |
1da177e4 | 1133 | cp->rx_buf_sz, PCI_DMA_FROMDEVICE); |
0ba894d4 | 1134 | dev_kfree_skb(cp->rx_skb[i]); |
1da177e4 LT |
1135 | } |
1136 | } | |
1137 | ||
1138 | for (i = 0; i < CP_TX_RING_SIZE; i++) { | |
48907e39 FR |
1139 | if (cp->tx_skb[i]) { |
1140 | struct sk_buff *skb = cp->tx_skb[i]; | |
5734418d | 1141 | |
3598b57b FR |
1142 | desc = cp->tx_ring + i; |
1143 | pci_unmap_single(cp->pdev, le64_to_cpu(desc->addr), | |
48907e39 FR |
1144 | le32_to_cpu(desc->opts1) & 0xffff, |
1145 | PCI_DMA_TODEVICE); | |
3598b57b | 1146 | if (le32_to_cpu(desc->opts1) & LastFrag) |
5734418d | 1147 | dev_kfree_skb(skb); |
1da177e4 LT |
1148 | cp->net_stats.tx_dropped++; |
1149 | } | |
1150 | } | |
1151 | ||
5734418d FR |
1152 | memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE); |
1153 | memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE); | |
1154 | ||
0ba894d4 | 1155 | memset(cp->rx_skb, 0, sizeof(struct sk_buff *) * CP_RX_RING_SIZE); |
48907e39 | 1156 | memset(cp->tx_skb, 0, sizeof(struct sk_buff *) * CP_TX_RING_SIZE); |
1da177e4 LT |
1157 | } |
1158 | ||
1159 | static void cp_free_rings (struct cp_private *cp) | |
1160 | { | |
1161 | cp_clean_rings(cp); | |
1162 | pci_free_consistent(cp->pdev, CP_RING_BYTES, cp->rx_ring, cp->ring_dma); | |
1163 | cp->rx_ring = NULL; | |
1164 | cp->tx_ring = NULL; | |
1da177e4 LT |
1165 | } |
1166 | ||
1167 | static int cp_open (struct net_device *dev) | |
1168 | { | |
1169 | struct cp_private *cp = netdev_priv(dev); | |
1170 | int rc; | |
1171 | ||
1172 | if (netif_msg_ifup(cp)) | |
1173 | printk(KERN_DEBUG "%s: enabling interface\n", dev->name); | |
1174 | ||
1175 | rc = cp_alloc_rings(cp); | |
1176 | if (rc) | |
1177 | return rc; | |
1178 | ||
1179 | cp_init_hw(cp); | |
1180 | ||
1fb9df5d | 1181 | rc = request_irq(dev->irq, cp_interrupt, IRQF_SHARED, dev->name, dev); |
1da177e4 LT |
1182 | if (rc) |
1183 | goto err_out_hw; | |
1184 | ||
1185 | netif_carrier_off(dev); | |
2501f843 | 1186 | mii_check_media(&cp->mii_if, netif_msg_link(cp), true); |
1da177e4 LT |
1187 | netif_start_queue(dev); |
1188 | ||
1189 | return 0; | |
1190 | ||
1191 | err_out_hw: | |
1192 | cp_stop_hw(cp); | |
1193 | cp_free_rings(cp); | |
1194 | return rc; | |
1195 | } | |
1196 | ||
1197 | static int cp_close (struct net_device *dev) | |
1198 | { | |
1199 | struct cp_private *cp = netdev_priv(dev); | |
1200 | unsigned long flags; | |
1201 | ||
1202 | if (netif_msg_ifdown(cp)) | |
1203 | printk(KERN_DEBUG "%s: disabling interface\n", dev->name); | |
1204 | ||
1205 | spin_lock_irqsave(&cp->lock, flags); | |
1206 | ||
1207 | netif_stop_queue(dev); | |
1208 | netif_carrier_off(dev); | |
1209 | ||
1210 | cp_stop_hw(cp); | |
1211 | ||
1212 | spin_unlock_irqrestore(&cp->lock, flags); | |
1213 | ||
1214 | synchronize_irq(dev->irq); | |
1215 | free_irq(dev->irq, dev); | |
1216 | ||
1217 | cp_free_rings(cp); | |
1218 | return 0; | |
1219 | } | |
1220 | ||
1221 | #ifdef BROKEN | |
1222 | static int cp_change_mtu(struct net_device *dev, int new_mtu) | |
1223 | { | |
1224 | struct cp_private *cp = netdev_priv(dev); | |
1225 | int rc; | |
1226 | unsigned long flags; | |
1227 | ||
1228 | /* check for invalid MTU, according to hardware limits */ | |
1229 | if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU) | |
1230 | return -EINVAL; | |
1231 | ||
1232 | /* if network interface not up, no need for complexity */ | |
1233 | if (!netif_running(dev)) { | |
1234 | dev->mtu = new_mtu; | |
1235 | cp_set_rxbufsize(cp); /* set new rx buf size */ | |
1236 | return 0; | |
1237 | } | |
1238 | ||
1239 | spin_lock_irqsave(&cp->lock, flags); | |
1240 | ||
1241 | cp_stop_hw(cp); /* stop h/w and free rings */ | |
1242 | cp_clean_rings(cp); | |
1243 | ||
1244 | dev->mtu = new_mtu; | |
1245 | cp_set_rxbufsize(cp); /* set new rx buf size */ | |
1246 | ||
1247 | rc = cp_init_rings(cp); /* realloc and restart h/w */ | |
1248 | cp_start_hw(cp); | |
1249 | ||
1250 | spin_unlock_irqrestore(&cp->lock, flags); | |
1251 | ||
1252 | return rc; | |
1253 | } | |
1254 | #endif /* BROKEN */ | |
1255 | ||
f71e1309 | 1256 | static const char mii_2_8139_map[8] = { |
1da177e4 LT |
1257 | BasicModeCtrl, |
1258 | BasicModeStatus, | |
1259 | 0, | |
1260 | 0, | |
1261 | NWayAdvert, | |
1262 | NWayLPAR, | |
1263 | NWayExpansion, | |
1264 | 0 | |
1265 | }; | |
1266 | ||
1267 | static int mdio_read(struct net_device *dev, int phy_id, int location) | |
1268 | { | |
1269 | struct cp_private *cp = netdev_priv(dev); | |
1270 | ||
1271 | return location < 8 && mii_2_8139_map[location] ? | |
1272 | readw(cp->regs + mii_2_8139_map[location]) : 0; | |
1273 | } | |
1274 | ||
1275 | ||
1276 | static void mdio_write(struct net_device *dev, int phy_id, int location, | |
1277 | int value) | |
1278 | { | |
1279 | struct cp_private *cp = netdev_priv(dev); | |
1280 | ||
1281 | if (location == 0) { | |
1282 | cpw8(Cfg9346, Cfg9346_Unlock); | |
1283 | cpw16(BasicModeCtrl, value); | |
1284 | cpw8(Cfg9346, Cfg9346_Lock); | |
1285 | } else if (location < 8 && mii_2_8139_map[location]) | |
1286 | cpw16(mii_2_8139_map[location], value); | |
1287 | } | |
1288 | ||
1289 | /* Set the ethtool Wake-on-LAN settings */ | |
1290 | static int netdev_set_wol (struct cp_private *cp, | |
1291 | const struct ethtool_wolinfo *wol) | |
1292 | { | |
1293 | u8 options; | |
1294 | ||
1295 | options = cpr8 (Config3) & ~(LinkUp | MagicPacket); | |
1296 | /* If WOL is being disabled, no need for complexity */ | |
1297 | if (wol->wolopts) { | |
1298 | if (wol->wolopts & WAKE_PHY) options |= LinkUp; | |
1299 | if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket; | |
1300 | } | |
1301 | ||
1302 | cpw8 (Cfg9346, Cfg9346_Unlock); | |
1303 | cpw8 (Config3, options); | |
1304 | cpw8 (Cfg9346, Cfg9346_Lock); | |
1305 | ||
1306 | options = 0; /* Paranoia setting */ | |
1307 | options = cpr8 (Config5) & ~(UWF | MWF | BWF); | |
1308 | /* If WOL is being disabled, no need for complexity */ | |
1309 | if (wol->wolopts) { | |
1310 | if (wol->wolopts & WAKE_UCAST) options |= UWF; | |
1311 | if (wol->wolopts & WAKE_BCAST) options |= BWF; | |
1312 | if (wol->wolopts & WAKE_MCAST) options |= MWF; | |
1313 | } | |
1314 | ||
1315 | cpw8 (Config5, options); | |
1316 | ||
1317 | cp->wol_enabled = (wol->wolopts) ? 1 : 0; | |
1318 | ||
1319 | return 0; | |
1320 | } | |
1321 | ||
1322 | /* Get the ethtool Wake-on-LAN settings */ | |
1323 | static void netdev_get_wol (struct cp_private *cp, | |
1324 | struct ethtool_wolinfo *wol) | |
1325 | { | |
1326 | u8 options; | |
1327 | ||
1328 | wol->wolopts = 0; /* Start from scratch */ | |
1329 | wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC | | |
1330 | WAKE_MCAST | WAKE_UCAST; | |
1331 | /* We don't need to go on if WOL is disabled */ | |
1332 | if (!cp->wol_enabled) return; | |
f3b197ac | 1333 | |
1da177e4 LT |
1334 | options = cpr8 (Config3); |
1335 | if (options & LinkUp) wol->wolopts |= WAKE_PHY; | |
1336 | if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC; | |
1337 | ||
1338 | options = 0; /* Paranoia setting */ | |
1339 | options = cpr8 (Config5); | |
1340 | if (options & UWF) wol->wolopts |= WAKE_UCAST; | |
1341 | if (options & BWF) wol->wolopts |= WAKE_BCAST; | |
1342 | if (options & MWF) wol->wolopts |= WAKE_MCAST; | |
1343 | } | |
1344 | ||
1345 | static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info) | |
1346 | { | |
1347 | struct cp_private *cp = netdev_priv(dev); | |
1348 | ||
1349 | strcpy (info->driver, DRV_NAME); | |
1350 | strcpy (info->version, DRV_VERSION); | |
1351 | strcpy (info->bus_info, pci_name(cp->pdev)); | |
1352 | } | |
1353 | ||
1354 | static int cp_get_regs_len(struct net_device *dev) | |
1355 | { | |
1356 | return CP_REGS_SIZE; | |
1357 | } | |
1358 | ||
1359 | static int cp_get_stats_count (struct net_device *dev) | |
1360 | { | |
1361 | return CP_NUM_STATS; | |
1362 | } | |
1363 | ||
1364 | static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1365 | { | |
1366 | struct cp_private *cp = netdev_priv(dev); | |
1367 | int rc; | |
1368 | unsigned long flags; | |
1369 | ||
1370 | spin_lock_irqsave(&cp->lock, flags); | |
1371 | rc = mii_ethtool_gset(&cp->mii_if, cmd); | |
1372 | spin_unlock_irqrestore(&cp->lock, flags); | |
1373 | ||
1374 | return rc; | |
1375 | } | |
1376 | ||
1377 | static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1378 | { | |
1379 | struct cp_private *cp = netdev_priv(dev); | |
1380 | int rc; | |
1381 | unsigned long flags; | |
1382 | ||
1383 | spin_lock_irqsave(&cp->lock, flags); | |
1384 | rc = mii_ethtool_sset(&cp->mii_if, cmd); | |
1385 | spin_unlock_irqrestore(&cp->lock, flags); | |
1386 | ||
1387 | return rc; | |
1388 | } | |
1389 | ||
1390 | static int cp_nway_reset(struct net_device *dev) | |
1391 | { | |
1392 | struct cp_private *cp = netdev_priv(dev); | |
1393 | return mii_nway_restart(&cp->mii_if); | |
1394 | } | |
1395 | ||
1396 | static u32 cp_get_msglevel(struct net_device *dev) | |
1397 | { | |
1398 | struct cp_private *cp = netdev_priv(dev); | |
1399 | return cp->msg_enable; | |
1400 | } | |
1401 | ||
1402 | static void cp_set_msglevel(struct net_device *dev, u32 value) | |
1403 | { | |
1404 | struct cp_private *cp = netdev_priv(dev); | |
1405 | cp->msg_enable = value; | |
1406 | } | |
1407 | ||
1408 | static u32 cp_get_rx_csum(struct net_device *dev) | |
1409 | { | |
1410 | struct cp_private *cp = netdev_priv(dev); | |
1411 | return (cpr16(CpCmd) & RxChkSum) ? 1 : 0; | |
1412 | } | |
1413 | ||
1414 | static int cp_set_rx_csum(struct net_device *dev, u32 data) | |
1415 | { | |
1416 | struct cp_private *cp = netdev_priv(dev); | |
1417 | u16 cmd = cp->cpcmd, newcmd; | |
1418 | ||
1419 | newcmd = cmd; | |
1420 | ||
1421 | if (data) | |
1422 | newcmd |= RxChkSum; | |
1423 | else | |
1424 | newcmd &= ~RxChkSum; | |
1425 | ||
1426 | if (newcmd != cmd) { | |
1427 | unsigned long flags; | |
1428 | ||
1429 | spin_lock_irqsave(&cp->lock, flags); | |
1430 | cp->cpcmd = newcmd; | |
1431 | cpw16_f(CpCmd, newcmd); | |
1432 | spin_unlock_irqrestore(&cp->lock, flags); | |
1433 | } | |
1434 | ||
1435 | return 0; | |
1436 | } | |
1437 | ||
1438 | static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
1439 | void *p) | |
1440 | { | |
1441 | struct cp_private *cp = netdev_priv(dev); | |
1442 | unsigned long flags; | |
1443 | ||
1444 | if (regs->len < CP_REGS_SIZE) | |
1445 | return /* -EINVAL */; | |
1446 | ||
1447 | regs->version = CP_REGS_VER; | |
1448 | ||
1449 | spin_lock_irqsave(&cp->lock, flags); | |
1450 | memcpy_fromio(p, cp->regs, CP_REGS_SIZE); | |
1451 | spin_unlock_irqrestore(&cp->lock, flags); | |
1452 | } | |
1453 | ||
1454 | static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol) | |
1455 | { | |
1456 | struct cp_private *cp = netdev_priv(dev); | |
1457 | unsigned long flags; | |
1458 | ||
1459 | spin_lock_irqsave (&cp->lock, flags); | |
1460 | netdev_get_wol (cp, wol); | |
1461 | spin_unlock_irqrestore (&cp->lock, flags); | |
1462 | } | |
1463 | ||
1464 | static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol) | |
1465 | { | |
1466 | struct cp_private *cp = netdev_priv(dev); | |
1467 | unsigned long flags; | |
1468 | int rc; | |
1469 | ||
1470 | spin_lock_irqsave (&cp->lock, flags); | |
1471 | rc = netdev_set_wol (cp, wol); | |
1472 | spin_unlock_irqrestore (&cp->lock, flags); | |
1473 | ||
1474 | return rc; | |
1475 | } | |
1476 | ||
1477 | static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf) | |
1478 | { | |
1479 | switch (stringset) { | |
1480 | case ETH_SS_STATS: | |
1481 | memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys)); | |
1482 | break; | |
1483 | default: | |
1484 | BUG(); | |
1485 | break; | |
1486 | } | |
1487 | } | |
1488 | ||
1489 | static void cp_get_ethtool_stats (struct net_device *dev, | |
1490 | struct ethtool_stats *estats, u64 *tmp_stats) | |
1491 | { | |
1492 | struct cp_private *cp = netdev_priv(dev); | |
8b512927 SH |
1493 | struct cp_dma_stats *nic_stats; |
1494 | dma_addr_t dma; | |
1da177e4 LT |
1495 | int i; |
1496 | ||
8b512927 SH |
1497 | nic_stats = pci_alloc_consistent(cp->pdev, sizeof(*nic_stats), &dma); |
1498 | if (!nic_stats) | |
1499 | return; | |
97f568d8 | 1500 | |
1da177e4 | 1501 | /* begin NIC statistics dump */ |
8b512927 SH |
1502 | cpw32(StatsAddr + 4, (u64)dma >> 32); |
1503 | cpw32(StatsAddr, ((u64)dma & DMA_32BIT_MASK) | DumpStats); | |
1da177e4 LT |
1504 | cpr32(StatsAddr); |
1505 | ||
97f568d8 | 1506 | for (i = 0; i < 1000; i++) { |
1da177e4 LT |
1507 | if ((cpr32(StatsAddr) & DumpStats) == 0) |
1508 | break; | |
97f568d8 | 1509 | udelay(10); |
1da177e4 | 1510 | } |
97f568d8 SH |
1511 | cpw32(StatsAddr, 0); |
1512 | cpw32(StatsAddr + 4, 0); | |
8b512927 | 1513 | cpr32(StatsAddr); |
1da177e4 LT |
1514 | |
1515 | i = 0; | |
8b512927 SH |
1516 | tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok); |
1517 | tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok); | |
1518 | tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err); | |
1519 | tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err); | |
1520 | tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo); | |
1521 | tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align); | |
1522 | tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col); | |
1523 | tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol); | |
1524 | tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys); | |
1525 | tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast); | |
1526 | tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast); | |
1527 | tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort); | |
1528 | tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun); | |
1da177e4 | 1529 | tmp_stats[i++] = cp->cp_stats.rx_frags; |
5d9428de | 1530 | BUG_ON(i != CP_NUM_STATS); |
8b512927 SH |
1531 | |
1532 | pci_free_consistent(cp->pdev, sizeof(*nic_stats), nic_stats, dma); | |
1da177e4 LT |
1533 | } |
1534 | ||
7282d491 | 1535 | static const struct ethtool_ops cp_ethtool_ops = { |
1da177e4 LT |
1536 | .get_drvinfo = cp_get_drvinfo, |
1537 | .get_regs_len = cp_get_regs_len, | |
1538 | .get_stats_count = cp_get_stats_count, | |
1539 | .get_settings = cp_get_settings, | |
1540 | .set_settings = cp_set_settings, | |
1541 | .nway_reset = cp_nway_reset, | |
1542 | .get_link = ethtool_op_get_link, | |
1543 | .get_msglevel = cp_get_msglevel, | |
1544 | .set_msglevel = cp_set_msglevel, | |
1545 | .get_rx_csum = cp_get_rx_csum, | |
1546 | .set_rx_csum = cp_set_rx_csum, | |
1547 | .get_tx_csum = ethtool_op_get_tx_csum, | |
1548 | .set_tx_csum = ethtool_op_set_tx_csum, /* local! */ | |
1549 | .get_sg = ethtool_op_get_sg, | |
1550 | .set_sg = ethtool_op_set_sg, | |
fcec3456 JG |
1551 | .get_tso = ethtool_op_get_tso, |
1552 | .set_tso = ethtool_op_set_tso, | |
1da177e4 LT |
1553 | .get_regs = cp_get_regs, |
1554 | .get_wol = cp_get_wol, | |
1555 | .set_wol = cp_set_wol, | |
1556 | .get_strings = cp_get_strings, | |
1557 | .get_ethtool_stats = cp_get_ethtool_stats, | |
bb0ce608 | 1558 | .get_perm_addr = ethtool_op_get_perm_addr, |
722fdb33 PC |
1559 | .get_eeprom_len = cp_get_eeprom_len, |
1560 | .get_eeprom = cp_get_eeprom, | |
1561 | .set_eeprom = cp_set_eeprom, | |
1da177e4 LT |
1562 | }; |
1563 | ||
1564 | static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd) | |
1565 | { | |
1566 | struct cp_private *cp = netdev_priv(dev); | |
1567 | int rc; | |
1568 | unsigned long flags; | |
1569 | ||
1570 | if (!netif_running(dev)) | |
1571 | return -EINVAL; | |
1572 | ||
1573 | spin_lock_irqsave(&cp->lock, flags); | |
1574 | rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL); | |
1575 | spin_unlock_irqrestore(&cp->lock, flags); | |
1576 | return rc; | |
1577 | } | |
1578 | ||
1579 | /* Serial EEPROM section. */ | |
1580 | ||
1581 | /* EEPROM_Ctrl bits. */ | |
1582 | #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */ | |
1583 | #define EE_CS 0x08 /* EEPROM chip select. */ | |
1584 | #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */ | |
1585 | #define EE_WRITE_0 0x00 | |
1586 | #define EE_WRITE_1 0x02 | |
1587 | #define EE_DATA_READ 0x01 /* EEPROM chip data out. */ | |
1588 | #define EE_ENB (0x80 | EE_CS) | |
1589 | ||
1590 | /* Delay between EEPROM clock transitions. | |
1591 | No extra delay is needed with 33Mhz PCI, but 66Mhz may change this. | |
1592 | */ | |
1593 | ||
1594 | #define eeprom_delay() readl(ee_addr) | |
1595 | ||
1596 | /* The EEPROM commands include the alway-set leading bit. */ | |
722fdb33 | 1597 | #define EE_EXTEND_CMD (4) |
1da177e4 LT |
1598 | #define EE_WRITE_CMD (5) |
1599 | #define EE_READ_CMD (6) | |
1600 | #define EE_ERASE_CMD (7) | |
1601 | ||
722fdb33 PC |
1602 | #define EE_EWDS_ADDR (0) |
1603 | #define EE_WRAL_ADDR (1) | |
1604 | #define EE_ERAL_ADDR (2) | |
1605 | #define EE_EWEN_ADDR (3) | |
1606 | ||
1607 | #define CP_EEPROM_MAGIC PCI_DEVICE_ID_REALTEK_8139 | |
1da177e4 | 1608 | |
722fdb33 PC |
1609 | static void eeprom_cmd_start(void __iomem *ee_addr) |
1610 | { | |
1da177e4 LT |
1611 | writeb (EE_ENB & ~EE_CS, ee_addr); |
1612 | writeb (EE_ENB, ee_addr); | |
1613 | eeprom_delay (); | |
722fdb33 | 1614 | } |
1da177e4 | 1615 | |
722fdb33 PC |
1616 | static void eeprom_cmd(void __iomem *ee_addr, int cmd, int cmd_len) |
1617 | { | |
1618 | int i; | |
1619 | ||
1620 | /* Shift the command bits out. */ | |
1621 | for (i = cmd_len - 1; i >= 0; i--) { | |
1622 | int dataval = (cmd & (1 << i)) ? EE_DATA_WRITE : 0; | |
1da177e4 LT |
1623 | writeb (EE_ENB | dataval, ee_addr); |
1624 | eeprom_delay (); | |
1625 | writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr); | |
1626 | eeprom_delay (); | |
1627 | } | |
1628 | writeb (EE_ENB, ee_addr); | |
1629 | eeprom_delay (); | |
722fdb33 PC |
1630 | } |
1631 | ||
1632 | static void eeprom_cmd_end(void __iomem *ee_addr) | |
1633 | { | |
1634 | writeb (~EE_CS, ee_addr); | |
1635 | eeprom_delay (); | |
1636 | } | |
1637 | ||
1638 | static void eeprom_extend_cmd(void __iomem *ee_addr, int extend_cmd, | |
1639 | int addr_len) | |
1640 | { | |
1641 | int cmd = (EE_EXTEND_CMD << addr_len) | (extend_cmd << (addr_len - 2)); | |
1642 | ||
1643 | eeprom_cmd_start(ee_addr); | |
1644 | eeprom_cmd(ee_addr, cmd, 3 + addr_len); | |
1645 | eeprom_cmd_end(ee_addr); | |
1646 | } | |
1647 | ||
1648 | static u16 read_eeprom (void __iomem *ioaddr, int location, int addr_len) | |
1649 | { | |
1650 | int i; | |
1651 | u16 retval = 0; | |
1652 | void __iomem *ee_addr = ioaddr + Cfg9346; | |
1653 | int read_cmd = location | (EE_READ_CMD << addr_len); | |
1654 | ||
1655 | eeprom_cmd_start(ee_addr); | |
1656 | eeprom_cmd(ee_addr, read_cmd, 3 + addr_len); | |
1da177e4 LT |
1657 | |
1658 | for (i = 16; i > 0; i--) { | |
1659 | writeb (EE_ENB | EE_SHIFT_CLK, ee_addr); | |
1660 | eeprom_delay (); | |
1661 | retval = | |
1662 | (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 : | |
1663 | 0); | |
1664 | writeb (EE_ENB, ee_addr); | |
1665 | eeprom_delay (); | |
1666 | } | |
1667 | ||
722fdb33 | 1668 | eeprom_cmd_end(ee_addr); |
1da177e4 LT |
1669 | |
1670 | return retval; | |
1671 | } | |
1672 | ||
722fdb33 PC |
1673 | static void write_eeprom(void __iomem *ioaddr, int location, u16 val, |
1674 | int addr_len) | |
1675 | { | |
1676 | int i; | |
1677 | void __iomem *ee_addr = ioaddr + Cfg9346; | |
1678 | int write_cmd = location | (EE_WRITE_CMD << addr_len); | |
1679 | ||
1680 | eeprom_extend_cmd(ee_addr, EE_EWEN_ADDR, addr_len); | |
1681 | ||
1682 | eeprom_cmd_start(ee_addr); | |
1683 | eeprom_cmd(ee_addr, write_cmd, 3 + addr_len); | |
1684 | eeprom_cmd(ee_addr, val, 16); | |
1685 | eeprom_cmd_end(ee_addr); | |
1686 | ||
1687 | eeprom_cmd_start(ee_addr); | |
1688 | for (i = 0; i < 20000; i++) | |
1689 | if (readb(ee_addr) & EE_DATA_READ) | |
1690 | break; | |
1691 | eeprom_cmd_end(ee_addr); | |
1692 | ||
1693 | eeprom_extend_cmd(ee_addr, EE_EWDS_ADDR, addr_len); | |
1694 | } | |
1695 | ||
1696 | static int cp_get_eeprom_len(struct net_device *dev) | |
1697 | { | |
1698 | struct cp_private *cp = netdev_priv(dev); | |
1699 | int size; | |
1700 | ||
1701 | spin_lock_irq(&cp->lock); | |
1702 | size = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 256 : 128; | |
1703 | spin_unlock_irq(&cp->lock); | |
1704 | ||
1705 | return size; | |
1706 | } | |
1707 | ||
1708 | static int cp_get_eeprom(struct net_device *dev, | |
1709 | struct ethtool_eeprom *eeprom, u8 *data) | |
1710 | { | |
1711 | struct cp_private *cp = netdev_priv(dev); | |
1712 | unsigned int addr_len; | |
1713 | u16 val; | |
1714 | u32 offset = eeprom->offset >> 1; | |
1715 | u32 len = eeprom->len; | |
1716 | u32 i = 0; | |
1717 | ||
1718 | eeprom->magic = CP_EEPROM_MAGIC; | |
1719 | ||
1720 | spin_lock_irq(&cp->lock); | |
1721 | ||
1722 | addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6; | |
1723 | ||
1724 | if (eeprom->offset & 1) { | |
1725 | val = read_eeprom(cp->regs, offset, addr_len); | |
1726 | data[i++] = (u8)(val >> 8); | |
1727 | offset++; | |
1728 | } | |
1729 | ||
1730 | while (i < len - 1) { | |
1731 | val = read_eeprom(cp->regs, offset, addr_len); | |
1732 | data[i++] = (u8)val; | |
1733 | data[i++] = (u8)(val >> 8); | |
1734 | offset++; | |
1735 | } | |
1736 | ||
1737 | if (i < len) { | |
1738 | val = read_eeprom(cp->regs, offset, addr_len); | |
1739 | data[i] = (u8)val; | |
1740 | } | |
1741 | ||
1742 | spin_unlock_irq(&cp->lock); | |
1743 | return 0; | |
1744 | } | |
1745 | ||
1746 | static int cp_set_eeprom(struct net_device *dev, | |
1747 | struct ethtool_eeprom *eeprom, u8 *data) | |
1748 | { | |
1749 | struct cp_private *cp = netdev_priv(dev); | |
1750 | unsigned int addr_len; | |
1751 | u16 val; | |
1752 | u32 offset = eeprom->offset >> 1; | |
1753 | u32 len = eeprom->len; | |
1754 | u32 i = 0; | |
1755 | ||
1756 | if (eeprom->magic != CP_EEPROM_MAGIC) | |
1757 | return -EINVAL; | |
1758 | ||
1759 | spin_lock_irq(&cp->lock); | |
1760 | ||
1761 | addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6; | |
1762 | ||
1763 | if (eeprom->offset & 1) { | |
1764 | val = read_eeprom(cp->regs, offset, addr_len) & 0xff; | |
1765 | val |= (u16)data[i++] << 8; | |
1766 | write_eeprom(cp->regs, offset, val, addr_len); | |
1767 | offset++; | |
1768 | } | |
1769 | ||
1770 | while (i < len - 1) { | |
1771 | val = (u16)data[i++]; | |
1772 | val |= (u16)data[i++] << 8; | |
1773 | write_eeprom(cp->regs, offset, val, addr_len); | |
1774 | offset++; | |
1775 | } | |
1776 | ||
1777 | if (i < len) { | |
1778 | val = read_eeprom(cp->regs, offset, addr_len) & 0xff00; | |
1779 | val |= (u16)data[i]; | |
1780 | write_eeprom(cp->regs, offset, val, addr_len); | |
1781 | } | |
1782 | ||
1783 | spin_unlock_irq(&cp->lock); | |
1784 | return 0; | |
1785 | } | |
1786 | ||
1da177e4 LT |
1787 | /* Put the board into D3cold state and wait for WakeUp signal */ |
1788 | static void cp_set_d3_state (struct cp_private *cp) | |
1789 | { | |
1790 | pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */ | |
1791 | pci_set_power_state (cp->pdev, PCI_D3hot); | |
1792 | } | |
1793 | ||
1794 | static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
1795 | { | |
1796 | struct net_device *dev; | |
1797 | struct cp_private *cp; | |
1798 | int rc; | |
1799 | void __iomem *regs; | |
2427ddd8 | 1800 | resource_size_t pciaddr; |
1da177e4 | 1801 | unsigned int addr_len, i, pci_using_dac; |
1da177e4 LT |
1802 | |
1803 | #ifndef MODULE | |
1804 | static int version_printed; | |
1805 | if (version_printed++ == 0) | |
1806 | printk("%s", version); | |
1807 | #endif | |
1808 | ||
1da177e4 | 1809 | if (pdev->vendor == PCI_VENDOR_ID_REALTEK && |
44c10138 | 1810 | pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision < 0x20) { |
9b91cf9d | 1811 | dev_err(&pdev->dev, |
2e8a538d | 1812 | "This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip\n", |
44c10138 | 1813 | pdev->vendor, pdev->device, pdev->revision); |
9b91cf9d | 1814 | dev_err(&pdev->dev, "Try the \"8139too\" driver instead.\n"); |
1da177e4 LT |
1815 | return -ENODEV; |
1816 | } | |
1817 | ||
1818 | dev = alloc_etherdev(sizeof(struct cp_private)); | |
1819 | if (!dev) | |
1820 | return -ENOMEM; | |
1821 | SET_MODULE_OWNER(dev); | |
1822 | SET_NETDEV_DEV(dev, &pdev->dev); | |
1823 | ||
1824 | cp = netdev_priv(dev); | |
1825 | cp->pdev = pdev; | |
1826 | cp->dev = dev; | |
1827 | cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug); | |
1828 | spin_lock_init (&cp->lock); | |
1829 | cp->mii_if.dev = dev; | |
1830 | cp->mii_if.mdio_read = mdio_read; | |
1831 | cp->mii_if.mdio_write = mdio_write; | |
1832 | cp->mii_if.phy_id = CP_INTERNAL_PHY; | |
1833 | cp->mii_if.phy_id_mask = 0x1f; | |
1834 | cp->mii_if.reg_num_mask = 0x1f; | |
1835 | cp_set_rxbufsize(cp); | |
1836 | ||
1837 | rc = pci_enable_device(pdev); | |
1838 | if (rc) | |
1839 | goto err_out_free; | |
1840 | ||
1841 | rc = pci_set_mwi(pdev); | |
1842 | if (rc) | |
1843 | goto err_out_disable; | |
1844 | ||
1845 | rc = pci_request_regions(pdev, DRV_NAME); | |
1846 | if (rc) | |
1847 | goto err_out_mwi; | |
1848 | ||
1849 | pciaddr = pci_resource_start(pdev, 1); | |
1850 | if (!pciaddr) { | |
1851 | rc = -EIO; | |
9b91cf9d | 1852 | dev_err(&pdev->dev, "no MMIO resource\n"); |
1da177e4 LT |
1853 | goto err_out_res; |
1854 | } | |
1855 | if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) { | |
1856 | rc = -EIO; | |
9b91cf9d | 1857 | dev_err(&pdev->dev, "MMIO resource (%llx) too small\n", |
2e8a538d | 1858 | (unsigned long long)pci_resource_len(pdev, 1)); |
1da177e4 LT |
1859 | goto err_out_res; |
1860 | } | |
1861 | ||
1862 | /* Configure DMA attributes. */ | |
1863 | if ((sizeof(dma_addr_t) > 4) && | |
8662d061 TK |
1864 | !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) && |
1865 | !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { | |
1da177e4 LT |
1866 | pci_using_dac = 1; |
1867 | } else { | |
1868 | pci_using_dac = 0; | |
1869 | ||
8662d061 | 1870 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); |
1da177e4 | 1871 | if (rc) { |
9b91cf9d | 1872 | dev_err(&pdev->dev, |
2e8a538d | 1873 | "No usable DMA configuration, aborting.\n"); |
1da177e4 LT |
1874 | goto err_out_res; |
1875 | } | |
8662d061 | 1876 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); |
1da177e4 | 1877 | if (rc) { |
9b91cf9d | 1878 | dev_err(&pdev->dev, |
2e8a538d JG |
1879 | "No usable consistent DMA configuration, " |
1880 | "aborting.\n"); | |
1da177e4 LT |
1881 | goto err_out_res; |
1882 | } | |
1883 | } | |
1884 | ||
1885 | cp->cpcmd = (pci_using_dac ? PCIDAC : 0) | | |
1886 | PCIMulRW | RxChkSum | CpRxOn | CpTxOn; | |
1887 | ||
1888 | regs = ioremap(pciaddr, CP_REGS_SIZE); | |
1889 | if (!regs) { | |
1890 | rc = -EIO; | |
4626dd46 | 1891 | dev_err(&pdev->dev, "Cannot map PCI MMIO (%Lx@%Lx)\n", |
2e8a538d JG |
1892 | (unsigned long long)pci_resource_len(pdev, 1), |
1893 | (unsigned long long)pciaddr); | |
1da177e4 LT |
1894 | goto err_out_res; |
1895 | } | |
1896 | dev->base_addr = (unsigned long) regs; | |
1897 | cp->regs = regs; | |
1898 | ||
1899 | cp_stop_hw(cp); | |
1900 | ||
1901 | /* read MAC address from EEPROM */ | |
1902 | addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6; | |
1903 | for (i = 0; i < 3; i++) | |
1904 | ((u16 *) (dev->dev_addr))[i] = | |
1905 | le16_to_cpu (read_eeprom (regs, i + 7, addr_len)); | |
bb0ce608 | 1906 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
1da177e4 LT |
1907 | |
1908 | dev->open = cp_open; | |
1909 | dev->stop = cp_close; | |
1910 | dev->set_multicast_list = cp_set_rx_mode; | |
1911 | dev->hard_start_xmit = cp_start_xmit; | |
1912 | dev->get_stats = cp_get_stats; | |
1913 | dev->do_ioctl = cp_ioctl; | |
1914 | dev->poll = cp_rx_poll; | |
7502cd10 SK |
1915 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1916 | dev->poll_controller = cp_poll_controller; | |
1917 | #endif | |
1da177e4 LT |
1918 | dev->weight = 16; /* arbitrary? from NAPI_HOWTO.txt. */ |
1919 | #ifdef BROKEN | |
1920 | dev->change_mtu = cp_change_mtu; | |
1921 | #endif | |
1922 | dev->ethtool_ops = &cp_ethtool_ops; | |
1923 | #if 0 | |
1924 | dev->tx_timeout = cp_tx_timeout; | |
1925 | dev->watchdog_timeo = TX_TIMEOUT; | |
1926 | #endif | |
1927 | ||
1928 | #if CP_VLAN_TAG_USED | |
1929 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
1930 | dev->vlan_rx_register = cp_vlan_rx_register; | |
1da177e4 LT |
1931 | #endif |
1932 | ||
1933 | if (pci_using_dac) | |
1934 | dev->features |= NETIF_F_HIGHDMA; | |
1935 | ||
fcec3456 JG |
1936 | #if 0 /* disabled by default until verified */ |
1937 | dev->features |= NETIF_F_TSO; | |
1938 | #endif | |
1939 | ||
1da177e4 LT |
1940 | dev->irq = pdev->irq; |
1941 | ||
1942 | rc = register_netdev(dev); | |
1943 | if (rc) | |
1944 | goto err_out_iomap; | |
1945 | ||
1946 | printk (KERN_INFO "%s: RTL-8139C+ at 0x%lx, " | |
1947 | "%02x:%02x:%02x:%02x:%02x:%02x, " | |
1948 | "IRQ %d\n", | |
1949 | dev->name, | |
1950 | dev->base_addr, | |
1951 | dev->dev_addr[0], dev->dev_addr[1], | |
1952 | dev->dev_addr[2], dev->dev_addr[3], | |
1953 | dev->dev_addr[4], dev->dev_addr[5], | |
1954 | dev->irq); | |
1955 | ||
1956 | pci_set_drvdata(pdev, dev); | |
1957 | ||
1958 | /* enable busmastering and memory-write-invalidate */ | |
1959 | pci_set_master(pdev); | |
1960 | ||
2e8a538d JG |
1961 | if (cp->wol_enabled) |
1962 | cp_set_d3_state (cp); | |
1da177e4 LT |
1963 | |
1964 | return 0; | |
1965 | ||
1966 | err_out_iomap: | |
1967 | iounmap(regs); | |
1968 | err_out_res: | |
1969 | pci_release_regions(pdev); | |
1970 | err_out_mwi: | |
1971 | pci_clear_mwi(pdev); | |
1972 | err_out_disable: | |
1973 | pci_disable_device(pdev); | |
1974 | err_out_free: | |
1975 | free_netdev(dev); | |
1976 | return rc; | |
1977 | } | |
1978 | ||
1979 | static void cp_remove_one (struct pci_dev *pdev) | |
1980 | { | |
1981 | struct net_device *dev = pci_get_drvdata(pdev); | |
1982 | struct cp_private *cp = netdev_priv(dev); | |
1983 | ||
1da177e4 LT |
1984 | unregister_netdev(dev); |
1985 | iounmap(cp->regs); | |
2e8a538d JG |
1986 | if (cp->wol_enabled) |
1987 | pci_set_power_state (pdev, PCI_D0); | |
1da177e4 LT |
1988 | pci_release_regions(pdev); |
1989 | pci_clear_mwi(pdev); | |
1990 | pci_disable_device(pdev); | |
1991 | pci_set_drvdata(pdev, NULL); | |
1992 | free_netdev(dev); | |
1993 | } | |
1994 | ||
1995 | #ifdef CONFIG_PM | |
05adc3b7 | 1996 | static int cp_suspend (struct pci_dev *pdev, pm_message_t state) |
1da177e4 | 1997 | { |
7668a494 FR |
1998 | struct net_device *dev = pci_get_drvdata(pdev); |
1999 | struct cp_private *cp = netdev_priv(dev); | |
1da177e4 LT |
2000 | unsigned long flags; |
2001 | ||
7668a494 FR |
2002 | if (!netif_running(dev)) |
2003 | return 0; | |
1da177e4 LT |
2004 | |
2005 | netif_device_detach (dev); | |
2006 | netif_stop_queue (dev); | |
2007 | ||
2008 | spin_lock_irqsave (&cp->lock, flags); | |
2009 | ||
2010 | /* Disable Rx and Tx */ | |
2011 | cpw16 (IntrMask, 0); | |
2012 | cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn)); | |
2013 | ||
2014 | spin_unlock_irqrestore (&cp->lock, flags); | |
2015 | ||
576cfa93 FR |
2016 | pci_save_state(pdev); |
2017 | pci_enable_wake(pdev, pci_choose_state(pdev, state), cp->wol_enabled); | |
2018 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
1da177e4 LT |
2019 | |
2020 | return 0; | |
2021 | } | |
2022 | ||
2023 | static int cp_resume (struct pci_dev *pdev) | |
2024 | { | |
576cfa93 FR |
2025 | struct net_device *dev = pci_get_drvdata (pdev); |
2026 | struct cp_private *cp = netdev_priv(dev); | |
a4cf0761 | 2027 | unsigned long flags; |
1da177e4 | 2028 | |
576cfa93 FR |
2029 | if (!netif_running(dev)) |
2030 | return 0; | |
1da177e4 LT |
2031 | |
2032 | netif_device_attach (dev); | |
576cfa93 FR |
2033 | |
2034 | pci_set_power_state(pdev, PCI_D0); | |
2035 | pci_restore_state(pdev); | |
2036 | pci_enable_wake(pdev, PCI_D0, 0); | |
2037 | ||
2038 | /* FIXME: sh*t may happen if the Rx ring buffer is depleted */ | |
2039 | cp_init_rings_index (cp); | |
1da177e4 LT |
2040 | cp_init_hw (cp); |
2041 | netif_start_queue (dev); | |
a4cf0761 PO |
2042 | |
2043 | spin_lock_irqsave (&cp->lock, flags); | |
2044 | ||
2501f843 | 2045 | mii_check_media(&cp->mii_if, netif_msg_link(cp), false); |
a4cf0761 PO |
2046 | |
2047 | spin_unlock_irqrestore (&cp->lock, flags); | |
f3b197ac | 2048 | |
1da177e4 LT |
2049 | return 0; |
2050 | } | |
2051 | #endif /* CONFIG_PM */ | |
2052 | ||
2053 | static struct pci_driver cp_driver = { | |
2054 | .name = DRV_NAME, | |
2055 | .id_table = cp_pci_tbl, | |
2056 | .probe = cp_init_one, | |
2057 | .remove = cp_remove_one, | |
2058 | #ifdef CONFIG_PM | |
2059 | .resume = cp_resume, | |
2060 | .suspend = cp_suspend, | |
2061 | #endif | |
2062 | }; | |
2063 | ||
2064 | static int __init cp_init (void) | |
2065 | { | |
2066 | #ifdef MODULE | |
2067 | printk("%s", version); | |
2068 | #endif | |
29917620 | 2069 | return pci_register_driver(&cp_driver); |
1da177e4 LT |
2070 | } |
2071 | ||
2072 | static void __exit cp_exit (void) | |
2073 | { | |
2074 | pci_unregister_driver (&cp_driver); | |
2075 | } | |
2076 | ||
2077 | module_init(cp_init); | |
2078 | module_exit(cp_exit); |