[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / mtd / nand / txx9ndfmc.c

/*
 * TXx9 NAND flash memory controller driver
 * Based on RBTX49xx patch from CELF patch archive.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * (C) Copyright TOSHIBA CORPORATION 2004-2007
 * All Rights Reserved.
 */
#include <linux/err.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>
#include <linux/io.h>
#include <asm/txx9/ndfmc.h>

/* TXX9 NDFMC Registers */
#define TXX9_NDFDTR	0x00
#define TXX9_NDFMCR	0x04
#define TXX9_NDFSR	0x08
#define TXX9_NDFISR	0x0c
#define TXX9_NDFIMR	0x10
#define TXX9_NDFSPR	0x14
#define TXX9_NDFRSTR	0x18	/* not TX4939 */

/* NDFMCR : NDFMC Mode Control */
#define TXX9_NDFMCR_WE	0x80
#define TXX9_NDFMCR_ECC_ALL	0x60
#define TXX9_NDFMCR_ECC_RESET	0x60
#define TXX9_NDFMCR_ECC_READ	0x40
#define TXX9_NDFMCR_ECC_ON	0x20
#define TXX9_NDFMCR_ECC_OFF	0x00
#define TXX9_NDFMCR_CE	0x10
#define TXX9_NDFMCR_BSPRT	0x04	/* TX4925/TX4926 only */
#define TXX9_NDFMCR_ALE	0x02
#define TXX9_NDFMCR_CLE	0x01
/* TX4939 only */
#define TXX9_NDFMCR_X16	0x0400
#define TXX9_NDFMCR_DMAREQ_MASK	0x0300
#define TXX9_NDFMCR_DMAREQ_NODMA	0x0000
#define TXX9_NDFMCR_DMAREQ_128	0x0100
#define TXX9_NDFMCR_DMAREQ_256	0x0200
#define TXX9_NDFMCR_DMAREQ_512	0x0300
#define TXX9_NDFMCR_CS_MASK	0x0c
#define TXX9_NDFMCR_CS(ch)	((ch) << 2)

/* NDFMCR : NDFMC Status */
#define TXX9_NDFSR_BUSY	0x80
/* TX4939 only */
#define TXX9_NDFSR_DMARUN	0x40

/* NDFMCR : NDFMC Reset */
#define TXX9_NDFRSTR_RST	0x01

struct txx9ndfmc_priv {
	struct platform_device *dev;
	struct nand_chip chip;
	struct mtd_info mtd;
	int cs;
	const char *mtdname;
};

#define MAX_TXX9NDFMC_DEV	4
struct txx9ndfmc_drvdata {
	struct mtd_info *mtds[MAX_TXX9NDFMC_DEV];
	void __iomem *base;
	unsigned char hold;	/* in gbusclock */
	unsigned char spw;	/* in gbusclock */
	struct nand_hw_control hw_control;
};

static struct platform_device *mtd_to_platdev(struct mtd_info *mtd)
{
	struct nand_chip *chip = mtd->priv;
	struct txx9ndfmc_priv *txx9_priv = chip->priv;
	return txx9_priv->dev;
}

static void __iomem *ndregaddr(struct platform_device *dev, unsigned int reg)
{
	struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
	struct txx9ndfmc_platform_data *plat = dev->dev.platform_data;

	return drvdata->base + (reg << plat->shift);
}

static u32 txx9ndfmc_read(struct platform_device *dev, unsigned int reg)
{
	return __raw_readl(ndregaddr(dev, reg));
}

static void txx9ndfmc_write(struct platform_device *dev,
			    u32 val, unsigned int reg)
{
	__raw_writel(val, ndregaddr(dev, reg));
}

static uint8_t txx9ndfmc_read_byte(struct mtd_info *mtd)
{
	struct platform_device *dev = mtd_to_platdev(mtd);

	return txx9ndfmc_read(dev, TXX9_NDFDTR);
}

static void txx9ndfmc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
				int len)
{
	struct platform_device *dev = mtd_to_platdev(mtd);
	void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR);
	u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);

	txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_WE, TXX9_NDFMCR);
	while (len--)
		__raw_writel(*buf++, ndfdtr);
	txx9ndfmc_write(dev, mcr, TXX9_NDFMCR);
}

static void txx9ndfmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
{
	struct platform_device *dev = mtd_to_platdev(mtd);
	void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR);

	while (len--)
		*buf++ = __raw_readl(ndfdtr);
}

static void txx9ndfmc_cmd_ctrl(struct mtd_info *mtd, int cmd,
			       unsigned int ctrl)
{
	struct nand_chip *chip = mtd->priv;
	struct txx9ndfmc_priv *txx9_priv = chip->priv;
	struct platform_device *dev = txx9_priv->dev;
	struct txx9ndfmc_platform_data *plat = dev->dev.platform_data;

	if (ctrl & NAND_CTRL_CHANGE) {
		u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);

		mcr &= ~(TXX9_NDFMCR_CLE | TXX9_NDFMCR_ALE | TXX9_NDFMCR_CE);
		mcr |= ctrl & NAND_CLE ? TXX9_NDFMCR_CLE : 0;
		mcr |= ctrl & NAND_ALE ? TXX9_NDFMCR_ALE : 0;
		/* TXX9_NDFMCR_CE bit is 0:high 1:low */
		mcr |= ctrl & NAND_NCE ? TXX9_NDFMCR_CE : 0;
		if (txx9_priv->cs >= 0 && (ctrl & NAND_NCE)) {
			mcr &= ~TXX9_NDFMCR_CS_MASK;
			mcr |= TXX9_NDFMCR_CS(txx9_priv->cs);
		}
		txx9ndfmc_write(dev, mcr, TXX9_NDFMCR);
	}
	if (cmd != NAND_CMD_NONE)
		txx9ndfmc_write(dev, cmd & 0xff, TXX9_NDFDTR);
	if (plat->flags & NDFMC_PLAT_FLAG_DUMMYWRITE) {
		/* dummy write to update external latch */
		if ((ctrl & NAND_CTRL_CHANGE) && cmd == NAND_CMD_NONE)
			txx9ndfmc_write(dev, 0, TXX9_NDFDTR);
	}
	mmiowb();
}

static int txx9ndfmc_dev_ready(struct mtd_info *mtd)
{
	struct platform_device *dev = mtd_to_platdev(mtd);

	return !(txx9ndfmc_read(dev, TXX9_NDFSR) & TXX9_NDFSR_BUSY);
}

static int txx9ndfmc_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
				   uint8_t *ecc_code)
{
	struct platform_device *dev = mtd_to_platdev(mtd);
	struct nand_chip *chip = mtd->priv;
	int eccbytes;
	u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);

	mcr &= ~TXX9_NDFMCR_ECC_ALL;
	txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
	txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_READ, TXX9_NDFMCR);
	for (eccbytes = chip->ecc.bytes; eccbytes > 0; eccbytes -= 3) {
		ecc_code[1] = txx9ndfmc_read(dev, TXX9_NDFDTR);
		ecc_code[0] = txx9ndfmc_read(dev, TXX9_NDFDTR);
		ecc_code[2] = txx9ndfmc_read(dev, TXX9_NDFDTR);
		ecc_code += 3;
	}
	txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
	return 0;
}

static int txx9ndfmc_correct_data(struct mtd_info *mtd, unsigned char *buf,
		unsigned char *read_ecc, unsigned char *calc_ecc)
{
	struct nand_chip *chip = mtd->priv;
	int eccsize;
	int corrected = 0;
	int stat;

	for (eccsize = chip->ecc.size; eccsize > 0; eccsize -= 256) {
		stat = __nand_correct_data(buf, read_ecc, calc_ecc, 256);
		if (stat < 0)
			return stat;
		corrected += stat;
		buf += 256;
		read_ecc += 3;
		calc_ecc += 3;
	}
	return corrected;
}

static void txx9ndfmc_enable_hwecc(struct mtd_info *mtd, int mode)
{
	struct platform_device *dev = mtd_to_platdev(mtd);
	u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);

	mcr &= ~TXX9_NDFMCR_ECC_ALL;
	txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_RESET, TXX9_NDFMCR);
	txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
	txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_ON, TXX9_NDFMCR);
}

static void txx9ndfmc_initialize(struct platform_device *dev)
{
	struct txx9ndfmc_platform_data *plat = dev->dev.platform_data;
	struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
	int tmout = 100;

	if (plat->flags & NDFMC_PLAT_FLAG_NO_RSTR)
		; /* no NDFRSTR.  Write to NDFSPR resets the NDFMC. */
	else {
		/* reset NDFMC */
		txx9ndfmc_write(dev,
				txx9ndfmc_read(dev, TXX9_NDFRSTR) |
				TXX9_NDFRSTR_RST,
				TXX9_NDFRSTR);
		while (txx9ndfmc_read(dev, TXX9_NDFRSTR) & TXX9_NDFRSTR_RST) {
			if (--tmout == 0) {
				dev_err(&dev->dev, "reset failed.\n");
				break;
			}
			udelay(1);
		}
	}
	/* setup Hold Time, Strobe Pulse Width */
	txx9ndfmc_write(dev, (drvdata->hold << 4) | drvdata->spw, TXX9_NDFSPR);
	txx9ndfmc_write(dev,
			(plat->flags & NDFMC_PLAT_FLAG_USE_BSPRT) ?
			TXX9_NDFMCR_BSPRT : 0, TXX9_NDFMCR);
}

#define TXX9NDFMC_NS_TO_CYC(gbusclk, ns) \
	DIV_ROUND_UP((ns) * DIV_ROUND_UP(gbusclk, 1000), 1000000)

static int txx9ndfmc_nand_scan(struct mtd_info *mtd)
{
	struct nand_chip *chip = mtd->priv;
	int ret;

	ret = nand_scan_ident(mtd, 1, NULL);
	if (!ret) {
		if (mtd->writesize >= 512) {
			/* Hardware ECC 6 byte ECC per 512 Byte data */
			chip->ecc.size = 512;
			chip->ecc.bytes = 6;
		}
		ret = nand_scan_tail(mtd);
	}
	return ret;
}

static int __init txx9ndfmc_probe(struct platform_device *dev)
{
	struct txx9ndfmc_platform_data *plat = dev->dev.platform_data;
	int hold, spw;
	int i;
	struct txx9ndfmc_drvdata *drvdata;
	unsigned long gbusclk = plat->gbus_clock;
	struct resource *res;

	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
	if (!res)
		return -ENODEV;
	drvdata = devm_kzalloc(&dev->dev, sizeof(*drvdata), GFP_KERNEL);
	if (!drvdata)
		return -ENOMEM;
	drvdata->base = devm_ioremap_resource(&dev->dev, res);
	if (IS_ERR(drvdata->base))
		return PTR_ERR(drvdata->base);

	hold = plat->hold ?: 20; /* tDH */
	spw = plat->spw ?: 90; /* max(tREADID, tWP, tRP) */

	hold = TXX9NDFMC_NS_TO_CYC(gbusclk, hold);
	spw = TXX9NDFMC_NS_TO_CYC(gbusclk, spw);
	if (plat->flags & NDFMC_PLAT_FLAG_HOLDADD)
		hold -= 2;	/* actual hold time : (HOLD + 2) BUSCLK */
	spw -= 1;	/* actual wait time : (SPW + 1) BUSCLK */
	hold = clamp(hold, 1, 15);
	drvdata->hold = hold;
	spw = clamp(spw, 1, 15);
	drvdata->spw = spw;
	dev_info(&dev->dev, "CLK:%ldMHz HOLD:%d SPW:%d\n",
		 (gbusclk + 500000) / 1000000, hold, spw);

	spin_lock_init(&drvdata->hw_control.lock);
	init_waitqueue_head(&drvdata->hw_control.wq);

	platform_set_drvdata(dev, drvdata);
	txx9ndfmc_initialize(dev);

	for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) {
		struct txx9ndfmc_priv *txx9_priv;
		struct nand_chip *chip;
		struct mtd_info *mtd;

		if (!(plat->ch_mask & (1 << i)))
			continue;
		txx9_priv = kzalloc(sizeof(struct txx9ndfmc_priv),
				    GFP_KERNEL);
		if (!txx9_priv) {
			dev_err(&dev->dev, "Unable to allocate "
				"TXx9 NDFMC MTD device structure.\n");
			continue;
		}
		chip = &txx9_priv->chip;
		mtd = &txx9_priv->mtd;
		mtd->owner = THIS_MODULE;

		mtd->priv = chip;

		chip->read_byte = txx9ndfmc_read_byte;
		chip->read_buf = txx9ndfmc_read_buf;
		chip->write_buf = txx9ndfmc_write_buf;
		chip->cmd_ctrl = txx9ndfmc_cmd_ctrl;
		chip->dev_ready = txx9ndfmc_dev_ready;
		chip->ecc.calculate = txx9ndfmc_calculate_ecc;
		chip->ecc.correct = txx9ndfmc_correct_data;
		chip->ecc.hwctl = txx9ndfmc_enable_hwecc;
		chip->ecc.mode = NAND_ECC_HW;
		/* txx9ndfmc_nand_scan will overwrite ecc.size and ecc.bytes */
		chip->ecc.size = 256;
		chip->ecc.bytes = 3;
		chip->ecc.strength = 1;
		chip->chip_delay = 100;
		chip->controller = &drvdata->hw_control;

		chip->priv = txx9_priv;
		txx9_priv->dev = dev;

		if (plat->ch_mask != 1) {
			txx9_priv->cs = i;
			txx9_priv->mtdname = kasprintf(GFP_KERNEL, "%s.%u",
						       dev_name(&dev->dev), i);
		} else {
			txx9_priv->cs = -1;
			txx9_priv->mtdname = kstrdup(dev_name(&dev->dev),
						     GFP_KERNEL);
		}
		if (!txx9_priv->mtdname) {
			kfree(txx9_priv);
			dev_err(&dev->dev, "Unable to allocate MTD name.\n");
			continue;
		}
		if (plat->wide_mask & (1 << i))
			chip->options |= NAND_BUSWIDTH_16;

		if (txx9ndfmc_nand_scan(mtd)) {
			kfree(txx9_priv->mtdname);
			kfree(txx9_priv);
			continue;
		}
		mtd->name = txx9_priv->mtdname;

		mtd_device_parse_register(mtd, NULL, NULL, NULL, 0);
		drvdata->mtds[i] = mtd;
	}

	return 0;
}

static int __exit txx9ndfmc_remove(struct platform_device *dev)
{
	struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
	int i;

	platform_set_drvdata(dev, NULL);
	if (!drvdata)
		return 0;
	for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) {
		struct mtd_info *mtd = drvdata->mtds[i];
		struct nand_chip *chip;
		struct txx9ndfmc_priv *txx9_priv;

		if (!mtd)
			continue;
		chip = mtd->priv;
		txx9_priv = chip->priv;

		nand_release(mtd);
		kfree(txx9_priv->mtdname);
		kfree(txx9_priv);
	}
	return 0;
}

#ifdef CONFIG_PM
static int txx9ndfmc_resume(struct platform_device *dev)
{
	if (platform_get_drvdata(dev))
		txx9ndfmc_initialize(dev);
	return 0;
}
#else
#define txx9ndfmc_resume NULL
#endif

static struct platform_driver txx9ndfmc_driver = {
	.remove		= __exit_p(txx9ndfmc_remove),
	.resume		= txx9ndfmc_resume,
	.driver		= {
		.name	= "txx9ndfmc",
		.owner	= THIS_MODULE,
	},
};

static int __init txx9ndfmc_init(void)
{
	return platform_driver_probe(&txx9ndfmc_driver, txx9ndfmc_probe);
}

static void __exit txx9ndfmc_exit(void)
{
	platform_driver_unregister(&txx9ndfmc_driver);
}

module_init(txx9ndfmc_init);
module_exit(txx9ndfmc_exit);

MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("TXx9 SoC NAND flash controller driver");
MODULE_ALIAS("platform:txx9ndfmc");
Commit	Line	Data
64fb65ba AN	1	/*
	2	* TXx9 NAND flash memory controller driver
	3	* Based on RBTX49xx patch from CELF patch archive.
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* (C) Copyright TOSHIBA CORPORATION 2004-2007
	10	* All Rights Reserved.
	11	*/
b0de774c	12	#include <linux/err.h>
64fb65ba AN	13	#include <linux/init.h>
	14	#include <linux/slab.h>
	15	#include <linux/module.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/delay.h>
	18	#include <linux/mtd/mtd.h>
	19	#include <linux/mtd/nand.h>
	20	#include <linux/mtd/nand_ecc.h>
	21	#include <linux/mtd/partitions.h>
	22	#include <linux/io.h>
	23	#include <asm/txx9/ndfmc.h>
	24
	25	/* TXX9 NDFMC Registers */
	26	#define TXX9_NDFDTR 0x00
	27	#define TXX9_NDFMCR 0x04
	28	#define TXX9_NDFSR 0x08
	29	#define TXX9_NDFISR 0x0c
	30	#define TXX9_NDFIMR 0x10
	31	#define TXX9_NDFSPR 0x14
	32	#define TXX9_NDFRSTR 0x18 /* not TX4939 */
	33
	34	/* NDFMCR : NDFMC Mode Control */
	35	#define TXX9_NDFMCR_WE 0x80
	36	#define TXX9_NDFMCR_ECC_ALL 0x60
	37	#define TXX9_NDFMCR_ECC_RESET 0x60
	38	#define TXX9_NDFMCR_ECC_READ 0x40
	39	#define TXX9_NDFMCR_ECC_ON 0x20
	40	#define TXX9_NDFMCR_ECC_OFF 0x00
	41	#define TXX9_NDFMCR_CE 0x10
	42	#define TXX9_NDFMCR_BSPRT 0x04 /* TX4925/TX4926 only */
	43	#define TXX9_NDFMCR_ALE 0x02
	44	#define TXX9_NDFMCR_CLE 0x01
	45	/* TX4939 only */
	46	#define TXX9_NDFMCR_X16 0x0400
	47	#define TXX9_NDFMCR_DMAREQ_MASK 0x0300
	48	#define TXX9_NDFMCR_DMAREQ_NODMA 0x0000
	49	#define TXX9_NDFMCR_DMAREQ_128 0x0100
	50	#define TXX9_NDFMCR_DMAREQ_256 0x0200
	51	#define TXX9_NDFMCR_DMAREQ_512 0x0300
	52	#define TXX9_NDFMCR_CS_MASK 0x0c
	53	#define TXX9_NDFMCR_CS(ch) ((ch) << 2)
	54
	55	/* NDFMCR : NDFMC Status */
	56	#define TXX9_NDFSR_BUSY 0x80
	57	/* TX4939 only */
	58	#define TXX9_NDFSR_DMARUN 0x40
	59
	60	/* NDFMCR : NDFMC Reset */
	61	#define TXX9_NDFRSTR_RST 0x01
	62
	63	struct txx9ndfmc_priv {
	64	struct platform_device *dev;
	65	struct nand_chip chip;
	66	struct mtd_info mtd;
	67	int cs;
81933046	68	const char *mtdname;
64fb65ba AN	69	};
	70
	71	#define MAX_TXX9NDFMC_DEV 4
	72	struct txx9ndfmc_drvdata {
	73	struct mtd_info *mtds[MAX_TXX9NDFMC_DEV];
	74	void __iomem *base;
	75	unsigned char hold; /* in gbusclock */
	76	unsigned char spw; /* in gbusclock */
	77	struct nand_hw_control hw_control;
64fb65ba AN	78	};
	79
	80	static struct platform_device mtd_to_platdev(struct mtd_info mtd)
	81	{
	82	struct nand_chip *chip = mtd->priv;
	83	struct txx9ndfmc_priv *txx9_priv = chip->priv;
	84	return txx9_priv->dev;
	85	}
	86
	87	static void __iomem ndregaddr(struct platform_device dev, unsigned int reg)
	88	{
	89	struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
	90	struct txx9ndfmc_platform_data *plat = dev->dev.platform_data;
	91
	92	return drvdata->base + (reg << plat->shift);
	93	}
	94
	95	static u32 txx9ndfmc_read(struct platform_device *dev, unsigned int reg)
	96	{
	97	return __raw_readl(ndregaddr(dev, reg));
	98	}
	99
	100	static void txx9ndfmc_write(struct platform_device *dev,
	101	u32 val, unsigned int reg)
	102	{
	103	__raw_writel(val, ndregaddr(dev, reg));
	104	}
	105
	106	static uint8_t txx9ndfmc_read_byte(struct mtd_info *mtd)
	107	{
	108	struct platform_device *dev = mtd_to_platdev(mtd);
	109
	110	return txx9ndfmc_read(dev, TXX9_NDFDTR);
	111	}
	112
	113	static void txx9ndfmc_write_buf(struct mtd_info mtd, const uint8_t buf,
	114	int len)
	115	{
	116	struct platform_device *dev = mtd_to_platdev(mtd);
	117	void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR);
	118	u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
	119
	120	txx9ndfmc_write(dev, mcr \| TXX9_NDFMCR_WE, TXX9_NDFMCR);
	121	while (len--)
	122	__raw_writel(*buf++, ndfdtr);
	123	txx9ndfmc_write(dev, mcr, TXX9_NDFMCR);
	124	}
	125
	126	static void txx9ndfmc_read_buf(struct mtd_info mtd, uint8_t buf, int len)
	127	{
	128	struct platform_device *dev = mtd_to_platdev(mtd);
	129	void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR);
	130
	131	while (len--)
	132	*buf++ = __raw_readl(ndfdtr);
	133	}
	134
64fb65ba AN	135	static void txx9ndfmc_cmd_ctrl(struct mtd_info *mtd, int cmd,
	136	unsigned int ctrl)
	137	{
	138	struct nand_chip *chip = mtd->priv;
	139	struct txx9ndfmc_priv *txx9_priv = chip->priv;
	140	struct platform_device *dev = txx9_priv->dev;
	141	struct txx9ndfmc_platform_data *plat = dev->dev.platform_data;
	142
	143	if (ctrl & NAND_CTRL_CHANGE) {
	144	u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
	145
	146	mcr &= ~(TXX9_NDFMCR_CLE \| TXX9_NDFMCR_ALE \| TXX9_NDFMCR_CE);
	147	mcr \|= ctrl & NAND_CLE ? TXX9_NDFMCR_CLE : 0;
	148	mcr \|= ctrl & NAND_ALE ? TXX9_NDFMCR_ALE : 0;
	149	/* TXX9_NDFMCR_CE bit is 0:high 1:low */
	150	mcr \|= ctrl & NAND_NCE ? TXX9_NDFMCR_CE : 0;
	151	if (txx9_priv->cs >= 0 && (ctrl & NAND_NCE)) {
	152	mcr &= ~TXX9_NDFMCR_CS_MASK;
	153	mcr \|= TXX9_NDFMCR_CS(txx9_priv->cs);
	154	}
	155	txx9ndfmc_write(dev, mcr, TXX9_NDFMCR);
	156	}
	157	if (cmd != NAND_CMD_NONE)
	158	txx9ndfmc_write(dev, cmd & 0xff, TXX9_NDFDTR);
	159	if (plat->flags & NDFMC_PLAT_FLAG_DUMMYWRITE) {
	160	/* dummy write to update external latch */
	161	if ((ctrl & NAND_CTRL_CHANGE) && cmd == NAND_CMD_NONE)
	162	txx9ndfmc_write(dev, 0, TXX9_NDFDTR);
	163	}
	164	mmiowb();
	165	}
	166
	167	static int txx9ndfmc_dev_ready(struct mtd_info *mtd)
	168	{
	169	struct platform_device *dev = mtd_to_platdev(mtd);
	170
	171	return !(txx9ndfmc_read(dev, TXX9_NDFSR) & TXX9_NDFSR_BUSY);
	172	}
	173
	174	static int txx9ndfmc_calculate_ecc(struct mtd_info mtd, const uint8_t dat,
	175	uint8_t *ecc_code)
	176	{
	177	struct platform_device *dev = mtd_to_platdev(mtd);
c0cbfd0e AN	178	struct nand_chip *chip = mtd->priv;
c0cbfd0e AN	179	int eccbytes;
64fb65ba AN	180	u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
	181
	182	mcr &= ~TXX9_NDFMCR_ECC_ALL;
	183	txx9ndfmc_write(dev, mcr \| TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
	184	txx9ndfmc_write(dev, mcr \| TXX9_NDFMCR_ECC_READ, TXX9_NDFMCR);
c0cbfd0e AN	185	for (eccbytes = chip->ecc.bytes; eccbytes > 0; eccbytes -= 3) {
	186	ecc_code[1] = txx9ndfmc_read(dev, TXX9_NDFDTR);
	187	ecc_code[0] = txx9ndfmc_read(dev, TXX9_NDFDTR);
	188	ecc_code[2] = txx9ndfmc_read(dev, TXX9_NDFDTR);
	189	ecc_code += 3;
	190	}
64fb65ba AN	191	txx9ndfmc_write(dev, mcr \| TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
	192	return 0;
	193	}
	194
c0cbfd0e AN	195	static int txx9ndfmc_correct_data(struct mtd_info mtd, unsigned char buf,
	196	unsigned char read_ecc, unsigned char calc_ecc)
	197	{
	198	struct nand_chip *chip = mtd->priv;
	199	int eccsize;
	200	int corrected = 0;
	201	int stat;
	202
	203	for (eccsize = chip->ecc.size; eccsize > 0; eccsize -= 256) {
	204	stat = __nand_correct_data(buf, read_ecc, calc_ecc, 256);
	205	if (stat < 0)
	206	return stat;
	207	corrected += stat;
	208	buf += 256;
	209	read_ecc += 3;
	210	calc_ecc += 3;
	211	}
	212	return corrected;
	213	}
	214
64fb65ba AN	215	static void txx9ndfmc_enable_hwecc(struct mtd_info *mtd, int mode)
	216	{
	217	struct platform_device *dev = mtd_to_platdev(mtd);
	218	u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR);
	219
	220	mcr &= ~TXX9_NDFMCR_ECC_ALL;
	221	txx9ndfmc_write(dev, mcr \| TXX9_NDFMCR_ECC_RESET, TXX9_NDFMCR);
	222	txx9ndfmc_write(dev, mcr \| TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR);
	223	txx9ndfmc_write(dev, mcr \| TXX9_NDFMCR_ECC_ON, TXX9_NDFMCR);
	224	}
	225
	226	static void txx9ndfmc_initialize(struct platform_device *dev)
	227	{
	228	struct txx9ndfmc_platform_data *plat = dev->dev.platform_data;
	229	struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
	230	int tmout = 100;
	231
	232	if (plat->flags & NDFMC_PLAT_FLAG_NO_RSTR)
	233	; /* no NDFRSTR. Write to NDFSPR resets the NDFMC. */
	234	else {
	235	/* reset NDFMC */
	236	txx9ndfmc_write(dev,
	237	txx9ndfmc_read(dev, TXX9_NDFRSTR) \|
	238	TXX9_NDFRSTR_RST,
	239	TXX9_NDFRSTR);
	240	while (txx9ndfmc_read(dev, TXX9_NDFRSTR) & TXX9_NDFRSTR_RST) {
	241	if (--tmout == 0) {
	242	dev_err(&dev->dev, "reset failed.\n");
	243	break;
	244	}
	245	udelay(1);
	246	}
	247	}
	248	/* setup Hold Time, Strobe Pulse Width */
	249	txx9ndfmc_write(dev, (drvdata->hold << 4) \| drvdata->spw, TXX9_NDFSPR);
	250	txx9ndfmc_write(dev,
	251	(plat->flags & NDFMC_PLAT_FLAG_USE_BSPRT) ?
	252	TXX9_NDFMCR_BSPRT : 0, TXX9_NDFMCR);
	253	}
	254
	255	#define TXX9NDFMC_NS_TO_CYC(gbusclk, ns) \
	256	DIV_ROUND_UP((ns) * DIV_ROUND_UP(gbusclk, 1000), 1000000)
	257
c0cbfd0e AN	258	static int txx9ndfmc_nand_scan(struct mtd_info *mtd)
	259	{
	260	struct nand_chip *chip = mtd->priv;
	261	int ret;
	262
5e81e88a	263	ret = nand_scan_ident(mtd, 1, NULL);
c0cbfd0e AN	264	if (!ret) {
c0cbfd0e AN	265	if (mtd->writesize >= 512) {
24ac9a94 RR	266	/* Hardware ECC 6 byte ECC per 512 Byte data */
	267	chip->ecc.size = 512;
	268	chip->ecc.bytes = 6;
c0cbfd0e AN	269	}
	270	ret = nand_scan_tail(mtd);
	271	}
	272	return ret;
	273	}
	274
64fb65ba AN	275	static int __init txx9ndfmc_probe(struct platform_device *dev)
	276	{
	277	struct txx9ndfmc_platform_data *plat = dev->dev.platform_data;
64fb65ba AN	278	int hold, spw;
	279	int i;
	280	struct txx9ndfmc_drvdata *drvdata;
	281	unsigned long gbusclk = plat->gbus_clock;
	282	struct resource *res;
	283
	284	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
	285	if (!res)
	286	return -ENODEV;
	287	drvdata = devm_kzalloc(&dev->dev, sizeof(*drvdata), GFP_KERNEL);
	288	if (!drvdata)
	289	return -ENOMEM;
b0de774c TR	290	drvdata->base = devm_ioremap_resource(&dev->dev, res);
	291	if (IS_ERR(drvdata->base))
	292	return PTR_ERR(drvdata->base);
64fb65ba AN	293
	294	hold = plat->hold ?: 20; /* tDH */
	295	spw = plat->spw ?: 90; /* max(tREADID, tWP, tRP) */
	296
	297	hold = TXX9NDFMC_NS_TO_CYC(gbusclk, hold);
	298	spw = TXX9NDFMC_NS_TO_CYC(gbusclk, spw);
	299	if (plat->flags & NDFMC_PLAT_FLAG_HOLDADD)
	300	hold -= 2; /* actual hold time : (HOLD + 2) BUSCLK */
	301	spw -= 1; /* actual wait time : (SPW + 1) BUSCLK */
	302	hold = clamp(hold, 1, 15);
	303	drvdata->hold = hold;
	304	spw = clamp(spw, 1, 15);
	305	drvdata->spw = spw;
	306	dev_info(&dev->dev, "CLK:%ldMHz HOLD:%d SPW:%d\n",
	307	(gbusclk + 500000) / 1000000, hold, spw);
	308
	309	spin_lock_init(&drvdata->hw_control.lock);
	310	init_waitqueue_head(&drvdata->hw_control.wq);
	311
	312	platform_set_drvdata(dev, drvdata);
	313	txx9ndfmc_initialize(dev);
	314
	315	for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) {
	316	struct txx9ndfmc_priv *txx9_priv;
	317	struct nand_chip *chip;
	318	struct mtd_info *mtd;
64fb65ba AN	319
	320	if (!(plat->ch_mask & (1 << i)))
	321	continue;
	322	txx9_priv = kzalloc(sizeof(struct txx9ndfmc_priv),
	323	GFP_KERNEL);
	324	if (!txx9_priv) {
	325	dev_err(&dev->dev, "Unable to allocate "
	326	"TXx9 NDFMC MTD device structure.\n");
	327	continue;
	328	}
	329	chip = &txx9_priv->chip;
	330	mtd = &txx9_priv->mtd;
	331	mtd->owner = THIS_MODULE;
	332
	333	mtd->priv = chip;
	334
	335	chip->read_byte = txx9ndfmc_read_byte;
	336	chip->read_buf = txx9ndfmc_read_buf;
	337	chip->write_buf = txx9ndfmc_write_buf;
64fb65ba AN	338	chip->cmd_ctrl = txx9ndfmc_cmd_ctrl;
	339	chip->dev_ready = txx9ndfmc_dev_ready;
	340	chip->ecc.calculate = txx9ndfmc_calculate_ecc;
c0cbfd0e	341	chip->ecc.correct = txx9ndfmc_correct_data;
64fb65ba AN	342	chip->ecc.hwctl = txx9ndfmc_enable_hwecc;
64fb65ba AN	343	chip->ecc.mode = NAND_ECC_HW;
c0cbfd0e	344	/* txx9ndfmc_nand_scan will overwrite ecc.size and ecc.bytes */
64fb65ba AN	345	chip->ecc.size = 256;
64fb65ba AN	346	chip->ecc.bytes = 3;
6a918bad	347	chip->ecc.strength = 1;
64fb65ba AN	348	chip->chip_delay = 100;
	349	chip->controller = &drvdata->hw_control;
	350
	351	chip->priv = txx9_priv;
	352	txx9_priv->dev = dev;
	353
	354	if (plat->ch_mask != 1) {
	355	txx9_priv->cs = i;
81933046 DW	356	txx9_priv->mtdname = kasprintf(GFP_KERNEL, "%s.%u",
81933046 DW	357	dev_name(&dev->dev), i);
64fb65ba AN	358	} else {
64fb65ba AN	359	txx9_priv->cs = -1;
272023df AN	360	txx9_priv->mtdname = kstrdup(dev_name(&dev->dev),
	361	GFP_KERNEL);
	362	}
	363	if (!txx9_priv->mtdname) {
	364	kfree(txx9_priv);
	365	dev_err(&dev->dev, "Unable to allocate MTD name.\n");
	366	continue;
64fb65ba AN	367	}
	368	if (plat->wide_mask & (1 << i))
	369	chip->options \|= NAND_BUSWIDTH_16;
	370
c0cbfd0e	371	if (txx9ndfmc_nand_scan(mtd)) {
272023df	372	kfree(txx9_priv->mtdname);
64fb65ba AN	373	kfree(txx9_priv);
	374	continue;
	375	}
	376	mtd->name = txx9_priv->mtdname;
	377
42d7fbe2	378	mtd_device_parse_register(mtd, NULL, NULL, NULL, 0);
64fb65ba AN	379	drvdata->mtds[i] = mtd;
	380	}
	381
	382	return 0;
	383	}
	384
	385	static int __exit txx9ndfmc_remove(struct platform_device *dev)
	386	{
	387	struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev);
	388	int i;
	389
	390	platform_set_drvdata(dev, NULL);
	391	if (!drvdata)
	392	return 0;
	393	for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) {
	394	struct mtd_info *mtd = drvdata->mtds[i];
	395	struct nand_chip *chip;
	396	struct txx9ndfmc_priv *txx9_priv;
	397
	398	if (!mtd)
	399	continue;
	400	chip = mtd->priv;
	401	txx9_priv = chip->priv;
	402
6eb4feff	403	nand_release(mtd);
272023df	404	kfree(txx9_priv->mtdname);
64fb65ba AN	405	kfree(txx9_priv);
	406	}
	407	return 0;
	408	}
	409
	410	#ifdef CONFIG_PM
	411	static int txx9ndfmc_resume(struct platform_device *dev)
	412	{
	413	if (platform_get_drvdata(dev))
	414	txx9ndfmc_initialize(dev);
	415	return 0;
	416	}
	417	#else
	418	#define txx9ndfmc_resume NULL
	419	#endif
	420
	421	static struct platform_driver txx9ndfmc_driver = {
	422	.remove = __exit_p(txx9ndfmc_remove),
	423	.resume = txx9ndfmc_resume,
	424	.driver = {
	425	.name = "txx9ndfmc",
	426	.owner = THIS_MODULE,
	427	},
	428	};
	429
	430	static int __init txx9ndfmc_init(void)
	431	{
	432	return platform_driver_probe(&txx9ndfmc_driver, txx9ndfmc_probe);
	433	}
	434
	435	static void __exit txx9ndfmc_exit(void)
	436	{
	437	platform_driver_unregister(&txx9ndfmc_driver);
	438	}
	439
	440	module_init(txx9ndfmc_init);
	441	module_exit(txx9ndfmc_exit);
	442
	443	MODULE_LICENSE("GPL");
	444	MODULE_DESCRIPTION("TXx9 SoC NAND flash controller driver");
	445	MODULE_ALIAS("platform:txx9ndfmc");