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1da177e4 LT |
1 | /* linux/drivers/mtd/nand/s3c2410.c |
2 | * | |
a4f957f1 | 3 | * Copyright (c) 2004,2005 Simtec Electronics |
fdf2fd52 BD |
4 | * http://www.simtec.co.uk/products/SWLINUX/ |
5 | * Ben Dooks <ben@simtec.co.uk> | |
1da177e4 | 6 | * |
a4f957f1 | 7 | * Samsung S3C2410/S3C240 NAND driver |
1da177e4 LT |
8 | * |
9 | * Changelog: | |
10 | * 21-Sep-2004 BJD Initial version | |
11 | * 23-Sep-2004 BJD Mulitple device support | |
12 | * 28-Sep-2004 BJD Fixed ECC placement for Hardware mode | |
13 | * 12-Oct-2004 BJD Fixed errors in use of platform data | |
3e4ef3bb BD |
14 | * 18-Feb-2005 BJD Fix sparse errors |
15 | * 14-Mar-2005 BJD Applied tglx's code reduction patch | |
a4f957f1 BD |
16 | * 02-May-2005 BJD Fixed s3c2440 support |
17 | * 02-May-2005 BJD Reduced hwcontrol decode | |
18 | * 20-Jun-2005 BJD Updated s3c2440 support, fixed timing bug | |
fb8d82a8 | 19 | * 08-Jul-2005 BJD Fix OOPS when no platform data supplied |
cfd320fb | 20 | * 20-Oct-2005 BJD Fix timing calculation bug |
1da177e4 | 21 | * |
61b03bd7 | 22 | * $Id: s3c2410.c,v 1.20 2005/11/07 11:14:31 gleixner Exp $ |
1da177e4 LT |
23 | * |
24 | * This program is free software; you can redistribute it and/or modify | |
25 | * it under the terms of the GNU General Public License as published by | |
26 | * the Free Software Foundation; either version 2 of the License, or | |
27 | * (at your option) any later version. | |
28 | * | |
29 | * This program is distributed in the hope that it will be useful, | |
30 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
31 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
32 | * GNU General Public License for more details. | |
33 | * | |
34 | * You should have received a copy of the GNU General Public License | |
35 | * along with this program; if not, write to the Free Software | |
36 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
37 | */ | |
38 | ||
39 | #include <config/mtd/nand/s3c2410/hwecc.h> | |
40 | #include <config/mtd/nand/s3c2410/debug.h> | |
41 | ||
42 | #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG | |
43 | #define DEBUG | |
44 | #endif | |
45 | ||
46 | #include <linux/module.h> | |
47 | #include <linux/types.h> | |
48 | #include <linux/init.h> | |
49 | #include <linux/kernel.h> | |
50 | #include <linux/string.h> | |
51 | #include <linux/ioport.h> | |
d052d1be | 52 | #include <linux/platform_device.h> |
1da177e4 LT |
53 | #include <linux/delay.h> |
54 | #include <linux/err.h> | |
4e57b681 | 55 | #include <linux/slab.h> |
1da177e4 LT |
56 | |
57 | #include <linux/mtd/mtd.h> | |
58 | #include <linux/mtd/nand.h> | |
59 | #include <linux/mtd/nand_ecc.h> | |
60 | #include <linux/mtd/partitions.h> | |
61 | ||
62 | #include <asm/io.h> | |
1da177e4 LT |
63 | #include <asm/hardware/clock.h> |
64 | ||
65 | #include <asm/arch/regs-nand.h> | |
66 | #include <asm/arch/nand.h> | |
67 | ||
68 | #define PFX "s3c2410-nand: " | |
69 | ||
70 | #ifdef CONFIG_MTD_NAND_S3C2410_HWECC | |
71 | static int hardware_ecc = 1; | |
72 | #else | |
73 | static int hardware_ecc = 0; | |
74 | #endif | |
75 | ||
76 | /* new oob placement block for use with hardware ecc generation | |
77 | */ | |
78 | ||
79 | static struct nand_oobinfo nand_hw_eccoob = { | |
fdf2fd52 BD |
80 | .useecc = MTD_NANDECC_AUTOPLACE, |
81 | .eccbytes = 3, | |
82 | .eccpos = {0, 1, 2 }, | |
83 | .oobfree = { {8, 8} } | |
1da177e4 LT |
84 | }; |
85 | ||
86 | /* controller and mtd information */ | |
87 | ||
88 | struct s3c2410_nand_info; | |
89 | ||
90 | struct s3c2410_nand_mtd { | |
91 | struct mtd_info mtd; | |
92 | struct nand_chip chip; | |
93 | struct s3c2410_nand_set *set; | |
94 | struct s3c2410_nand_info *info; | |
95 | int scan_res; | |
96 | }; | |
97 | ||
98 | /* overview of the s3c2410 nand state */ | |
99 | ||
100 | struct s3c2410_nand_info { | |
101 | /* mtd info */ | |
102 | struct nand_hw_control controller; | |
103 | struct s3c2410_nand_mtd *mtds; | |
104 | struct s3c2410_platform_nand *platform; | |
105 | ||
106 | /* device info */ | |
107 | struct device *device; | |
108 | struct resource *area; | |
109 | struct clk *clk; | |
fdf2fd52 | 110 | void __iomem *regs; |
1da177e4 | 111 | int mtd_count; |
a4f957f1 BD |
112 | |
113 | unsigned char is_s3c2440; | |
1da177e4 LT |
114 | }; |
115 | ||
116 | /* conversion functions */ | |
117 | ||
118 | static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd) | |
119 | { | |
120 | return container_of(mtd, struct s3c2410_nand_mtd, mtd); | |
121 | } | |
122 | ||
123 | static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd) | |
124 | { | |
125 | return s3c2410_nand_mtd_toours(mtd)->info; | |
126 | } | |
127 | ||
128 | static struct s3c2410_nand_info *to_nand_info(struct device *dev) | |
129 | { | |
130 | return dev_get_drvdata(dev); | |
131 | } | |
132 | ||
133 | static struct s3c2410_platform_nand *to_nand_plat(struct device *dev) | |
134 | { | |
135 | return dev->platform_data; | |
136 | } | |
137 | ||
138 | /* timing calculations */ | |
139 | ||
cfd320fb | 140 | #define NS_IN_KHZ 1000000 |
1da177e4 LT |
141 | |
142 | static int s3c2410_nand_calc_rate(int wanted, unsigned long clk, int max) | |
143 | { | |
144 | int result; | |
145 | ||
cfd320fb | 146 | result = (wanted * clk) / NS_IN_KHZ; |
1da177e4 LT |
147 | result++; |
148 | ||
149 | pr_debug("result %d from %ld, %d\n", result, clk, wanted); | |
150 | ||
151 | if (result > max) { | |
152 | printk("%d ns is too big for current clock rate %ld\n", | |
153 | wanted, clk); | |
154 | return -1; | |
155 | } | |
156 | ||
157 | if (result < 1) | |
158 | result = 1; | |
159 | ||
160 | return result; | |
161 | } | |
162 | ||
cfd320fb | 163 | #define to_ns(ticks,clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk)) |
1da177e4 LT |
164 | |
165 | /* controller setup */ | |
166 | ||
61b03bd7 | 167 | static int s3c2410_nand_inithw(struct s3c2410_nand_info *info, |
1da177e4 LT |
168 | struct device *dev) |
169 | { | |
170 | struct s3c2410_platform_nand *plat = to_nand_plat(dev); | |
1da177e4 | 171 | unsigned long clkrate = clk_get_rate(info->clk); |
cfd320fb | 172 | int tacls, twrph0, twrph1; |
1da177e4 LT |
173 | unsigned long cfg; |
174 | ||
175 | /* calculate the timing information for the controller */ | |
176 | ||
cfd320fb BD |
177 | clkrate /= 1000; /* turn clock into kHz for ease of use */ |
178 | ||
1da177e4 | 179 | if (plat != NULL) { |
a4f957f1 | 180 | tacls = s3c2410_nand_calc_rate(plat->tacls, clkrate, 4); |
1da177e4 LT |
181 | twrph0 = s3c2410_nand_calc_rate(plat->twrph0, clkrate, 8); |
182 | twrph1 = s3c2410_nand_calc_rate(plat->twrph1, clkrate, 8); | |
183 | } else { | |
184 | /* default timings */ | |
a4f957f1 | 185 | tacls = 4; |
1da177e4 LT |
186 | twrph0 = 8; |
187 | twrph1 = 8; | |
188 | } | |
61b03bd7 | 189 | |
1da177e4 LT |
190 | if (tacls < 0 || twrph0 < 0 || twrph1 < 0) { |
191 | printk(KERN_ERR PFX "cannot get timings suitable for board\n"); | |
192 | return -EINVAL; | |
193 | } | |
194 | ||
cfd320fb BD |
195 | printk(KERN_INFO PFX "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n", |
196 | tacls, to_ns(tacls, clkrate), | |
61b03bd7 | 197 | twrph0, to_ns(twrph0, clkrate), |
cfd320fb | 198 | twrph1, to_ns(twrph1, clkrate)); |
1da177e4 | 199 | |
a4f957f1 BD |
200 | if (!info->is_s3c2440) { |
201 | cfg = S3C2410_NFCONF_EN; | |
202 | cfg |= S3C2410_NFCONF_TACLS(tacls-1); | |
203 | cfg |= S3C2410_NFCONF_TWRPH0(twrph0-1); | |
204 | cfg |= S3C2410_NFCONF_TWRPH1(twrph1-1); | |
205 | } else { | |
206 | cfg = S3C2440_NFCONF_TACLS(tacls-1); | |
207 | cfg |= S3C2440_NFCONF_TWRPH0(twrph0-1); | |
208 | cfg |= S3C2440_NFCONF_TWRPH1(twrph1-1); | |
209 | } | |
1da177e4 LT |
210 | |
211 | pr_debug(PFX "NF_CONF is 0x%lx\n", cfg); | |
212 | ||
213 | writel(cfg, info->regs + S3C2410_NFCONF); | |
214 | return 0; | |
215 | } | |
216 | ||
217 | /* select chip */ | |
218 | ||
219 | static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip) | |
220 | { | |
221 | struct s3c2410_nand_info *info; | |
61b03bd7 | 222 | struct s3c2410_nand_mtd *nmtd; |
1da177e4 | 223 | struct nand_chip *this = mtd->priv; |
a4f957f1 | 224 | void __iomem *reg; |
1da177e4 | 225 | unsigned long cur; |
a4f957f1 | 226 | unsigned long bit; |
1da177e4 LT |
227 | |
228 | nmtd = this->priv; | |
229 | info = nmtd->info; | |
230 | ||
a4f957f1 BD |
231 | bit = (info->is_s3c2440) ? S3C2440_NFCONT_nFCE : S3C2410_NFCONF_nFCE; |
232 | reg = info->regs+((info->is_s3c2440) ? S3C2440_NFCONT:S3C2410_NFCONF); | |
233 | ||
234 | cur = readl(reg); | |
1da177e4 LT |
235 | |
236 | if (chip == -1) { | |
a4f957f1 | 237 | cur |= bit; |
1da177e4 | 238 | } else { |
fb8d82a8 | 239 | if (nmtd->set != NULL && chip > nmtd->set->nr_chips) { |
1da177e4 LT |
240 | printk(KERN_ERR PFX "chip %d out of range\n", chip); |
241 | return; | |
242 | } | |
243 | ||
244 | if (info->platform != NULL) { | |
245 | if (info->platform->select_chip != NULL) | |
246 | (info->platform->select_chip)(nmtd->set, chip); | |
247 | } | |
248 | ||
a4f957f1 | 249 | cur &= ~bit; |
1da177e4 LT |
250 | } |
251 | ||
a4f957f1 | 252 | writel(cur, reg); |
1da177e4 LT |
253 | } |
254 | ||
61b03bd7 | 255 | /* command and control functions |
a4f957f1 BD |
256 | * |
257 | * Note, these all use tglx's method of changing the IO_ADDR_W field | |
258 | * to make the code simpler, and use the nand layer's code to issue the | |
259 | * command and address sequences via the proper IO ports. | |
260 | * | |
261 | */ | |
1da177e4 LT |
262 | |
263 | static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd) | |
264 | { | |
265 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
3e4ef3bb | 266 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
267 | |
268 | switch (cmd) { | |
269 | case NAND_CTL_SETNCE: | |
a4f957f1 BD |
270 | case NAND_CTL_CLRNCE: |
271 | printk(KERN_ERR "%s: called for NCE\n", __FUNCTION__); | |
272 | break; | |
273 | ||
274 | case NAND_CTL_SETCLE: | |
275 | chip->IO_ADDR_W = info->regs + S3C2410_NFCMD; | |
276 | break; | |
277 | ||
278 | case NAND_CTL_SETALE: | |
279 | chip->IO_ADDR_W = info->regs + S3C2410_NFADDR; | |
280 | break; | |
281 | ||
282 | /* NAND_CTL_CLRCLE: */ | |
283 | /* NAND_CTL_CLRALE: */ | |
284 | default: | |
285 | chip->IO_ADDR_W = info->regs + S3C2410_NFDATA; | |
1da177e4 | 286 | break; |
a4f957f1 BD |
287 | } |
288 | } | |
289 | ||
290 | /* command and control functions */ | |
291 | ||
292 | static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd) | |
293 | { | |
294 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
295 | struct nand_chip *chip = mtd->priv; | |
1da177e4 | 296 | |
a4f957f1 BD |
297 | switch (cmd) { |
298 | case NAND_CTL_SETNCE: | |
1da177e4 | 299 | case NAND_CTL_CLRNCE: |
a4f957f1 | 300 | printk(KERN_ERR "%s: called for NCE\n", __FUNCTION__); |
1da177e4 LT |
301 | break; |
302 | ||
1da177e4 | 303 | case NAND_CTL_SETCLE: |
a4f957f1 | 304 | chip->IO_ADDR_W = info->regs + S3C2440_NFCMD; |
1da177e4 | 305 | break; |
1da177e4 | 306 | |
3e4ef3bb | 307 | case NAND_CTL_SETALE: |
a4f957f1 | 308 | chip->IO_ADDR_W = info->regs + S3C2440_NFADDR; |
3e4ef3bb | 309 | break; |
1da177e4 | 310 | |
3e4ef3bb BD |
311 | /* NAND_CTL_CLRCLE: */ |
312 | /* NAND_CTL_CLRALE: */ | |
1da177e4 | 313 | default: |
a4f957f1 | 314 | chip->IO_ADDR_W = info->regs + S3C2440_NFDATA; |
3e4ef3bb | 315 | break; |
1da177e4 | 316 | } |
1da177e4 LT |
317 | } |
318 | ||
1da177e4 LT |
319 | /* s3c2410_nand_devready() |
320 | * | |
321 | * returns 0 if the nand is busy, 1 if it is ready | |
322 | */ | |
323 | ||
324 | static int s3c2410_nand_devready(struct mtd_info *mtd) | |
325 | { | |
326 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
61b03bd7 | 327 | |
a4f957f1 BD |
328 | if (info->is_s3c2440) |
329 | return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY; | |
1da177e4 LT |
330 | return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY; |
331 | } | |
332 | ||
a4f957f1 | 333 | |
1da177e4 LT |
334 | /* ECC handling functions */ |
335 | ||
336 | static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat, | |
337 | u_char *read_ecc, u_char *calc_ecc) | |
338 | { | |
339 | pr_debug("s3c2410_nand_correct_data(%p,%p,%p,%p)\n", | |
340 | mtd, dat, read_ecc, calc_ecc); | |
341 | ||
342 | pr_debug("eccs: read %02x,%02x,%02x vs calc %02x,%02x,%02x\n", | |
343 | read_ecc[0], read_ecc[1], read_ecc[2], | |
344 | calc_ecc[0], calc_ecc[1], calc_ecc[2]); | |
345 | ||
346 | if (read_ecc[0] == calc_ecc[0] && | |
347 | read_ecc[1] == calc_ecc[1] && | |
61b03bd7 | 348 | read_ecc[2] == calc_ecc[2]) |
1da177e4 LT |
349 | return 0; |
350 | ||
351 | /* we curently have no method for correcting the error */ | |
352 | ||
353 | return -1; | |
354 | } | |
355 | ||
a4f957f1 BD |
356 | /* ECC functions |
357 | * | |
358 | * These allow the s3c2410 and s3c2440 to use the controller's ECC | |
359 | * generator block to ECC the data as it passes through] | |
360 | */ | |
361 | ||
1da177e4 LT |
362 | static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode) |
363 | { | |
364 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
365 | unsigned long ctrl; | |
366 | ||
367 | ctrl = readl(info->regs + S3C2410_NFCONF); | |
368 | ctrl |= S3C2410_NFCONF_INITECC; | |
369 | writel(ctrl, info->regs + S3C2410_NFCONF); | |
370 | } | |
371 | ||
a4f957f1 BD |
372 | static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode) |
373 | { | |
374 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
375 | unsigned long ctrl; | |
376 | ||
377 | ctrl = readl(info->regs + S3C2440_NFCONT); | |
378 | writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT); | |
379 | } | |
380 | ||
1da177e4 LT |
381 | static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, |
382 | const u_char *dat, u_char *ecc_code) | |
383 | { | |
384 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
385 | ||
386 | ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0); | |
387 | ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1); | |
388 | ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2); | |
389 | ||
390 | pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", | |
391 | ecc_code[0], ecc_code[1], ecc_code[2]); | |
392 | ||
393 | return 0; | |
394 | } | |
395 | ||
396 | ||
a4f957f1 BD |
397 | static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, |
398 | const u_char *dat, u_char *ecc_code) | |
399 | { | |
400 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
401 | unsigned long ecc = readl(info->regs + S3C2440_NFMECC0); | |
402 | ||
403 | ecc_code[0] = ecc; | |
404 | ecc_code[1] = ecc >> 8; | |
405 | ecc_code[2] = ecc >> 16; | |
406 | ||
407 | pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", | |
408 | ecc_code[0], ecc_code[1], ecc_code[2]); | |
409 | ||
410 | return 0; | |
411 | } | |
412 | ||
413 | ||
414 | /* over-ride the standard functions for a little more speed. We can | |
415 | * use read/write block to move the data buffers to/from the controller | |
416 | */ | |
1da177e4 LT |
417 | |
418 | static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) | |
419 | { | |
420 | struct nand_chip *this = mtd->priv; | |
421 | readsb(this->IO_ADDR_R, buf, len); | |
422 | } | |
423 | ||
424 | static void s3c2410_nand_write_buf(struct mtd_info *mtd, | |
425 | const u_char *buf, int len) | |
426 | { | |
427 | struct nand_chip *this = mtd->priv; | |
428 | writesb(this->IO_ADDR_W, buf, len); | |
429 | } | |
430 | ||
431 | /* device management functions */ | |
432 | ||
433 | static int s3c2410_nand_remove(struct device *dev) | |
434 | { | |
435 | struct s3c2410_nand_info *info = to_nand_info(dev); | |
436 | ||
437 | dev_set_drvdata(dev, NULL); | |
438 | ||
61b03bd7 | 439 | if (info == NULL) |
1da177e4 LT |
440 | return 0; |
441 | ||
442 | /* first thing we need to do is release all our mtds | |
443 | * and their partitions, then go through freeing the | |
61b03bd7 | 444 | * resources used |
1da177e4 | 445 | */ |
61b03bd7 | 446 | |
1da177e4 LT |
447 | if (info->mtds != NULL) { |
448 | struct s3c2410_nand_mtd *ptr = info->mtds; | |
449 | int mtdno; | |
450 | ||
451 | for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) { | |
452 | pr_debug("releasing mtd %d (%p)\n", mtdno, ptr); | |
453 | nand_release(&ptr->mtd); | |
454 | } | |
455 | ||
456 | kfree(info->mtds); | |
457 | } | |
458 | ||
459 | /* free the common resources */ | |
460 | ||
461 | if (info->clk != NULL && !IS_ERR(info->clk)) { | |
462 | clk_disable(info->clk); | |
463 | clk_unuse(info->clk); | |
464 | clk_put(info->clk); | |
465 | } | |
466 | ||
467 | if (info->regs != NULL) { | |
468 | iounmap(info->regs); | |
469 | info->regs = NULL; | |
470 | } | |
471 | ||
472 | if (info->area != NULL) { | |
473 | release_resource(info->area); | |
474 | kfree(info->area); | |
475 | info->area = NULL; | |
476 | } | |
477 | ||
478 | kfree(info); | |
479 | ||
480 | return 0; | |
481 | } | |
482 | ||
483 | #ifdef CONFIG_MTD_PARTITIONS | |
484 | static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info, | |
485 | struct s3c2410_nand_mtd *mtd, | |
486 | struct s3c2410_nand_set *set) | |
487 | { | |
488 | if (set == NULL) | |
489 | return add_mtd_device(&mtd->mtd); | |
490 | ||
491 | if (set->nr_partitions > 0 && set->partitions != NULL) { | |
492 | return add_mtd_partitions(&mtd->mtd, | |
493 | set->partitions, | |
494 | set->nr_partitions); | |
495 | } | |
496 | ||
497 | return add_mtd_device(&mtd->mtd); | |
498 | } | |
499 | #else | |
500 | static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info, | |
501 | struct s3c2410_nand_mtd *mtd, | |
502 | struct s3c2410_nand_set *set) | |
503 | { | |
504 | return add_mtd_device(&mtd->mtd); | |
505 | } | |
506 | #endif | |
507 | ||
508 | /* s3c2410_nand_init_chip | |
509 | * | |
61b03bd7 | 510 | * init a single instance of an chip |
1da177e4 LT |
511 | */ |
512 | ||
513 | static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info, | |
514 | struct s3c2410_nand_mtd *nmtd, | |
515 | struct s3c2410_nand_set *set) | |
516 | { | |
517 | struct nand_chip *chip = &nmtd->chip; | |
518 | ||
fdf2fd52 BD |
519 | chip->IO_ADDR_R = info->regs + S3C2410_NFDATA; |
520 | chip->IO_ADDR_W = info->regs + S3C2410_NFDATA; | |
1da177e4 LT |
521 | chip->hwcontrol = s3c2410_nand_hwcontrol; |
522 | chip->dev_ready = s3c2410_nand_devready; | |
1da177e4 LT |
523 | chip->write_buf = s3c2410_nand_write_buf; |
524 | chip->read_buf = s3c2410_nand_read_buf; | |
525 | chip->select_chip = s3c2410_nand_select_chip; | |
526 | chip->chip_delay = 50; | |
527 | chip->priv = nmtd; | |
528 | chip->options = 0; | |
529 | chip->controller = &info->controller; | |
530 | ||
a4f957f1 BD |
531 | if (info->is_s3c2440) { |
532 | chip->IO_ADDR_R = info->regs + S3C2440_NFDATA; | |
533 | chip->IO_ADDR_W = info->regs + S3C2440_NFDATA; | |
534 | chip->hwcontrol = s3c2440_nand_hwcontrol; | |
535 | } | |
536 | ||
1da177e4 LT |
537 | nmtd->info = info; |
538 | nmtd->mtd.priv = chip; | |
539 | nmtd->set = set; | |
540 | ||
541 | if (hardware_ecc) { | |
542 | chip->correct_data = s3c2410_nand_correct_data; | |
543 | chip->enable_hwecc = s3c2410_nand_enable_hwecc; | |
544 | chip->calculate_ecc = s3c2410_nand_calculate_ecc; | |
545 | chip->eccmode = NAND_ECC_HW3_512; | |
546 | chip->autooob = &nand_hw_eccoob; | |
a4f957f1 BD |
547 | |
548 | if (info->is_s3c2440) { | |
549 | chip->enable_hwecc = s3c2440_nand_enable_hwecc; | |
550 | chip->calculate_ecc = s3c2440_nand_calculate_ecc; | |
551 | } | |
1da177e4 LT |
552 | } else { |
553 | chip->eccmode = NAND_ECC_SOFT; | |
554 | } | |
555 | } | |
556 | ||
557 | /* s3c2410_nand_probe | |
558 | * | |
559 | * called by device layer when it finds a device matching | |
560 | * one our driver can handled. This code checks to see if | |
561 | * it can allocate all necessary resources then calls the | |
562 | * nand layer to look for devices | |
563 | */ | |
564 | ||
a4f957f1 | 565 | static int s3c24xx_nand_probe(struct device *dev, int is_s3c2440) |
1da177e4 LT |
566 | { |
567 | struct platform_device *pdev = to_platform_device(dev); | |
568 | struct s3c2410_platform_nand *plat = to_nand_plat(dev); | |
569 | struct s3c2410_nand_info *info; | |
570 | struct s3c2410_nand_mtd *nmtd; | |
571 | struct s3c2410_nand_set *sets; | |
572 | struct resource *res; | |
573 | int err = 0; | |
574 | int size; | |
575 | int nr_sets; | |
576 | int setno; | |
577 | ||
578 | pr_debug("s3c2410_nand_probe(%p)\n", dev); | |
579 | ||
580 | info = kmalloc(sizeof(*info), GFP_KERNEL); | |
581 | if (info == NULL) { | |
d5745041 | 582 | dev_err(dev, "no memory for flash info\n"); |
1da177e4 LT |
583 | err = -ENOMEM; |
584 | goto exit_error; | |
585 | } | |
586 | ||
587 | memzero(info, sizeof(*info)); | |
588 | dev_set_drvdata(dev, info); | |
589 | ||
590 | spin_lock_init(&info->controller.lock); | |
a4f957f1 | 591 | init_waitqueue_head(&info->controller.wq); |
1da177e4 LT |
592 | |
593 | /* get the clock source and enable it */ | |
594 | ||
595 | info->clk = clk_get(dev, "nand"); | |
596 | if (IS_ERR(info->clk)) { | |
0255fc1b | 597 | dev_err(dev, "failed to get clock"); |
1da177e4 LT |
598 | err = -ENOENT; |
599 | goto exit_error; | |
600 | } | |
601 | ||
602 | clk_use(info->clk); | |
603 | clk_enable(info->clk); | |
604 | ||
605 | /* allocate and map the resource */ | |
606 | ||
a4f957f1 BD |
607 | /* currently we assume we have the one resource */ |
608 | res = pdev->resource; | |
1da177e4 LT |
609 | size = res->end - res->start + 1; |
610 | ||
611 | info->area = request_mem_region(res->start, size, pdev->name); | |
612 | ||
613 | if (info->area == NULL) { | |
0255fc1b | 614 | dev_err(dev, "cannot reserve register region\n"); |
1da177e4 LT |
615 | err = -ENOENT; |
616 | goto exit_error; | |
617 | } | |
618 | ||
a4f957f1 BD |
619 | info->device = dev; |
620 | info->platform = plat; | |
621 | info->regs = ioremap(res->start, size); | |
622 | info->is_s3c2440 = is_s3c2440; | |
1da177e4 LT |
623 | |
624 | if (info->regs == NULL) { | |
0255fc1b | 625 | dev_err(dev, "cannot reserve register region\n"); |
1da177e4 LT |
626 | err = -EIO; |
627 | goto exit_error; | |
61b03bd7 | 628 | } |
1da177e4 | 629 | |
0255fc1b | 630 | dev_dbg(dev, "mapped registers at %p\n", info->regs); |
1da177e4 LT |
631 | |
632 | /* initialise the hardware */ | |
633 | ||
634 | err = s3c2410_nand_inithw(info, dev); | |
635 | if (err != 0) | |
636 | goto exit_error; | |
637 | ||
638 | sets = (plat != NULL) ? plat->sets : NULL; | |
639 | nr_sets = (plat != NULL) ? plat->nr_sets : 1; | |
640 | ||
641 | info->mtd_count = nr_sets; | |
642 | ||
643 | /* allocate our information */ | |
644 | ||
645 | size = nr_sets * sizeof(*info->mtds); | |
646 | info->mtds = kmalloc(size, GFP_KERNEL); | |
647 | if (info->mtds == NULL) { | |
0255fc1b | 648 | dev_err(dev, "failed to allocate mtd storage\n"); |
1da177e4 LT |
649 | err = -ENOMEM; |
650 | goto exit_error; | |
651 | } | |
652 | ||
653 | memzero(info->mtds, size); | |
654 | ||
655 | /* initialise all possible chips */ | |
656 | ||
657 | nmtd = info->mtds; | |
658 | ||
659 | for (setno = 0; setno < nr_sets; setno++, nmtd++) { | |
660 | pr_debug("initialising set %d (%p, info %p)\n", | |
661 | setno, nmtd, info); | |
61b03bd7 | 662 | |
1da177e4 LT |
663 | s3c2410_nand_init_chip(info, nmtd, sets); |
664 | ||
665 | nmtd->scan_res = nand_scan(&nmtd->mtd, | |
666 | (sets) ? sets->nr_chips : 1); | |
667 | ||
668 | if (nmtd->scan_res == 0) { | |
669 | s3c2410_nand_add_partition(info, nmtd, sets); | |
670 | } | |
671 | ||
672 | if (sets != NULL) | |
673 | sets++; | |
674 | } | |
61b03bd7 | 675 | |
1da177e4 LT |
676 | pr_debug("initialised ok\n"); |
677 | return 0; | |
678 | ||
679 | exit_error: | |
680 | s3c2410_nand_remove(dev); | |
681 | ||
682 | if (err == 0) | |
683 | err = -EINVAL; | |
684 | return err; | |
685 | } | |
686 | ||
a4f957f1 BD |
687 | /* driver device registration */ |
688 | ||
689 | static int s3c2410_nand_probe(struct device *dev) | |
690 | { | |
691 | return s3c24xx_nand_probe(dev, 0); | |
692 | } | |
693 | ||
694 | static int s3c2440_nand_probe(struct device *dev) | |
695 | { | |
696 | return s3c24xx_nand_probe(dev, 1); | |
697 | } | |
698 | ||
1da177e4 LT |
699 | static struct device_driver s3c2410_nand_driver = { |
700 | .name = "s3c2410-nand", | |
61a72754 | 701 | .owner = THIS_MODULE, |
1da177e4 LT |
702 | .bus = &platform_bus_type, |
703 | .probe = s3c2410_nand_probe, | |
704 | .remove = s3c2410_nand_remove, | |
705 | }; | |
706 | ||
a4f957f1 BD |
707 | static struct device_driver s3c2440_nand_driver = { |
708 | .name = "s3c2440-nand", | |
61a72754 | 709 | .owner = THIS_MODULE, |
a4f957f1 BD |
710 | .bus = &platform_bus_type, |
711 | .probe = s3c2440_nand_probe, | |
712 | .remove = s3c2410_nand_remove, | |
713 | }; | |
714 | ||
1da177e4 LT |
715 | static int __init s3c2410_nand_init(void) |
716 | { | |
a4f957f1 BD |
717 | printk("S3C24XX NAND Driver, (c) 2004 Simtec Electronics\n"); |
718 | ||
719 | driver_register(&s3c2440_nand_driver); | |
1da177e4 LT |
720 | return driver_register(&s3c2410_nand_driver); |
721 | } | |
722 | ||
723 | static void __exit s3c2410_nand_exit(void) | |
724 | { | |
a4f957f1 | 725 | driver_unregister(&s3c2440_nand_driver); |
1da177e4 LT |
726 | driver_unregister(&s3c2410_nand_driver); |
727 | } | |
728 | ||
729 | module_init(s3c2410_nand_init); | |
730 | module_exit(s3c2410_nand_exit); | |
731 | ||
732 | MODULE_LICENSE("GPL"); | |
733 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); | |
a4f957f1 | 734 | MODULE_DESCRIPTION("S3C24XX MTD NAND driver"); |