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drivers: power: report battery voltage in AOSP compatible format
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / mtd / nand / nand_base.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
61b03bd7 7 *
1da177e4 8 * Additional technical information is available on
8b2b403c 9 * http://www.linux-mtd.infradead.org/doc/nand.html
61b03bd7 10 *
1da177e4 11 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
ace4dfee 12 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
1da177e4 13 *
ace4dfee 14 * Credits:
61b03bd7
TG		 15 * David Woodhouse for adding multichip support
16 *
1da177e4
LT		 17 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
18 * rework for 2K page size chips
19 *
ace4dfee 20 * TODO:
1da177e4
LT		 21 * Enable cached programming for 2k page size chips
22 * Check, if mtd->ecctype should be set to MTD_ECC_HW
7854d3f7 23 * if we have HW ECC support.
c0b8ba7b 24 * BBT table is not serialized, has to be fixed
1da177e4 25 *
1da177e4
LT		 26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License version 2 as
28 * published by the Free Software Foundation.
29 *
30 */
31
552d9205 32#include <linux/module.h>
1da177e4
LT		 33#include <linux/delay.h>
34#include <linux/errno.h>
7aa65bfd 35#include <linux/err.h>
1da177e4
LT		 36#include <linux/sched.h>
37#include <linux/slab.h>
38#include <linux/types.h>
39#include <linux/mtd/mtd.h>
40#include <linux/mtd/nand.h>
41#include <linux/mtd/nand_ecc.h>
193bd400 42#include <linux/mtd/nand_bch.h>
1da177e4
LT		 43#include <linux/interrupt.h>
44#include <linux/bitops.h>
8fe833c1 45#include <linux/leds.h>
7351d3a5 46#include <linux/io.h>
1da177e4 47#include <linux/mtd/partitions.h>
6fa3eb70
S		 48#ifdef CONFIG_MTK_MTD_NAND
49#include <asm/cache.h> // for ARCH_DMA_MINALIGN
50#endif
1da177e4
LT		 51
52/* Define default oob placement schemes for large and small page devices */
5bd34c09 53static struct nand_ecclayout nand_oob_8 = {
1da177e4
LT		 54 .eccbytes = 3,
55 .eccpos = {0, 1, 2},
5bd34c09
TG		 56 .oobfree = {
57 {.offset = 3,
58 .length = 2},
59 {.offset = 6,
f8ac0414 60 .length = 2} }
1da177e4
LT		 61};
62
5bd34c09 63static struct nand_ecclayout nand_oob_16 = {
1da177e4
LT		 64 .eccbytes = 6,
65 .eccpos = {0, 1, 2, 3, 6, 7},
5bd34c09
TG		 66 .oobfree = {
67 {.offset = 8,
f8ac0414 68 . length = 8} }
1da177e4
LT		 69};
70
5bd34c09 71static struct nand_ecclayout nand_oob_64 = {
1da177e4
LT		 72 .eccbytes = 24,
73 .eccpos = {
e0c7d767
DW		 74 40, 41, 42, 43, 44, 45, 46, 47,
75 48, 49, 50, 51, 52, 53, 54, 55,
76 56, 57, 58, 59, 60, 61, 62, 63},
5bd34c09
TG		 77 .oobfree = {
78 {.offset = 2,
f8ac0414 79 .length = 38} }
1da177e4
LT		 80};
81
81ec5364
TG		 82static struct nand_ecclayout nand_oob_128 = {
83 .eccbytes = 48,
84 .eccpos = {
85 80, 81, 82, 83, 84, 85, 86, 87,
86 88, 89, 90, 91, 92, 93, 94, 95,
87 96, 97, 98, 99, 100, 101, 102, 103,
88 104, 105, 106, 107, 108, 109, 110, 111,
89 112, 113, 114, 115, 116, 117, 118, 119,
90 120, 121, 122, 123, 124, 125, 126, 127},
91 .oobfree = {
92 {.offset = 2,
f8ac0414 93 .length = 78} }
81ec5364
TG		 94};
95
6fa3eb70
S		 96#ifdef CONFIG_MTK_MTD_NAND
97extern void nand_enable_clock(void);
98extern void nand_disable_clock(void);
99#endif
100
101#ifdef CONFIG_MTK_MLC_NAND_SUPPORT
102extern bool g_b2Die_CS;
103extern bool mtk_nand_IsRawPartition(loff_t logical_addres);
104#endif
105
106#define PMT_POOL_SIZE (2)
107
108#ifdef CONFIG_MTK_MTD_NAND
109int
110#else
111static int
112#endif
113nand_get_device(struct mtd_info *mtd, int new_state);
1da177e4 114
8593fbc6
TG		 115static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
116 struct mtd_oob_ops *ops);
117
d470a97c 118/*
8e87d782 119 * For devices which display every fart in the system on a separate LED. Is
d470a97c
TG		 120 * compiled away when LED support is disabled.
121 */
122DEFINE_LED_TRIGGER(nand_led_trigger);
123
6fe5a6ac
VS		 124static int check_offs_len(struct mtd_info *mtd,
125 loff_t ofs, uint64_t len)
126{
127 struct nand_chip *chip = mtd->priv;
128 int ret = 0;
6fa3eb70
S		 129#ifdef CONFIG_MTK_MLC_NAND_SUPPORT
130 int block_size;
131 if(mtk_nand_IsRawPartition(ofs))
132 {
133 block_size = (1 << (chip->phys_erase_shift-1));
134 }
135 else
136 {
137 block_size = (1 << chip->phys_erase_shift);
138 }
139 /* Start address must align on block boundary */
140 if (ofs & (block_size - 1)) {
141 pr_debug("%s: unaligned address\n", __func__);
142 ret = -EINVAL;
143 }
6fe5a6ac 144
6fa3eb70
S		 145 /* Length must align on block boundary */
146 if (len & (block_size - 1)) {
147 pr_debug("%s: length not block aligned\n", __func__);
148 ret = -EINVAL;
149 }
150#else
6fe5a6ac
VS		 151 /* Start address must align on block boundary */
152 if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
289c0522 153 pr_debug("%s: unaligned address\n", __func__);
6fe5a6ac
VS		 154 ret = -EINVAL;
155 }
156
157 /* Length must align on block boundary */
158 if (len & ((1 << chip->phys_erase_shift) - 1)) {
289c0522 159 pr_debug("%s: length not block aligned\n", __func__);
6fe5a6ac
VS		 160 ret = -EINVAL;
161 }
6fa3eb70 162#endif
6fe5a6ac 163
6fa3eb70
S		 164#ifdef CONFIG_MTK_MTD_NAND
165 /* Do not allow past end of device */
166 if (ofs + len > (mtd->size+PMT_POOL_SIZE*mtd->erasesize)) {
167 pr_debug("%s: Past end of device\n",__func__);
168 ret = -EINVAL;
169 }
170#endif
6fe5a6ac
VS		 171 return ret;
172}
173
1da177e4
LT		 174/**
175 * nand_release_device - [GENERIC] release chip
8b6e50c9 176 * @mtd: MTD device structure
61b03bd7 177 *
b0bb6903 178 * Release chip lock and wake up anyone waiting on the device.
1da177e4 179 */
6fa3eb70
S		 180#ifdef CONFIG_MTK_MTD_NAND
181void
182#else
183static void
184#endif
185nand_release_device(struct mtd_info *mtd)
1da177e4 186{
ace4dfee 187 struct nand_chip *chip = mtd->priv;
1da177e4 188
a36ed299 189 /* Release the controller and the chip */
ace4dfee
TG		 190 spin_lock(&chip->controller->lock);
191 chip->controller->active = NULL;
6fa3eb70
S		 192#ifdef CONFIG_MTK_MTD_NAND
193 if(chip->state!=FL_READY&&chip->state!= FL_PM_SUSPENDED)
194 {
195 nand_disable_clock();
196 }
197#endif
ace4dfee
TG		 198 chip->state = FL_READY;
199 wake_up(&chip->controller->wq);
200 spin_unlock(&chip->controller->lock);
1da177e4
LT		 201}
202
203/**
204 * nand_read_byte - [DEFAULT] read one byte from the chip
8b6e50c9 205 * @mtd: MTD device structure
1da177e4 206 *
7854d3f7 207 * Default read function for 8bit buswidth
1da177e4 208 */
58dd8f2b 209static uint8_t nand_read_byte(struct mtd_info *mtd)
1da177e4 210{
ace4dfee
TG		 211 struct nand_chip *chip = mtd->priv;
212 return readb(chip->IO_ADDR_R);
1da177e4
LT		 213}
214
1da177e4 215/**
064a7694 216 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
7854d3f7 217 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
8b6e50c9 218 * @mtd: MTD device structure
1da177e4 219 *
7854d3f7
BN		 220 * Default read function for 16bit buswidth with endianness conversion.
221 *
1da177e4 222 */
58dd8f2b 223static uint8_t nand_read_byte16(struct mtd_info *mtd)
1da177e4 224{
ace4dfee
TG		 225 struct nand_chip *chip = mtd->priv;
226 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
1da177e4
LT		 227}
228
1da177e4
LT		 229/**
230 * nand_read_word - [DEFAULT] read one word from the chip
8b6e50c9 231 * @mtd: MTD device structure
1da177e4 232 *
7854d3f7 233 * Default read function for 16bit buswidth without endianness conversion.
1da177e4
LT		 234 */
235static u16 nand_read_word(struct mtd_info *mtd)
236{
ace4dfee
TG		 237 struct nand_chip *chip = mtd->priv;
238 return readw(chip->IO_ADDR_R);
1da177e4
LT		 239}
240
1da177e4
LT		 241/**
242 * nand_select_chip - [DEFAULT] control CE line
8b6e50c9
BN		 243 * @mtd: MTD device structure
244 * @chipnr: chipnumber to select, -1 for deselect
1da177e4
LT		 245 *
246 * Default select function for 1 chip devices.
247 */
ace4dfee 248static void nand_select_chip(struct mtd_info *mtd, int chipnr)
1da177e4 249{
ace4dfee
TG		 250 struct nand_chip *chip = mtd->priv;
251
252 switch (chipnr) {
1da177e4 253 case -1:
ace4dfee 254 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
1da177e4
LT		 255 break;
256 case 0:
1da177e4
LT		 257 break;
258
259 default:
260 BUG();
261 }
262}
263
264/**
265 * nand_write_buf - [DEFAULT] write buffer to chip
8b6e50c9
BN		 266 * @mtd: MTD device structure
267 * @buf: data buffer
268 * @len: number of bytes to write
1da177e4 269 *
7854d3f7 270 * Default write function for 8bit buswidth.
1da177e4 271 */
58dd8f2b 272static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 273{
274 int i;
ace4dfee 275 struct nand_chip *chip = mtd->priv;
1da177e4 276
e0c7d767 277 for (i = 0; i < len; i++)
ace4dfee 278 writeb(buf[i], chip->IO_ADDR_W);
1da177e4
LT		 279}
280
281/**
61b03bd7 282 * nand_read_buf - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 283 * @mtd: MTD device structure
284 * @buf: buffer to store date
285 * @len: number of bytes to read
1da177e4 286 *
7854d3f7 287 * Default read function for 8bit buswidth.
1da177e4 288 */
58dd8f2b 289static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 290{
291 int i;
ace4dfee 292 struct nand_chip *chip = mtd->priv;
1da177e4 293
e0c7d767 294 for (i = 0; i < len; i++)
ace4dfee 295 buf[i] = readb(chip->IO_ADDR_R);
1da177e4
LT		 296}
297
1da177e4
LT		 298/**
299 * nand_write_buf16 - [DEFAULT] write buffer to chip
8b6e50c9
BN		 300 * @mtd: MTD device structure
301 * @buf: data buffer
302 * @len: number of bytes to write
1da177e4 303 *
7854d3f7 304 * Default write function for 16bit buswidth.
1da177e4 305 */
58dd8f2b 306static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 307{
308 int i;
ace4dfee 309 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 310 u16 *p = (u16 *) buf;
311 len >>= 1;
61b03bd7 312
e0c7d767 313 for (i = 0; i < len; i++)
ace4dfee 314 writew(p[i], chip->IO_ADDR_W);
61b03bd7 315
1da177e4
LT		 316}
317
318/**
61b03bd7 319 * nand_read_buf16 - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 320 * @mtd: MTD device structure
321 * @buf: buffer to store date
322 * @len: number of bytes to read
1da177e4 323 *
7854d3f7 324 * Default read function for 16bit buswidth.
1da177e4 325 */
58dd8f2b 326static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 327{
328 int i;
ace4dfee 329 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 330 u16 *p = (u16 *) buf;
331 len >>= 1;
332
e0c7d767 333 for (i = 0; i < len; i++)
ace4dfee 334 p[i] = readw(chip->IO_ADDR_R);
1da177e4
LT		 335}
336
1da177e4
LT		 337/**
338 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
8b6e50c9
BN		 339 * @mtd: MTD device structure
340 * @ofs: offset from device start
341 * @getchip: 0, if the chip is already selected
1da177e4 342 *
61b03bd7 343 * Check, if the block is bad.
1da177e4
LT		 344 */
345static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
346{
cdbec050 347 int page, chipnr, res = 0, i = 0;
ace4dfee 348 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 349 u16 bad;
350
5fb1549d 351 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
b60b08b0
KC		 352 ofs += mtd->erasesize - mtd->writesize;
353
1a12f46a
TK		 354 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
355
1da177e4 356 if (getchip) {
ace4dfee 357 chipnr = (int)(ofs >> chip->chip_shift);
1da177e4 358
6a8214aa 359 nand_get_device(mtd, FL_READING);
1da177e4
LT		 360
361 /* Select the NAND device */
ace4dfee 362 chip->select_chip(mtd, chipnr);
1a12f46a 363 }
1da177e4 364
cdbec050
BN		 365 do {
366 if (chip->options & NAND_BUSWIDTH_16) {
367 chip->cmdfunc(mtd, NAND_CMD_READOOB,
368 chip->badblockpos & 0xFE, page);
369 bad = cpu_to_le16(chip->read_word(mtd));
370 if (chip->badblockpos & 0x1)
371 bad >>= 8;
372 else
373 bad &= 0xFF;
374 } else {
375 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
376 page);
377 bad = chip->read_byte(mtd);
378 }
379
380 if (likely(chip->badblockbits == 8))
381 res = bad != 0xFF;
e0b58d0a 382 else
cdbec050
BN		 383 res = hweight8(bad) < chip->badblockbits;
384 ofs += mtd->writesize;
385 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
386 i++;
387 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
e0b58d0a 388
b0bb6903
HS		 389 if (getchip) {
390 chip->select_chip(mtd, -1);
1da177e4 391 nand_release_device(mtd);
b0bb6903 392 }
61b03bd7 393
1da177e4
LT		 394 return res;
395}
396
397/**
398 * nand_default_block_markbad - [DEFAULT] mark a block bad
8b6e50c9
BN		 399 * @mtd: MTD device structure
400 * @ofs: offset from device start
1da177e4 401 *
8b6e50c9 402 * This is the default implementation, which can be overridden by a hardware
e2414f4c
BN		 403 * specific driver. We try operations in the following order, according to our
404 * bbt_options (NAND_BBT_NO_OOB_BBM and NAND_BBT_USE_FLASH):
405 * (1) erase the affected block, to allow OOB marker to be written cleanly
406 * (2) update in-memory BBT
407 * (3) write bad block marker to OOB area of affected block
408 * (4) update flash-based BBT
409 * Note that we retain the first error encountered in (3) or (4), finish the
410 * procedures, and dump the error in the end.
1da177e4
LT		 411*/
412static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
413{
ace4dfee 414 struct nand_chip *chip = mtd->priv;
58dd8f2b 415 uint8_t buf[2] = { 0, 0 };
e2414f4c
BN		 416 int block, res, ret = 0, i = 0;
417 int write_oob = !(chip->bbt_options & NAND_BBT_NO_OOB_BBM);
61b03bd7 418
e2414f4c 419 if (write_oob) {
00918429
BN		 420 struct erase_info einfo;
421
422 /* Attempt erase before marking OOB */
423 memset(&einfo, 0, sizeof(einfo));
424 einfo.mtd = mtd;
425 einfo.addr = ofs;
426 einfo.len = 1 << chip->phys_erase_shift;
427 nand_erase_nand(mtd, &einfo, 0);
428 }
429
1da177e4 430 /* Get block number */
4226b510 431 block = (int)(ofs >> chip->bbt_erase_shift);
e2414f4c 432 /* Mark block bad in memory-based BBT */
ace4dfee
TG		 433 if (chip->bbt)
434 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
1da177e4 435
e2414f4c
BN		 436 /* Write bad block marker to OOB */
437 if (write_oob) {
4a89ff88 438 struct mtd_oob_ops ops;
df698621 439 loff_t wr_ofs = ofs;
4a89ff88 440
6a8214aa 441 nand_get_device(mtd, FL_WRITING);
f1a28c02 442
4a89ff88
BN		 443 ops.datbuf = NULL;
444 ops.oobbuf = buf;
85443319
BN		 445 ops.ooboffs = chip->badblockpos;
446 if (chip->options & NAND_BUSWIDTH_16) {
447 ops.ooboffs &= ~0x01;
448 ops.len = ops.ooblen = 2;
449 } else {
450 ops.len = ops.ooblen = 1;
451 }
23b1a99b 452 ops.mode = MTD_OPS_PLACE_OOB;
df698621 453
e2414f4c 454 /* Write to first/last page(s) if necessary */
df698621
BN		 455 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
456 wr_ofs += mtd->erasesize - mtd->writesize;
02ed70bb 457 do {
e2414f4c
BN		 458 res = nand_do_write_oob(mtd, wr_ofs, &ops);
459 if (!ret)
460 ret = res;
02ed70bb 461
02ed70bb 462 i++;
df698621 463 wr_ofs += mtd->writesize;
e2414f4c 464 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
02ed70bb 465
c0b8ba7b 466 nand_release_device(mtd);
f1a28c02 467 }
e2414f4c
BN		 468
469 /* Update flash-based bad block table */
470 if (chip->bbt_options & NAND_BBT_USE_FLASH) {
471 res = nand_update_bbt(mtd, ofs);
472 if (!ret)
473 ret = res;
474 }
475
f1a28c02
TG		 476 if (!ret)
477 mtd->ecc_stats.badblocks++;
c0b8ba7b 478
f1a28c02 479 return ret;
1da177e4
LT		 480}
481
61b03bd7 482/**
1da177e4 483 * nand_check_wp - [GENERIC] check if the chip is write protected
8b6e50c9 484 * @mtd: MTD device structure
1da177e4 485 *
8b6e50c9
BN		 486 * Check, if the device is write protected. The function expects, that the
487 * device is already selected.
1da177e4 488 */
e0c7d767 489static int nand_check_wp(struct mtd_info *mtd)
1da177e4 490{
ace4dfee 491 struct nand_chip *chip = mtd->priv;
93edbad6 492
8b6e50c9 493 /* Broken xD cards report WP despite being writable */
93edbad6
ML		 494 if (chip->options & NAND_BROKEN_XD)
495 return 0;
496
1da177e4 497 /* Check the WP bit */
ace4dfee
TG		 498 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
499 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
1da177e4
LT		 500}
501
502/**
503 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
8b6e50c9
BN		 504 * @mtd: MTD device structure
505 * @ofs: offset from device start
506 * @getchip: 0, if the chip is already selected
507 * @allowbbt: 1, if its allowed to access the bbt area
1da177e4
LT		 508 *
509 * Check, if the block is bad. Either by reading the bad block table or
510 * calling of the scan function.
511 */
2c0a2bed
TG		 512static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
513 int allowbbt)
1da177e4 514{
ace4dfee 515 struct nand_chip *chip = mtd->priv;
61b03bd7 516
ace4dfee
TG		 517 if (!chip->bbt)
518 return chip->block_bad(mtd, ofs, getchip);
61b03bd7 519
1da177e4 520 /* Return info from the table */
e0c7d767 521 return nand_isbad_bbt(mtd, ofs, allowbbt);
1da177e4
LT		 522}
523
2af7c653
SK		 524/**
525 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
8b6e50c9
BN		 526 * @mtd: MTD device structure
527 * @timeo: Timeout
2af7c653
SK		 528 *
529 * Helper function for nand_wait_ready used when needing to wait in interrupt
530 * context.
531 */
532static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
533{
534 struct nand_chip *chip = mtd->priv;
535 int i;
536
537 /* Wait for the device to get ready */
538 for (i = 0; i < timeo; i++) {
539 if (chip->dev_ready(mtd))
540 break;
541 touch_softlockup_watchdog();
542 mdelay(1);
543 }
544}
545
7854d3f7 546/* Wait for the ready pin, after a command. The timeout is caught later. */
4b648b02 547void nand_wait_ready(struct mtd_info *mtd)
3b88775c 548{
ace4dfee 549 struct nand_chip *chip = mtd->priv;
ca6a2489 550 unsigned long timeo = jiffies + msecs_to_jiffies(20);
3b88775c 551
2af7c653
SK		 552 /* 400ms timeout */
553 if (in_interrupt() || oops_in_progress)
554 return panic_nand_wait_ready(mtd, 400);
555
8fe833c1 556 led_trigger_event(nand_led_trigger, LED_FULL);
7854d3f7 557 /* Wait until command is processed or timeout occurs */
3b88775c 558 do {
ace4dfee 559 if (chip->dev_ready(mtd))
8fe833c1 560 break;
8446f1d3 561 touch_softlockup_watchdog();
61b03bd7 562 } while (time_before(jiffies, timeo));
8fe833c1 563 led_trigger_event(nand_led_trigger, LED_OFF);
3b88775c 564}
4b648b02 565EXPORT_SYMBOL_GPL(nand_wait_ready);
3b88775c 566
1da177e4
LT		 567/**
568 * nand_command - [DEFAULT] Send command to NAND device
8b6e50c9
BN		 569 * @mtd: MTD device structure
570 * @command: the command to be sent
571 * @column: the column address for this command, -1 if none
572 * @page_addr: the page address for this command, -1 if none
1da177e4 573 *
8b6e50c9 574 * Send command to NAND device. This function is used for small page devices
51148f1f 575 * (512 Bytes per page).
1da177e4 576 */
7abd3ef9
TG		 577static void nand_command(struct mtd_info *mtd, unsigned int command,
578 int column, int page_addr)
1da177e4 579{
ace4dfee 580 register struct nand_chip *chip = mtd->priv;
7abd3ef9 581 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
1da177e4 582
8b6e50c9 583 /* Write out the command to the device */
1da177e4
LT		 584 if (command == NAND_CMD_SEQIN) {
585 int readcmd;
586
28318776 587 if (column >= mtd->writesize) {
1da177e4 588 /* OOB area */
28318776 589 column -= mtd->writesize;
1da177e4
LT		 590 readcmd = NAND_CMD_READOOB;
591 } else if (column < 256) {
592 /* First 256 bytes --> READ0 */
593 readcmd = NAND_CMD_READ0;
594 } else {
595 column -= 256;
596 readcmd = NAND_CMD_READ1;
597 }
ace4dfee 598 chip->cmd_ctrl(mtd, readcmd, ctrl);
7abd3ef9 599 ctrl &= ~NAND_CTRL_CHANGE;
1da177e4 600 }
ace4dfee 601 chip->cmd_ctrl(mtd, command, ctrl);
1da177e4 602
8b6e50c9 603 /* Address cycle, when necessary */
7abd3ef9
TG		 604 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
605 /* Serially input address */
606 if (column != -1) {
607 /* Adjust columns for 16 bit buswidth */
ace4dfee 608 if (chip->options & NAND_BUSWIDTH_16)
7abd3ef9 609 column >>= 1;
ace4dfee 610 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9
TG		 611 ctrl &= ~NAND_CTRL_CHANGE;
612 }
613 if (page_addr != -1) {
ace4dfee 614 chip->cmd_ctrl(mtd, page_addr, ctrl);
7abd3ef9 615 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 616 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
7abd3ef9 617 /* One more address cycle for devices > 32MiB */
ace4dfee
TG		 618 if (chip->chipsize > (32 << 20))
619 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
1da177e4 620 }
ace4dfee 621 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 622
623 /*
8b6e50c9
BN		 624 * Program and erase have their own busy handlers status and sequential
625 * in needs no delay
e0c7d767 626 */
1da177e4 627 switch (command) {
61b03bd7 628
1da177e4
LT		 629 case NAND_CMD_PAGEPROG:
630 case NAND_CMD_ERASE1:
631 case NAND_CMD_ERASE2:
632 case NAND_CMD_SEQIN:
633 case NAND_CMD_STATUS:
634 return;
635
636 case NAND_CMD_RESET:
ace4dfee 637 if (chip->dev_ready)
1da177e4 638 break;
ace4dfee
TG		 639 udelay(chip->chip_delay);
640 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
7abd3ef9 641 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
12efdde3
TG		 642 chip->cmd_ctrl(mtd,
643 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 644 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
645 ;
1da177e4
LT		 646 return;
647
e0c7d767 648 /* This applies to read commands */
1da177e4 649 default:
61b03bd7 650 /*
1da177e4
LT		 651 * If we don't have access to the busy pin, we apply the given
652 * command delay
e0c7d767 653 */
ace4dfee
TG		 654 if (!chip->dev_ready) {
655 udelay(chip->chip_delay);
1da177e4 656 return;
61b03bd7 657 }
1da177e4 658 }
8b6e50c9
BN		 659 /*
660 * Apply this short delay always to ensure that we do wait tWB in
661 * any case on any machine.
662 */
e0c7d767 663 ndelay(100);
3b88775c
TG		 664
665 nand_wait_ready(mtd);
1da177e4
LT		 666}
667
668/**
669 * nand_command_lp - [DEFAULT] Send command to NAND large page device
8b6e50c9
BN		 670 * @mtd: MTD device structure
671 * @command: the command to be sent
672 * @column: the column address for this command, -1 if none
673 * @page_addr: the page address for this command, -1 if none
1da177e4 674 *
7abd3ef9 675 * Send command to NAND device. This is the version for the new large page
7854d3f7
BN		 676 * devices. We don't have the separate regions as we have in the small page
677 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
1da177e4 678 */
7abd3ef9
TG		 679static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
680 int column, int page_addr)
1da177e4 681{
ace4dfee 682 register struct nand_chip *chip = mtd->priv;
1da177e4
LT		 683
684 /* Emulate NAND_CMD_READOOB */
685 if (command == NAND_CMD_READOOB) {
28318776 686 column += mtd->writesize;
1da177e4
LT		 687 command = NAND_CMD_READ0;
688 }
61b03bd7 689
7abd3ef9 690 /* Command latch cycle */
fb066ada 691 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
1da177e4
LT		 692
693 if (column != -1 || page_addr != -1) {
7abd3ef9 694 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
1da177e4
LT		 695
696 /* Serially input address */
697 if (column != -1) {
698 /* Adjust columns for 16 bit buswidth */
ace4dfee 699 if (chip->options & NAND_BUSWIDTH_16)
1da177e4 700 column >>= 1;
ace4dfee 701 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9 702 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 703 chip->cmd_ctrl(mtd, column >> 8, ctrl);
61b03bd7 704 }
1da177e4 705 if (page_addr != -1) {
ace4dfee
TG		 706 chip->cmd_ctrl(mtd, page_addr, ctrl);
707 chip->cmd_ctrl(mtd, page_addr >> 8,
7abd3ef9 708 NAND_NCE | NAND_ALE);
1da177e4 709 /* One more address cycle for devices > 128MiB */
ace4dfee
TG		 710 if (chip->chipsize > (128 << 20))
711 chip->cmd_ctrl(mtd, page_addr >> 16,
7abd3ef9 712 NAND_NCE | NAND_ALE);
1da177e4 713 }
1da177e4 714 }
ace4dfee 715 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 716
717 /*
8b6e50c9
BN		 718 * Program and erase have their own busy handlers status, sequential
719 * in, and deplete1 need no delay.
30f464b7 720 */
1da177e4 721 switch (command) {
61b03bd7 722
1da177e4
LT		 723 case NAND_CMD_CACHEDPROG:
724 case NAND_CMD_PAGEPROG:
725 case NAND_CMD_ERASE1:
726 case NAND_CMD_ERASE2:
727 case NAND_CMD_SEQIN:
7bc3312b 728 case NAND_CMD_RNDIN:
1da177e4 729 case NAND_CMD_STATUS:
30f464b7 730 return;
1da177e4
LT		 731
732 case NAND_CMD_RESET:
ace4dfee 733 if (chip->dev_ready)
1da177e4 734 break;
ace4dfee 735 udelay(chip->chip_delay);
12efdde3
TG		 736 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
737 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
738 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
739 NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 740 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
741 ;
1da177e4
LT		 742 return;
743
7bc3312b
TG		 744 case NAND_CMD_RNDOUT:
745 /* No ready / busy check necessary */
746 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
747 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
748 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
749 NAND_NCE | NAND_CTRL_CHANGE);
750 return;
751
1da177e4 752 case NAND_CMD_READ0:
12efdde3
TG		 753 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
754 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
755 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
756 NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7 757
e0c7d767 758 /* This applies to read commands */
1da177e4 759 default:
61b03bd7 760 /*
1da177e4 761 * If we don't have access to the busy pin, we apply the given
8b6e50c9 762 * command delay.
e0c7d767 763 */
ace4dfee
TG		 764 if (!chip->dev_ready) {
765 udelay(chip->chip_delay);
1da177e4 766 return;
61b03bd7 767 }
1da177e4 768 }
3b88775c 769
8b6e50c9
BN		 770 /*
771 * Apply this short delay always to ensure that we do wait tWB in
772 * any case on any machine.
773 */
e0c7d767 774 ndelay(100);
3b88775c
TG		 775
776 nand_wait_ready(mtd);
1da177e4
LT		 777}
778
2af7c653
SK		 779/**
780 * panic_nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 781 * @chip: the nand chip descriptor
782 * @mtd: MTD device structure
783 * @new_state: the state which is requested
2af7c653
SK		 784 *
785 * Used when in panic, no locks are taken.
786 */
787static void panic_nand_get_device(struct nand_chip *chip,
788 struct mtd_info *mtd, int new_state)
789{
7854d3f7 790 /* Hardware controller shared among independent devices */
2af7c653
SK		 791 chip->controller->active = chip;
792 chip->state = new_state;
793}
794
1da177e4
LT		 795/**
796 * nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 797 * @mtd: MTD device structure
798 * @new_state: the state which is requested
1da177e4
LT		 799 *
800 * Get the device and lock it for exclusive access
801 */
6fa3eb70
S		 802#ifdef CONFIG_MTK_MTD_NAND
803 int
804#else
2c0a2bed 805static int
6fa3eb70 806#endif
6a8214aa 807nand_get_device(struct mtd_info *mtd, int new_state)
1da177e4 808{
6a8214aa 809 struct nand_chip *chip = mtd->priv;
ace4dfee
TG		 810 spinlock_t *lock = &chip->controller->lock;
811 wait_queue_head_t *wq = &chip->controller->wq;
e0c7d767 812 DECLARE_WAITQUEUE(wait, current);
7351d3a5 813retry:
0dfc6246
TG		 814 spin_lock(lock);
815
b8b3ee9a 816 /* Hardware controller shared among independent devices */
ace4dfee
TG		 817 if (!chip->controller->active)
818 chip->controller->active = chip;
a36ed299 819
ace4dfee 820 if (chip->controller->active == chip && chip->state == FL_READY) {
6fa3eb70
S		 821#ifdef CONFIG_MTK_MTD_NAND
822 if(new_state!=FL_READY&&new_state!= FL_PM_SUSPENDED)
823 {
824 nand_enable_clock();
825 }
826#endif
ace4dfee 827 chip->state = new_state;
0dfc6246 828 spin_unlock(lock);
962034f4
VW		 829 return 0;
830 }
831 if (new_state == FL_PM_SUSPENDED) {
6b0d9a84
LY		 832 if (chip->controller->active->state == FL_PM_SUSPENDED) {
833 chip->state = FL_PM_SUSPENDED;
834 spin_unlock(lock);
835 return 0;
6b0d9a84 836 }
0dfc6246
TG		 837 }
838 set_current_state(TASK_UNINTERRUPTIBLE);
839 add_wait_queue(wq, &wait);
840 spin_unlock(lock);
841 schedule();
842 remove_wait_queue(wq, &wait);
1da177e4
LT		 843 goto retry;
844}
845
2af7c653 846/**
8b6e50c9
BN		 847 * panic_nand_wait - [GENERIC] wait until the command is done
848 * @mtd: MTD device structure
849 * @chip: NAND chip structure
850 * @timeo: timeout
2af7c653
SK		 851 *
852 * Wait for command done. This is a helper function for nand_wait used when
853 * we are in interrupt context. May happen when in panic and trying to write
b595076a 854 * an oops through mtdoops.
2af7c653
SK		 855 */
856static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
857 unsigned long timeo)
858{
859 int i;
860 for (i = 0; i < timeo; i++) {
861 if (chip->dev_ready) {
862 if (chip->dev_ready(mtd))
863 break;
864 } else {
865 if (chip->read_byte(mtd) & NAND_STATUS_READY)
866 break;
867 }
868 mdelay(1);
f8ac0414 869 }
2af7c653
SK		 870}
871
6fa3eb70
S		 872#ifdef CONFIG_MTK_MTD_NAND
873u8 mtk_nand_util_time_before(struct timeval *time_a, struct timeval *time_b)
874{
875 if (time_a->tv_sec < time_b->tv_sec)
876 {
877 return 1;
878 }
879 else if (time_a->tv_sec > time_b->tv_sec)
880 {
881 return 0;
882 }
883 else // sec is the same
884 {
885 if (time_a->tv_usec < time_b->tv_usec)
886 {
887 return 1;
888 }
889 else
890 {
891 return 0;
892 }
893 }
894
895 return 0;
896} /* timeval_diff() */
897#endif
1da177e4 898/**
8b6e50c9
BN		 899 * nand_wait - [DEFAULT] wait until the command is done
900 * @mtd: MTD device structure
901 * @chip: NAND chip structure
1da177e4 902 *
8b6e50c9
BN		 903 * Wait for command done. This applies to erase and program only. Erase can
904 * take up to 400ms and program up to 20ms according to general NAND and
905 * SmartMedia specs.
844d3b42 906 */
7bc3312b 907static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1da177e4 908{
6fa3eb70 909 unsigned long timeo = jiffies;
7bc3312b 910 int status, state = chip->state;
6fa3eb70
S		 911
912 #ifdef CONFIG_MTK_MTD_NAND
913 struct timeval timer_timeout, timer_cur;
914 #endif
915
916 #ifdef CONFIG_MTK_MTD_NAND
917 do_gettimeofday(&timer_timeout);
918
919 if (state == FL_ERASING)
920 timer_timeout.tv_usec += 400 * 1000; // 400 ms
921 else
922 timer_timeout.tv_usec += 20 * 1000; // 20 ms
923
924 if (timer_timeout.tv_usec >= 1000000) // 1 second
925 {
926 timer_timeout.tv_usec -= 1000000;
927 timer_timeout.tv_sec += 1;
928 }
929 #else
930 if (state == FL_ERASING)
931 timeo += (HZ * 400) / 1000;
932 else
933 timeo += (HZ * 20) / 1000;
934 #endif
1da177e4 935
8fe833c1
RP		 936 led_trigger_event(nand_led_trigger, LED_FULL);
937
8b6e50c9
BN		 938 /*
939 * Apply this short delay always to ensure that we do wait tWB in any
940 * case on any machine.
941 */
e0c7d767 942 ndelay(100);
1da177e4 943
14c65786 944 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1da177e4 945
2af7c653
SK		 946 if (in_interrupt() || oops_in_progress)
947 panic_nand_wait(mtd, chip, timeo);
948 else {
6fa3eb70
S		 949 #ifdef CONFIG_MTK_MTD_NAND
950 /*
951 * use non-jiffies-based method for timeout detection to prevent jiffies issue due to dynamic tick (CONFIG_NO_HZ is on)
952 */
953 while (1)
954 {
955 do_gettimeofday(&timer_cur);
956
957 if (0 == mtk_nand_util_time_before(&timer_cur, &timer_timeout))
958 {
959 break; // timeout
960 }
961 #else
962 while (time_before(jiffies, timeo))
963 {
964 #endif
2af7c653
SK		 965 if (chip->dev_ready) {
966 if (chip->dev_ready(mtd))
967 break;
968 } else {
969 if (chip->read_byte(mtd) & NAND_STATUS_READY)
970 break;
971 }
972 cond_resched();
1da177e4 973 }
1da177e4 974 }
8fe833c1
RP		 975 led_trigger_event(nand_led_trigger, LED_OFF);
976
ace4dfee 977 status = (int)chip->read_byte(mtd);
f251b8df
MC		 978 /* This can happen if in case of timeout or buggy dev_ready */
979 WARN_ON(!(status & NAND_STATUS_READY));
1da177e4
LT		 980 return status;
981}
982
7d70f334 983/**
b6d676db 984 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 985 * @mtd: mtd info
986 * @ofs: offset to start unlock from
987 * @len: length to unlock
8b6e50c9
BN		 988 * @invert: when = 0, unlock the range of blocks within the lower and
989 * upper boundary address
990 * when = 1, unlock the range of blocks outside the boundaries
991 * of the lower and upper boundary address
7d70f334 992 *
8b6e50c9 993 * Returs unlock status.
7d70f334
VS		 994 */
995static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
996 uint64_t len, int invert)
997{
998 int ret = 0;
999 int status, page;
1000 struct nand_chip *chip = mtd->priv;
1001
1002 /* Submit address of first page to unlock */
1003 page = ofs >> chip->page_shift;
1004 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
1005
1006 /* Submit address of last page to unlock */
1007 page = (ofs + len) >> chip->page_shift;
1008 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
1009 (page | invert) & chip->pagemask);
1010
1011 /* Call wait ready function */
1012 status = chip->waitfunc(mtd, chip);
7d70f334 1013 /* See if device thinks it succeeded */
74830966 1014 if (status & NAND_STATUS_FAIL) {
289c0522 1015 pr_debug("%s: error status = 0x%08x\n",
7d70f334
VS		 1016 __func__, status);
1017 ret = -EIO;
1018 }
1019
1020 return ret;
1021}
1022
1023/**
b6d676db 1024 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 1025 * @mtd: mtd info
1026 * @ofs: offset to start unlock from
1027 * @len: length to unlock
7d70f334 1028 *
8b6e50c9 1029 * Returns unlock status.
7d70f334
VS		 1030 */
1031int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1032{
1033 int ret = 0;
1034 int chipnr;
1035 struct nand_chip *chip = mtd->priv;
1036
289c0522 1037 pr_debug("%s: start = 0x%012llx, len = %llu\n",
7d70f334
VS		 1038 __func__, (unsigned long long)ofs, len);
1039
1040 if (check_offs_len(mtd, ofs, len))
1041 ret = -EINVAL;
1042
1043 /* Align to last block address if size addresses end of the device */
1044 if (ofs + len == mtd->size)
1045 len -= mtd->erasesize;
1046
6a8214aa 1047 nand_get_device(mtd, FL_UNLOCKING);
7d70f334
VS		 1048
1049 /* Shift to get chip number */
1050 chipnr = ofs >> chip->chip_shift;
1051
1052 chip->select_chip(mtd, chipnr);
1053
1054 /* Check, if it is write protected */
1055 if (nand_check_wp(mtd)) {
289c0522 1056 pr_debug("%s: device is write protected!\n",
7d70f334
VS		 1057 __func__);
1058 ret = -EIO;
1059 goto out;
1060 }
1061
1062 ret = __nand_unlock(mtd, ofs, len, 0);
1063
1064out:
b0bb6903 1065 chip->select_chip(mtd, -1);
7d70f334
VS		 1066 nand_release_device(mtd);
1067
1068 return ret;
1069}
7351d3a5 1070EXPORT_SYMBOL(nand_unlock);
7d70f334
VS		 1071
1072/**
b6d676db 1073 * nand_lock - [REPLACEABLE] locks all blocks present in the device
b6d676db
RD		 1074 * @mtd: mtd info
1075 * @ofs: offset to start unlock from
1076 * @len: length to unlock
7d70f334 1077 *
8b6e50c9
BN		 1078 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1079 * have this feature, but it allows only to lock all blocks, not for specified
1080 * range for block. Implementing 'lock' feature by making use of 'unlock', for
1081 * now.
7d70f334 1082 *
8b6e50c9 1083 * Returns lock status.
7d70f334
VS		 1084 */
1085int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1086{
1087 int ret = 0;
1088 int chipnr, status, page;
1089 struct nand_chip *chip = mtd->priv;
1090
289c0522 1091 pr_debug("%s: start = 0x%012llx, len = %llu\n",
7d70f334
VS		 1092 __func__, (unsigned long long)ofs, len);
1093
1094 if (check_offs_len(mtd, ofs, len))
1095 ret = -EINVAL;
1096
6a8214aa 1097 nand_get_device(mtd, FL_LOCKING);
7d70f334
VS		 1098
1099 /* Shift to get chip number */
1100 chipnr = ofs >> chip->chip_shift;
1101
1102 chip->select_chip(mtd, chipnr);
1103
1104 /* Check, if it is write protected */
1105 if (nand_check_wp(mtd)) {
289c0522 1106 pr_debug("%s: device is write protected!\n",
7d70f334
VS		 1107 __func__);
1108 status = MTD_ERASE_FAILED;
1109 ret = -EIO;
1110 goto out;
1111 }
1112
1113 /* Submit address of first page to lock */
1114 page = ofs >> chip->page_shift;
1115 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1116
1117 /* Call wait ready function */
1118 status = chip->waitfunc(mtd, chip);
7d70f334 1119 /* See if device thinks it succeeded */
74830966 1120 if (status & NAND_STATUS_FAIL) {
289c0522 1121 pr_debug("%s: error status = 0x%08x\n",
7d70f334
VS		 1122 __func__, status);
1123 ret = -EIO;
1124 goto out;
1125 }
1126
1127 ret = __nand_unlock(mtd, ofs, len, 0x1);
1128
1129out:
b0bb6903 1130 chip->select_chip(mtd, -1);
7d70f334
VS		 1131 nand_release_device(mtd);
1132
1133 return ret;
1134}
7351d3a5 1135EXPORT_SYMBOL(nand_lock);
7d70f334 1136
8593fbc6 1137/**
7854d3f7 1138 * nand_read_page_raw - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1139 * @mtd: mtd info structure
1140 * @chip: nand chip info structure
1141 * @buf: buffer to store read data
1fbb938d 1142 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1143 * @page: page number to read
52ff49df 1144 *
7854d3f7 1145 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6
TG		 1146 */
1147static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1148 uint8_t *buf, int oob_required, int page)
8593fbc6
TG		 1149{
1150 chip->read_buf(mtd, buf, mtd->writesize);
279f08d4
BN		 1151 if (oob_required)
1152 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
8593fbc6
TG		 1153 return 0;
1154}
1155
52ff49df 1156/**
7854d3f7 1157 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1158 * @mtd: mtd info structure
1159 * @chip: nand chip info structure
1160 * @buf: buffer to store read data
1fbb938d 1161 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1162 * @page: page number to read
52ff49df
DB		 1163 *
1164 * We need a special oob layout and handling even when OOB isn't used.
1165 */
7351d3a5 1166static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1fbb938d
BN		 1167 struct nand_chip *chip, uint8_t *buf,
1168 int oob_required, int page)
52ff49df
DB		 1169{
1170 int eccsize = chip->ecc.size;
1171 int eccbytes = chip->ecc.bytes;
1172 uint8_t *oob = chip->oob_poi;
1173 int steps, size;
1174
1175 for (steps = chip->ecc.steps; steps > 0; steps--) {
1176 chip->read_buf(mtd, buf, eccsize);
1177 buf += eccsize;
1178
1179 if (chip->ecc.prepad) {
1180 chip->read_buf(mtd, oob, chip->ecc.prepad);
1181 oob += chip->ecc.prepad;
1182 }
1183
1184 chip->read_buf(mtd, oob, eccbytes);
1185 oob += eccbytes;
1186
1187 if (chip->ecc.postpad) {
1188 chip->read_buf(mtd, oob, chip->ecc.postpad);
1189 oob += chip->ecc.postpad;
1190 }
1191 }
1192
1193 size = mtd->oobsize - (oob - chip->oob_poi);
1194 if (size)
1195 chip->read_buf(mtd, oob, size);
1196
1197 return 0;
1198}
1199
1da177e4 1200/**
7854d3f7 1201 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
8b6e50c9
BN		 1202 * @mtd: mtd info structure
1203 * @chip: nand chip info structure
1204 * @buf: buffer to store read data
1fbb938d 1205 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1206 * @page: page number to read
068e3c0a 1207 */
f5bbdacc 1208static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1209 uint8_t *buf, int oob_required, int page)
1da177e4 1210{
f5bbdacc
TG		 1211 int i, eccsize = chip->ecc.size;
1212 int eccbytes = chip->ecc.bytes;
1213 int eccsteps = chip->ecc.steps;
1214 uint8_t *p = buf;
4bf63fcb
DW		 1215 uint8_t *ecc_calc = chip->buffers->ecccalc;
1216 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1217 uint32_t *eccpos = chip->ecc.layout->eccpos;
3f91e94f 1218 unsigned int max_bitflips = 0;
f5bbdacc 1219
1fbb938d 1220 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
f5bbdacc
TG		 1221
1222 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1223 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1224
1225 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1226 ecc_code[i] = chip->oob_poi[eccpos[i]];
f5bbdacc
TG		 1227
1228 eccsteps = chip->ecc.steps;
1229 p = buf;
1230
1231 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1232 int stat;
1233
1234 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
3f91e94f 1235 if (stat < 0) {
f5bbdacc 1236 mtd->ecc_stats.failed++;
3f91e94f 1237 } else {
f5bbdacc 1238 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1239 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1240 }
f5bbdacc 1241 }
3f91e94f 1242 return max_bitflips;
22c60f5f 1243}
1da177e4 1244
3d459559 1245/**
837a6ba4 1246 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
8b6e50c9
BN		 1247 * @mtd: mtd info structure
1248 * @chip: nand chip info structure
1249 * @data_offs: offset of requested data within the page
1250 * @readlen: data length
1251 * @bufpoi: buffer to store read data
3d459559 1252 */
7351d3a5
FF		 1253static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1254 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
3d459559
AK		 1255{
1256 int start_step, end_step, num_steps;
1257 uint32_t *eccpos = chip->ecc.layout->eccpos;
1258 uint8_t *p;
1259 int data_col_addr, i, gaps = 0;
1260 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1261 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
7351d3a5 1262 int index = 0;
3f91e94f 1263 unsigned int max_bitflips = 0;
3d459559 1264
7854d3f7 1265 /* Column address within the page aligned to ECC size (256bytes) */
3d459559
AK		 1266 start_step = data_offs / chip->ecc.size;
1267 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1268 num_steps = end_step - start_step + 1;
1269
8b6e50c9 1270 /* Data size aligned to ECC ecc.size */
3d459559
AK		 1271 datafrag_len = num_steps * chip->ecc.size;
1272 eccfrag_len = num_steps * chip->ecc.bytes;
1273
1274 data_col_addr = start_step * chip->ecc.size;
1275 /* If we read not a page aligned data */
1276 if (data_col_addr != 0)
1277 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1278
1279 p = bufpoi + data_col_addr;
1280 chip->read_buf(mtd, p, datafrag_len);
1281
8b6e50c9 1282 /* Calculate ECC */
3d459559
AK		 1283 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1284 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1285
8b6e50c9
BN		 1286 /*
1287 * The performance is faster if we position offsets according to
7854d3f7 1288 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
8b6e50c9 1289 */
3d459559
AK		 1290 for (i = 0; i < eccfrag_len - 1; i++) {
1291 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1292 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1293 gaps = 1;
1294 break;
1295 }
1296 }
1297 if (gaps) {
1298 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1299 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1300 } else {
8b6e50c9 1301 /*
7854d3f7 1302 * Send the command to read the particular ECC bytes take care
8b6e50c9
BN		 1303 * about buswidth alignment in read_buf.
1304 */
7351d3a5
FF		 1305 index = start_step * chip->ecc.bytes;
1306
1307 aligned_pos = eccpos[index] & ~(busw - 1);
3d459559 1308 aligned_len = eccfrag_len;
7351d3a5 1309 if (eccpos[index] & (busw - 1))
3d459559 1310 aligned_len++;
7351d3a5 1311 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
3d459559
AK		 1312 aligned_len++;
1313
7351d3a5
FF		 1314 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1315 mtd->writesize + aligned_pos, -1);
3d459559
AK		 1316 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1317 }
1318
1319 for (i = 0; i < eccfrag_len; i++)
7351d3a5 1320 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
3d459559
AK		 1321
1322 p = bufpoi + data_col_addr;
1323 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1324 int stat;
1325
7351d3a5
FF		 1326 stat = chip->ecc.correct(mtd, p,
1327 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
3f91e94f 1328 if (stat < 0) {
3d459559 1329 mtd->ecc_stats.failed++;
3f91e94f 1330 } else {
3d459559 1331 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1332 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1333 }
3d459559 1334 }
3f91e94f 1335 return max_bitflips;
3d459559
AK		 1336}
1337
068e3c0a 1338/**
7854d3f7 1339 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
8b6e50c9
BN		 1340 * @mtd: mtd info structure
1341 * @chip: nand chip info structure
1342 * @buf: buffer to store read data
1fbb938d 1343 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1344 * @page: page number to read
068e3c0a 1345 *
7854d3f7 1346 * Not for syndrome calculating ECC controllers which need a special oob layout.
068e3c0a 1347 */
f5bbdacc 1348static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1349 uint8_t *buf, int oob_required, int page)
1da177e4 1350{
f5bbdacc
TG		 1351 int i, eccsize = chip->ecc.size;
1352 int eccbytes = chip->ecc.bytes;
1353 int eccsteps = chip->ecc.steps;
1354 uint8_t *p = buf;
4bf63fcb
DW		 1355 uint8_t *ecc_calc = chip->buffers->ecccalc;
1356 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1357 uint32_t *eccpos = chip->ecc.layout->eccpos;
3f91e94f 1358 unsigned int max_bitflips = 0;
f5bbdacc
TG		 1359
1360 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1361 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1362 chip->read_buf(mtd, p, eccsize);
1363 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1da177e4 1364 }
f75e5097 1365 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4 1366
f5bbdacc 1367 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1368 ecc_code[i] = chip->oob_poi[eccpos[i]];
1da177e4 1369
f5bbdacc
TG		 1370 eccsteps = chip->ecc.steps;
1371 p = buf;
61b03bd7 1372
f5bbdacc
TG		 1373 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1374 int stat;
1da177e4 1375
f5bbdacc 1376 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
3f91e94f 1377 if (stat < 0) {
f5bbdacc 1378 mtd->ecc_stats.failed++;
3f91e94f 1379 } else {
f5bbdacc 1380 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1381 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1382 }
f5bbdacc 1383 }
3f91e94f 1384 return max_bitflips;
f5bbdacc 1385}
1da177e4 1386
6e0cb135 1387/**
7854d3f7 1388 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
8b6e50c9
BN		 1389 * @mtd: mtd info structure
1390 * @chip: nand chip info structure
1391 * @buf: buffer to store read data
1fbb938d 1392 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1393 * @page: page number to read
6e0cb135 1394 *
8b6e50c9
BN		 1395 * Hardware ECC for large page chips, require OOB to be read first. For this
1396 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1397 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1398 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1399 * the data area, by overwriting the NAND manufacturer bad block markings.
6e0cb135
SN		 1400 */
1401static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1fbb938d 1402 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
6e0cb135
SN		 1403{
1404 int i, eccsize = chip->ecc.size;
1405 int eccbytes = chip->ecc.bytes;
1406 int eccsteps = chip->ecc.steps;
1407 uint8_t *p = buf;
1408 uint8_t *ecc_code = chip->buffers->ecccode;
1409 uint32_t *eccpos = chip->ecc.layout->eccpos;
1410 uint8_t *ecc_calc = chip->buffers->ecccalc;
3f91e94f 1411 unsigned int max_bitflips = 0;
6e0cb135
SN		 1412
1413 /* Read the OOB area first */
1414 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1415 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1416 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1417
1418 for (i = 0; i < chip->ecc.total; i++)
1419 ecc_code[i] = chip->oob_poi[eccpos[i]];
1420
1421 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1422 int stat;
1423
1424 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1425 chip->read_buf(mtd, p, eccsize);
1426 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1427
1428 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
3f91e94f 1429 if (stat < 0) {
6e0cb135 1430 mtd->ecc_stats.failed++;
3f91e94f 1431 } else {
6e0cb135 1432 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1433 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1434 }
6e0cb135 1435 }
3f91e94f 1436 return max_bitflips;
6e0cb135
SN		 1437}
1438
f5bbdacc 1439/**
7854d3f7 1440 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
8b6e50c9
BN		 1441 * @mtd: mtd info structure
1442 * @chip: nand chip info structure
1443 * @buf: buffer to store read data
1fbb938d 1444 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1445 * @page: page number to read
f5bbdacc 1446 *
8b6e50c9
BN		 1447 * The hw generator calculates the error syndrome automatically. Therefore we
1448 * need a special oob layout and handling.
f5bbdacc
TG		 1449 */
1450static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1451 uint8_t *buf, int oob_required, int page)
f5bbdacc
TG		 1452{
1453 int i, eccsize = chip->ecc.size;
1454 int eccbytes = chip->ecc.bytes;
1455 int eccsteps = chip->ecc.steps;
1456 uint8_t *p = buf;
f75e5097 1457 uint8_t *oob = chip->oob_poi;
3f91e94f 1458 unsigned int max_bitflips = 0;
1da177e4 1459
f5bbdacc
TG		 1460 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1461 int stat;
61b03bd7 1462
f5bbdacc
TG		 1463 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1464 chip->read_buf(mtd, p, eccsize);
1da177e4 1465
f5bbdacc
TG		 1466 if (chip->ecc.prepad) {
1467 chip->read_buf(mtd, oob, chip->ecc.prepad);
1468 oob += chip->ecc.prepad;
1469 }
1da177e4 1470
f5bbdacc
TG		 1471 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1472 chip->read_buf(mtd, oob, eccbytes);
1473 stat = chip->ecc.correct(mtd, p, oob, NULL);
61b03bd7 1474
3f91e94f 1475 if (stat < 0) {
f5bbdacc 1476 mtd->ecc_stats.failed++;
3f91e94f 1477 } else {
f5bbdacc 1478 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1479 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1480 }
61b03bd7 1481
f5bbdacc 1482 oob += eccbytes;
1da177e4 1483
f5bbdacc
TG		 1484 if (chip->ecc.postpad) {
1485 chip->read_buf(mtd, oob, chip->ecc.postpad);
1486 oob += chip->ecc.postpad;
61b03bd7 1487 }
f5bbdacc 1488 }
1da177e4 1489
f5bbdacc 1490 /* Calculate remaining oob bytes */
7e4178f9 1491 i = mtd->oobsize - (oob - chip->oob_poi);
f5bbdacc
TG		 1492 if (i)
1493 chip->read_buf(mtd, oob, i);
61b03bd7 1494
3f91e94f 1495 return max_bitflips;
f5bbdacc 1496}
1da177e4 1497
f5bbdacc 1498/**
7854d3f7 1499 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
8b6e50c9
BN		 1500 * @chip: nand chip structure
1501 * @oob: oob destination address
1502 * @ops: oob ops structure
1503 * @len: size of oob to transfer
8593fbc6
TG		 1504 */
1505static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
7014568b 1506 struct mtd_oob_ops *ops, size_t len)
8593fbc6 1507{
f8ac0414 1508 switch (ops->mode) {
8593fbc6 1509
0612b9dd
BN		 1510 case MTD_OPS_PLACE_OOB:
1511 case MTD_OPS_RAW:
8593fbc6
TG		 1512 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1513 return oob + len;
1514
0612b9dd 1515 case MTD_OPS_AUTO_OOB: {
8593fbc6 1516 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 1517 uint32_t boffs = 0, roffs = ops->ooboffs;
1518 size_t bytes = 0;
8593fbc6 1519
f8ac0414 1520 for (; free->length && len; free++, len -= bytes) {
8b6e50c9 1521 /* Read request not from offset 0? */
7bc3312b
TG		 1522 if (unlikely(roffs)) {
1523 if (roffs >= free->length) {
1524 roffs -= free->length;
1525 continue;
1526 }
1527 boffs = free->offset + roffs;
1528 bytes = min_t(size_t, len,
1529 (free->length - roffs));
1530 roffs = 0;
1531 } else {
1532 bytes = min_t(size_t, len, free->length);
1533 boffs = free->offset;
1534 }
1535 memcpy(oob, chip->oob_poi + boffs, bytes);
8593fbc6
TG		 1536 oob += bytes;
1537 }
1538 return oob;
1539 }
1540 default:
1541 BUG();
1542 }
1543 return NULL;
1544}
6fa3eb70
S		 1545#ifdef CONFIG_MTK_MTD_NAND
1546struct mtd_perf_log g_MtdPerfLog={0};
1547#endif
8593fbc6 1548/**
7854d3f7 1549 * nand_do_read_ops - [INTERN] Read data with ECC
8b6e50c9
BN		 1550 * @mtd: MTD device structure
1551 * @from: offset to read from
1552 * @ops: oob ops structure
f5bbdacc
TG		 1553 *
1554 * Internal function. Called with chip held.
1555 */
8593fbc6
TG		 1556static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1557 struct mtd_oob_ops *ops)
f5bbdacc 1558{
e47f3db4 1559 int chipnr, page, realpage, col, bytes, aligned, oob_required;
f5bbdacc
TG		 1560 struct nand_chip *chip = mtd->priv;
1561 struct mtd_ecc_stats stats;
f5bbdacc 1562 int ret = 0;
8593fbc6 1563 uint32_t readlen = ops->len;
7014568b 1564 uint32_t oobreadlen = ops->ooblen;
0612b9dd 1565 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
9aca334e
ML		 1566 mtd->oobavail : mtd->oobsize;
1567
8593fbc6 1568 uint8_t *bufpoi, *oob, *buf;
edbc4540 1569 unsigned int max_bitflips = 0;
6fa3eb70
S		 1570#ifdef CONFIG_MTK_MTD_NAND
1571 if(readlen<512)
1572 {
1573 g_MtdPerfLog.read_size_0_512++;
1574 }
1575 else if((512<=readlen)&&(readlen<1024))
1576 {
1577 g_MtdPerfLog.read_size_512_1K++;
1578 }
1579 else if((1024<=readlen)&&(readlen<2048))
1580 {
1581 g_MtdPerfLog.read_size_1K_2K++;
1582 }
1583 else if((2048<=readlen)&&(readlen<3072))
1584 {
1585 g_MtdPerfLog.read_size_2K_3K++;
1586 }
1587 else if((3072<=readlen)&&(readlen<4096))
1588 {
1589 g_MtdPerfLog.read_size_3K_4K++;
1590 }
1591 else
1592 {
1593 g_MtdPerfLog.read_size_Above_4K += ((readlen+ mtd->writesize-1)/mtd->writesize);
1594 }
1da177e4 1595
6fa3eb70 1596#endif
f5bbdacc 1597 stats = mtd->ecc_stats;
1da177e4 1598
f5bbdacc
TG		 1599 chipnr = (int)(from >> chip->chip_shift);
1600 chip->select_chip(mtd, chipnr);
61b03bd7 1601
f5bbdacc
TG		 1602 realpage = (int)(from >> chip->page_shift);
1603 page = realpage & chip->pagemask;
1da177e4 1604
f5bbdacc 1605 col = (int)(from & (mtd->writesize - 1));
61b03bd7 1606
8593fbc6
TG		 1607 buf = ops->datbuf;
1608 oob = ops->oobbuf;
e47f3db4 1609 oob_required = oob ? 1 : 0;
8593fbc6 1610
f8ac0414 1611 while (1) {
f5bbdacc
TG		 1612 bytes = min(mtd->writesize - col, readlen);
1613 aligned = (bytes == mtd->writesize);
61b03bd7 1614
8b6e50c9 1615 /* Is the current page in the buffer? */
8593fbc6 1616 if (realpage != chip->pagebuf || oob) {
4bf63fcb 1617 bufpoi = aligned ? buf : chip->buffers->databuf;
61b03bd7 1618
6fa3eb70
S		 1619#ifdef CONFIG_MTK_MTD_NAND
1620 ret = chip->read_page(mtd, chip, bufpoi, page);
1621#else
c00a0991 1622 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
6fa3eb70 1623 /* Now read the page into the buffer. Absent an error,
edbc4540
MD		 1624 * the read methods return max bitflips per ecc step.
1625 */
0612b9dd 1626 if (unlikely(ops->mode == MTD_OPS_RAW))
1fbb938d 1627 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
e47f3db4
BN		 1628 oob_required,
1629 page);
a5ff4f10
JW		 1630 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1631 !oob)
7351d3a5
FF		 1632 ret = chip->ecc.read_subpage(mtd, chip,
1633 col, bytes, bufpoi);
956e944c 1634 else
46a8cf2d 1635 ret = chip->ecc.read_page(mtd, chip, bufpoi,
e47f3db4 1636 oob_required, page);
6fa3eb70 1637#endif
6d77b9d0
BN		 1638 if (ret < 0) {
1639 if (!aligned)
1640 /* Invalidate page cache */
1641 chip->pagebuf = -1;
1da177e4 1642 break;
6d77b9d0 1643 }
f5bbdacc 1644
edbc4540
MD		 1645 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1646
f5bbdacc
TG		 1647 /* Transfer not aligned data */
1648 if (!aligned) {
a5ff4f10 1649 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
6d77b9d0 1650 !(mtd->ecc_stats.failed - stats.failed) &&
edbc4540 1651 (ops->mode != MTD_OPS_RAW)) {
3d459559 1652 chip->pagebuf = realpage;
edbc4540
MD		 1653 chip->pagebuf_bitflips = ret;
1654 } else {
6d77b9d0
BN		 1655 /* Invalidate page cache */
1656 chip->pagebuf = -1;
edbc4540 1657 }
4bf63fcb 1658 memcpy(buf, chip->buffers->databuf + col, bytes);
f5bbdacc
TG		 1659 }
1660
8593fbc6
TG		 1661 buf += bytes;
1662
1663 if (unlikely(oob)) {
b64d39d8
ML		 1664 int toread = min(oobreadlen, max_oobsize);
1665
1666 if (toread) {
1667 oob = nand_transfer_oob(chip,
1668 oob, ops, toread);
1669 oobreadlen -= toread;
1670 }
8593fbc6 1671 }
5bc7c33c
BN		 1672
1673 if (chip->options & NAND_NEED_READRDY) {
1674 /* Apply delay or wait for ready/busy pin */
1675 if (!chip->dev_ready)
1676 udelay(chip->chip_delay);
1677 else
1678 nand_wait_ready(mtd);
1679 }
8593fbc6 1680 } else {
4bf63fcb 1681 memcpy(buf, chip->buffers->databuf + col, bytes);
8593fbc6 1682 buf += bytes;
edbc4540
MD		 1683 max_bitflips = max_t(unsigned int, max_bitflips,
1684 chip->pagebuf_bitflips);
8593fbc6 1685 }
1da177e4 1686
f5bbdacc 1687 readlen -= bytes;
61b03bd7 1688
f5bbdacc 1689 if (!readlen)
61b03bd7 1690 break;
1da177e4 1691
8b6e50c9 1692 /* For subsequent reads align to page boundary */
1da177e4
LT		 1693 col = 0;
1694 /* Increment page address */
1695 realpage++;
1696
ace4dfee 1697 page = realpage & chip->pagemask;
1da177e4
LT		 1698 /* Check, if we cross a chip boundary */
1699 if (!page) {
1700 chipnr++;
ace4dfee
TG		 1701 chip->select_chip(mtd, -1);
1702 chip->select_chip(mtd, chipnr);
1da177e4 1703 }
1da177e4 1704 }
b0bb6903 1705 chip->select_chip(mtd, -1);
1da177e4 1706
8593fbc6 1707 ops->retlen = ops->len - (size_t) readlen;
7014568b
VW		 1708 if (oob)
1709 ops->oobretlen = ops->ooblen - oobreadlen;
1da177e4 1710
3f91e94f 1711 if (ret < 0)
f5bbdacc
TG		 1712 return ret;
1713
9a1fcdfd
TG		 1714 if (mtd->ecc_stats.failed - stats.failed)
1715 return -EBADMSG;
1716
edbc4540 1717 return max_bitflips;
f5bbdacc
TG		 1718}
1719
6fa3eb70
S		 1720#ifdef CONFIG_MTK_MTD_NAND
1721
1722//#define _SNAND_SUBPAGE_READ_DBG
1723
1724#define MTK_NSS_CACHEV_MAX_CNT (CONFIG_MTK_NSS_CACHEV_MAX_CNT)
1725
1726int g_mtk_nss_cachev_cnt = 0;
1727u32 g_mtk_nss_timestamp = 0;
1728
1729typedef struct
1730{
1731 int val;
1732 unsigned int timestamp;
1733 int part_begin;
1734 int part_end;
1735 u8 * buf;
1736} mtk_nss_cachev_struct;
1737
1738mtk_nss_cachev_struct g_mtk_nss_cachev[MTK_NSS_CACHEV_MAX_CNT];
1739
1740void mtk_nss_add_cache(mtk_nss_cachev_struct *cache, int cache_idx, int target_val, int part_begin, int part_end, u32 *timestamp)
1741{
1742 cache[cache_idx].val = target_val;
1743 cache[cache_idx].part_begin = part_begin;
1744 cache[cache_idx].part_end = part_end;
1745 cache[cache_idx].timestamp = *timestamp;
1746 *timestamp = *timestamp + 1;
1747
1748 #ifdef _SNAND_SUBPAGE_READ_DBG
1749 printk("[CacheV-I] Add,idx %d,page %d,begin %d,end %d,stamp %d\n", cache_idx, target_val, part_begin, part_end, *timestamp-1);
1750 #endif
1751}
1752
1753int mtk_nss_get_victim(mtk_nss_cachev_struct *cache)
1754{
1755 int i;
1756 unsigned int min_timestamp = 0xFFFFFFFF;
1757 int min_idx = -1;
1758
1759 for (i = 0; i < g_mtk_nss_cachev_cnt; i++)
1760 {
1761 if (cache[i].val == -1)
1762 {
1763 return i;
1764 }
1765 else
1766 {
1767 if (cache[i].timestamp < min_timestamp)
1768 {
1769 min_timestamp = cache[i].timestamp;
1770 min_idx = i;
1771 }
1772 }
1773 }
1774
1775 #ifdef _SNAND_SUBPAGE_READ_DBG
1776 printk("[CacheV-I] GetVic,idx %d\n", min_idx);
1777 #endif
1778
1779 return min_idx;
1780}
1781
1782void mtk_nss_invalidate_cache_by_val(mtk_nss_cachev_struct *cache, int target_val)
1783{
1784 int i;
1785
1786 for (i = 0; i < g_mtk_nss_cachev_cnt; i++)
1787 {
1788 if (cache[i].val == target_val)
1789 {
1790 cache[i].val = -1;
1791 }
1792 }
1793
1794 #ifdef _SNAND_SUBPAGE_READ_DBG
1795 printk("[CacheV-I] Invalidate,idx %d,val %d\n", i, target_val);
1796 #endif
1797}
1798
1799void mtk_nss_invalidate_cache_by_idx(mtk_nss_cachev_struct *cache, int idx)
1800{
1801 cache[idx].val = -1;
1802
1803 #ifdef _SNAND_SUBPAGE_READ_DBG
1804 printk("[CacheV-I] Invalidate,idx %d\n", idx);
1805 #endif
1806}
1807
1808void mtk_nss_invalidate_all_cache(mtk_nss_cachev_struct *cache)
1809{
1810 int i;
1811
1812 for (i = 0; i < g_mtk_nss_cachev_cnt; i++)
1813 {
1814 cache[i].val = -1;
1815 }
1816
1817 #ifdef _SNAND_SUBPAGE_READ_DBG
1818 printk("[CacheV-I] Invalidate all\n");
1819 #endif
1820}
1821
1822void mtk_nss_invalidate_cache_by_range(mtk_nss_cachev_struct *cache, int val_min, int val_max)
1823{
1824 int i;
1825
1826 for (i = 0; i < g_mtk_nss_cachev_cnt; i++)
1827 {
1828 if ((cache[i].val >= val_min) &&
1829 (cache[i].val <= val_max))
1830 {
1831 cache[i].val = -1;
1832
1833 #ifdef _SNAND_SUBPAGE_READ_DBG
1834 printk("[CacheV-I] Invalidate idx %d (by range)\n", i);
1835 #endif
1836 }
1837 }
1838}
1839
1840int mtk_nss_if_cache_hit(mtk_nss_cachev_struct *cache, int target_val, int part_begin, int part_end, uint32_t *timestamp, int *hit_type)
1841{
1842 int i;
1843
1844 for (i = 0; i < g_mtk_nss_cachev_cnt; i++)
1845 {
1846 if (cache[i].val == target_val)
1847 {
1848 if ((part_begin >= cache[i].part_begin) &&
1849 (part_end <= cache[i].part_end))
1850 {
1851 *hit_type = 0;
1852 }
1853
1854 else if (part_end <= cache[i].part_end)
1855 {
1856 *hit_type = 1;
1857 }
1858 else if (part_begin >= cache[i].part_begin)
1859 {
1860 *hit_type = 2;
1861 }
1862 else
1863 {
1864 *hit_type = 3;
1865 }
1866
1867 *timestamp = *timestamp + 1;
1868 cache[i].timestamp = *timestamp;
1869
1870 #ifdef _SNAND_SUBPAGE_READ_DBG
1871 printk("[CacheV-I] Hit,idx %d,page %d,blk %d,begin %d,end %d,hit_type %d\n", i, cache[i].val, cache[i].val/64, cache[i].part_begin, cache[i].part_end, *hit_type);
1872 #endif
1873
1874 return i;
1875 }
1876 }
1877
1878 #ifdef _SNAND_SUBPAGE_READ_DBG
1879 printk("[CacheV-I] Miss,tar_page %d,begin %d,end %d\n", target_val, part_begin, part_end);
1880 #endif
1881
1882 *hit_type = -1;
1883
1884 return -1;
1885}
1886
1887void mtk_nss_init_cache(struct mtd_info *mtd)
1888{
1889 struct nand_chip *chip = mtd->priv;
1890 int j;
1891
1892 if (NULL != chip->read_subpage) // driver would like to use CacheV
1893 {
1894 for (j = 0; j < MTK_NSS_CACHEV_MAX_CNT; j++) // try to malloc CacheV one by one
1895 {
1896 g_mtk_nss_cachev[j].buf = kmalloc(mtd->writesize + ARCH_DMA_MINALIGN, GFP_KERNEL);
1897
1898 if (NULL != g_mtk_nss_cachev[j].buf)
1899 {
1900 if ((u32)(g_mtk_nss_cachev[j].buf) & (ARCH_DMA_MINALIGN - 1))
1901 {
1902 g_mtk_nss_cachev[j].buf = (u8 *)((u32)(g_mtk_nss_cachev[j].buf) + (ARCH_DMA_MINALIGN - ((u32)(g_mtk_nss_cachev[j].buf) & (ARCH_DMA_MINALIGN - 1))));
1903 }
1904
1905 g_mtk_nss_cachev[j].val = -1; // initialize each CacheV
1906 g_mtk_nss_cachev[j].timestamp = 0;
1907
1908 printk("[NSS] idx: %d, buf: 0x%X\n", j, (u32)(g_mtk_nss_cachev[j].buf));
1909 }
1910 else
1911 {
1912 break; // can't malloc, just leave
1913 }
1914 }
1915
1916 g_mtk_nss_cachev_cnt = j;
1917
1918 printk("[NSS] Init OK, cnt: %d, aligned size: %d\n", g_mtk_nss_cachev_cnt, ARCH_DMA_MINALIGN);
1919 }
1920 else // disable CacheV
1921 {
1922 g_mtk_nss_cachev_cnt = 0;
1923
1924 printk("[NSS] Disabled\n");
1925 }
1926}
1927
1928static int nand_do_read_ops_ex(struct mtd_info *mtd, loff_t from,
1929 struct mtd_oob_ops *ops)
1930{
1931 int chipnr, page, realpage, col, bytes, aligned;
1932 struct nand_chip *chip = mtd->priv;
1933 struct mtd_ecc_stats stats;
1934 int ret = 0;
1935 uint32_t readlen = ops->len;
1936 uint32_t oobreadlen = ops->ooblen;
1937 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
1938 mtd->oobavail : mtd->oobsize;
1939 uint8_t *bufpoi, *oob, *buf;
1940
1941 uint32_t total_byte_read = 0;
1942 static int last_page = -1;
1943 int subpage_begin, subpage_end;
1944
1945 int toread;
1946 int hit_idx;
1947 int victim_idx;
1948 int hit_type;
1949 int temp_int;
1950
1951 stats = mtd->ecc_stats;
1952
1953 chipnr = (int)(from >> chip->chip_shift);
1954 chip->select_chip(mtd, chipnr);
1955
1956 realpage = (int)(from >> chip->page_shift);
1957 page = realpage & chip->pagemask;
1958
1959 col = (int)(from & (mtd->writesize - 1));
1960
1961 buf = ops->datbuf;
1962 oob = ops->oobbuf;
1963
1964 #ifdef _SNAND_SUBPAGE_READ_DBG
1965 printk("[CacheV] -MTD1,from %u,readlen %d,page %i,last_page %d,blk %d,col %d,buf %X,oob %X\n", (u32)from, readlen, page, last_page, page/64, col, buf, oob);
1966 #endif
1967
1968 while (1)
1969 {
1970 bytes = min(mtd->writesize - col, readlen);
1971 aligned = (bytes == mtd->writesize);
1972
1973 if (likely(!oob))
1974 {
1975 col = (int)((from + total_byte_read) & (mtd->writesize - 1));
1976 subpage_begin = col / chip->subpage_size;
1977 subpage_end = (col + bytes - 1) / chip->subpage_size;
1978
1979 hit_idx = mtk_nss_if_cache_hit(g_mtk_nss_cachev, realpage, subpage_begin, subpage_end, &g_mtk_nss_timestamp, &hit_type);
1980
1981 #ifdef _SNAND_SUBPAGE_READ_DBG
1982 printk("[CacheV] -MTD2-1,from %u,page %i,blk %d,col %d,bytes %d,subbegin %d,subend %d,hit_idx %d,hit_type %d\n", (u32)(from + total_byte_read), page, page/64, col, bytes, subpage_begin, subpage_end, hit_idx, hit_type);
1983 #endif
1984
1985 if (-1 != hit_idx) // perfect hit or partial hit
1986 {
1987 if (0 != hit_type) // partial hit
1988 {
1989 if (1 == hit_type)
1990 {
1991 temp_int = g_mtk_nss_cachev[hit_idx].part_begin - subpage_begin;
1992
1993 ret = chip->read_subpage(mtd, chip, g_mtk_nss_cachev[hit_idx].buf + (subpage_begin * chip->subpage_size), page, subpage_begin, temp_int);
1994
1995 g_mtk_nss_cachev[hit_idx].part_begin = subpage_begin;
1996 }
1997 else if (hit_type == 2)
1998 {
1999 temp_int = subpage_end - g_mtk_nss_cachev[hit_idx].part_end;
2000
2001 ret = chip->read_subpage(mtd, chip, g_mtk_nss_cachev[hit_idx].buf + ((g_mtk_nss_cachev[hit_idx].part_end + 1) * chip->subpage_size), page, g_mtk_nss_cachev[hit_idx].part_end + 1, temp_int);
2002
2003 g_mtk_nss_cachev[hit_idx].part_end = subpage_end;
2004 }
2005 else
2006 {
2007 ret = chip->read_page(mtd, chip, g_mtk_nss_cachev[hit_idx].buf, page);
2008
2009 g_mtk_nss_cachev[hit_idx].part_begin = 0;
2010 g_mtk_nss_cachev[hit_idx].part_end = ((mtd->writesize / chip->subpage_size) - 1);
2011 }
2012 }
2013
2014 // NOTE: Perfect Match needs nothing else to do
2015
2016 memcpy(buf, g_mtk_nss_cachev[hit_idx].buf + col, bytes);
2017 }
2018 else // cahce miss
2019 {
2020 victim_idx = mtk_nss_get_victim(g_mtk_nss_cachev);
2021
2022 if ((realpage == (last_page + 1)) || // favor sequential read
2023 ((subpage_end - subpage_begin + 1) == (mtd->writesize / chip->subpage_size)))
2024 {
2025 ret = chip->read_page(mtd, chip, g_mtk_nss_cachev[victim_idx].buf, page);
2026
2027 g_mtk_nss_cachev[victim_idx].part_begin = 0;
2028 g_mtk_nss_cachev[victim_idx].part_end = ((mtd->writesize / chip->subpage_size) - 1);
2029
2030 mtk_nss_add_cache(g_mtk_nss_cachev, victim_idx, realpage, 0, (mtd->writesize / chip->subpage_size) - 1, &g_mtk_nss_timestamp);
2031 }
2032 else
2033 {
2034 temp_int = (subpage_end - subpage_begin + 1);
2035
2036 ret = chip->read_subpage(mtd, chip, g_mtk_nss_cachev[victim_idx].buf + (subpage_begin * chip->subpage_size), page, subpage_begin, temp_int);
2037
2038 mtk_nss_add_cache(g_mtk_nss_cachev, victim_idx, realpage, subpage_begin, subpage_end, &g_mtk_nss_timestamp);
2039 }
2040
2041 memcpy(buf, g_mtk_nss_cachev[victim_idx].buf + col, bytes);
2042 }
2043 }
2044 else // oob
2045 {
2046 victim_idx = -1;
2047
2048 if (aligned)
2049 {
2050 bufpoi = buf;
2051 }
2052 else // !aligned, use CacheV's buffer
2053 {
2054 victim_idx = mtk_nss_get_victim(g_mtk_nss_cachev);
2055
2056 mtk_nss_invalidate_cache_by_idx(g_mtk_nss_cachev, victim_idx);
2057
2058 bufpoi = g_mtk_nss_cachev[victim_idx].buf;
2059 }
2060
2061 #ifdef _SNAND_SUBPAGE_READ_DBG
2062 printk("[CacheV] -MTD2-2,aligned %d,victim_idx %d\n", aligned, victim_idx);
2063 #endif
2064
2065 ret = chip->read_page(mtd, chip, bufpoi, page);
2066
2067 // for data part
2068
2069 if (!aligned && bytes)
2070 {
2071 memcpy(buf, bufpoi + col, bytes);
2072 }
2073
2074 // for oob
2075 {
2076 toread = min(oobreadlen, max_oobsize);
2077
2078 if (toread)
2079 {
2080 oob = nand_transfer_oob(chip, oob, ops, toread);
2081
2082 oobreadlen -= toread;
2083 }
2084 }
2085
2086 if (-1 != victim_idx)
2087 {
2088 mtk_nss_invalidate_cache_by_idx(g_mtk_nss_cachev, victim_idx);
2089 }
2090 }
2091
2092 // read error, discard cache and leave
2093 if (ret < 0)
2094 {
2095 mtk_nss_invalidate_cache_by_val(g_mtk_nss_cachev, realpage);
2096
2097 break;
2098 }
2099
2100 // discard cache in these cases
2101 if (!oob & // NOTE. oob will not occupy CacheV here
2102 (0 != (mtd->ecc_stats.failed - stats.failed)) ||
2103 (ops->mode == MTD_OPS_RAW))
2104 {
2105 mtk_nss_invalidate_cache_by_val(g_mtk_nss_cachev, realpage);
2106 }
2107
2108 if (!(chip->options & NAND_NO_READRDY)) {
2109 /*
2110 * Apply delay or wait for ready/busy pin. Do
2111 * this before the AUTOINCR check, so no
2112 * problems arise if a chip which does auto
2113 * increment is marked as NOAUTOINCR by the
2114 * board driver.
2115 */
2116 if (!chip->dev_ready)
2117 udelay(chip->chip_delay);
2118 else
2119 nand_wait_ready(mtd);
2120 }
2121
2122 buf += bytes;
2123
2124 readlen -= bytes;
2125
2126 total_byte_read += bytes;
2127
2128 last_page = realpage;
2129
2130 if (!readlen)
2131 {
2132 break;
2133 }
2134
2135 /* For subsequent reads align to page boundary */
2136 col = 0;
2137
2138 /* Increment page address */
2139 realpage++;
2140
2141 page = realpage & chip->pagemask;
2142
2143 /* Check, if we cross a chip boundary */
2144 if (!page)
2145 {
2146 chipnr++;
2147 chip->select_chip(mtd, -1);
2148 chip->select_chip(mtd, chipnr);
2149 }
2150 }
2151
2152 ops->retlen = ops->len - (size_t) readlen;
2153
2154 if (oob)
2155 ops->oobretlen = ops->ooblen - oobreadlen;
2156
2157 if (ret)
2158 return ret;
2159
2160 if (mtd->ecc_stats.failed - stats.failed)
2161 return -EBADMSG;
2162
2163 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
2164}
2165
2166#endif // CONFIG_MTK_MTD_NAND
2167
f5bbdacc 2168/**
25985edc 2169 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
8b6e50c9
BN		 2170 * @mtd: MTD device structure
2171 * @from: offset to read from
2172 * @len: number of bytes to read
2173 * @retlen: pointer to variable to store the number of read bytes
2174 * @buf: the databuffer to put data
f5bbdacc 2175 *
8b6e50c9 2176 * Get hold of the chip and call nand_do_read.
f5bbdacc
TG		 2177 */
2178static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
2179 size_t *retlen, uint8_t *buf)
2180{
4a89ff88 2181 struct mtd_oob_ops ops;
f5bbdacc
TG		 2182 int ret;
2183
6a8214aa 2184 nand_get_device(mtd, FL_READING);
4a89ff88
BN		 2185 ops.len = len;
2186 ops.datbuf = buf;
2187 ops.oobbuf = NULL;
11041ae6 2188 ops.mode = MTD_OPS_PLACE_OOB;
6fa3eb70
S		 2189 #ifdef CONFIG_MTK_MTD_NAND
2190 if (g_mtk_nss_cachev_cnt)
2191 {
2192 ret = nand_do_read_ops_ex(mtd, from, &ops);
2193 }
2194 else
2195 {
2196 ret = nand_do_read_ops(mtd, from, &ops);
2197 }
2198 #else
4a89ff88 2199 ret = nand_do_read_ops(mtd, from, &ops);
6fa3eb70 2200 #endif
4a89ff88 2201 *retlen = ops.retlen;
f5bbdacc 2202 nand_release_device(mtd);
f5bbdacc 2203 return ret;
1da177e4
LT		 2204}
2205
7bc3312b 2206/**
7854d3f7 2207 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
8b6e50c9
BN		 2208 * @mtd: mtd info structure
2209 * @chip: nand chip info structure
2210 * @page: page number to read
7bc3312b
TG		 2211 */
2212static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
5c2ffb11 2213 int page)
7bc3312b 2214{
5c2ffb11 2215 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
7bc3312b 2216 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
5c2ffb11 2217 return 0;
7bc3312b
TG		 2218}
2219
2220/**
7854d3f7 2221 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
7bc3312b 2222 * with syndromes
8b6e50c9
BN		 2223 * @mtd: mtd info structure
2224 * @chip: nand chip info structure
2225 * @page: page number to read
7bc3312b
TG		 2226 */
2227static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
5c2ffb11 2228 int page)
7bc3312b
TG		 2229{
2230 uint8_t *buf = chip->oob_poi;
2231 int length = mtd->oobsize;
2232 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
2233 int eccsize = chip->ecc.size;
2234 uint8_t *bufpoi = buf;
2235 int i, toread, sndrnd = 0, pos;
2236
2237 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
2238 for (i = 0; i < chip->ecc.steps; i++) {
2239 if (sndrnd) {
2240 pos = eccsize + i * (eccsize + chunk);
2241 if (mtd->writesize > 512)
2242 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
2243 else
2244 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
2245 } else
2246 sndrnd = 1;
2247 toread = min_t(int, length, chunk);
2248 chip->read_buf(mtd, bufpoi, toread);
2249 bufpoi += toread;
2250 length -= toread;
2251 }
2252 if (length > 0)
2253 chip->read_buf(mtd, bufpoi, length);
2254
5c2ffb11 2255 return 0;
7bc3312b
TG		 2256}
2257
2258/**
7854d3f7 2259 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
8b6e50c9
BN		 2260 * @mtd: mtd info structure
2261 * @chip: nand chip info structure
2262 * @page: page number to write
7bc3312b
TG		 2263 */
2264static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
2265 int page)
2266{
2267 int status = 0;
2268 const uint8_t *buf = chip->oob_poi;
2269 int length = mtd->oobsize;
2270
2271 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
2272 chip->write_buf(mtd, buf, length);
2273 /* Send command to program the OOB data */
2274 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2275
2276 status = chip->waitfunc(mtd, chip);
2277
0d420f9d 2278 return status & NAND_STATUS_FAIL ? -EIO : 0;
7bc3312b
TG		 2279}
2280
2281/**
7854d3f7 2282 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
8b6e50c9
BN		 2283 * with syndrome - only for large page flash
2284 * @mtd: mtd info structure
2285 * @chip: nand chip info structure
2286 * @page: page number to write
7bc3312b
TG		 2287 */
2288static int nand_write_oob_syndrome(struct mtd_info *mtd,
2289 struct nand_chip *chip, int page)
2290{
2291 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
2292 int eccsize = chip->ecc.size, length = mtd->oobsize;
2293 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
2294 const uint8_t *bufpoi = chip->oob_poi;
2295
2296 /*
2297 * data-ecc-data-ecc ... ecc-oob
2298 * or
2299 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
2300 */
2301 if (!chip->ecc.prepad && !chip->ecc.postpad) {
2302 pos = steps * (eccsize + chunk);
2303 steps = 0;
2304 } else
8b0036ee 2305 pos = eccsize;
7bc3312b
TG		 2306
2307 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
2308 for (i = 0; i < steps; i++) {
2309 if (sndcmd) {
2310 if (mtd->writesize <= 512) {
2311 uint32_t fill = 0xFFFFFFFF;
2312
2313 len = eccsize;
2314 while (len > 0) {
2315 int num = min_t(int, len, 4);
2316 chip->write_buf(mtd, (uint8_t *)&fill,
2317 num);
2318 len -= num;
2319 }
2320 } else {
2321 pos = eccsize + i * (eccsize + chunk);
2322 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
2323 }
2324 } else
2325 sndcmd = 1;
2326 len = min_t(int, length, chunk);
2327 chip->write_buf(mtd, bufpoi, len);
2328 bufpoi += len;
2329 length -= len;
2330 }
2331 if (length > 0)
2332 chip->write_buf(mtd, bufpoi, length);
2333
2334 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2335 status = chip->waitfunc(mtd, chip);
2336
2337 return status & NAND_STATUS_FAIL ? -EIO : 0;
2338}
2339
1da177e4 2340/**
7854d3f7 2341 * nand_do_read_oob - [INTERN] NAND read out-of-band
8b6e50c9
BN		 2342 * @mtd: MTD device structure
2343 * @from: offset to read from
2344 * @ops: oob operations description structure
1da177e4 2345 *
8b6e50c9 2346 * NAND read out-of-band data from the spare area.
1da177e4 2347 */
8593fbc6
TG		 2348static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
2349 struct mtd_oob_ops *ops)
1da177e4 2350{
c00a0991 2351 int page, realpage, chipnr;
ace4dfee 2352 struct nand_chip *chip = mtd->priv;
041e4575 2353 struct mtd_ecc_stats stats;
7014568b
VW		 2354 int readlen = ops->ooblen;
2355 int len;
7bc3312b 2356 uint8_t *buf = ops->oobbuf;
1951f2f7 2357 int ret = 0;
61b03bd7 2358
6fa3eb70
S		 2359#ifdef CONFIG_MTK_MTD_NAND
2360 // variable we need for checksum
2361 u8 oob_checksum = 0;
2362 u8 i, j;
2363 bool empty = true;
2364 struct nand_oobfree *free_entry;
2365#endif
2366#ifdef CONFIG_MTK_MTD_NAND
2367 g_MtdPerfLog.read_size_0_512++;
2368#endif
2369
289c0522 2370 pr_debug("%s: from = 0x%08Lx, len = %i\n",
20d8e248 2371 __func__, (unsigned long long)from, readlen);
1da177e4 2372
041e4575
BN		 2373 stats = mtd->ecc_stats;
2374
0612b9dd 2375 if (ops->mode == MTD_OPS_AUTO_OOB)
7014568b 2376 len = chip->ecc.layout->oobavail;
03736155
AH		 2377 else
2378 len = mtd->oobsize;
2379
2380 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 2381 pr_debug("%s: attempt to start read outside oob\n",
2382 __func__);
03736155
AH		 2383 return -EINVAL;
2384 }
2385
2386 /* Do not allow reads past end of device */
2387 if (unlikely(from >= mtd->size ||
2388 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
2389 (from >> chip->page_shift)) * len)) {
289c0522
BN		 2390 pr_debug("%s: attempt to read beyond end of device\n",
2391 __func__);
03736155
AH		 2392 return -EINVAL;
2393 }
7014568b 2394
7314e9e7 2395 chipnr = (int)(from >> chip->chip_shift);
ace4dfee 2396 chip->select_chip(mtd, chipnr);
1da177e4 2397
7314e9e7
TG		 2398 /* Shift to get page */
2399 realpage = (int)(from >> chip->page_shift);
2400 page = realpage & chip->pagemask;
1da177e4 2401
f8ac0414 2402 while (1) {
0612b9dd 2403 if (ops->mode == MTD_OPS_RAW)
1951f2f7 2404 ret = chip->ecc.read_oob_raw(mtd, chip, page);
c46f6483 2405 else
1951f2f7
SL		 2406 ret = chip->ecc.read_oob(mtd, chip, page);
2407
2408 if (ret < 0)
2409 break;
6fa3eb70
S		 2410#ifdef CONFIG_MTK_MTD_NAND
2411 oob_checksum = 0;
2412 for (i = 0;
2413 i < MTD_MAX_OOBFREE_ENTRIES && chip->ecc.layout->oobfree[i].length;
2414 i++)
2415 {
2416 free_entry = (struct nand_oobfree*)(chip->ecc.layout->oobfree) + i;
2417 for (j = 0; j < free_entry->length; j++)
2418 {
2419 oob_checksum ^= chip->oob_poi[free_entry->offset + j];
2420 if (chip->oob_poi[free_entry->offset + j] != 0xFF)
2421 empty = false;
2422 }
2423 }
2424
2425 if (!empty && (oob_checksum != chip->oob_poi[free_entry->offset + free_entry->length]))
2426 return -EIO;
2427#endif
7014568b
VW		 2428
2429 len = min(len, readlen);
2430 buf = nand_transfer_oob(chip, buf, ops, len);
8593fbc6 2431
5bc7c33c
BN		 2432 if (chip->options & NAND_NEED_READRDY) {
2433 /* Apply delay or wait for ready/busy pin */
2434 if (!chip->dev_ready)
2435 udelay(chip->chip_delay);
2436 else
2437 nand_wait_ready(mtd);
2438 }
2439
7014568b 2440 readlen -= len;
0d420f9d
SZ		 2441 if (!readlen)
2442 break;
2443
7314e9e7
TG		 2444 /* Increment page address */
2445 realpage++;
2446
2447 page = realpage & chip->pagemask;
2448 /* Check, if we cross a chip boundary */
2449 if (!page) {
2450 chipnr++;
2451 chip->select_chip(mtd, -1);
2452 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2453 }
2454 }
b0bb6903 2455 chip->select_chip(mtd, -1);
1da177e4 2456
1951f2f7
SL		 2457 ops->oobretlen = ops->ooblen - readlen;
2458
2459 if (ret < 0)
2460 return ret;
041e4575
BN		 2461
2462 if (mtd->ecc_stats.failed - stats.failed)
2463 return -EBADMSG;
2464
2465 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1da177e4
LT		 2466}
2467
2468/**
8593fbc6 2469 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
8b6e50c9
BN		 2470 * @mtd: MTD device structure
2471 * @from: offset to read from
2472 * @ops: oob operation description structure
1da177e4 2473 *
8b6e50c9 2474 * NAND read data and/or out-of-band data.
1da177e4 2475 */
8593fbc6
TG		 2476static int nand_read_oob(struct mtd_info *mtd, loff_t from,
2477 struct mtd_oob_ops *ops)
1da177e4 2478{
8593fbc6
TG		 2479 int ret = -ENOTSUPP;
2480
2481 ops->retlen = 0;
1da177e4
LT		 2482
2483 /* Do not allow reads past end of device */
6fa3eb70
S		 2484#ifdef CONFIG_MTK_MTD_NAND
2485 if (ops->datbuf && (from + ops->len) > (mtd->size+PMT_POOL_SIZE*mtd->erasesize))
2486#else
2487 if (ops->datbuf && (from + ops->len) > mtd->size)
2488#endif
2489 {
289c0522
BN		 2490 pr_debug("%s: attempt to read beyond end of device\n",
2491 __func__);
1da177e4
LT		 2492 return -EINVAL;
2493 }
2494
6a8214aa 2495 nand_get_device(mtd, FL_READING);
1da177e4 2496
f8ac0414 2497 switch (ops->mode) {
0612b9dd
BN		 2498 case MTD_OPS_PLACE_OOB:
2499 case MTD_OPS_AUTO_OOB:
2500 case MTD_OPS_RAW:
8593fbc6 2501 break;
1da177e4 2502
8593fbc6
TG		 2503 default:
2504 goto out;
2505 }
1da177e4 2506
8593fbc6
TG		 2507 if (!ops->datbuf)
2508 ret = nand_do_read_oob(mtd, from, ops);
2509 else
6fa3eb70
S		 2510 {
2511 #ifdef CONFIG_MTK_MTD_NAND
2512 if (g_mtk_nss_cachev_cnt)
2513 {
2514 ret = nand_do_read_ops_ex(mtd, from, ops);
2515 }
2516 else
2517 {
2518 ret = nand_do_read_ops(mtd, from, ops);
2519 }
2520 #else
8593fbc6 2521 ret = nand_do_read_ops(mtd, from, ops);
6fa3eb70
S		 2522 #endif
2523 }
61b03bd7 2524
7351d3a5 2525out:
8593fbc6
TG		 2526 nand_release_device(mtd);
2527 return ret;
2528}
61b03bd7 2529
1da177e4 2530
8593fbc6 2531/**
7854d3f7 2532 * nand_write_page_raw - [INTERN] raw page write function
8b6e50c9
BN		 2533 * @mtd: mtd info structure
2534 * @chip: nand chip info structure
2535 * @buf: data buffer
1fbb938d 2536 * @oob_required: must write chip->oob_poi to OOB
52ff49df 2537 *
7854d3f7 2538 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6 2539 */
fdbad98d 2540static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 2541 const uint8_t *buf, int oob_required)
8593fbc6
TG		 2542{
2543 chip->write_buf(mtd, buf, mtd->writesize);
279f08d4
BN		 2544 if (oob_required)
2545 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
fdbad98d
JW		 2546
2547 return 0;
1da177e4
LT		 2548}
2549
52ff49df 2550/**
7854d3f7 2551 * nand_write_page_raw_syndrome - [INTERN] raw page write function
8b6e50c9
BN		 2552 * @mtd: mtd info structure
2553 * @chip: nand chip info structure
2554 * @buf: data buffer
1fbb938d 2555 * @oob_required: must write chip->oob_poi to OOB
52ff49df
DB		 2556 *
2557 * We need a special oob layout and handling even when ECC isn't checked.
2558 */
fdbad98d 2559static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
7351d3a5 2560 struct nand_chip *chip,
1fbb938d 2561 const uint8_t *buf, int oob_required)
52ff49df
DB		 2562{
2563 int eccsize = chip->ecc.size;
2564 int eccbytes = chip->ecc.bytes;
2565 uint8_t *oob = chip->oob_poi;
2566 int steps, size;
2567
2568 for (steps = chip->ecc.steps; steps > 0; steps--) {
2569 chip->write_buf(mtd, buf, eccsize);
2570 buf += eccsize;
2571
2572 if (chip->ecc.prepad) {
2573 chip->write_buf(mtd, oob, chip->ecc.prepad);
2574 oob += chip->ecc.prepad;
2575 }
2576
2577 chip->read_buf(mtd, oob, eccbytes);
2578 oob += eccbytes;
2579
2580 if (chip->ecc.postpad) {
2581 chip->write_buf(mtd, oob, chip->ecc.postpad);
2582 oob += chip->ecc.postpad;
2583 }
2584 }
2585
2586 size = mtd->oobsize - (oob - chip->oob_poi);
2587 if (size)
2588 chip->write_buf(mtd, oob, size);
fdbad98d
JW		 2589
2590 return 0;
52ff49df 2591}
9223a456 2592/**
7854d3f7 2593 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
8b6e50c9
BN		 2594 * @mtd: mtd info structure
2595 * @chip: nand chip info structure
2596 * @buf: data buffer
1fbb938d 2597 * @oob_required: must write chip->oob_poi to OOB
9223a456 2598 */
fdbad98d 2599static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 2600 const uint8_t *buf, int oob_required)
9223a456 2601{
f75e5097
TG		 2602 int i, eccsize = chip->ecc.size;
2603 int eccbytes = chip->ecc.bytes;
2604 int eccsteps = chip->ecc.steps;
4bf63fcb 2605 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 2606 const uint8_t *p = buf;
8b099a39 2607 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 2608
7854d3f7 2609 /* Software ECC calculation */
8593fbc6
TG		 2610 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
2611 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456 2612
8593fbc6
TG		 2613 for (i = 0; i < chip->ecc.total; i++)
2614 chip->oob_poi[eccpos[i]] = ecc_calc[i];
9223a456 2615
fdbad98d 2616 return chip->ecc.write_page_raw(mtd, chip, buf, 1);
f75e5097 2617}
9223a456 2618
f75e5097 2619/**
7854d3f7 2620 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
8b6e50c9
BN		 2621 * @mtd: mtd info structure
2622 * @chip: nand chip info structure
2623 * @buf: data buffer
1fbb938d 2624 * @oob_required: must write chip->oob_poi to OOB
f75e5097 2625 */
fdbad98d 2626static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 2627 const uint8_t *buf, int oob_required)
f75e5097
TG		 2628{
2629 int i, eccsize = chip->ecc.size;
2630 int eccbytes = chip->ecc.bytes;
2631 int eccsteps = chip->ecc.steps;
4bf63fcb 2632 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 2633 const uint8_t *p = buf;
8b099a39 2634 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 2635
f75e5097
TG		 2636 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2637 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
29da9cea 2638 chip->write_buf(mtd, p, eccsize);
f75e5097 2639 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456
TG		 2640 }
2641
f75e5097
TG		 2642 for (i = 0; i < chip->ecc.total; i++)
2643 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2644
2645 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
fdbad98d
JW		 2646
2647 return 0;
9223a456
TG		 2648}
2649
837a6ba4
GP		 2650
2651/**
2652 * nand_write_subpage_hwecc - [REPLACABLE] hardware ECC based subpage write
2653 * @mtd: mtd info structure
2654 * @chip: nand chip info structure
2655 * @column: column address of subpage within the page
2656 * @data_len: data length
2657 * @oob_required: must write chip->oob_poi to OOB
2658 */
2659static int nand_write_subpage_hwecc(struct mtd_info *mtd,
2660 struct nand_chip *chip, uint32_t offset,
2661 uint32_t data_len, const uint8_t *data_buf,
2662 int oob_required)
2663{
2664 uint8_t *oob_buf = chip->oob_poi;
2665 uint8_t *ecc_calc = chip->buffers->ecccalc;
2666 int ecc_size = chip->ecc.size;
2667 int ecc_bytes = chip->ecc.bytes;
2668 int ecc_steps = chip->ecc.steps;
2669 uint32_t *eccpos = chip->ecc.layout->eccpos;
2670 uint32_t start_step = offset / ecc_size;
2671 uint32_t end_step = (offset + data_len - 1) / ecc_size;
2672 int oob_bytes = mtd->oobsize / ecc_steps;
2673 int step, i;
2674
2675 for (step = 0; step < ecc_steps; step++) {
2676 /* configure controller for WRITE access */
2677 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2678
2679 /* write data (untouched subpages already masked by 0xFF) */
2680 chip->write_buf(mtd, data_buf, ecc_size);
2681
2682 /* mask ECC of un-touched subpages by padding 0xFF */
2683 if ((step < start_step) || (step > end_step))
2684 memset(ecc_calc, 0xff, ecc_bytes);
2685 else
2686 chip->ecc.calculate(mtd, data_buf, ecc_calc);
2687
2688 /* mask OOB of un-touched subpages by padding 0xFF */
2689 /* if oob_required, preserve OOB metadata of written subpage */
2690 if (!oob_required || (step < start_step) || (step > end_step))
2691 memset(oob_buf, 0xff, oob_bytes);
2692
2693 data_buf += ecc_size;
2694 ecc_calc += ecc_bytes;
2695 oob_buf += oob_bytes;
2696 }
2697
2698 /* copy calculated ECC for whole page to chip->buffer->oob */
2699 /* this include masked-value(0xFF) for unwritten subpages */
2700 ecc_calc = chip->buffers->ecccalc;
2701 for (i = 0; i < chip->ecc.total; i++)
2702 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2703
2704 /* write OOB buffer to NAND device */
2705 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2706
2707 return 0;
2708}
2709
2710
61b03bd7 2711/**
7854d3f7 2712 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
8b6e50c9
BN		 2713 * @mtd: mtd info structure
2714 * @chip: nand chip info structure
2715 * @buf: data buffer
1fbb938d 2716 * @oob_required: must write chip->oob_poi to OOB
1da177e4 2717 *
8b6e50c9
BN		 2718 * The hw generator calculates the error syndrome automatically. Therefore we
2719 * need a special oob layout and handling.
f75e5097 2720 */
fdbad98d 2721static int nand_write_page_syndrome(struct mtd_info *mtd,
1fbb938d
BN		 2722 struct nand_chip *chip,
2723 const uint8_t *buf, int oob_required)
1da177e4 2724{
f75e5097
TG		 2725 int i, eccsize = chip->ecc.size;
2726 int eccbytes = chip->ecc.bytes;
2727 int eccsteps = chip->ecc.steps;
2728 const uint8_t *p = buf;
2729 uint8_t *oob = chip->oob_poi;
1da177e4 2730
f75e5097 2731 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1da177e4 2732
f75e5097
TG		 2733 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2734 chip->write_buf(mtd, p, eccsize);
61b03bd7 2735
f75e5097
TG		 2736 if (chip->ecc.prepad) {
2737 chip->write_buf(mtd, oob, chip->ecc.prepad);
2738 oob += chip->ecc.prepad;
2739 }
2740
2741 chip->ecc.calculate(mtd, p, oob);
2742 chip->write_buf(mtd, oob, eccbytes);
2743 oob += eccbytes;
2744
2745 if (chip->ecc.postpad) {
2746 chip->write_buf(mtd, oob, chip->ecc.postpad);
2747 oob += chip->ecc.postpad;
1da177e4 2748 }
1da177e4 2749 }
f75e5097
TG		 2750
2751 /* Calculate remaining oob bytes */
7e4178f9 2752 i = mtd->oobsize - (oob - chip->oob_poi);
f75e5097
TG		 2753 if (i)
2754 chip->write_buf(mtd, oob, i);
fdbad98d
JW		 2755
2756 return 0;
f75e5097
TG		 2757}
2758
2759/**
956e944c 2760 * nand_write_page - [REPLACEABLE] write one page
8b6e50c9
BN		 2761 * @mtd: MTD device structure
2762 * @chip: NAND chip descriptor
837a6ba4
GP		 2763 * @offset: address offset within the page
2764 * @data_len: length of actual data to be written
8b6e50c9 2765 * @buf: the data to write
1fbb938d 2766 * @oob_required: must write chip->oob_poi to OOB
8b6e50c9
BN		 2767 * @page: page number to write
2768 * @cached: cached programming
2769 * @raw: use _raw version of write_page
f75e5097
TG		 2770 */
2771static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
837a6ba4
GP		 2772 uint32_t offset, int data_len, const uint8_t *buf,
2773 int oob_required, int page, int cached, int raw)
f75e5097 2774{
837a6ba4
GP		 2775 int status, subpage;
2776
2777 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2778 chip->ecc.write_subpage)
2779 subpage = offset || (data_len < mtd->writesize);
2780 else
2781 subpage = 0;
f75e5097
TG		 2782
2783 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2784
956e944c 2785 if (unlikely(raw))
837a6ba4
GP		 2786 status = chip->ecc.write_page_raw(mtd, chip, buf,
2787 oob_required);
2788 else if (subpage)
2789 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
2790 buf, oob_required);
956e944c 2791 else
fdbad98d
JW		 2792 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
2793
2794 if (status < 0)
2795 return status;
f75e5097
TG		 2796
2797 /*
7854d3f7 2798 * Cached progamming disabled for now. Not sure if it's worth the
8b6e50c9 2799 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
f75e5097
TG		 2800 */
2801 cached = 0;
2802
3239a6cd 2803 if (!cached || !NAND_HAS_CACHEPROG(chip)) {
f75e5097
TG		 2804
2805 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
7bc3312b 2806 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2807 /*
2808 * See if operation failed and additional status checks are
8b6e50c9 2809 * available.
f75e5097
TG		 2810 */
2811 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2812 status = chip->errstat(mtd, chip, FL_WRITING, status,
2813 page);
2814
2815 if (status & NAND_STATUS_FAIL)
2816 return -EIO;
2817 } else {
2818 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
7bc3312b 2819 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2820 }
2821
6fa3eb70
S		 2822#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
2823 /* Send command to read back the data */
2824 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2825
2826 if (chip->verify_buf(mtd, buf, mtd->writesize))
2827 return -EIO;
2828#endif
f75e5097 2829 return 0;
1da177e4
LT		 2830}
2831
8593fbc6 2832/**
7854d3f7 2833 * nand_fill_oob - [INTERN] Transfer client buffer to oob
f722013e 2834 * @mtd: MTD device structure
8b6e50c9
BN		 2835 * @oob: oob data buffer
2836 * @len: oob data write length
2837 * @ops: oob ops structure
8593fbc6 2838 */
f722013e
TAA		 2839static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2840 struct mtd_oob_ops *ops)
8593fbc6 2841{
f722013e
TAA		 2842 struct nand_chip *chip = mtd->priv;
2843
2844 /*
2845 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2846 * data from a previous OOB read.
2847 */
2848 memset(chip->oob_poi, 0xff, mtd->oobsize);
2849
f8ac0414 2850 switch (ops->mode) {
8593fbc6 2851
0612b9dd
BN		 2852 case MTD_OPS_PLACE_OOB:
2853 case MTD_OPS_RAW:
8593fbc6
TG		 2854 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2855 return oob + len;
2856
0612b9dd 2857 case MTD_OPS_AUTO_OOB: {
8593fbc6 2858 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 2859 uint32_t boffs = 0, woffs = ops->ooboffs;
2860 size_t bytes = 0;
8593fbc6 2861
f8ac0414 2862 for (; free->length && len; free++, len -= bytes) {
8b6e50c9 2863 /* Write request not from offset 0? */
7bc3312b
TG		 2864 if (unlikely(woffs)) {
2865 if (woffs >= free->length) {
2866 woffs -= free->length;
2867 continue;
2868 }
2869 boffs = free->offset + woffs;
2870 bytes = min_t(size_t, len,
2871 (free->length - woffs));
2872 woffs = 0;
2873 } else {
2874 bytes = min_t(size_t, len, free->length);
2875 boffs = free->offset;
2876 }
8b0036ee 2877 memcpy(chip->oob_poi + boffs, oob, bytes);
8593fbc6
TG		 2878 oob += bytes;
2879 }
2880 return oob;
2881 }
2882 default:
2883 BUG();
2884 }
2885 return NULL;
2886}
2887
f8ac0414 2888#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
1da177e4
LT		 2889
2890/**
7854d3f7 2891 * nand_do_write_ops - [INTERN] NAND write with ECC
8b6e50c9
BN		 2892 * @mtd: MTD device structure
2893 * @to: offset to write to
2894 * @ops: oob operations description structure
1da177e4 2895 *
8b6e50c9 2896 * NAND write with ECC.
1da177e4 2897 */
8593fbc6
TG		 2898static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2899 struct mtd_oob_ops *ops)
1da177e4 2900{
29072b96 2901 int chipnr, realpage, page, blockmask, column;
ace4dfee 2902 struct nand_chip *chip = mtd->priv;
8593fbc6 2903 uint32_t writelen = ops->len;
782ce79a
ML		 2904
2905 uint32_t oobwritelen = ops->ooblen;
0612b9dd 2906 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
782ce79a
ML		 2907 mtd->oobavail : mtd->oobsize;
2908
8593fbc6
TG		 2909 uint8_t *oob = ops->oobbuf;
2910 uint8_t *buf = ops->datbuf;
837a6ba4 2911 int ret;
e47f3db4 2912 int oob_required = oob ? 1 : 0;
1da177e4 2913
8593fbc6 2914 ops->retlen = 0;
29072b96
TG		 2915 if (!writelen)
2916 return 0;
1da177e4 2917
8b6e50c9 2918 /* Reject writes, which are not page aligned */
8593fbc6 2919 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
d0370219
BN		 2920 pr_notice("%s: attempt to write non page aligned data\n",
2921 __func__);
1da177e4
LT		 2922 return -EINVAL;
2923 }
2924
29072b96 2925 column = to & (mtd->writesize - 1);
1da177e4 2926
6a930961
TG		 2927 chipnr = (int)(to >> chip->chip_shift);
2928 chip->select_chip(mtd, chipnr);
2929
1da177e4 2930 /* Check, if it is write protected */
b0bb6903
HS		 2931 if (nand_check_wp(mtd)) {
2932 ret = -EIO;
2933 goto err_out;
2934 }
1da177e4 2935
f75e5097
TG		 2936 realpage = (int)(to >> chip->page_shift);
2937 page = realpage & chip->pagemask;
2938 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
6fa3eb70
S		 2939#ifdef CONFIG_MTK_MLC_NAND_SUPPORT
2940 if(mtk_nand_IsRawPartition(to))
2941 {
2942 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift-1)) - 1;
2943 }
2944#endif
f75e5097
TG		 2945 /* Invalidate the page cache, when we write to the cached page */
2946 if (to <= (chip->pagebuf << chip->page_shift) &&
8593fbc6 2947 (chip->pagebuf << chip->page_shift) < (to + ops->len))
ace4dfee 2948 chip->pagebuf = -1;
61b03bd7 2949
6fa3eb70
S		 2950 #ifdef CONFIG_MTK_MTD_NAND
2951 mtk_nss_invalidate_cache_by_val(g_mtk_nss_cachev, realpage);
2952 #endif
782ce79a 2953 /* Don't allow multipage oob writes with offset */
b0bb6903
HS		 2954 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2955 ret = -EINVAL;
2956 goto err_out;
2957 }
782ce79a 2958
f8ac0414 2959 while (1) {
29072b96 2960 int bytes = mtd->writesize;
f75e5097 2961 int cached = writelen > bytes && page != blockmask;
29072b96
TG		 2962 uint8_t *wbuf = buf;
2963
8b6e50c9 2964 /* Partial page write? */
29072b96
TG		 2965 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2966 cached = 0;
2967 bytes = min_t(int, bytes - column, (int) writelen);
2968 chip->pagebuf = -1;
2969 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2970 memcpy(&chip->buffers->databuf[column], buf, bytes);
2971 wbuf = chip->buffers->databuf;
2972 }
1da177e4 2973
782ce79a
ML		 2974 if (unlikely(oob)) {
2975 size_t len = min(oobwritelen, oobmaxlen);
f722013e 2976 oob = nand_fill_oob(mtd, oob, len, ops);
782ce79a 2977 oobwritelen -= len;
f722013e
TAA		 2978 } else {
2979 /* We still need to erase leftover OOB data */
2980 memset(chip->oob_poi, 0xff, mtd->oobsize);
782ce79a 2981 }
837a6ba4
GP		 2982 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
2983 oob_required, page, cached,
2984 (ops->mode == MTD_OPS_RAW));
f75e5097
TG		 2985 if (ret)
2986 break;
2987
2988 writelen -= bytes;
2989 if (!writelen)
2990 break;
2991
29072b96 2992 column = 0;
f75e5097
TG		 2993 buf += bytes;
2994 realpage++;
2995
2996 page = realpage & chip->pagemask;
2997 /* Check, if we cross a chip boundary */
2998 if (!page) {
2999 chipnr++;
3000 chip->select_chip(mtd, -1);
3001 chip->select_chip(mtd, chipnr);
1da177e4
LT		 3002 }
3003 }
8593fbc6 3004
8593fbc6 3005 ops->retlen = ops->len - writelen;
7014568b
VW		 3006 if (unlikely(oob))
3007 ops->oobretlen = ops->ooblen;
b0bb6903
HS		 3008
3009err_out:
3010 chip->select_chip(mtd, -1);
1da177e4
LT		 3011 return ret;
3012}
3013
2af7c653
SK		 3014/**
3015 * panic_nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 3016 * @mtd: MTD device structure
3017 * @to: offset to write to
3018 * @len: number of bytes to write
3019 * @retlen: pointer to variable to store the number of written bytes
3020 * @buf: the data to write
2af7c653
SK		 3021 *
3022 * NAND write with ECC. Used when performing writes in interrupt context, this
3023 * may for example be called by mtdoops when writing an oops while in panic.
3024 */
3025static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
3026 size_t *retlen, const uint8_t *buf)
3027{
3028 struct nand_chip *chip = mtd->priv;
4a89ff88 3029 struct mtd_oob_ops ops;
2af7c653
SK		 3030 int ret;
3031
6fa3eb70
S		 3032#ifdef CONFIG_MTK_MTD_NAND
3033 nand_enable_clock();
3034#endif
8b6e50c9 3035 /* Wait for the device to get ready */
2af7c653
SK		 3036 panic_nand_wait(mtd, chip, 400);
3037
8b6e50c9 3038 /* Grab the device */
2af7c653
SK		 3039 panic_nand_get_device(chip, mtd, FL_WRITING);
3040
4a89ff88
BN		 3041 ops.len = len;
3042 ops.datbuf = (uint8_t *)buf;
3043 ops.oobbuf = NULL;
11041ae6 3044 ops.mode = MTD_OPS_PLACE_OOB;
2af7c653 3045
4a89ff88 3046 ret = nand_do_write_ops(mtd, to, &ops);
2af7c653 3047
4a89ff88 3048 *retlen = ops.retlen;
6fa3eb70
S		 3049#ifdef CONFIG_MTK_MTD_NAND
3050 nand_disable_clock();
3051#endif
2af7c653
SK		 3052 return ret;
3053}
3054
f75e5097 3055/**
8593fbc6 3056 * nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 3057 * @mtd: MTD device structure
3058 * @to: offset to write to
3059 * @len: number of bytes to write
3060 * @retlen: pointer to variable to store the number of written bytes
3061 * @buf: the data to write
f75e5097 3062 *
8b6e50c9 3063 * NAND write with ECC.
f75e5097 3064 */
8593fbc6
TG		 3065static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
3066 size_t *retlen, const uint8_t *buf)
f75e5097 3067{
4a89ff88 3068 struct mtd_oob_ops ops;
f75e5097
TG		 3069 int ret;
3070
6a8214aa 3071 nand_get_device(mtd, FL_WRITING);
4a89ff88
BN		 3072 ops.len = len;
3073 ops.datbuf = (uint8_t *)buf;
3074 ops.oobbuf = NULL;
11041ae6 3075 ops.mode = MTD_OPS_PLACE_OOB;
4a89ff88 3076 ret = nand_do_write_ops(mtd, to, &ops);
4a89ff88 3077 *retlen = ops.retlen;
f75e5097 3078 nand_release_device(mtd);
8593fbc6 3079 return ret;
f75e5097 3080}
7314e9e7 3081
1da177e4 3082/**
8593fbc6 3083 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
8b6e50c9
BN		 3084 * @mtd: MTD device structure
3085 * @to: offset to write to
3086 * @ops: oob operation description structure
1da177e4 3087 *
8b6e50c9 3088 * NAND write out-of-band.
1da177e4 3089 */
8593fbc6
TG		 3090static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
3091 struct mtd_oob_ops *ops)
1da177e4 3092{
03736155 3093 int chipnr, page, status, len;
ace4dfee 3094 struct nand_chip *chip = mtd->priv;
1da177e4 3095
289c0522 3096 pr_debug("%s: to = 0x%08x, len = %i\n",
20d8e248 3097 __func__, (unsigned int)to, (int)ops->ooblen);
1da177e4 3098
0612b9dd 3099 if (ops->mode == MTD_OPS_AUTO_OOB)
03736155
AH		 3100 len = chip->ecc.layout->oobavail;
3101 else
3102 len = mtd->oobsize;
3103
1da177e4 3104 /* Do not allow write past end of page */
03736155 3105 if ((ops->ooboffs + ops->ooblen) > len) {
289c0522
BN		 3106 pr_debug("%s: attempt to write past end of page\n",
3107 __func__);
1da177e4
LT		 3108 return -EINVAL;
3109 }
3110
03736155 3111 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 3112 pr_debug("%s: attempt to start write outside oob\n",
3113 __func__);
03736155
AH		 3114 return -EINVAL;
3115 }
3116
775adc3d 3117 /* Do not allow write past end of device */
03736155
AH		 3118 if (unlikely(to >= mtd->size ||
3119 ops->ooboffs + ops->ooblen >
3120 ((mtd->size >> chip->page_shift) -
3121 (to >> chip->page_shift)) * len)) {
289c0522
BN		 3122 pr_debug("%s: attempt to write beyond end of device\n",
3123 __func__);
03736155
AH		 3124 return -EINVAL;
3125 }
3126
7314e9e7 3127 chipnr = (int)(to >> chip->chip_shift);
ace4dfee 3128 chip->select_chip(mtd, chipnr);
1da177e4 3129
7314e9e7
TG		 3130 /* Shift to get page */
3131 page = (int)(to >> chip->page_shift);
3132
3133 /*
3134 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
3135 * of my DiskOnChip 2000 test units) will clear the whole data page too
3136 * if we don't do this. I have no clue why, but I seem to have 'fixed'
3137 * it in the doc2000 driver in August 1999. dwmw2.
3138 */
ace4dfee 3139 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4
LT		 3140
3141 /* Check, if it is write protected */
b0bb6903
HS		 3142 if (nand_check_wp(mtd)) {
3143 chip->select_chip(mtd, -1);
8593fbc6 3144 return -EROFS;
b0bb6903 3145 }
61b03bd7 3146
1da177e4 3147 /* Invalidate the page cache, if we write to the cached page */
ace4dfee
TG		 3148 if (page == chip->pagebuf)
3149 chip->pagebuf = -1;
1da177e4 3150
f722013e 3151 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
9ce244b3 3152
0612b9dd 3153 if (ops->mode == MTD_OPS_RAW)
9ce244b3
BN		 3154 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
3155 else
3156 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
1da177e4 3157
b0bb6903
HS		 3158 chip->select_chip(mtd, -1);
3159
7bc3312b
TG		 3160 if (status)
3161 return status;
1da177e4 3162
7014568b 3163 ops->oobretlen = ops->ooblen;
1da177e4 3164
7bc3312b 3165 return 0;
8593fbc6
TG		 3166}
3167
3168/**
3169 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
8b6e50c9
BN		 3170 * @mtd: MTD device structure
3171 * @to: offset to write to
3172 * @ops: oob operation description structure
8593fbc6
TG		 3173 */
3174static int nand_write_oob(struct mtd_info *mtd, loff_t to,
3175 struct mtd_oob_ops *ops)
3176{
8593fbc6
TG		 3177 int ret = -ENOTSUPP;
3178
3179 ops->retlen = 0;
3180
3181 /* Do not allow writes past end of device */
7014568b 3182 if (ops->datbuf && (to + ops->len) > mtd->size) {
289c0522
BN		 3183 pr_debug("%s: attempt to write beyond end of device\n",
3184 __func__);
8593fbc6
TG		 3185 return -EINVAL;
3186 }
3187
6a8214aa 3188 nand_get_device(mtd, FL_WRITING);
8593fbc6 3189
f8ac0414 3190 switch (ops->mode) {
0612b9dd
BN		 3191 case MTD_OPS_PLACE_OOB:
3192 case MTD_OPS_AUTO_OOB:
3193 case MTD_OPS_RAW:
8593fbc6
TG		 3194 break;
3195
3196 default:
3197 goto out;
3198 }
3199
3200 if (!ops->datbuf)
3201 ret = nand_do_write_oob(mtd, to, ops);
3202 else
3203 ret = nand_do_write_ops(mtd, to, ops);
3204
7351d3a5 3205out:
1da177e4 3206 nand_release_device(mtd);
1da177e4
LT		 3207 return ret;
3208}
3209
1da177e4 3210/**
7854d3f7 3211 * single_erase_cmd - [GENERIC] NAND standard block erase command function
8b6e50c9
BN		 3212 * @mtd: MTD device structure
3213 * @page: the page address of the block which will be erased
1da177e4 3214 *
8b6e50c9 3215 * Standard erase command for NAND chips.
1da177e4 3216 */
e0c7d767 3217static void single_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 3218{
ace4dfee 3219 struct nand_chip *chip = mtd->priv;
1da177e4 3220 /* Send commands to erase a block */
ace4dfee
TG		 3221 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
3222 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 3223}
3224
1da177e4
LT		 3225/**
3226 * nand_erase - [MTD Interface] erase block(s)
8b6e50c9
BN		 3227 * @mtd: MTD device structure
3228 * @instr: erase instruction
1da177e4 3229 *
8b6e50c9 3230 * Erase one ore more blocks.
1da177e4 3231 */
e0c7d767 3232static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1da177e4 3233{
e0c7d767 3234 return nand_erase_nand(mtd, instr, 0);
1da177e4 3235}
61b03bd7 3236
1da177e4 3237/**
7854d3f7 3238 * nand_erase_nand - [INTERN] erase block(s)
8b6e50c9
BN		 3239 * @mtd: MTD device structure
3240 * @instr: erase instruction
3241 * @allowbbt: allow erasing the bbt area
1da177e4 3242 *
8b6e50c9 3243 * Erase one ore more blocks.
1da177e4 3244 */
ace4dfee
TG		 3245int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
3246 int allowbbt)
1da177e4 3247{
69423d99 3248 int page, status, pages_per_block, ret, chipnr;
ace4dfee 3249 struct nand_chip *chip = mtd->priv;
69423d99 3250 loff_t len;
6fa3eb70
S		 3251 #ifdef CONFIG_MTK_MLC_NAND_SUPPORT
3252 bool raw_partition = false;
3253 #endif
1da177e4 3254
289c0522
BN		 3255 pr_debug("%s: start = 0x%012llx, len = %llu\n",
3256 __func__, (unsigned long long)instr->addr,
3257 (unsigned long long)instr->len);
1da177e4 3258
6fe5a6ac 3259 if (check_offs_len(mtd, instr->addr, instr->len))
1da177e4 3260 return -EINVAL;
1da177e4 3261
1da177e4 3262 /* Grab the lock and see if the device is available */
6a8214aa 3263 nand_get_device(mtd, FL_ERASING);
1da177e4
LT		 3264
3265 /* Shift to get first page */
ace4dfee
TG		 3266 page = (int)(instr->addr >> chip->page_shift);
3267 chipnr = (int)(instr->addr >> chip->chip_shift);
1da177e4
LT		 3268
3269 /* Calculate pages in each block */
ace4dfee 3270 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
6fa3eb70
S		 3271#ifdef CONFIG_MTK_MLC_NAND_SUPPORT
3272 if(mtk_nand_IsRawPartition(instr->addr))
3273 {
3274 raw_partition = true;
3275 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift-1);
3276 }
3277#endif
1da177e4
LT		 3278
3279 /* Select the NAND device */
ace4dfee 3280 chip->select_chip(mtd, chipnr);
1da177e4 3281
1da177e4
LT		 3282 /* Check, if it is write protected */
3283 if (nand_check_wp(mtd)) {
289c0522
BN		 3284 pr_debug("%s: device is write protected!\n",
3285 __func__);
1da177e4
LT		 3286 instr->state = MTD_ERASE_FAILED;
3287 goto erase_exit;
3288 }
3289
3290 /* Loop through the pages */
3291 len = instr->len;
3292
3293 instr->state = MTD_ERASING;
3294
3295 while (len) {
12183a20 3296 /* Check if we have a bad block, we do not erase bad blocks! */
ace4dfee
TG		 3297 if (nand_block_checkbad(mtd, ((loff_t) page) <<
3298 chip->page_shift, 0, allowbbt)) {
d0370219
BN		 3299 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
3300 __func__, page);
1da177e4
LT		 3301 instr->state = MTD_ERASE_FAILED;
3302 goto erase_exit;
3303 }
61b03bd7 3304
ace4dfee
TG		 3305 /*
3306 * Invalidate the page cache, if we erase the block which
8b6e50c9 3307 * contains the current cached page.
ace4dfee
TG		 3308 */
3309 if (page <= chip->pagebuf && chip->pagebuf <
3310 (page + pages_per_block))
3311 chip->pagebuf = -1;
1da177e4 3312
6fa3eb70
S		 3313 #ifdef CONFIG_MTK_MTD_NAND
3314 mtk_nss_invalidate_cache_by_range(g_mtk_nss_cachev, page, page + pages_per_block - 1);
3315 #endif
3316
3317#ifdef CONFIG_MTK_MTD_NAND
3318 status = chip->erase(mtd, page & chip->pagemask);
3319#else
ace4dfee 3320 chip->erase_cmd(mtd, page & chip->pagemask);
61b03bd7 3321
7bc3312b 3322 status = chip->waitfunc(mtd, chip);
6fa3eb70 3323#endif
ace4dfee
TG		 3324 /*
3325 * See if operation failed and additional status checks are
3326 * available
3327 */
3328 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
3329 status = chip->errstat(mtd, chip, FL_ERASING,
3330 status, page);
068e3c0a 3331
1da177e4 3332 /* See if block erase succeeded */
a4ab4c5d 3333 if (status & NAND_STATUS_FAIL) {
289c0522
BN		 3334 pr_debug("%s: failed erase, page 0x%08x\n",
3335 __func__, page);
1da177e4 3336 instr->state = MTD_ERASE_FAILED;
69423d99
AH		 3337 instr->fail_addr =
3338 ((loff_t)page << chip->page_shift);
1da177e4
LT		 3339 goto erase_exit;
3340 }
30f464b7 3341
1da177e4 3342 /* Increment page address and decrement length */
6fa3eb70
S		 3343#ifdef CONFIG_MTK_MLC_NAND_SUPPORT
3344 if(raw_partition)
3345 {
3346 len -= (1 << (chip->phys_erase_shift-1));
3347 }
3348 else
3349 {
3350 len -= (1 << chip->phys_erase_shift);
3351 }
3352#else
ace4dfee 3353 len -= (1 << chip->phys_erase_shift);
6fa3eb70 3354#endif
1da177e4
LT		 3355 page += pages_per_block;
3356
3357 /* Check, if we cross a chip boundary */
ace4dfee 3358 if (len && !(page & chip->pagemask)) {
1da177e4 3359 chipnr++;
ace4dfee
TG		 3360 chip->select_chip(mtd, -1);
3361 chip->select_chip(mtd, chipnr);
1da177e4
LT		 3362 }
3363 }
3364 instr->state = MTD_ERASE_DONE;
3365
7351d3a5 3366erase_exit:
1da177e4
LT		 3367
3368 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1da177e4
LT		 3369
3370 /* Deselect and wake up anyone waiting on the device */
b0bb6903 3371 chip->select_chip(mtd, -1);
1da177e4
LT		 3372 nand_release_device(mtd);
3373
49defc01
DW		 3374 /* Do call back function */
3375 if (!ret)
3376 mtd_erase_callback(instr);
3377
1da177e4
LT		 3378 /* Return more or less happy */
3379 return ret;
3380}
3381
3382/**
3383 * nand_sync - [MTD Interface] sync
8b6e50c9 3384 * @mtd: MTD device structure
1da177e4 3385 *
8b6e50c9 3386 * Sync is actually a wait for chip ready function.
1da177e4 3387 */
e0c7d767 3388static void nand_sync(struct mtd_info *mtd)
1da177e4 3389{
289c0522 3390 pr_debug("%s: called\n", __func__);
1da177e4
LT		 3391
3392 /* Grab the lock and see if the device is available */
6a8214aa 3393 nand_get_device(mtd, FL_SYNCING);
1da177e4 3394 /* Release it and go back */
e0c7d767 3395 nand_release_device(mtd);
1da177e4
LT		 3396}
3397
1da177e4 3398/**
ace4dfee 3399 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
8b6e50c9
BN		 3400 * @mtd: MTD device structure
3401 * @offs: offset relative to mtd start
1da177e4 3402 */
ace4dfee 3403static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1da177e4 3404{
ace4dfee 3405 return nand_block_checkbad(mtd, offs, 1, 0);
1da177e4
LT		 3406}
3407
3408/**
ace4dfee 3409 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
8b6e50c9
BN		 3410 * @mtd: MTD device structure
3411 * @ofs: offset relative to mtd start
1da177e4 3412 */
e0c7d767 3413static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1da177e4 3414{
ace4dfee 3415 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 3416 int ret;
3417
f8ac0414
FF		 3418 ret = nand_block_isbad(mtd, ofs);
3419 if (ret) {
8b6e50c9 3420 /* If it was bad already, return success and do nothing */
1da177e4
LT		 3421 if (ret > 0)
3422 return 0;
e0c7d767
DW		 3423 return ret;
3424 }
1da177e4 3425
ace4dfee 3426 return chip->block_markbad(mtd, ofs);
1da177e4
LT		 3427}
3428
7db03ecc
HS		 3429/**
3430 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
3431 * @mtd: MTD device structure
3432 * @chip: nand chip info structure
3433 * @addr: feature address.
3434 * @subfeature_param: the subfeature parameters, a four bytes array.
3435 */
3436static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
3437 int addr, uint8_t *subfeature_param)
3438{
3439 int status;
3440
3441 if (!chip->onfi_version)
3442 return -EINVAL;
3443
3444 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
3445 chip->write_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
3446 status = chip->waitfunc(mtd, chip);
3447 if (status & NAND_STATUS_FAIL)
3448 return -EIO;
3449 return 0;
3450}
3451
3452/**
3453 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
3454 * @mtd: MTD device structure
3455 * @chip: nand chip info structure
3456 * @addr: feature address.
3457 * @subfeature_param: the subfeature parameters, a four bytes array.
3458 */
3459static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
3460 int addr, uint8_t *subfeature_param)
3461{
3462 if (!chip->onfi_version)
3463 return -EINVAL;
3464
3465 /* clear the sub feature parameters */
3466 memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
3467
3468 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
3469 chip->read_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
3470 return 0;
3471}
3472
962034f4
VW		 3473/**
3474 * nand_suspend - [MTD Interface] Suspend the NAND flash
8b6e50c9 3475 * @mtd: MTD device structure
962034f4
VW		 3476 */
3477static int nand_suspend(struct mtd_info *mtd)
3478{
6a8214aa 3479 return nand_get_device(mtd, FL_PM_SUSPENDED);
962034f4
VW		 3480}
3481
3482/**
3483 * nand_resume - [MTD Interface] Resume the NAND flash
8b6e50c9 3484 * @mtd: MTD device structure
962034f4
VW		 3485 */
3486static void nand_resume(struct mtd_info *mtd)
3487{
ace4dfee 3488 struct nand_chip *chip = mtd->priv;
962034f4 3489
ace4dfee 3490 if (chip->state == FL_PM_SUSPENDED)
962034f4
VW		 3491 nand_release_device(mtd);
3492 else
d0370219
BN		 3493 pr_err("%s called for a chip which is not in suspended state\n",
3494 __func__);
962034f4
VW		 3495}
3496
8b6e50c9 3497/* Set default functions */
ace4dfee 3498static void nand_set_defaults(struct nand_chip *chip, int busw)
7aa65bfd 3499{
1da177e4 3500 /* check for proper chip_delay setup, set 20us if not */
ace4dfee
TG		 3501 if (!chip->chip_delay)
3502 chip->chip_delay = 20;
1da177e4
LT		 3503
3504 /* check, if a user supplied command function given */
ace4dfee
TG		 3505 if (chip->cmdfunc == NULL)
3506 chip->cmdfunc = nand_command;
1da177e4
LT		 3507
3508 /* check, if a user supplied wait function given */
ace4dfee
TG		 3509 if (chip->waitfunc == NULL)
3510 chip->waitfunc = nand_wait;
3511
3512 if (!chip->select_chip)
3513 chip->select_chip = nand_select_chip;
497587f8
BN		 3514
3515 /* If called twice, pointers that depend on busw may need to be reset */
3516 if (!chip->read_byte || chip->read_byte == nand_read_byte)
ace4dfee
TG		 3517 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
3518 if (!chip->read_word)
3519 chip->read_word = nand_read_word;
3520 if (!chip->block_bad)
3521 chip->block_bad = nand_block_bad;
3522 if (!chip->block_markbad)
3523 chip->block_markbad = nand_default_block_markbad;
497587f8 3524 if (!chip->write_buf || chip->write_buf == nand_write_buf)
ace4dfee 3525 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
497587f8 3526 if (!chip->read_buf || chip->read_buf == nand_read_buf)
ace4dfee 3527 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
ace4dfee
TG		 3528 if (!chip->scan_bbt)
3529 chip->scan_bbt = nand_default_bbt;
f75e5097
TG		 3530
3531 if (!chip->controller) {
3532 chip->controller = &chip->hwcontrol;
3533 spin_lock_init(&chip->controller->lock);
3534 init_waitqueue_head(&chip->controller->wq);
3535 }
3536
7aa65bfd
TG		 3537}
3538
8b6e50c9 3539/* Sanitize ONFI strings so we can safely print them */
d1e1f4e4
FF		 3540static void sanitize_string(uint8_t *s, size_t len)
3541{
3542 ssize_t i;
3543
8b6e50c9 3544 /* Null terminate */
d1e1f4e4
FF		 3545 s[len - 1] = 0;
3546
8b6e50c9 3547 /* Remove non printable chars */
d1e1f4e4
FF		 3548 for (i = 0; i < len - 1; i++) {
3549 if (s[i] < ' ' || s[i] > 127)
3550 s[i] = '?';
3551 }
3552
8b6e50c9 3553 /* Remove trailing spaces */
d1e1f4e4
FF		 3554 strim(s);
3555}
3556
3557static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
3558{
3559 int i;
3560 while (len--) {
3561 crc ^= *p++ << 8;
3562 for (i = 0; i < 8; i++)
3563 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
3564 }
3565
3566 return crc;
3567}
3568
6fb277ba 3569/*
8b6e50c9 3570 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
6fb277ba
FF		 3571 */
3572static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
08c248fb 3573 int *busw)
6fb277ba
FF		 3574{
3575 struct nand_onfi_params *p = &chip->onfi_params;
3576 int i;
3577 int val;
3578
0ce82b7f
MC		 3579 /* ONFI need to be probed in 8 bits mode, and 16 bits should be selected with NAND_BUSWIDTH_AUTO */
3580 if (chip->options & NAND_BUSWIDTH_16) {
3581 pr_err("Trying ONFI probe in 16 bits mode, aborting !\n");
3582 return 0;
3583 }
7854d3f7 3584 /* Try ONFI for unknown chip or LP */
6fb277ba
FF		 3585 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
3586 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
3587 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
3588 return 0;
3589
6fb277ba
FF		 3590 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3591 for (i = 0; i < 3; i++) {
3592 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
3593 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
3594 le16_to_cpu(p->crc)) {
9a4d4d69 3595 pr_info("ONFI param page %d valid\n", i);
6fb277ba
FF		 3596 break;
3597 }
3598 }
3599
3600 if (i == 3)
3601 return 0;
3602
8b6e50c9 3603 /* Check version */
6fb277ba 3604 val = le16_to_cpu(p->revision);
b7b1a29d
BN		 3605 if (val & (1 << 5))
3606 chip->onfi_version = 23;
3607 else if (val & (1 << 4))
6fb277ba
FF		 3608 chip->onfi_version = 22;
3609 else if (val & (1 << 3))
3610 chip->onfi_version = 21;
3611 else if (val & (1 << 2))
3612 chip->onfi_version = 20;
b7b1a29d 3613 else if (val & (1 << 1))
6fb277ba 3614 chip->onfi_version = 10;
b7b1a29d
BN		 3615
3616 if (!chip->onfi_version) {
d0370219 3617 pr_info("%s: unsupported ONFI version: %d\n", __func__, val);
b7b1a29d
BN		 3618 return 0;
3619 }
6fb277ba
FF		 3620
3621 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3622 sanitize_string(p->model, sizeof(p->model));
3623 if (!mtd->name)
3624 mtd->name = p->model;
017beeaf 3625
6fb277ba 3626 mtd->writesize = le32_to_cpu(p->byte_per_page);
017beeaf
BN		 3627
3628 /*
3629 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3630 * (don't ask me who thought of this...). MTD assumes that these
3631 * dimensions will be power-of-2, so just truncate the remaining area.
3632 */
3633 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3634 mtd->erasesize *= mtd->writesize;
3635
6fb277ba 3636 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
017beeaf
BN		 3637
3638 /* See erasesize comment */
3639 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
63795755 3640 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
08c248fb 3641 *busw = 0;
6fb277ba 3642 if (le16_to_cpu(p->features) & 1)
08c248fb 3643 *busw = NAND_BUSWIDTH_16;
6fb277ba 3644
d42b5de3 3645 pr_info("ONFI flash detected\n");
6fb277ba
FF		 3646 return 1;
3647}
3648
e3b88bd6
BN		 3649/*
3650 * nand_id_has_period - Check if an ID string has a given wraparound period
3651 * @id_data: the ID string
3652 * @arrlen: the length of the @id_data array
3653 * @period: the period of repitition
3654 *
3655 * Check if an ID string is repeated within a given sequence of bytes at
3656 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
d4d4f1bf 3657 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
e3b88bd6
BN		 3658 * if the repetition has a period of @period; otherwise, returns zero.
3659 */
3660static int nand_id_has_period(u8 *id_data, int arrlen, int period)
3661{
3662 int i, j;
3663 for (i = 0; i < period; i++)
3664 for (j = i + period; j < arrlen; j += period)
3665 if (id_data[i] != id_data[j])
3666 return 0;
3667 return 1;
3668}
3669
3670/*
3671 * nand_id_len - Get the length of an ID string returned by CMD_READID
3672 * @id_data: the ID string
3673 * @arrlen: the length of the @id_data array
3674
3675 * Returns the length of the ID string, according to known wraparound/trailing
3676 * zero patterns. If no pattern exists, returns the length of the array.
3677 */
3678static int nand_id_len(u8 *id_data, int arrlen)
3679{
3680 int last_nonzero, period;
3681
3682 /* Find last non-zero byte */
3683 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
3684 if (id_data[last_nonzero])
3685 break;
3686
3687 /* All zeros */
3688 if (last_nonzero < 0)
3689 return 0;
3690
3691 /* Calculate wraparound period */
3692 for (period = 1; period < arrlen; period++)
3693 if (nand_id_has_period(id_data, arrlen, period))
3694 break;
3695
3696 /* There's a repeated pattern */
3697 if (period < arrlen)
3698 return period;
3699
3700 /* There are trailing zeros */
3701 if (last_nonzero < arrlen - 1)
3702 return last_nonzero + 1;
3703
3704 /* No pattern detected */
3705 return arrlen;
3706}
3707
fc09bbc0
BN		 3708/*
3709 * Many new NAND share similar device ID codes, which represent the size of the
3710 * chip. The rest of the parameters must be decoded according to generic or
3711 * manufacturer-specific "extended ID" decoding patterns.
3712 */
3713static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
3714 u8 id_data[8], int *busw)
3715{
e3b88bd6 3716 int extid, id_len;
fc09bbc0
BN		 3717 /* The 3rd id byte holds MLC / multichip data */
3718 chip->cellinfo = id_data[2];
3719 /* The 4th id byte is the important one */
3720 extid = id_data[3];
3721
e3b88bd6
BN		 3722 id_len = nand_id_len(id_data, 8);
3723
fc09bbc0
BN		 3724 /*
3725 * Field definitions are in the following datasheets:
3726 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
af451af4 3727 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
73ca392f 3728 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
fc09bbc0 3729 *
af451af4
BN		 3730 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3731 * ID to decide what to do.
fc09bbc0 3732 */
af451af4 3733 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
6924d99f 3734 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
af451af4 3735 id_data[5] != 0x00) {
fc09bbc0
BN		 3736 /* Calc pagesize */
3737 mtd->writesize = 2048 << (extid & 0x03);
3738 extid >>= 2;
3739 /* Calc oobsize */
e2d3a35e 3740 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
fc09bbc0
BN		 3741 case 1:
3742 mtd->oobsize = 128;
3743 break;
3744 case 2:
3745 mtd->oobsize = 218;
3746 break;
3747 case 3:
3748 mtd->oobsize = 400;
3749 break;
e2d3a35e 3750 case 4:
fc09bbc0
BN		 3751 mtd->oobsize = 436;
3752 break;
e2d3a35e
BN		 3753 case 5:
3754 mtd->oobsize = 512;
3755 break;
3756 case 6:
3757 default: /* Other cases are "reserved" (unknown) */
3758 mtd->oobsize = 640;
3759 break;
fc09bbc0
BN		 3760 }
3761 extid >>= 2;
3762 /* Calc blocksize */
3763 mtd->erasesize = (128 * 1024) <<
3764 (((extid >> 1) & 0x04) | (extid & 0x03));
3765 *busw = 0;
73ca392f
BN		 3766 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
3767 (chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3768 unsigned int tmp;
3769
3770 /* Calc pagesize */
3771 mtd->writesize = 2048 << (extid & 0x03);
3772 extid >>= 2;
3773 /* Calc oobsize */
3774 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3775 case 0:
3776 mtd->oobsize = 128;
3777 break;
3778 case 1:
3779 mtd->oobsize = 224;
3780 break;
3781 case 2:
3782 mtd->oobsize = 448;
3783 break;
3784 case 3:
3785 mtd->oobsize = 64;
3786 break;
3787 case 4:
3788 mtd->oobsize = 32;
3789 break;
3790 case 5:
3791 mtd->oobsize = 16;
3792 break;
3793 default:
3794 mtd->oobsize = 640;
3795 break;
3796 }
3797 extid >>= 2;
3798 /* Calc blocksize */
3799 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3800 if (tmp < 0x03)
3801 mtd->erasesize = (128 * 1024) << tmp;
3802 else if (tmp == 0x03)
3803 mtd->erasesize = 768 * 1024;
3804 else
3805 mtd->erasesize = (64 * 1024) << tmp;
3806 *busw = 0;
fc09bbc0
BN		 3807 } else {
3808 /* Calc pagesize */
3809 mtd->writesize = 1024 << (extid & 0x03);
3810 extid >>= 2;
3811 /* Calc oobsize */
3812 mtd->oobsize = (8 << (extid & 0x01)) *
3813 (mtd->writesize >> 9);
3814 extid >>= 2;
3815 /* Calc blocksize. Blocksize is multiples of 64KiB */
3816 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3817 extid >>= 2;
3818 /* Get buswidth information */
3819 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3820 }
3821}
3822
f23a481c
BN		 3823/*
3824 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3825 * decodes a matching ID table entry and assigns the MTD size parameters for
3826 * the chip.
3827 */
3828static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3829 struct nand_flash_dev *type, u8 id_data[8],
3830 int *busw)
3831{
3832 int maf_id = id_data[0];
3833
3834 mtd->erasesize = type->erasesize;
3835 mtd->writesize = type->pagesize;
3836 mtd->oobsize = mtd->writesize / 32;
3837 *busw = type->options & NAND_BUSWIDTH_16;
3838
3839 /*
3840 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3841 * some Spansion chips have erasesize that conflicts with size
3842 * listed in nand_ids table.
3843 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3844 */
3845 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3846 && id_data[6] == 0x00 && id_data[7] == 0x00
3847 && mtd->writesize == 512) {
3848 mtd->erasesize = 128 * 1024;
3849 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3850 }
3851}
3852
7e74c2d7
BN		 3853/*
3854 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3855 * heuristic patterns using various detected parameters (e.g., manufacturer,
3856 * page size, cell-type information).
3857 */
3858static void nand_decode_bbm_options(struct mtd_info *mtd,
3859 struct nand_chip *chip, u8 id_data[8])
3860{
3861 int maf_id = id_data[0];
3862
3863 /* Set the bad block position */
3864 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3865 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3866 else
3867 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3868
3869 /*
3870 * Bad block marker is stored in the last page of each block on Samsung
3871 * and Hynix MLC devices; stored in first two pages of each block on
3872 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3873 * AMD/Spansion, and Macronix. All others scan only the first page.
3874 */
3875 if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3876 (maf_id == NAND_MFR_SAMSUNG ||
3877 maf_id == NAND_MFR_HYNIX))
3878 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3879 else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3880 (maf_id == NAND_MFR_SAMSUNG ||
3881 maf_id == NAND_MFR_HYNIX ||
3882 maf_id == NAND_MFR_TOSHIBA ||
3883 maf_id == NAND_MFR_AMD ||
3884 maf_id == NAND_MFR_MACRONIX)) ||
3885 (mtd->writesize == 2048 &&
3886 maf_id == NAND_MFR_MICRON))
3887 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3888}
3889
ec6e87e3
HS		 3890static inline bool is_full_id_nand(struct nand_flash_dev *type)
3891{
3892 return type->id_len;
3893}
3894
3895static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
3896 struct nand_flash_dev *type, u8 *id_data, int *busw)
3897{
3898 if (!strncmp(type->id, id_data, type->id_len)) {
3899 mtd->writesize = type->pagesize;
3900 mtd->erasesize = type->erasesize;
3901 mtd->oobsize = type->oobsize;
3902
3903 chip->cellinfo = id_data[2];
3904 chip->chipsize = (uint64_t)type->chipsize << 20;
3905 chip->options |= type->options;
3906
3907 *busw = type->options & NAND_BUSWIDTH_16;
3908
3909 return true;
3910 }
3911 return false;
3912}
3913
7aa65bfd 3914/*
8b6e50c9 3915 * Get the flash and manufacturer id and lookup if the type is supported.
7aa65bfd
TG		 3916 */
3917static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
ace4dfee 3918 struct nand_chip *chip,
7351d3a5
FF		 3919 int busw,
3920 int *maf_id, int *dev_id,
5e81e88a 3921 struct nand_flash_dev *type)
7aa65bfd 3922{
d1e1f4e4 3923 int i, maf_idx;
426c457a 3924 u8 id_data[8];
1da177e4
LT		 3925
3926 /* Select the device */
ace4dfee 3927 chip->select_chip(mtd, 0);
1da177e4 3928
ef89a880
KB		 3929 /*
3930 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
8b6e50c9 3931 * after power-up.
ef89a880
KB		 3932 */
3933 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3934
1da177e4 3935 /* Send the command for reading device ID */
ace4dfee 3936 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4
LT		 3937
3938 /* Read manufacturer and device IDs */
ace4dfee 3939 *maf_id = chip->read_byte(mtd);
d1e1f4e4 3940 *dev_id = chip->read_byte(mtd);
1da177e4 3941
8b6e50c9
BN		 3942 /*
3943 * Try again to make sure, as some systems the bus-hold or other
ed8165c7
BD		 3944 * interface concerns can cause random data which looks like a
3945 * possibly credible NAND flash to appear. If the two results do
3946 * not match, ignore the device completely.
3947 */
3948
3949 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3950
4aef9b78
BN		 3951 /* Read entire ID string */
3952 for (i = 0; i < 8; i++)
426c457a 3953 id_data[i] = chip->read_byte(mtd);
ed8165c7 3954
d1e1f4e4 3955 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
9a4d4d69 3956 pr_info("%s: second ID read did not match "
d0370219
BN		 3957 "%02x,%02x against %02x,%02x\n", __func__,
3958 *maf_id, *dev_id, id_data[0], id_data[1]);
ed8165c7
BD		 3959 return ERR_PTR(-ENODEV);
3960 }
3961
7aa65bfd 3962 if (!type)
5e81e88a
DW		 3963 type = nand_flash_ids;
3964
ec6e87e3
HS		 3965 for (; type->name != NULL; type++) {
3966 if (is_full_id_nand(type)) {
3967 if (find_full_id_nand(mtd, chip, type, id_data, &busw))
3968 goto ident_done;
3969 } else if (*dev_id == type->dev_id) {
3970 break;
3971 }
3972 }
5e81e88a 3973
d1e1f4e4
FF		 3974 chip->onfi_version = 0;
3975 if (!type->name || !type->pagesize) {
6fb277ba 3976 /* Check is chip is ONFI compliant */
47450b35 3977 if (nand_flash_detect_onfi(mtd, chip, &busw))
6fb277ba 3978 goto ident_done;
d1e1f4e4
FF		 3979 }
3980
5e81e88a 3981 if (!type->name)
7aa65bfd
TG		 3982 return ERR_PTR(-ENODEV);
3983
ba0251fe
TG		 3984 if (!mtd->name)
3985 mtd->name = type->name;
3986
69423d99 3987 chip->chipsize = (uint64_t)type->chipsize << 20;
7aa65bfd 3988
12a40a57 3989 if (!type->pagesize && chip->init_size) {
8b6e50c9 3990 /* Set the pagesize, oobsize, erasesize by the driver */
12a40a57
HS		 3991 busw = chip->init_size(mtd, chip, id_data);
3992 } else if (!type->pagesize) {
fc09bbc0
BN		 3993 /* Decode parameters from extended ID */
3994 nand_decode_ext_id(mtd, chip, id_data, &busw);
7aa65bfd 3995 } else {
f23a481c 3996 nand_decode_id(mtd, chip, type, id_data, &busw);
7aa65bfd 3997 }
bf7a01bf
BN		 3998 /* Get chip options */
3999 chip->options |= type->options;
d1e1f4e4 4000
8b6e50c9
BN		 4001 /*
4002 * Check if chip is not a Samsung device. Do not clear the
4003 * options for chips which do not have an extended id.
d1e1f4e4
FF		 4004 */
4005 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
4006 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
4007ident_done:
4008
7aa65bfd 4009 /* Try to identify manufacturer */
9a909867 4010 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
7aa65bfd
TG		 4011 if (nand_manuf_ids[maf_idx].id == *maf_id)
4012 break;
4013 }
0ea4a755 4014
64b37b2a
MC		 4015 if (chip->options & NAND_BUSWIDTH_AUTO) {
4016 WARN_ON(chip->options & NAND_BUSWIDTH_16);
4017 chip->options |= busw;
4018 nand_set_defaults(chip, busw);
4019 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
4020 /*
4021 * Check, if buswidth is correct. Hardware drivers should set
4022 * chip correct!
4023 */
9a4d4d69 4024 pr_info("NAND device: Manufacturer ID:"
d0370219
BN		 4025 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
4026 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
9a4d4d69 4027 pr_warn("NAND bus width %d instead %d bit\n",
d0370219
BN		 4028 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
4029 busw ? 16 : 8);
7aa65bfd
TG		 4030 return ERR_PTR(-EINVAL);
4031 }
61b03bd7 4032
7e74c2d7
BN		 4033 nand_decode_bbm_options(mtd, chip, id_data);
4034
7aa65bfd 4035 /* Calculate the address shift from the page size */
ace4dfee 4036 chip->page_shift = ffs(mtd->writesize) - 1;
8b6e50c9 4037 /* Convert chipsize to number of pages per chip -1 */
ace4dfee 4038 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
61b03bd7 4039
ace4dfee 4040 chip->bbt_erase_shift = chip->phys_erase_shift =
7aa65bfd 4041 ffs(mtd->erasesize) - 1;
69423d99
AH		 4042 if (chip->chipsize & 0xffffffff)
4043 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
7351d3a5
FF		 4044 else {
4045 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
4046 chip->chip_shift += 32 - 1;
4047 }
1da177e4 4048
26d9be11 4049 chip->badblockbits = 8;
14c65786 4050 chip->erase_cmd = single_erase_cmd;
7aa65bfd 4051
8b6e50c9 4052 /* Do not replace user supplied command function! */
ace4dfee
TG		 4053 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
4054 chip->cmdfunc = nand_command_lp;
7aa65bfd 4055
886bd33d 4056 pr_info("NAND device: Manufacturer ID: 0x%02x, Chip ID: 0x%02x (%s %s),"
2fd71a29 4057 " %dMiB, page size: %d, OOB size: %d\n",
886bd33d
HS		 4058 *maf_id, *dev_id, nand_manuf_ids[maf_idx].name,
4059 chip->onfi_version ? chip->onfi_params.model : type->name,
2fd71a29 4060 (int)(chip->chipsize >> 20), mtd->writesize, mtd->oobsize);
7aa65bfd
TG		 4061
4062 return type;
4063}
4064
7aa65bfd 4065/**
3b85c321 4066 * nand_scan_ident - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 4067 * @mtd: MTD device structure
4068 * @maxchips: number of chips to scan for
4069 * @table: alternative NAND ID table
7aa65bfd 4070 *
8b6e50c9
BN		 4071 * This is the first phase of the normal nand_scan() function. It reads the
4072 * flash ID and sets up MTD fields accordingly.
7aa65bfd 4073 *
3b85c321 4074 * The mtd->owner field must be set to the module of the caller.
7aa65bfd 4075 */
5e81e88a
DW		 4076int nand_scan_ident(struct mtd_info *mtd, int maxchips,
4077 struct nand_flash_dev *table)
7aa65bfd 4078{
d1e1f4e4 4079 int i, busw, nand_maf_id, nand_dev_id;
ace4dfee 4080 struct nand_chip *chip = mtd->priv;
7aa65bfd
TG		 4081 struct nand_flash_dev *type;
4082
7aa65bfd 4083 /* Get buswidth to select the correct functions */
ace4dfee 4084 busw = chip->options & NAND_BUSWIDTH_16;
7aa65bfd 4085 /* Set the default functions */
ace4dfee 4086 nand_set_defaults(chip, busw);
7aa65bfd
TG		 4087
4088 /* Read the flash type */
7351d3a5
FF		 4089 type = nand_get_flash_type(mtd, chip, busw,
4090 &nand_maf_id, &nand_dev_id, table);
7aa65bfd
TG		 4091
4092 if (IS_ERR(type)) {
b1c6e6db 4093 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
d0370219 4094 pr_warn("No NAND device found\n");
ace4dfee 4095 chip->select_chip(mtd, -1);
7aa65bfd 4096 return PTR_ERR(type);
1da177e4
LT		 4097 }
4098
07300164
HS		 4099 chip->select_chip(mtd, -1);
4100
7aa65bfd 4101 /* Check for a chip array */
e0c7d767 4102 for (i = 1; i < maxchips; i++) {
ace4dfee 4103 chip->select_chip(mtd, i);
ef89a880
KB		 4104 /* See comment in nand_get_flash_type for reset */
4105 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4 4106 /* Send the command for reading device ID */
ace4dfee 4107 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4 4108 /* Read manufacturer and device IDs */
ace4dfee 4109 if (nand_maf_id != chip->read_byte(mtd) ||
07300164
HS		 4110 nand_dev_id != chip->read_byte(mtd)) {
4111 chip->select_chip(mtd, -1);
1da177e4 4112 break;
07300164
HS		 4113 }
4114 chip->select_chip(mtd, -1);
1da177e4
LT		 4115 }
4116 if (i > 1)
9a4d4d69 4117 pr_info("%d NAND chips detected\n", i);
6fa3eb70
S		 4118#ifdef CONFIG_MTK_MLC_NAND_SUPPORT
4119 /* Store the number of chips and calc total size for mtd */
4120 chip->numchips = i;
4121 mtd->size = i * chip->chipsize;
4122 if(g_b2Die_CS && (i > 1))
4123 {
4124 chip->pagemask = (mtd->size >> chip->page_shift) - 1;
4125 if (mtd->size & 0xffffffff)
4126 chip->chip_shift = ffs((unsigned)mtd->size) - 1;
4127 else {
4128 chip->chip_shift = ffs((unsigned)(mtd->size >> 32));
4129 chip->chip_shift += 32 - 1;
4130 }
4131 }
4132#else
1da177e4 4133 /* Store the number of chips and calc total size for mtd */
ace4dfee
TG		 4134 chip->numchips = i;
4135 mtd->size = i * chip->chipsize;
6fa3eb70 4136#endif
3b85c321
DW		 4137 return 0;
4138}
7351d3a5 4139EXPORT_SYMBOL(nand_scan_ident);
3b85c321
DW		 4140
4141
4142/**
4143 * nand_scan_tail - [NAND Interface] Scan for the NAND device
8b6e50c9 4144 * @mtd: MTD device structure
3b85c321 4145 *
8b6e50c9
BN		 4146 * This is the second phase of the normal nand_scan() function. It fills out
4147 * all the uninitialized function pointers with the defaults and scans for a
4148 * bad block table if appropriate.
3b85c321
DW		 4149 */
4150int nand_scan_tail(struct mtd_info *mtd)
4151{
4152 int i;
4153 struct nand_chip *chip = mtd->priv;
4154
e2414f4c
BN		 4155 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
4156 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
4157 !(chip->bbt_options & NAND_BBT_USE_FLASH));
4158
4bf63fcb
DW		 4159 if (!(chip->options & NAND_OWN_BUFFERS))
4160 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
4161 if (!chip->buffers)
4162 return -ENOMEM;
4163
7dcdcbef 4164 /* Set the internal oob buffer location, just after the page data */
784f4d5e 4165 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
1da177e4 4166
7aa65bfd 4167 /*
8b6e50c9 4168 * If no default placement scheme is given, select an appropriate one.
7aa65bfd 4169 */
193bd400 4170 if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
61b03bd7 4171 switch (mtd->oobsize) {
1da177e4 4172 case 8:
5bd34c09 4173 chip->ecc.layout = &nand_oob_8;
1da177e4
LT		 4174 break;
4175 case 16:
5bd34c09 4176 chip->ecc.layout = &nand_oob_16;
1da177e4
LT		 4177 break;
4178 case 64:
5bd34c09 4179 chip->ecc.layout = &nand_oob_64;
1da177e4 4180 break;
81ec5364
TG		 4181 case 128:
4182 chip->ecc.layout = &nand_oob_128;
4183 break;
1da177e4 4184 default:
d0370219
BN		 4185 pr_warn("No oob scheme defined for oobsize %d\n",
4186 mtd->oobsize);
1da177e4
LT		 4187 BUG();
4188 }
4189 }
61b03bd7 4190
956e944c
DW		 4191 if (!chip->write_page)
4192 chip->write_page = nand_write_page;
4193
7db03ecc
HS		 4194 /* set for ONFI nand */
4195 if (!chip->onfi_set_features)
4196 chip->onfi_set_features = nand_onfi_set_features;
4197 if (!chip->onfi_get_features)
4198 chip->onfi_get_features = nand_onfi_get_features;
4199
61b03bd7 4200 /*
8b6e50c9 4201 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
7aa65bfd 4202 * selected and we have 256 byte pagesize fallback to software ECC
e0c7d767 4203 */
956e944c 4204
ace4dfee 4205 switch (chip->ecc.mode) {
6e0cb135
SN		 4206 case NAND_ECC_HW_OOB_FIRST:
4207 /* Similar to NAND_ECC_HW, but a separate read_page handle */
4208 if (!chip->ecc.calculate || !chip->ecc.correct ||
4209 !chip->ecc.hwctl) {
9a4d4d69 4210 pr_warn("No ECC functions supplied; "
d0370219 4211 "hardware ECC not possible\n");
6e0cb135
SN		 4212 BUG();
4213 }
4214 if (!chip->ecc.read_page)
4215 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
4216
6dfc6d25 4217 case NAND_ECC_HW:
8b6e50c9 4218 /* Use standard hwecc read page function? */
f5bbdacc
TG		 4219 if (!chip->ecc.read_page)
4220 chip->ecc.read_page = nand_read_page_hwecc;
f75e5097
TG		 4221 if (!chip->ecc.write_page)
4222 chip->ecc.write_page = nand_write_page_hwecc;
52ff49df
DB		 4223 if (!chip->ecc.read_page_raw)
4224 chip->ecc.read_page_raw = nand_read_page_raw;
4225 if (!chip->ecc.write_page_raw)
4226 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 4227 if (!chip->ecc.read_oob)
4228 chip->ecc.read_oob = nand_read_oob_std;
4229 if (!chip->ecc.write_oob)
4230 chip->ecc.write_oob = nand_write_oob_std;
837a6ba4
GP		 4231 if (!chip->ecc.read_subpage)
4232 chip->ecc.read_subpage = nand_read_subpage;
4233 if (!chip->ecc.write_subpage)
4234 chip->ecc.write_subpage = nand_write_subpage_hwecc;
f5bbdacc 4235
6dfc6d25 4236 case NAND_ECC_HW_SYNDROME:
78b65179
SW		 4237 if ((!chip->ecc.calculate || !chip->ecc.correct ||
4238 !chip->ecc.hwctl) &&
4239 (!chip->ecc.read_page ||
1c45f604 4240 chip->ecc.read_page == nand_read_page_hwecc ||
78b65179 4241 !chip->ecc.write_page ||
1c45f604 4242 chip->ecc.write_page == nand_write_page_hwecc)) {
9a4d4d69 4243 pr_warn("No ECC functions supplied; "
d0370219 4244 "hardware ECC not possible\n");
6dfc6d25
TG		 4245 BUG();
4246 }
8b6e50c9 4247 /* Use standard syndrome read/write page function? */
f5bbdacc
TG		 4248 if (!chip->ecc.read_page)
4249 chip->ecc.read_page = nand_read_page_syndrome;
f75e5097
TG		 4250 if (!chip->ecc.write_page)
4251 chip->ecc.write_page = nand_write_page_syndrome;
52ff49df
DB		 4252 if (!chip->ecc.read_page_raw)
4253 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
4254 if (!chip->ecc.write_page_raw)
4255 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
7bc3312b
TG		 4256 if (!chip->ecc.read_oob)
4257 chip->ecc.read_oob = nand_read_oob_syndrome;
4258 if (!chip->ecc.write_oob)
4259 chip->ecc.write_oob = nand_write_oob_syndrome;
f5bbdacc 4260
e2788c98
MD		 4261 if (mtd->writesize >= chip->ecc.size) {
4262 if (!chip->ecc.strength) {
4263 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
6fa3eb70 4264 //BUG();//bu qq
e2788c98 4265 }
6dfc6d25 4266 break;
e2788c98 4267 }
9a4d4d69 4268 pr_warn("%d byte HW ECC not possible on "
d0370219
BN		 4269 "%d byte page size, fallback to SW ECC\n",
4270 chip->ecc.size, mtd->writesize);
ace4dfee 4271 chip->ecc.mode = NAND_ECC_SOFT;
61b03bd7 4272
6dfc6d25 4273 case NAND_ECC_SOFT:
ace4dfee
TG		 4274 chip->ecc.calculate = nand_calculate_ecc;
4275 chip->ecc.correct = nand_correct_data;
f5bbdacc 4276 chip->ecc.read_page = nand_read_page_swecc;
3d459559 4277 chip->ecc.read_subpage = nand_read_subpage;
f75e5097 4278 chip->ecc.write_page = nand_write_page_swecc;
52ff49df
DB		 4279 chip->ecc.read_page_raw = nand_read_page_raw;
4280 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 4281 chip->ecc.read_oob = nand_read_oob_std;
4282 chip->ecc.write_oob = nand_write_oob_std;
9a73290d
SV		 4283 if (!chip->ecc.size)
4284 chip->ecc.size = 256;
ace4dfee 4285 chip->ecc.bytes = 3;
6a918bad 4286 chip->ecc.strength = 1;
1da177e4 4287 break;
61b03bd7 4288
193bd400
ID		 4289 case NAND_ECC_SOFT_BCH:
4290 if (!mtd_nand_has_bch()) {
9a4d4d69 4291 pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
193bd400
ID		 4292 BUG();
4293 }
4294 chip->ecc.calculate = nand_bch_calculate_ecc;
4295 chip->ecc.correct = nand_bch_correct_data;
4296 chip->ecc.read_page = nand_read_page_swecc;
4297 chip->ecc.read_subpage = nand_read_subpage;
4298 chip->ecc.write_page = nand_write_page_swecc;
4299 chip->ecc.read_page_raw = nand_read_page_raw;
4300 chip->ecc.write_page_raw = nand_write_page_raw;
4301 chip->ecc.read_oob = nand_read_oob_std;
4302 chip->ecc.write_oob = nand_write_oob_std;
4303 /*
4304 * Board driver should supply ecc.size and ecc.bytes values to
4305 * select how many bits are correctable; see nand_bch_init()
8b6e50c9
BN		 4306 * for details. Otherwise, default to 4 bits for large page
4307 * devices.
193bd400
ID		 4308 */
4309 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
4310 chip->ecc.size = 512;
4311 chip->ecc.bytes = 7;
4312 }
4313 chip->ecc.priv = nand_bch_init(mtd,
4314 chip->ecc.size,
4315 chip->ecc.bytes,
4316 &chip->ecc.layout);
4317 if (!chip->ecc.priv) {
9a4d4d69 4318 pr_warn("BCH ECC initialization failed!\n");
193bd400
ID		 4319 BUG();
4320 }
6a918bad 4321 chip->ecc.strength =
e2788c98 4322 chip->ecc.bytes * 8 / fls(8 * chip->ecc.size);
193bd400
ID		 4323 break;
4324
61b03bd7 4325 case NAND_ECC_NONE:
9a4d4d69 4326 pr_warn("NAND_ECC_NONE selected by board driver. "
d0370219 4327 "This is not recommended!\n");
8593fbc6
TG		 4328 chip->ecc.read_page = nand_read_page_raw;
4329 chip->ecc.write_page = nand_write_page_raw;
7bc3312b 4330 chip->ecc.read_oob = nand_read_oob_std;
52ff49df
DB		 4331 chip->ecc.read_page_raw = nand_read_page_raw;
4332 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b 4333 chip->ecc.write_oob = nand_write_oob_std;
ace4dfee
TG		 4334 chip->ecc.size = mtd->writesize;
4335 chip->ecc.bytes = 0;
6a918bad 4336 chip->ecc.strength = 0;
1da177e4 4337 break;
956e944c 4338
1da177e4 4339 default:
d0370219 4340 pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode);
61b03bd7 4341 BUG();
1da177e4 4342 }
61b03bd7 4343
9ce244b3 4344 /* For many systems, the standard OOB write also works for raw */
c46f6483
BN		 4345 if (!chip->ecc.read_oob_raw)
4346 chip->ecc.read_oob_raw = chip->ecc.read_oob;
9ce244b3
BN		 4347 if (!chip->ecc.write_oob_raw)
4348 chip->ecc.write_oob_raw = chip->ecc.write_oob;
4349
5bd34c09
TG		 4350 /*
4351 * The number of bytes available for a client to place data into
8b6e50c9 4352 * the out of band area.
5bd34c09
TG		 4353 */
4354 chip->ecc.layout->oobavail = 0;
81d19b04
DB		 4355 for (i = 0; chip->ecc.layout->oobfree[i].length
4356 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
5bd34c09
TG		 4357 chip->ecc.layout->oobavail +=
4358 chip->ecc.layout->oobfree[i].length;
1f92267c 4359 mtd->oobavail = chip->ecc.layout->oobavail;
5bd34c09 4360
7aa65bfd
TG		 4361 /*
4362 * Set the number of read / write steps for one page depending on ECC
8b6e50c9 4363 * mode.
7aa65bfd 4364 */
ace4dfee 4365 chip->ecc.steps = mtd->writesize / chip->ecc.size;
f8ac0414 4366 if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
9a4d4d69 4367 pr_warn("Invalid ECC parameters\n");
6dfc6d25 4368 BUG();
1da177e4 4369 }
f5bbdacc 4370 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
61b03bd7 4371
8b6e50c9 4372 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
29072b96
TG		 4373 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
4374 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
f8ac0414 4375 switch (chip->ecc.steps) {
29072b96
TG		 4376 case 2:
4377 mtd->subpage_sft = 1;
4378 break;
4379 case 4:
4380 case 8:
81ec5364 4381 case 16:
29072b96
TG		 4382 mtd->subpage_sft = 2;
4383 break;
4384 }
4385 }
4386 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
4387
04bbd0ea 4388 /* Initialize state */
ace4dfee 4389 chip->state = FL_READY;
1da177e4 4390
1da177e4 4391 /* Invalidate the pagebuffer reference */
ace4dfee 4392 chip->pagebuf = -1;
1da177e4 4393
a5ff4f10
JW		 4394 /* Large page NAND with SOFT_ECC should support subpage reads */
4395 if ((chip->ecc.mode == NAND_ECC_SOFT) && (chip->page_shift > 9))
4396 chip->options |= NAND_SUBPAGE_READ;
4397
1da177e4
LT		 4398 /* Fill in remaining MTD driver data */
4399 mtd->type = MTD_NANDFLASH;
93edbad6
ML		 4400 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
4401 MTD_CAP_NANDFLASH;
3c3c10bb
AB		 4402 mtd->_erase = nand_erase;
4403 mtd->_point = NULL;
4404 mtd->_unpoint = NULL;
4405 mtd->_read = nand_read;
4406 mtd->_write = nand_write;
4407 mtd->_panic_write = panic_nand_write;
4408 mtd->_read_oob = nand_read_oob;
4409 mtd->_write_oob = nand_write_oob;
4410 mtd->_sync = nand_sync;
4411 mtd->_lock = NULL;
4412 mtd->_unlock = NULL;
4413 mtd->_suspend = nand_suspend;
4414 mtd->_resume = nand_resume;
4415 mtd->_block_isbad = nand_block_isbad;
4416 mtd->_block_markbad = nand_block_markbad;
cbcab65a 4417 mtd->writebufsize = mtd->writesize;
1da177e4 4418
6a918bad 4419 /* propagate ecc info to mtd_info */
5bd34c09 4420 mtd->ecclayout = chip->ecc.layout;
86c2072b 4421 mtd->ecc_strength = chip->ecc.strength;
ea3b2ea2
SL		 4422 /*
4423 * Initialize bitflip_threshold to its default prior scan_bbt() call.
4424 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4425 * properly set.
4426 */
4427 if (!mtd->bitflip_threshold)
4428 mtd->bitflip_threshold = mtd->ecc_strength;
1da177e4 4429
0040bf38 4430 /* Check, if we should skip the bad block table scan */
ace4dfee 4431 if (chip->options & NAND_SKIP_BBTSCAN)
0040bf38 4432 return 0;
1da177e4
LT		 4433
4434 /* Build bad block table */
ace4dfee 4435 return chip->scan_bbt(mtd);
1da177e4 4436}
7351d3a5 4437EXPORT_SYMBOL(nand_scan_tail);
1da177e4 4438
8b6e50c9
BN		 4439/*
4440 * is_module_text_address() isn't exported, and it's mostly a pointless
7351d3a5 4441 * test if this is a module _anyway_ -- they'd have to try _really_ hard
8b6e50c9
BN		 4442 * to call us from in-kernel code if the core NAND support is modular.
4443 */
3b85c321
DW		 4444#ifdef MODULE
4445#define caller_is_module() (1)
4446#else
4447#define caller_is_module() \
a6e6abd5 4448 is_module_text_address((unsigned long)__builtin_return_address(0))
3b85c321
DW		 4449#endif
4450
4451/**
4452 * nand_scan - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 4453 * @mtd: MTD device structure
4454 * @maxchips: number of chips to scan for
3b85c321 4455 *
8b6e50c9
BN		 4456 * This fills out all the uninitialized function pointers with the defaults.
4457 * The flash ID is read and the mtd/chip structures are filled with the
4458 * appropriate values. The mtd->owner field must be set to the module of the
4459 * caller.
3b85c321
DW		 4460 */
4461int nand_scan(struct mtd_info *mtd, int maxchips)
4462{
4463 int ret;
4464
4465 /* Many callers got this wrong, so check for it for a while... */
4466 if (!mtd->owner && caller_is_module()) {
d0370219 4467 pr_crit("%s called with NULL mtd->owner!\n", __func__);
3b85c321
DW		 4468 BUG();
4469 }
4470
5e81e88a 4471 ret = nand_scan_ident(mtd, maxchips, NULL);
6fa3eb70
S		 4472 #ifdef CONFIG_MTK_MTD_NAND
4473 mtk_nss_init_cache(mtd); // init CacheV (if CacheV is disabled by driver, do nothing inside)
4474 #endif
3b85c321
DW		 4475 if (!ret)
4476 ret = nand_scan_tail(mtd);
4477 return ret;
4478}
7351d3a5 4479EXPORT_SYMBOL(nand_scan);
3b85c321 4480
1da177e4 4481/**
61b03bd7 4482 * nand_release - [NAND Interface] Free resources held by the NAND device
8b6e50c9
BN		 4483 * @mtd: MTD device structure
4484 */
e0c7d767 4485void nand_release(struct mtd_info *mtd)
1da177e4 4486{
ace4dfee 4487 struct nand_chip *chip = mtd->priv;
1da177e4 4488
193bd400
ID		 4489 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
4490 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
4491
5ffcaf3d 4492 mtd_device_unregister(mtd);
1da177e4 4493
fa671646 4494 /* Free bad block table memory */
ace4dfee 4495 kfree(chip->bbt);
4bf63fcb
DW		 4496 if (!(chip->options & NAND_OWN_BUFFERS))
4497 kfree(chip->buffers);
58373ff0
BN		 4498
4499 /* Free bad block descriptor memory */
4500 if (chip->badblock_pattern && chip->badblock_pattern->options
4501 & NAND_BBT_DYNAMICSTRUCT)
4502 kfree(chip->badblock_pattern);
1da177e4 4503}
e0c7d767 4504EXPORT_SYMBOL_GPL(nand_release);
8fe833c1
RP		 4505
4506static int __init nand_base_init(void)
4507{
4508 led_trigger_register_simple("nand-disk", &nand_led_trigger);
4509 return 0;
4510}
4511
4512static void __exit nand_base_exit(void)
4513{
4514 led_trigger_unregister_simple(nand_led_trigger);
4515}
4516
4517module_init(nand_base_init);
4518module_exit(nand_base_exit);
4519
e0c7d767 4520MODULE_LICENSE("GPL");
7351d3a5
FF		 4521MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4522MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
e0c7d767 4523MODULE_DESCRIPTION("Generic NAND flash driver code");
kernel source for telekom puls (alcatel/mediatek)