Commit | Line | Data |
---|---|---|
42cb1403 | 1 | /* |
42cb1403 AV |
2 | * Copyright (C) 2003 Rick Bronson |
3 | * | |
4 | * Derived from drivers/mtd/nand/autcpu12.c | |
5 | * Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de) | |
6 | * | |
7 | * Derived from drivers/mtd/spia.c | |
8 | * Copyright (C) 2000 Steven J. Hill (sjhill@cotw.com) | |
9 | * | |
77f5492c RG |
10 | * |
11 | * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263 | |
12 | * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright (C) 2007 | |
13 | * | |
14 | * Derived from Das U-Boot source code | |
15 | * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c) | |
16 | * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas | |
17 | * | |
18 | * | |
42cb1403 AV |
19 | * This program is free software; you can redistribute it and/or modify |
20 | * it under the terms of the GNU General Public License version 2 as | |
21 | * published by the Free Software Foundation. | |
22 | * | |
23 | */ | |
24 | ||
b7f080cf | 25 | #include <linux/dma-mapping.h> |
42cb1403 AV |
26 | #include <linux/slab.h> |
27 | #include <linux/module.h> | |
f4fa697c | 28 | #include <linux/moduleparam.h> |
42cb1403 AV |
29 | #include <linux/platform_device.h> |
30 | #include <linux/mtd/mtd.h> | |
31 | #include <linux/mtd/nand.h> | |
32 | #include <linux/mtd/partitions.h> | |
33 | ||
5c39c4c5 | 34 | #include <linux/dmaengine.h> |
90574d0a DW |
35 | #include <linux/gpio.h> |
36 | #include <linux/io.h> | |
42cb1403 | 37 | |
a09e64fb RK |
38 | #include <mach/board.h> |
39 | #include <mach/cpu.h> | |
42cb1403 | 40 | |
d4f4c0aa | 41 | #ifdef CONFIG_MTD_NAND_ATMEL_ECC_HW |
77f5492c RG |
42 | #define hard_ecc 1 |
43 | #else | |
44 | #define hard_ecc 0 | |
45 | #endif | |
46 | ||
d4f4c0aa | 47 | #ifdef CONFIG_MTD_NAND_ATMEL_ECC_NONE |
77f5492c RG |
48 | #define no_ecc 1 |
49 | #else | |
50 | #define no_ecc 0 | |
51 | #endif | |
52 | ||
cbc6c5e7 HX |
53 | static int use_dma = 1; |
54 | module_param(use_dma, int, 0); | |
55 | ||
f4fa697c SP |
56 | static int on_flash_bbt = 0; |
57 | module_param(on_flash_bbt, int, 0); | |
58 | ||
77f5492c RG |
59 | /* Register access macros */ |
60 | #define ecc_readl(add, reg) \ | |
3c3796cc | 61 | __raw_readl(add + ATMEL_ECC_##reg) |
77f5492c | 62 | #define ecc_writel(add, reg, value) \ |
3c3796cc | 63 | __raw_writel((value), add + ATMEL_ECC_##reg) |
77f5492c | 64 | |
d4f4c0aa | 65 | #include "atmel_nand_ecc.h" /* Hardware ECC registers */ |
77f5492c RG |
66 | |
67 | /* oob layout for large page size | |
68 | * bad block info is on bytes 0 and 1 | |
69 | * the bytes have to be consecutives to avoid | |
70 | * several NAND_CMD_RNDOUT during read | |
71 | */ | |
3c3796cc | 72 | static struct nand_ecclayout atmel_oobinfo_large = { |
77f5492c RG |
73 | .eccbytes = 4, |
74 | .eccpos = {60, 61, 62, 63}, | |
75 | .oobfree = { | |
76 | {2, 58} | |
77 | }, | |
78 | }; | |
79 | ||
80 | /* oob layout for small page size | |
81 | * bad block info is on bytes 4 and 5 | |
82 | * the bytes have to be consecutives to avoid | |
83 | * several NAND_CMD_RNDOUT during read | |
84 | */ | |
3c3796cc | 85 | static struct nand_ecclayout atmel_oobinfo_small = { |
77f5492c RG |
86 | .eccbytes = 4, |
87 | .eccpos = {0, 1, 2, 3}, | |
88 | .oobfree = { | |
89 | {6, 10} | |
90 | }, | |
91 | }; | |
92 | ||
3c3796cc | 93 | struct atmel_nand_host { |
42cb1403 AV |
94 | struct nand_chip nand_chip; |
95 | struct mtd_info mtd; | |
96 | void __iomem *io_base; | |
cbc6c5e7 | 97 | dma_addr_t io_phys; |
3c3796cc | 98 | struct atmel_nand_data *board; |
77f5492c RG |
99 | struct device *dev; |
100 | void __iomem *ecc; | |
cbc6c5e7 HX |
101 | |
102 | struct completion comp; | |
103 | struct dma_chan *dma_chan; | |
42cb1403 AV |
104 | }; |
105 | ||
cbc6c5e7 HX |
106 | static int cpu_has_dma(void) |
107 | { | |
108 | return cpu_is_at91sam9rl() || cpu_is_at91sam9g45(); | |
109 | } | |
110 | ||
8136508c AN |
111 | /* |
112 | * Enable NAND. | |
113 | */ | |
3c3796cc | 114 | static void atmel_nand_enable(struct atmel_nand_host *host) |
8136508c | 115 | { |
1d6dc068 | 116 | if (gpio_is_valid(host->board->enable_pin)) |
62fd71fe | 117 | gpio_set_value(host->board->enable_pin, 0); |
8136508c AN |
118 | } |
119 | ||
120 | /* | |
121 | * Disable NAND. | |
122 | */ | |
3c3796cc | 123 | static void atmel_nand_disable(struct atmel_nand_host *host) |
8136508c | 124 | { |
1d6dc068 | 125 | if (gpio_is_valid(host->board->enable_pin)) |
62fd71fe | 126 | gpio_set_value(host->board->enable_pin, 1); |
8136508c AN |
127 | } |
128 | ||
42cb1403 AV |
129 | /* |
130 | * Hardware specific access to control-lines | |
131 | */ | |
3c3796cc | 132 | static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
42cb1403 AV |
133 | { |
134 | struct nand_chip *nand_chip = mtd->priv; | |
3c3796cc | 135 | struct atmel_nand_host *host = nand_chip->priv; |
42cb1403 | 136 | |
8136508c | 137 | if (ctrl & NAND_CTRL_CHANGE) { |
2314488e | 138 | if (ctrl & NAND_NCE) |
3c3796cc | 139 | atmel_nand_enable(host); |
2314488e | 140 | else |
3c3796cc | 141 | atmel_nand_disable(host); |
2314488e | 142 | } |
42cb1403 AV |
143 | if (cmd == NAND_CMD_NONE) |
144 | return; | |
145 | ||
146 | if (ctrl & NAND_CLE) | |
147 | writeb(cmd, host->io_base + (1 << host->board->cle)); | |
148 | else | |
149 | writeb(cmd, host->io_base + (1 << host->board->ale)); | |
150 | } | |
151 | ||
152 | /* | |
153 | * Read the Device Ready pin. | |
154 | */ | |
3c3796cc | 155 | static int atmel_nand_device_ready(struct mtd_info *mtd) |
42cb1403 AV |
156 | { |
157 | struct nand_chip *nand_chip = mtd->priv; | |
3c3796cc | 158 | struct atmel_nand_host *host = nand_chip->priv; |
42cb1403 | 159 | |
744f6592 GC |
160 | return gpio_get_value(host->board->rdy_pin) ^ |
161 | !!host->board->rdy_pin_active_low; | |
42cb1403 AV |
162 | } |
163 | ||
cbc6c5e7 HX |
164 | static void dma_complete_func(void *completion) |
165 | { | |
166 | complete(completion); | |
167 | } | |
168 | ||
169 | static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len, | |
170 | int is_read) | |
171 | { | |
172 | struct dma_device *dma_dev; | |
173 | enum dma_ctrl_flags flags; | |
174 | dma_addr_t dma_src_addr, dma_dst_addr, phys_addr; | |
175 | struct dma_async_tx_descriptor *tx = NULL; | |
176 | dma_cookie_t cookie; | |
177 | struct nand_chip *chip = mtd->priv; | |
178 | struct atmel_nand_host *host = chip->priv; | |
179 | void *p = buf; | |
180 | int err = -EIO; | |
181 | enum dma_data_direction dir = is_read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; | |
182 | ||
80b4f81a HX |
183 | if (buf >= high_memory) |
184 | goto err_buf; | |
cbc6c5e7 HX |
185 | |
186 | dma_dev = host->dma_chan->device; | |
187 | ||
188 | flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_SRC_UNMAP | | |
189 | DMA_COMPL_SKIP_DEST_UNMAP; | |
190 | ||
191 | phys_addr = dma_map_single(dma_dev->dev, p, len, dir); | |
192 | if (dma_mapping_error(dma_dev->dev, phys_addr)) { | |
193 | dev_err(host->dev, "Failed to dma_map_single\n"); | |
194 | goto err_buf; | |
195 | } | |
196 | ||
197 | if (is_read) { | |
198 | dma_src_addr = host->io_phys; | |
199 | dma_dst_addr = phys_addr; | |
200 | } else { | |
201 | dma_src_addr = phys_addr; | |
202 | dma_dst_addr = host->io_phys; | |
203 | } | |
204 | ||
205 | tx = dma_dev->device_prep_dma_memcpy(host->dma_chan, dma_dst_addr, | |
206 | dma_src_addr, len, flags); | |
207 | if (!tx) { | |
208 | dev_err(host->dev, "Failed to prepare DMA memcpy\n"); | |
209 | goto err_dma; | |
210 | } | |
211 | ||
212 | init_completion(&host->comp); | |
213 | tx->callback = dma_complete_func; | |
214 | tx->callback_param = &host->comp; | |
215 | ||
216 | cookie = tx->tx_submit(tx); | |
217 | if (dma_submit_error(cookie)) { | |
218 | dev_err(host->dev, "Failed to do DMA tx_submit\n"); | |
219 | goto err_dma; | |
220 | } | |
221 | ||
222 | dma_async_issue_pending(host->dma_chan); | |
223 | wait_for_completion(&host->comp); | |
224 | ||
225 | err = 0; | |
226 | ||
227 | err_dma: | |
228 | dma_unmap_single(dma_dev->dev, phys_addr, len, dir); | |
229 | err_buf: | |
230 | if (err != 0) | |
231 | dev_warn(host->dev, "Fall back to CPU I/O\n"); | |
232 | return err; | |
233 | } | |
234 | ||
235 | static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len) | |
236 | { | |
237 | struct nand_chip *chip = mtd->priv; | |
cbc6c5e7 | 238 | |
9d51567e NF |
239 | if (use_dma && len > mtd->oobsize) |
240 | /* only use DMA for bigger than oob size: better performances */ | |
cbc6c5e7 HX |
241 | if (atmel_nand_dma_op(mtd, buf, len, 1) == 0) |
242 | return; | |
243 | ||
fb542750 NF |
244 | /* if no DMA operation possible, use PIO */ |
245 | memcpy_fromio(buf, chip->IO_ADDR_R, len); | |
cbc6c5e7 HX |
246 | } |
247 | ||
248 | static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len) | |
249 | { | |
250 | struct nand_chip *chip = mtd->priv; | |
cbc6c5e7 | 251 | |
9d51567e NF |
252 | if (use_dma && len > mtd->oobsize) |
253 | /* only use DMA for bigger than oob size: better performances */ | |
cbc6c5e7 HX |
254 | if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) == 0) |
255 | return; | |
256 | ||
fb542750 NF |
257 | /* if no DMA operation possible, use PIO */ |
258 | memcpy_toio(chip->IO_ADDR_W, buf, len); | |
cbc6c5e7 HX |
259 | } |
260 | ||
77f5492c RG |
261 | /* |
262 | * Calculate HW ECC | |
263 | * | |
264 | * function called after a write | |
265 | * | |
266 | * mtd: MTD block structure | |
267 | * dat: raw data (unused) | |
268 | * ecc_code: buffer for ECC | |
269 | */ | |
3c3796cc | 270 | static int atmel_nand_calculate(struct mtd_info *mtd, |
77f5492c RG |
271 | const u_char *dat, unsigned char *ecc_code) |
272 | { | |
273 | struct nand_chip *nand_chip = mtd->priv; | |
3c3796cc | 274 | struct atmel_nand_host *host = nand_chip->priv; |
77f5492c RG |
275 | unsigned int ecc_value; |
276 | ||
277 | /* get the first 2 ECC bytes */ | |
d43fa149 | 278 | ecc_value = ecc_readl(host->ecc, PR); |
77f5492c | 279 | |
3fc23898 RG |
280 | ecc_code[0] = ecc_value & 0xFF; |
281 | ecc_code[1] = (ecc_value >> 8) & 0xFF; | |
77f5492c RG |
282 | |
283 | /* get the last 2 ECC bytes */ | |
3c3796cc | 284 | ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY; |
77f5492c | 285 | |
3fc23898 RG |
286 | ecc_code[2] = ecc_value & 0xFF; |
287 | ecc_code[3] = (ecc_value >> 8) & 0xFF; | |
77f5492c RG |
288 | |
289 | return 0; | |
290 | } | |
291 | ||
292 | /* | |
293 | * HW ECC read page function | |
294 | * | |
295 | * mtd: mtd info structure | |
296 | * chip: nand chip info structure | |
297 | * buf: buffer to store read data | |
298 | */ | |
3c3796cc | 299 | static int atmel_nand_read_page(struct mtd_info *mtd, |
46a8cf2d | 300 | struct nand_chip *chip, uint8_t *buf, int page) |
77f5492c RG |
301 | { |
302 | int eccsize = chip->ecc.size; | |
303 | int eccbytes = chip->ecc.bytes; | |
304 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
305 | uint8_t *p = buf; | |
306 | uint8_t *oob = chip->oob_poi; | |
307 | uint8_t *ecc_pos; | |
308 | int stat; | |
309 | ||
d6248fdd HS |
310 | /* |
311 | * Errata: ALE is incorrectly wired up to the ECC controller | |
312 | * on the AP7000, so it will include the address cycles in the | |
313 | * ECC calculation. | |
314 | * | |
315 | * Workaround: Reset the parity registers before reading the | |
316 | * actual data. | |
317 | */ | |
318 | if (cpu_is_at32ap7000()) { | |
319 | struct atmel_nand_host *host = chip->priv; | |
320 | ecc_writel(host->ecc, CR, ATMEL_ECC_RST); | |
321 | } | |
322 | ||
77f5492c RG |
323 | /* read the page */ |
324 | chip->read_buf(mtd, p, eccsize); | |
325 | ||
326 | /* move to ECC position if needed */ | |
327 | if (eccpos[0] != 0) { | |
328 | /* This only works on large pages | |
329 | * because the ECC controller waits for | |
330 | * NAND_CMD_RNDOUTSTART after the | |
331 | * NAND_CMD_RNDOUT. | |
332 | * anyway, for small pages, the eccpos[0] == 0 | |
333 | */ | |
334 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, | |
335 | mtd->writesize + eccpos[0], -1); | |
336 | } | |
337 | ||
338 | /* the ECC controller needs to read the ECC just after the data */ | |
339 | ecc_pos = oob + eccpos[0]; | |
340 | chip->read_buf(mtd, ecc_pos, eccbytes); | |
341 | ||
342 | /* check if there's an error */ | |
343 | stat = chip->ecc.correct(mtd, p, oob, NULL); | |
344 | ||
345 | if (stat < 0) | |
346 | mtd->ecc_stats.failed++; | |
347 | else | |
348 | mtd->ecc_stats.corrected += stat; | |
349 | ||
350 | /* get back to oob start (end of page) */ | |
351 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1); | |
352 | ||
353 | /* read the oob */ | |
354 | chip->read_buf(mtd, oob, mtd->oobsize); | |
355 | ||
356 | return 0; | |
357 | } | |
358 | ||
359 | /* | |
360 | * HW ECC Correction | |
361 | * | |
362 | * function called after a read | |
363 | * | |
364 | * mtd: MTD block structure | |
365 | * dat: raw data read from the chip | |
366 | * read_ecc: ECC from the chip (unused) | |
367 | * isnull: unused | |
368 | * | |
369 | * Detect and correct a 1 bit error for a page | |
370 | */ | |
3c3796cc | 371 | static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat, |
77f5492c RG |
372 | u_char *read_ecc, u_char *isnull) |
373 | { | |
374 | struct nand_chip *nand_chip = mtd->priv; | |
3c3796cc | 375 | struct atmel_nand_host *host = nand_chip->priv; |
77f5492c RG |
376 | unsigned int ecc_status; |
377 | unsigned int ecc_word, ecc_bit; | |
378 | ||
379 | /* get the status from the Status Register */ | |
380 | ecc_status = ecc_readl(host->ecc, SR); | |
381 | ||
382 | /* if there's no error */ | |
3c3796cc | 383 | if (likely(!(ecc_status & ATMEL_ECC_RECERR))) |
77f5492c RG |
384 | return 0; |
385 | ||
386 | /* get error bit offset (4 bits) */ | |
3c3796cc | 387 | ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR; |
77f5492c | 388 | /* get word address (12 bits) */ |
3c3796cc | 389 | ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR; |
77f5492c RG |
390 | ecc_word >>= 4; |
391 | ||
392 | /* if there are multiple errors */ | |
3c3796cc | 393 | if (ecc_status & ATMEL_ECC_MULERR) { |
77f5492c RG |
394 | /* check if it is a freshly erased block |
395 | * (filled with 0xff) */ | |
3c3796cc HS |
396 | if ((ecc_bit == ATMEL_ECC_BITADDR) |
397 | && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) { | |
77f5492c RG |
398 | /* the block has just been erased, return OK */ |
399 | return 0; | |
400 | } | |
401 | /* it doesn't seems to be a freshly | |
402 | * erased block. | |
403 | * We can't correct so many errors */ | |
3c3796cc | 404 | dev_dbg(host->dev, "atmel_nand : multiple errors detected." |
77f5492c RG |
405 | " Unable to correct.\n"); |
406 | return -EIO; | |
407 | } | |
408 | ||
409 | /* if there's a single bit error : we can correct it */ | |
3c3796cc | 410 | if (ecc_status & ATMEL_ECC_ECCERR) { |
77f5492c RG |
411 | /* there's nothing much to do here. |
412 | * the bit error is on the ECC itself. | |
413 | */ | |
3c3796cc | 414 | dev_dbg(host->dev, "atmel_nand : one bit error on ECC code." |
77f5492c RG |
415 | " Nothing to correct\n"); |
416 | return 0; | |
417 | } | |
418 | ||
3c3796cc | 419 | dev_dbg(host->dev, "atmel_nand : one bit error on data." |
77f5492c RG |
420 | " (word offset in the page :" |
421 | " 0x%x bit offset : 0x%x)\n", | |
422 | ecc_word, ecc_bit); | |
423 | /* correct the error */ | |
424 | if (nand_chip->options & NAND_BUSWIDTH_16) { | |
425 | /* 16 bits words */ | |
426 | ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit); | |
427 | } else { | |
428 | /* 8 bits words */ | |
429 | dat[ecc_word] ^= (1 << ecc_bit); | |
430 | } | |
3c3796cc | 431 | dev_dbg(host->dev, "atmel_nand : error corrected\n"); |
77f5492c RG |
432 | return 1; |
433 | } | |
434 | ||
435 | /* | |
d6248fdd | 436 | * Enable HW ECC : unused on most chips |
77f5492c | 437 | */ |
d6248fdd HS |
438 | static void atmel_nand_hwctl(struct mtd_info *mtd, int mode) |
439 | { | |
440 | if (cpu_is_at32ap7000()) { | |
441 | struct nand_chip *nand_chip = mtd->priv; | |
442 | struct atmel_nand_host *host = nand_chip->priv; | |
443 | ecc_writel(host->ecc, CR, ATMEL_ECC_RST); | |
444 | } | |
445 | } | |
77f5492c | 446 | |
42cb1403 AV |
447 | /* |
448 | * Probe for the NAND device. | |
449 | */ | |
3c3796cc | 450 | static int __init atmel_nand_probe(struct platform_device *pdev) |
42cb1403 | 451 | { |
3c3796cc | 452 | struct atmel_nand_host *host; |
42cb1403 AV |
453 | struct mtd_info *mtd; |
454 | struct nand_chip *nand_chip; | |
77f5492c RG |
455 | struct resource *regs; |
456 | struct resource *mem; | |
42cb1403 | 457 | int res; |
42cb1403 | 458 | |
cc0c72e1 HS |
459 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
460 | if (!mem) { | |
461 | printk(KERN_ERR "atmel_nand: can't get I/O resource mem\n"); | |
462 | return -ENXIO; | |
463 | } | |
464 | ||
42cb1403 | 465 | /* Allocate memory for the device structure (and zero it) */ |
3c3796cc | 466 | host = kzalloc(sizeof(struct atmel_nand_host), GFP_KERNEL); |
42cb1403 | 467 | if (!host) { |
3c3796cc | 468 | printk(KERN_ERR "atmel_nand: failed to allocate device structure.\n"); |
42cb1403 AV |
469 | return -ENOMEM; |
470 | } | |
471 | ||
cbc6c5e7 HX |
472 | host->io_phys = (dma_addr_t)mem->start; |
473 | ||
28f65c11 | 474 | host->io_base = ioremap(mem->start, resource_size(mem)); |
42cb1403 | 475 | if (host->io_base == NULL) { |
3c3796cc | 476 | printk(KERN_ERR "atmel_nand: ioremap failed\n"); |
cc0c72e1 HS |
477 | res = -EIO; |
478 | goto err_nand_ioremap; | |
42cb1403 AV |
479 | } |
480 | ||
481 | mtd = &host->mtd; | |
482 | nand_chip = &host->nand_chip; | |
483 | host->board = pdev->dev.platform_data; | |
77f5492c | 484 | host->dev = &pdev->dev; |
42cb1403 AV |
485 | |
486 | nand_chip->priv = host; /* link the private data structures */ | |
487 | mtd->priv = nand_chip; | |
488 | mtd->owner = THIS_MODULE; | |
489 | ||
490 | /* Set address of NAND IO lines */ | |
491 | nand_chip->IO_ADDR_R = host->io_base; | |
492 | nand_chip->IO_ADDR_W = host->io_base; | |
3c3796cc | 493 | nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl; |
a4265f8d | 494 | |
1d6dc068 | 495 | if (gpio_is_valid(host->board->rdy_pin)) |
3c3796cc | 496 | nand_chip->dev_ready = atmel_nand_device_ready; |
a4265f8d | 497 | |
77f5492c RG |
498 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
499 | if (!regs && hard_ecc) { | |
3c3796cc | 500 | printk(KERN_ERR "atmel_nand: can't get I/O resource " |
77f5492c RG |
501 | "regs\nFalling back on software ECC\n"); |
502 | } | |
503 | ||
42cb1403 | 504 | nand_chip->ecc.mode = NAND_ECC_SOFT; /* enable ECC */ |
77f5492c RG |
505 | if (no_ecc) |
506 | nand_chip->ecc.mode = NAND_ECC_NONE; | |
507 | if (hard_ecc && regs) { | |
28f65c11 | 508 | host->ecc = ioremap(regs->start, resource_size(regs)); |
77f5492c | 509 | if (host->ecc == NULL) { |
3c3796cc | 510 | printk(KERN_ERR "atmel_nand: ioremap failed\n"); |
77f5492c RG |
511 | res = -EIO; |
512 | goto err_ecc_ioremap; | |
513 | } | |
3fc23898 | 514 | nand_chip->ecc.mode = NAND_ECC_HW; |
3c3796cc HS |
515 | nand_chip->ecc.calculate = atmel_nand_calculate; |
516 | nand_chip->ecc.correct = atmel_nand_correct; | |
517 | nand_chip->ecc.hwctl = atmel_nand_hwctl; | |
518 | nand_chip->ecc.read_page = atmel_nand_read_page; | |
77f5492c | 519 | nand_chip->ecc.bytes = 4; |
77f5492c RG |
520 | } |
521 | ||
42cb1403 AV |
522 | nand_chip->chip_delay = 20; /* 20us command delay time */ |
523 | ||
cbc6c5e7 | 524 | if (host->board->bus_width_16) /* 16-bit bus width */ |
dd11b8cd | 525 | nand_chip->options |= NAND_BUSWIDTH_16; |
cbc6c5e7 HX |
526 | |
527 | nand_chip->read_buf = atmel_read_buf; | |
528 | nand_chip->write_buf = atmel_write_buf; | |
dd11b8cd | 529 | |
42cb1403 | 530 | platform_set_drvdata(pdev, host); |
3c3796cc | 531 | atmel_nand_enable(host); |
42cb1403 | 532 | |
1d6dc068 | 533 | if (gpio_is_valid(host->board->det_pin)) { |
62fd71fe | 534 | if (gpio_get_value(host->board->det_pin)) { |
f4fa697c | 535 | printk(KERN_INFO "No SmartMedia card inserted.\n"); |
895fb494 | 536 | res = -ENXIO; |
cc0c72e1 | 537 | goto err_no_card; |
42cb1403 AV |
538 | } |
539 | } | |
540 | ||
f4fa697c SP |
541 | if (on_flash_bbt) { |
542 | printk(KERN_INFO "atmel_nand: Use On Flash BBT\n"); | |
bb9ebd4e | 543 | nand_chip->bbt_options |= NAND_BBT_USE_FLASH; |
f4fa697c SP |
544 | } |
545 | ||
cb457a4d HX |
546 | if (!cpu_has_dma()) |
547 | use_dma = 0; | |
548 | ||
549 | if (use_dma) { | |
cbc6c5e7 HX |
550 | dma_cap_mask_t mask; |
551 | ||
552 | dma_cap_zero(mask); | |
553 | dma_cap_set(DMA_MEMCPY, mask); | |
201ab536 | 554 | host->dma_chan = dma_request_channel(mask, NULL, NULL); |
cbc6c5e7 HX |
555 | if (!host->dma_chan) { |
556 | dev_err(host->dev, "Failed to request DMA channel\n"); | |
557 | use_dma = 0; | |
558 | } | |
559 | } | |
560 | if (use_dma) | |
042bc9c0 NF |
561 | dev_info(host->dev, "Using %s for DMA transfers.\n", |
562 | dma_chan_name(host->dma_chan)); | |
cbc6c5e7 HX |
563 | else |
564 | dev_info(host->dev, "No DMA support for NAND access.\n"); | |
565 | ||
77f5492c | 566 | /* first scan to find the device and get the page size */ |
5e81e88a | 567 | if (nand_scan_ident(mtd, 1, NULL)) { |
77f5492c | 568 | res = -ENXIO; |
cc0c72e1 | 569 | goto err_scan_ident; |
77f5492c RG |
570 | } |
571 | ||
3fc23898 | 572 | if (nand_chip->ecc.mode == NAND_ECC_HW) { |
77f5492c RG |
573 | /* ECC is calculated for the whole page (1 step) */ |
574 | nand_chip->ecc.size = mtd->writesize; | |
575 | ||
576 | /* set ECC page size and oob layout */ | |
577 | switch (mtd->writesize) { | |
578 | case 512: | |
3c3796cc | 579 | nand_chip->ecc.layout = &atmel_oobinfo_small; |
3c3796cc | 580 | ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528); |
77f5492c RG |
581 | break; |
582 | case 1024: | |
3c3796cc HS |
583 | nand_chip->ecc.layout = &atmel_oobinfo_large; |
584 | ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056); | |
77f5492c RG |
585 | break; |
586 | case 2048: | |
3c3796cc HS |
587 | nand_chip->ecc.layout = &atmel_oobinfo_large; |
588 | ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112); | |
77f5492c RG |
589 | break; |
590 | case 4096: | |
3c3796cc HS |
591 | nand_chip->ecc.layout = &atmel_oobinfo_large; |
592 | ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224); | |
77f5492c RG |
593 | break; |
594 | default: | |
595 | /* page size not handled by HW ECC */ | |
596 | /* switching back to soft ECC */ | |
597 | nand_chip->ecc.mode = NAND_ECC_SOFT; | |
598 | nand_chip->ecc.calculate = NULL; | |
599 | nand_chip->ecc.correct = NULL; | |
600 | nand_chip->ecc.hwctl = NULL; | |
601 | nand_chip->ecc.read_page = NULL; | |
602 | nand_chip->ecc.postpad = 0; | |
603 | nand_chip->ecc.prepad = 0; | |
604 | nand_chip->ecc.bytes = 0; | |
605 | break; | |
606 | } | |
607 | } | |
608 | ||
609 | /* second phase scan */ | |
610 | if (nand_scan_tail(mtd)) { | |
42cb1403 | 611 | res = -ENXIO; |
cc0c72e1 | 612 | goto err_scan_tail; |
42cb1403 AV |
613 | } |
614 | ||
3c3796cc | 615 | mtd->name = "atmel_nand"; |
ef5d79f1 DES |
616 | res = mtd_device_parse_register(mtd, NULL, 0, |
617 | host->board->parts, host->board->num_parts); | |
42cb1403 AV |
618 | if (!res) |
619 | return res; | |
620 | ||
cc0c72e1 HS |
621 | err_scan_tail: |
622 | err_scan_ident: | |
623 | err_no_card: | |
3c3796cc | 624 | atmel_nand_disable(host); |
42cb1403 | 625 | platform_set_drvdata(pdev, NULL); |
cbc6c5e7 HX |
626 | if (host->dma_chan) |
627 | dma_release_channel(host->dma_chan); | |
cc0c72e1 HS |
628 | if (host->ecc) |
629 | iounmap(host->ecc); | |
630 | err_ecc_ioremap: | |
42cb1403 | 631 | iounmap(host->io_base); |
cc0c72e1 | 632 | err_nand_ioremap: |
42cb1403 AV |
633 | kfree(host); |
634 | return res; | |
635 | } | |
636 | ||
637 | /* | |
638 | * Remove a NAND device. | |
639 | */ | |
23a346ca | 640 | static int __exit atmel_nand_remove(struct platform_device *pdev) |
42cb1403 | 641 | { |
3c3796cc | 642 | struct atmel_nand_host *host = platform_get_drvdata(pdev); |
42cb1403 AV |
643 | struct mtd_info *mtd = &host->mtd; |
644 | ||
645 | nand_release(mtd); | |
646 | ||
3c3796cc | 647 | atmel_nand_disable(host); |
42cb1403 | 648 | |
cc0c72e1 HS |
649 | if (host->ecc) |
650 | iounmap(host->ecc); | |
cbc6c5e7 HX |
651 | |
652 | if (host->dma_chan) | |
653 | dma_release_channel(host->dma_chan); | |
654 | ||
42cb1403 AV |
655 | iounmap(host->io_base); |
656 | kfree(host); | |
657 | ||
658 | return 0; | |
659 | } | |
660 | ||
3c3796cc | 661 | static struct platform_driver atmel_nand_driver = { |
23a346ca | 662 | .remove = __exit_p(atmel_nand_remove), |
42cb1403 | 663 | .driver = { |
3c3796cc | 664 | .name = "atmel_nand", |
42cb1403 AV |
665 | .owner = THIS_MODULE, |
666 | }, | |
667 | }; | |
668 | ||
3c3796cc | 669 | static int __init atmel_nand_init(void) |
42cb1403 | 670 | { |
23a346ca | 671 | return platform_driver_probe(&atmel_nand_driver, atmel_nand_probe); |
42cb1403 AV |
672 | } |
673 | ||
674 | ||
3c3796cc | 675 | static void __exit atmel_nand_exit(void) |
42cb1403 | 676 | { |
3c3796cc | 677 | platform_driver_unregister(&atmel_nand_driver); |
42cb1403 AV |
678 | } |
679 | ||
680 | ||
3c3796cc HS |
681 | module_init(atmel_nand_init); |
682 | module_exit(atmel_nand_exit); | |
42cb1403 AV |
683 | |
684 | MODULE_LICENSE("GPL"); | |
685 | MODULE_AUTHOR("Rick Bronson"); | |
d4f4c0aa | 686 | MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32"); |
3c3796cc | 687 | MODULE_ALIAS("platform:atmel_nand"); |