Commit | Line | Data |
---|---|---|
d129bceb | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver |
d129bceb | 3 | * |
b69c9058 | 4 | * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. |
d129bceb PO |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
643f720c PO |
7 | * it under the terms of the GNU General Public License as published by |
8 | * the Free Software Foundation; either version 2 of the License, or (at | |
9 | * your option) any later version. | |
84c46a53 PO |
10 | * |
11 | * Thanks to the following companies for their support: | |
12 | * | |
13 | * - JMicron (hardware and technical support) | |
d129bceb PO |
14 | */ |
15 | ||
d129bceb PO |
16 | #include <linux/delay.h> |
17 | #include <linux/highmem.h> | |
b8c86fc5 | 18 | #include <linux/io.h> |
d129bceb | 19 | #include <linux/dma-mapping.h> |
11763609 | 20 | #include <linux/scatterlist.h> |
d129bceb | 21 | |
2f730fec PO |
22 | #include <linux/leds.h> |
23 | ||
d129bceb | 24 | #include <linux/mmc/host.h> |
d129bceb | 25 | |
d129bceb PO |
26 | #include "sdhci.h" |
27 | ||
28 | #define DRIVER_NAME "sdhci" | |
d129bceb | 29 | |
d129bceb | 30 | #define DBG(f, x...) \ |
c6563178 | 31 | pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) |
d129bceb | 32 | |
f9134319 PO |
33 | #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \ |
34 | defined(CONFIG_MMC_SDHCI_MODULE)) | |
35 | #define SDHCI_USE_LEDS_CLASS | |
36 | #endif | |
37 | ||
df673b22 | 38 | static unsigned int debug_quirks = 0; |
67435274 | 39 | |
d129bceb PO |
40 | static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *); |
41 | static void sdhci_finish_data(struct sdhci_host *); | |
42 | ||
43 | static void sdhci_send_command(struct sdhci_host *, struct mmc_command *); | |
44 | static void sdhci_finish_command(struct sdhci_host *); | |
45 | ||
46 | static void sdhci_dumpregs(struct sdhci_host *host) | |
47 | { | |
48 | printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n"); | |
49 | ||
50 | printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", | |
4e4141a5 AV |
51 | sdhci_readl(host, SDHCI_DMA_ADDRESS), |
52 | sdhci_readw(host, SDHCI_HOST_VERSION)); | |
d129bceb | 53 | printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", |
4e4141a5 AV |
54 | sdhci_readw(host, SDHCI_BLOCK_SIZE), |
55 | sdhci_readw(host, SDHCI_BLOCK_COUNT)); | |
d129bceb | 56 | printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", |
4e4141a5 AV |
57 | sdhci_readl(host, SDHCI_ARGUMENT), |
58 | sdhci_readw(host, SDHCI_TRANSFER_MODE)); | |
d129bceb | 59 | printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", |
4e4141a5 AV |
60 | sdhci_readl(host, SDHCI_PRESENT_STATE), |
61 | sdhci_readb(host, SDHCI_HOST_CONTROL)); | |
d129bceb | 62 | printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", |
4e4141a5 AV |
63 | sdhci_readb(host, SDHCI_POWER_CONTROL), |
64 | sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); | |
d129bceb | 65 | printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", |
4e4141a5 AV |
66 | sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), |
67 | sdhci_readw(host, SDHCI_CLOCK_CONTROL)); | |
d129bceb | 68 | printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", |
4e4141a5 AV |
69 | sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), |
70 | sdhci_readl(host, SDHCI_INT_STATUS)); | |
d129bceb | 71 | printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", |
4e4141a5 AV |
72 | sdhci_readl(host, SDHCI_INT_ENABLE), |
73 | sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); | |
d129bceb | 74 | printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", |
4e4141a5 AV |
75 | sdhci_readw(host, SDHCI_ACMD12_ERR), |
76 | sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); | |
d129bceb | 77 | printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n", |
4e4141a5 AV |
78 | sdhci_readl(host, SDHCI_CAPABILITIES), |
79 | sdhci_readl(host, SDHCI_MAX_CURRENT)); | |
d129bceb | 80 | |
be3f4ae0 BD |
81 | if (host->flags & SDHCI_USE_ADMA) |
82 | printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", | |
83 | readl(host->ioaddr + SDHCI_ADMA_ERROR), | |
84 | readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); | |
85 | ||
d129bceb PO |
86 | printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n"); |
87 | } | |
88 | ||
89 | /*****************************************************************************\ | |
90 | * * | |
91 | * Low level functions * | |
92 | * * | |
93 | \*****************************************************************************/ | |
94 | ||
7260cf5e AV |
95 | static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set) |
96 | { | |
97 | u32 ier; | |
98 | ||
99 | ier = sdhci_readl(host, SDHCI_INT_ENABLE); | |
100 | ier &= ~clear; | |
101 | ier |= set; | |
102 | sdhci_writel(host, ier, SDHCI_INT_ENABLE); | |
103 | sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE); | |
104 | } | |
105 | ||
106 | static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs) | |
107 | { | |
108 | sdhci_clear_set_irqs(host, 0, irqs); | |
109 | } | |
110 | ||
111 | static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs) | |
112 | { | |
113 | sdhci_clear_set_irqs(host, irqs, 0); | |
114 | } | |
115 | ||
116 | static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) | |
117 | { | |
118 | u32 irqs = SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT; | |
119 | ||
68d1fb7e AV |
120 | if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) |
121 | return; | |
122 | ||
7260cf5e AV |
123 | if (enable) |
124 | sdhci_unmask_irqs(host, irqs); | |
125 | else | |
126 | sdhci_mask_irqs(host, irqs); | |
127 | } | |
128 | ||
129 | static void sdhci_enable_card_detection(struct sdhci_host *host) | |
130 | { | |
131 | sdhci_set_card_detection(host, true); | |
132 | } | |
133 | ||
134 | static void sdhci_disable_card_detection(struct sdhci_host *host) | |
135 | { | |
136 | sdhci_set_card_detection(host, false); | |
137 | } | |
138 | ||
d129bceb PO |
139 | static void sdhci_reset(struct sdhci_host *host, u8 mask) |
140 | { | |
e16514d8 | 141 | unsigned long timeout; |
063a9dbb | 142 | u32 uninitialized_var(ier); |
e16514d8 | 143 | |
b8c86fc5 | 144 | if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { |
4e4141a5 | 145 | if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & |
8a4da143 PO |
146 | SDHCI_CARD_PRESENT)) |
147 | return; | |
148 | } | |
149 | ||
063a9dbb AV |
150 | if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) |
151 | ier = sdhci_readl(host, SDHCI_INT_ENABLE); | |
152 | ||
4e4141a5 | 153 | sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); |
d129bceb | 154 | |
e16514d8 | 155 | if (mask & SDHCI_RESET_ALL) |
d129bceb PO |
156 | host->clock = 0; |
157 | ||
e16514d8 PO |
158 | /* Wait max 100 ms */ |
159 | timeout = 100; | |
160 | ||
161 | /* hw clears the bit when it's done */ | |
4e4141a5 | 162 | while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { |
e16514d8 | 163 | if (timeout == 0) { |
acf1da45 | 164 | printk(KERN_ERR "%s: Reset 0x%x never completed.\n", |
e16514d8 PO |
165 | mmc_hostname(host->mmc), (int)mask); |
166 | sdhci_dumpregs(host); | |
167 | return; | |
168 | } | |
169 | timeout--; | |
170 | mdelay(1); | |
d129bceb | 171 | } |
063a9dbb AV |
172 | |
173 | if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) | |
174 | sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier); | |
d129bceb PO |
175 | } |
176 | ||
177 | static void sdhci_init(struct sdhci_host *host) | |
178 | { | |
d129bceb PO |
179 | sdhci_reset(host, SDHCI_RESET_ALL); |
180 | ||
7260cf5e AV |
181 | sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, |
182 | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | | |
3192a28f PO |
183 | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | |
184 | SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | | |
6aa943ab | 185 | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE); |
7260cf5e | 186 | } |
d129bceb | 187 | |
7260cf5e AV |
188 | static void sdhci_reinit(struct sdhci_host *host) |
189 | { | |
190 | sdhci_init(host); | |
191 | sdhci_enable_card_detection(host); | |
d129bceb PO |
192 | } |
193 | ||
194 | static void sdhci_activate_led(struct sdhci_host *host) | |
195 | { | |
196 | u8 ctrl; | |
197 | ||
4e4141a5 | 198 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
d129bceb | 199 | ctrl |= SDHCI_CTRL_LED; |
4e4141a5 | 200 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
d129bceb PO |
201 | } |
202 | ||
203 | static void sdhci_deactivate_led(struct sdhci_host *host) | |
204 | { | |
205 | u8 ctrl; | |
206 | ||
4e4141a5 | 207 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
d129bceb | 208 | ctrl &= ~SDHCI_CTRL_LED; |
4e4141a5 | 209 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
d129bceb PO |
210 | } |
211 | ||
f9134319 | 212 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec PO |
213 | static void sdhci_led_control(struct led_classdev *led, |
214 | enum led_brightness brightness) | |
215 | { | |
216 | struct sdhci_host *host = container_of(led, struct sdhci_host, led); | |
217 | unsigned long flags; | |
218 | ||
219 | spin_lock_irqsave(&host->lock, flags); | |
220 | ||
221 | if (brightness == LED_OFF) | |
222 | sdhci_deactivate_led(host); | |
223 | else | |
224 | sdhci_activate_led(host); | |
225 | ||
226 | spin_unlock_irqrestore(&host->lock, flags); | |
227 | } | |
228 | #endif | |
229 | ||
d129bceb PO |
230 | /*****************************************************************************\ |
231 | * * | |
232 | * Core functions * | |
233 | * * | |
234 | \*****************************************************************************/ | |
235 | ||
a406f5a3 | 236 | static void sdhci_read_block_pio(struct sdhci_host *host) |
d129bceb | 237 | { |
7659150c PO |
238 | unsigned long flags; |
239 | size_t blksize, len, chunk; | |
7244b85b | 240 | u32 uninitialized_var(scratch); |
7659150c | 241 | u8 *buf; |
d129bceb | 242 | |
a406f5a3 | 243 | DBG("PIO reading\n"); |
d129bceb | 244 | |
a406f5a3 | 245 | blksize = host->data->blksz; |
7659150c | 246 | chunk = 0; |
d129bceb | 247 | |
7659150c | 248 | local_irq_save(flags); |
d129bceb | 249 | |
a406f5a3 | 250 | while (blksize) { |
7659150c PO |
251 | if (!sg_miter_next(&host->sg_miter)) |
252 | BUG(); | |
d129bceb | 253 | |
7659150c | 254 | len = min(host->sg_miter.length, blksize); |
d129bceb | 255 | |
7659150c PO |
256 | blksize -= len; |
257 | host->sg_miter.consumed = len; | |
14d836e7 | 258 | |
7659150c | 259 | buf = host->sg_miter.addr; |
d129bceb | 260 | |
7659150c PO |
261 | while (len) { |
262 | if (chunk == 0) { | |
4e4141a5 | 263 | scratch = sdhci_readl(host, SDHCI_BUFFER); |
7659150c | 264 | chunk = 4; |
a406f5a3 | 265 | } |
7659150c PO |
266 | |
267 | *buf = scratch & 0xFF; | |
268 | ||
269 | buf++; | |
270 | scratch >>= 8; | |
271 | chunk--; | |
272 | len--; | |
d129bceb | 273 | } |
a406f5a3 | 274 | } |
7659150c PO |
275 | |
276 | sg_miter_stop(&host->sg_miter); | |
277 | ||
278 | local_irq_restore(flags); | |
a406f5a3 | 279 | } |
d129bceb | 280 | |
a406f5a3 PO |
281 | static void sdhci_write_block_pio(struct sdhci_host *host) |
282 | { | |
7659150c PO |
283 | unsigned long flags; |
284 | size_t blksize, len, chunk; | |
285 | u32 scratch; | |
286 | u8 *buf; | |
d129bceb | 287 | |
a406f5a3 PO |
288 | DBG("PIO writing\n"); |
289 | ||
290 | blksize = host->data->blksz; | |
7659150c PO |
291 | chunk = 0; |
292 | scratch = 0; | |
d129bceb | 293 | |
7659150c | 294 | local_irq_save(flags); |
d129bceb | 295 | |
a406f5a3 | 296 | while (blksize) { |
7659150c PO |
297 | if (!sg_miter_next(&host->sg_miter)) |
298 | BUG(); | |
a406f5a3 | 299 | |
7659150c PO |
300 | len = min(host->sg_miter.length, blksize); |
301 | ||
302 | blksize -= len; | |
303 | host->sg_miter.consumed = len; | |
304 | ||
305 | buf = host->sg_miter.addr; | |
d129bceb | 306 | |
7659150c PO |
307 | while (len) { |
308 | scratch |= (u32)*buf << (chunk * 8); | |
309 | ||
310 | buf++; | |
311 | chunk++; | |
312 | len--; | |
313 | ||
314 | if ((chunk == 4) || ((len == 0) && (blksize == 0))) { | |
4e4141a5 | 315 | sdhci_writel(host, scratch, SDHCI_BUFFER); |
7659150c PO |
316 | chunk = 0; |
317 | scratch = 0; | |
d129bceb | 318 | } |
d129bceb PO |
319 | } |
320 | } | |
7659150c PO |
321 | |
322 | sg_miter_stop(&host->sg_miter); | |
323 | ||
324 | local_irq_restore(flags); | |
a406f5a3 PO |
325 | } |
326 | ||
327 | static void sdhci_transfer_pio(struct sdhci_host *host) | |
328 | { | |
329 | u32 mask; | |
330 | ||
331 | BUG_ON(!host->data); | |
332 | ||
7659150c | 333 | if (host->blocks == 0) |
a406f5a3 PO |
334 | return; |
335 | ||
336 | if (host->data->flags & MMC_DATA_READ) | |
337 | mask = SDHCI_DATA_AVAILABLE; | |
338 | else | |
339 | mask = SDHCI_SPACE_AVAILABLE; | |
340 | ||
4a3cba32 PO |
341 | /* |
342 | * Some controllers (JMicron JMB38x) mess up the buffer bits | |
343 | * for transfers < 4 bytes. As long as it is just one block, | |
344 | * we can ignore the bits. | |
345 | */ | |
346 | if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && | |
347 | (host->data->blocks == 1)) | |
348 | mask = ~0; | |
349 | ||
4e4141a5 | 350 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { |
3e3bf207 AV |
351 | if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) |
352 | udelay(100); | |
353 | ||
a406f5a3 PO |
354 | if (host->data->flags & MMC_DATA_READ) |
355 | sdhci_read_block_pio(host); | |
356 | else | |
357 | sdhci_write_block_pio(host); | |
d129bceb | 358 | |
7659150c PO |
359 | host->blocks--; |
360 | if (host->blocks == 0) | |
a406f5a3 | 361 | break; |
a406f5a3 | 362 | } |
d129bceb | 363 | |
a406f5a3 | 364 | DBG("PIO transfer complete.\n"); |
d129bceb PO |
365 | } |
366 | ||
2134a922 PO |
367 | static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) |
368 | { | |
369 | local_irq_save(*flags); | |
370 | return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset; | |
371 | } | |
372 | ||
373 | static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) | |
374 | { | |
375 | kunmap_atomic(buffer, KM_BIO_SRC_IRQ); | |
376 | local_irq_restore(*flags); | |
377 | } | |
378 | ||
8f1934ce | 379 | static int sdhci_adma_table_pre(struct sdhci_host *host, |
2134a922 PO |
380 | struct mmc_data *data) |
381 | { | |
382 | int direction; | |
383 | ||
384 | u8 *desc; | |
385 | u8 *align; | |
386 | dma_addr_t addr; | |
387 | dma_addr_t align_addr; | |
388 | int len, offset; | |
389 | ||
390 | struct scatterlist *sg; | |
391 | int i; | |
392 | char *buffer; | |
393 | unsigned long flags; | |
394 | ||
395 | /* | |
396 | * The spec does not specify endianness of descriptor table. | |
397 | * We currently guess that it is LE. | |
398 | */ | |
399 | ||
400 | if (data->flags & MMC_DATA_READ) | |
401 | direction = DMA_FROM_DEVICE; | |
402 | else | |
403 | direction = DMA_TO_DEVICE; | |
404 | ||
405 | /* | |
406 | * The ADMA descriptor table is mapped further down as we | |
407 | * need to fill it with data first. | |
408 | */ | |
409 | ||
410 | host->align_addr = dma_map_single(mmc_dev(host->mmc), | |
411 | host->align_buffer, 128 * 4, direction); | |
8d8bb39b | 412 | if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr)) |
8f1934ce | 413 | goto fail; |
2134a922 PO |
414 | BUG_ON(host->align_addr & 0x3); |
415 | ||
416 | host->sg_count = dma_map_sg(mmc_dev(host->mmc), | |
417 | data->sg, data->sg_len, direction); | |
8f1934ce PO |
418 | if (host->sg_count == 0) |
419 | goto unmap_align; | |
2134a922 PO |
420 | |
421 | desc = host->adma_desc; | |
422 | align = host->align_buffer; | |
423 | ||
424 | align_addr = host->align_addr; | |
425 | ||
426 | for_each_sg(data->sg, sg, host->sg_count, i) { | |
427 | addr = sg_dma_address(sg); | |
428 | len = sg_dma_len(sg); | |
429 | ||
430 | /* | |
431 | * The SDHCI specification states that ADMA | |
432 | * addresses must be 32-bit aligned. If they | |
433 | * aren't, then we use a bounce buffer for | |
434 | * the (up to three) bytes that screw up the | |
435 | * alignment. | |
436 | */ | |
437 | offset = (4 - (addr & 0x3)) & 0x3; | |
438 | if (offset) { | |
439 | if (data->flags & MMC_DATA_WRITE) { | |
440 | buffer = sdhci_kmap_atomic(sg, &flags); | |
6cefd05f | 441 | WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); |
2134a922 PO |
442 | memcpy(align, buffer, offset); |
443 | sdhci_kunmap_atomic(buffer, &flags); | |
444 | } | |
445 | ||
446 | desc[7] = (align_addr >> 24) & 0xff; | |
447 | desc[6] = (align_addr >> 16) & 0xff; | |
448 | desc[5] = (align_addr >> 8) & 0xff; | |
449 | desc[4] = (align_addr >> 0) & 0xff; | |
450 | ||
451 | BUG_ON(offset > 65536); | |
452 | ||
453 | desc[3] = (offset >> 8) & 0xff; | |
454 | desc[2] = (offset >> 0) & 0xff; | |
455 | ||
456 | desc[1] = 0x00; | |
457 | desc[0] = 0x21; /* tran, valid */ | |
458 | ||
459 | align += 4; | |
460 | align_addr += 4; | |
461 | ||
462 | desc += 8; | |
463 | ||
464 | addr += offset; | |
465 | len -= offset; | |
466 | } | |
467 | ||
468 | desc[7] = (addr >> 24) & 0xff; | |
469 | desc[6] = (addr >> 16) & 0xff; | |
470 | desc[5] = (addr >> 8) & 0xff; | |
471 | desc[4] = (addr >> 0) & 0xff; | |
472 | ||
473 | BUG_ON(len > 65536); | |
474 | ||
475 | desc[3] = (len >> 8) & 0xff; | |
476 | desc[2] = (len >> 0) & 0xff; | |
477 | ||
478 | desc[1] = 0x00; | |
479 | desc[0] = 0x21; /* tran, valid */ | |
480 | ||
481 | desc += 8; | |
482 | ||
483 | /* | |
484 | * If this triggers then we have a calculation bug | |
485 | * somewhere. :/ | |
486 | */ | |
487 | WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4); | |
488 | } | |
489 | ||
490 | /* | |
491 | * Add a terminating entry. | |
492 | */ | |
493 | desc[7] = 0; | |
494 | desc[6] = 0; | |
495 | desc[5] = 0; | |
496 | desc[4] = 0; | |
497 | ||
498 | desc[3] = 0; | |
499 | desc[2] = 0; | |
500 | ||
501 | desc[1] = 0x00; | |
502 | desc[0] = 0x03; /* nop, end, valid */ | |
503 | ||
504 | /* | |
505 | * Resync align buffer as we might have changed it. | |
506 | */ | |
507 | if (data->flags & MMC_DATA_WRITE) { | |
508 | dma_sync_single_for_device(mmc_dev(host->mmc), | |
509 | host->align_addr, 128 * 4, direction); | |
510 | } | |
511 | ||
512 | host->adma_addr = dma_map_single(mmc_dev(host->mmc), | |
513 | host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE); | |
980167b7 | 514 | if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr)) |
8f1934ce | 515 | goto unmap_entries; |
2134a922 | 516 | BUG_ON(host->adma_addr & 0x3); |
8f1934ce PO |
517 | |
518 | return 0; | |
519 | ||
520 | unmap_entries: | |
521 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, | |
522 | data->sg_len, direction); | |
523 | unmap_align: | |
524 | dma_unmap_single(mmc_dev(host->mmc), host->align_addr, | |
525 | 128 * 4, direction); | |
526 | fail: | |
527 | return -EINVAL; | |
2134a922 PO |
528 | } |
529 | ||
530 | static void sdhci_adma_table_post(struct sdhci_host *host, | |
531 | struct mmc_data *data) | |
532 | { | |
533 | int direction; | |
534 | ||
535 | struct scatterlist *sg; | |
536 | int i, size; | |
537 | u8 *align; | |
538 | char *buffer; | |
539 | unsigned long flags; | |
540 | ||
541 | if (data->flags & MMC_DATA_READ) | |
542 | direction = DMA_FROM_DEVICE; | |
543 | else | |
544 | direction = DMA_TO_DEVICE; | |
545 | ||
546 | dma_unmap_single(mmc_dev(host->mmc), host->adma_addr, | |
547 | (128 * 2 + 1) * 4, DMA_TO_DEVICE); | |
548 | ||
549 | dma_unmap_single(mmc_dev(host->mmc), host->align_addr, | |
550 | 128 * 4, direction); | |
551 | ||
552 | if (data->flags & MMC_DATA_READ) { | |
553 | dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, | |
554 | data->sg_len, direction); | |
555 | ||
556 | align = host->align_buffer; | |
557 | ||
558 | for_each_sg(data->sg, sg, host->sg_count, i) { | |
559 | if (sg_dma_address(sg) & 0x3) { | |
560 | size = 4 - (sg_dma_address(sg) & 0x3); | |
561 | ||
562 | buffer = sdhci_kmap_atomic(sg, &flags); | |
6cefd05f | 563 | WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); |
2134a922 PO |
564 | memcpy(buffer, align, size); |
565 | sdhci_kunmap_atomic(buffer, &flags); | |
566 | ||
567 | align += 4; | |
568 | } | |
569 | } | |
570 | } | |
571 | ||
572 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, | |
573 | data->sg_len, direction); | |
574 | } | |
575 | ||
ee53ab5d | 576 | static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data) |
d129bceb | 577 | { |
1c8cde92 PO |
578 | u8 count; |
579 | unsigned target_timeout, current_timeout; | |
d129bceb | 580 | |
ee53ab5d PO |
581 | /* |
582 | * If the host controller provides us with an incorrect timeout | |
583 | * value, just skip the check and use 0xE. The hardware may take | |
584 | * longer to time out, but that's much better than having a too-short | |
585 | * timeout value. | |
586 | */ | |
587 | if ((host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)) | |
588 | return 0xE; | |
e538fbe8 | 589 | |
1c8cde92 PO |
590 | /* timeout in us */ |
591 | target_timeout = data->timeout_ns / 1000 + | |
592 | data->timeout_clks / host->clock; | |
d129bceb | 593 | |
1c8cde92 PO |
594 | /* |
595 | * Figure out needed cycles. | |
596 | * We do this in steps in order to fit inside a 32 bit int. | |
597 | * The first step is the minimum timeout, which will have a | |
598 | * minimum resolution of 6 bits: | |
599 | * (1) 2^13*1000 > 2^22, | |
600 | * (2) host->timeout_clk < 2^16 | |
601 | * => | |
602 | * (1) / (2) > 2^6 | |
603 | */ | |
604 | count = 0; | |
605 | current_timeout = (1 << 13) * 1000 / host->timeout_clk; | |
606 | while (current_timeout < target_timeout) { | |
607 | count++; | |
608 | current_timeout <<= 1; | |
609 | if (count >= 0xF) | |
610 | break; | |
611 | } | |
612 | ||
613 | if (count >= 0xF) { | |
614 | printk(KERN_WARNING "%s: Too large timeout requested!\n", | |
615 | mmc_hostname(host->mmc)); | |
616 | count = 0xE; | |
617 | } | |
618 | ||
ee53ab5d PO |
619 | return count; |
620 | } | |
621 | ||
6aa943ab AV |
622 | static void sdhci_set_transfer_irqs(struct sdhci_host *host) |
623 | { | |
624 | u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; | |
625 | u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; | |
626 | ||
627 | if (host->flags & SDHCI_REQ_USE_DMA) | |
628 | sdhci_clear_set_irqs(host, pio_irqs, dma_irqs); | |
629 | else | |
630 | sdhci_clear_set_irqs(host, dma_irqs, pio_irqs); | |
631 | } | |
632 | ||
ee53ab5d PO |
633 | static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data) |
634 | { | |
635 | u8 count; | |
2134a922 | 636 | u8 ctrl; |
8f1934ce | 637 | int ret; |
ee53ab5d PO |
638 | |
639 | WARN_ON(host->data); | |
640 | ||
641 | if (data == NULL) | |
642 | return; | |
643 | ||
644 | /* Sanity checks */ | |
645 | BUG_ON(data->blksz * data->blocks > 524288); | |
646 | BUG_ON(data->blksz > host->mmc->max_blk_size); | |
647 | BUG_ON(data->blocks > 65535); | |
648 | ||
649 | host->data = data; | |
650 | host->data_early = 0; | |
651 | ||
652 | count = sdhci_calc_timeout(host, data); | |
4e4141a5 | 653 | sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); |
d129bceb | 654 | |
c9fddbc4 PO |
655 | if (host->flags & SDHCI_USE_DMA) |
656 | host->flags |= SDHCI_REQ_USE_DMA; | |
657 | ||
2134a922 PO |
658 | /* |
659 | * FIXME: This doesn't account for merging when mapping the | |
660 | * scatterlist. | |
661 | */ | |
662 | if (host->flags & SDHCI_REQ_USE_DMA) { | |
663 | int broken, i; | |
664 | struct scatterlist *sg; | |
665 | ||
666 | broken = 0; | |
667 | if (host->flags & SDHCI_USE_ADMA) { | |
668 | if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) | |
669 | broken = 1; | |
670 | } else { | |
671 | if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) | |
672 | broken = 1; | |
673 | } | |
674 | ||
675 | if (unlikely(broken)) { | |
676 | for_each_sg(data->sg, sg, data->sg_len, i) { | |
677 | if (sg->length & 0x3) { | |
678 | DBG("Reverting to PIO because of " | |
679 | "transfer size (%d)\n", | |
680 | sg->length); | |
681 | host->flags &= ~SDHCI_REQ_USE_DMA; | |
682 | break; | |
683 | } | |
684 | } | |
685 | } | |
c9fddbc4 PO |
686 | } |
687 | ||
688 | /* | |
689 | * The assumption here being that alignment is the same after | |
690 | * translation to device address space. | |
691 | */ | |
2134a922 PO |
692 | if (host->flags & SDHCI_REQ_USE_DMA) { |
693 | int broken, i; | |
694 | struct scatterlist *sg; | |
695 | ||
696 | broken = 0; | |
697 | if (host->flags & SDHCI_USE_ADMA) { | |
698 | /* | |
699 | * As we use 3 byte chunks to work around | |
700 | * alignment problems, we need to check this | |
701 | * quirk. | |
702 | */ | |
703 | if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) | |
704 | broken = 1; | |
705 | } else { | |
706 | if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) | |
707 | broken = 1; | |
708 | } | |
709 | ||
710 | if (unlikely(broken)) { | |
711 | for_each_sg(data->sg, sg, data->sg_len, i) { | |
712 | if (sg->offset & 0x3) { | |
713 | DBG("Reverting to PIO because of " | |
714 | "bad alignment\n"); | |
715 | host->flags &= ~SDHCI_REQ_USE_DMA; | |
716 | break; | |
717 | } | |
718 | } | |
719 | } | |
720 | } | |
721 | ||
8f1934ce PO |
722 | if (host->flags & SDHCI_REQ_USE_DMA) { |
723 | if (host->flags & SDHCI_USE_ADMA) { | |
724 | ret = sdhci_adma_table_pre(host, data); | |
725 | if (ret) { | |
726 | /* | |
727 | * This only happens when someone fed | |
728 | * us an invalid request. | |
729 | */ | |
730 | WARN_ON(1); | |
ebd6d357 | 731 | host->flags &= ~SDHCI_REQ_USE_DMA; |
8f1934ce | 732 | } else { |
4e4141a5 AV |
733 | sdhci_writel(host, host->adma_addr, |
734 | SDHCI_ADMA_ADDRESS); | |
8f1934ce PO |
735 | } |
736 | } else { | |
c8b3e02e | 737 | int sg_cnt; |
8f1934ce | 738 | |
c8b3e02e | 739 | sg_cnt = dma_map_sg(mmc_dev(host->mmc), |
8f1934ce PO |
740 | data->sg, data->sg_len, |
741 | (data->flags & MMC_DATA_READ) ? | |
742 | DMA_FROM_DEVICE : | |
743 | DMA_TO_DEVICE); | |
c8b3e02e | 744 | if (sg_cnt == 0) { |
8f1934ce PO |
745 | /* |
746 | * This only happens when someone fed | |
747 | * us an invalid request. | |
748 | */ | |
749 | WARN_ON(1); | |
ebd6d357 | 750 | host->flags &= ~SDHCI_REQ_USE_DMA; |
8f1934ce | 751 | } else { |
719a61b4 | 752 | WARN_ON(sg_cnt != 1); |
4e4141a5 AV |
753 | sdhci_writel(host, sg_dma_address(data->sg), |
754 | SDHCI_DMA_ADDRESS); | |
8f1934ce PO |
755 | } |
756 | } | |
757 | } | |
758 | ||
2134a922 PO |
759 | /* |
760 | * Always adjust the DMA selection as some controllers | |
761 | * (e.g. JMicron) can't do PIO properly when the selection | |
762 | * is ADMA. | |
763 | */ | |
764 | if (host->version >= SDHCI_SPEC_200) { | |
4e4141a5 | 765 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
2134a922 PO |
766 | ctrl &= ~SDHCI_CTRL_DMA_MASK; |
767 | if ((host->flags & SDHCI_REQ_USE_DMA) && | |
768 | (host->flags & SDHCI_USE_ADMA)) | |
769 | ctrl |= SDHCI_CTRL_ADMA32; | |
770 | else | |
771 | ctrl |= SDHCI_CTRL_SDMA; | |
4e4141a5 | 772 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
c9fddbc4 PO |
773 | } |
774 | ||
8f1934ce | 775 | if (!(host->flags & SDHCI_REQ_USE_DMA)) { |
7659150c PO |
776 | sg_miter_start(&host->sg_miter, |
777 | data->sg, data->sg_len, SG_MITER_ATOMIC); | |
778 | host->blocks = data->blocks; | |
d129bceb | 779 | } |
c7fa9963 | 780 | |
6aa943ab AV |
781 | sdhci_set_transfer_irqs(host); |
782 | ||
bab76961 | 783 | /* We do not handle DMA boundaries, so set it to max (512 KiB) */ |
4e4141a5 AV |
784 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, data->blksz), SDHCI_BLOCK_SIZE); |
785 | sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); | |
c7fa9963 PO |
786 | } |
787 | ||
788 | static void sdhci_set_transfer_mode(struct sdhci_host *host, | |
789 | struct mmc_data *data) | |
790 | { | |
791 | u16 mode; | |
792 | ||
c7fa9963 PO |
793 | if (data == NULL) |
794 | return; | |
795 | ||
e538fbe8 PO |
796 | WARN_ON(!host->data); |
797 | ||
c7fa9963 PO |
798 | mode = SDHCI_TRNS_BLK_CNT_EN; |
799 | if (data->blocks > 1) | |
800 | mode |= SDHCI_TRNS_MULTI; | |
801 | if (data->flags & MMC_DATA_READ) | |
802 | mode |= SDHCI_TRNS_READ; | |
c9fddbc4 | 803 | if (host->flags & SDHCI_REQ_USE_DMA) |
c7fa9963 PO |
804 | mode |= SDHCI_TRNS_DMA; |
805 | ||
4e4141a5 | 806 | sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); |
d129bceb PO |
807 | } |
808 | ||
809 | static void sdhci_finish_data(struct sdhci_host *host) | |
810 | { | |
811 | struct mmc_data *data; | |
d129bceb PO |
812 | |
813 | BUG_ON(!host->data); | |
814 | ||
815 | data = host->data; | |
816 | host->data = NULL; | |
817 | ||
c9fddbc4 | 818 | if (host->flags & SDHCI_REQ_USE_DMA) { |
2134a922 PO |
819 | if (host->flags & SDHCI_USE_ADMA) |
820 | sdhci_adma_table_post(host, data); | |
821 | else { | |
822 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, | |
823 | data->sg_len, (data->flags & MMC_DATA_READ) ? | |
824 | DMA_FROM_DEVICE : DMA_TO_DEVICE); | |
825 | } | |
d129bceb PO |
826 | } |
827 | ||
828 | /* | |
c9b74c5b PO |
829 | * The specification states that the block count register must |
830 | * be updated, but it does not specify at what point in the | |
831 | * data flow. That makes the register entirely useless to read | |
832 | * back so we have to assume that nothing made it to the card | |
833 | * in the event of an error. | |
d129bceb | 834 | */ |
c9b74c5b PO |
835 | if (data->error) |
836 | data->bytes_xfered = 0; | |
d129bceb | 837 | else |
c9b74c5b | 838 | data->bytes_xfered = data->blksz * data->blocks; |
d129bceb | 839 | |
d129bceb PO |
840 | if (data->stop) { |
841 | /* | |
842 | * The controller needs a reset of internal state machines | |
843 | * upon error conditions. | |
844 | */ | |
17b0429d | 845 | if (data->error) { |
d129bceb PO |
846 | sdhci_reset(host, SDHCI_RESET_CMD); |
847 | sdhci_reset(host, SDHCI_RESET_DATA); | |
848 | } | |
849 | ||
850 | sdhci_send_command(host, data->stop); | |
851 | } else | |
852 | tasklet_schedule(&host->finish_tasklet); | |
853 | } | |
854 | ||
855 | static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) | |
856 | { | |
857 | int flags; | |
fd2208d7 | 858 | u32 mask; |
7cb2c76f | 859 | unsigned long timeout; |
d129bceb PO |
860 | |
861 | WARN_ON(host->cmd); | |
862 | ||
d129bceb | 863 | /* Wait max 10 ms */ |
7cb2c76f | 864 | timeout = 10; |
fd2208d7 PO |
865 | |
866 | mask = SDHCI_CMD_INHIBIT; | |
867 | if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) | |
868 | mask |= SDHCI_DATA_INHIBIT; | |
869 | ||
870 | /* We shouldn't wait for data inihibit for stop commands, even | |
871 | though they might use busy signaling */ | |
872 | if (host->mrq->data && (cmd == host->mrq->data->stop)) | |
873 | mask &= ~SDHCI_DATA_INHIBIT; | |
874 | ||
4e4141a5 | 875 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { |
7cb2c76f | 876 | if (timeout == 0) { |
d129bceb | 877 | printk(KERN_ERR "%s: Controller never released " |
acf1da45 | 878 | "inhibit bit(s).\n", mmc_hostname(host->mmc)); |
d129bceb | 879 | sdhci_dumpregs(host); |
17b0429d | 880 | cmd->error = -EIO; |
d129bceb PO |
881 | tasklet_schedule(&host->finish_tasklet); |
882 | return; | |
883 | } | |
7cb2c76f PO |
884 | timeout--; |
885 | mdelay(1); | |
886 | } | |
d129bceb PO |
887 | |
888 | mod_timer(&host->timer, jiffies + 10 * HZ); | |
889 | ||
890 | host->cmd = cmd; | |
891 | ||
892 | sdhci_prepare_data(host, cmd->data); | |
893 | ||
4e4141a5 | 894 | sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); |
d129bceb | 895 | |
c7fa9963 PO |
896 | sdhci_set_transfer_mode(host, cmd->data); |
897 | ||
d129bceb | 898 | if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { |
acf1da45 | 899 | printk(KERN_ERR "%s: Unsupported response type!\n", |
d129bceb | 900 | mmc_hostname(host->mmc)); |
17b0429d | 901 | cmd->error = -EINVAL; |
d129bceb PO |
902 | tasklet_schedule(&host->finish_tasklet); |
903 | return; | |
904 | } | |
905 | ||
906 | if (!(cmd->flags & MMC_RSP_PRESENT)) | |
907 | flags = SDHCI_CMD_RESP_NONE; | |
908 | else if (cmd->flags & MMC_RSP_136) | |
909 | flags = SDHCI_CMD_RESP_LONG; | |
910 | else if (cmd->flags & MMC_RSP_BUSY) | |
911 | flags = SDHCI_CMD_RESP_SHORT_BUSY; | |
912 | else | |
913 | flags = SDHCI_CMD_RESP_SHORT; | |
914 | ||
915 | if (cmd->flags & MMC_RSP_CRC) | |
916 | flags |= SDHCI_CMD_CRC; | |
917 | if (cmd->flags & MMC_RSP_OPCODE) | |
918 | flags |= SDHCI_CMD_INDEX; | |
919 | if (cmd->data) | |
920 | flags |= SDHCI_CMD_DATA; | |
921 | ||
4e4141a5 | 922 | sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); |
d129bceb PO |
923 | } |
924 | ||
925 | static void sdhci_finish_command(struct sdhci_host *host) | |
926 | { | |
927 | int i; | |
928 | ||
929 | BUG_ON(host->cmd == NULL); | |
930 | ||
931 | if (host->cmd->flags & MMC_RSP_PRESENT) { | |
932 | if (host->cmd->flags & MMC_RSP_136) { | |
933 | /* CRC is stripped so we need to do some shifting. */ | |
934 | for (i = 0;i < 4;i++) { | |
4e4141a5 | 935 | host->cmd->resp[i] = sdhci_readl(host, |
d129bceb PO |
936 | SDHCI_RESPONSE + (3-i)*4) << 8; |
937 | if (i != 3) | |
938 | host->cmd->resp[i] |= | |
4e4141a5 | 939 | sdhci_readb(host, |
d129bceb PO |
940 | SDHCI_RESPONSE + (3-i)*4-1); |
941 | } | |
942 | } else { | |
4e4141a5 | 943 | host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); |
d129bceb PO |
944 | } |
945 | } | |
946 | ||
17b0429d | 947 | host->cmd->error = 0; |
d129bceb | 948 | |
e538fbe8 PO |
949 | if (host->data && host->data_early) |
950 | sdhci_finish_data(host); | |
951 | ||
952 | if (!host->cmd->data) | |
d129bceb PO |
953 | tasklet_schedule(&host->finish_tasklet); |
954 | ||
955 | host->cmd = NULL; | |
956 | } | |
957 | ||
958 | static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) | |
959 | { | |
960 | int div; | |
961 | u16 clk; | |
7cb2c76f | 962 | unsigned long timeout; |
d129bceb PO |
963 | |
964 | if (clock == host->clock) | |
965 | return; | |
966 | ||
8114634c AV |
967 | if (host->ops->set_clock) { |
968 | host->ops->set_clock(host, clock); | |
969 | if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) | |
970 | return; | |
971 | } | |
972 | ||
4e4141a5 | 973 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); |
d129bceb PO |
974 | |
975 | if (clock == 0) | |
976 | goto out; | |
977 | ||
978 | for (div = 1;div < 256;div *= 2) { | |
979 | if ((host->max_clk / div) <= clock) | |
980 | break; | |
981 | } | |
982 | div >>= 1; | |
983 | ||
984 | clk = div << SDHCI_DIVIDER_SHIFT; | |
985 | clk |= SDHCI_CLOCK_INT_EN; | |
4e4141a5 | 986 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
d129bceb PO |
987 | |
988 | /* Wait max 10 ms */ | |
7cb2c76f | 989 | timeout = 10; |
4e4141a5 | 990 | while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) |
7cb2c76f PO |
991 | & SDHCI_CLOCK_INT_STABLE)) { |
992 | if (timeout == 0) { | |
acf1da45 PO |
993 | printk(KERN_ERR "%s: Internal clock never " |
994 | "stabilised.\n", mmc_hostname(host->mmc)); | |
d129bceb PO |
995 | sdhci_dumpregs(host); |
996 | return; | |
997 | } | |
7cb2c76f PO |
998 | timeout--; |
999 | mdelay(1); | |
1000 | } | |
d129bceb PO |
1001 | |
1002 | clk |= SDHCI_CLOCK_CARD_EN; | |
4e4141a5 | 1003 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
d129bceb PO |
1004 | |
1005 | out: | |
1006 | host->clock = clock; | |
1007 | } | |
1008 | ||
146ad66e PO |
1009 | static void sdhci_set_power(struct sdhci_host *host, unsigned short power) |
1010 | { | |
1011 | u8 pwr; | |
1012 | ||
ae628903 PO |
1013 | if (power == (unsigned short)-1) |
1014 | pwr = 0; | |
1015 | else { | |
1016 | switch (1 << power) { | |
1017 | case MMC_VDD_165_195: | |
1018 | pwr = SDHCI_POWER_180; | |
1019 | break; | |
1020 | case MMC_VDD_29_30: | |
1021 | case MMC_VDD_30_31: | |
1022 | pwr = SDHCI_POWER_300; | |
1023 | break; | |
1024 | case MMC_VDD_32_33: | |
1025 | case MMC_VDD_33_34: | |
1026 | pwr = SDHCI_POWER_330; | |
1027 | break; | |
1028 | default: | |
1029 | BUG(); | |
1030 | } | |
1031 | } | |
1032 | ||
1033 | if (host->pwr == pwr) | |
146ad66e PO |
1034 | return; |
1035 | ||
ae628903 PO |
1036 | host->pwr = pwr; |
1037 | ||
1038 | if (pwr == 0) { | |
4e4141a5 | 1039 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
ae628903 | 1040 | return; |
9e9dc5f2 DS |
1041 | } |
1042 | ||
1043 | /* | |
1044 | * Spec says that we should clear the power reg before setting | |
1045 | * a new value. Some controllers don't seem to like this though. | |
1046 | */ | |
b8c86fc5 | 1047 | if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) |
4e4141a5 | 1048 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
146ad66e | 1049 | |
e08c1694 | 1050 | /* |
c71f6512 | 1051 | * At least the Marvell CaFe chip gets confused if we set the voltage |
e08c1694 AS |
1052 | * and set turn on power at the same time, so set the voltage first. |
1053 | */ | |
b8c86fc5 | 1054 | if ((host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)) |
ae628903 | 1055 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
e08c1694 | 1056 | |
ae628903 | 1057 | pwr |= SDHCI_POWER_ON; |
146ad66e | 1058 | |
ae628903 | 1059 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
146ad66e PO |
1060 | } |
1061 | ||
d129bceb PO |
1062 | /*****************************************************************************\ |
1063 | * * | |
1064 | * MMC callbacks * | |
1065 | * * | |
1066 | \*****************************************************************************/ | |
1067 | ||
1068 | static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
1069 | { | |
1070 | struct sdhci_host *host; | |
68d1fb7e | 1071 | bool present; |
d129bceb PO |
1072 | unsigned long flags; |
1073 | ||
1074 | host = mmc_priv(mmc); | |
1075 | ||
1076 | spin_lock_irqsave(&host->lock, flags); | |
1077 | ||
1078 | WARN_ON(host->mrq != NULL); | |
1079 | ||
f9134319 | 1080 | #ifndef SDHCI_USE_LEDS_CLASS |
d129bceb | 1081 | sdhci_activate_led(host); |
2f730fec | 1082 | #endif |
d129bceb PO |
1083 | |
1084 | host->mrq = mrq; | |
1085 | ||
68d1fb7e AV |
1086 | /* If polling, assume that the card is always present. */ |
1087 | if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) | |
1088 | present = true; | |
1089 | else | |
1090 | present = sdhci_readl(host, SDHCI_PRESENT_STATE) & | |
1091 | SDHCI_CARD_PRESENT; | |
1092 | ||
1093 | if (!present || host->flags & SDHCI_DEVICE_DEAD) { | |
17b0429d | 1094 | host->mrq->cmd->error = -ENOMEDIUM; |
d129bceb PO |
1095 | tasklet_schedule(&host->finish_tasklet); |
1096 | } else | |
1097 | sdhci_send_command(host, mrq->cmd); | |
1098 | ||
5f25a66f | 1099 | mmiowb(); |
d129bceb PO |
1100 | spin_unlock_irqrestore(&host->lock, flags); |
1101 | } | |
1102 | ||
1103 | static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
1104 | { | |
1105 | struct sdhci_host *host; | |
1106 | unsigned long flags; | |
1107 | u8 ctrl; | |
1108 | ||
1109 | host = mmc_priv(mmc); | |
1110 | ||
1111 | spin_lock_irqsave(&host->lock, flags); | |
1112 | ||
1e72859e PO |
1113 | if (host->flags & SDHCI_DEVICE_DEAD) |
1114 | goto out; | |
1115 | ||
d129bceb PO |
1116 | /* |
1117 | * Reset the chip on each power off. | |
1118 | * Should clear out any weird states. | |
1119 | */ | |
1120 | if (ios->power_mode == MMC_POWER_OFF) { | |
4e4141a5 | 1121 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); |
7260cf5e | 1122 | sdhci_reinit(host); |
d129bceb PO |
1123 | } |
1124 | ||
1125 | sdhci_set_clock(host, ios->clock); | |
1126 | ||
1127 | if (ios->power_mode == MMC_POWER_OFF) | |
146ad66e | 1128 | sdhci_set_power(host, -1); |
d129bceb | 1129 | else |
146ad66e | 1130 | sdhci_set_power(host, ios->vdd); |
d129bceb | 1131 | |
4e4141a5 | 1132 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
cd9277c0 | 1133 | |
d129bceb PO |
1134 | if (ios->bus_width == MMC_BUS_WIDTH_4) |
1135 | ctrl |= SDHCI_CTRL_4BITBUS; | |
1136 | else | |
1137 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
cd9277c0 PO |
1138 | |
1139 | if (ios->timing == MMC_TIMING_SD_HS) | |
1140 | ctrl |= SDHCI_CTRL_HISPD; | |
1141 | else | |
1142 | ctrl &= ~SDHCI_CTRL_HISPD; | |
1143 | ||
4e4141a5 | 1144 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
d129bceb | 1145 | |
b8352260 LD |
1146 | /* |
1147 | * Some (ENE) controllers go apeshit on some ios operation, | |
1148 | * signalling timeout and CRC errors even on CMD0. Resetting | |
1149 | * it on each ios seems to solve the problem. | |
1150 | */ | |
b8c86fc5 | 1151 | if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) |
b8352260 LD |
1152 | sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); |
1153 | ||
1e72859e | 1154 | out: |
5f25a66f | 1155 | mmiowb(); |
d129bceb PO |
1156 | spin_unlock_irqrestore(&host->lock, flags); |
1157 | } | |
1158 | ||
1159 | static int sdhci_get_ro(struct mmc_host *mmc) | |
1160 | { | |
1161 | struct sdhci_host *host; | |
1162 | unsigned long flags; | |
1163 | int present; | |
1164 | ||
1165 | host = mmc_priv(mmc); | |
1166 | ||
1167 | spin_lock_irqsave(&host->lock, flags); | |
1168 | ||
1e72859e PO |
1169 | if (host->flags & SDHCI_DEVICE_DEAD) |
1170 | present = 0; | |
1171 | else | |
4e4141a5 | 1172 | present = sdhci_readl(host, SDHCI_PRESENT_STATE); |
d129bceb PO |
1173 | |
1174 | spin_unlock_irqrestore(&host->lock, flags); | |
1175 | ||
c5075a10 AV |
1176 | if (host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT) |
1177 | return !!(present & SDHCI_WRITE_PROTECT); | |
d129bceb PO |
1178 | return !(present & SDHCI_WRITE_PROTECT); |
1179 | } | |
1180 | ||
f75979b7 PO |
1181 | static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) |
1182 | { | |
1183 | struct sdhci_host *host; | |
1184 | unsigned long flags; | |
f75979b7 PO |
1185 | |
1186 | host = mmc_priv(mmc); | |
1187 | ||
1188 | spin_lock_irqsave(&host->lock, flags); | |
1189 | ||
1e72859e PO |
1190 | if (host->flags & SDHCI_DEVICE_DEAD) |
1191 | goto out; | |
1192 | ||
f75979b7 | 1193 | if (enable) |
7260cf5e AV |
1194 | sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT); |
1195 | else | |
1196 | sdhci_mask_irqs(host, SDHCI_INT_CARD_INT); | |
1e72859e | 1197 | out: |
f75979b7 PO |
1198 | mmiowb(); |
1199 | ||
1200 | spin_unlock_irqrestore(&host->lock, flags); | |
1201 | } | |
1202 | ||
ab7aefd0 | 1203 | static const struct mmc_host_ops sdhci_ops = { |
d129bceb PO |
1204 | .request = sdhci_request, |
1205 | .set_ios = sdhci_set_ios, | |
1206 | .get_ro = sdhci_get_ro, | |
f75979b7 | 1207 | .enable_sdio_irq = sdhci_enable_sdio_irq, |
d129bceb PO |
1208 | }; |
1209 | ||
1210 | /*****************************************************************************\ | |
1211 | * * | |
1212 | * Tasklets * | |
1213 | * * | |
1214 | \*****************************************************************************/ | |
1215 | ||
1216 | static void sdhci_tasklet_card(unsigned long param) | |
1217 | { | |
1218 | struct sdhci_host *host; | |
1219 | unsigned long flags; | |
1220 | ||
1221 | host = (struct sdhci_host*)param; | |
1222 | ||
1223 | spin_lock_irqsave(&host->lock, flags); | |
1224 | ||
4e4141a5 | 1225 | if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { |
d129bceb PO |
1226 | if (host->mrq) { |
1227 | printk(KERN_ERR "%s: Card removed during transfer!\n", | |
1228 | mmc_hostname(host->mmc)); | |
1229 | printk(KERN_ERR "%s: Resetting controller.\n", | |
1230 | mmc_hostname(host->mmc)); | |
1231 | ||
1232 | sdhci_reset(host, SDHCI_RESET_CMD); | |
1233 | sdhci_reset(host, SDHCI_RESET_DATA); | |
1234 | ||
17b0429d | 1235 | host->mrq->cmd->error = -ENOMEDIUM; |
d129bceb PO |
1236 | tasklet_schedule(&host->finish_tasklet); |
1237 | } | |
1238 | } | |
1239 | ||
1240 | spin_unlock_irqrestore(&host->lock, flags); | |
1241 | ||
04cf585d | 1242 | mmc_detect_change(host->mmc, msecs_to_jiffies(200)); |
d129bceb PO |
1243 | } |
1244 | ||
1245 | static void sdhci_tasklet_finish(unsigned long param) | |
1246 | { | |
1247 | struct sdhci_host *host; | |
1248 | unsigned long flags; | |
1249 | struct mmc_request *mrq; | |
1250 | ||
1251 | host = (struct sdhci_host*)param; | |
1252 | ||
1253 | spin_lock_irqsave(&host->lock, flags); | |
1254 | ||
1255 | del_timer(&host->timer); | |
1256 | ||
1257 | mrq = host->mrq; | |
1258 | ||
d129bceb PO |
1259 | /* |
1260 | * The controller needs a reset of internal state machines | |
1261 | * upon error conditions. | |
1262 | */ | |
1e72859e PO |
1263 | if (!(host->flags & SDHCI_DEVICE_DEAD) && |
1264 | (mrq->cmd->error || | |
1265 | (mrq->data && (mrq->data->error || | |
1266 | (mrq->data->stop && mrq->data->stop->error))) || | |
1267 | (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { | |
645289dc PO |
1268 | |
1269 | /* Some controllers need this kick or reset won't work here */ | |
b8c86fc5 | 1270 | if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) { |
645289dc PO |
1271 | unsigned int clock; |
1272 | ||
1273 | /* This is to force an update */ | |
1274 | clock = host->clock; | |
1275 | host->clock = 0; | |
1276 | sdhci_set_clock(host, clock); | |
1277 | } | |
1278 | ||
1279 | /* Spec says we should do both at the same time, but Ricoh | |
1280 | controllers do not like that. */ | |
d129bceb PO |
1281 | sdhci_reset(host, SDHCI_RESET_CMD); |
1282 | sdhci_reset(host, SDHCI_RESET_DATA); | |
1283 | } | |
1284 | ||
1285 | host->mrq = NULL; | |
1286 | host->cmd = NULL; | |
1287 | host->data = NULL; | |
1288 | ||
f9134319 | 1289 | #ifndef SDHCI_USE_LEDS_CLASS |
d129bceb | 1290 | sdhci_deactivate_led(host); |
2f730fec | 1291 | #endif |
d129bceb | 1292 | |
5f25a66f | 1293 | mmiowb(); |
d129bceb PO |
1294 | spin_unlock_irqrestore(&host->lock, flags); |
1295 | ||
1296 | mmc_request_done(host->mmc, mrq); | |
1297 | } | |
1298 | ||
1299 | static void sdhci_timeout_timer(unsigned long data) | |
1300 | { | |
1301 | struct sdhci_host *host; | |
1302 | unsigned long flags; | |
1303 | ||
1304 | host = (struct sdhci_host*)data; | |
1305 | ||
1306 | spin_lock_irqsave(&host->lock, flags); | |
1307 | ||
1308 | if (host->mrq) { | |
acf1da45 PO |
1309 | printk(KERN_ERR "%s: Timeout waiting for hardware " |
1310 | "interrupt.\n", mmc_hostname(host->mmc)); | |
d129bceb PO |
1311 | sdhci_dumpregs(host); |
1312 | ||
1313 | if (host->data) { | |
17b0429d | 1314 | host->data->error = -ETIMEDOUT; |
d129bceb PO |
1315 | sdhci_finish_data(host); |
1316 | } else { | |
1317 | if (host->cmd) | |
17b0429d | 1318 | host->cmd->error = -ETIMEDOUT; |
d129bceb | 1319 | else |
17b0429d | 1320 | host->mrq->cmd->error = -ETIMEDOUT; |
d129bceb PO |
1321 | |
1322 | tasklet_schedule(&host->finish_tasklet); | |
1323 | } | |
1324 | } | |
1325 | ||
5f25a66f | 1326 | mmiowb(); |
d129bceb PO |
1327 | spin_unlock_irqrestore(&host->lock, flags); |
1328 | } | |
1329 | ||
1330 | /*****************************************************************************\ | |
1331 | * * | |
1332 | * Interrupt handling * | |
1333 | * * | |
1334 | \*****************************************************************************/ | |
1335 | ||
1336 | static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask) | |
1337 | { | |
1338 | BUG_ON(intmask == 0); | |
1339 | ||
1340 | if (!host->cmd) { | |
b67ac3f3 PO |
1341 | printk(KERN_ERR "%s: Got command interrupt 0x%08x even " |
1342 | "though no command operation was in progress.\n", | |
1343 | mmc_hostname(host->mmc), (unsigned)intmask); | |
d129bceb PO |
1344 | sdhci_dumpregs(host); |
1345 | return; | |
1346 | } | |
1347 | ||
43b58b36 | 1348 | if (intmask & SDHCI_INT_TIMEOUT) |
17b0429d PO |
1349 | host->cmd->error = -ETIMEDOUT; |
1350 | else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT | | |
1351 | SDHCI_INT_INDEX)) | |
1352 | host->cmd->error = -EILSEQ; | |
43b58b36 | 1353 | |
e809517f | 1354 | if (host->cmd->error) { |
d129bceb | 1355 | tasklet_schedule(&host->finish_tasklet); |
e809517f PO |
1356 | return; |
1357 | } | |
1358 | ||
1359 | /* | |
1360 | * The host can send and interrupt when the busy state has | |
1361 | * ended, allowing us to wait without wasting CPU cycles. | |
1362 | * Unfortunately this is overloaded on the "data complete" | |
1363 | * interrupt, so we need to take some care when handling | |
1364 | * it. | |
1365 | * | |
1366 | * Note: The 1.0 specification is a bit ambiguous about this | |
1367 | * feature so there might be some problems with older | |
1368 | * controllers. | |
1369 | */ | |
1370 | if (host->cmd->flags & MMC_RSP_BUSY) { | |
1371 | if (host->cmd->data) | |
1372 | DBG("Cannot wait for busy signal when also " | |
1373 | "doing a data transfer"); | |
f945405c | 1374 | else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)) |
e809517f | 1375 | return; |
f945405c BD |
1376 | |
1377 | /* The controller does not support the end-of-busy IRQ, | |
1378 | * fall through and take the SDHCI_INT_RESPONSE */ | |
e809517f PO |
1379 | } |
1380 | ||
1381 | if (intmask & SDHCI_INT_RESPONSE) | |
43b58b36 | 1382 | sdhci_finish_command(host); |
d129bceb PO |
1383 | } |
1384 | ||
6882a8c0 BD |
1385 | #ifdef DEBUG |
1386 | static void sdhci_show_adma_error(struct sdhci_host *host) | |
1387 | { | |
1388 | const char *name = mmc_hostname(host->mmc); | |
1389 | u8 *desc = host->adma_desc; | |
1390 | __le32 *dma; | |
1391 | __le16 *len; | |
1392 | u8 attr; | |
1393 | ||
1394 | sdhci_dumpregs(host); | |
1395 | ||
1396 | while (true) { | |
1397 | dma = (__le32 *)(desc + 4); | |
1398 | len = (__le16 *)(desc + 2); | |
1399 | attr = *desc; | |
1400 | ||
1401 | DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", | |
1402 | name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr); | |
1403 | ||
1404 | desc += 8; | |
1405 | ||
1406 | if (attr & 2) | |
1407 | break; | |
1408 | } | |
1409 | } | |
1410 | #else | |
1411 | static void sdhci_show_adma_error(struct sdhci_host *host) { } | |
1412 | #endif | |
1413 | ||
d129bceb PO |
1414 | static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) |
1415 | { | |
1416 | BUG_ON(intmask == 0); | |
1417 | ||
1418 | if (!host->data) { | |
1419 | /* | |
e809517f PO |
1420 | * The "data complete" interrupt is also used to |
1421 | * indicate that a busy state has ended. See comment | |
1422 | * above in sdhci_cmd_irq(). | |
d129bceb | 1423 | */ |
e809517f PO |
1424 | if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) { |
1425 | if (intmask & SDHCI_INT_DATA_END) { | |
1426 | sdhci_finish_command(host); | |
1427 | return; | |
1428 | } | |
1429 | } | |
d129bceb | 1430 | |
b67ac3f3 PO |
1431 | printk(KERN_ERR "%s: Got data interrupt 0x%08x even " |
1432 | "though no data operation was in progress.\n", | |
1433 | mmc_hostname(host->mmc), (unsigned)intmask); | |
d129bceb PO |
1434 | sdhci_dumpregs(host); |
1435 | ||
1436 | return; | |
1437 | } | |
1438 | ||
1439 | if (intmask & SDHCI_INT_DATA_TIMEOUT) | |
17b0429d PO |
1440 | host->data->error = -ETIMEDOUT; |
1441 | else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) | |
1442 | host->data->error = -EILSEQ; | |
6882a8c0 BD |
1443 | else if (intmask & SDHCI_INT_ADMA_ERROR) { |
1444 | printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc)); | |
1445 | sdhci_show_adma_error(host); | |
2134a922 | 1446 | host->data->error = -EIO; |
6882a8c0 | 1447 | } |
d129bceb | 1448 | |
17b0429d | 1449 | if (host->data->error) |
d129bceb PO |
1450 | sdhci_finish_data(host); |
1451 | else { | |
a406f5a3 | 1452 | if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) |
d129bceb PO |
1453 | sdhci_transfer_pio(host); |
1454 | ||
6ba736a1 PO |
1455 | /* |
1456 | * We currently don't do anything fancy with DMA | |
1457 | * boundaries, but as we can't disable the feature | |
1458 | * we need to at least restart the transfer. | |
1459 | */ | |
1460 | if (intmask & SDHCI_INT_DMA_END) | |
4e4141a5 AV |
1461 | sdhci_writel(host, sdhci_readl(host, SDHCI_DMA_ADDRESS), |
1462 | SDHCI_DMA_ADDRESS); | |
6ba736a1 | 1463 | |
e538fbe8 PO |
1464 | if (intmask & SDHCI_INT_DATA_END) { |
1465 | if (host->cmd) { | |
1466 | /* | |
1467 | * Data managed to finish before the | |
1468 | * command completed. Make sure we do | |
1469 | * things in the proper order. | |
1470 | */ | |
1471 | host->data_early = 1; | |
1472 | } else { | |
1473 | sdhci_finish_data(host); | |
1474 | } | |
1475 | } | |
d129bceb PO |
1476 | } |
1477 | } | |
1478 | ||
7d12e780 | 1479 | static irqreturn_t sdhci_irq(int irq, void *dev_id) |
d129bceb PO |
1480 | { |
1481 | irqreturn_t result; | |
1482 | struct sdhci_host* host = dev_id; | |
1483 | u32 intmask; | |
f75979b7 | 1484 | int cardint = 0; |
d129bceb PO |
1485 | |
1486 | spin_lock(&host->lock); | |
1487 | ||
4e4141a5 | 1488 | intmask = sdhci_readl(host, SDHCI_INT_STATUS); |
d129bceb | 1489 | |
62df67a5 | 1490 | if (!intmask || intmask == 0xffffffff) { |
d129bceb PO |
1491 | result = IRQ_NONE; |
1492 | goto out; | |
1493 | } | |
1494 | ||
b69c9058 PO |
1495 | DBG("*** %s got interrupt: 0x%08x\n", |
1496 | mmc_hostname(host->mmc), intmask); | |
d129bceb | 1497 | |
3192a28f | 1498 | if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { |
4e4141a5 AV |
1499 | sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | |
1500 | SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); | |
d129bceb | 1501 | tasklet_schedule(&host->card_tasklet); |
3192a28f | 1502 | } |
d129bceb | 1503 | |
3192a28f | 1504 | intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); |
d129bceb | 1505 | |
3192a28f | 1506 | if (intmask & SDHCI_INT_CMD_MASK) { |
4e4141a5 AV |
1507 | sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK, |
1508 | SDHCI_INT_STATUS); | |
3192a28f | 1509 | sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); |
d129bceb PO |
1510 | } |
1511 | ||
1512 | if (intmask & SDHCI_INT_DATA_MASK) { | |
4e4141a5 AV |
1513 | sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK, |
1514 | SDHCI_INT_STATUS); | |
3192a28f | 1515 | sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); |
d129bceb PO |
1516 | } |
1517 | ||
1518 | intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); | |
1519 | ||
964f9ce2 PO |
1520 | intmask &= ~SDHCI_INT_ERROR; |
1521 | ||
d129bceb | 1522 | if (intmask & SDHCI_INT_BUS_POWER) { |
3192a28f | 1523 | printk(KERN_ERR "%s: Card is consuming too much power!\n", |
d129bceb | 1524 | mmc_hostname(host->mmc)); |
4e4141a5 | 1525 | sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS); |
d129bceb PO |
1526 | } |
1527 | ||
9d26a5d3 | 1528 | intmask &= ~SDHCI_INT_BUS_POWER; |
3192a28f | 1529 | |
f75979b7 PO |
1530 | if (intmask & SDHCI_INT_CARD_INT) |
1531 | cardint = 1; | |
1532 | ||
1533 | intmask &= ~SDHCI_INT_CARD_INT; | |
1534 | ||
3192a28f | 1535 | if (intmask) { |
acf1da45 | 1536 | printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n", |
3192a28f | 1537 | mmc_hostname(host->mmc), intmask); |
d129bceb PO |
1538 | sdhci_dumpregs(host); |
1539 | ||
4e4141a5 | 1540 | sdhci_writel(host, intmask, SDHCI_INT_STATUS); |
3192a28f | 1541 | } |
d129bceb PO |
1542 | |
1543 | result = IRQ_HANDLED; | |
1544 | ||
5f25a66f | 1545 | mmiowb(); |
d129bceb PO |
1546 | out: |
1547 | spin_unlock(&host->lock); | |
1548 | ||
f75979b7 PO |
1549 | /* |
1550 | * We have to delay this as it calls back into the driver. | |
1551 | */ | |
1552 | if (cardint) | |
1553 | mmc_signal_sdio_irq(host->mmc); | |
1554 | ||
d129bceb PO |
1555 | return result; |
1556 | } | |
1557 | ||
1558 | /*****************************************************************************\ | |
1559 | * * | |
1560 | * Suspend/resume * | |
1561 | * * | |
1562 | \*****************************************************************************/ | |
1563 | ||
1564 | #ifdef CONFIG_PM | |
1565 | ||
b8c86fc5 | 1566 | int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state) |
d129bceb | 1567 | { |
b8c86fc5 | 1568 | int ret; |
a715dfc7 | 1569 | |
7260cf5e AV |
1570 | sdhci_disable_card_detection(host); |
1571 | ||
b8c86fc5 PO |
1572 | ret = mmc_suspend_host(host->mmc, state); |
1573 | if (ret) | |
1574 | return ret; | |
a715dfc7 | 1575 | |
b8c86fc5 | 1576 | free_irq(host->irq, host); |
d129bceb PO |
1577 | |
1578 | return 0; | |
1579 | } | |
1580 | ||
b8c86fc5 | 1581 | EXPORT_SYMBOL_GPL(sdhci_suspend_host); |
d129bceb | 1582 | |
b8c86fc5 PO |
1583 | int sdhci_resume_host(struct sdhci_host *host) |
1584 | { | |
1585 | int ret; | |
d129bceb | 1586 | |
b8c86fc5 PO |
1587 | if (host->flags & SDHCI_USE_DMA) { |
1588 | if (host->ops->enable_dma) | |
1589 | host->ops->enable_dma(host); | |
1590 | } | |
d129bceb | 1591 | |
b8c86fc5 PO |
1592 | ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, |
1593 | mmc_hostname(host->mmc), host); | |
df1c4b7b PO |
1594 | if (ret) |
1595 | return ret; | |
d129bceb | 1596 | |
b8c86fc5 PO |
1597 | sdhci_init(host); |
1598 | mmiowb(); | |
1599 | ||
1600 | ret = mmc_resume_host(host->mmc); | |
1601 | if (ret) | |
1602 | return ret; | |
d129bceb | 1603 | |
7260cf5e AV |
1604 | sdhci_enable_card_detection(host); |
1605 | ||
d129bceb PO |
1606 | return 0; |
1607 | } | |
1608 | ||
b8c86fc5 | 1609 | EXPORT_SYMBOL_GPL(sdhci_resume_host); |
d129bceb PO |
1610 | |
1611 | #endif /* CONFIG_PM */ | |
1612 | ||
1613 | /*****************************************************************************\ | |
1614 | * * | |
b8c86fc5 | 1615 | * Device allocation/registration * |
d129bceb PO |
1616 | * * |
1617 | \*****************************************************************************/ | |
1618 | ||
b8c86fc5 PO |
1619 | struct sdhci_host *sdhci_alloc_host(struct device *dev, |
1620 | size_t priv_size) | |
d129bceb | 1621 | { |
d129bceb PO |
1622 | struct mmc_host *mmc; |
1623 | struct sdhci_host *host; | |
1624 | ||
b8c86fc5 | 1625 | WARN_ON(dev == NULL); |
d129bceb | 1626 | |
b8c86fc5 | 1627 | mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); |
d129bceb | 1628 | if (!mmc) |
b8c86fc5 | 1629 | return ERR_PTR(-ENOMEM); |
d129bceb PO |
1630 | |
1631 | host = mmc_priv(mmc); | |
1632 | host->mmc = mmc; | |
1633 | ||
b8c86fc5 PO |
1634 | return host; |
1635 | } | |
8a4da143 | 1636 | |
b8c86fc5 | 1637 | EXPORT_SYMBOL_GPL(sdhci_alloc_host); |
d129bceb | 1638 | |
b8c86fc5 PO |
1639 | int sdhci_add_host(struct sdhci_host *host) |
1640 | { | |
1641 | struct mmc_host *mmc; | |
1642 | unsigned int caps; | |
b8c86fc5 | 1643 | int ret; |
d129bceb | 1644 | |
b8c86fc5 PO |
1645 | WARN_ON(host == NULL); |
1646 | if (host == NULL) | |
1647 | return -EINVAL; | |
d129bceb | 1648 | |
b8c86fc5 | 1649 | mmc = host->mmc; |
d129bceb | 1650 | |
b8c86fc5 PO |
1651 | if (debug_quirks) |
1652 | host->quirks = debug_quirks; | |
d129bceb | 1653 | |
d96649ed PO |
1654 | sdhci_reset(host, SDHCI_RESET_ALL); |
1655 | ||
4e4141a5 | 1656 | host->version = sdhci_readw(host, SDHCI_HOST_VERSION); |
2134a922 PO |
1657 | host->version = (host->version & SDHCI_SPEC_VER_MASK) |
1658 | >> SDHCI_SPEC_VER_SHIFT; | |
1659 | if (host->version > SDHCI_SPEC_200) { | |
4a965505 | 1660 | printk(KERN_ERR "%s: Unknown controller version (%d). " |
b69c9058 | 1661 | "You may experience problems.\n", mmc_hostname(mmc), |
2134a922 | 1662 | host->version); |
4a965505 PO |
1663 | } |
1664 | ||
4e4141a5 | 1665 | caps = sdhci_readl(host, SDHCI_CAPABILITIES); |
d129bceb | 1666 | |
b8c86fc5 | 1667 | if (host->quirks & SDHCI_QUIRK_FORCE_DMA) |
98608076 | 1668 | host->flags |= SDHCI_USE_DMA; |
67435274 PO |
1669 | else if (!(caps & SDHCI_CAN_DO_DMA)) |
1670 | DBG("Controller doesn't have DMA capability\n"); | |
1671 | else | |
d129bceb PO |
1672 | host->flags |= SDHCI_USE_DMA; |
1673 | ||
b8c86fc5 | 1674 | if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && |
7c168e3d | 1675 | (host->flags & SDHCI_USE_DMA)) { |
cee687ce | 1676 | DBG("Disabling DMA as it is marked broken\n"); |
7c168e3d FT |
1677 | host->flags &= ~SDHCI_USE_DMA; |
1678 | } | |
1679 | ||
2134a922 PO |
1680 | if (host->flags & SDHCI_USE_DMA) { |
1681 | if ((host->version >= SDHCI_SPEC_200) && | |
1682 | (caps & SDHCI_CAN_DO_ADMA2)) | |
1683 | host->flags |= SDHCI_USE_ADMA; | |
1684 | } | |
1685 | ||
1686 | if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && | |
1687 | (host->flags & SDHCI_USE_ADMA)) { | |
1688 | DBG("Disabling ADMA as it is marked broken\n"); | |
1689 | host->flags &= ~SDHCI_USE_ADMA; | |
1690 | } | |
1691 | ||
d129bceb | 1692 | if (host->flags & SDHCI_USE_DMA) { |
b8c86fc5 PO |
1693 | if (host->ops->enable_dma) { |
1694 | if (host->ops->enable_dma(host)) { | |
1695 | printk(KERN_WARNING "%s: No suitable DMA " | |
1696 | "available. Falling back to PIO.\n", | |
1697 | mmc_hostname(mmc)); | |
2134a922 | 1698 | host->flags &= ~(SDHCI_USE_DMA | SDHCI_USE_ADMA); |
b8c86fc5 | 1699 | } |
d129bceb PO |
1700 | } |
1701 | } | |
1702 | ||
2134a922 PO |
1703 | if (host->flags & SDHCI_USE_ADMA) { |
1704 | /* | |
1705 | * We need to allocate descriptors for all sg entries | |
1706 | * (128) and potentially one alignment transfer for | |
1707 | * each of those entries. | |
1708 | */ | |
1709 | host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL); | |
1710 | host->align_buffer = kmalloc(128 * 4, GFP_KERNEL); | |
1711 | if (!host->adma_desc || !host->align_buffer) { | |
1712 | kfree(host->adma_desc); | |
1713 | kfree(host->align_buffer); | |
1714 | printk(KERN_WARNING "%s: Unable to allocate ADMA " | |
1715 | "buffers. Falling back to standard DMA.\n", | |
1716 | mmc_hostname(mmc)); | |
1717 | host->flags &= ~SDHCI_USE_ADMA; | |
1718 | } | |
1719 | } | |
1720 | ||
7659150c PO |
1721 | /* |
1722 | * If we use DMA, then it's up to the caller to set the DMA | |
1723 | * mask, but PIO does not need the hw shim so we set a new | |
1724 | * mask here in that case. | |
1725 | */ | |
1726 | if (!(host->flags & SDHCI_USE_DMA)) { | |
1727 | host->dma_mask = DMA_BIT_MASK(64); | |
1728 | mmc_dev(host->mmc)->dma_mask = &host->dma_mask; | |
1729 | } | |
d129bceb | 1730 | |
8ef1a143 PO |
1731 | host->max_clk = |
1732 | (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; | |
4240ff0a | 1733 | host->max_clk *= 1000000; |
8ef1a143 | 1734 | if (host->max_clk == 0) { |
4240ff0a BD |
1735 | if (!host->ops->get_max_clock) { |
1736 | printk(KERN_ERR | |
1737 | "%s: Hardware doesn't specify base clock " | |
1738 | "frequency.\n", mmc_hostname(mmc)); | |
1739 | return -ENODEV; | |
1740 | } | |
1741 | host->max_clk = host->ops->get_max_clock(host); | |
8ef1a143 | 1742 | } |
d129bceb | 1743 | |
1c8cde92 PO |
1744 | host->timeout_clk = |
1745 | (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; | |
1746 | if (host->timeout_clk == 0) { | |
4240ff0a BD |
1747 | if (!host->ops->get_timeout_clock) { |
1748 | printk(KERN_ERR | |
1749 | "%s: Hardware doesn't specify timeout clock " | |
1750 | "frequency.\n", mmc_hostname(mmc)); | |
1751 | return -ENODEV; | |
1752 | } | |
1753 | host->timeout_clk = host->ops->get_timeout_clock(host); | |
1c8cde92 PO |
1754 | } |
1755 | if (caps & SDHCI_TIMEOUT_CLK_UNIT) | |
1756 | host->timeout_clk *= 1000; | |
d129bceb PO |
1757 | |
1758 | /* | |
1759 | * Set host parameters. | |
1760 | */ | |
1761 | mmc->ops = &sdhci_ops; | |
1762 | mmc->f_min = host->max_clk / 256; | |
1763 | mmc->f_max = host->max_clk; | |
5fe23c7f AV |
1764 | mmc->caps = MMC_CAP_SDIO_IRQ; |
1765 | ||
1766 | if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) | |
1767 | mmc->caps |= MMC_CAP_4_BIT_DATA; | |
d129bceb | 1768 | |
86a6a874 | 1769 | if (caps & SDHCI_CAN_DO_HISPD) |
cd9277c0 PO |
1770 | mmc->caps |= MMC_CAP_SD_HIGHSPEED; |
1771 | ||
68d1fb7e AV |
1772 | if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) |
1773 | mmc->caps |= MMC_CAP_NEEDS_POLL; | |
1774 | ||
146ad66e PO |
1775 | mmc->ocr_avail = 0; |
1776 | if (caps & SDHCI_CAN_VDD_330) | |
1777 | mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34; | |
c70840e8 | 1778 | if (caps & SDHCI_CAN_VDD_300) |
146ad66e | 1779 | mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31; |
c70840e8 | 1780 | if (caps & SDHCI_CAN_VDD_180) |
55556da0 | 1781 | mmc->ocr_avail |= MMC_VDD_165_195; |
146ad66e PO |
1782 | |
1783 | if (mmc->ocr_avail == 0) { | |
1784 | printk(KERN_ERR "%s: Hardware doesn't report any " | |
b69c9058 | 1785 | "support voltages.\n", mmc_hostname(mmc)); |
b8c86fc5 | 1786 | return -ENODEV; |
146ad66e PO |
1787 | } |
1788 | ||
d129bceb PO |
1789 | spin_lock_init(&host->lock); |
1790 | ||
1791 | /* | |
2134a922 PO |
1792 | * Maximum number of segments. Depends on if the hardware |
1793 | * can do scatter/gather or not. | |
d129bceb | 1794 | */ |
2134a922 PO |
1795 | if (host->flags & SDHCI_USE_ADMA) |
1796 | mmc->max_hw_segs = 128; | |
1797 | else if (host->flags & SDHCI_USE_DMA) | |
d129bceb | 1798 | mmc->max_hw_segs = 1; |
2134a922 PO |
1799 | else /* PIO */ |
1800 | mmc->max_hw_segs = 128; | |
1801 | mmc->max_phys_segs = 128; | |
d129bceb PO |
1802 | |
1803 | /* | |
bab76961 | 1804 | * Maximum number of sectors in one transfer. Limited by DMA boundary |
55db890a | 1805 | * size (512KiB). |
d129bceb | 1806 | */ |
55db890a | 1807 | mmc->max_req_size = 524288; |
d129bceb PO |
1808 | |
1809 | /* | |
1810 | * Maximum segment size. Could be one segment with the maximum number | |
2134a922 PO |
1811 | * of bytes. When doing hardware scatter/gather, each entry cannot |
1812 | * be larger than 64 KiB though. | |
d129bceb | 1813 | */ |
2134a922 PO |
1814 | if (host->flags & SDHCI_USE_ADMA) |
1815 | mmc->max_seg_size = 65536; | |
1816 | else | |
1817 | mmc->max_seg_size = mmc->max_req_size; | |
d129bceb | 1818 | |
fe4a3c7a PO |
1819 | /* |
1820 | * Maximum block size. This varies from controller to controller and | |
1821 | * is specified in the capabilities register. | |
1822 | */ | |
0633f654 AV |
1823 | if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { |
1824 | mmc->max_blk_size = 2; | |
1825 | } else { | |
1826 | mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> | |
1827 | SDHCI_MAX_BLOCK_SHIFT; | |
1828 | if (mmc->max_blk_size >= 3) { | |
1829 | printk(KERN_WARNING "%s: Invalid maximum block size, " | |
1830 | "assuming 512 bytes\n", mmc_hostname(mmc)); | |
1831 | mmc->max_blk_size = 0; | |
1832 | } | |
1833 | } | |
1834 | ||
1835 | mmc->max_blk_size = 512 << mmc->max_blk_size; | |
fe4a3c7a | 1836 | |
55db890a PO |
1837 | /* |
1838 | * Maximum block count. | |
1839 | */ | |
1388eefd | 1840 | mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; |
55db890a | 1841 | |
d129bceb PO |
1842 | /* |
1843 | * Init tasklets. | |
1844 | */ | |
1845 | tasklet_init(&host->card_tasklet, | |
1846 | sdhci_tasklet_card, (unsigned long)host); | |
1847 | tasklet_init(&host->finish_tasklet, | |
1848 | sdhci_tasklet_finish, (unsigned long)host); | |
1849 | ||
e4cad1b5 | 1850 | setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); |
d129bceb | 1851 | |
dace1453 | 1852 | ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, |
b69c9058 | 1853 | mmc_hostname(mmc), host); |
d129bceb | 1854 | if (ret) |
8ef1a143 | 1855 | goto untasklet; |
d129bceb PO |
1856 | |
1857 | sdhci_init(host); | |
1858 | ||
1859 | #ifdef CONFIG_MMC_DEBUG | |
1860 | sdhci_dumpregs(host); | |
1861 | #endif | |
1862 | ||
f9134319 | 1863 | #ifdef SDHCI_USE_LEDS_CLASS |
5dbace0c HS |
1864 | snprintf(host->led_name, sizeof(host->led_name), |
1865 | "%s::", mmc_hostname(mmc)); | |
1866 | host->led.name = host->led_name; | |
2f730fec PO |
1867 | host->led.brightness = LED_OFF; |
1868 | host->led.default_trigger = mmc_hostname(mmc); | |
1869 | host->led.brightness_set = sdhci_led_control; | |
1870 | ||
b8c86fc5 | 1871 | ret = led_classdev_register(mmc_dev(mmc), &host->led); |
2f730fec PO |
1872 | if (ret) |
1873 | goto reset; | |
1874 | #endif | |
1875 | ||
5f25a66f PO |
1876 | mmiowb(); |
1877 | ||
d129bceb PO |
1878 | mmc_add_host(mmc); |
1879 | ||
2134a922 | 1880 | printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s%s\n", |
d1b26863 | 1881 | mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), |
2134a922 | 1882 | (host->flags & SDHCI_USE_ADMA)?"A":"", |
d129bceb PO |
1883 | (host->flags & SDHCI_USE_DMA)?"DMA":"PIO"); |
1884 | ||
7260cf5e AV |
1885 | sdhci_enable_card_detection(host); |
1886 | ||
d129bceb PO |
1887 | return 0; |
1888 | ||
f9134319 | 1889 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec PO |
1890 | reset: |
1891 | sdhci_reset(host, SDHCI_RESET_ALL); | |
1892 | free_irq(host->irq, host); | |
1893 | #endif | |
8ef1a143 | 1894 | untasklet: |
d129bceb PO |
1895 | tasklet_kill(&host->card_tasklet); |
1896 | tasklet_kill(&host->finish_tasklet); | |
d129bceb PO |
1897 | |
1898 | return ret; | |
1899 | } | |
1900 | ||
b8c86fc5 | 1901 | EXPORT_SYMBOL_GPL(sdhci_add_host); |
d129bceb | 1902 | |
1e72859e | 1903 | void sdhci_remove_host(struct sdhci_host *host, int dead) |
b8c86fc5 | 1904 | { |
1e72859e PO |
1905 | unsigned long flags; |
1906 | ||
1907 | if (dead) { | |
1908 | spin_lock_irqsave(&host->lock, flags); | |
1909 | ||
1910 | host->flags |= SDHCI_DEVICE_DEAD; | |
1911 | ||
1912 | if (host->mrq) { | |
1913 | printk(KERN_ERR "%s: Controller removed during " | |
1914 | " transfer!\n", mmc_hostname(host->mmc)); | |
1915 | ||
1916 | host->mrq->cmd->error = -ENOMEDIUM; | |
1917 | tasklet_schedule(&host->finish_tasklet); | |
1918 | } | |
1919 | ||
1920 | spin_unlock_irqrestore(&host->lock, flags); | |
1921 | } | |
1922 | ||
7260cf5e AV |
1923 | sdhci_disable_card_detection(host); |
1924 | ||
b8c86fc5 | 1925 | mmc_remove_host(host->mmc); |
d129bceb | 1926 | |
f9134319 | 1927 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec PO |
1928 | led_classdev_unregister(&host->led); |
1929 | #endif | |
1930 | ||
1e72859e PO |
1931 | if (!dead) |
1932 | sdhci_reset(host, SDHCI_RESET_ALL); | |
d129bceb PO |
1933 | |
1934 | free_irq(host->irq, host); | |
1935 | ||
1936 | del_timer_sync(&host->timer); | |
1937 | ||
1938 | tasklet_kill(&host->card_tasklet); | |
1939 | tasklet_kill(&host->finish_tasklet); | |
2134a922 PO |
1940 | |
1941 | kfree(host->adma_desc); | |
1942 | kfree(host->align_buffer); | |
1943 | ||
1944 | host->adma_desc = NULL; | |
1945 | host->align_buffer = NULL; | |
d129bceb PO |
1946 | } |
1947 | ||
b8c86fc5 | 1948 | EXPORT_SYMBOL_GPL(sdhci_remove_host); |
d129bceb | 1949 | |
b8c86fc5 | 1950 | void sdhci_free_host(struct sdhci_host *host) |
d129bceb | 1951 | { |
b8c86fc5 | 1952 | mmc_free_host(host->mmc); |
d129bceb PO |
1953 | } |
1954 | ||
b8c86fc5 | 1955 | EXPORT_SYMBOL_GPL(sdhci_free_host); |
d129bceb PO |
1956 | |
1957 | /*****************************************************************************\ | |
1958 | * * | |
1959 | * Driver init/exit * | |
1960 | * * | |
1961 | \*****************************************************************************/ | |
1962 | ||
1963 | static int __init sdhci_drv_init(void) | |
1964 | { | |
1965 | printk(KERN_INFO DRIVER_NAME | |
52fbf9c9 | 1966 | ": Secure Digital Host Controller Interface driver\n"); |
d129bceb PO |
1967 | printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); |
1968 | ||
b8c86fc5 | 1969 | return 0; |
d129bceb PO |
1970 | } |
1971 | ||
1972 | static void __exit sdhci_drv_exit(void) | |
1973 | { | |
d129bceb PO |
1974 | } |
1975 | ||
1976 | module_init(sdhci_drv_init); | |
1977 | module_exit(sdhci_drv_exit); | |
1978 | ||
df673b22 | 1979 | module_param(debug_quirks, uint, 0444); |
67435274 | 1980 | |
32710e8f | 1981 | MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); |
b8c86fc5 | 1982 | MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); |
d129bceb | 1983 | MODULE_LICENSE("GPL"); |
67435274 | 1984 | |
df673b22 | 1985 | MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); |