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sdhci-pci: don't penalize newer jmicron chips
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
d129bceb 19#include <linux/dma-mapping.h>
11763609 20#include <linux/scatterlist.h>
d129bceb 21
2f730fec
PO		 22#include <linux/leds.h>
23
d129bceb 24#include <linux/mmc/host.h>
d129bceb 25
d129bceb
PO		 26#include "sdhci.h"
27
28#define DRIVER_NAME "sdhci"
d129bceb 29
d129bceb 30#define DBG(f, x...) \
c6563178 31 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 32
df673b22 33static unsigned int debug_quirks = 0;
67435274 34
d129bceb
PO		 35static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
36static void sdhci_finish_data(struct sdhci_host *);
37
38static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
39static void sdhci_finish_command(struct sdhci_host *);
40
41static void sdhci_dumpregs(struct sdhci_host *host)
42{
43 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
44
45 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
46 readl(host->ioaddr + SDHCI_DMA_ADDRESS),
47 readw(host->ioaddr + SDHCI_HOST_VERSION));
48 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
49 readw(host->ioaddr + SDHCI_BLOCK_SIZE),
50 readw(host->ioaddr + SDHCI_BLOCK_COUNT));
51 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
52 readl(host->ioaddr + SDHCI_ARGUMENT),
53 readw(host->ioaddr + SDHCI_TRANSFER_MODE));
54 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
55 readl(host->ioaddr + SDHCI_PRESENT_STATE),
56 readb(host->ioaddr + SDHCI_HOST_CONTROL));
57 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
58 readb(host->ioaddr + SDHCI_POWER_CONTROL),
59 readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
60 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
2df3b71b 61 readb(host->ioaddr + SDHCI_WAKE_UP_CONTROL),
d129bceb
PO		 62 readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
63 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
64 readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
65 readl(host->ioaddr + SDHCI_INT_STATUS));
66 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
67 readl(host->ioaddr + SDHCI_INT_ENABLE),
68 readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
69 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
70 readw(host->ioaddr + SDHCI_ACMD12_ERR),
71 readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
72 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
73 readl(host->ioaddr + SDHCI_CAPABILITIES),
74 readl(host->ioaddr + SDHCI_MAX_CURRENT));
75
76 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
77}
78
79/*****************************************************************************\
80 * *
81 * Low level functions *
82 * *
83\*****************************************************************************/
84
85static void sdhci_reset(struct sdhci_host *host, u8 mask)
86{
e16514d8
PO		 87 unsigned long timeout;
88
b8c86fc5 89 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
8a4da143
PO		 90 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
91 SDHCI_CARD_PRESENT))
92 return;
93 }
94
d129bceb
PO		 95 writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
96
e16514d8 97 if (mask & SDHCI_RESET_ALL)
d129bceb
PO		 98 host->clock = 0;
99
e16514d8
PO		 100 /* Wait max 100 ms */
101 timeout = 100;
102
103 /* hw clears the bit when it's done */
104 while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
105 if (timeout == 0) {
acf1da45 106 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
e16514d8
PO		 107 mmc_hostname(host->mmc), (int)mask);
108 sdhci_dumpregs(host);
109 return;
110 }
111 timeout--;
112 mdelay(1);
d129bceb
PO		 113 }
114}
115
116static void sdhci_init(struct sdhci_host *host)
117{
118 u32 intmask;
119
120 sdhci_reset(host, SDHCI_RESET_ALL);
121
3192a28f
PO		 122 intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
123 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
124 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
125 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
a406f5a3 126 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
3192a28f 127 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
d129bceb
PO		 128
129 writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
130 writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 131}
132
133static void sdhci_activate_led(struct sdhci_host *host)
134{
135 u8 ctrl;
136
137 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
138 ctrl |= SDHCI_CTRL_LED;
139 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
140}
141
142static void sdhci_deactivate_led(struct sdhci_host *host)
143{
144 u8 ctrl;
145
146 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
147 ctrl &= ~SDHCI_CTRL_LED;
148 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
149}
150
2f730fec
PO		 151#ifdef CONFIG_LEDS_CLASS
152static void sdhci_led_control(struct led_classdev *led,
153 enum led_brightness brightness)
154{
155 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
156 unsigned long flags;
157
158 spin_lock_irqsave(&host->lock, flags);
159
160 if (brightness == LED_OFF)
161 sdhci_deactivate_led(host);
162 else
163 sdhci_activate_led(host);
164
165 spin_unlock_irqrestore(&host->lock, flags);
166}
167#endif
168
d129bceb
PO		 169/*****************************************************************************\
170 * *
171 * Core functions *
172 * *
173\*****************************************************************************/
174
2a22b14e 175static inline char* sdhci_sg_to_buffer(struct sdhci_host* host)
d129bceb 176{
45711f1a 177 return sg_virt(host->cur_sg);
d129bceb
PO		 178}
179
180static inline int sdhci_next_sg(struct sdhci_host* host)
181{
182 /*
183 * Skip to next SG entry.
184 */
185 host->cur_sg++;
186 host->num_sg--;
187
188 /*
189 * Any entries left?
190 */
191 if (host->num_sg > 0) {
192 host->offset = 0;
193 host->remain = host->cur_sg->length;
194 }
195
196 return host->num_sg;
197}
198
a406f5a3 199static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 200{
a406f5a3
PO		 201 int blksize, chunk_remain;
202 u32 data;
d129bceb 203 char *buffer;
a406f5a3 204 int size;
d129bceb 205
a406f5a3 206 DBG("PIO reading\n");
d129bceb 207
a406f5a3
PO		 208 blksize = host->data->blksz;
209 chunk_remain = 0;
210 data = 0;
d129bceb 211
2a22b14e 212 buffer = sdhci_sg_to_buffer(host) + host->offset;
d129bceb 213
a406f5a3
PO		 214 while (blksize) {
215 if (chunk_remain == 0) {
216 data = readl(host->ioaddr + SDHCI_BUFFER);
217 chunk_remain = min(blksize, 4);
218 }
d129bceb 219
14d836e7 220 size = min(host->remain, chunk_remain);
d129bceb 221
a406f5a3
PO		 222 chunk_remain -= size;
223 blksize -= size;
224 host->offset += size;
225 host->remain -= size;
14d836e7 226
a406f5a3
PO		 227 while (size) {
228 *buffer = data & 0xFF;
229 buffer++;
230 data >>= 8;
231 size--;
232 }
d129bceb 233
a406f5a3 234 if (host->remain == 0) {
a406f5a3
PO		 235 if (sdhci_next_sg(host) == 0) {
236 BUG_ON(blksize != 0);
237 return;
238 }
2a22b14e 239 buffer = sdhci_sg_to_buffer(host);
d129bceb 240 }
a406f5a3 241 }
a406f5a3 242}
d129bceb 243
a406f5a3
PO		 244static void sdhci_write_block_pio(struct sdhci_host *host)
245{
246 int blksize, chunk_remain;
247 u32 data;
248 char *buffer;
249 int bytes, size;
d129bceb 250
a406f5a3
PO		 251 DBG("PIO writing\n");
252
253 blksize = host->data->blksz;
254 chunk_remain = 4;
255 data = 0;
d129bceb 256
a406f5a3 257 bytes = 0;
2a22b14e 258 buffer = sdhci_sg_to_buffer(host) + host->offset;
d129bceb 259
a406f5a3 260 while (blksize) {
14d836e7 261 size = min(host->remain, chunk_remain);
a406f5a3
PO		 262
263 chunk_remain -= size;
264 blksize -= size;
d129bceb
PO		 265 host->offset += size;
266 host->remain -= size;
14d836e7 267
a406f5a3
PO		 268 while (size) {
269 data >>= 8;
270 data |= (u32)*buffer << 24;
271 buffer++;
272 size--;
273 }
274
275 if (chunk_remain == 0) {
276 writel(data, host->ioaddr + SDHCI_BUFFER);
277 chunk_remain = min(blksize, 4);
278 }
d129bceb
PO		 279
280 if (host->remain == 0) {
d129bceb 281 if (sdhci_next_sg(host) == 0) {
a406f5a3 282 BUG_ON(blksize != 0);
d129bceb
PO		 283 return;
284 }
2a22b14e 285 buffer = sdhci_sg_to_buffer(host);
d129bceb
PO		 286 }
287 }
a406f5a3
PO		 288}
289
290static void sdhci_transfer_pio(struct sdhci_host *host)
291{
292 u32 mask;
293
294 BUG_ON(!host->data);
295
14d836e7 296 if (host->num_sg == 0)
a406f5a3
PO		 297 return;
298
299 if (host->data->flags & MMC_DATA_READ)
300 mask = SDHCI_DATA_AVAILABLE;
301 else
302 mask = SDHCI_SPACE_AVAILABLE;
303
304 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
305 if (host->data->flags & MMC_DATA_READ)
306 sdhci_read_block_pio(host);
307 else
308 sdhci_write_block_pio(host);
d129bceb 309
14d836e7 310 if (host->num_sg == 0)
a406f5a3 311 break;
a406f5a3 312 }
d129bceb 313
a406f5a3 314 DBG("PIO transfer complete.\n");
d129bceb
PO		 315}
316
ee53ab5d 317static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
d129bceb 318{
1c8cde92
PO		 319 u8 count;
320 unsigned target_timeout, current_timeout;
d129bceb 321
ee53ab5d
PO		 322 /*
323 * If the host controller provides us with an incorrect timeout
324 * value, just skip the check and use 0xE. The hardware may take
325 * longer to time out, but that's much better than having a too-short
326 * timeout value.
327 */
328 if ((host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL))
329 return 0xE;
e538fbe8 330
1c8cde92
PO		 331 /* timeout in us */
332 target_timeout = data->timeout_ns / 1000 +
333 data->timeout_clks / host->clock;
d129bceb 334
1c8cde92
PO		 335 /*
336 * Figure out needed cycles.
337 * We do this in steps in order to fit inside a 32 bit int.
338 * The first step is the minimum timeout, which will have a
339 * minimum resolution of 6 bits:
340 * (1) 2^13*1000 > 2^22,
341 * (2) host->timeout_clk < 2^16
342 * =>
343 * (1) / (2) > 2^6
344 */
345 count = 0;
346 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
347 while (current_timeout < target_timeout) {
348 count++;
349 current_timeout <<= 1;
350 if (count >= 0xF)
351 break;
352 }
353
354 if (count >= 0xF) {
355 printk(KERN_WARNING "%s: Too large timeout requested!\n",
356 mmc_hostname(host->mmc));
357 count = 0xE;
358 }
359
ee53ab5d
PO		 360 return count;
361}
362
363static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
364{
365 u8 count;
366
367 WARN_ON(host->data);
368
369 if (data == NULL)
370 return;
371
372 /* Sanity checks */
373 BUG_ON(data->blksz * data->blocks > 524288);
374 BUG_ON(data->blksz > host->mmc->max_blk_size);
375 BUG_ON(data->blocks > 65535);
376
377 host->data = data;
378 host->data_early = 0;
379
380 count = sdhci_calc_timeout(host, data);
1c8cde92 381 writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
d129bceb 382
c9fddbc4
PO		 383 if (host->flags & SDHCI_USE_DMA)
384 host->flags |= SDHCI_REQ_USE_DMA;
385
386 if (unlikely((host->flags & SDHCI_REQ_USE_DMA) &&
b8c86fc5 387 (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
c9fddbc4
PO		 388 ((data->blksz * data->blocks) & 0x3))) {
389 DBG("Reverting to PIO because of transfer size (%d)\n",
390 data->blksz * data->blocks);
391 host->flags &= ~SDHCI_REQ_USE_DMA;
392 }
393
394 /*
395 * The assumption here being that alignment is the same after
396 * translation to device address space.
397 */
398 if (unlikely((host->flags & SDHCI_REQ_USE_DMA) &&
b8c86fc5 399 (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
c9fddbc4
PO		 400 (data->sg->offset & 0x3))) {
401 DBG("Reverting to PIO because of bad alignment\n");
402 host->flags &= ~SDHCI_REQ_USE_DMA;
403 }
404
405 if (host->flags & SDHCI_REQ_USE_DMA) {
d129bceb
PO		 406 int count;
407
b8c86fc5
PO		 408 count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
409 (data->flags & MMC_DATA_READ) ?
410 DMA_FROM_DEVICE : DMA_TO_DEVICE);
411 WARN_ON(count != 1);
d129bceb 412
b8c86fc5
PO		 413 writel(sg_dma_address(data->sg),
414 host->ioaddr + SDHCI_DMA_ADDRESS);
d129bceb 415 } else {
d129bceb
PO		 416 host->cur_sg = data->sg;
417 host->num_sg = data->sg_len;
418
419 host->offset = 0;
420 host->remain = host->cur_sg->length;
421 }
c7fa9963 422
bab76961
PO		 423 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
424 writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
425 host->ioaddr + SDHCI_BLOCK_SIZE);
c7fa9963
PO		 426 writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
427}
428
429static void sdhci_set_transfer_mode(struct sdhci_host *host,
430 struct mmc_data *data)
431{
432 u16 mode;
433
c7fa9963
PO		 434 if (data == NULL)
435 return;
436
e538fbe8
PO		 437 WARN_ON(!host->data);
438
c7fa9963
PO		 439 mode = SDHCI_TRNS_BLK_CNT_EN;
440 if (data->blocks > 1)
441 mode |= SDHCI_TRNS_MULTI;
442 if (data->flags & MMC_DATA_READ)
443 mode |= SDHCI_TRNS_READ;
c9fddbc4 444 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 445 mode |= SDHCI_TRNS_DMA;
446
447 writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
d129bceb
PO		 448}
449
450static void sdhci_finish_data(struct sdhci_host *host)
451{
452 struct mmc_data *data;
d129bceb
PO		 453
454 BUG_ON(!host->data);
455
456 data = host->data;
457 host->data = NULL;
458
c9fddbc4 459 if (host->flags & SDHCI_REQ_USE_DMA) {
b8c86fc5
PO		 460 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
461 (data->flags & MMC_DATA_READ) ?
462 DMA_FROM_DEVICE : DMA_TO_DEVICE);
d129bceb
PO		 463 }
464
465 /*
c9b74c5b
PO		 466 * The specification states that the block count register must
467 * be updated, but it does not specify at what point in the
468 * data flow. That makes the register entirely useless to read
469 * back so we have to assume that nothing made it to the card
470 * in the event of an error.
d129bceb 471 */
c9b74c5b
PO		 472 if (data->error)
473 data->bytes_xfered = 0;
d129bceb 474 else
c9b74c5b 475 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 476
d129bceb
PO		 477 if (data->stop) {
478 /*
479 * The controller needs a reset of internal state machines
480 * upon error conditions.
481 */
17b0429d 482 if (data->error) {
d129bceb
PO		 483 sdhci_reset(host, SDHCI_RESET_CMD);
484 sdhci_reset(host, SDHCI_RESET_DATA);
485 }
486
487 sdhci_send_command(host, data->stop);
488 } else
489 tasklet_schedule(&host->finish_tasklet);
490}
491
492static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
493{
494 int flags;
fd2208d7 495 u32 mask;
7cb2c76f 496 unsigned long timeout;
d129bceb
PO		 497
498 WARN_ON(host->cmd);
499
d129bceb 500 /* Wait max 10 ms */
7cb2c76f 501 timeout = 10;
fd2208d7
PO		 502
503 mask = SDHCI_CMD_INHIBIT;
504 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
505 mask |= SDHCI_DATA_INHIBIT;
506
507 /* We shouldn't wait for data inihibit for stop commands, even
508 though they might use busy signaling */
509 if (host->mrq->data && (cmd == host->mrq->data->stop))
510 mask &= ~SDHCI_DATA_INHIBIT;
511
512 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 513 if (timeout == 0) {
d129bceb 514 printk(KERN_ERR "%s: Controller never released "
acf1da45 515 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 516 sdhci_dumpregs(host);
17b0429d 517 cmd->error = -EIO;
d129bceb
PO		 518 tasklet_schedule(&host->finish_tasklet);
519 return;
520 }
7cb2c76f
PO		 521 timeout--;
522 mdelay(1);
523 }
d129bceb
PO		 524
525 mod_timer(&host->timer, jiffies + 10 * HZ);
526
527 host->cmd = cmd;
528
529 sdhci_prepare_data(host, cmd->data);
530
531 writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
532
c7fa9963
PO		 533 sdhci_set_transfer_mode(host, cmd->data);
534
d129bceb 535 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
acf1da45 536 printk(KERN_ERR "%s: Unsupported response type!\n",
d129bceb 537 mmc_hostname(host->mmc));
17b0429d 538 cmd->error = -EINVAL;
d129bceb
PO		 539 tasklet_schedule(&host->finish_tasklet);
540 return;
541 }
542
543 if (!(cmd->flags & MMC_RSP_PRESENT))
544 flags = SDHCI_CMD_RESP_NONE;
545 else if (cmd->flags & MMC_RSP_136)
546 flags = SDHCI_CMD_RESP_LONG;
547 else if (cmd->flags & MMC_RSP_BUSY)
548 flags = SDHCI_CMD_RESP_SHORT_BUSY;
549 else
550 flags = SDHCI_CMD_RESP_SHORT;
551
552 if (cmd->flags & MMC_RSP_CRC)
553 flags |= SDHCI_CMD_CRC;
554 if (cmd->flags & MMC_RSP_OPCODE)
555 flags |= SDHCI_CMD_INDEX;
556 if (cmd->data)
557 flags |= SDHCI_CMD_DATA;
558
fb61e289 559 writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
d129bceb
PO		 560 host->ioaddr + SDHCI_COMMAND);
561}
562
563static void sdhci_finish_command(struct sdhci_host *host)
564{
565 int i;
566
567 BUG_ON(host->cmd == NULL);
568
569 if (host->cmd->flags & MMC_RSP_PRESENT) {
570 if (host->cmd->flags & MMC_RSP_136) {
571 /* CRC is stripped so we need to do some shifting. */
572 for (i = 0;i < 4;i++) {
573 host->cmd->resp[i] = readl(host->ioaddr +
574 SDHCI_RESPONSE + (3-i)*4) << 8;
575 if (i != 3)
576 host->cmd->resp[i] |=
577 readb(host->ioaddr +
578 SDHCI_RESPONSE + (3-i)*4-1);
579 }
580 } else {
581 host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
582 }
583 }
584
17b0429d 585 host->cmd->error = 0;
d129bceb 586
e538fbe8
PO		 587 if (host->data && host->data_early)
588 sdhci_finish_data(host);
589
590 if (!host->cmd->data)
d129bceb
PO		 591 tasklet_schedule(&host->finish_tasklet);
592
593 host->cmd = NULL;
594}
595
596static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
597{
598 int div;
599 u16 clk;
7cb2c76f 600 unsigned long timeout;
d129bceb
PO		 601
602 if (clock == host->clock)
603 return;
604
605 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
606
607 if (clock == 0)
608 goto out;
609
610 for (div = 1;div < 256;div *= 2) {
611 if ((host->max_clk / div) <= clock)
612 break;
613 }
614 div >>= 1;
615
616 clk = div << SDHCI_DIVIDER_SHIFT;
617 clk |= SDHCI_CLOCK_INT_EN;
618 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
619
620 /* Wait max 10 ms */
7cb2c76f
PO		 621 timeout = 10;
622 while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
623 & SDHCI_CLOCK_INT_STABLE)) {
624 if (timeout == 0) {
acf1da45
PO		 625 printk(KERN_ERR "%s: Internal clock never "
626 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 627 sdhci_dumpregs(host);
628 return;
629 }
7cb2c76f
PO		 630 timeout--;
631 mdelay(1);
632 }
d129bceb
PO		 633
634 clk |= SDHCI_CLOCK_CARD_EN;
635 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
636
637out:
638 host->clock = clock;
639}
640
146ad66e
PO		 641static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
642{
643 u8 pwr;
644
645 if (host->power == power)
646 return;
647
9e9dc5f2
DS		 648 if (power == (unsigned short)-1) {
649 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
146ad66e 650 goto out;
9e9dc5f2
DS		 651 }
652
653 /*
654 * Spec says that we should clear the power reg before setting
655 * a new value. Some controllers don't seem to like this though.
656 */
b8c86fc5 657 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
9e9dc5f2 658 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
146ad66e
PO		 659
660 pwr = SDHCI_POWER_ON;
661
4be34c99 662 switch (1 << power) {
55556da0 663 case MMC_VDD_165_195:
146ad66e
PO		 664 pwr |= SDHCI_POWER_180;
665 break;
4be34c99
PL		 666 case MMC_VDD_29_30:
667 case MMC_VDD_30_31:
146ad66e
PO		 668 pwr |= SDHCI_POWER_300;
669 break;
4be34c99
PL		 670 case MMC_VDD_32_33:
671 case MMC_VDD_33_34:
146ad66e
PO		 672 pwr |= SDHCI_POWER_330;
673 break;
674 default:
675 BUG();
676 }
677
e08c1694
AS		 678 /*
679 * At least the CaFe chip gets confused if we set the voltage
680 * and set turn on power at the same time, so set the voltage first.
681 */
b8c86fc5 682 if ((host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER))
e08c1694
AS		 683 writeb(pwr & ~SDHCI_POWER_ON,
684 host->ioaddr + SDHCI_POWER_CONTROL);
685
146ad66e
PO		 686 writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
687
688out:
689 host->power = power;
690}
691
d129bceb
PO		 692/*****************************************************************************\
693 * *
694 * MMC callbacks *
695 * *
696\*****************************************************************************/
697
698static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
699{
700 struct sdhci_host *host;
701 unsigned long flags;
702
703 host = mmc_priv(mmc);
704
705 spin_lock_irqsave(&host->lock, flags);
706
707 WARN_ON(host->mrq != NULL);
708
2f730fec 709#ifndef CONFIG_LEDS_CLASS
d129bceb 710 sdhci_activate_led(host);
2f730fec 711#endif
d129bceb
PO		 712
713 host->mrq = mrq;
714
1e72859e
PO		 715 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)
716 || (host->flags & SDHCI_DEVICE_DEAD)) {
17b0429d 717 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb
PO		 718 tasklet_schedule(&host->finish_tasklet);
719 } else
720 sdhci_send_command(host, mrq->cmd);
721
5f25a66f 722 mmiowb();
d129bceb
PO		 723 spin_unlock_irqrestore(&host->lock, flags);
724}
725
726static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
727{
728 struct sdhci_host *host;
729 unsigned long flags;
730 u8 ctrl;
731
732 host = mmc_priv(mmc);
733
734 spin_lock_irqsave(&host->lock, flags);
735
1e72859e
PO		 736 if (host->flags & SDHCI_DEVICE_DEAD)
737 goto out;
738
d129bceb
PO		 739 /*
740 * Reset the chip on each power off.
741 * Should clear out any weird states.
742 */
743 if (ios->power_mode == MMC_POWER_OFF) {
744 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
d129bceb 745 sdhci_init(host);
d129bceb
PO		 746 }
747
748 sdhci_set_clock(host, ios->clock);
749
750 if (ios->power_mode == MMC_POWER_OFF)
146ad66e 751 sdhci_set_power(host, -1);
d129bceb 752 else
146ad66e 753 sdhci_set_power(host, ios->vdd);
d129bceb
PO		 754
755 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
cd9277c0 756
d129bceb
PO		 757 if (ios->bus_width == MMC_BUS_WIDTH_4)
758 ctrl |= SDHCI_CTRL_4BITBUS;
759 else
760 ctrl &= ~SDHCI_CTRL_4BITBUS;
cd9277c0
PO		 761
762 if (ios->timing == MMC_TIMING_SD_HS)
763 ctrl |= SDHCI_CTRL_HISPD;
764 else
765 ctrl &= ~SDHCI_CTRL_HISPD;
766
d129bceb
PO		 767 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
768
b8352260
LD		 769 /*
770 * Some (ENE) controllers go apeshit on some ios operation,
771 * signalling timeout and CRC errors even on CMD0. Resetting
772 * it on each ios seems to solve the problem.
773 */
b8c86fc5 774 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
b8352260
LD		 775 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
776
1e72859e 777out:
5f25a66f 778 mmiowb();
d129bceb
PO		 779 spin_unlock_irqrestore(&host->lock, flags);
780}
781
782static int sdhci_get_ro(struct mmc_host *mmc)
783{
784 struct sdhci_host *host;
785 unsigned long flags;
786 int present;
787
788 host = mmc_priv(mmc);
789
790 spin_lock_irqsave(&host->lock, flags);
791
1e72859e
PO		 792 if (host->flags & SDHCI_DEVICE_DEAD)
793 present = 0;
794 else
795 present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
d129bceb
PO		 796
797 spin_unlock_irqrestore(&host->lock, flags);
798
799 return !(present & SDHCI_WRITE_PROTECT);
800}
801
f75979b7
PO		 802static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
803{
804 struct sdhci_host *host;
805 unsigned long flags;
806 u32 ier;
807
808 host = mmc_priv(mmc);
809
810 spin_lock_irqsave(&host->lock, flags);
811
1e72859e
PO		 812 if (host->flags & SDHCI_DEVICE_DEAD)
813 goto out;
814
f75979b7
PO		 815 ier = readl(host->ioaddr + SDHCI_INT_ENABLE);
816
817 ier &= ~SDHCI_INT_CARD_INT;
818 if (enable)
819 ier |= SDHCI_INT_CARD_INT;
820
821 writel(ier, host->ioaddr + SDHCI_INT_ENABLE);
822 writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE);
823
1e72859e 824out:
f75979b7
PO		 825 mmiowb();
826
827 spin_unlock_irqrestore(&host->lock, flags);
828}
829
ab7aefd0 830static const struct mmc_host_ops sdhci_ops = {
d129bceb
PO		 831 .request = sdhci_request,
832 .set_ios = sdhci_set_ios,
833 .get_ro = sdhci_get_ro,
f75979b7 834 .enable_sdio_irq = sdhci_enable_sdio_irq,
d129bceb
PO		 835};
836
837/*****************************************************************************\
838 * *
839 * Tasklets *
840 * *
841\*****************************************************************************/
842
843static void sdhci_tasklet_card(unsigned long param)
844{
845 struct sdhci_host *host;
846 unsigned long flags;
847
848 host = (struct sdhci_host*)param;
849
850 spin_lock_irqsave(&host->lock, flags);
851
852 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
853 if (host->mrq) {
854 printk(KERN_ERR "%s: Card removed during transfer!\n",
855 mmc_hostname(host->mmc));
856 printk(KERN_ERR "%s: Resetting controller.\n",
857 mmc_hostname(host->mmc));
858
859 sdhci_reset(host, SDHCI_RESET_CMD);
860 sdhci_reset(host, SDHCI_RESET_DATA);
861
17b0429d 862 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb
PO		 863 tasklet_schedule(&host->finish_tasklet);
864 }
865 }
866
867 spin_unlock_irqrestore(&host->lock, flags);
868
869 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
870}
871
872static void sdhci_tasklet_finish(unsigned long param)
873{
874 struct sdhci_host *host;
875 unsigned long flags;
876 struct mmc_request *mrq;
877
878 host = (struct sdhci_host*)param;
879
880 spin_lock_irqsave(&host->lock, flags);
881
882 del_timer(&host->timer);
883
884 mrq = host->mrq;
885
d129bceb
PO		 886 /*
887 * The controller needs a reset of internal state machines
888 * upon error conditions.
889 */
1e72859e
PO		 890 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
891 (mrq->cmd->error ||
892 (mrq->data && (mrq->data->error ||
893 (mrq->data->stop && mrq->data->stop->error))) ||
894 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 895
896 /* Some controllers need this kick or reset won't work here */
b8c86fc5 897 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
645289dc
PO		 898 unsigned int clock;
899
900 /* This is to force an update */
901 clock = host->clock;
902 host->clock = 0;
903 sdhci_set_clock(host, clock);
904 }
905
906 /* Spec says we should do both at the same time, but Ricoh
907 controllers do not like that. */
d129bceb
PO		 908 sdhci_reset(host, SDHCI_RESET_CMD);
909 sdhci_reset(host, SDHCI_RESET_DATA);
910 }
911
912 host->mrq = NULL;
913 host->cmd = NULL;
914 host->data = NULL;
915
2f730fec 916#ifndef CONFIG_LEDS_CLASS
d129bceb 917 sdhci_deactivate_led(host);
2f730fec 918#endif
d129bceb 919
5f25a66f 920 mmiowb();
d129bceb
PO		 921 spin_unlock_irqrestore(&host->lock, flags);
922
923 mmc_request_done(host->mmc, mrq);
924}
925
926static void sdhci_timeout_timer(unsigned long data)
927{
928 struct sdhci_host *host;
929 unsigned long flags;
930
931 host = (struct sdhci_host*)data;
932
933 spin_lock_irqsave(&host->lock, flags);
934
935 if (host->mrq) {
acf1da45
PO		 936 printk(KERN_ERR "%s: Timeout waiting for hardware "
937 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 938 sdhci_dumpregs(host);
939
940 if (host->data) {
17b0429d 941 host->data->error = -ETIMEDOUT;
d129bceb
PO		 942 sdhci_finish_data(host);
943 } else {
944 if (host->cmd)
17b0429d 945 host->cmd->error = -ETIMEDOUT;
d129bceb 946 else
17b0429d 947 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 948
949 tasklet_schedule(&host->finish_tasklet);
950 }
951 }
952
5f25a66f 953 mmiowb();
d129bceb
PO		 954 spin_unlock_irqrestore(&host->lock, flags);
955}
956
957/*****************************************************************************\
958 * *
959 * Interrupt handling *
960 * *
961\*****************************************************************************/
962
963static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
964{
965 BUG_ON(intmask == 0);
966
967 if (!host->cmd) {
b67ac3f3
PO		 968 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
969 "though no command operation was in progress.\n",
970 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 971 sdhci_dumpregs(host);
972 return;
973 }
974
43b58b36 975 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 976 host->cmd->error = -ETIMEDOUT;
977 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
978 SDHCI_INT_INDEX))
979 host->cmd->error = -EILSEQ;
43b58b36 980
17b0429d 981 if (host->cmd->error)
d129bceb 982 tasklet_schedule(&host->finish_tasklet);
43b58b36
PO		 983 else if (intmask & SDHCI_INT_RESPONSE)
984 sdhci_finish_command(host);
d129bceb
PO		 985}
986
987static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
988{
989 BUG_ON(intmask == 0);
990
991 if (!host->data) {
992 /*
993 * A data end interrupt is sent together with the response
994 * for the stop command.
995 */
996 if (intmask & SDHCI_INT_DATA_END)
997 return;
998
b67ac3f3
PO		 999 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1000 "though no data operation was in progress.\n",
1001 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 1002 sdhci_dumpregs(host);
1003
1004 return;
1005 }
1006
1007 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d
PO		 1008 host->data->error = -ETIMEDOUT;
1009 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1010 host->data->error = -EILSEQ;
d129bceb 1011
17b0429d 1012 if (host->data->error)
d129bceb
PO		 1013 sdhci_finish_data(host);
1014 else {
a406f5a3 1015 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 1016 sdhci_transfer_pio(host);
1017
6ba736a1
PO		 1018 /*
1019 * We currently don't do anything fancy with DMA
1020 * boundaries, but as we can't disable the feature
1021 * we need to at least restart the transfer.
1022 */
1023 if (intmask & SDHCI_INT_DMA_END)
1024 writel(readl(host->ioaddr + SDHCI_DMA_ADDRESS),
1025 host->ioaddr + SDHCI_DMA_ADDRESS);
1026
e538fbe8
PO		 1027 if (intmask & SDHCI_INT_DATA_END) {
1028 if (host->cmd) {
1029 /*
1030 * Data managed to finish before the
1031 * command completed. Make sure we do
1032 * things in the proper order.
1033 */
1034 host->data_early = 1;
1035 } else {
1036 sdhci_finish_data(host);
1037 }
1038 }
d129bceb
PO		 1039 }
1040}
1041
7d12e780 1042static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb
PO		 1043{
1044 irqreturn_t result;
1045 struct sdhci_host* host = dev_id;
1046 u32 intmask;
f75979b7 1047 int cardint = 0;
d129bceb
PO		 1048
1049 spin_lock(&host->lock);
1050
1051 intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
1052
62df67a5 1053 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 1054 result = IRQ_NONE;
1055 goto out;
1056 }
1057
b69c9058
PO		 1058 DBG("*** %s got interrupt: 0x%08x\n",
1059 mmc_hostname(host->mmc), intmask);
d129bceb 1060
3192a28f
PO		 1061 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1062 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
1063 host->ioaddr + SDHCI_INT_STATUS);
d129bceb 1064 tasklet_schedule(&host->card_tasklet);
3192a28f 1065 }
d129bceb 1066
3192a28f 1067 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 1068
3192a28f 1069 if (intmask & SDHCI_INT_CMD_MASK) {
d129bceb
PO		 1070 writel(intmask & SDHCI_INT_CMD_MASK,
1071 host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1072 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 1073 }
1074
1075 if (intmask & SDHCI_INT_DATA_MASK) {
d129bceb
PO		 1076 writel(intmask & SDHCI_INT_DATA_MASK,
1077 host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1078 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 1079 }
1080
1081 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1082
964f9ce2
PO		 1083 intmask &= ~SDHCI_INT_ERROR;
1084
d129bceb 1085 if (intmask & SDHCI_INT_BUS_POWER) {
3192a28f 1086 printk(KERN_ERR "%s: Card is consuming too much power!\n",
d129bceb 1087 mmc_hostname(host->mmc));
3192a28f 1088 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
d129bceb
PO		 1089 }
1090
9d26a5d3 1091 intmask &= ~SDHCI_INT_BUS_POWER;
3192a28f 1092
f75979b7
PO		 1093 if (intmask & SDHCI_INT_CARD_INT)
1094 cardint = 1;
1095
1096 intmask &= ~SDHCI_INT_CARD_INT;
1097
3192a28f 1098 if (intmask) {
acf1da45 1099 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
3192a28f 1100 mmc_hostname(host->mmc), intmask);
d129bceb
PO		 1101 sdhci_dumpregs(host);
1102
d129bceb 1103 writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1104 }
d129bceb
PO		 1105
1106 result = IRQ_HANDLED;
1107
5f25a66f 1108 mmiowb();
d129bceb
PO		 1109out:
1110 spin_unlock(&host->lock);
1111
f75979b7
PO		 1112 /*
1113 * We have to delay this as it calls back into the driver.
1114 */
1115 if (cardint)
1116 mmc_signal_sdio_irq(host->mmc);
1117
d129bceb
PO		 1118 return result;
1119}
1120
1121/*****************************************************************************\
1122 * *
1123 * Suspend/resume *
1124 * *
1125\*****************************************************************************/
1126
1127#ifdef CONFIG_PM
1128
b8c86fc5 1129int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
d129bceb 1130{
b8c86fc5 1131 int ret;
a715dfc7 1132
b8c86fc5
PO		 1133 ret = mmc_suspend_host(host->mmc, state);
1134 if (ret)
1135 return ret;
a715dfc7 1136
b8c86fc5 1137 free_irq(host->irq, host);
d129bceb
PO		 1138
1139 return 0;
1140}
1141
b8c86fc5 1142EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 1143
b8c86fc5
PO		 1144int sdhci_resume_host(struct sdhci_host *host)
1145{
1146 int ret;
d129bceb 1147
b8c86fc5
PO		 1148 if (host->flags & SDHCI_USE_DMA) {
1149 if (host->ops->enable_dma)
1150 host->ops->enable_dma(host);
1151 }
d129bceb 1152
b8c86fc5
PO		 1153 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1154 mmc_hostname(host->mmc), host);
df1c4b7b
PO		 1155 if (ret)
1156 return ret;
d129bceb 1157
b8c86fc5
PO		 1158 sdhci_init(host);
1159 mmiowb();
1160
1161 ret = mmc_resume_host(host->mmc);
1162 if (ret)
1163 return ret;
d129bceb
PO		 1164
1165 return 0;
1166}
1167
b8c86fc5 1168EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb
PO		 1169
1170#endif /* CONFIG_PM */
1171
1172/*****************************************************************************\
1173 * *
b8c86fc5 1174 * Device allocation/registration *
d129bceb
PO		 1175 * *
1176\*****************************************************************************/
1177
b8c86fc5
PO		 1178struct sdhci_host *sdhci_alloc_host(struct device *dev,
1179 size_t priv_size)
d129bceb 1180{
d129bceb
PO		 1181 struct mmc_host *mmc;
1182 struct sdhci_host *host;
1183
b8c86fc5 1184 WARN_ON(dev == NULL);
d129bceb 1185
b8c86fc5 1186 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 1187 if (!mmc)
b8c86fc5 1188 return ERR_PTR(-ENOMEM);
d129bceb
PO		 1189
1190 host = mmc_priv(mmc);
1191 host->mmc = mmc;
1192
b8c86fc5
PO		 1193 return host;
1194}
8a4da143 1195
b8c86fc5 1196EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 1197
b8c86fc5
PO		 1198int sdhci_add_host(struct sdhci_host *host)
1199{
1200 struct mmc_host *mmc;
1201 unsigned int caps;
1202 unsigned int version;
1203 int ret;
d129bceb 1204
b8c86fc5
PO		 1205 WARN_ON(host == NULL);
1206 if (host == NULL)
1207 return -EINVAL;
d129bceb 1208
b8c86fc5 1209 mmc = host->mmc;
d129bceb 1210
b8c86fc5
PO		 1211 if (debug_quirks)
1212 host->quirks = debug_quirks;
d129bceb 1213
d96649ed
PO		 1214 sdhci_reset(host, SDHCI_RESET_ALL);
1215
4a965505
PO		 1216 version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1217 version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
c6573c94 1218 if (version > 1) {
4a965505 1219 printk(KERN_ERR "%s: Unknown controller version (%d). "
b69c9058 1220 "You may experience problems.\n", mmc_hostname(mmc),
4a965505 1221 version);
4a965505
PO		 1222 }
1223
d129bceb
PO		 1224 caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1225
b8c86fc5 1226 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
98608076 1227 host->flags |= SDHCI_USE_DMA;
67435274
PO		 1228 else if (!(caps & SDHCI_CAN_DO_DMA))
1229 DBG("Controller doesn't have DMA capability\n");
1230 else
d129bceb
PO		 1231 host->flags |= SDHCI_USE_DMA;
1232
b8c86fc5 1233 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
7c168e3d 1234 (host->flags & SDHCI_USE_DMA)) {
cee687ce 1235 DBG("Disabling DMA as it is marked broken\n");
7c168e3d
FT		 1236 host->flags &= ~SDHCI_USE_DMA;
1237 }
1238
d129bceb 1239 if (host->flags & SDHCI_USE_DMA) {
b8c86fc5
PO		 1240 if (host->ops->enable_dma) {
1241 if (host->ops->enable_dma(host)) {
1242 printk(KERN_WARNING "%s: No suitable DMA "
1243 "available. Falling back to PIO.\n",
1244 mmc_hostname(mmc));
1245 host->flags &= ~SDHCI_USE_DMA;
1246 }
d129bceb
PO		 1247 }
1248 }
1249
b8c86fc5
PO		 1250 /* XXX: Hack to get MMC layer to avoid highmem */
1251 if (!(host->flags & SDHCI_USE_DMA))
1252 mmc_dev(host->mmc)->dma_mask = 0;
d129bceb 1253
8ef1a143
PO		 1254 host->max_clk =
1255 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1256 if (host->max_clk == 0) {
1257 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
b69c9058 1258 "frequency.\n", mmc_hostname(mmc));
b8c86fc5 1259 return -ENODEV;
8ef1a143 1260 }
d129bceb
PO		 1261 host->max_clk *= 1000000;
1262
1c8cde92
PO		 1263 host->timeout_clk =
1264 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1265 if (host->timeout_clk == 0) {
1266 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
b69c9058 1267 "frequency.\n", mmc_hostname(mmc));
b8c86fc5 1268 return -ENODEV;
1c8cde92
PO		 1269 }
1270 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1271 host->timeout_clk *= 1000;
d129bceb
PO		 1272
1273 /*
1274 * Set host parameters.
1275 */
1276 mmc->ops = &sdhci_ops;
1277 mmc->f_min = host->max_clk / 256;
1278 mmc->f_max = host->max_clk;
c9b74c5b 1279 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
d129bceb 1280
cd9277c0
PO		 1281 if (caps & SDHCI_CAN_DO_HISPD)
1282 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1283
146ad66e
PO		 1284 mmc->ocr_avail = 0;
1285 if (caps & SDHCI_CAN_VDD_330)
1286 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
c70840e8 1287 if (caps & SDHCI_CAN_VDD_300)
146ad66e 1288 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
c70840e8 1289 if (caps & SDHCI_CAN_VDD_180)
55556da0 1290 mmc->ocr_avail |= MMC_VDD_165_195;
146ad66e
PO		 1291
1292 if (mmc->ocr_avail == 0) {
1293 printk(KERN_ERR "%s: Hardware doesn't report any "
b69c9058 1294 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 1295 return -ENODEV;
146ad66e
PO		 1296 }
1297
d129bceb
PO		 1298 spin_lock_init(&host->lock);
1299
1300 /*
1301 * Maximum number of segments. Hardware cannot do scatter lists.
1302 */
1303 if (host->flags & SDHCI_USE_DMA)
1304 mmc->max_hw_segs = 1;
1305 else
1306 mmc->max_hw_segs = 16;
1307 mmc->max_phys_segs = 16;
1308
1309 /*
bab76961 1310 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 1311 * size (512KiB).
d129bceb 1312 */
55db890a 1313 mmc->max_req_size = 524288;
d129bceb
PO		 1314
1315 /*
1316 * Maximum segment size. Could be one segment with the maximum number
55db890a 1317 * of bytes.
d129bceb 1318 */
55db890a 1319 mmc->max_seg_size = mmc->max_req_size;
d129bceb 1320
fe4a3c7a
PO		 1321 /*
1322 * Maximum block size. This varies from controller to controller and
1323 * is specified in the capabilities register.
1324 */
1325 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1326 if (mmc->max_blk_size >= 3) {
b69c9058
PO		 1327 printk(KERN_WARNING "%s: Invalid maximum block size, "
1328 "assuming 512 bytes\n", mmc_hostname(mmc));
03f8590d
DV		 1329 mmc->max_blk_size = 512;
1330 } else
1331 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 1332
55db890a
PO		 1333 /*
1334 * Maximum block count.
1335 */
1336 mmc->max_blk_count = 65535;
1337
d129bceb
PO		 1338 /*
1339 * Init tasklets.
1340 */
1341 tasklet_init(&host->card_tasklet,
1342 sdhci_tasklet_card, (unsigned long)host);
1343 tasklet_init(&host->finish_tasklet,
1344 sdhci_tasklet_finish, (unsigned long)host);
1345
e4cad1b5 1346 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 1347
dace1453 1348 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
b69c9058 1349 mmc_hostname(mmc), host);
d129bceb 1350 if (ret)
8ef1a143 1351 goto untasklet;
d129bceb
PO		 1352
1353 sdhci_init(host);
1354
1355#ifdef CONFIG_MMC_DEBUG
1356 sdhci_dumpregs(host);
1357#endif
1358
2f730fec
PO		 1359#ifdef CONFIG_LEDS_CLASS
1360 host->led.name = mmc_hostname(mmc);
1361 host->led.brightness = LED_OFF;
1362 host->led.default_trigger = mmc_hostname(mmc);
1363 host->led.brightness_set = sdhci_led_control;
1364
b8c86fc5 1365 ret = led_classdev_register(mmc_dev(mmc), &host->led);
2f730fec
PO		 1366 if (ret)
1367 goto reset;
1368#endif
1369
5f25a66f
PO		 1370 mmiowb();
1371
d129bceb
PO		 1372 mmc_add_host(mmc);
1373
b8c86fc5
PO		 1374 printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n",
1375 mmc_hostname(mmc), host->hw_name, mmc_dev(mmc)->bus_id,
d129bceb
PO		 1376 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1377
1378 return 0;
1379
2f730fec
PO		 1380#ifdef CONFIG_LEDS_CLASS
1381reset:
1382 sdhci_reset(host, SDHCI_RESET_ALL);
1383 free_irq(host->irq, host);
1384#endif
8ef1a143 1385untasklet:
d129bceb
PO		 1386 tasklet_kill(&host->card_tasklet);
1387 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 1388
1389 return ret;
1390}
1391
b8c86fc5 1392EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 1393
1e72859e 1394void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 1395{
1e72859e
PO		 1396 unsigned long flags;
1397
1398 if (dead) {
1399 spin_lock_irqsave(&host->lock, flags);
1400
1401 host->flags |= SDHCI_DEVICE_DEAD;
1402
1403 if (host->mrq) {
1404 printk(KERN_ERR "%s: Controller removed during "
1405 " transfer!\n", mmc_hostname(host->mmc));
1406
1407 host->mrq->cmd->error = -ENOMEDIUM;
1408 tasklet_schedule(&host->finish_tasklet);
1409 }
1410
1411 spin_unlock_irqrestore(&host->lock, flags);
1412 }
1413
b8c86fc5 1414 mmc_remove_host(host->mmc);
d129bceb 1415
2f730fec
PO		 1416#ifdef CONFIG_LEDS_CLASS
1417 led_classdev_unregister(&host->led);
1418#endif
1419
1e72859e
PO		 1420 if (!dead)
1421 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb
PO		 1422
1423 free_irq(host->irq, host);
1424
1425 del_timer_sync(&host->timer);
1426
1427 tasklet_kill(&host->card_tasklet);
1428 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 1429}
1430
b8c86fc5 1431EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 1432
b8c86fc5 1433void sdhci_free_host(struct sdhci_host *host)
d129bceb 1434{
b8c86fc5 1435 mmc_free_host(host->mmc);
d129bceb
PO		 1436}
1437
b8c86fc5 1438EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 1439
1440/*****************************************************************************\
1441 * *
1442 * Driver init/exit *
1443 * *
1444\*****************************************************************************/
1445
1446static int __init sdhci_drv_init(void)
1447{
1448 printk(KERN_INFO DRIVER_NAME
52fbf9c9 1449 ": Secure Digital Host Controller Interface driver\n");
d129bceb
PO		 1450 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1451
b8c86fc5 1452 return 0;
d129bceb
PO		 1453}
1454
1455static void __exit sdhci_drv_exit(void)
1456{
d129bceb
PO		 1457}
1458
1459module_init(sdhci_drv_init);
1460module_exit(sdhci_drv_exit);
1461
df673b22 1462module_param(debug_quirks, uint, 0444);
67435274 1463
d129bceb 1464MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
b8c86fc5 1465MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 1466MODULE_LICENSE("GPL");
67435274 1467
df673b22 1468MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
kernel source for telekom puls (alcatel/mediatek)