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b8c86fc5 PO |
1 | /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface |
2 | * | |
3 | * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or (at | |
8 | * your option) any later version. | |
9 | * | |
10 | * Thanks to the following companies for their support: | |
11 | * | |
12 | * - JMicron (hardware and technical support) | |
13 | */ | |
14 | ||
15 | #include <linux/delay.h> | |
16 | #include <linux/highmem.h> | |
88b47679 | 17 | #include <linux/module.h> |
b8c86fc5 PO |
18 | #include <linux/pci.h> |
19 | #include <linux/dma-mapping.h> | |
5a0e3ad6 | 20 | #include <linux/slab.h> |
ccc92c23 | 21 | #include <linux/device.h> |
b8c86fc5 | 22 | #include <linux/mmc/host.h> |
b177bc91 AP |
23 | #include <linux/scatterlist.h> |
24 | #include <linux/io.h> | |
0f201655 | 25 | #include <linux/gpio.h> |
66fd8ad5 | 26 | #include <linux/pm_runtime.h> |
52c506f0 | 27 | #include <linux/mmc/sdhci-pci-data.h> |
b8c86fc5 PO |
28 | |
29 | #include "sdhci.h" | |
30 | ||
296e0b03 AS |
31 | /* |
32 | * PCI device IDs | |
33 | */ | |
34 | #define PCI_DEVICE_ID_INTEL_PCH_SDIO0 0x8809 | |
35 | #define PCI_DEVICE_ID_INTEL_PCH_SDIO1 0x880a | |
728ef3d1 AH |
36 | #define PCI_DEVICE_ID_INTEL_BYT_EMMC 0x0f14 |
37 | #define PCI_DEVICE_ID_INTEL_BYT_SDIO 0x0f15 | |
38 | #define PCI_DEVICE_ID_INTEL_BYT_SD 0x0f16 | |
296e0b03 | 39 | |
b8c86fc5 PO |
40 | /* |
41 | * PCI registers | |
42 | */ | |
43 | ||
44 | #define PCI_SDHCI_IFPIO 0x00 | |
45 | #define PCI_SDHCI_IFDMA 0x01 | |
46 | #define PCI_SDHCI_IFVENDOR 0x02 | |
47 | ||
48 | #define PCI_SLOT_INFO 0x40 /* 8 bits */ | |
49 | #define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7) | |
50 | #define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07 | |
51 | ||
52 | #define MAX_SLOTS 8 | |
53 | ||
22606405 | 54 | struct sdhci_pci_chip; |
4489428a | 55 | struct sdhci_pci_slot; |
22606405 PO |
56 | |
57 | struct sdhci_pci_fixes { | |
58 | unsigned int quirks; | |
f3c55a7b | 59 | unsigned int quirks2; |
c43fd774 | 60 | bool allow_runtime_pm; |
22606405 | 61 | |
b177bc91 | 62 | int (*probe) (struct sdhci_pci_chip *); |
45211e21 | 63 | |
b177bc91 AP |
64 | int (*probe_slot) (struct sdhci_pci_slot *); |
65 | void (*remove_slot) (struct sdhci_pci_slot *, int); | |
4489428a | 66 | |
29495aa0 | 67 | int (*suspend) (struct sdhci_pci_chip *); |
b177bc91 | 68 | int (*resume) (struct sdhci_pci_chip *); |
22606405 PO |
69 | }; |
70 | ||
71 | struct sdhci_pci_slot { | |
72 | struct sdhci_pci_chip *chip; | |
73 | struct sdhci_host *host; | |
52c506f0 | 74 | struct sdhci_pci_data *data; |
b8c86fc5 | 75 | |
22606405 | 76 | int pci_bar; |
0f201655 | 77 | int rst_n_gpio; |
66fd8ad5 AH |
78 | int cd_gpio; |
79 | int cd_irq; | |
22606405 PO |
80 | }; |
81 | ||
82 | struct sdhci_pci_chip { | |
83 | struct pci_dev *pdev; | |
84 | ||
85 | unsigned int quirks; | |
f3c55a7b | 86 | unsigned int quirks2; |
c43fd774 | 87 | bool allow_runtime_pm; |
22606405 PO |
88 | const struct sdhci_pci_fixes *fixes; |
89 | ||
90 | int num_slots; /* Slots on controller */ | |
91 | struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */ | |
92 | }; | |
93 | ||
94 | ||
95 | /*****************************************************************************\ | |
96 | * * | |
97 | * Hardware specific quirk handling * | |
98 | * * | |
99 | \*****************************************************************************/ | |
100 | ||
101 | static int ricoh_probe(struct sdhci_pci_chip *chip) | |
102 | { | |
c99436fb CB |
103 | if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || |
104 | chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) | |
22606405 | 105 | chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; |
ccc92c23 ML |
106 | return 0; |
107 | } | |
108 | ||
109 | static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) | |
110 | { | |
111 | slot->host->caps = | |
112 | ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) | |
113 | & SDHCI_TIMEOUT_CLK_MASK) | | |
22606405 | 114 | |
ccc92c23 ML |
115 | ((0x21 << SDHCI_CLOCK_BASE_SHIFT) |
116 | & SDHCI_CLOCK_BASE_MASK) | | |
117 | ||
118 | SDHCI_TIMEOUT_CLK_UNIT | | |
119 | SDHCI_CAN_VDD_330 | | |
1a1f1f04 | 120 | SDHCI_CAN_DO_HISPD | |
ccc92c23 ML |
121 | SDHCI_CAN_DO_SDMA; |
122 | return 0; | |
123 | } | |
124 | ||
125 | static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) | |
126 | { | |
127 | /* Apply a delay to allow controller to settle */ | |
128 | /* Otherwise it becomes confused if card state changed | |
129 | during suspend */ | |
130 | msleep(500); | |
22606405 PO |
131 | return 0; |
132 | } | |
133 | ||
134 | static const struct sdhci_pci_fixes sdhci_ricoh = { | |
135 | .probe = ricoh_probe, | |
84938294 VK |
136 | .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | |
137 | SDHCI_QUIRK_FORCE_DMA | | |
138 | SDHCI_QUIRK_CLOCK_BEFORE_RESET, | |
22606405 PO |
139 | }; |
140 | ||
ccc92c23 ML |
141 | static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { |
142 | .probe_slot = ricoh_mmc_probe_slot, | |
143 | .resume = ricoh_mmc_resume, | |
144 | .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | | |
145 | SDHCI_QUIRK_CLOCK_BEFORE_RESET | | |
146 | SDHCI_QUIRK_NO_CARD_NO_RESET | | |
147 | SDHCI_QUIRK_MISSING_CAPS | |
148 | }; | |
149 | ||
22606405 PO |
150 | static const struct sdhci_pci_fixes sdhci_ene_712 = { |
151 | .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | | |
152 | SDHCI_QUIRK_BROKEN_DMA, | |
153 | }; | |
154 | ||
155 | static const struct sdhci_pci_fixes sdhci_ene_714 = { | |
156 | .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | | |
157 | SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | | |
158 | SDHCI_QUIRK_BROKEN_DMA, | |
159 | }; | |
160 | ||
161 | static const struct sdhci_pci_fixes sdhci_cafe = { | |
162 | .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | | |
a0874897 | 163 | SDHCI_QUIRK_NO_BUSY_IRQ | |
55fc05b7 | 164 | SDHCI_QUIRK_BROKEN_CARD_DETECTION | |
ee53ab5d | 165 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, |
22606405 PO |
166 | }; |
167 | ||
68077b02 ML |
168 | static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) |
169 | { | |
170 | slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; | |
171 | return 0; | |
172 | } | |
173 | ||
f9ee3eab AC |
174 | /* |
175 | * ADMA operation is disabled for Moorestown platform due to | |
176 | * hardware bugs. | |
177 | */ | |
35ac6f08 | 178 | static int mrst_hc_probe(struct sdhci_pci_chip *chip) |
f9ee3eab AC |
179 | { |
180 | /* | |
35ac6f08 JP |
181 | * slots number is fixed here for MRST as SDIO3/5 are never used and |
182 | * have hardware bugs. | |
f9ee3eab AC |
183 | */ |
184 | chip->num_slots = 1; | |
185 | return 0; | |
186 | } | |
187 | ||
296e0b03 AS |
188 | static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) |
189 | { | |
190 | slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; | |
191 | return 0; | |
192 | } | |
193 | ||
66fd8ad5 AH |
194 | #ifdef CONFIG_PM_RUNTIME |
195 | ||
c5e027a4 | 196 | static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) |
66fd8ad5 AH |
197 | { |
198 | struct sdhci_pci_slot *slot = dev_id; | |
199 | struct sdhci_host *host = slot->host; | |
200 | ||
201 | mmc_detect_change(host->mmc, msecs_to_jiffies(200)); | |
202 | return IRQ_HANDLED; | |
203 | } | |
204 | ||
c5e027a4 | 205 | static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) |
66fd8ad5 | 206 | { |
c5e027a4 | 207 | int err, irq, gpio = slot->cd_gpio; |
66fd8ad5 AH |
208 | |
209 | slot->cd_gpio = -EINVAL; | |
210 | slot->cd_irq = -EINVAL; | |
211 | ||
c5e027a4 AH |
212 | if (!gpio_is_valid(gpio)) |
213 | return; | |
214 | ||
66fd8ad5 AH |
215 | err = gpio_request(gpio, "sd_cd"); |
216 | if (err < 0) | |
217 | goto out; | |
218 | ||
219 | err = gpio_direction_input(gpio); | |
220 | if (err < 0) | |
221 | goto out_free; | |
222 | ||
223 | irq = gpio_to_irq(gpio); | |
224 | if (irq < 0) | |
225 | goto out_free; | |
226 | ||
c5e027a4 | 227 | err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | |
66fd8ad5 AH |
228 | IRQF_TRIGGER_FALLING, "sd_cd", slot); |
229 | if (err) | |
230 | goto out_free; | |
231 | ||
232 | slot->cd_gpio = gpio; | |
233 | slot->cd_irq = irq; | |
66fd8ad5 | 234 | |
c5e027a4 | 235 | return; |
66fd8ad5 AH |
236 | |
237 | out_free: | |
238 | gpio_free(gpio); | |
239 | out: | |
240 | dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); | |
66fd8ad5 AH |
241 | } |
242 | ||
c5e027a4 | 243 | static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) |
66fd8ad5 AH |
244 | { |
245 | if (slot->cd_irq >= 0) | |
246 | free_irq(slot->cd_irq, slot); | |
c5e027a4 AH |
247 | if (gpio_is_valid(slot->cd_gpio)) |
248 | gpio_free(slot->cd_gpio); | |
66fd8ad5 AH |
249 | } |
250 | ||
251 | #else | |
252 | ||
c5e027a4 AH |
253 | static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) |
254 | { | |
255 | } | |
256 | ||
257 | static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) | |
258 | { | |
259 | } | |
66fd8ad5 AH |
260 | |
261 | #endif | |
262 | ||
0d013bcf AH |
263 | static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) |
264 | { | |
66fd8ad5 | 265 | slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; |
da721cf7 AH |
266 | slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC | |
267 | MMC_CAP2_HC_ERASE_SZ; | |
0d013bcf AH |
268 | return 0; |
269 | } | |
270 | ||
93933508 AH |
271 | static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) |
272 | { | |
012e4671 | 273 | slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; |
93933508 AH |
274 | return 0; |
275 | } | |
276 | ||
f9ee3eab AC |
277 | static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { |
278 | .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, | |
68077b02 | 279 | .probe_slot = mrst_hc_probe_slot, |
f9ee3eab AC |
280 | }; |
281 | ||
35ac6f08 | 282 | static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { |
f9ee3eab | 283 | .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, |
35ac6f08 | 284 | .probe = mrst_hc_probe, |
f9ee3eab AC |
285 | }; |
286 | ||
29229052 XS |
287 | static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { |
288 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, | |
c43fd774 | 289 | .allow_runtime_pm = true, |
29229052 XS |
290 | }; |
291 | ||
0d013bcf AH |
292 | static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { |
293 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, | |
f3c55a7b | 294 | .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, |
c43fd774 | 295 | .allow_runtime_pm = true, |
93933508 | 296 | .probe_slot = mfd_sdio_probe_slot, |
0d013bcf AH |
297 | }; |
298 | ||
299 | static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { | |
29229052 | 300 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, |
c43fd774 | 301 | .allow_runtime_pm = true, |
0d013bcf | 302 | .probe_slot = mfd_emmc_probe_slot, |
29229052 XS |
303 | }; |
304 | ||
296e0b03 AS |
305 | static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { |
306 | .quirks = SDHCI_QUIRK_BROKEN_ADMA, | |
307 | .probe_slot = pch_hc_probe_slot, | |
308 | }; | |
309 | ||
728ef3d1 AH |
310 | static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) |
311 | { | |
312 | slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; | |
313 | slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ; | |
314 | return 0; | |
315 | } | |
316 | ||
317 | static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) | |
318 | { | |
319 | slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; | |
320 | return 0; | |
321 | } | |
322 | ||
323 | static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { | |
324 | .allow_runtime_pm = true, | |
325 | .probe_slot = byt_emmc_probe_slot, | |
326 | }; | |
327 | ||
328 | static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { | |
329 | .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, | |
330 | .allow_runtime_pm = true, | |
331 | .probe_slot = byt_sdio_probe_slot, | |
332 | }; | |
333 | ||
334 | static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { | |
335 | }; | |
336 | ||
26daa1ed JL |
337 | /* O2Micro extra registers */ |
338 | #define O2_SD_LOCK_WP 0xD3 | |
339 | #define O2_SD_MULTI_VCC3V 0xEE | |
340 | #define O2_SD_CLKREQ 0xEC | |
341 | #define O2_SD_CAPS 0xE0 | |
342 | #define O2_SD_ADMA1 0xE2 | |
343 | #define O2_SD_ADMA2 0xE7 | |
344 | #define O2_SD_INF_MOD 0xF1 | |
345 | ||
346 | static int o2_probe(struct sdhci_pci_chip *chip) | |
347 | { | |
348 | int ret; | |
349 | u8 scratch; | |
350 | ||
351 | switch (chip->pdev->device) { | |
352 | case PCI_DEVICE_ID_O2_8220: | |
353 | case PCI_DEVICE_ID_O2_8221: | |
354 | case PCI_DEVICE_ID_O2_8320: | |
355 | case PCI_DEVICE_ID_O2_8321: | |
356 | /* This extra setup is required due to broken ADMA. */ | |
357 | ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); | |
358 | if (ret) | |
359 | return ret; | |
360 | scratch &= 0x7f; | |
361 | pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); | |
362 | ||
363 | /* Set Multi 3 to VCC3V# */ | |
364 | pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08); | |
365 | ||
366 | /* Disable CLK_REQ# support after media DET */ | |
367 | ret = pci_read_config_byte(chip->pdev, O2_SD_CLKREQ, &scratch); | |
368 | if (ret) | |
369 | return ret; | |
370 | scratch |= 0x20; | |
371 | pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch); | |
372 | ||
373 | /* Choose capabilities, enable SDMA. We have to write 0x01 | |
374 | * to the capabilities register first to unlock it. | |
375 | */ | |
376 | ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch); | |
377 | if (ret) | |
378 | return ret; | |
379 | scratch |= 0x01; | |
380 | pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch); | |
381 | pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73); | |
382 | ||
383 | /* Disable ADMA1/2 */ | |
384 | pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39); | |
385 | pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08); | |
386 | ||
387 | /* Disable the infinite transfer mode */ | |
388 | ret = pci_read_config_byte(chip->pdev, O2_SD_INF_MOD, &scratch); | |
389 | if (ret) | |
390 | return ret; | |
391 | scratch |= 0x08; | |
392 | pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch); | |
393 | ||
394 | /* Lock WP */ | |
395 | ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); | |
396 | if (ret) | |
397 | return ret; | |
398 | scratch |= 0x80; | |
399 | pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); | |
400 | } | |
401 | ||
402 | return 0; | |
403 | } | |
404 | ||
45211e21 PO |
405 | static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) |
406 | { | |
407 | u8 scratch; | |
408 | int ret; | |
409 | ||
410 | ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); | |
411 | if (ret) | |
412 | return ret; | |
413 | ||
414 | /* | |
415 | * Turn PMOS on [bit 0], set over current detection to 2.4 V | |
416 | * [bit 1:2] and enable over current debouncing [bit 6]. | |
417 | */ | |
418 | if (on) | |
419 | scratch |= 0x47; | |
420 | else | |
421 | scratch &= ~0x47; | |
422 | ||
423 | ret = pci_write_config_byte(chip->pdev, 0xAE, scratch); | |
424 | if (ret) | |
425 | return ret; | |
426 | ||
427 | return 0; | |
428 | } | |
429 | ||
430 | static int jmicron_probe(struct sdhci_pci_chip *chip) | |
431 | { | |
432 | int ret; | |
8f230f45 | 433 | u16 mmcdev = 0; |
45211e21 | 434 | |
93fc48c7 PO |
435 | if (chip->pdev->revision == 0) { |
436 | chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | | |
437 | SDHCI_QUIRK_32BIT_DMA_SIZE | | |
2134a922 | 438 | SDHCI_QUIRK_32BIT_ADMA_SIZE | |
4a3cba32 | 439 | SDHCI_QUIRK_RESET_AFTER_REQUEST | |
86a6a874 | 440 | SDHCI_QUIRK_BROKEN_SMALL_PIO; |
93fc48c7 PO |
441 | } |
442 | ||
4489428a PO |
443 | /* |
444 | * JMicron chips can have two interfaces to the same hardware | |
445 | * in order to work around limitations in Microsoft's driver. | |
446 | * We need to make sure we only bind to one of them. | |
447 | * | |
448 | * This code assumes two things: | |
449 | * | |
450 | * 1. The PCI code adds subfunctions in order. | |
451 | * | |
452 | * 2. The MMC interface has a lower subfunction number | |
453 | * than the SD interface. | |
454 | */ | |
8f230f45 TI |
455 | if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) |
456 | mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; | |
457 | else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) | |
458 | mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; | |
459 | ||
460 | if (mmcdev) { | |
4489428a PO |
461 | struct pci_dev *sd_dev; |
462 | ||
463 | sd_dev = NULL; | |
464 | while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, | |
8f230f45 | 465 | mmcdev, sd_dev)) != NULL) { |
4489428a PO |
466 | if ((PCI_SLOT(chip->pdev->devfn) == |
467 | PCI_SLOT(sd_dev->devfn)) && | |
468 | (chip->pdev->bus == sd_dev->bus)) | |
469 | break; | |
470 | } | |
471 | ||
472 | if (sd_dev) { | |
473 | pci_dev_put(sd_dev); | |
474 | dev_info(&chip->pdev->dev, "Refusing to bind to " | |
475 | "secondary interface.\n"); | |
476 | return -ENODEV; | |
477 | } | |
478 | } | |
479 | ||
45211e21 PO |
480 | /* |
481 | * JMicron chips need a bit of a nudge to enable the power | |
482 | * output pins. | |
483 | */ | |
484 | ret = jmicron_pmos(chip, 1); | |
485 | if (ret) { | |
486 | dev_err(&chip->pdev->dev, "Failure enabling card power\n"); | |
487 | return ret; | |
488 | } | |
489 | ||
82b0e23a TI |
490 | /* quirk for unsable RO-detection on JM388 chips */ |
491 | if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || | |
492 | chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) | |
493 | chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; | |
494 | ||
45211e21 PO |
495 | return 0; |
496 | } | |
497 | ||
4489428a PO |
498 | static void jmicron_enable_mmc(struct sdhci_host *host, int on) |
499 | { | |
500 | u8 scratch; | |
501 | ||
502 | scratch = readb(host->ioaddr + 0xC0); | |
503 | ||
504 | if (on) | |
505 | scratch |= 0x01; | |
506 | else | |
507 | scratch &= ~0x01; | |
508 | ||
509 | writeb(scratch, host->ioaddr + 0xC0); | |
510 | } | |
511 | ||
512 | static int jmicron_probe_slot(struct sdhci_pci_slot *slot) | |
513 | { | |
2134a922 PO |
514 | if (slot->chip->pdev->revision == 0) { |
515 | u16 version; | |
516 | ||
517 | version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); | |
518 | version = (version & SDHCI_VENDOR_VER_MASK) >> | |
519 | SDHCI_VENDOR_VER_SHIFT; | |
520 | ||
521 | /* | |
522 | * Older versions of the chip have lots of nasty glitches | |
523 | * in the ADMA engine. It's best just to avoid it | |
524 | * completely. | |
525 | */ | |
526 | if (version < 0xAC) | |
527 | slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; | |
528 | } | |
529 | ||
8f230f45 TI |
530 | /* JM388 MMC doesn't support 1.8V while SD supports it */ |
531 | if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { | |
532 | slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | | |
533 | MMC_VDD_29_30 | MMC_VDD_30_31 | | |
534 | MMC_VDD_165_195; /* allow 1.8V */ | |
535 | slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | | |
536 | MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ | |
537 | } | |
538 | ||
4489428a PO |
539 | /* |
540 | * The secondary interface requires a bit set to get the | |
541 | * interrupts. | |
542 | */ | |
8f230f45 TI |
543 | if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || |
544 | slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) | |
4489428a PO |
545 | jmicron_enable_mmc(slot->host, 1); |
546 | ||
d75c1084 TI |
547 | slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; |
548 | ||
4489428a PO |
549 | return 0; |
550 | } | |
551 | ||
1e72859e | 552 | static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) |
4489428a | 553 | { |
1e72859e PO |
554 | if (dead) |
555 | return; | |
556 | ||
8f230f45 TI |
557 | if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || |
558 | slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) | |
4489428a PO |
559 | jmicron_enable_mmc(slot->host, 0); |
560 | } | |
561 | ||
29495aa0 | 562 | static int jmicron_suspend(struct sdhci_pci_chip *chip) |
4489428a PO |
563 | { |
564 | int i; | |
565 | ||
8f230f45 TI |
566 | if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || |
567 | chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { | |
b177bc91 | 568 | for (i = 0; i < chip->num_slots; i++) |
4489428a PO |
569 | jmicron_enable_mmc(chip->slots[i]->host, 0); |
570 | } | |
571 | ||
572 | return 0; | |
573 | } | |
574 | ||
45211e21 PO |
575 | static int jmicron_resume(struct sdhci_pci_chip *chip) |
576 | { | |
4489428a PO |
577 | int ret, i; |
578 | ||
8f230f45 TI |
579 | if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || |
580 | chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { | |
b177bc91 | 581 | for (i = 0; i < chip->num_slots; i++) |
4489428a PO |
582 | jmicron_enable_mmc(chip->slots[i]->host, 1); |
583 | } | |
45211e21 PO |
584 | |
585 | ret = jmicron_pmos(chip, 1); | |
586 | if (ret) { | |
587 | dev_err(&chip->pdev->dev, "Failure enabling card power\n"); | |
588 | return ret; | |
589 | } | |
590 | ||
591 | return 0; | |
592 | } | |
593 | ||
26daa1ed JL |
594 | static const struct sdhci_pci_fixes sdhci_o2 = { |
595 | .probe = o2_probe, | |
596 | }; | |
597 | ||
22606405 | 598 | static const struct sdhci_pci_fixes sdhci_jmicron = { |
45211e21 PO |
599 | .probe = jmicron_probe, |
600 | ||
4489428a PO |
601 | .probe_slot = jmicron_probe_slot, |
602 | .remove_slot = jmicron_remove_slot, | |
603 | ||
604 | .suspend = jmicron_suspend, | |
45211e21 | 605 | .resume = jmicron_resume, |
22606405 PO |
606 | }; |
607 | ||
a7a6186c NP |
608 | /* SysKonnect CardBus2SDIO extra registers */ |
609 | #define SYSKT_CTRL 0x200 | |
610 | #define SYSKT_RDFIFO_STAT 0x204 | |
611 | #define SYSKT_WRFIFO_STAT 0x208 | |
612 | #define SYSKT_POWER_DATA 0x20c | |
613 | #define SYSKT_POWER_330 0xef | |
614 | #define SYSKT_POWER_300 0xf8 | |
615 | #define SYSKT_POWER_184 0xcc | |
616 | #define SYSKT_POWER_CMD 0x20d | |
617 | #define SYSKT_POWER_START (1 << 7) | |
618 | #define SYSKT_POWER_STATUS 0x20e | |
619 | #define SYSKT_POWER_STATUS_OK (1 << 0) | |
620 | #define SYSKT_BOARD_REV 0x210 | |
621 | #define SYSKT_CHIP_REV 0x211 | |
622 | #define SYSKT_CONF_DATA 0x212 | |
623 | #define SYSKT_CONF_DATA_1V8 (1 << 2) | |
624 | #define SYSKT_CONF_DATA_2V5 (1 << 1) | |
625 | #define SYSKT_CONF_DATA_3V3 (1 << 0) | |
626 | ||
627 | static int syskt_probe(struct sdhci_pci_chip *chip) | |
628 | { | |
629 | if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { | |
630 | chip->pdev->class &= ~0x0000FF; | |
631 | chip->pdev->class |= PCI_SDHCI_IFDMA; | |
632 | } | |
633 | return 0; | |
634 | } | |
635 | ||
636 | static int syskt_probe_slot(struct sdhci_pci_slot *slot) | |
637 | { | |
638 | int tm, ps; | |
639 | ||
640 | u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); | |
641 | u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); | |
642 | dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " | |
643 | "board rev %d.%d, chip rev %d.%d\n", | |
644 | board_rev >> 4, board_rev & 0xf, | |
645 | chip_rev >> 4, chip_rev & 0xf); | |
646 | if (chip_rev >= 0x20) | |
647 | slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; | |
648 | ||
649 | writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); | |
650 | writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); | |
651 | udelay(50); | |
652 | tm = 10; /* Wait max 1 ms */ | |
653 | do { | |
654 | ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); | |
655 | if (ps & SYSKT_POWER_STATUS_OK) | |
656 | break; | |
657 | udelay(100); | |
658 | } while (--tm); | |
659 | if (!tm) { | |
660 | dev_err(&slot->chip->pdev->dev, | |
661 | "power regulator never stabilized"); | |
662 | writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); | |
663 | return -ENODEV; | |
664 | } | |
665 | ||
666 | return 0; | |
667 | } | |
668 | ||
669 | static const struct sdhci_pci_fixes sdhci_syskt = { | |
670 | .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, | |
671 | .probe = syskt_probe, | |
672 | .probe_slot = syskt_probe_slot, | |
673 | }; | |
674 | ||
557b0697 HW |
675 | static int via_probe(struct sdhci_pci_chip *chip) |
676 | { | |
677 | if (chip->pdev->revision == 0x10) | |
678 | chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; | |
679 | ||
680 | return 0; | |
681 | } | |
682 | ||
683 | static const struct sdhci_pci_fixes sdhci_via = { | |
684 | .probe = via_probe, | |
685 | }; | |
686 | ||
9647f84d | 687 | static const struct pci_device_id pci_ids[] = { |
b8c86fc5 PO |
688 | { |
689 | .vendor = PCI_VENDOR_ID_RICOH, | |
690 | .device = PCI_DEVICE_ID_RICOH_R5C822, | |
22606405 | 691 | .subvendor = PCI_ANY_ID, |
b8c86fc5 | 692 | .subdevice = PCI_ANY_ID, |
22606405 | 693 | .driver_data = (kernel_ulong_t)&sdhci_ricoh, |
b8c86fc5 PO |
694 | }, |
695 | ||
ccc92c23 ML |
696 | { |
697 | .vendor = PCI_VENDOR_ID_RICOH, | |
698 | .device = 0x843, | |
699 | .subvendor = PCI_ANY_ID, | |
700 | .subdevice = PCI_ANY_ID, | |
701 | .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, | |
702 | }, | |
703 | ||
568133eb PC |
704 | { |
705 | .vendor = PCI_VENDOR_ID_RICOH, | |
706 | .device = 0xe822, | |
707 | .subvendor = PCI_ANY_ID, | |
708 | .subdevice = PCI_ANY_ID, | |
709 | .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, | |
710 | }, | |
711 | ||
5fd11c07 MI |
712 | { |
713 | .vendor = PCI_VENDOR_ID_RICOH, | |
714 | .device = 0xe823, | |
715 | .subvendor = PCI_ANY_ID, | |
716 | .subdevice = PCI_ANY_ID, | |
717 | .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, | |
718 | }, | |
719 | ||
b8c86fc5 PO |
720 | { |
721 | .vendor = PCI_VENDOR_ID_ENE, | |
722 | .device = PCI_DEVICE_ID_ENE_CB712_SD, | |
723 | .subvendor = PCI_ANY_ID, | |
724 | .subdevice = PCI_ANY_ID, | |
22606405 | 725 | .driver_data = (kernel_ulong_t)&sdhci_ene_712, |
b8c86fc5 PO |
726 | }, |
727 | ||
728 | { | |
729 | .vendor = PCI_VENDOR_ID_ENE, | |
730 | .device = PCI_DEVICE_ID_ENE_CB712_SD_2, | |
731 | .subvendor = PCI_ANY_ID, | |
732 | .subdevice = PCI_ANY_ID, | |
22606405 | 733 | .driver_data = (kernel_ulong_t)&sdhci_ene_712, |
b8c86fc5 PO |
734 | }, |
735 | ||
736 | { | |
737 | .vendor = PCI_VENDOR_ID_ENE, | |
738 | .device = PCI_DEVICE_ID_ENE_CB714_SD, | |
739 | .subvendor = PCI_ANY_ID, | |
740 | .subdevice = PCI_ANY_ID, | |
22606405 | 741 | .driver_data = (kernel_ulong_t)&sdhci_ene_714, |
b8c86fc5 PO |
742 | }, |
743 | ||
744 | { | |
745 | .vendor = PCI_VENDOR_ID_ENE, | |
746 | .device = PCI_DEVICE_ID_ENE_CB714_SD_2, | |
747 | .subvendor = PCI_ANY_ID, | |
748 | .subdevice = PCI_ANY_ID, | |
22606405 | 749 | .driver_data = (kernel_ulong_t)&sdhci_ene_714, |
b8c86fc5 PO |
750 | }, |
751 | ||
752 | { | |
753 | .vendor = PCI_VENDOR_ID_MARVELL, | |
8c5eb880 | 754 | .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD, |
b8c86fc5 PO |
755 | .subvendor = PCI_ANY_ID, |
756 | .subdevice = PCI_ANY_ID, | |
22606405 | 757 | .driver_data = (kernel_ulong_t)&sdhci_cafe, |
b8c86fc5 PO |
758 | }, |
759 | ||
760 | { | |
761 | .vendor = PCI_VENDOR_ID_JMICRON, | |
762 | .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD, | |
763 | .subvendor = PCI_ANY_ID, | |
764 | .subdevice = PCI_ANY_ID, | |
22606405 | 765 | .driver_data = (kernel_ulong_t)&sdhci_jmicron, |
b8c86fc5 PO |
766 | }, |
767 | ||
4489428a PO |
768 | { |
769 | .vendor = PCI_VENDOR_ID_JMICRON, | |
770 | .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC, | |
771 | .subvendor = PCI_ANY_ID, | |
772 | .subdevice = PCI_ANY_ID, | |
773 | .driver_data = (kernel_ulong_t)&sdhci_jmicron, | |
8f230f45 TI |
774 | }, |
775 | ||
776 | { | |
777 | .vendor = PCI_VENDOR_ID_JMICRON, | |
778 | .device = PCI_DEVICE_ID_JMICRON_JMB388_SD, | |
779 | .subvendor = PCI_ANY_ID, | |
780 | .subdevice = PCI_ANY_ID, | |
781 | .driver_data = (kernel_ulong_t)&sdhci_jmicron, | |
782 | }, | |
783 | ||
784 | { | |
785 | .vendor = PCI_VENDOR_ID_JMICRON, | |
786 | .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD, | |
787 | .subvendor = PCI_ANY_ID, | |
788 | .subdevice = PCI_ANY_ID, | |
789 | .driver_data = (kernel_ulong_t)&sdhci_jmicron, | |
4489428a PO |
790 | }, |
791 | ||
a7a6186c NP |
792 | { |
793 | .vendor = PCI_VENDOR_ID_SYSKONNECT, | |
794 | .device = 0x8000, | |
795 | .subvendor = PCI_ANY_ID, | |
796 | .subdevice = PCI_ANY_ID, | |
797 | .driver_data = (kernel_ulong_t)&sdhci_syskt, | |
798 | }, | |
799 | ||
557b0697 HW |
800 | { |
801 | .vendor = PCI_VENDOR_ID_VIA, | |
802 | .device = 0x95d0, | |
803 | .subvendor = PCI_ANY_ID, | |
804 | .subdevice = PCI_ANY_ID, | |
805 | .driver_data = (kernel_ulong_t)&sdhci_via, | |
806 | }, | |
807 | ||
29229052 XS |
808 | { |
809 | .vendor = PCI_VENDOR_ID_INTEL, | |
f9ee3eab AC |
810 | .device = PCI_DEVICE_ID_INTEL_MRST_SD0, |
811 | .subvendor = PCI_ANY_ID, | |
812 | .subdevice = PCI_ANY_ID, | |
813 | .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0, | |
814 | }, | |
815 | ||
816 | { | |
817 | .vendor = PCI_VENDOR_ID_INTEL, | |
818 | .device = PCI_DEVICE_ID_INTEL_MRST_SD1, | |
819 | .subvendor = PCI_ANY_ID, | |
820 | .subdevice = PCI_ANY_ID, | |
35ac6f08 JP |
821 | .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, |
822 | }, | |
823 | ||
824 | { | |
825 | .vendor = PCI_VENDOR_ID_INTEL, | |
826 | .device = PCI_DEVICE_ID_INTEL_MRST_SD2, | |
827 | .subvendor = PCI_ANY_ID, | |
828 | .subdevice = PCI_ANY_ID, | |
829 | .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, | |
f9ee3eab AC |
830 | }, |
831 | ||
832 | { | |
833 | .vendor = PCI_VENDOR_ID_INTEL, | |
29229052 XS |
834 | .device = PCI_DEVICE_ID_INTEL_MFD_SD, |
835 | .subvendor = PCI_ANY_ID, | |
836 | .subdevice = PCI_ANY_ID, | |
837 | .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, | |
838 | }, | |
839 | ||
840 | { | |
841 | .vendor = PCI_VENDOR_ID_INTEL, | |
842 | .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1, | |
843 | .subvendor = PCI_ANY_ID, | |
844 | .subdevice = PCI_ANY_ID, | |
0d013bcf | 845 | .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, |
29229052 XS |
846 | }, |
847 | ||
848 | { | |
849 | .vendor = PCI_VENDOR_ID_INTEL, | |
850 | .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2, | |
851 | .subvendor = PCI_ANY_ID, | |
852 | .subdevice = PCI_ANY_ID, | |
0d013bcf | 853 | .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, |
29229052 XS |
854 | }, |
855 | ||
856 | { | |
857 | .vendor = PCI_VENDOR_ID_INTEL, | |
858 | .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0, | |
859 | .subvendor = PCI_ANY_ID, | |
860 | .subdevice = PCI_ANY_ID, | |
0d013bcf | 861 | .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, |
29229052 XS |
862 | }, |
863 | ||
864 | { | |
865 | .vendor = PCI_VENDOR_ID_INTEL, | |
866 | .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1, | |
867 | .subvendor = PCI_ANY_ID, | |
868 | .subdevice = PCI_ANY_ID, | |
0d013bcf | 869 | .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, |
29229052 XS |
870 | }, |
871 | ||
296e0b03 AS |
872 | { |
873 | .vendor = PCI_VENDOR_ID_INTEL, | |
874 | .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0, | |
875 | .subvendor = PCI_ANY_ID, | |
876 | .subdevice = PCI_ANY_ID, | |
877 | .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, | |
878 | }, | |
879 | ||
880 | { | |
881 | .vendor = PCI_VENDOR_ID_INTEL, | |
882 | .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1, | |
883 | .subvendor = PCI_ANY_ID, | |
884 | .subdevice = PCI_ANY_ID, | |
885 | .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, | |
886 | }, | |
887 | ||
728ef3d1 AH |
888 | { |
889 | .vendor = PCI_VENDOR_ID_INTEL, | |
890 | .device = PCI_DEVICE_ID_INTEL_BYT_EMMC, | |
891 | .subvendor = PCI_ANY_ID, | |
892 | .subdevice = PCI_ANY_ID, | |
893 | .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, | |
894 | }, | |
895 | ||
896 | { | |
897 | .vendor = PCI_VENDOR_ID_INTEL, | |
898 | .device = PCI_DEVICE_ID_INTEL_BYT_SDIO, | |
899 | .subvendor = PCI_ANY_ID, | |
900 | .subdevice = PCI_ANY_ID, | |
901 | .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, | |
902 | }, | |
903 | ||
904 | { | |
905 | .vendor = PCI_VENDOR_ID_INTEL, | |
906 | .device = PCI_DEVICE_ID_INTEL_BYT_SD, | |
907 | .subvendor = PCI_ANY_ID, | |
908 | .subdevice = PCI_ANY_ID, | |
909 | .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, | |
910 | }, | |
911 | ||
26daa1ed JL |
912 | { |
913 | .vendor = PCI_VENDOR_ID_O2, | |
914 | .device = PCI_DEVICE_ID_O2_8120, | |
915 | .subvendor = PCI_ANY_ID, | |
916 | .subdevice = PCI_ANY_ID, | |
917 | .driver_data = (kernel_ulong_t)&sdhci_o2, | |
918 | }, | |
919 | ||
920 | { | |
921 | .vendor = PCI_VENDOR_ID_O2, | |
922 | .device = PCI_DEVICE_ID_O2_8220, | |
923 | .subvendor = PCI_ANY_ID, | |
924 | .subdevice = PCI_ANY_ID, | |
925 | .driver_data = (kernel_ulong_t)&sdhci_o2, | |
926 | }, | |
927 | ||
928 | { | |
929 | .vendor = PCI_VENDOR_ID_O2, | |
930 | .device = PCI_DEVICE_ID_O2_8221, | |
931 | .subvendor = PCI_ANY_ID, | |
932 | .subdevice = PCI_ANY_ID, | |
933 | .driver_data = (kernel_ulong_t)&sdhci_o2, | |
934 | }, | |
935 | ||
936 | { | |
937 | .vendor = PCI_VENDOR_ID_O2, | |
938 | .device = PCI_DEVICE_ID_O2_8320, | |
939 | .subvendor = PCI_ANY_ID, | |
940 | .subdevice = PCI_ANY_ID, | |
941 | .driver_data = (kernel_ulong_t)&sdhci_o2, | |
942 | }, | |
943 | ||
944 | { | |
945 | .vendor = PCI_VENDOR_ID_O2, | |
946 | .device = PCI_DEVICE_ID_O2_8321, | |
947 | .subvendor = PCI_ANY_ID, | |
948 | .subdevice = PCI_ANY_ID, | |
949 | .driver_data = (kernel_ulong_t)&sdhci_o2, | |
950 | }, | |
951 | ||
b8c86fc5 PO |
952 | { /* Generic SD host controller */ |
953 | PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) | |
954 | }, | |
955 | ||
956 | { /* end: all zeroes */ }, | |
957 | }; | |
958 | ||
959 | MODULE_DEVICE_TABLE(pci, pci_ids); | |
960 | ||
b8c86fc5 PO |
961 | /*****************************************************************************\ |
962 | * * | |
963 | * SDHCI core callbacks * | |
964 | * * | |
965 | \*****************************************************************************/ | |
966 | ||
967 | static int sdhci_pci_enable_dma(struct sdhci_host *host) | |
968 | { | |
969 | struct sdhci_pci_slot *slot; | |
970 | struct pci_dev *pdev; | |
971 | int ret; | |
972 | ||
973 | slot = sdhci_priv(host); | |
974 | pdev = slot->chip->pdev; | |
975 | ||
976 | if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && | |
977 | ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && | |
a13abc7b | 978 | (host->flags & SDHCI_USE_SDMA)) { |
b8c86fc5 PO |
979 | dev_warn(&pdev->dev, "Will use DMA mode even though HW " |
980 | "doesn't fully claim to support it.\n"); | |
981 | } | |
982 | ||
284901a9 | 983 | ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
b8c86fc5 PO |
984 | if (ret) |
985 | return ret; | |
986 | ||
987 | pci_set_master(pdev); | |
988 | ||
989 | return 0; | |
990 | } | |
991 | ||
7bc088d3 | 992 | static int sdhci_pci_bus_width(struct sdhci_host *host, int width) |
68077b02 ML |
993 | { |
994 | u8 ctrl; | |
995 | ||
996 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); | |
997 | ||
998 | switch (width) { | |
999 | case MMC_BUS_WIDTH_8: | |
1000 | ctrl |= SDHCI_CTRL_8BITBUS; | |
1001 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
1002 | break; | |
1003 | case MMC_BUS_WIDTH_4: | |
1004 | ctrl |= SDHCI_CTRL_4BITBUS; | |
1005 | ctrl &= ~SDHCI_CTRL_8BITBUS; | |
1006 | break; | |
1007 | default: | |
1008 | ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS); | |
1009 | break; | |
1010 | } | |
1011 | ||
1012 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
1013 | ||
1014 | return 0; | |
1015 | } | |
1016 | ||
0f201655 AH |
1017 | static void sdhci_pci_hw_reset(struct sdhci_host *host) |
1018 | { | |
1019 | struct sdhci_pci_slot *slot = sdhci_priv(host); | |
1020 | int rst_n_gpio = slot->rst_n_gpio; | |
1021 | ||
1022 | if (!gpio_is_valid(rst_n_gpio)) | |
1023 | return; | |
1024 | gpio_set_value_cansleep(rst_n_gpio, 0); | |
1025 | /* For eMMC, minimum is 1us but give it 10us for good measure */ | |
1026 | udelay(10); | |
1027 | gpio_set_value_cansleep(rst_n_gpio, 1); | |
1028 | /* For eMMC, minimum is 200us but give it 300us for good measure */ | |
1029 | usleep_range(300, 1000); | |
1030 | } | |
1031 | ||
c915568d | 1032 | static const struct sdhci_ops sdhci_pci_ops = { |
b8c86fc5 | 1033 | .enable_dma = sdhci_pci_enable_dma, |
7bc088d3 | 1034 | .platform_bus_width = sdhci_pci_bus_width, |
0f201655 | 1035 | .hw_reset = sdhci_pci_hw_reset, |
b8c86fc5 PO |
1036 | }; |
1037 | ||
1038 | /*****************************************************************************\ | |
1039 | * * | |
1040 | * Suspend/resume * | |
1041 | * * | |
1042 | \*****************************************************************************/ | |
1043 | ||
1044 | #ifdef CONFIG_PM | |
1045 | ||
29495aa0 | 1046 | static int sdhci_pci_suspend(struct device *dev) |
b8c86fc5 | 1047 | { |
29495aa0 | 1048 | struct pci_dev *pdev = to_pci_dev(dev); |
b8c86fc5 PO |
1049 | struct sdhci_pci_chip *chip; |
1050 | struct sdhci_pci_slot *slot; | |
5f619704 | 1051 | mmc_pm_flag_t slot_pm_flags; |
2f4cbb3d | 1052 | mmc_pm_flag_t pm_flags = 0; |
b8c86fc5 PO |
1053 | int i, ret; |
1054 | ||
1055 | chip = pci_get_drvdata(pdev); | |
1056 | if (!chip) | |
1057 | return 0; | |
1058 | ||
b177bc91 | 1059 | for (i = 0; i < chip->num_slots; i++) { |
b8c86fc5 PO |
1060 | slot = chip->slots[i]; |
1061 | if (!slot) | |
1062 | continue; | |
1063 | ||
29495aa0 | 1064 | ret = sdhci_suspend_host(slot->host); |
b8c86fc5 | 1065 | |
b678b91f AL |
1066 | if (ret) |
1067 | goto err_pci_suspend; | |
2f4cbb3d | 1068 | |
5f619704 DD |
1069 | slot_pm_flags = slot->host->mmc->pm_flags; |
1070 | if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ) | |
1071 | sdhci_enable_irq_wakeups(slot->host); | |
1072 | ||
1073 | pm_flags |= slot_pm_flags; | |
b8c86fc5 PO |
1074 | } |
1075 | ||
4489428a | 1076 | if (chip->fixes && chip->fixes->suspend) { |
29495aa0 | 1077 | ret = chip->fixes->suspend(chip); |
b678b91f AL |
1078 | if (ret) |
1079 | goto err_pci_suspend; | |
4489428a PO |
1080 | } |
1081 | ||
b8c86fc5 | 1082 | pci_save_state(pdev); |
2f4cbb3d | 1083 | if (pm_flags & MMC_PM_KEEP_POWER) { |
5f619704 DD |
1084 | if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) { |
1085 | pci_pme_active(pdev, true); | |
2f4cbb3d | 1086 | pci_enable_wake(pdev, PCI_D3hot, 1); |
5f619704 | 1087 | } |
2f4cbb3d NP |
1088 | pci_set_power_state(pdev, PCI_D3hot); |
1089 | } else { | |
29495aa0 | 1090 | pci_enable_wake(pdev, PCI_D3hot, 0); |
2f4cbb3d | 1091 | pci_disable_device(pdev); |
29495aa0 | 1092 | pci_set_power_state(pdev, PCI_D3hot); |
2f4cbb3d | 1093 | } |
b8c86fc5 PO |
1094 | |
1095 | return 0; | |
b678b91f AL |
1096 | |
1097 | err_pci_suspend: | |
1098 | while (--i >= 0) | |
1099 | sdhci_resume_host(chip->slots[i]->host); | |
1100 | return ret; | |
b8c86fc5 PO |
1101 | } |
1102 | ||
29495aa0 | 1103 | static int sdhci_pci_resume(struct device *dev) |
b8c86fc5 | 1104 | { |
29495aa0 | 1105 | struct pci_dev *pdev = to_pci_dev(dev); |
b8c86fc5 PO |
1106 | struct sdhci_pci_chip *chip; |
1107 | struct sdhci_pci_slot *slot; | |
1108 | int i, ret; | |
1109 | ||
1110 | chip = pci_get_drvdata(pdev); | |
1111 | if (!chip) | |
1112 | return 0; | |
1113 | ||
1114 | pci_set_power_state(pdev, PCI_D0); | |
1115 | pci_restore_state(pdev); | |
1116 | ret = pci_enable_device(pdev); | |
1117 | if (ret) | |
1118 | return ret; | |
1119 | ||
45211e21 PO |
1120 | if (chip->fixes && chip->fixes->resume) { |
1121 | ret = chip->fixes->resume(chip); | |
1122 | if (ret) | |
1123 | return ret; | |
1124 | } | |
1125 | ||
b177bc91 | 1126 | for (i = 0; i < chip->num_slots; i++) { |
b8c86fc5 PO |
1127 | slot = chip->slots[i]; |
1128 | if (!slot) | |
1129 | continue; | |
1130 | ||
1131 | ret = sdhci_resume_host(slot->host); | |
1132 | if (ret) | |
1133 | return ret; | |
1134 | } | |
1135 | ||
1136 | return 0; | |
1137 | } | |
1138 | ||
1139 | #else /* CONFIG_PM */ | |
1140 | ||
1141 | #define sdhci_pci_suspend NULL | |
1142 | #define sdhci_pci_resume NULL | |
1143 | ||
1144 | #endif /* CONFIG_PM */ | |
1145 | ||
66fd8ad5 AH |
1146 | #ifdef CONFIG_PM_RUNTIME |
1147 | ||
1148 | static int sdhci_pci_runtime_suspend(struct device *dev) | |
1149 | { | |
1150 | struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); | |
1151 | struct sdhci_pci_chip *chip; | |
1152 | struct sdhci_pci_slot *slot; | |
66fd8ad5 AH |
1153 | int i, ret; |
1154 | ||
1155 | chip = pci_get_drvdata(pdev); | |
1156 | if (!chip) | |
1157 | return 0; | |
1158 | ||
1159 | for (i = 0; i < chip->num_slots; i++) { | |
1160 | slot = chip->slots[i]; | |
1161 | if (!slot) | |
1162 | continue; | |
1163 | ||
1164 | ret = sdhci_runtime_suspend_host(slot->host); | |
1165 | ||
b678b91f AL |
1166 | if (ret) |
1167 | goto err_pci_runtime_suspend; | |
66fd8ad5 AH |
1168 | } |
1169 | ||
1170 | if (chip->fixes && chip->fixes->suspend) { | |
29495aa0 | 1171 | ret = chip->fixes->suspend(chip); |
b678b91f AL |
1172 | if (ret) |
1173 | goto err_pci_runtime_suspend; | |
66fd8ad5 AH |
1174 | } |
1175 | ||
1176 | return 0; | |
b678b91f AL |
1177 | |
1178 | err_pci_runtime_suspend: | |
1179 | while (--i >= 0) | |
1180 | sdhci_runtime_resume_host(chip->slots[i]->host); | |
1181 | return ret; | |
66fd8ad5 AH |
1182 | } |
1183 | ||
1184 | static int sdhci_pci_runtime_resume(struct device *dev) | |
1185 | { | |
1186 | struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); | |
1187 | struct sdhci_pci_chip *chip; | |
1188 | struct sdhci_pci_slot *slot; | |
1189 | int i, ret; | |
1190 | ||
1191 | chip = pci_get_drvdata(pdev); | |
1192 | if (!chip) | |
1193 | return 0; | |
1194 | ||
1195 | if (chip->fixes && chip->fixes->resume) { | |
1196 | ret = chip->fixes->resume(chip); | |
1197 | if (ret) | |
1198 | return ret; | |
1199 | } | |
1200 | ||
1201 | for (i = 0; i < chip->num_slots; i++) { | |
1202 | slot = chip->slots[i]; | |
1203 | if (!slot) | |
1204 | continue; | |
1205 | ||
1206 | ret = sdhci_runtime_resume_host(slot->host); | |
1207 | if (ret) | |
1208 | return ret; | |
1209 | } | |
1210 | ||
1211 | return 0; | |
1212 | } | |
1213 | ||
1214 | static int sdhci_pci_runtime_idle(struct device *dev) | |
1215 | { | |
1216 | return 0; | |
1217 | } | |
1218 | ||
1219 | #else | |
1220 | ||
1221 | #define sdhci_pci_runtime_suspend NULL | |
1222 | #define sdhci_pci_runtime_resume NULL | |
1223 | #define sdhci_pci_runtime_idle NULL | |
1224 | ||
1225 | #endif | |
1226 | ||
1227 | static const struct dev_pm_ops sdhci_pci_pm_ops = { | |
29495aa0 ML |
1228 | .suspend = sdhci_pci_suspend, |
1229 | .resume = sdhci_pci_resume, | |
66fd8ad5 AH |
1230 | .runtime_suspend = sdhci_pci_runtime_suspend, |
1231 | .runtime_resume = sdhci_pci_runtime_resume, | |
1232 | .runtime_idle = sdhci_pci_runtime_idle, | |
1233 | }; | |
1234 | ||
b8c86fc5 PO |
1235 | /*****************************************************************************\ |
1236 | * * | |
1237 | * Device probing/removal * | |
1238 | * * | |
1239 | \*****************************************************************************/ | |
1240 | ||
c3be1efd | 1241 | static struct sdhci_pci_slot *sdhci_pci_probe_slot( |
52c506f0 AH |
1242 | struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, |
1243 | int slotno) | |
b8c86fc5 PO |
1244 | { |
1245 | struct sdhci_pci_slot *slot; | |
1246 | struct sdhci_host *host; | |
52c506f0 | 1247 | int ret, bar = first_bar + slotno; |
b8c86fc5 PO |
1248 | |
1249 | if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { | |
1250 | dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); | |
1251 | return ERR_PTR(-ENODEV); | |
1252 | } | |
1253 | ||
90b3e6c5 | 1254 | if (pci_resource_len(pdev, bar) < 0x100) { |
b8c86fc5 PO |
1255 | dev_err(&pdev->dev, "Invalid iomem size. You may " |
1256 | "experience problems.\n"); | |
1257 | } | |
1258 | ||
1259 | if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { | |
1260 | dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); | |
1261 | return ERR_PTR(-ENODEV); | |
1262 | } | |
1263 | ||
1264 | if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { | |
1265 | dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); | |
1266 | return ERR_PTR(-ENODEV); | |
1267 | } | |
1268 | ||
1269 | host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot)); | |
1270 | if (IS_ERR(host)) { | |
c60a32cd | 1271 | dev_err(&pdev->dev, "cannot allocate host\n"); |
dc0fd7b5 | 1272 | return ERR_CAST(host); |
b8c86fc5 PO |
1273 | } |
1274 | ||
1275 | slot = sdhci_priv(host); | |
1276 | ||
1277 | slot->chip = chip; | |
1278 | slot->host = host; | |
1279 | slot->pci_bar = bar; | |
0f201655 | 1280 | slot->rst_n_gpio = -EINVAL; |
c5e027a4 | 1281 | slot->cd_gpio = -EINVAL; |
b8c86fc5 | 1282 | |
52c506f0 AH |
1283 | /* Retrieve platform data if there is any */ |
1284 | if (*sdhci_pci_get_data) | |
1285 | slot->data = sdhci_pci_get_data(pdev, slotno); | |
1286 | ||
1287 | if (slot->data) { | |
1288 | if (slot->data->setup) { | |
1289 | ret = slot->data->setup(slot->data); | |
1290 | if (ret) { | |
1291 | dev_err(&pdev->dev, "platform setup failed\n"); | |
1292 | goto free; | |
1293 | } | |
1294 | } | |
c5e027a4 AH |
1295 | slot->rst_n_gpio = slot->data->rst_n_gpio; |
1296 | slot->cd_gpio = slot->data->cd_gpio; | |
52c506f0 AH |
1297 | } |
1298 | ||
b8c86fc5 PO |
1299 | host->hw_name = "PCI"; |
1300 | host->ops = &sdhci_pci_ops; | |
1301 | host->quirks = chip->quirks; | |
f3c55a7b | 1302 | host->quirks2 = chip->quirks2; |
b8c86fc5 PO |
1303 | |
1304 | host->irq = pdev->irq; | |
1305 | ||
1306 | ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc)); | |
1307 | if (ret) { | |
1308 | dev_err(&pdev->dev, "cannot request region\n"); | |
52c506f0 | 1309 | goto cleanup; |
b8c86fc5 PO |
1310 | } |
1311 | ||
092f82ed | 1312 | host->ioaddr = pci_ioremap_bar(pdev, bar); |
b8c86fc5 PO |
1313 | if (!host->ioaddr) { |
1314 | dev_err(&pdev->dev, "failed to remap registers\n"); | |
9fdcdbb0 | 1315 | ret = -ENOMEM; |
b8c86fc5 PO |
1316 | goto release; |
1317 | } | |
1318 | ||
4489428a PO |
1319 | if (chip->fixes && chip->fixes->probe_slot) { |
1320 | ret = chip->fixes->probe_slot(slot); | |
1321 | if (ret) | |
1322 | goto unmap; | |
1323 | } | |
1324 | ||
c5e027a4 AH |
1325 | if (gpio_is_valid(slot->rst_n_gpio)) { |
1326 | if (!gpio_request(slot->rst_n_gpio, "eMMC_reset")) { | |
1327 | gpio_direction_output(slot->rst_n_gpio, 1); | |
1328 | slot->host->mmc->caps |= MMC_CAP_HW_RESET; | |
1329 | } else { | |
1330 | dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); | |
1331 | slot->rst_n_gpio = -EINVAL; | |
1332 | } | |
1333 | } | |
1334 | ||
2f4cbb3d | 1335 | host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; |
eed222ac | 1336 | host->mmc->slotno = slotno; |
a08b17be | 1337 | host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; |
2f4cbb3d | 1338 | |
b8c86fc5 PO |
1339 | ret = sdhci_add_host(host); |
1340 | if (ret) | |
4489428a | 1341 | goto remove; |
b8c86fc5 | 1342 | |
c5e027a4 AH |
1343 | sdhci_pci_add_own_cd(slot); |
1344 | ||
b8c86fc5 PO |
1345 | return slot; |
1346 | ||
4489428a | 1347 | remove: |
c5e027a4 AH |
1348 | if (gpio_is_valid(slot->rst_n_gpio)) |
1349 | gpio_free(slot->rst_n_gpio); | |
1350 | ||
4489428a | 1351 | if (chip->fixes && chip->fixes->remove_slot) |
1e72859e | 1352 | chip->fixes->remove_slot(slot, 0); |
4489428a | 1353 | |
b8c86fc5 PO |
1354 | unmap: |
1355 | iounmap(host->ioaddr); | |
1356 | ||
1357 | release: | |
1358 | pci_release_region(pdev, bar); | |
c60a32cd | 1359 | |
52c506f0 AH |
1360 | cleanup: |
1361 | if (slot->data && slot->data->cleanup) | |
1362 | slot->data->cleanup(slot->data); | |
1363 | ||
c60a32cd | 1364 | free: |
b8c86fc5 PO |
1365 | sdhci_free_host(host); |
1366 | ||
1367 | return ERR_PTR(ret); | |
1368 | } | |
1369 | ||
1370 | static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) | |
1371 | { | |
1e72859e PO |
1372 | int dead; |
1373 | u32 scratch; | |
1374 | ||
c5e027a4 AH |
1375 | sdhci_pci_remove_own_cd(slot); |
1376 | ||
1e72859e PO |
1377 | dead = 0; |
1378 | scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); | |
1379 | if (scratch == (u32)-1) | |
1380 | dead = 1; | |
1381 | ||
1382 | sdhci_remove_host(slot->host, dead); | |
4489428a | 1383 | |
c5e027a4 AH |
1384 | if (gpio_is_valid(slot->rst_n_gpio)) |
1385 | gpio_free(slot->rst_n_gpio); | |
1386 | ||
4489428a | 1387 | if (slot->chip->fixes && slot->chip->fixes->remove_slot) |
1e72859e | 1388 | slot->chip->fixes->remove_slot(slot, dead); |
4489428a | 1389 | |
52c506f0 AH |
1390 | if (slot->data && slot->data->cleanup) |
1391 | slot->data->cleanup(slot->data); | |
1392 | ||
b8c86fc5 | 1393 | pci_release_region(slot->chip->pdev, slot->pci_bar); |
4489428a | 1394 | |
b8c86fc5 PO |
1395 | sdhci_free_host(slot->host); |
1396 | } | |
1397 | ||
c3be1efd | 1398 | static void sdhci_pci_runtime_pm_allow(struct device *dev) |
66fd8ad5 AH |
1399 | { |
1400 | pm_runtime_put_noidle(dev); | |
1401 | pm_runtime_allow(dev); | |
1402 | pm_runtime_set_autosuspend_delay(dev, 50); | |
1403 | pm_runtime_use_autosuspend(dev); | |
1404 | pm_suspend_ignore_children(dev, 1); | |
1405 | } | |
1406 | ||
6e0ee714 | 1407 | static void sdhci_pci_runtime_pm_forbid(struct device *dev) |
66fd8ad5 AH |
1408 | { |
1409 | pm_runtime_forbid(dev); | |
1410 | pm_runtime_get_noresume(dev); | |
1411 | } | |
1412 | ||
c3be1efd | 1413 | static int sdhci_pci_probe(struct pci_dev *pdev, |
b8c86fc5 PO |
1414 | const struct pci_device_id *ent) |
1415 | { | |
1416 | struct sdhci_pci_chip *chip; | |
1417 | struct sdhci_pci_slot *slot; | |
1418 | ||
cf5e23e1 | 1419 | u8 slots, first_bar; |
b8c86fc5 PO |
1420 | int ret, i; |
1421 | ||
1422 | BUG_ON(pdev == NULL); | |
1423 | BUG_ON(ent == NULL); | |
1424 | ||
b8c86fc5 | 1425 | dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", |
cf5e23e1 | 1426 | (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); |
b8c86fc5 PO |
1427 | |
1428 | ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); | |
1429 | if (ret) | |
1430 | return ret; | |
1431 | ||
1432 | slots = PCI_SLOT_INFO_SLOTS(slots) + 1; | |
1433 | dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); | |
1434 | if (slots == 0) | |
1435 | return -ENODEV; | |
1436 | ||
1437 | BUG_ON(slots > MAX_SLOTS); | |
1438 | ||
1439 | ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); | |
1440 | if (ret) | |
1441 | return ret; | |
1442 | ||
1443 | first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; | |
1444 | ||
1445 | if (first_bar > 5) { | |
1446 | dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); | |
1447 | return -ENODEV; | |
1448 | } | |
1449 | ||
1450 | ret = pci_enable_device(pdev); | |
1451 | if (ret) | |
1452 | return ret; | |
1453 | ||
1454 | chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL); | |
1455 | if (!chip) { | |
1456 | ret = -ENOMEM; | |
1457 | goto err; | |
1458 | } | |
1459 | ||
1460 | chip->pdev = pdev; | |
b177bc91 | 1461 | chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; |
c43fd774 | 1462 | if (chip->fixes) { |
22606405 | 1463 | chip->quirks = chip->fixes->quirks; |
f3c55a7b | 1464 | chip->quirks2 = chip->fixes->quirks2; |
c43fd774 AH |
1465 | chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; |
1466 | } | |
b8c86fc5 PO |
1467 | chip->num_slots = slots; |
1468 | ||
1469 | pci_set_drvdata(pdev, chip); | |
1470 | ||
22606405 PO |
1471 | if (chip->fixes && chip->fixes->probe) { |
1472 | ret = chip->fixes->probe(chip); | |
1473 | if (ret) | |
1474 | goto free; | |
1475 | } | |
1476 | ||
225d85fe AC |
1477 | slots = chip->num_slots; /* Quirk may have changed this */ |
1478 | ||
b177bc91 | 1479 | for (i = 0; i < slots; i++) { |
52c506f0 | 1480 | slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); |
b8c86fc5 | 1481 | if (IS_ERR(slot)) { |
b177bc91 | 1482 | for (i--; i >= 0; i--) |
b8c86fc5 PO |
1483 | sdhci_pci_remove_slot(chip->slots[i]); |
1484 | ret = PTR_ERR(slot); | |
1485 | goto free; | |
1486 | } | |
1487 | ||
1488 | chip->slots[i] = slot; | |
1489 | } | |
1490 | ||
c43fd774 AH |
1491 | if (chip->allow_runtime_pm) |
1492 | sdhci_pci_runtime_pm_allow(&pdev->dev); | |
66fd8ad5 | 1493 | |
b8c86fc5 PO |
1494 | return 0; |
1495 | ||
1496 | free: | |
1497 | pci_set_drvdata(pdev, NULL); | |
1498 | kfree(chip); | |
1499 | ||
1500 | err: | |
1501 | pci_disable_device(pdev); | |
1502 | return ret; | |
1503 | } | |
1504 | ||
6e0ee714 | 1505 | static void sdhci_pci_remove(struct pci_dev *pdev) |
b8c86fc5 PO |
1506 | { |
1507 | int i; | |
1508 | struct sdhci_pci_chip *chip; | |
1509 | ||
1510 | chip = pci_get_drvdata(pdev); | |
1511 | ||
1512 | if (chip) { | |
c43fd774 AH |
1513 | if (chip->allow_runtime_pm) |
1514 | sdhci_pci_runtime_pm_forbid(&pdev->dev); | |
1515 | ||
b177bc91 | 1516 | for (i = 0; i < chip->num_slots; i++) |
b8c86fc5 PO |
1517 | sdhci_pci_remove_slot(chip->slots[i]); |
1518 | ||
1519 | pci_set_drvdata(pdev, NULL); | |
1520 | kfree(chip); | |
1521 | } | |
1522 | ||
1523 | pci_disable_device(pdev); | |
1524 | } | |
1525 | ||
1526 | static struct pci_driver sdhci_driver = { | |
b177bc91 | 1527 | .name = "sdhci-pci", |
b8c86fc5 | 1528 | .id_table = pci_ids, |
b177bc91 | 1529 | .probe = sdhci_pci_probe, |
0433c143 | 1530 | .remove = sdhci_pci_remove, |
66fd8ad5 AH |
1531 | .driver = { |
1532 | .pm = &sdhci_pci_pm_ops | |
1533 | }, | |
b8c86fc5 PO |
1534 | }; |
1535 | ||
acc69646 | 1536 | module_pci_driver(sdhci_driver); |
b8c86fc5 | 1537 | |
32710e8f | 1538 | MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); |
b8c86fc5 PO |
1539 | MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); |
1540 | MODULE_LICENSE("GPL"); |