Commit | Line | Data |
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95f25efe WS |
1 | /* |
2 | * Freescale eSDHC i.MX controller driver for the platform bus. | |
3 | * | |
4 | * derived from the OF-version. | |
5 | * | |
6 | * Copyright (c) 2010 Pengutronix e.K. | |
035ff831 | 7 | * Author: Wolfram Sang <kernel@pengutronix.de> |
95f25efe WS |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License. | |
12 | */ | |
13 | ||
14 | #include <linux/io.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/clk.h> | |
0c6d49ce | 18 | #include <linux/gpio.h> |
66506f76 | 19 | #include <linux/module.h> |
e149860d | 20 | #include <linux/slab.h> |
95f25efe | 21 | #include <linux/mmc/host.h> |
58ac8177 RZ |
22 | #include <linux/mmc/mmc.h> |
23 | #include <linux/mmc/sdio.h> | |
fbe5fdd1 | 24 | #include <linux/mmc/slot-gpio.h> |
abfafc2d SG |
25 | #include <linux/of.h> |
26 | #include <linux/of_device.h> | |
27 | #include <linux/of_gpio.h> | |
e62d8b8f | 28 | #include <linux/pinctrl/consumer.h> |
82906b13 | 29 | #include <linux/platform_data/mmc-esdhc-imx.h> |
89d7e5c1 | 30 | #include <linux/pm_runtime.h> |
95f25efe WS |
31 | #include "sdhci-pltfm.h" |
32 | #include "sdhci-esdhc.h" | |
33 | ||
a215186d | 34 | #define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f |
60bf6396 | 35 | #define ESDHC_CTRL_D3CD 0x08 |
fd44954e | 36 | #define ESDHC_BURST_LEN_EN_INCR (1 << 27) |
58ac8177 | 37 | /* VENDOR SPEC register */ |
60bf6396 SG |
38 | #define ESDHC_VENDOR_SPEC 0xc0 |
39 | #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) | |
0322191e | 40 | #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) |
fed2f6e2 | 41 | #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) |
60bf6396 | 42 | #define ESDHC_WTMK_LVL 0x44 |
cc17e129 | 43 | #define ESDHC_WTMK_DEFAULT_VAL 0x10401040 |
60bf6396 | 44 | #define ESDHC_MIX_CTRL 0x48 |
de5bdbff | 45 | #define ESDHC_MIX_CTRL_DDREN (1 << 3) |
2a15f981 | 46 | #define ESDHC_MIX_CTRL_AC23EN (1 << 7) |
0322191e DA |
47 | #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) |
48 | #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) | |
0b330e38 | 49 | #define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24) |
0322191e | 50 | #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) |
28b07674 | 51 | #define ESDHC_MIX_CTRL_HS400_EN (1 << 26) |
2a15f981 SG |
52 | /* Bits 3 and 6 are not SDHCI standard definitions */ |
53 | #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 | |
d131a71c DA |
54 | /* Tuning bits */ |
55 | #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000 | |
58ac8177 | 56 | |
602519b2 DA |
57 | /* dll control register */ |
58 | #define ESDHC_DLL_CTRL 0x60 | |
59 | #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9 | |
60 | #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8 | |
61 | ||
0322191e DA |
62 | /* tune control register */ |
63 | #define ESDHC_TUNE_CTRL_STATUS 0x68 | |
64 | #define ESDHC_TUNE_CTRL_STEP 1 | |
65 | #define ESDHC_TUNE_CTRL_MIN 0 | |
66 | #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) | |
67 | ||
28b07674 HC |
68 | /* strobe dll register */ |
69 | #define ESDHC_STROBE_DLL_CTRL 0x70 | |
70 | #define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0) | |
71 | #define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1) | |
72 | #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3 | |
73 | ||
74 | #define ESDHC_STROBE_DLL_STATUS 0x74 | |
75 | #define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1) | |
76 | #define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1 | |
77 | ||
6e9fd28e DA |
78 | #define ESDHC_TUNING_CTRL 0xcc |
79 | #define ESDHC_STD_TUNING_EN (1 << 24) | |
80 | /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ | |
d87fc966 DA |
81 | #define ESDHC_TUNING_START_TAP_DEFAULT 0x1 |
82 | #define ESDHC_TUNING_START_TAP_MASK 0xff | |
260ecb3c | 83 | #define ESDHC_TUNING_STEP_MASK 0x00070000 |
d407e30b | 84 | #define ESDHC_TUNING_STEP_SHIFT 16 |
6e9fd28e | 85 | |
ad93220d DA |
86 | /* pinctrl state */ |
87 | #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" | |
88 | #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz" | |
89 | ||
af51079e SH |
90 | /* |
91 | * Our interpretation of the SDHCI_HOST_CONTROL register | |
92 | */ | |
93 | #define ESDHC_CTRL_4BITBUS (0x1 << 1) | |
94 | #define ESDHC_CTRL_8BITBUS (0x2 << 1) | |
95 | #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) | |
96 | ||
97e4ba6a RZ |
97 | /* |
98 | * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC: | |
99 | * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, | |
100 | * but bit28 is used as the INT DMA ERR in fsl eSDHC design. | |
101 | * Define this macro DMA error INT for fsl eSDHC | |
102 | */ | |
60bf6396 | 103 | #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) |
97e4ba6a | 104 | |
58ac8177 RZ |
105 | /* |
106 | * The CMDTYPE of the CMD register (offset 0xE) should be set to | |
107 | * "11" when the STOP CMD12 is issued on imx53 to abort one | |
108 | * open ended multi-blk IO. Otherwise the TC INT wouldn't | |
109 | * be generated. | |
110 | * In exact block transfer, the controller doesn't complete the | |
111 | * operations automatically as required at the end of the | |
112 | * transfer and remains on hold if the abort command is not sent. | |
113 | * As a result, the TC flag is not asserted and SW received timeout | |
114 | * exeception. Bit1 of Vendor Spec registor is used to fix it. | |
115 | */ | |
31fbb301 SG |
116 | #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) |
117 | /* | |
118 | * The flag enables the workaround for ESDHC errata ENGcm07207 which | |
119 | * affects i.MX25 and i.MX35. | |
120 | */ | |
121 | #define ESDHC_FLAG_ENGCM07207 BIT(2) | |
9d61c009 SG |
122 | /* |
123 | * The flag tells that the ESDHC controller is an USDHC block that is | |
124 | * integrated on the i.MX6 series. | |
125 | */ | |
126 | #define ESDHC_FLAG_USDHC BIT(3) | |
6e9fd28e DA |
127 | /* The IP supports manual tuning process */ |
128 | #define ESDHC_FLAG_MAN_TUNING BIT(4) | |
129 | /* The IP supports standard tuning process */ | |
130 | #define ESDHC_FLAG_STD_TUNING BIT(5) | |
131 | /* The IP has SDHCI_CAPABILITIES_1 register */ | |
132 | #define ESDHC_FLAG_HAVE_CAP1 BIT(6) | |
18094430 DA |
133 | /* |
134 | * The IP has errata ERR004536 | |
135 | * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow, | |
136 | * when reading data from the card | |
137 | */ | |
138 | #define ESDHC_FLAG_ERR004536 BIT(7) | |
4245afff DA |
139 | /* The IP supports HS200 mode */ |
140 | #define ESDHC_FLAG_HS200 BIT(8) | |
28b07674 HC |
141 | /* The IP supports HS400 mode */ |
142 | #define ESDHC_FLAG_HS400 BIT(9) | |
143 | ||
144 | /* A higher clock ferquency than this rate requires strobell dll control */ | |
145 | #define ESDHC_STROBE_DLL_CLK_FREQ 100000000 | |
e149860d | 146 | |
f47c4bbf SG |
147 | struct esdhc_soc_data { |
148 | u32 flags; | |
149 | }; | |
150 | ||
151 | static struct esdhc_soc_data esdhc_imx25_data = { | |
152 | .flags = ESDHC_FLAG_ENGCM07207, | |
153 | }; | |
154 | ||
155 | static struct esdhc_soc_data esdhc_imx35_data = { | |
156 | .flags = ESDHC_FLAG_ENGCM07207, | |
157 | }; | |
158 | ||
159 | static struct esdhc_soc_data esdhc_imx51_data = { | |
160 | .flags = 0, | |
161 | }; | |
162 | ||
163 | static struct esdhc_soc_data esdhc_imx53_data = { | |
164 | .flags = ESDHC_FLAG_MULTIBLK_NO_INT, | |
165 | }; | |
166 | ||
167 | static struct esdhc_soc_data usdhc_imx6q_data = { | |
6e9fd28e DA |
168 | .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING, |
169 | }; | |
170 | ||
171 | static struct esdhc_soc_data usdhc_imx6sl_data = { | |
172 | .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING | |
4245afff DA |
173 | | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536 |
174 | | ESDHC_FLAG_HS200, | |
57ed3314 SG |
175 | }; |
176 | ||
913d4951 DA |
177 | static struct esdhc_soc_data usdhc_imx6sx_data = { |
178 | .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING | |
4245afff | 179 | | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200, |
913d4951 DA |
180 | }; |
181 | ||
28b07674 HC |
182 | static struct esdhc_soc_data usdhc_imx7d_data = { |
183 | .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING | |
184 | | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 | |
185 | | ESDHC_FLAG_HS400, | |
186 | }; | |
187 | ||
e149860d | 188 | struct pltfm_imx_data { |
e149860d | 189 | u32 scratchpad; |
e62d8b8f | 190 | struct pinctrl *pinctrl; |
ad93220d DA |
191 | struct pinctrl_state *pins_default; |
192 | struct pinctrl_state *pins_100mhz; | |
193 | struct pinctrl_state *pins_200mhz; | |
f47c4bbf | 194 | const struct esdhc_soc_data *socdata; |
842afc02 | 195 | struct esdhc_platform_data boarddata; |
52dac615 SH |
196 | struct clk *clk_ipg; |
197 | struct clk *clk_ahb; | |
198 | struct clk *clk_per; | |
361b8482 LS |
199 | enum { |
200 | NO_CMD_PENDING, /* no multiblock command pending*/ | |
201 | MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ | |
202 | WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ | |
203 | } multiblock_status; | |
de5bdbff | 204 | u32 is_ddr; |
e149860d RZ |
205 | }; |
206 | ||
f8cbf461 | 207 | static const struct platform_device_id imx_esdhc_devtype[] = { |
57ed3314 SG |
208 | { |
209 | .name = "sdhci-esdhc-imx25", | |
f47c4bbf | 210 | .driver_data = (kernel_ulong_t) &esdhc_imx25_data, |
57ed3314 SG |
211 | }, { |
212 | .name = "sdhci-esdhc-imx35", | |
f47c4bbf | 213 | .driver_data = (kernel_ulong_t) &esdhc_imx35_data, |
57ed3314 SG |
214 | }, { |
215 | .name = "sdhci-esdhc-imx51", | |
f47c4bbf | 216 | .driver_data = (kernel_ulong_t) &esdhc_imx51_data, |
57ed3314 SG |
217 | }, { |
218 | /* sentinel */ | |
219 | } | |
220 | }; | |
221 | MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); | |
222 | ||
abfafc2d | 223 | static const struct of_device_id imx_esdhc_dt_ids[] = { |
f47c4bbf SG |
224 | { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, }, |
225 | { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, }, | |
226 | { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, }, | |
227 | { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, }, | |
913d4951 | 228 | { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, }, |
6e9fd28e | 229 | { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, |
f47c4bbf | 230 | { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, |
28b07674 | 231 | { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, }, |
abfafc2d SG |
232 | { /* sentinel */ } |
233 | }; | |
234 | MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); | |
235 | ||
57ed3314 SG |
236 | static inline int is_imx25_esdhc(struct pltfm_imx_data *data) |
237 | { | |
f47c4bbf | 238 | return data->socdata == &esdhc_imx25_data; |
57ed3314 SG |
239 | } |
240 | ||
241 | static inline int is_imx53_esdhc(struct pltfm_imx_data *data) | |
242 | { | |
f47c4bbf | 243 | return data->socdata == &esdhc_imx53_data; |
57ed3314 SG |
244 | } |
245 | ||
95a2482a SG |
246 | static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) |
247 | { | |
f47c4bbf | 248 | return data->socdata == &usdhc_imx6q_data; |
95a2482a SG |
249 | } |
250 | ||
9d61c009 SG |
251 | static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) |
252 | { | |
f47c4bbf | 253 | return !!(data->socdata->flags & ESDHC_FLAG_USDHC); |
9d61c009 SG |
254 | } |
255 | ||
95f25efe WS |
256 | static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) |
257 | { | |
258 | void __iomem *base = host->ioaddr + (reg & ~0x3); | |
259 | u32 shift = (reg & 0x3) * 8; | |
260 | ||
261 | writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); | |
262 | } | |
263 | ||
7e29c306 WS |
264 | static u32 esdhc_readl_le(struct sdhci_host *host, int reg) |
265 | { | |
361b8482 | 266 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
070e6d3f | 267 | struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); |
7e29c306 WS |
268 | u32 val = readl(host->ioaddr + reg); |
269 | ||
0322191e DA |
270 | if (unlikely(reg == SDHCI_PRESENT_STATE)) { |
271 | u32 fsl_prss = val; | |
272 | /* save the least 20 bits */ | |
273 | val = fsl_prss & 0x000FFFFF; | |
274 | /* move dat[0-3] bits */ | |
275 | val |= (fsl_prss & 0x0F000000) >> 4; | |
276 | /* move cmd line bit */ | |
277 | val |= (fsl_prss & 0x00800000) << 1; | |
278 | } | |
279 | ||
97e4ba6a | 280 | if (unlikely(reg == SDHCI_CAPABILITIES)) { |
6b4fb671 DA |
281 | /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ |
282 | if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) | |
283 | val &= 0xffff0000; | |
284 | ||
97e4ba6a RZ |
285 | /* In FSL esdhc IC module, only bit20 is used to indicate the |
286 | * ADMA2 capability of esdhc, but this bit is messed up on | |
287 | * some SOCs (e.g. on MX25, MX35 this bit is set, but they | |
288 | * don't actually support ADMA2). So set the BROKEN_ADMA | |
289 | * uirk on MX25/35 platforms. | |
290 | */ | |
291 | ||
292 | if (val & SDHCI_CAN_DO_ADMA1) { | |
293 | val &= ~SDHCI_CAN_DO_ADMA1; | |
294 | val |= SDHCI_CAN_DO_ADMA2; | |
295 | } | |
296 | } | |
297 | ||
6e9fd28e DA |
298 | if (unlikely(reg == SDHCI_CAPABILITIES_1)) { |
299 | if (esdhc_is_usdhc(imx_data)) { | |
300 | if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) | |
301 | val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; | |
302 | else | |
303 | /* imx6q/dl does not have cap_1 register, fake one */ | |
304 | val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 | |
888824bb | 305 | | SDHCI_SUPPORT_SDR50 |
da0295ff DA |
306 | | SDHCI_USE_SDR50_TUNING |
307 | | (SDHCI_TUNING_MODE_3 << SDHCI_RETUNING_MODE_SHIFT); | |
28b07674 HC |
308 | |
309 | if (imx_data->socdata->flags & ESDHC_FLAG_HS400) | |
310 | val |= SDHCI_SUPPORT_HS400; | |
6e9fd28e DA |
311 | } |
312 | } | |
0322191e | 313 | |
9d61c009 | 314 | if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) { |
0322191e DA |
315 | val = 0; |
316 | val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT; | |
317 | val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT; | |
318 | val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT; | |
319 | } | |
320 | ||
97e4ba6a | 321 | if (unlikely(reg == SDHCI_INT_STATUS)) { |
60bf6396 SG |
322 | if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { |
323 | val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; | |
97e4ba6a RZ |
324 | val |= SDHCI_INT_ADMA_ERROR; |
325 | } | |
361b8482 LS |
326 | |
327 | /* | |
328 | * mask off the interrupt we get in response to the manually | |
329 | * sent CMD12 | |
330 | */ | |
331 | if ((imx_data->multiblock_status == WAIT_FOR_INT) && | |
332 | ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) { | |
333 | val &= ~SDHCI_INT_RESPONSE; | |
334 | writel(SDHCI_INT_RESPONSE, host->ioaddr + | |
335 | SDHCI_INT_STATUS); | |
336 | imx_data->multiblock_status = NO_CMD_PENDING; | |
337 | } | |
97e4ba6a RZ |
338 | } |
339 | ||
7e29c306 WS |
340 | return val; |
341 | } | |
342 | ||
343 | static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) | |
344 | { | |
e149860d | 345 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
070e6d3f | 346 | struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); |
0d58864b TL |
347 | u32 data; |
348 | ||
77da3da0 AB |
349 | if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE || |
350 | reg == SDHCI_INT_STATUS)) { | |
b7321042 | 351 | if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) { |
0d58864b TL |
352 | /* |
353 | * Clear and then set D3CD bit to avoid missing the | |
354 | * card interrupt. This is a eSDHC controller problem | |
355 | * so we need to apply the following workaround: clear | |
356 | * and set D3CD bit will make eSDHC re-sample the card | |
357 | * interrupt. In case a card interrupt was lost, | |
358 | * re-sample it by the following steps. | |
359 | */ | |
360 | data = readl(host->ioaddr + SDHCI_HOST_CONTROL); | |
60bf6396 | 361 | data &= ~ESDHC_CTRL_D3CD; |
0d58864b | 362 | writel(data, host->ioaddr + SDHCI_HOST_CONTROL); |
60bf6396 | 363 | data |= ESDHC_CTRL_D3CD; |
0d58864b TL |
364 | writel(data, host->ioaddr + SDHCI_HOST_CONTROL); |
365 | } | |
915be485 DA |
366 | |
367 | if (val & SDHCI_INT_ADMA_ERROR) { | |
368 | val &= ~SDHCI_INT_ADMA_ERROR; | |
369 | val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; | |
370 | } | |
0d58864b | 371 | } |
7e29c306 | 372 | |
f47c4bbf | 373 | if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) |
58ac8177 RZ |
374 | && (reg == SDHCI_INT_STATUS) |
375 | && (val & SDHCI_INT_DATA_END))) { | |
376 | u32 v; | |
60bf6396 SG |
377 | v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
378 | v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; | |
379 | writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); | |
361b8482 LS |
380 | |
381 | if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) | |
382 | { | |
383 | /* send a manual CMD12 with RESPTYP=none */ | |
384 | data = MMC_STOP_TRANSMISSION << 24 | | |
385 | SDHCI_CMD_ABORTCMD << 16; | |
386 | writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); | |
387 | imx_data->multiblock_status = WAIT_FOR_INT; | |
388 | } | |
58ac8177 RZ |
389 | } |
390 | ||
7e29c306 WS |
391 | writel(val, host->ioaddr + reg); |
392 | } | |
393 | ||
95f25efe WS |
394 | static u16 esdhc_readw_le(struct sdhci_host *host, int reg) |
395 | { | |
ef4d0888 | 396 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
070e6d3f | 397 | struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); |
0322191e DA |
398 | u16 ret = 0; |
399 | u32 val; | |
ef4d0888 | 400 | |
95a2482a | 401 | if (unlikely(reg == SDHCI_HOST_VERSION)) { |
ef4d0888 | 402 | reg ^= 2; |
9d61c009 | 403 | if (esdhc_is_usdhc(imx_data)) { |
ef4d0888 SG |
404 | /* |
405 | * The usdhc register returns a wrong host version. | |
406 | * Correct it here. | |
407 | */ | |
408 | return SDHCI_SPEC_300; | |
409 | } | |
95a2482a | 410 | } |
95f25efe | 411 | |
0322191e DA |
412 | if (unlikely(reg == SDHCI_HOST_CONTROL2)) { |
413 | val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); | |
414 | if (val & ESDHC_VENDOR_SPEC_VSELECT) | |
415 | ret |= SDHCI_CTRL_VDD_180; | |
416 | ||
9d61c009 | 417 | if (esdhc_is_usdhc(imx_data)) { |
6e9fd28e DA |
418 | if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) |
419 | val = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
420 | else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) | |
421 | /* the std tuning bits is in ACMD12_ERR for imx6sl */ | |
422 | val = readl(host->ioaddr + SDHCI_ACMD12_ERR); | |
0322191e DA |
423 | } |
424 | ||
6e9fd28e DA |
425 | if (val & ESDHC_MIX_CTRL_EXE_TUNE) |
426 | ret |= SDHCI_CTRL_EXEC_TUNING; | |
427 | if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) | |
428 | ret |= SDHCI_CTRL_TUNED_CLK; | |
429 | ||
0322191e DA |
430 | ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; |
431 | ||
432 | return ret; | |
433 | } | |
434 | ||
7dd109ef DA |
435 | if (unlikely(reg == SDHCI_TRANSFER_MODE)) { |
436 | if (esdhc_is_usdhc(imx_data)) { | |
437 | u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
438 | ret = m & ESDHC_MIX_CTRL_SDHCI_MASK; | |
439 | /* Swap AC23 bit */ | |
440 | if (m & ESDHC_MIX_CTRL_AC23EN) { | |
441 | ret &= ~ESDHC_MIX_CTRL_AC23EN; | |
442 | ret |= SDHCI_TRNS_AUTO_CMD23; | |
443 | } | |
444 | } else { | |
445 | ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); | |
446 | } | |
447 | ||
448 | return ret; | |
449 | } | |
450 | ||
95f25efe WS |
451 | return readw(host->ioaddr + reg); |
452 | } | |
453 | ||
454 | static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) | |
455 | { | |
456 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
070e6d3f | 457 | struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); |
0322191e | 458 | u32 new_val = 0; |
95f25efe WS |
459 | |
460 | switch (reg) { | |
0322191e DA |
461 | case SDHCI_CLOCK_CONTROL: |
462 | new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); | |
463 | if (val & SDHCI_CLOCK_CARD_EN) | |
464 | new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; | |
465 | else | |
466 | new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; | |
eeed7026 | 467 | writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); |
0322191e DA |
468 | return; |
469 | case SDHCI_HOST_CONTROL2: | |
470 | new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); | |
471 | if (val & SDHCI_CTRL_VDD_180) | |
472 | new_val |= ESDHC_VENDOR_SPEC_VSELECT; | |
473 | else | |
474 | new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; | |
475 | writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); | |
6e9fd28e DA |
476 | if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { |
477 | new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
da0295ff | 478 | if (val & SDHCI_CTRL_TUNED_CLK) { |
6e9fd28e | 479 | new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL; |
da0295ff DA |
480 | new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; |
481 | } else { | |
6e9fd28e | 482 | new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; |
da0295ff DA |
483 | new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN; |
484 | } | |
6e9fd28e DA |
485 | writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); |
486 | } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { | |
487 | u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR); | |
488 | u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
8b2bb0ad DA |
489 | if (val & SDHCI_CTRL_TUNED_CLK) { |
490 | v |= ESDHC_MIX_CTRL_SMPCLK_SEL; | |
491 | } else { | |
492 | v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; | |
493 | m &= ~ESDHC_MIX_CTRL_FBCLK_SEL; | |
0b330e38 | 494 | m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN; |
8b2bb0ad DA |
495 | } |
496 | ||
6e9fd28e | 497 | if (val & SDHCI_CTRL_EXEC_TUNING) { |
6e9fd28e DA |
498 | v |= ESDHC_MIX_CTRL_EXE_TUNE; |
499 | m |= ESDHC_MIX_CTRL_FBCLK_SEL; | |
0b330e38 | 500 | m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; |
6e9fd28e | 501 | } else { |
6e9fd28e | 502 | v &= ~ESDHC_MIX_CTRL_EXE_TUNE; |
6e9fd28e DA |
503 | } |
504 | ||
6e9fd28e DA |
505 | writel(v, host->ioaddr + SDHCI_ACMD12_ERR); |
506 | writel(m, host->ioaddr + ESDHC_MIX_CTRL); | |
507 | } | |
0322191e | 508 | return; |
95f25efe | 509 | case SDHCI_TRANSFER_MODE: |
f47c4bbf | 510 | if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) |
58ac8177 RZ |
511 | && (host->cmd->opcode == SD_IO_RW_EXTENDED) |
512 | && (host->cmd->data->blocks > 1) | |
513 | && (host->cmd->data->flags & MMC_DATA_READ)) { | |
514 | u32 v; | |
60bf6396 SG |
515 | v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
516 | v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; | |
517 | writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); | |
58ac8177 | 518 | } |
69f54698 | 519 | |
9d61c009 | 520 | if (esdhc_is_usdhc(imx_data)) { |
69f54698 | 521 | u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); |
2a15f981 SG |
522 | /* Swap AC23 bit */ |
523 | if (val & SDHCI_TRNS_AUTO_CMD23) { | |
524 | val &= ~SDHCI_TRNS_AUTO_CMD23; | |
525 | val |= ESDHC_MIX_CTRL_AC23EN; | |
526 | } | |
527 | m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); | |
69f54698 SG |
528 | writel(m, host->ioaddr + ESDHC_MIX_CTRL); |
529 | } else { | |
530 | /* | |
531 | * Postpone this write, we must do it together with a | |
532 | * command write that is down below. | |
533 | */ | |
534 | imx_data->scratchpad = val; | |
535 | } | |
95f25efe WS |
536 | return; |
537 | case SDHCI_COMMAND: | |
361b8482 | 538 | if (host->cmd->opcode == MMC_STOP_TRANSMISSION) |
58ac8177 | 539 | val |= SDHCI_CMD_ABORTCMD; |
95a2482a | 540 | |
361b8482 | 541 | if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && |
f47c4bbf | 542 | (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) |
361b8482 LS |
543 | imx_data->multiblock_status = MULTIBLK_IN_PROCESS; |
544 | ||
9d61c009 | 545 | if (esdhc_is_usdhc(imx_data)) |
95a2482a SG |
546 | writel(val << 16, |
547 | host->ioaddr + SDHCI_TRANSFER_MODE); | |
69f54698 | 548 | else |
95a2482a SG |
549 | writel(val << 16 | imx_data->scratchpad, |
550 | host->ioaddr + SDHCI_TRANSFER_MODE); | |
95f25efe WS |
551 | return; |
552 | case SDHCI_BLOCK_SIZE: | |
553 | val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); | |
554 | break; | |
555 | } | |
556 | esdhc_clrset_le(host, 0xffff, val, reg); | |
557 | } | |
558 | ||
77da3da0 AB |
559 | static u8 esdhc_readb_le(struct sdhci_host *host, int reg) |
560 | { | |
561 | u8 ret; | |
562 | u32 val; | |
563 | ||
564 | switch (reg) { | |
565 | case SDHCI_HOST_CONTROL: | |
566 | val = readl(host->ioaddr + reg); | |
567 | ||
568 | ret = val & SDHCI_CTRL_LED; | |
569 | ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK; | |
570 | ret |= (val & ESDHC_CTRL_4BITBUS); | |
571 | ret |= (val & ESDHC_CTRL_8BITBUS) << 3; | |
572 | return ret; | |
573 | } | |
574 | ||
575 | return readb(host->ioaddr + reg); | |
576 | } | |
577 | ||
95f25efe WS |
578 | static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) |
579 | { | |
9a0985b7 | 580 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
070e6d3f | 581 | struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); |
95f25efe | 582 | u32 new_val; |
af51079e | 583 | u32 mask; |
95f25efe WS |
584 | |
585 | switch (reg) { | |
586 | case SDHCI_POWER_CONTROL: | |
587 | /* | |
588 | * FSL put some DMA bits here | |
589 | * If your board has a regulator, code should be here | |
590 | */ | |
591 | return; | |
592 | case SDHCI_HOST_CONTROL: | |
6b40d182 | 593 | /* FSL messed up here, so we need to manually compose it. */ |
af51079e | 594 | new_val = val & SDHCI_CTRL_LED; |
7122bbb0 | 595 | /* ensure the endianness */ |
95f25efe | 596 | new_val |= ESDHC_HOST_CONTROL_LE; |
9a0985b7 WC |
597 | /* bits 8&9 are reserved on mx25 */ |
598 | if (!is_imx25_esdhc(imx_data)) { | |
599 | /* DMA mode bits are shifted */ | |
600 | new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; | |
601 | } | |
95f25efe | 602 | |
af51079e SH |
603 | /* |
604 | * Do not touch buswidth bits here. This is done in | |
605 | * esdhc_pltfm_bus_width. | |
f6825748 MF |
606 | * Do not touch the D3CD bit either which is used for the |
607 | * SDIO interrupt errata workaround. | |
af51079e | 608 | */ |
f6825748 | 609 | mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); |
af51079e SH |
610 | |
611 | esdhc_clrset_le(host, mask, new_val, reg); | |
95f25efe WS |
612 | return; |
613 | } | |
614 | esdhc_clrset_le(host, 0xff, val, reg); | |
913413c3 SG |
615 | |
616 | /* | |
617 | * The esdhc has a design violation to SDHC spec which tells | |
618 | * that software reset should not affect card detection circuit. | |
619 | * But esdhc clears its SYSCTL register bits [0..2] during the | |
620 | * software reset. This will stop those clocks that card detection | |
621 | * circuit relies on. To work around it, we turn the clocks on back | |
622 | * to keep card detection circuit functional. | |
623 | */ | |
58c8c4fb | 624 | if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) { |
913413c3 | 625 | esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); |
58c8c4fb SG |
626 | /* |
627 | * The reset on usdhc fails to clear MIX_CTRL register. | |
628 | * Do it manually here. | |
629 | */ | |
de5bdbff | 630 | if (esdhc_is_usdhc(imx_data)) { |
d131a71c DA |
631 | /* the tuning bits should be kept during reset */ |
632 | new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
633 | writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK, | |
634 | host->ioaddr + ESDHC_MIX_CTRL); | |
de5bdbff DA |
635 | imx_data->is_ddr = 0; |
636 | } | |
58c8c4fb | 637 | } |
95f25efe WS |
638 | } |
639 | ||
0ddf03c9 LS |
640 | static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) |
641 | { | |
642 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
0ddf03c9 | 643 | |
a3bd4f98 | 644 | return pltfm_host->clock; |
0ddf03c9 LS |
645 | } |
646 | ||
95f25efe WS |
647 | static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) |
648 | { | |
649 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
650 | ||
a974862f | 651 | return pltfm_host->clock / 256 / 16; |
95f25efe WS |
652 | } |
653 | ||
8ba9580a LS |
654 | static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, |
655 | unsigned int clock) | |
656 | { | |
657 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
070e6d3f | 658 | struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); |
a974862f | 659 | unsigned int host_clock = pltfm_host->clock; |
d31fc00a DA |
660 | int pre_div = 2; |
661 | int div = 1; | |
fed2f6e2 | 662 | u32 temp, val; |
d31fc00a | 663 | |
fed2f6e2 | 664 | if (clock == 0) { |
1650d0c7 RK |
665 | host->mmc->actual_clock = 0; |
666 | ||
9d61c009 | 667 | if (esdhc_is_usdhc(imx_data)) { |
fed2f6e2 DA |
668 | val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
669 | writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, | |
670 | host->ioaddr + ESDHC_VENDOR_SPEC); | |
671 | } | |
373073ef | 672 | return; |
fed2f6e2 | 673 | } |
d31fc00a | 674 | |
de5bdbff | 675 | if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr) |
5f7886c5 DA |
676 | pre_div = 1; |
677 | ||
d31fc00a DA |
678 | temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); |
679 | temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN | |
680 | | ESDHC_CLOCK_MASK); | |
681 | sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); | |
682 | ||
683 | while (host_clock / pre_div / 16 > clock && pre_div < 256) | |
684 | pre_div *= 2; | |
685 | ||
686 | while (host_clock / pre_div / div > clock && div < 16) | |
687 | div++; | |
688 | ||
e76b8559 | 689 | host->mmc->actual_clock = host_clock / pre_div / div; |
d31fc00a | 690 | dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", |
e76b8559 | 691 | clock, host->mmc->actual_clock); |
d31fc00a | 692 | |
de5bdbff DA |
693 | if (imx_data->is_ddr) |
694 | pre_div >>= 2; | |
695 | else | |
696 | pre_div >>= 1; | |
d31fc00a DA |
697 | div--; |
698 | ||
699 | temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); | |
700 | temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN | |
701 | | (div << ESDHC_DIVIDER_SHIFT) | |
702 | | (pre_div << ESDHC_PREDIV_SHIFT)); | |
703 | sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); | |
fed2f6e2 | 704 | |
9d61c009 | 705 | if (esdhc_is_usdhc(imx_data)) { |
fed2f6e2 DA |
706 | val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
707 | writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, | |
708 | host->ioaddr + ESDHC_VENDOR_SPEC); | |
709 | } | |
710 | ||
d31fc00a | 711 | mdelay(1); |
8ba9580a LS |
712 | } |
713 | ||
913413c3 SG |
714 | static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) |
715 | { | |
842afc02 | 716 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
070e6d3f | 717 | struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); |
842afc02 | 718 | struct esdhc_platform_data *boarddata = &imx_data->boarddata; |
913413c3 SG |
719 | |
720 | switch (boarddata->wp_type) { | |
721 | case ESDHC_WP_GPIO: | |
fbe5fdd1 | 722 | return mmc_gpio_get_ro(host->mmc); |
913413c3 SG |
723 | case ESDHC_WP_CONTROLLER: |
724 | return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & | |
725 | SDHCI_WRITE_PROTECT); | |
726 | case ESDHC_WP_NONE: | |
727 | break; | |
728 | } | |
729 | ||
730 | return -ENOSYS; | |
731 | } | |
732 | ||
2317f56c | 733 | static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) |
af51079e SH |
734 | { |
735 | u32 ctrl; | |
736 | ||
737 | switch (width) { | |
738 | case MMC_BUS_WIDTH_8: | |
739 | ctrl = ESDHC_CTRL_8BITBUS; | |
740 | break; | |
741 | case MMC_BUS_WIDTH_4: | |
742 | ctrl = ESDHC_CTRL_4BITBUS; | |
743 | break; | |
744 | default: | |
745 | ctrl = 0; | |
746 | break; | |
747 | } | |
748 | ||
749 | esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, | |
750 | SDHCI_HOST_CONTROL); | |
af51079e SH |
751 | } |
752 | ||
0322191e DA |
753 | static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) |
754 | { | |
755 | u32 reg; | |
756 | ||
757 | /* FIXME: delay a bit for card to be ready for next tuning due to errors */ | |
758 | mdelay(1); | |
759 | ||
760 | reg = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
761 | reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | | |
762 | ESDHC_MIX_CTRL_FBCLK_SEL; | |
763 | writel(reg, host->ioaddr + ESDHC_MIX_CTRL); | |
764 | writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); | |
765 | dev_dbg(mmc_dev(host->mmc), | |
766 | "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", | |
767 | val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); | |
768 | } | |
769 | ||
0322191e DA |
770 | static void esdhc_post_tuning(struct sdhci_host *host) |
771 | { | |
772 | u32 reg; | |
773 | ||
774 | reg = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
775 | reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; | |
da0295ff | 776 | reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; |
0322191e DA |
777 | writel(reg, host->ioaddr + ESDHC_MIX_CTRL); |
778 | } | |
779 | ||
780 | static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) | |
781 | { | |
782 | int min, max, avg, ret; | |
783 | ||
784 | /* find the mininum delay first which can pass tuning */ | |
785 | min = ESDHC_TUNE_CTRL_MIN; | |
786 | while (min < ESDHC_TUNE_CTRL_MAX) { | |
787 | esdhc_prepare_tuning(host, min); | |
9979dbe5 | 788 | if (!mmc_send_tuning(host->mmc, opcode, NULL)) |
0322191e DA |
789 | break; |
790 | min += ESDHC_TUNE_CTRL_STEP; | |
791 | } | |
792 | ||
793 | /* find the maxinum delay which can not pass tuning */ | |
794 | max = min + ESDHC_TUNE_CTRL_STEP; | |
795 | while (max < ESDHC_TUNE_CTRL_MAX) { | |
796 | esdhc_prepare_tuning(host, max); | |
9979dbe5 | 797 | if (mmc_send_tuning(host->mmc, opcode, NULL)) { |
0322191e DA |
798 | max -= ESDHC_TUNE_CTRL_STEP; |
799 | break; | |
800 | } | |
801 | max += ESDHC_TUNE_CTRL_STEP; | |
802 | } | |
803 | ||
804 | /* use average delay to get the best timing */ | |
805 | avg = (min + max) / 2; | |
806 | esdhc_prepare_tuning(host, avg); | |
9979dbe5 | 807 | ret = mmc_send_tuning(host->mmc, opcode, NULL); |
0322191e DA |
808 | esdhc_post_tuning(host); |
809 | ||
810 | dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n", | |
811 | ret ? "failed" : "passed", avg, ret); | |
812 | ||
813 | return ret; | |
814 | } | |
815 | ||
ad93220d DA |
816 | static int esdhc_change_pinstate(struct sdhci_host *host, |
817 | unsigned int uhs) | |
818 | { | |
819 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
070e6d3f | 820 | struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); |
ad93220d DA |
821 | struct pinctrl_state *pinctrl; |
822 | ||
823 | dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); | |
824 | ||
825 | if (IS_ERR(imx_data->pinctrl) || | |
826 | IS_ERR(imx_data->pins_default) || | |
827 | IS_ERR(imx_data->pins_100mhz) || | |
828 | IS_ERR(imx_data->pins_200mhz)) | |
829 | return -EINVAL; | |
830 | ||
831 | switch (uhs) { | |
832 | case MMC_TIMING_UHS_SDR50: | |
9f327845 | 833 | case MMC_TIMING_UHS_DDR50: |
ad93220d DA |
834 | pinctrl = imx_data->pins_100mhz; |
835 | break; | |
836 | case MMC_TIMING_UHS_SDR104: | |
429a5b45 | 837 | case MMC_TIMING_MMC_HS200: |
28b07674 | 838 | case MMC_TIMING_MMC_HS400: |
ad93220d DA |
839 | pinctrl = imx_data->pins_200mhz; |
840 | break; | |
841 | default: | |
842 | /* back to default state for other legacy timing */ | |
843 | pinctrl = imx_data->pins_default; | |
844 | } | |
845 | ||
846 | return pinctrl_select_state(imx_data->pinctrl, pinctrl); | |
847 | } | |
848 | ||
28b07674 HC |
849 | /* |
850 | * For HS400 eMMC, there is a data_strobe line, this signal is generated | |
851 | * by the device and used for data output and CRC status response output | |
852 | * in HS400 mode. The frequency of this signal follows the frequency of | |
853 | * CLK generated by host. Host receive the data which is aligned to the | |
854 | * edge of data_strobe line. Due to the time delay between CLK line and | |
855 | * data_strobe line, if the delay time is larger than one clock cycle, | |
856 | * then CLK and data_strobe line will misaligned, read error shows up. | |
857 | * So when the CLK is higher than 100MHz, each clock cycle is short enough, | |
858 | * host should config the delay target. | |
859 | */ | |
860 | static void esdhc_set_strobe_dll(struct sdhci_host *host) | |
861 | { | |
862 | u32 v; | |
863 | ||
864 | if (host->mmc->actual_clock > ESDHC_STROBE_DLL_CLK_FREQ) { | |
7ac6da26 DA |
865 | /* disable clock before enabling strobe dll */ |
866 | writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) & | |
867 | ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, | |
868 | host->ioaddr + ESDHC_VENDOR_SPEC); | |
869 | ||
28b07674 HC |
870 | /* force a reset on strobe dll */ |
871 | writel(ESDHC_STROBE_DLL_CTRL_RESET, | |
872 | host->ioaddr + ESDHC_STROBE_DLL_CTRL); | |
873 | /* | |
874 | * enable strobe dll ctrl and adjust the delay target | |
875 | * for the uSDHC loopback read clock | |
876 | */ | |
877 | v = ESDHC_STROBE_DLL_CTRL_ENABLE | | |
878 | (7 << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT); | |
879 | writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL); | |
880 | /* wait 1us to make sure strobe dll status register stable */ | |
881 | udelay(1); | |
882 | v = readl(host->ioaddr + ESDHC_STROBE_DLL_STATUS); | |
883 | if (!(v & ESDHC_STROBE_DLL_STS_REF_LOCK)) | |
884 | dev_warn(mmc_dev(host->mmc), | |
885 | "warning! HS400 strobe DLL status REF not lock!\n"); | |
886 | if (!(v & ESDHC_STROBE_DLL_STS_SLV_LOCK)) | |
887 | dev_warn(mmc_dev(host->mmc), | |
888 | "warning! HS400 strobe DLL status SLV not lock!\n"); | |
889 | } | |
890 | } | |
891 | ||
d9370424 HC |
892 | static void esdhc_reset_tuning(struct sdhci_host *host) |
893 | { | |
894 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
895 | struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); | |
896 | u32 ctrl; | |
897 | ||
898 | /* Rest the tuning circurt */ | |
899 | if (esdhc_is_usdhc(imx_data)) { | |
900 | if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { | |
901 | ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
902 | ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; | |
903 | ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL; | |
904 | writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL); | |
905 | writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); | |
906 | } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { | |
907 | ctrl = readl(host->ioaddr + SDHCI_ACMD12_ERR); | |
908 | ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; | |
909 | writel(ctrl, host->ioaddr + SDHCI_ACMD12_ERR); | |
910 | } | |
911 | } | |
912 | } | |
913 | ||
850a29b8 | 914 | static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) |
ad93220d | 915 | { |
28b07674 | 916 | u32 m; |
ad93220d | 917 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
070e6d3f | 918 | struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); |
602519b2 | 919 | struct esdhc_platform_data *boarddata = &imx_data->boarddata; |
ad93220d | 920 | |
28b07674 HC |
921 | /* disable ddr mode and disable HS400 mode */ |
922 | m = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
923 | m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN); | |
924 | imx_data->is_ddr = 0; | |
925 | ||
850a29b8 | 926 | switch (timing) { |
ad93220d | 927 | case MMC_TIMING_UHS_SDR12: |
ad93220d | 928 | case MMC_TIMING_UHS_SDR25: |
ad93220d | 929 | case MMC_TIMING_UHS_SDR50: |
ad93220d | 930 | case MMC_TIMING_UHS_SDR104: |
429a5b45 | 931 | case MMC_TIMING_MMC_HS200: |
28b07674 | 932 | writel(m, host->ioaddr + ESDHC_MIX_CTRL); |
ad93220d DA |
933 | break; |
934 | case MMC_TIMING_UHS_DDR50: | |
69f5bf38 | 935 | case MMC_TIMING_MMC_DDR52: |
28b07674 HC |
936 | m |= ESDHC_MIX_CTRL_DDREN; |
937 | writel(m, host->ioaddr + ESDHC_MIX_CTRL); | |
de5bdbff | 938 | imx_data->is_ddr = 1; |
602519b2 DA |
939 | if (boarddata->delay_line) { |
940 | u32 v; | |
941 | v = boarddata->delay_line << | |
942 | ESDHC_DLL_OVERRIDE_VAL_SHIFT | | |
943 | (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT); | |
944 | if (is_imx53_esdhc(imx_data)) | |
945 | v <<= 1; | |
946 | writel(v, host->ioaddr + ESDHC_DLL_CTRL); | |
947 | } | |
ad93220d | 948 | break; |
28b07674 HC |
949 | case MMC_TIMING_MMC_HS400: |
950 | m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN; | |
951 | writel(m, host->ioaddr + ESDHC_MIX_CTRL); | |
952 | imx_data->is_ddr = 1; | |
7ac6da26 DA |
953 | /* update clock after enable DDR for strobe DLL lock */ |
954 | host->ops->set_clock(host, host->clock); | |
28b07674 HC |
955 | esdhc_set_strobe_dll(host); |
956 | break; | |
d9370424 HC |
957 | case MMC_TIMING_LEGACY: |
958 | default: | |
959 | esdhc_reset_tuning(host); | |
960 | break; | |
ad93220d DA |
961 | } |
962 | ||
850a29b8 | 963 | esdhc_change_pinstate(host, timing); |
ad93220d DA |
964 | } |
965 | ||
0718e59a RK |
966 | static void esdhc_reset(struct sdhci_host *host, u8 mask) |
967 | { | |
968 | sdhci_reset(host, mask); | |
969 | ||
970 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | |
971 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
972 | } | |
973 | ||
10fd0ad9 AD |
974 | static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host) |
975 | { | |
976 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
070e6d3f | 977 | struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); |
10fd0ad9 | 978 | |
2fb0b02b HC |
979 | /* Doc Errata: the uSDHC actual maximum timeout count is 1 << 29 */ |
980 | return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27; | |
10fd0ad9 AD |
981 | } |
982 | ||
e33eb8e2 AD |
983 | static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) |
984 | { | |
985 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
070e6d3f | 986 | struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); |
e33eb8e2 AD |
987 | |
988 | /* use maximum timeout counter */ | |
a215186d HC |
989 | esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK, |
990 | esdhc_is_usdhc(imx_data) ? 0xF : 0xE, | |
e33eb8e2 AD |
991 | SDHCI_TIMEOUT_CONTROL); |
992 | } | |
993 | ||
6e9fd28e | 994 | static struct sdhci_ops sdhci_esdhc_ops = { |
e149860d | 995 | .read_l = esdhc_readl_le, |
0c6d49ce | 996 | .read_w = esdhc_readw_le, |
77da3da0 | 997 | .read_b = esdhc_readb_le, |
e149860d | 998 | .write_l = esdhc_writel_le, |
0c6d49ce WS |
999 | .write_w = esdhc_writew_le, |
1000 | .write_b = esdhc_writeb_le, | |
8ba9580a | 1001 | .set_clock = esdhc_pltfm_set_clock, |
0ddf03c9 | 1002 | .get_max_clock = esdhc_pltfm_get_max_clock, |
0c6d49ce | 1003 | .get_min_clock = esdhc_pltfm_get_min_clock, |
10fd0ad9 | 1004 | .get_max_timeout_count = esdhc_get_max_timeout_count, |
913413c3 | 1005 | .get_ro = esdhc_pltfm_get_ro, |
e33eb8e2 | 1006 | .set_timeout = esdhc_set_timeout, |
2317f56c | 1007 | .set_bus_width = esdhc_pltfm_set_bus_width, |
ad93220d | 1008 | .set_uhs_signaling = esdhc_set_uhs_signaling, |
0718e59a | 1009 | .reset = esdhc_reset, |
0c6d49ce WS |
1010 | }; |
1011 | ||
1db5eebf | 1012 | static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { |
97e4ba6a RZ |
1013 | .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT |
1014 | | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | |
1015 | | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | |
85d6509d | 1016 | | SDHCI_QUIRK_BROKEN_CARD_DETECTION, |
85d6509d SG |
1017 | .ops = &sdhci_esdhc_ops, |
1018 | }; | |
1019 | ||
f3f5cf3d DA |
1020 | static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host) |
1021 | { | |
1022 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1023 | struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); | |
2b16cf32 | 1024 | int tmp; |
f3f5cf3d DA |
1025 | |
1026 | if (esdhc_is_usdhc(imx_data)) { | |
1027 | /* | |
1028 | * The imx6q ROM code will change the default watermark | |
1029 | * level setting to something insane. Change it back here. | |
1030 | */ | |
1031 | writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL); | |
1032 | ||
1033 | /* | |
1034 | * ROM code will change the bit burst_length_enable setting | |
1035 | * to zero if this usdhc is choosed to boot system. Change | |
1036 | * it back here, otherwise it will impact the performance a | |
1037 | * lot. This bit is used to enable/disable the burst length | |
1038 | * for the external AHB2AXI bridge, it's usefully especially | |
1039 | * for INCR transfer because without burst length indicator, | |
1040 | * the AHB2AXI bridge does not know the burst length in | |
1041 | * advance. And without burst length indicator, AHB INCR | |
1042 | * transfer can only be converted to singles on the AXI side. | |
1043 | */ | |
1044 | writel(readl(host->ioaddr + SDHCI_HOST_CONTROL) | |
1045 | | ESDHC_BURST_LEN_EN_INCR, | |
1046 | host->ioaddr + SDHCI_HOST_CONTROL); | |
1047 | /* | |
1048 | * errata ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL | |
1049 | * TO1.1, it's harmless for MX6SL | |
1050 | */ | |
1051 | writel(readl(host->ioaddr + 0x6c) | BIT(7), | |
1052 | host->ioaddr + 0x6c); | |
1053 | ||
1054 | /* disable DLL_CTRL delay line settings */ | |
1055 | writel(0x0, host->ioaddr + ESDHC_DLL_CTRL); | |
2b16cf32 DA |
1056 | |
1057 | if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { | |
1058 | tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); | |
1059 | tmp |= ESDHC_STD_TUNING_EN | | |
1060 | ESDHC_TUNING_START_TAP_DEFAULT; | |
1061 | if (imx_data->boarddata.tuning_start_tap) { | |
1062 | tmp &= ~ESDHC_TUNING_START_TAP_MASK; | |
1063 | tmp |= imx_data->boarddata.tuning_start_tap; | |
1064 | } | |
1065 | ||
1066 | if (imx_data->boarddata.tuning_step) { | |
1067 | tmp &= ~ESDHC_TUNING_STEP_MASK; | |
1068 | tmp |= imx_data->boarddata.tuning_step | |
1069 | << ESDHC_TUNING_STEP_SHIFT; | |
1070 | } | |
1071 | writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); | |
1072 | } | |
f3f5cf3d DA |
1073 | } |
1074 | } | |
1075 | ||
abfafc2d | 1076 | #ifdef CONFIG_OF |
c3be1efd | 1077 | static int |
abfafc2d | 1078 | sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, |
07bf2b54 | 1079 | struct sdhci_host *host, |
91fa4252 | 1080 | struct pltfm_imx_data *imx_data) |
abfafc2d SG |
1081 | { |
1082 | struct device_node *np = pdev->dev.of_node; | |
91fa4252 | 1083 | struct esdhc_platform_data *boarddata = &imx_data->boarddata; |
4800e87a | 1084 | int ret; |
abfafc2d | 1085 | |
abfafc2d SG |
1086 | if (of_get_property(np, "fsl,wp-controller", NULL)) |
1087 | boarddata->wp_type = ESDHC_WP_CONTROLLER; | |
1088 | ||
abfafc2d SG |
1089 | boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); |
1090 | if (gpio_is_valid(boarddata->wp_gpio)) | |
1091 | boarddata->wp_type = ESDHC_WP_GPIO; | |
1092 | ||
d407e30b | 1093 | of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step); |
d87fc966 DA |
1094 | of_property_read_u32(np, "fsl,tuning-start-tap", |
1095 | &boarddata->tuning_start_tap); | |
d407e30b | 1096 | |
ad93220d DA |
1097 | if (of_find_property(np, "no-1-8-v", NULL)) |
1098 | boarddata->support_vsel = false; | |
1099 | else | |
1100 | boarddata->support_vsel = true; | |
1101 | ||
602519b2 DA |
1102 | if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) |
1103 | boarddata->delay_line = 0; | |
1104 | ||
07bf2b54 SH |
1105 | mmc_of_parse_voltage(np, &host->ocr_mask); |
1106 | ||
91fa4252 DA |
1107 | /* sdr50 and sdr104 needs work on 1.8v signal voltage */ |
1108 | if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data) && | |
1109 | !IS_ERR(imx_data->pins_default)) { | |
1110 | imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, | |
1111 | ESDHC_PINCTRL_STATE_100MHZ); | |
1112 | imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, | |
1113 | ESDHC_PINCTRL_STATE_200MHZ); | |
1114 | if (IS_ERR(imx_data->pins_100mhz) || | |
1115 | IS_ERR(imx_data->pins_200mhz)) { | |
1116 | dev_warn(mmc_dev(host->mmc), | |
1117 | "could not get ultra high speed state, work on normal mode\n"); | |
1118 | /* | |
1119 | * fall back to not support uhs by specify no 1.8v quirk | |
1120 | */ | |
1121 | host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; | |
1122 | } | |
1123 | } else { | |
1124 | host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; | |
1125 | } | |
1126 | ||
15064119 | 1127 | /* call to generic mmc_of_parse to support additional capabilities */ |
4800e87a DA |
1128 | ret = mmc_of_parse(host->mmc); |
1129 | if (ret) | |
1130 | return ret; | |
1131 | ||
287980e4 | 1132 | if (mmc_gpio_get_cd(host->mmc) >= 0) |
4800e87a DA |
1133 | host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; |
1134 | ||
1135 | return 0; | |
abfafc2d SG |
1136 | } |
1137 | #else | |
1138 | static inline int | |
1139 | sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, | |
07bf2b54 | 1140 | struct sdhci_host *host, |
91fa4252 | 1141 | struct pltfm_imx_data *imx_data) |
abfafc2d SG |
1142 | { |
1143 | return -ENODEV; | |
1144 | } | |
1145 | #endif | |
1146 | ||
91fa4252 DA |
1147 | static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev, |
1148 | struct sdhci_host *host, | |
1149 | struct pltfm_imx_data *imx_data) | |
1150 | { | |
1151 | struct esdhc_platform_data *boarddata = &imx_data->boarddata; | |
1152 | int err; | |
1153 | ||
1154 | if (!host->mmc->parent->platform_data) { | |
1155 | dev_err(mmc_dev(host->mmc), "no board data!\n"); | |
1156 | return -EINVAL; | |
1157 | } | |
1158 | ||
1159 | imx_data->boarddata = *((struct esdhc_platform_data *) | |
1160 | host->mmc->parent->platform_data); | |
1161 | /* write_protect */ | |
1162 | if (boarddata->wp_type == ESDHC_WP_GPIO) { | |
1163 | err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio); | |
1164 | if (err) { | |
1165 | dev_err(mmc_dev(host->mmc), | |
1166 | "failed to request write-protect gpio!\n"); | |
1167 | return err; | |
1168 | } | |
1169 | host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; | |
1170 | } | |
1171 | ||
1172 | /* card_detect */ | |
1173 | switch (boarddata->cd_type) { | |
1174 | case ESDHC_CD_GPIO: | |
1175 | err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0); | |
1176 | if (err) { | |
1177 | dev_err(mmc_dev(host->mmc), | |
1178 | "failed to request card-detect gpio!\n"); | |
1179 | return err; | |
1180 | } | |
1181 | /* fall through */ | |
1182 | ||
1183 | case ESDHC_CD_CONTROLLER: | |
1184 | /* we have a working card_detect back */ | |
1185 | host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; | |
1186 | break; | |
1187 | ||
1188 | case ESDHC_CD_PERMANENT: | |
1189 | host->mmc->caps |= MMC_CAP_NONREMOVABLE; | |
1190 | break; | |
1191 | ||
1192 | case ESDHC_CD_NONE: | |
1193 | break; | |
1194 | } | |
1195 | ||
1196 | switch (boarddata->max_bus_width) { | |
1197 | case 8: | |
1198 | host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA; | |
1199 | break; | |
1200 | case 4: | |
1201 | host->mmc->caps |= MMC_CAP_4_BIT_DATA; | |
1202 | break; | |
1203 | case 1: | |
1204 | default: | |
1205 | host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA; | |
1206 | break; | |
1207 | } | |
1208 | ||
1209 | return 0; | |
1210 | } | |
1211 | ||
c3be1efd | 1212 | static int sdhci_esdhc_imx_probe(struct platform_device *pdev) |
95f25efe | 1213 | { |
abfafc2d SG |
1214 | const struct of_device_id *of_id = |
1215 | of_match_device(imx_esdhc_dt_ids, &pdev->dev); | |
85d6509d SG |
1216 | struct sdhci_pltfm_host *pltfm_host; |
1217 | struct sdhci_host *host; | |
0c6d49ce | 1218 | int err; |
e149860d | 1219 | struct pltfm_imx_data *imx_data; |
95f25efe | 1220 | |
070e6d3f JZ |
1221 | host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, |
1222 | sizeof(*imx_data)); | |
85d6509d SG |
1223 | if (IS_ERR(host)) |
1224 | return PTR_ERR(host); | |
1225 | ||
1226 | pltfm_host = sdhci_priv(host); | |
1227 | ||
070e6d3f | 1228 | imx_data = sdhci_pltfm_priv(pltfm_host); |
57ed3314 | 1229 | |
f47c4bbf SG |
1230 | imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *) |
1231 | pdev->id_entry->driver_data; | |
85d6509d | 1232 | |
52dac615 SH |
1233 | imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
1234 | if (IS_ERR(imx_data->clk_ipg)) { | |
1235 | err = PTR_ERR(imx_data->clk_ipg); | |
e3af31c6 | 1236 | goto free_sdhci; |
95f25efe | 1237 | } |
52dac615 SH |
1238 | |
1239 | imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); | |
1240 | if (IS_ERR(imx_data->clk_ahb)) { | |
1241 | err = PTR_ERR(imx_data->clk_ahb); | |
e3af31c6 | 1242 | goto free_sdhci; |
52dac615 SH |
1243 | } |
1244 | ||
1245 | imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); | |
1246 | if (IS_ERR(imx_data->clk_per)) { | |
1247 | err = PTR_ERR(imx_data->clk_per); | |
e3af31c6 | 1248 | goto free_sdhci; |
52dac615 SH |
1249 | } |
1250 | ||
1251 | pltfm_host->clk = imx_data->clk_per; | |
a974862f | 1252 | pltfm_host->clock = clk_get_rate(pltfm_host->clk); |
52dac615 SH |
1253 | clk_prepare_enable(imx_data->clk_per); |
1254 | clk_prepare_enable(imx_data->clk_ipg); | |
1255 | clk_prepare_enable(imx_data->clk_ahb); | |
95f25efe | 1256 | |
ad93220d | 1257 | imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); |
e62d8b8f DA |
1258 | if (IS_ERR(imx_data->pinctrl)) { |
1259 | err = PTR_ERR(imx_data->pinctrl); | |
e3af31c6 | 1260 | goto disable_clk; |
e62d8b8f DA |
1261 | } |
1262 | ||
ad93220d DA |
1263 | imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl, |
1264 | PINCTRL_STATE_DEFAULT); | |
cd529af7 DB |
1265 | if (IS_ERR(imx_data->pins_default)) |
1266 | dev_warn(mmc_dev(host->mmc), "could not get default state\n"); | |
ad93220d | 1267 | |
f47c4bbf | 1268 | if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207) |
0c6d49ce | 1269 | /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */ |
97e4ba6a RZ |
1270 | host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK |
1271 | | SDHCI_QUIRK_BROKEN_ADMA; | |
0c6d49ce | 1272 | |
69ed60e0 | 1273 | if (esdhc_is_usdhc(imx_data)) { |
69ed60e0 | 1274 | host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; |
e2997c94 | 1275 | host->mmc->caps |= MMC_CAP_1_8V_DDR; |
4245afff DA |
1276 | if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200)) |
1277 | host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; | |
a75dcbf4 DA |
1278 | |
1279 | /* clear tuning bits in case ROM has set it already */ | |
1280 | writel(0x0, host->ioaddr + ESDHC_MIX_CTRL); | |
1281 | writel(0x0, host->ioaddr + SDHCI_ACMD12_ERR); | |
1282 | writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); | |
69ed60e0 | 1283 | } |
f750ba9b | 1284 | |
6e9fd28e DA |
1285 | if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) |
1286 | sdhci_esdhc_ops.platform_execute_tuning = | |
1287 | esdhc_executing_tuning; | |
8b2bb0ad | 1288 | |
18094430 DA |
1289 | if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536) |
1290 | host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; | |
1291 | ||
28b07674 HC |
1292 | if (imx_data->socdata->flags & ESDHC_FLAG_HS400) |
1293 | host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400; | |
1294 | ||
91fa4252 DA |
1295 | if (of_id) |
1296 | err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data); | |
1297 | else | |
1298 | err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data); | |
1299 | if (err) | |
1300 | goto disable_clk; | |
ad93220d | 1301 | |
f3f5cf3d DA |
1302 | sdhci_esdhc_imx_hwinit(host); |
1303 | ||
85d6509d SG |
1304 | err = sdhci_add_host(host); |
1305 | if (err) | |
e3af31c6 | 1306 | goto disable_clk; |
85d6509d | 1307 | |
89d7e5c1 | 1308 | pm_runtime_set_active(&pdev->dev); |
89d7e5c1 DA |
1309 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); |
1310 | pm_runtime_use_autosuspend(&pdev->dev); | |
1311 | pm_suspend_ignore_children(&pdev->dev, 1); | |
77903c01 | 1312 | pm_runtime_enable(&pdev->dev); |
89d7e5c1 | 1313 | |
95f25efe | 1314 | return 0; |
7e29c306 | 1315 | |
e3af31c6 | 1316 | disable_clk: |
52dac615 SH |
1317 | clk_disable_unprepare(imx_data->clk_per); |
1318 | clk_disable_unprepare(imx_data->clk_ipg); | |
1319 | clk_disable_unprepare(imx_data->clk_ahb); | |
e3af31c6 | 1320 | free_sdhci: |
85d6509d SG |
1321 | sdhci_pltfm_free(pdev); |
1322 | return err; | |
95f25efe WS |
1323 | } |
1324 | ||
6e0ee714 | 1325 | static int sdhci_esdhc_imx_remove(struct platform_device *pdev) |
95f25efe | 1326 | { |
85d6509d | 1327 | struct sdhci_host *host = platform_get_drvdata(pdev); |
95f25efe | 1328 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
070e6d3f | 1329 | struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); |
85d6509d SG |
1330 | int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); |
1331 | ||
0b414368 | 1332 | pm_runtime_get_sync(&pdev->dev); |
89d7e5c1 | 1333 | pm_runtime_disable(&pdev->dev); |
0b414368 | 1334 | pm_runtime_put_noidle(&pdev->dev); |
89d7e5c1 | 1335 | |
0b414368 UH |
1336 | sdhci_remove_host(host, dead); |
1337 | ||
1338 | clk_disable_unprepare(imx_data->clk_per); | |
1339 | clk_disable_unprepare(imx_data->clk_ipg); | |
1340 | clk_disable_unprepare(imx_data->clk_ahb); | |
52dac615 | 1341 | |
85d6509d SG |
1342 | sdhci_pltfm_free(pdev); |
1343 | ||
1344 | return 0; | |
95f25efe WS |
1345 | } |
1346 | ||
2788ed42 | 1347 | #ifdef CONFIG_PM_SLEEP |
04143fba DA |
1348 | static int sdhci_esdhc_suspend(struct device *dev) |
1349 | { | |
3e3274ab UH |
1350 | struct sdhci_host *host = dev_get_drvdata(dev); |
1351 | ||
d38dcad4 AH |
1352 | if (host->tuning_mode != SDHCI_TUNING_MODE_3) |
1353 | mmc_retune_needed(host->mmc); | |
1354 | ||
3e3274ab | 1355 | return sdhci_suspend_host(host); |
04143fba DA |
1356 | } |
1357 | ||
1358 | static int sdhci_esdhc_resume(struct device *dev) | |
1359 | { | |
cc17e129 | 1360 | struct sdhci_host *host = dev_get_drvdata(dev); |
cc17e129 | 1361 | |
19dbfdd3 DA |
1362 | /* re-initialize hw state in case it's lost in low power mode */ |
1363 | sdhci_esdhc_imx_hwinit(host); | |
cc17e129 | 1364 | |
3e3274ab | 1365 | return sdhci_resume_host(host); |
04143fba | 1366 | } |
2788ed42 | 1367 | #endif |
04143fba | 1368 | |
2788ed42 | 1369 | #ifdef CONFIG_PM |
89d7e5c1 DA |
1370 | static int sdhci_esdhc_runtime_suspend(struct device *dev) |
1371 | { | |
1372 | struct sdhci_host *host = dev_get_drvdata(dev); | |
1373 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
070e6d3f | 1374 | struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); |
89d7e5c1 DA |
1375 | int ret; |
1376 | ||
1377 | ret = sdhci_runtime_suspend_host(host); | |
1378 | ||
d38dcad4 AH |
1379 | if (host->tuning_mode != SDHCI_TUNING_MODE_3) |
1380 | mmc_retune_needed(host->mmc); | |
1381 | ||
be138554 RK |
1382 | if (!sdhci_sdio_irq_enabled(host)) { |
1383 | clk_disable_unprepare(imx_data->clk_per); | |
1384 | clk_disable_unprepare(imx_data->clk_ipg); | |
1385 | } | |
89d7e5c1 DA |
1386 | clk_disable_unprepare(imx_data->clk_ahb); |
1387 | ||
1388 | return ret; | |
1389 | } | |
1390 | ||
1391 | static int sdhci_esdhc_runtime_resume(struct device *dev) | |
1392 | { | |
1393 | struct sdhci_host *host = dev_get_drvdata(dev); | |
1394 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
070e6d3f | 1395 | struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); |
89d7e5c1 | 1396 | |
be138554 RK |
1397 | if (!sdhci_sdio_irq_enabled(host)) { |
1398 | clk_prepare_enable(imx_data->clk_per); | |
1399 | clk_prepare_enable(imx_data->clk_ipg); | |
1400 | } | |
89d7e5c1 DA |
1401 | clk_prepare_enable(imx_data->clk_ahb); |
1402 | ||
1403 | return sdhci_runtime_resume_host(host); | |
1404 | } | |
1405 | #endif | |
1406 | ||
1407 | static const struct dev_pm_ops sdhci_esdhc_pmops = { | |
04143fba | 1408 | SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume) |
89d7e5c1 DA |
1409 | SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend, |
1410 | sdhci_esdhc_runtime_resume, NULL) | |
1411 | }; | |
1412 | ||
85d6509d SG |
1413 | static struct platform_driver sdhci_esdhc_imx_driver = { |
1414 | .driver = { | |
1415 | .name = "sdhci-esdhc-imx", | |
abfafc2d | 1416 | .of_match_table = imx_esdhc_dt_ids, |
89d7e5c1 | 1417 | .pm = &sdhci_esdhc_pmops, |
85d6509d | 1418 | }, |
57ed3314 | 1419 | .id_table = imx_esdhc_devtype, |
85d6509d | 1420 | .probe = sdhci_esdhc_imx_probe, |
0433c143 | 1421 | .remove = sdhci_esdhc_imx_remove, |
95f25efe | 1422 | }; |
85d6509d | 1423 | |
d1f81a64 | 1424 | module_platform_driver(sdhci_esdhc_imx_driver); |
85d6509d SG |
1425 | |
1426 | MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); | |
035ff831 | 1427 | MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>"); |
85d6509d | 1428 | MODULE_LICENSE("GPL v2"); |