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Merge branch 'timer/cleanup' into late/mvebu2
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / mmc / host / rtsx_pci_sdmmc.c
CommitLineData
ff984e57
WW		 1/* Realtek PCI-Express SD/MMC Card Interface driver
2 *
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21 */
22
23#include <linux/module.h>
433e075c 24#include <linux/slab.h>
ff984e57
WW		 25#include <linux/highmem.h>
26#include <linux/delay.h>
27#include <linux/platform_device.h>
28#include <linux/mmc/host.h>
29#include <linux/mmc/mmc.h>
30#include <linux/mmc/sd.h>
31#include <linux/mmc/card.h>
32#include <linux/mfd/rtsx_pci.h>
33#include <asm/unaligned.h>
34
35/* SD Tuning Data Structure
36 * Record continuous timing phase path
37 */
38struct timing_phase_path {
39 int start;
40 int end;
41 int mid;
42 int len;
43};
44
45struct realtek_pci_sdmmc {
46 struct platform_device *pdev;
47 struct rtsx_pcr *pcr;
48 struct mmc_host *mmc;
49 struct mmc_request *mrq;
50
51 struct mutex host_mutex;
52
53 u8 ssc_depth;
54 unsigned int clock;
55 bool vpclk;
56 bool double_clk;
57 bool eject;
58 bool initial_mode;
59 bool ddr_mode;
60};
61
62static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host)
63{
64 return &(host->pdev->dev);
65}
66
67static inline void sd_clear_error(struct realtek_pci_sdmmc *host)
68{
69 rtsx_pci_write_register(host->pcr, CARD_STOP,
70 SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
71}
72
73#ifdef DEBUG
74static void sd_print_debug_regs(struct realtek_pci_sdmmc *host)
75{
76 struct rtsx_pcr *pcr = host->pcr;
77 u16 i;
78 u8 *ptr;
79
80 /* Print SD host internal registers */
81 rtsx_pci_init_cmd(pcr);
82 for (i = 0xFDA0; i <= 0xFDAE; i++)
83 rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0);
84 for (i = 0xFD52; i <= 0xFD69; i++)
85 rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0);
86 rtsx_pci_send_cmd(pcr, 100);
87
88 ptr = rtsx_pci_get_cmd_data(pcr);
89 for (i = 0xFDA0; i <= 0xFDAE; i++)
90 dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++));
91 for (i = 0xFD52; i <= 0xFD69; i++)
92 dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++));
93}
94#else
95#define sd_print_debug_regs(host)
96#endif /* DEBUG */
97
98static int sd_read_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt,
99 u8 *buf, int buf_len, int timeout)
100{
101 struct rtsx_pcr *pcr = host->pcr;
102 int err, i;
103 u8 trans_mode;
104
105 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD%d\n", __func__, cmd[0] - 0x40);
106
107 if (!buf)
108 buf_len = 0;
109
110 if ((cmd[0] & 0x3F) == MMC_SEND_TUNING_BLOCK)
111 trans_mode = SD_TM_AUTO_TUNING;
112 else
113 trans_mode = SD_TM_NORMAL_READ;
114
115 rtsx_pci_init_cmd(pcr);
116
117 for (i = 0; i < 5; i++)
118 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0 + i, 0xFF, cmd[i]);
119
120 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
121 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H,
122 0xFF, (u8)(byte_cnt >> 8));
123 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1);
124 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0);
125
126 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
127 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
128 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
129 if (trans_mode != SD_TM_AUTO_TUNING)
130 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
131 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
132
133 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
134 0xFF, trans_mode | SD_TRANSFER_START);
135 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
136 SD_TRANSFER_END, SD_TRANSFER_END);
137
138 err = rtsx_pci_send_cmd(pcr, timeout);
139 if (err < 0) {
140 sd_print_debug_regs(host);
141 dev_dbg(sdmmc_dev(host),
142 "rtsx_pci_send_cmd fail (err = %d)\n", err);
143 return err;
144 }
145
146 if (buf && buf_len) {
147 err = rtsx_pci_read_ppbuf(pcr, buf, buf_len);
148 if (err < 0) {
149 dev_dbg(sdmmc_dev(host),
150 "rtsx_pci_read_ppbuf fail (err = %d)\n", err);
151 return err;
152 }
153 }
154
155 return 0;
156}
157
158static int sd_write_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt,
159 u8 *buf, int buf_len, int timeout)
160{
161 struct rtsx_pcr *pcr = host->pcr;
162 int err, i;
163 u8 trans_mode;
164
165 if (!buf)
166 buf_len = 0;
167
168 if (buf && buf_len) {
169 err = rtsx_pci_write_ppbuf(pcr, buf, buf_len);
170 if (err < 0) {
171 dev_dbg(sdmmc_dev(host),
172 "rtsx_pci_write_ppbuf fail (err = %d)\n", err);
173 return err;
174 }
175 }
176
177 trans_mode = cmd ? SD_TM_AUTO_WRITE_2 : SD_TM_AUTO_WRITE_3;
178 rtsx_pci_init_cmd(pcr);
179
180 if (cmd) {
181 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d\n", __func__,
182 cmd[0] - 0x40);
183
184 for (i = 0; i < 5; i++)
185 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
186 SD_CMD0 + i, 0xFF, cmd[i]);
187 }
188
189 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
190 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H,
191 0xFF, (u8)(byte_cnt >> 8));
192 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1);
193 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0);
194
195 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
196 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
197 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
198
199 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
200 trans_mode | SD_TRANSFER_START);
201 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
202 SD_TRANSFER_END, SD_TRANSFER_END);
203
204 err = rtsx_pci_send_cmd(pcr, timeout);
205 if (err < 0) {
206 sd_print_debug_regs(host);
207 dev_dbg(sdmmc_dev(host),
208 "rtsx_pci_send_cmd fail (err = %d)\n", err);
209 return err;
210 }
211
212 return 0;
213}
214
215static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host,
216 struct mmc_command *cmd)
217{
218 struct rtsx_pcr *pcr = host->pcr;
219 u8 cmd_idx = (u8)cmd->opcode;
220 u32 arg = cmd->arg;
221 int err = 0;
222 int timeout = 100;
223 int i;
224 u8 *ptr;
225 int stat_idx = 0;
226 u8 rsp_type;
227 int rsp_len = 5;
228
229 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
230 __func__, cmd_idx, arg);
231
232 /* Response type:
233 * R0
234 * R1, R5, R6, R7
235 * R1b
236 * R2
237 * R3, R4
238 */
239 switch (mmc_resp_type(cmd)) {
240 case MMC_RSP_NONE:
241 rsp_type = SD_RSP_TYPE_R0;
242 rsp_len = 0;
243 break;
244 case MMC_RSP_R1:
245 rsp_type = SD_RSP_TYPE_R1;
246 break;
247 case MMC_RSP_R1B:
248 rsp_type = SD_RSP_TYPE_R1b;
249 break;
250 case MMC_RSP_R2:
251 rsp_type = SD_RSP_TYPE_R2;
252 rsp_len = 16;
253 break;
254 case MMC_RSP_R3:
255 rsp_type = SD_RSP_TYPE_R3;
256 break;
257 default:
258 dev_dbg(sdmmc_dev(host), "cmd->flag is not valid\n");
259 err = -EINVAL;
260 goto out;
261 }
262
263 if (rsp_type == SD_RSP_TYPE_R1b)
264 timeout = 3000;
265
266 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
267 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
268 0xFF, SD_CLK_TOGGLE_EN);
269 if (err < 0)
270 goto out;
271 }
272
273 rtsx_pci_init_cmd(pcr);
274
275 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF, 0x40 | cmd_idx);
276 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD1, 0xFF, (u8)(arg >> 24));
277 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD2, 0xFF, (u8)(arg >> 16));
278 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD3, 0xFF, (u8)(arg >> 8));
279 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD4, 0xFF, (u8)arg);
280
281 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
282 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
283 0x01, PINGPONG_BUFFER);
284 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
285 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
286 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
287 SD_TRANSFER_END | SD_STAT_IDLE,
288 SD_TRANSFER_END | SD_STAT_IDLE);
289
290 if (rsp_type == SD_RSP_TYPE_R2) {
291 /* Read data from ping-pong buffer */
292 for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++)
293 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
294 stat_idx = 16;
295 } else if (rsp_type != SD_RSP_TYPE_R0) {
296 /* Read data from SD_CMDx registers */
297 for (i = SD_CMD0; i <= SD_CMD4; i++)
298 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
299 stat_idx = 5;
300 }
301
302 rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0);
303
304 err = rtsx_pci_send_cmd(pcr, timeout);
305 if (err < 0) {
306 sd_print_debug_regs(host);
307 sd_clear_error(host);
308 dev_dbg(sdmmc_dev(host),
309 "rtsx_pci_send_cmd error (err = %d)\n", err);
310 goto out;
311 }
312
313 if (rsp_type == SD_RSP_TYPE_R0) {
314 err = 0;
315 goto out;
316 }
317
318 /* Eliminate returned value of CHECK_REG_CMD */
319 ptr = rtsx_pci_get_cmd_data(pcr) + 1;
320
321 /* Check (Start,Transmission) bit of Response */
322 if ((ptr[0] & 0xC0) != 0) {
323 err = -EILSEQ;
324 dev_dbg(sdmmc_dev(host), "Invalid response bit\n");
325 goto out;
326 }
327
328 /* Check CRC7 */
329 if (!(rsp_type & SD_NO_CHECK_CRC7)) {
330 if (ptr[stat_idx] & SD_CRC7_ERR) {
331 err = -EILSEQ;
332 dev_dbg(sdmmc_dev(host), "CRC7 error\n");
333 goto out;
334 }
335 }
336
337 if (rsp_type == SD_RSP_TYPE_R2) {
338 for (i = 0; i < 4; i++) {
339 cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4);
340 dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n",
341 i, cmd->resp[i]);
342 }
343 } else {
344 cmd->resp[0] = get_unaligned_be32(ptr + 1);
345 dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n",
346 cmd->resp[0]);
347 }
348
349out:
350 cmd->error = err;
351}
352
353static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq)
354{
355 struct rtsx_pcr *pcr = host->pcr;
356 struct mmc_host *mmc = host->mmc;
357 struct mmc_card *card = mmc->card;
358 struct mmc_data *data = mrq->data;
359 int uhs = mmc_sd_card_uhs(card);
360 int read = (data->flags & MMC_DATA_READ) ? 1 : 0;
361 u8 cfg2, trans_mode;
362 int err;
363 size_t data_len = data->blksz * data->blocks;
364
365 if (read) {
366 cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
367 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0;
368 trans_mode = SD_TM_AUTO_READ_3;
369 } else {
370 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
371 SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
372 trans_mode = SD_TM_AUTO_WRITE_3;
373 }
374
375 if (!uhs)
376 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
377
378 rtsx_pci_init_cmd(pcr);
379
380 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, 0x00);
381 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, 0x02);
382 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L,
383 0xFF, (u8)data->blocks);
384 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H,
385 0xFF, (u8)(data->blocks >> 8));
ff984e57
WW		 386
387 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
388 DMA_DONE_INT, DMA_DONE_INT);
389 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
390 0xFF, (u8)(data_len >> 24));
391 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
392 0xFF, (u8)(data_len >> 16));
393 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
394 0xFF, (u8)(data_len >> 8));
395 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
396 if (read) {
397 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
398 0x03 | DMA_PACK_SIZE_MASK,
399 DMA_DIR_FROM_CARD | DMA_EN | DMA_512);
400 } else {
401 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
402 0x03 | DMA_PACK_SIZE_MASK,
403 DMA_DIR_TO_CARD | DMA_EN | DMA_512);
404 }
405
406 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
407 0x01, RING_BUFFER);
408
38d324df 409 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
ff984e57
WW		 410 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
411 trans_mode | SD_TRANSFER_START);
412 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
413 SD_TRANSFER_END, SD_TRANSFER_END);
414
415 rtsx_pci_send_cmd_no_wait(pcr);
416
417 err = rtsx_pci_transfer_data(pcr, data->sg, data->sg_len, read, 10000);
418 if (err < 0) {
419 sd_clear_error(host);
420 return err;
421 }
422
423 return 0;
424}
425
426static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host)
427{
428 rtsx_pci_write_register(host->pcr, SD_CFG1,
429 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128);
430}
431
432static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host)
433{
434 rtsx_pci_write_register(host->pcr, SD_CFG1,
435 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
436}
437
438static void sd_normal_rw(struct realtek_pci_sdmmc *host,
439 struct mmc_request *mrq)
440{
441 struct mmc_command *cmd = mrq->cmd;
442 struct mmc_data *data = mrq->data;
443 u8 _cmd[5], *buf;
444
445 _cmd[0] = 0x40 | (u8)cmd->opcode;
446 put_unaligned_be32(cmd->arg, (u32 *)(&_cmd[1]));
447
448 buf = kzalloc(data->blksz, GFP_NOIO);
449 if (!buf) {
450 cmd->error = -ENOMEM;
451 return;
452 }
453
454 if (data->flags & MMC_DATA_READ) {
455 if (host->initial_mode)
456 sd_disable_initial_mode(host);
457
458 cmd->error = sd_read_data(host, _cmd, (u16)data->blksz, buf,
459 data->blksz, 200);
460
461 if (host->initial_mode)
462 sd_enable_initial_mode(host);
463
464 sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz);
465 } else {
466 sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz);
467
468 cmd->error = sd_write_data(host, _cmd, (u16)data->blksz, buf,
469 data->blksz, 200);
470 }
471
472 kfree(buf);
473}
474
475static int sd_change_phase(struct realtek_pci_sdmmc *host, u8 sample_point)
476{
477 struct rtsx_pcr *pcr = host->pcr;
478 int err;
479
480 dev_dbg(sdmmc_dev(host), "%s: sample_point = %d\n",
481 __func__, sample_point);
482
483 rtsx_pci_init_cmd(pcr);
484
485 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
486 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPRX_CTL, 0x1F, sample_point);
487 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
488 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
489 PHASE_NOT_RESET, PHASE_NOT_RESET);
490 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0);
491 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
492
493 err = rtsx_pci_send_cmd(pcr, 100);
494 if (err < 0)
495 return err;
496
497 return 0;
498}
499
500static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map)
501{
502 struct timing_phase_path path[MAX_PHASE + 1];
503 int i, j, cont_path_cnt;
504 int new_block, max_len, final_path_idx;
505 u8 final_phase = 0xFF;
506
507 /* Parse phase_map, take it as a bit-ring */
508 cont_path_cnt = 0;
509 new_block = 1;
510 j = 0;
511 for (i = 0; i < MAX_PHASE + 1; i++) {
512 if (phase_map & (1 << i)) {
513 if (new_block) {
514 new_block = 0;
515 j = cont_path_cnt++;
516 path[j].start = i;
517 path[j].end = i;
518 } else {
519 path[j].end = i;
520 }
521 } else {
522 new_block = 1;
523 if (cont_path_cnt) {
524 /* Calculate path length and middle point */
525 int idx = cont_path_cnt - 1;
526 path[idx].len =
527 path[idx].end - path[idx].start + 1;
528 path[idx].mid =
529 path[idx].start + path[idx].len / 2;
530 }
531 }
532 }
533
534 if (cont_path_cnt == 0) {
535 dev_dbg(sdmmc_dev(host), "No continuous phase path\n");
536 goto finish;
537 } else {
538 /* Calculate last continuous path length and middle point */
539 int idx = cont_path_cnt - 1;
540 path[idx].len = path[idx].end - path[idx].start + 1;
541 path[idx].mid = path[idx].start + path[idx].len / 2;
542 }
543
544 /* Connect the first and last continuous paths if they are adjacent */
545 if (!path[0].start && (path[cont_path_cnt - 1].end == MAX_PHASE)) {
546 /* Using negative index */
547 path[0].start = path[cont_path_cnt - 1].start - MAX_PHASE - 1;
548 path[0].len += path[cont_path_cnt - 1].len;
549 path[0].mid = path[0].start + path[0].len / 2;
550 /* Convert negative middle point index to positive one */
551 if (path[0].mid < 0)
552 path[0].mid += MAX_PHASE + 1;
553 cont_path_cnt--;
554 }
555
556 /* Choose the longest continuous phase path */
557 max_len = 0;
558 final_phase = 0;
559 final_path_idx = 0;
560 for (i = 0; i < cont_path_cnt; i++) {
561 if (path[i].len > max_len) {
562 max_len = path[i].len;
563 final_phase = (u8)path[i].mid;
564 final_path_idx = i;
565 }
566
567 dev_dbg(sdmmc_dev(host), "path[%d].start = %d\n",
568 i, path[i].start);
569 dev_dbg(sdmmc_dev(host), "path[%d].end = %d\n",
570 i, path[i].end);
571 dev_dbg(sdmmc_dev(host), "path[%d].len = %d\n",
572 i, path[i].len);
573 dev_dbg(sdmmc_dev(host), "path[%d].mid = %d\n",
574 i, path[i].mid);
575 }
576
577finish:
578 dev_dbg(sdmmc_dev(host), "Final chosen phase: %d\n", final_phase);
579 return final_phase;
580}
581
582static void sd_wait_data_idle(struct realtek_pci_sdmmc *host)
583{
584 int err, i;
585 u8 val = 0;
586
587 for (i = 0; i < 100; i++) {
588 err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val);
589 if (val & SD_DATA_IDLE)
590 return;
591
592 udelay(100);
593 }
594}
595
596static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host,
597 u8 opcode, u8 sample_point)
598{
599 int err;
600 u8 cmd[5] = {0};
601
602 err = sd_change_phase(host, sample_point);
603 if (err < 0)
604 return err;
605
606 cmd[0] = 0x40 | opcode;
607 err = sd_read_data(host, cmd, 0x40, NULL, 0, 100);
608 if (err < 0) {
609 /* Wait till SD DATA IDLE */
610 sd_wait_data_idle(host);
611 sd_clear_error(host);
612 return err;
613 }
614
615 return 0;
616}
617
618static int sd_tuning_phase(struct realtek_pci_sdmmc *host,
619 u8 opcode, u32 *phase_map)
620{
621 int err, i;
622 u32 raw_phase_map = 0;
623
624 for (i = MAX_PHASE; i >= 0; i--) {
625 err = sd_tuning_rx_cmd(host, opcode, (u8)i);
626 if (err == 0)
627 raw_phase_map |= 1 << i;
628 }
629
630 if (phase_map)
631 *phase_map = raw_phase_map;
632
633 return 0;
634}
635
636static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode)
637{
638 int err, i;
639 u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map;
640 u8 final_phase;
641
642 for (i = 0; i < RX_TUNING_CNT; i++) {
643 err = sd_tuning_phase(host, opcode, &(raw_phase_map[i]));
644 if (err < 0)
645 return err;
646
647 if (raw_phase_map[i] == 0)
648 break;
649 }
650
651 phase_map = 0xFFFFFFFF;
652 for (i = 0; i < RX_TUNING_CNT; i++) {
653 dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n",
654 i, raw_phase_map[i]);
655 phase_map &= raw_phase_map[i];
656 }
657 dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map);
658
659 if (phase_map) {
660 final_phase = sd_search_final_phase(host, phase_map);
661 if (final_phase == 0xFF)
662 return -EINVAL;
663
664 err = sd_change_phase(host, final_phase);
665 if (err < 0)
666 return err;
667 } else {
668 return -EINVAL;
669 }
670
671 return 0;
672}
673
674static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
675{
676 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
677 struct rtsx_pcr *pcr = host->pcr;
678 struct mmc_command *cmd = mrq->cmd;
679 struct mmc_data *data = mrq->data;
680 unsigned int data_size = 0;
681
682 if (host->eject) {
683 cmd->error = -ENOMEDIUM;
684 goto finish;
685 }
686
687 mutex_lock(&pcr->pcr_mutex);
688
689 rtsx_pci_start_run(pcr);
690
691 rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth,
692 host->initial_mode, host->double_clk, host->vpclk);
693 rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL);
694 rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
695 CARD_SHARE_MASK, CARD_SHARE_48_SD);
696
697 mutex_lock(&host->host_mutex);
698 host->mrq = mrq;
699 mutex_unlock(&host->host_mutex);
700
701 if (mrq->data)
702 data_size = data->blocks * data->blksz;
703
704 if (!data_size || mmc_op_multi(cmd->opcode) ||
705 (cmd->opcode == MMC_READ_SINGLE_BLOCK) ||
706 (cmd->opcode == MMC_WRITE_BLOCK)) {
707 sd_send_cmd_get_rsp(host, cmd);
708
709 if (!cmd->error && data_size) {
710 sd_rw_multi(host, mrq);
711
712 if (mmc_op_multi(cmd->opcode) && mrq->stop)
713 sd_send_cmd_get_rsp(host, mrq->stop);
714 }
715 } else {
716 sd_normal_rw(host, mrq);
717 }
718
719 if (mrq->data) {
720 if (cmd->error || data->error)
721 data->bytes_xfered = 0;
722 else
723 data->bytes_xfered = data->blocks * data->blksz;
724 }
725
726 mutex_unlock(&pcr->pcr_mutex);
727
728finish:
729 if (cmd->error)
730 dev_dbg(sdmmc_dev(host), "cmd->error = %d\n", cmd->error);
731
732 mutex_lock(&host->host_mutex);
733 host->mrq = NULL;
734 mutex_unlock(&host->host_mutex);
735
736 mmc_request_done(mmc, mrq);
737}
738
739static int sd_set_bus_width(struct realtek_pci_sdmmc *host,
740 unsigned char bus_width)
741{
742 int err = 0;
743 u8 width[] = {
744 [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT,
745 [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT,
746 [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT,
747 };
748
749 if (bus_width <= MMC_BUS_WIDTH_8)
750 err = rtsx_pci_write_register(host->pcr, SD_CFG1,
751 0x03, width[bus_width]);
752
753 return err;
754}
755
756static int sd_power_on(struct realtek_pci_sdmmc *host)
757{
758 struct rtsx_pcr *pcr = host->pcr;
759 int err;
760
761 rtsx_pci_init_cmd(pcr);
762 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
763 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
764 CARD_SHARE_MASK, CARD_SHARE_48_SD);
765 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
766 SD_CLK_EN, SD_CLK_EN);
767 err = rtsx_pci_send_cmd(pcr, 100);
768 if (err < 0)
769 return err;
770
771 err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD);
772 if (err < 0)
773 return err;
774
775 err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD);
776 if (err < 0)
777 return err;
778
779 err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
780 if (err < 0)
781 return err;
782
783 return 0;
784}
785
786static int sd_power_off(struct realtek_pci_sdmmc *host)
787{
788 struct rtsx_pcr *pcr = host->pcr;
789 int err;
790
791 rtsx_pci_init_cmd(pcr);
792
793 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
794 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
795
796 err = rtsx_pci_send_cmd(pcr, 100);
797 if (err < 0)
798 return err;
799
800 err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
801 if (err < 0)
802 return err;
803
804 return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
805}
806
807static int sd_set_power_mode(struct realtek_pci_sdmmc *host,
808 unsigned char power_mode)
809{
810 int err;
811
812 if (power_mode == MMC_POWER_OFF)
813 err = sd_power_off(host);
814 else
815 err = sd_power_on(host);
816
817 return err;
818}
819
820static int sd_set_timing(struct realtek_pci_sdmmc *host,
821 unsigned char timing, bool *ddr_mode)
822{
823 struct rtsx_pcr *pcr = host->pcr;
824 int err = 0;
825
826 *ddr_mode = false;
827
828 rtsx_pci_init_cmd(pcr);
829
830 switch (timing) {
831 case MMC_TIMING_UHS_SDR104:
832 case MMC_TIMING_UHS_SDR50:
833 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
834 0x0C | SD_ASYNC_FIFO_NOT_RST,
835 SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
836 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
837 CLK_LOW_FREQ, CLK_LOW_FREQ);
838 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
839 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
840 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
841 break;
842
843 case MMC_TIMING_UHS_DDR50:
844 *ddr_mode = true;
845
846 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
847 0x0C | SD_ASYNC_FIFO_NOT_RST,
848 SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
849 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
850 CLK_LOW_FREQ, CLK_LOW_FREQ);
851 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
852 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
853 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
854 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
855 DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT);
856 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
857 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
858 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
859 break;
860
861 case MMC_TIMING_MMC_HS:
862 case MMC_TIMING_SD_HS:
863 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
864 0x0C, SD_20_MODE);
865 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
866 CLK_LOW_FREQ, CLK_LOW_FREQ);
867 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
868 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
869 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
870 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
871 SD20_TX_SEL_MASK, SD20_TX_14_AHEAD);
872 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
873 SD20_RX_SEL_MASK, SD20_RX_14_DELAY);
874 break;
875
876 default:
877 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
878 SD_CFG1, 0x0C, SD_20_MODE);
879 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
880 CLK_LOW_FREQ, CLK_LOW_FREQ);
881 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
882 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
883 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
884 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
885 SD_PUSH_POINT_CTL, 0xFF, 0);
886 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
887 SD20_RX_SEL_MASK, SD20_RX_POS_EDGE);
888 break;
889 }
890
891 err = rtsx_pci_send_cmd(pcr, 100);
892
893 return err;
894}
895
896static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
897{
898 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
899 struct rtsx_pcr *pcr = host->pcr;
900
901 if (host->eject)
902 return;
903
904 mutex_lock(&pcr->pcr_mutex);
905
906 rtsx_pci_start_run(pcr);
907
908 sd_set_bus_width(host, ios->bus_width);
909 sd_set_power_mode(host, ios->power_mode);
910 sd_set_timing(host, ios->timing, &host->ddr_mode);
911
912 host->vpclk = false;
913 host->double_clk = true;
914
915 switch (ios->timing) {
916 case MMC_TIMING_UHS_SDR104:
917 case MMC_TIMING_UHS_SDR50:
918 host->ssc_depth = RTSX_SSC_DEPTH_2M;
919 host->vpclk = true;
920 host->double_clk = false;
921 break;
922 case MMC_TIMING_UHS_DDR50:
923 case MMC_TIMING_UHS_SDR25:
924 host->ssc_depth = RTSX_SSC_DEPTH_1M;
925 break;
926 default:
927 host->ssc_depth = RTSX_SSC_DEPTH_500K;
928 break;
929 }
930
931 host->initial_mode = (ios->clock <= 1000000) ? true : false;
932
933 host->clock = ios->clock;
934 rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth,
935 host->initial_mode, host->double_clk, host->vpclk);
936
937 mutex_unlock(&pcr->pcr_mutex);
938}
939
940static int sdmmc_get_ro(struct mmc_host *mmc)
941{
942 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
943 struct rtsx_pcr *pcr = host->pcr;
944 int ro = 0;
945 u32 val;
946
947 if (host->eject)
948 return -ENOMEDIUM;
949
950 mutex_lock(&pcr->pcr_mutex);
951
952 rtsx_pci_start_run(pcr);
953
954 /* Check SD mechanical write-protect switch */
955 val = rtsx_pci_readl(pcr, RTSX_BIPR);
956 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
957 if (val & SD_WRITE_PROTECT)
958 ro = 1;
959
960 mutex_unlock(&pcr->pcr_mutex);
961
962 return ro;
963}
964
965static int sdmmc_get_cd(struct mmc_host *mmc)
966{
967 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
968 struct rtsx_pcr *pcr = host->pcr;
969 int cd = 0;
970 u32 val;
971
972 if (host->eject)
973 return -ENOMEDIUM;
974
975 mutex_lock(&pcr->pcr_mutex);
976
977 rtsx_pci_start_run(pcr);
978
979 /* Check SD card detect */
980 val = rtsx_pci_card_exist(pcr);
981 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
982 if (val & SD_EXIST)
983 cd = 1;
984
985 mutex_unlock(&pcr->pcr_mutex);
986
987 return cd;
988}
989
990static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host)
991{
992 struct rtsx_pcr *pcr = host->pcr;
993 int err;
994 u8 stat;
995
996 /* Reference to Signal Voltage Switch Sequence in SD spec.
997 * Wait for a period of time so that the card can drive SD_CMD and
998 * SD_DAT[3:0] to low after sending back CMD11 response.
999 */
1000 mdelay(1);
1001
1002 /* SD_CMD, SD_DAT[3:0] should be driven to low by card;
1003 * If either one of SD_CMD,SD_DAT[3:0] is not low,
1004 * abort the voltage switch sequence;
1005 */
1006 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1007 if (err < 0)
1008 return err;
1009
1010 if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1011 SD_DAT1_STATUS | SD_DAT0_STATUS))
1012 return -EINVAL;
1013
1014 /* Stop toggle SD clock */
1015 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1016 0xFF, SD_CLK_FORCE_STOP);
1017 if (err < 0)
1018 return err;
1019
1020 return 0;
1021}
1022
1023static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host)
1024{
1025 struct rtsx_pcr *pcr = host->pcr;
1026 int err;
1027 u8 stat, mask, val;
1028
1029 /* Wait 1.8V output of voltage regulator in card stable */
1030 msleep(50);
1031
1032 /* Toggle SD clock again */
1033 err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
1034 if (err < 0)
1035 return err;
1036
1037 /* Wait for a period of time so that the card can drive
1038 * SD_DAT[3:0] to high at 1.8V
1039 */
1040 msleep(20);
1041
1042 /* SD_CMD, SD_DAT[3:0] should be pulled high by host */
1043 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1044 if (err < 0)
1045 return err;
1046
1047 mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1048 SD_DAT1_STATUS | SD_DAT0_STATUS;
1049 val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1050 SD_DAT1_STATUS | SD_DAT0_STATUS;
1051 if ((stat & mask) != val) {
1052 dev_dbg(sdmmc_dev(host),
1053 "%s: SD_BUS_STAT = 0x%x\n", __func__, stat);
1054 rtsx_pci_write_register(pcr, SD_BUS_STAT,
1055 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1056 rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0);
1057 return -EINVAL;
1058 }
1059
1060 return 0;
1061}
1062
ff984e57
WW		 1063static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1064{
1065 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1066 struct rtsx_pcr *pcr = host->pcr;
1067 int err = 0;
1068 u8 voltage;
1069
1070 dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n",
1071 __func__, ios->signal_voltage);
1072
1073 if (host->eject)
1074 return -ENOMEDIUM;
1075
1076 mutex_lock(&pcr->pcr_mutex);
1077
1078 rtsx_pci_start_run(pcr);
1079
1080 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
ef85e736 1081 voltage = OUTPUT_3V3;
ff984e57 1082 else
ef85e736 1083 voltage = OUTPUT_1V8;
ff984e57 1084
ef85e736 1085 if (voltage == OUTPUT_1V8) {
ff984e57
WW		 1086 err = rtsx_pci_write_register(pcr,
1087 SD30_DRIVE_SEL, 0x07, DRIVER_TYPE_B);
1088 if (err < 0)
1089 goto out;
1090
1091 err = sd_wait_voltage_stable_1(host);
1092 if (err < 0)
1093 goto out;
1094 }
1095
ef85e736 1096 err = rtsx_pci_switch_output_voltage(pcr, voltage);
ff984e57
WW		 1097 if (err < 0)
1098 goto out;
1099
ef85e736 1100 if (voltage == OUTPUT_1V8) {
ff984e57
WW		 1101 err = sd_wait_voltage_stable_2(host);
1102 if (err < 0)
1103 goto out;
1104 }
1105
1106 /* Stop toggle SD clock in idle */
1107 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1108 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1109
1110out:
1111 mutex_unlock(&pcr->pcr_mutex);
1112
1113 return err;
1114}
1115
1116static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1117{
1118 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1119 struct rtsx_pcr *pcr = host->pcr;
1120 int err = 0;
1121
1122 if (host->eject)
1123 return -ENOMEDIUM;
1124
1125 mutex_lock(&pcr->pcr_mutex);
1126
1127 rtsx_pci_start_run(pcr);
1128
1129 if (!host->ddr_mode)
1130 err = sd_tuning_rx(host, MMC_SEND_TUNING_BLOCK);
1131
1132 mutex_unlock(&pcr->pcr_mutex);
1133
1134 return err;
1135}
1136
1137static const struct mmc_host_ops realtek_pci_sdmmc_ops = {
1138 .request = sdmmc_request,
1139 .set_ios = sdmmc_set_ios,
1140 .get_ro = sdmmc_get_ro,
1141 .get_cd = sdmmc_get_cd,
1142 .start_signal_voltage_switch = sdmmc_switch_voltage,
1143 .execute_tuning = sdmmc_execute_tuning,
1144};
1145
1146#ifdef CONFIG_PM
1147static int rtsx_pci_sdmmc_suspend(struct platform_device *pdev,
1148 pm_message_t state)
1149{
1150 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1151 struct mmc_host *mmc = host->mmc;
1152 int err;
1153
1154 dev_dbg(sdmmc_dev(host), "--> %s\n", __func__);
1155
1156 err = mmc_suspend_host(mmc);
1157 if (err)
1158 return err;
1159
1160 return 0;
1161}
1162
1163static int rtsx_pci_sdmmc_resume(struct platform_device *pdev)
1164{
1165 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1166 struct mmc_host *mmc = host->mmc;
1167
1168 dev_dbg(sdmmc_dev(host), "--> %s\n", __func__);
1169
1170 return mmc_resume_host(mmc);
1171}
1172#else /* CONFIG_PM */
1173#define rtsx_pci_sdmmc_suspend NULL
1174#define rtsx_pci_sdmmc_resume NULL
1175#endif /* CONFIG_PM */
1176
1177static void init_extra_caps(struct realtek_pci_sdmmc *host)
1178{
1179 struct mmc_host *mmc = host->mmc;
1180 struct rtsx_pcr *pcr = host->pcr;
1181
1182 dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps);
1183
1184 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50)
1185 mmc->caps |= MMC_CAP_UHS_SDR50;
1186 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
1187 mmc->caps |= MMC_CAP_UHS_SDR104;
1188 if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50)
1189 mmc->caps |= MMC_CAP_UHS_DDR50;
1190 if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR)
1191 mmc->caps |= MMC_CAP_1_8V_DDR;
1192 if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT)
1193 mmc->caps |= MMC_CAP_8_BIT_DATA;
1194}
1195
1196static void realtek_init_host(struct realtek_pci_sdmmc *host)
1197{
1198 struct mmc_host *mmc = host->mmc;
1199
1200 mmc->f_min = 250000;
1201 mmc->f_max = 208000000;
1202 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1203 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
1204 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST |
1205 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
1206 mmc->max_current_330 = 400;
1207 mmc->max_current_180 = 800;
1208 mmc->ops = &realtek_pci_sdmmc_ops;
1209
1210 init_extra_caps(host);
1211
1212 mmc->max_segs = 256;
1213 mmc->max_seg_size = 65536;
1214 mmc->max_blk_size = 512;
1215 mmc->max_blk_count = 65535;
1216 mmc->max_req_size = 524288;
1217}
1218
1219static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev)
1220{
1221 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1222
1223 mmc_detect_change(host->mmc, 0);
1224}
1225
1226static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev)
1227{
1228 struct mmc_host *mmc;
1229 struct realtek_pci_sdmmc *host;
1230 struct rtsx_pcr *pcr;
1231 struct pcr_handle *handle = pdev->dev.platform_data;
1232
1233 if (!handle)
1234 return -ENXIO;
1235
1236 pcr = handle->pcr;
1237 if (!pcr)
1238 return -ENXIO;
1239
1240 dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n");
1241
1242 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1243 if (!mmc)
1244 return -ENOMEM;
1245
1246 host = mmc_priv(mmc);
1247 host->pcr = pcr;
1248 host->mmc = mmc;
1249 host->pdev = pdev;
1250 platform_set_drvdata(pdev, host);
1251 pcr->slots[RTSX_SD_CARD].p_dev = pdev;
1252 pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event;
1253
1254 mutex_init(&host->host_mutex);
1255
1256 realtek_init_host(host);
1257
1258 mmc_add_host(mmc);
1259
1260 return 0;
1261}
1262
1263static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev)
1264{
1265 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1266 struct rtsx_pcr *pcr;
1267 struct mmc_host *mmc;
1268
1269 if (!host)
1270 return 0;
1271
1272 pcr = host->pcr;
1273 pcr->slots[RTSX_SD_CARD].p_dev = NULL;
1274 pcr->slots[RTSX_SD_CARD].card_event = NULL;
1275 mmc = host->mmc;
1276 host->eject = true;
1277
1278 mutex_lock(&host->host_mutex);
1279 if (host->mrq) {
1280 dev_dbg(&(pdev->dev),
1281 "%s: Controller removed during transfer\n",
1282 mmc_hostname(mmc));
1283
1284 rtsx_pci_complete_unfinished_transfer(pcr);
1285
1286 host->mrq->cmd->error = -ENOMEDIUM;
1287 if (host->mrq->stop)
1288 host->mrq->stop->error = -ENOMEDIUM;
1289 mmc_request_done(mmc, host->mrq);
1290 }
1291 mutex_unlock(&host->host_mutex);
1292
1293 mmc_remove_host(mmc);
1294 mmc_free_host(mmc);
1295
1296 platform_set_drvdata(pdev, NULL);
1297
1298 dev_dbg(&(pdev->dev),
1299 ": Realtek PCI-E SDMMC controller has been removed\n");
1300
1301 return 0;
1302}
1303
1304static struct platform_device_id rtsx_pci_sdmmc_ids[] = {
1305 {
1306 .name = DRV_NAME_RTSX_PCI_SDMMC,
1307 }, {
1308 /* sentinel */
1309 }
1310};
1311MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids);
1312
1313static struct platform_driver rtsx_pci_sdmmc_driver = {
1314 .probe = rtsx_pci_sdmmc_drv_probe,
1315 .remove = rtsx_pci_sdmmc_drv_remove,
1316 .id_table = rtsx_pci_sdmmc_ids,
1317 .suspend = rtsx_pci_sdmmc_suspend,
1318 .resume = rtsx_pci_sdmmc_resume,
1319 .driver = {
1320 .owner = THIS_MODULE,
1321 .name = DRV_NAME_RTSX_PCI_SDMMC,
1322 },
1323};
1324module_platform_driver(rtsx_pci_sdmmc_driver);
1325
1326MODULE_LICENSE("GPL");
1327MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1328MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver");
kernel source for telekom puls (alcatel/mediatek)