Commit | Line | Data |
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a45c6cb8 MC |
1 | /* |
2 | * drivers/mmc/host/omap_hsmmc.c | |
3 | * | |
4 | * Driver for OMAP2430/3430 MMC controller. | |
5 | * | |
6 | * Copyright (C) 2007 Texas Instruments. | |
7 | * | |
8 | * Authors: | |
9 | * Syed Mohammed Khasim <x0khasim@ti.com> | |
10 | * Madhusudhan <madhu.cr@ti.com> | |
11 | * Mohit Jalori <mjalori@ti.com> | |
12 | * | |
13 | * This file is licensed under the terms of the GNU General Public License | |
14 | * version 2. This program is licensed "as is" without any warranty of any | |
15 | * kind, whether express or implied. | |
16 | */ | |
17 | ||
18 | #include <linux/module.h> | |
19 | #include <linux/init.h> | |
ac330f44 | 20 | #include <linux/kernel.h> |
d900f712 | 21 | #include <linux/debugfs.h> |
c5c98927 | 22 | #include <linux/dmaengine.h> |
d900f712 | 23 | #include <linux/seq_file.h> |
031cd037 | 24 | #include <linux/sizes.h> |
a45c6cb8 MC |
25 | #include <linux/interrupt.h> |
26 | #include <linux/delay.h> | |
27 | #include <linux/dma-mapping.h> | |
28 | #include <linux/platform_device.h> | |
a45c6cb8 MC |
29 | #include <linux/timer.h> |
30 | #include <linux/clk.h> | |
46856a68 | 31 | #include <linux/of.h> |
2cd3a2a5 | 32 | #include <linux/of_irq.h> |
46856a68 RN |
33 | #include <linux/of_gpio.h> |
34 | #include <linux/of_device.h> | |
a45c6cb8 | 35 | #include <linux/mmc/host.h> |
13189e78 | 36 | #include <linux/mmc/core.h> |
93caf8e6 | 37 | #include <linux/mmc/mmc.h> |
41afa314 | 38 | #include <linux/mmc/slot-gpio.h> |
a45c6cb8 | 39 | #include <linux/io.h> |
2cd3a2a5 | 40 | #include <linux/irq.h> |
db0fefc5 AH |
41 | #include <linux/gpio.h> |
42 | #include <linux/regulator/consumer.h> | |
46b76035 | 43 | #include <linux/pinctrl/consumer.h> |
fa4aa2d4 | 44 | #include <linux/pm_runtime.h> |
5b83b223 | 45 | #include <linux/pm_wakeirq.h> |
55143438 | 46 | #include <linux/platform_data/hsmmc-omap.h> |
a45c6cb8 MC |
47 | |
48 | /* OMAP HSMMC Host Controller Registers */ | |
11dd62a7 | 49 | #define OMAP_HSMMC_SYSSTATUS 0x0014 |
a45c6cb8 | 50 | #define OMAP_HSMMC_CON 0x002C |
a2e77152 | 51 | #define OMAP_HSMMC_SDMASA 0x0100 |
a45c6cb8 MC |
52 | #define OMAP_HSMMC_BLK 0x0104 |
53 | #define OMAP_HSMMC_ARG 0x0108 | |
54 | #define OMAP_HSMMC_CMD 0x010C | |
55 | #define OMAP_HSMMC_RSP10 0x0110 | |
56 | #define OMAP_HSMMC_RSP32 0x0114 | |
57 | #define OMAP_HSMMC_RSP54 0x0118 | |
58 | #define OMAP_HSMMC_RSP76 0x011C | |
59 | #define OMAP_HSMMC_DATA 0x0120 | |
bb0635f0 | 60 | #define OMAP_HSMMC_PSTATE 0x0124 |
a45c6cb8 MC |
61 | #define OMAP_HSMMC_HCTL 0x0128 |
62 | #define OMAP_HSMMC_SYSCTL 0x012C | |
63 | #define OMAP_HSMMC_STAT 0x0130 | |
64 | #define OMAP_HSMMC_IE 0x0134 | |
65 | #define OMAP_HSMMC_ISE 0x0138 | |
a2e77152 | 66 | #define OMAP_HSMMC_AC12 0x013C |
a45c6cb8 MC |
67 | #define OMAP_HSMMC_CAPA 0x0140 |
68 | ||
69 | #define VS18 (1 << 26) | |
70 | #define VS30 (1 << 25) | |
cd587096 | 71 | #define HSS (1 << 21) |
a45c6cb8 MC |
72 | #define SDVS18 (0x5 << 9) |
73 | #define SDVS30 (0x6 << 9) | |
eb250826 | 74 | #define SDVS33 (0x7 << 9) |
1b331e69 | 75 | #define SDVS_MASK 0x00000E00 |
a45c6cb8 MC |
76 | #define SDVSCLR 0xFFFFF1FF |
77 | #define SDVSDET 0x00000400 | |
78 | #define AUTOIDLE 0x1 | |
79 | #define SDBP (1 << 8) | |
80 | #define DTO 0xe | |
81 | #define ICE 0x1 | |
82 | #define ICS 0x2 | |
83 | #define CEN (1 << 2) | |
ed164182 | 84 | #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */ |
a45c6cb8 MC |
85 | #define CLKD_MASK 0x0000FFC0 |
86 | #define CLKD_SHIFT 6 | |
87 | #define DTO_MASK 0x000F0000 | |
88 | #define DTO_SHIFT 16 | |
a45c6cb8 | 89 | #define INIT_STREAM (1 << 1) |
a2e77152 | 90 | #define ACEN_ACMD23 (2 << 2) |
a45c6cb8 MC |
91 | #define DP_SELECT (1 << 21) |
92 | #define DDIR (1 << 4) | |
a7e96879 | 93 | #define DMAE 0x1 |
a45c6cb8 MC |
94 | #define MSBS (1 << 5) |
95 | #define BCE (1 << 1) | |
96 | #define FOUR_BIT (1 << 1) | |
cd587096 | 97 | #define HSPE (1 << 2) |
5a52b08b | 98 | #define IWE (1 << 24) |
03b5d924 | 99 | #define DDR (1 << 19) |
5a52b08b B |
100 | #define CLKEXTFREE (1 << 16) |
101 | #define CTPL (1 << 11) | |
73153010 | 102 | #define DW8 (1 << 5) |
a45c6cb8 | 103 | #define OD 0x1 |
a45c6cb8 MC |
104 | #define STAT_CLEAR 0xFFFFFFFF |
105 | #define INIT_STREAM_CMD 0x00000000 | |
106 | #define DUAL_VOLT_OCR_BIT 7 | |
107 | #define SRC (1 << 25) | |
108 | #define SRD (1 << 26) | |
11dd62a7 | 109 | #define SOFTRESET (1 << 1) |
a45c6cb8 | 110 | |
f945901f AF |
111 | /* PSTATE */ |
112 | #define DLEV_DAT(x) (1 << (20 + (x))) | |
113 | ||
a7e96879 V |
114 | /* Interrupt masks for IE and ISE register */ |
115 | #define CC_EN (1 << 0) | |
116 | #define TC_EN (1 << 1) | |
117 | #define BWR_EN (1 << 4) | |
118 | #define BRR_EN (1 << 5) | |
2cd3a2a5 | 119 | #define CIRQ_EN (1 << 8) |
a7e96879 V |
120 | #define ERR_EN (1 << 15) |
121 | #define CTO_EN (1 << 16) | |
122 | #define CCRC_EN (1 << 17) | |
123 | #define CEB_EN (1 << 18) | |
124 | #define CIE_EN (1 << 19) | |
125 | #define DTO_EN (1 << 20) | |
126 | #define DCRC_EN (1 << 21) | |
127 | #define DEB_EN (1 << 22) | |
a2e77152 | 128 | #define ACE_EN (1 << 24) |
a7e96879 V |
129 | #define CERR_EN (1 << 28) |
130 | #define BADA_EN (1 << 29) | |
131 | ||
a2e77152 | 132 | #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\ |
a7e96879 V |
133 | DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \ |
134 | BRR_EN | BWR_EN | TC_EN | CC_EN) | |
135 | ||
a2e77152 B |
136 | #define CNI (1 << 7) |
137 | #define ACIE (1 << 4) | |
138 | #define ACEB (1 << 3) | |
139 | #define ACCE (1 << 2) | |
140 | #define ACTO (1 << 1) | |
141 | #define ACNE (1 << 0) | |
142 | ||
fa4aa2d4 | 143 | #define MMC_AUTOSUSPEND_DELAY 100 |
1e881786 JM |
144 | #define MMC_TIMEOUT_MS 20 /* 20 mSec */ |
145 | #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */ | |
6b206efe AS |
146 | #define OMAP_MMC_MIN_CLOCK 400000 |
147 | #define OMAP_MMC_MAX_CLOCK 52000000 | |
0005ae73 | 148 | #define DRIVER_NAME "omap_hsmmc" |
a45c6cb8 | 149 | |
e99448ff B |
150 | #define VDD_1V8 1800000 /* 180000 uV */ |
151 | #define VDD_3V0 3000000 /* 300000 uV */ | |
152 | #define VDD_165_195 (ffs(MMC_VDD_165_195) - 1) | |
153 | ||
a45c6cb8 MC |
154 | /* |
155 | * One controller can have multiple slots, like on some omap boards using | |
156 | * omap.c controller driver. Luckily this is not currently done on any known | |
157 | * omap_hsmmc.c device. | |
158 | */ | |
326119c9 | 159 | #define mmc_pdata(host) host->pdata |
a45c6cb8 MC |
160 | |
161 | /* | |
162 | * MMC Host controller read/write API's | |
163 | */ | |
164 | #define OMAP_HSMMC_READ(base, reg) \ | |
165 | __raw_readl((base) + OMAP_HSMMC_##reg) | |
166 | ||
167 | #define OMAP_HSMMC_WRITE(base, reg, val) \ | |
168 | __raw_writel((val), (base) + OMAP_HSMMC_##reg) | |
169 | ||
9782aff8 PF |
170 | struct omap_hsmmc_next { |
171 | unsigned int dma_len; | |
172 | s32 cookie; | |
173 | }; | |
174 | ||
70a3341a | 175 | struct omap_hsmmc_host { |
a45c6cb8 MC |
176 | struct device *dev; |
177 | struct mmc_host *mmc; | |
178 | struct mmc_request *mrq; | |
179 | struct mmc_command *cmd; | |
180 | struct mmc_data *data; | |
181 | struct clk *fclk; | |
a45c6cb8 | 182 | struct clk *dbclk; |
e99448ff | 183 | struct regulator *pbias; |
bb2726b5 | 184 | bool pbias_enabled; |
a45c6cb8 | 185 | void __iomem *base; |
3f77f702 | 186 | int vqmmc_enabled; |
a45c6cb8 | 187 | resource_size_t mapbase; |
4dffd7a2 | 188 | spinlock_t irq_lock; /* Prevent races with irq handler */ |
a45c6cb8 | 189 | unsigned int dma_len; |
0ccd76d4 | 190 | unsigned int dma_sg_idx; |
a45c6cb8 | 191 | unsigned char bus_mode; |
a3621465 | 192 | unsigned char power_mode; |
a45c6cb8 | 193 | int suspended; |
0a82e06e TL |
194 | u32 con; |
195 | u32 hctl; | |
196 | u32 sysctl; | |
197 | u32 capa; | |
a45c6cb8 | 198 | int irq; |
2cd3a2a5 | 199 | int wake_irq; |
a45c6cb8 | 200 | int use_dma, dma_ch; |
c5c98927 RK |
201 | struct dma_chan *tx_chan; |
202 | struct dma_chan *rx_chan; | |
4a694dc9 | 203 | int response_busy; |
11dd62a7 | 204 | int context_loss; |
b62f6228 AH |
205 | int protect_card; |
206 | int reqs_blocked; | |
b417577d | 207 | int req_in_progress; |
6e3076c2 | 208 | unsigned long clk_rate; |
a2e77152 | 209 | unsigned int flags; |
2cd3a2a5 AF |
210 | #define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */ |
211 | #define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */ | |
9782aff8 | 212 | struct omap_hsmmc_next next_data; |
55143438 | 213 | struct omap_hsmmc_platform_data *pdata; |
b5cd43f0 | 214 | |
b5cd43f0 AF |
215 | /* return MMC cover switch state, can be NULL if not supported. |
216 | * | |
217 | * possible return values: | |
218 | * 0 - closed | |
219 | * 1 - open | |
220 | */ | |
80412ca8 | 221 | int (*get_cover_state)(struct device *dev); |
b5cd43f0 | 222 | |
80412ca8 | 223 | int (*card_detect)(struct device *dev); |
a45c6cb8 MC |
224 | }; |
225 | ||
59445b10 NM |
226 | struct omap_mmc_of_data { |
227 | u32 reg_offset; | |
228 | u8 controller_flags; | |
229 | }; | |
230 | ||
bf129e1c B |
231 | static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host); |
232 | ||
80412ca8 | 233 | static int omap_hsmmc_card_detect(struct device *dev) |
db0fefc5 | 234 | { |
9ea28ecb | 235 | struct omap_hsmmc_host *host = dev_get_drvdata(dev); |
db0fefc5 | 236 | |
41afa314 | 237 | return mmc_gpio_get_cd(host->mmc); |
db0fefc5 AH |
238 | } |
239 | ||
80412ca8 | 240 | static int omap_hsmmc_get_cover_state(struct device *dev) |
db0fefc5 | 241 | { |
9ea28ecb | 242 | struct omap_hsmmc_host *host = dev_get_drvdata(dev); |
db0fefc5 | 243 | |
41afa314 | 244 | return mmc_gpio_get_cd(host->mmc); |
db0fefc5 AH |
245 | } |
246 | ||
1d17f30b | 247 | static int omap_hsmmc_enable_supply(struct mmc_host *mmc) |
2a17f844 KVA |
248 | { |
249 | int ret; | |
3f77f702 | 250 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
1d17f30b | 251 | struct mmc_ios *ios = &mmc->ios; |
2a17f844 KVA |
252 | |
253 | if (mmc->supply.vmmc) { | |
1d17f30b | 254 | ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); |
2a17f844 KVA |
255 | if (ret) |
256 | return ret; | |
257 | } | |
258 | ||
259 | /* Enable interface voltage rail, if needed */ | |
3f77f702 | 260 | if (mmc->supply.vqmmc && !host->vqmmc_enabled) { |
2a17f844 KVA |
261 | ret = regulator_enable(mmc->supply.vqmmc); |
262 | if (ret) { | |
263 | dev_err(mmc_dev(mmc), "vmmc_aux reg enable failed\n"); | |
264 | goto err_vqmmc; | |
265 | } | |
3f77f702 | 266 | host->vqmmc_enabled = 1; |
2a17f844 KVA |
267 | } |
268 | ||
269 | return 0; | |
270 | ||
271 | err_vqmmc: | |
272 | if (mmc->supply.vmmc) | |
273 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); | |
274 | ||
275 | return ret; | |
276 | } | |
277 | ||
278 | static int omap_hsmmc_disable_supply(struct mmc_host *mmc) | |
279 | { | |
280 | int ret; | |
281 | int status; | |
3f77f702 | 282 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
2a17f844 | 283 | |
3f77f702 | 284 | if (mmc->supply.vqmmc && host->vqmmc_enabled) { |
2a17f844 KVA |
285 | ret = regulator_disable(mmc->supply.vqmmc); |
286 | if (ret) { | |
287 | dev_err(mmc_dev(mmc), "vmmc_aux reg disable failed\n"); | |
288 | return ret; | |
289 | } | |
3f77f702 | 290 | host->vqmmc_enabled = 0; |
2a17f844 KVA |
291 | } |
292 | ||
293 | if (mmc->supply.vmmc) { | |
294 | ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); | |
295 | if (ret) | |
296 | goto err_set_ocr; | |
297 | } | |
298 | ||
299 | return 0; | |
300 | ||
301 | err_set_ocr: | |
302 | if (mmc->supply.vqmmc) { | |
303 | status = regulator_enable(mmc->supply.vqmmc); | |
304 | if (status) | |
305 | dev_err(mmc_dev(mmc), "vmmc_aux re-enable failed\n"); | |
306 | } | |
307 | ||
308 | return ret; | |
309 | } | |
310 | ||
ec85c95e KVA |
311 | static int omap_hsmmc_set_pbias(struct omap_hsmmc_host *host, bool power_on, |
312 | int vdd) | |
313 | { | |
314 | int ret; | |
315 | ||
316 | if (!host->pbias) | |
317 | return 0; | |
318 | ||
319 | if (power_on) { | |
320 | if (vdd <= VDD_165_195) | |
321 | ret = regulator_set_voltage(host->pbias, VDD_1V8, | |
322 | VDD_1V8); | |
323 | else | |
324 | ret = regulator_set_voltage(host->pbias, VDD_3V0, | |
325 | VDD_3V0); | |
326 | if (ret < 0) { | |
327 | dev_err(host->dev, "pbias set voltage fail\n"); | |
328 | return ret; | |
329 | } | |
330 | ||
bb2726b5 | 331 | if (host->pbias_enabled == 0) { |
ec85c95e KVA |
332 | ret = regulator_enable(host->pbias); |
333 | if (ret) { | |
334 | dev_err(host->dev, "pbias reg enable fail\n"); | |
335 | return ret; | |
336 | } | |
bb2726b5 | 337 | host->pbias_enabled = 1; |
ec85c95e KVA |
338 | } |
339 | } else { | |
bb2726b5 | 340 | if (host->pbias_enabled == 1) { |
ec85c95e KVA |
341 | ret = regulator_disable(host->pbias); |
342 | if (ret) { | |
343 | dev_err(host->dev, "pbias reg disable fail\n"); | |
344 | return ret; | |
345 | } | |
bb2726b5 | 346 | host->pbias_enabled = 0; |
ec85c95e KVA |
347 | } |
348 | } | |
349 | ||
350 | return 0; | |
351 | } | |
352 | ||
1ca4d359 AF |
353 | static int omap_hsmmc_set_power(struct omap_hsmmc_host *host, int power_on, |
354 | int vdd) | |
db0fefc5 | 355 | { |
aa9a6801 | 356 | struct mmc_host *mmc = host->mmc; |
db0fefc5 AH |
357 | int ret = 0; |
358 | ||
f7f0f035 | 359 | if (mmc_pdata(host)->set_power) |
1ca4d359 | 360 | return mmc_pdata(host)->set_power(host->dev, power_on, vdd); |
f7f0f035 | 361 | |
db0fefc5 AH |
362 | /* |
363 | * If we don't see a Vcc regulator, assume it's a fixed | |
364 | * voltage always-on regulator. | |
365 | */ | |
aa9a6801 | 366 | if (!mmc->supply.vmmc) |
db0fefc5 AH |
367 | return 0; |
368 | ||
326119c9 | 369 | if (mmc_pdata(host)->before_set_reg) |
1ca4d359 | 370 | mmc_pdata(host)->before_set_reg(host->dev, power_on, vdd); |
db0fefc5 | 371 | |
ec85c95e KVA |
372 | ret = omap_hsmmc_set_pbias(host, false, 0); |
373 | if (ret) | |
374 | return ret; | |
e99448ff | 375 | |
db0fefc5 AH |
376 | /* |
377 | * Assume Vcc regulator is used only to power the card ... OMAP | |
378 | * VDDS is used to power the pins, optionally with a transceiver to | |
379 | * support cards using voltages other than VDDS (1.8V nominal). When a | |
380 | * transceiver is used, DAT3..7 are muxed as transceiver control pins. | |
381 | * | |
382 | * In some cases this regulator won't support enable/disable; | |
383 | * e.g. it's a fixed rail for a WLAN chip. | |
384 | * | |
385 | * In other cases vcc_aux switches interface power. Example, for | |
386 | * eMMC cards it represents VccQ. Sometimes transceivers or SDIO | |
387 | * chips/cards need an interface voltage rail too. | |
388 | */ | |
389 | if (power_on) { | |
1d17f30b | 390 | ret = omap_hsmmc_enable_supply(mmc); |
2a17f844 KVA |
391 | if (ret) |
392 | return ret; | |
97fe7e5a KVA |
393 | |
394 | ret = omap_hsmmc_set_pbias(host, true, vdd); | |
395 | if (ret) | |
396 | goto err_set_voltage; | |
db0fefc5 | 397 | } else { |
2a17f844 KVA |
398 | ret = omap_hsmmc_disable_supply(mmc); |
399 | if (ret) | |
400 | return ret; | |
db0fefc5 AH |
401 | } |
402 | ||
326119c9 | 403 | if (mmc_pdata(host)->after_set_reg) |
1ca4d359 | 404 | mmc_pdata(host)->after_set_reg(host->dev, power_on, vdd); |
db0fefc5 | 405 | |
229f3292 KVA |
406 | return 0; |
407 | ||
408 | err_set_voltage: | |
2a17f844 | 409 | omap_hsmmc_disable_supply(mmc); |
229f3292 | 410 | |
db0fefc5 AH |
411 | return ret; |
412 | } | |
413 | ||
c8518efa KVA |
414 | static int omap_hsmmc_disable_boot_regulator(struct regulator *reg) |
415 | { | |
416 | int ret; | |
417 | ||
418 | if (!reg) | |
419 | return 0; | |
420 | ||
421 | if (regulator_is_enabled(reg)) { | |
422 | ret = regulator_enable(reg); | |
423 | if (ret) | |
424 | return ret; | |
425 | ||
426 | ret = regulator_disable(reg); | |
427 | if (ret) | |
428 | return ret; | |
429 | } | |
430 | ||
431 | return 0; | |
432 | } | |
433 | ||
434 | static int omap_hsmmc_disable_boot_regulators(struct omap_hsmmc_host *host) | |
435 | { | |
436 | struct mmc_host *mmc = host->mmc; | |
437 | int ret; | |
438 | ||
439 | /* | |
440 | * disable regulators enabled during boot and get the usecount | |
441 | * right so that regulators can be enabled/disabled by checking | |
442 | * the return value of regulator_is_enabled | |
443 | */ | |
444 | ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vmmc); | |
445 | if (ret) { | |
446 | dev_err(host->dev, "fail to disable boot enabled vmmc reg\n"); | |
447 | return ret; | |
448 | } | |
449 | ||
450 | ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vqmmc); | |
451 | if (ret) { | |
452 | dev_err(host->dev, | |
453 | "fail to disable boot enabled vmmc_aux reg\n"); | |
454 | return ret; | |
455 | } | |
456 | ||
457 | ret = omap_hsmmc_disable_boot_regulator(host->pbias); | |
458 | if (ret) { | |
459 | dev_err(host->dev, | |
460 | "failed to disable boot enabled pbias reg\n"); | |
461 | return ret; | |
462 | } | |
463 | ||
464 | return 0; | |
465 | } | |
466 | ||
db0fefc5 AH |
467 | static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) |
468 | { | |
64be9782 | 469 | int ocr_value = 0; |
7d607f91 | 470 | int ret; |
aa9a6801 | 471 | struct mmc_host *mmc = host->mmc; |
db0fefc5 | 472 | |
f7f0f035 AF |
473 | if (mmc_pdata(host)->set_power) |
474 | return 0; | |
475 | ||
aa9a6801 KVA |
476 | mmc->supply.vmmc = devm_regulator_get_optional(host->dev, "vmmc"); |
477 | if (IS_ERR(mmc->supply.vmmc)) { | |
478 | ret = PTR_ERR(mmc->supply.vmmc); | |
123e20b1 | 479 | if ((ret != -ENODEV) && host->dev->of_node) |
7d607f91 | 480 | return ret; |
7d607f91 | 481 | dev_dbg(host->dev, "unable to get vmmc regulator %ld\n", |
aa9a6801 KVA |
482 | PTR_ERR(mmc->supply.vmmc)); |
483 | mmc->supply.vmmc = NULL; | |
db0fefc5 | 484 | } else { |
aa9a6801 | 485 | ocr_value = mmc_regulator_get_ocrmask(mmc->supply.vmmc); |
b49069fc | 486 | if (ocr_value > 0) |
326119c9 | 487 | mmc_pdata(host)->ocr_mask = ocr_value; |
987fd49b | 488 | } |
db0fefc5 | 489 | |
987fd49b | 490 | /* Allow an aux regulator */ |
aa9a6801 KVA |
491 | mmc->supply.vqmmc = devm_regulator_get_optional(host->dev, "vmmc_aux"); |
492 | if (IS_ERR(mmc->supply.vqmmc)) { | |
493 | ret = PTR_ERR(mmc->supply.vqmmc); | |
123e20b1 | 494 | if ((ret != -ENODEV) && host->dev->of_node) |
6a9b2ff0 | 495 | return ret; |
6a9b2ff0 | 496 | dev_dbg(host->dev, "unable to get vmmc_aux regulator %ld\n", |
aa9a6801 KVA |
497 | PTR_ERR(mmc->supply.vqmmc)); |
498 | mmc->supply.vqmmc = NULL; | |
6a9b2ff0 | 499 | } |
987fd49b | 500 | |
c299dc39 KVA |
501 | host->pbias = devm_regulator_get_optional(host->dev, "pbias"); |
502 | if (IS_ERR(host->pbias)) { | |
503 | ret = PTR_ERR(host->pbias); | |
9143757b KVA |
504 | if ((ret != -ENODEV) && host->dev->of_node) { |
505 | dev_err(host->dev, | |
506 | "SD card detect fail? enable CONFIG_REGULATOR_PBIAS\n"); | |
6a9b2ff0 | 507 | return ret; |
9143757b | 508 | } |
6a9b2ff0 | 509 | dev_dbg(host->dev, "unable to get pbias regulator %ld\n", |
c299dc39 KVA |
510 | PTR_ERR(host->pbias)); |
511 | host->pbias = NULL; | |
6a9b2ff0 | 512 | } |
e99448ff | 513 | |
987fd49b | 514 | /* For eMMC do not power off when not in sleep state */ |
326119c9 | 515 | if (mmc_pdata(host)->no_regulator_off_init) |
987fd49b | 516 | return 0; |
987fd49b | 517 | |
c8518efa KVA |
518 | ret = omap_hsmmc_disable_boot_regulators(host); |
519 | if (ret) | |
520 | return ret; | |
db0fefc5 AH |
521 | |
522 | return 0; | |
db0fefc5 AH |
523 | } |
524 | ||
cde592cb | 525 | static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id); |
41afa314 N |
526 | |
527 | static int omap_hsmmc_gpio_init(struct mmc_host *mmc, | |
528 | struct omap_hsmmc_host *host, | |
1e363e3b | 529 | struct omap_hsmmc_platform_data *pdata) |
b702b106 AH |
530 | { |
531 | int ret; | |
532 | ||
b7a5646f AF |
533 | if (gpio_is_valid(pdata->gpio_cod)) { |
534 | ret = mmc_gpio_request_cd(mmc, pdata->gpio_cod, 0); | |
b702b106 AH |
535 | if (ret) |
536 | return ret; | |
cde592cb AF |
537 | |
538 | host->get_cover_state = omap_hsmmc_get_cover_state; | |
539 | mmc_gpio_set_cd_isr(mmc, omap_hsmmc_cover_irq); | |
b7a5646f AF |
540 | } else if (gpio_is_valid(pdata->gpio_cd)) { |
541 | ret = mmc_gpio_request_cd(mmc, pdata->gpio_cd, 0); | |
cde592cb AF |
542 | if (ret) |
543 | return ret; | |
544 | ||
545 | host->card_detect = omap_hsmmc_card_detect; | |
326119c9 | 546 | } |
b702b106 | 547 | |
326119c9 | 548 | if (gpio_is_valid(pdata->gpio_wp)) { |
41afa314 | 549 | ret = mmc_gpio_request_ro(mmc, pdata->gpio_wp); |
b702b106 | 550 | if (ret) |
41afa314 | 551 | return ret; |
326119c9 | 552 | } |
b702b106 AH |
553 | |
554 | return 0; | |
b702b106 AH |
555 | } |
556 | ||
e0c7f99b AS |
557 | /* |
558 | * Start clock to the card | |
559 | */ | |
560 | static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) | |
561 | { | |
562 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
563 | OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); | |
564 | } | |
565 | ||
a45c6cb8 MC |
566 | /* |
567 | * Stop clock to the card | |
568 | */ | |
70a3341a | 569 | static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) |
a45c6cb8 MC |
570 | { |
571 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
572 | OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); | |
573 | if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) | |
7122bbb0 | 574 | dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n"); |
a45c6cb8 MC |
575 | } |
576 | ||
93caf8e6 AH |
577 | static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, |
578 | struct mmc_command *cmd) | |
b417577d | 579 | { |
2cd3a2a5 AF |
580 | u32 irq_mask = INT_EN_MASK; |
581 | unsigned long flags; | |
b417577d AH |
582 | |
583 | if (host->use_dma) | |
2cd3a2a5 | 584 | irq_mask &= ~(BRR_EN | BWR_EN); |
b417577d | 585 | |
93caf8e6 AH |
586 | /* Disable timeout for erases */ |
587 | if (cmd->opcode == MMC_ERASE) | |
a7e96879 | 588 | irq_mask &= ~DTO_EN; |
93caf8e6 | 589 | |
2cd3a2a5 | 590 | spin_lock_irqsave(&host->irq_lock, flags); |
b417577d AH |
591 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); |
592 | OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); | |
2cd3a2a5 AF |
593 | |
594 | /* latch pending CIRQ, but don't signal MMC core */ | |
595 | if (host->flags & HSMMC_SDIO_IRQ_ENABLED) | |
596 | irq_mask |= CIRQ_EN; | |
b417577d | 597 | OMAP_HSMMC_WRITE(host->base, IE, irq_mask); |
2cd3a2a5 | 598 | spin_unlock_irqrestore(&host->irq_lock, flags); |
b417577d AH |
599 | } |
600 | ||
601 | static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) | |
602 | { | |
2cd3a2a5 AF |
603 | u32 irq_mask = 0; |
604 | unsigned long flags; | |
605 | ||
606 | spin_lock_irqsave(&host->irq_lock, flags); | |
607 | /* no transfer running but need to keep cirq if enabled */ | |
608 | if (host->flags & HSMMC_SDIO_IRQ_ENABLED) | |
609 | irq_mask |= CIRQ_EN; | |
610 | OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); | |
611 | OMAP_HSMMC_WRITE(host->base, IE, irq_mask); | |
b417577d | 612 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); |
2cd3a2a5 | 613 | spin_unlock_irqrestore(&host->irq_lock, flags); |
b417577d AH |
614 | } |
615 | ||
ac330f44 | 616 | /* Calculate divisor for the given clock frequency */ |
d83b6e03 | 617 | static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) |
ac330f44 AS |
618 | { |
619 | u16 dsor = 0; | |
620 | ||
621 | if (ios->clock) { | |
d83b6e03 | 622 | dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); |
ed164182 B |
623 | if (dsor > CLKD_MAX) |
624 | dsor = CLKD_MAX; | |
ac330f44 AS |
625 | } |
626 | ||
627 | return dsor; | |
628 | } | |
629 | ||
5934df2f AS |
630 | static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) |
631 | { | |
632 | struct mmc_ios *ios = &host->mmc->ios; | |
633 | unsigned long regval; | |
634 | unsigned long timeout; | |
cd587096 | 635 | unsigned long clkdiv; |
5934df2f | 636 | |
8986d31b | 637 | dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); |
5934df2f AS |
638 | |
639 | omap_hsmmc_stop_clock(host); | |
640 | ||
641 | regval = OMAP_HSMMC_READ(host->base, SYSCTL); | |
642 | regval = regval & ~(CLKD_MASK | DTO_MASK); | |
cd587096 HG |
643 | clkdiv = calc_divisor(host, ios); |
644 | regval = regval | (clkdiv << 6) | (DTO << 16); | |
5934df2f AS |
645 | OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); |
646 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
647 | OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); | |
648 | ||
649 | /* Wait till the ICS bit is set */ | |
650 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
651 | while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS | |
652 | && time_before(jiffies, timeout)) | |
653 | cpu_relax(); | |
654 | ||
cd587096 HG |
655 | /* |
656 | * Enable High-Speed Support | |
657 | * Pre-Requisites | |
658 | * - Controller should support High-Speed-Enable Bit | |
659 | * - Controller should not be using DDR Mode | |
660 | * - Controller should advertise that it supports High Speed | |
661 | * in capabilities register | |
662 | * - MMC/SD clock coming out of controller > 25MHz | |
663 | */ | |
326119c9 | 664 | if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) && |
5438ad95 | 665 | (ios->timing != MMC_TIMING_MMC_DDR52) && |
903101a8 | 666 | (ios->timing != MMC_TIMING_UHS_DDR50) && |
cd587096 HG |
667 | ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { |
668 | regval = OMAP_HSMMC_READ(host->base, HCTL); | |
669 | if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) | |
670 | regval |= HSPE; | |
671 | else | |
672 | regval &= ~HSPE; | |
673 | ||
674 | OMAP_HSMMC_WRITE(host->base, HCTL, regval); | |
675 | } | |
676 | ||
5934df2f AS |
677 | omap_hsmmc_start_clock(host); |
678 | } | |
679 | ||
3796fb8a AS |
680 | static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) |
681 | { | |
682 | struct mmc_ios *ios = &host->mmc->ios; | |
683 | u32 con; | |
684 | ||
685 | con = OMAP_HSMMC_READ(host->base, CON); | |
903101a8 UH |
686 | if (ios->timing == MMC_TIMING_MMC_DDR52 || |
687 | ios->timing == MMC_TIMING_UHS_DDR50) | |
03b5d924 B |
688 | con |= DDR; /* configure in DDR mode */ |
689 | else | |
690 | con &= ~DDR; | |
3796fb8a AS |
691 | switch (ios->bus_width) { |
692 | case MMC_BUS_WIDTH_8: | |
693 | OMAP_HSMMC_WRITE(host->base, CON, con | DW8); | |
694 | break; | |
695 | case MMC_BUS_WIDTH_4: | |
696 | OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); | |
697 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
698 | OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); | |
699 | break; | |
700 | case MMC_BUS_WIDTH_1: | |
701 | OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); | |
702 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
703 | OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); | |
704 | break; | |
705 | } | |
706 | } | |
707 | ||
708 | static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) | |
709 | { | |
710 | struct mmc_ios *ios = &host->mmc->ios; | |
711 | u32 con; | |
712 | ||
713 | con = OMAP_HSMMC_READ(host->base, CON); | |
714 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) | |
715 | OMAP_HSMMC_WRITE(host->base, CON, con | OD); | |
716 | else | |
717 | OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); | |
718 | } | |
719 | ||
11dd62a7 DK |
720 | #ifdef CONFIG_PM |
721 | ||
722 | /* | |
723 | * Restore the MMC host context, if it was lost as result of a | |
724 | * power state change. | |
725 | */ | |
70a3341a | 726 | static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) |
11dd62a7 DK |
727 | { |
728 | struct mmc_ios *ios = &host->mmc->ios; | |
3796fb8a | 729 | u32 hctl, capa; |
11dd62a7 DK |
730 | unsigned long timeout; |
731 | ||
0a82e06e TL |
732 | if (host->con == OMAP_HSMMC_READ(host->base, CON) && |
733 | host->hctl == OMAP_HSMMC_READ(host->base, HCTL) && | |
734 | host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) && | |
735 | host->capa == OMAP_HSMMC_READ(host->base, CAPA)) | |
736 | return 0; | |
737 | ||
738 | host->context_loss++; | |
739 | ||
c2200efb | 740 | if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { |
11dd62a7 DK |
741 | if (host->power_mode != MMC_POWER_OFF && |
742 | (1 << ios->vdd) <= MMC_VDD_23_24) | |
743 | hctl = SDVS18; | |
744 | else | |
745 | hctl = SDVS30; | |
746 | capa = VS30 | VS18; | |
747 | } else { | |
748 | hctl = SDVS18; | |
749 | capa = VS18; | |
750 | } | |
751 | ||
5a52b08b B |
752 | if (host->mmc->caps & MMC_CAP_SDIO_IRQ) |
753 | hctl |= IWE; | |
754 | ||
11dd62a7 DK |
755 | OMAP_HSMMC_WRITE(host->base, HCTL, |
756 | OMAP_HSMMC_READ(host->base, HCTL) | hctl); | |
757 | ||
758 | OMAP_HSMMC_WRITE(host->base, CAPA, | |
759 | OMAP_HSMMC_READ(host->base, CAPA) | capa); | |
760 | ||
761 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
762 | OMAP_HSMMC_READ(host->base, HCTL) | SDBP); | |
763 | ||
764 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
765 | while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP | |
766 | && time_before(jiffies, timeout)) | |
767 | ; | |
768 | ||
2cd3a2a5 AF |
769 | OMAP_HSMMC_WRITE(host->base, ISE, 0); |
770 | OMAP_HSMMC_WRITE(host->base, IE, 0); | |
771 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); | |
11dd62a7 DK |
772 | |
773 | /* Do not initialize card-specific things if the power is off */ | |
774 | if (host->power_mode == MMC_POWER_OFF) | |
775 | goto out; | |
776 | ||
3796fb8a | 777 | omap_hsmmc_set_bus_width(host); |
11dd62a7 | 778 | |
5934df2f | 779 | omap_hsmmc_set_clock(host); |
11dd62a7 | 780 | |
3796fb8a AS |
781 | omap_hsmmc_set_bus_mode(host); |
782 | ||
11dd62a7 | 783 | out: |
0a82e06e TL |
784 | dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n", |
785 | host->context_loss); | |
11dd62a7 DK |
786 | return 0; |
787 | } | |
788 | ||
789 | /* | |
790 | * Save the MMC host context (store the number of power state changes so far). | |
791 | */ | |
70a3341a | 792 | static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) |
11dd62a7 | 793 | { |
0a82e06e TL |
794 | host->con = OMAP_HSMMC_READ(host->base, CON); |
795 | host->hctl = OMAP_HSMMC_READ(host->base, HCTL); | |
796 | host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL); | |
797 | host->capa = OMAP_HSMMC_READ(host->base, CAPA); | |
11dd62a7 DK |
798 | } |
799 | ||
800 | #else | |
801 | ||
70a3341a | 802 | static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) |
11dd62a7 DK |
803 | { |
804 | return 0; | |
805 | } | |
806 | ||
70a3341a | 807 | static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) |
11dd62a7 DK |
808 | { |
809 | } | |
810 | ||
811 | #endif | |
812 | ||
a45c6cb8 MC |
813 | /* |
814 | * Send init stream sequence to card | |
815 | * before sending IDLE command | |
816 | */ | |
70a3341a | 817 | static void send_init_stream(struct omap_hsmmc_host *host) |
a45c6cb8 MC |
818 | { |
819 | int reg = 0; | |
820 | unsigned long timeout; | |
821 | ||
b62f6228 AH |
822 | if (host->protect_card) |
823 | return; | |
824 | ||
a45c6cb8 | 825 | disable_irq(host->irq); |
b417577d AH |
826 | |
827 | OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); | |
a45c6cb8 MC |
828 | OMAP_HSMMC_WRITE(host->base, CON, |
829 | OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); | |
830 | OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); | |
831 | ||
832 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
a7e96879 V |
833 | while ((reg != CC_EN) && time_before(jiffies, timeout)) |
834 | reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN; | |
a45c6cb8 MC |
835 | |
836 | OMAP_HSMMC_WRITE(host->base, CON, | |
837 | OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); | |
c653a6d4 AH |
838 | |
839 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); | |
840 | OMAP_HSMMC_READ(host->base, STAT); | |
841 | ||
a45c6cb8 MC |
842 | enable_irq(host->irq); |
843 | } | |
844 | ||
845 | static inline | |
70a3341a | 846 | int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) |
a45c6cb8 MC |
847 | { |
848 | int r = 1; | |
849 | ||
b5cd43f0 | 850 | if (host->get_cover_state) |
80412ca8 | 851 | r = host->get_cover_state(host->dev); |
a45c6cb8 MC |
852 | return r; |
853 | } | |
854 | ||
855 | static ssize_t | |
70a3341a | 856 | omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, |
a45c6cb8 MC |
857 | char *buf) |
858 | { | |
859 | struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); | |
70a3341a | 860 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a45c6cb8 | 861 | |
70a3341a DK |
862 | return sprintf(buf, "%s\n", |
863 | omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); | |
a45c6cb8 MC |
864 | } |
865 | ||
70a3341a | 866 | static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); |
a45c6cb8 MC |
867 | |
868 | static ssize_t | |
70a3341a | 869 | omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, |
a45c6cb8 MC |
870 | char *buf) |
871 | { | |
872 | struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); | |
70a3341a | 873 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a45c6cb8 | 874 | |
326119c9 | 875 | return sprintf(buf, "%s\n", mmc_pdata(host)->name); |
a45c6cb8 MC |
876 | } |
877 | ||
70a3341a | 878 | static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); |
a45c6cb8 MC |
879 | |
880 | /* | |
881 | * Configure the response type and send the cmd. | |
882 | */ | |
883 | static void | |
70a3341a | 884 | omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, |
a45c6cb8 MC |
885 | struct mmc_data *data) |
886 | { | |
887 | int cmdreg = 0, resptype = 0, cmdtype = 0; | |
888 | ||
8986d31b | 889 | dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", |
a45c6cb8 MC |
890 | mmc_hostname(host->mmc), cmd->opcode, cmd->arg); |
891 | host->cmd = cmd; | |
892 | ||
93caf8e6 | 893 | omap_hsmmc_enable_irq(host, cmd); |
a45c6cb8 | 894 | |
4a694dc9 | 895 | host->response_busy = 0; |
a45c6cb8 MC |
896 | if (cmd->flags & MMC_RSP_PRESENT) { |
897 | if (cmd->flags & MMC_RSP_136) | |
898 | resptype = 1; | |
4a694dc9 AH |
899 | else if (cmd->flags & MMC_RSP_BUSY) { |
900 | resptype = 3; | |
901 | host->response_busy = 1; | |
902 | } else | |
a45c6cb8 MC |
903 | resptype = 2; |
904 | } | |
905 | ||
906 | /* | |
907 | * Unlike OMAP1 controller, the cmdtype does not seem to be based on | |
908 | * ac, bc, adtc, bcr. Only commands ending an open ended transfer need | |
909 | * a val of 0x3, rest 0x0. | |
910 | */ | |
911 | if (cmd == host->mrq->stop) | |
912 | cmdtype = 0x3; | |
913 | ||
914 | cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); | |
915 | ||
a2e77152 B |
916 | if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) && |
917 | host->mrq->sbc) { | |
918 | cmdreg |= ACEN_ACMD23; | |
919 | OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg); | |
920 | } | |
a45c6cb8 MC |
921 | if (data) { |
922 | cmdreg |= DP_SELECT | MSBS | BCE; | |
923 | if (data->flags & MMC_DATA_READ) | |
924 | cmdreg |= DDIR; | |
925 | else | |
926 | cmdreg &= ~(DDIR); | |
927 | } | |
928 | ||
929 | if (host->use_dma) | |
a7e96879 | 930 | cmdreg |= DMAE; |
a45c6cb8 | 931 | |
b417577d | 932 | host->req_in_progress = 1; |
4dffd7a2 | 933 | |
a45c6cb8 MC |
934 | OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); |
935 | OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); | |
936 | } | |
937 | ||
c5c98927 RK |
938 | static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host, |
939 | struct mmc_data *data) | |
940 | { | |
941 | return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; | |
942 | } | |
943 | ||
b417577d AH |
944 | static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) |
945 | { | |
946 | int dma_ch; | |
31463b14 | 947 | unsigned long flags; |
b417577d | 948 | |
31463b14 | 949 | spin_lock_irqsave(&host->irq_lock, flags); |
b417577d AH |
950 | host->req_in_progress = 0; |
951 | dma_ch = host->dma_ch; | |
31463b14 | 952 | spin_unlock_irqrestore(&host->irq_lock, flags); |
b417577d AH |
953 | |
954 | omap_hsmmc_disable_irq(host); | |
955 | /* Do not complete the request if DMA is still in progress */ | |
956 | if (mrq->data && host->use_dma && dma_ch != -1) | |
957 | return; | |
958 | host->mrq = NULL; | |
959 | mmc_request_done(host->mmc, mrq); | |
960 | } | |
961 | ||
a45c6cb8 MC |
962 | /* |
963 | * Notify the transfer complete to MMC core | |
964 | */ | |
965 | static void | |
70a3341a | 966 | omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) |
a45c6cb8 | 967 | { |
4a694dc9 AH |
968 | if (!data) { |
969 | struct mmc_request *mrq = host->mrq; | |
970 | ||
23050103 AH |
971 | /* TC before CC from CMD6 - don't know why, but it happens */ |
972 | if (host->cmd && host->cmd->opcode == 6 && | |
973 | host->response_busy) { | |
974 | host->response_busy = 0; | |
975 | return; | |
976 | } | |
977 | ||
b417577d | 978 | omap_hsmmc_request_done(host, mrq); |
4a694dc9 AH |
979 | return; |
980 | } | |
981 | ||
a45c6cb8 MC |
982 | host->data = NULL; |
983 | ||
a45c6cb8 MC |
984 | if (!data->error) |
985 | data->bytes_xfered += data->blocks * (data->blksz); | |
986 | else | |
987 | data->bytes_xfered = 0; | |
988 | ||
bf129e1c B |
989 | if (data->stop && (data->error || !host->mrq->sbc)) |
990 | omap_hsmmc_start_command(host, data->stop, NULL); | |
991 | else | |
b417577d | 992 | omap_hsmmc_request_done(host, data->mrq); |
a45c6cb8 MC |
993 | } |
994 | ||
995 | /* | |
996 | * Notify the core about command completion | |
997 | */ | |
998 | static void | |
70a3341a | 999 | omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) |
a45c6cb8 | 1000 | { |
bf129e1c | 1001 | if (host->mrq->sbc && (host->cmd == host->mrq->sbc) && |
a2e77152 | 1002 | !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) { |
2177fa94 | 1003 | host->cmd = NULL; |
bf129e1c B |
1004 | omap_hsmmc_start_dma_transfer(host); |
1005 | omap_hsmmc_start_command(host, host->mrq->cmd, | |
1006 | host->mrq->data); | |
1007 | return; | |
1008 | } | |
1009 | ||
2177fa94 B |
1010 | host->cmd = NULL; |
1011 | ||
a45c6cb8 MC |
1012 | if (cmd->flags & MMC_RSP_PRESENT) { |
1013 | if (cmd->flags & MMC_RSP_136) { | |
1014 | /* response type 2 */ | |
1015 | cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); | |
1016 | cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); | |
1017 | cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); | |
1018 | cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); | |
1019 | } else { | |
1020 | /* response types 1, 1b, 3, 4, 5, 6 */ | |
1021 | cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); | |
1022 | } | |
1023 | } | |
b417577d | 1024 | if ((host->data == NULL && !host->response_busy) || cmd->error) |
d4b2c375 | 1025 | omap_hsmmc_request_done(host, host->mrq); |
a45c6cb8 MC |
1026 | } |
1027 | ||
1028 | /* | |
1029 | * DMA clean up for command errors | |
1030 | */ | |
70a3341a | 1031 | static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) |
a45c6cb8 | 1032 | { |
b417577d | 1033 | int dma_ch; |
31463b14 | 1034 | unsigned long flags; |
b417577d | 1035 | |
82788ff5 | 1036 | host->data->error = errno; |
a45c6cb8 | 1037 | |
31463b14 | 1038 | spin_lock_irqsave(&host->irq_lock, flags); |
b417577d AH |
1039 | dma_ch = host->dma_ch; |
1040 | host->dma_ch = -1; | |
31463b14 | 1041 | spin_unlock_irqrestore(&host->irq_lock, flags); |
b417577d AH |
1042 | |
1043 | if (host->use_dma && dma_ch != -1) { | |
c5c98927 RK |
1044 | struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data); |
1045 | ||
1046 | dmaengine_terminate_all(chan); | |
1047 | dma_unmap_sg(chan->device->dev, | |
1048 | host->data->sg, host->data->sg_len, | |
feeef096 | 1049 | mmc_get_dma_dir(host->data)); |
c5c98927 | 1050 | |
053bf34f | 1051 | host->data->host_cookie = 0; |
a45c6cb8 MC |
1052 | } |
1053 | host->data = NULL; | |
a45c6cb8 MC |
1054 | } |
1055 | ||
1056 | /* | |
1057 | * Readable error output | |
1058 | */ | |
1059 | #ifdef CONFIG_MMC_DEBUG | |
699b958b | 1060 | static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) |
a45c6cb8 MC |
1061 | { |
1062 | /* --- means reserved bit without definition at documentation */ | |
70a3341a | 1063 | static const char *omap_hsmmc_status_bits[] = { |
699b958b AH |
1064 | "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , |
1065 | "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", | |
1066 | "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , | |
1067 | "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" | |
a45c6cb8 MC |
1068 | }; |
1069 | char res[256]; | |
1070 | char *buf = res; | |
1071 | int len, i; | |
1072 | ||
1073 | len = sprintf(buf, "MMC IRQ 0x%x :", status); | |
1074 | buf += len; | |
1075 | ||
70a3341a | 1076 | for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) |
a45c6cb8 | 1077 | if (status & (1 << i)) { |
70a3341a | 1078 | len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); |
a45c6cb8 MC |
1079 | buf += len; |
1080 | } | |
1081 | ||
8986d31b | 1082 | dev_vdbg(mmc_dev(host->mmc), "%s\n", res); |
a45c6cb8 | 1083 | } |
699b958b AH |
1084 | #else |
1085 | static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, | |
1086 | u32 status) | |
1087 | { | |
1088 | } | |
a45c6cb8 MC |
1089 | #endif /* CONFIG_MMC_DEBUG */ |
1090 | ||
3ebf74b1 JP |
1091 | /* |
1092 | * MMC controller internal state machines reset | |
1093 | * | |
1094 | * Used to reset command or data internal state machines, using respectively | |
1095 | * SRC or SRD bit of SYSCTL register | |
1096 | * Can be called from interrupt context | |
1097 | */ | |
70a3341a DK |
1098 | static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, |
1099 | unsigned long bit) | |
3ebf74b1 JP |
1100 | { |
1101 | unsigned long i = 0; | |
1e881786 | 1102 | unsigned long limit = MMC_TIMEOUT_US; |
3ebf74b1 JP |
1103 | |
1104 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
1105 | OMAP_HSMMC_READ(host->base, SYSCTL) | bit); | |
1106 | ||
07ad64b6 MC |
1107 | /* |
1108 | * OMAP4 ES2 and greater has an updated reset logic. | |
1109 | * Monitor a 0->1 transition first | |
1110 | */ | |
326119c9 | 1111 | if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) { |
b432b4b3 | 1112 | while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) |
07ad64b6 | 1113 | && (i++ < limit)) |
1e881786 | 1114 | udelay(1); |
07ad64b6 MC |
1115 | } |
1116 | i = 0; | |
1117 | ||
3ebf74b1 JP |
1118 | while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && |
1119 | (i++ < limit)) | |
1e881786 | 1120 | udelay(1); |
3ebf74b1 JP |
1121 | |
1122 | if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) | |
1123 | dev_err(mmc_dev(host->mmc), | |
1124 | "Timeout waiting on controller reset in %s\n", | |
1125 | __func__); | |
1126 | } | |
a45c6cb8 | 1127 | |
25e1897b B |
1128 | static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, |
1129 | int err, int end_cmd) | |
ae4bf788 | 1130 | { |
25e1897b | 1131 | if (end_cmd) { |
94d4f272 | 1132 | omap_hsmmc_reset_controller_fsm(host, SRC); |
25e1897b B |
1133 | if (host->cmd) |
1134 | host->cmd->error = err; | |
1135 | } | |
ae4bf788 V |
1136 | |
1137 | if (host->data) { | |
1138 | omap_hsmmc_reset_controller_fsm(host, SRD); | |
1139 | omap_hsmmc_dma_cleanup(host, err); | |
dc7745bd B |
1140 | } else if (host->mrq && host->mrq->cmd) |
1141 | host->mrq->cmd->error = err; | |
ae4bf788 V |
1142 | } |
1143 | ||
b417577d | 1144 | static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) |
a45c6cb8 | 1145 | { |
a45c6cb8 | 1146 | struct mmc_data *data; |
b417577d | 1147 | int end_cmd = 0, end_trans = 0; |
a2e77152 | 1148 | int error = 0; |
b417577d | 1149 | |
a45c6cb8 | 1150 | data = host->data; |
8986d31b | 1151 | dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); |
a45c6cb8 | 1152 | |
a7e96879 | 1153 | if (status & ERR_EN) { |
699b958b | 1154 | omap_hsmmc_dbg_report_irq(host, status); |
25e1897b | 1155 | |
24380dd4 | 1156 | if (status & (CTO_EN | CCRC_EN | CEB_EN)) |
25e1897b | 1157 | end_cmd = 1; |
408806f7 KVA |
1158 | if (host->data || host->response_busy) { |
1159 | end_trans = !end_cmd; | |
1160 | host->response_busy = 0; | |
1161 | } | |
a7e96879 | 1162 | if (status & (CTO_EN | DTO_EN)) |
25e1897b | 1163 | hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd); |
5027cd1e V |
1164 | else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN | |
1165 | BADA_EN)) | |
25e1897b | 1166 | hsmmc_command_incomplete(host, -EILSEQ, end_cmd); |
ae4bf788 | 1167 | |
a2e77152 B |
1168 | if (status & ACE_EN) { |
1169 | u32 ac12; | |
1170 | ac12 = OMAP_HSMMC_READ(host->base, AC12); | |
1171 | if (!(ac12 & ACNE) && host->mrq->sbc) { | |
1172 | end_cmd = 1; | |
1173 | if (ac12 & ACTO) | |
1174 | error = -ETIMEDOUT; | |
1175 | else if (ac12 & (ACCE | ACEB | ACIE)) | |
1176 | error = -EILSEQ; | |
1177 | host->mrq->sbc->error = error; | |
1178 | hsmmc_command_incomplete(host, error, end_cmd); | |
1179 | } | |
1180 | dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12); | |
1181 | } | |
a45c6cb8 MC |
1182 | } |
1183 | ||
7472bab2 | 1184 | OMAP_HSMMC_WRITE(host->base, STAT, status); |
a7e96879 | 1185 | if (end_cmd || ((status & CC_EN) && host->cmd)) |
70a3341a | 1186 | omap_hsmmc_cmd_done(host, host->cmd); |
a7e96879 | 1187 | if ((end_trans || (status & TC_EN)) && host->mrq) |
70a3341a | 1188 | omap_hsmmc_xfer_done(host, data); |
b417577d | 1189 | } |
a45c6cb8 | 1190 | |
b417577d AH |
1191 | /* |
1192 | * MMC controller IRQ handler | |
1193 | */ | |
1194 | static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) | |
1195 | { | |
1196 | struct omap_hsmmc_host *host = dev_id; | |
1197 | int status; | |
1198 | ||
1199 | status = OMAP_HSMMC_READ(host->base, STAT); | |
2cd3a2a5 AF |
1200 | while (status & (INT_EN_MASK | CIRQ_EN)) { |
1201 | if (host->req_in_progress) | |
1202 | omap_hsmmc_do_irq(host, status); | |
1203 | ||
1204 | if (status & CIRQ_EN) | |
1205 | mmc_signal_sdio_irq(host->mmc); | |
1f6b9fa4 | 1206 | |
b417577d AH |
1207 | /* Flush posted write */ |
1208 | status = OMAP_HSMMC_READ(host->base, STAT); | |
1f6b9fa4 | 1209 | } |
4dffd7a2 | 1210 | |
a45c6cb8 MC |
1211 | return IRQ_HANDLED; |
1212 | } | |
1213 | ||
70a3341a | 1214 | static void set_sd_bus_power(struct omap_hsmmc_host *host) |
e13bb300 AH |
1215 | { |
1216 | unsigned long i; | |
1217 | ||
1218 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
1219 | OMAP_HSMMC_READ(host->base, HCTL) | SDBP); | |
1220 | for (i = 0; i < loops_per_jiffy; i++) { | |
1221 | if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) | |
1222 | break; | |
1223 | cpu_relax(); | |
1224 | } | |
1225 | } | |
1226 | ||
a45c6cb8 | 1227 | /* |
eb250826 DB |
1228 | * Switch MMC interface voltage ... only relevant for MMC1. |
1229 | * | |
1230 | * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. | |
1231 | * The MMC2 transceiver controls are used instead of DAT4..DAT7. | |
1232 | * Some chips, like eMMC ones, use internal transceivers. | |
a45c6cb8 | 1233 | */ |
70a3341a | 1234 | static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) |
a45c6cb8 MC |
1235 | { |
1236 | u32 reg_val = 0; | |
1237 | int ret; | |
1238 | ||
1239 | /* Disable the clocks */ | |
cd03d9a8 | 1240 | if (host->dbclk) |
94c18149 | 1241 | clk_disable_unprepare(host->dbclk); |
a45c6cb8 MC |
1242 | |
1243 | /* Turn the power off */ | |
1ca4d359 | 1244 | ret = omap_hsmmc_set_power(host, 0, 0); |
a45c6cb8 MC |
1245 | |
1246 | /* Turn the power ON with given VDD 1.8 or 3.0v */ | |
2bec0893 | 1247 | if (!ret) |
1ca4d359 | 1248 | ret = omap_hsmmc_set_power(host, 1, vdd); |
cd03d9a8 | 1249 | if (host->dbclk) |
94c18149 | 1250 | clk_prepare_enable(host->dbclk); |
2bec0893 | 1251 | |
a45c6cb8 MC |
1252 | if (ret != 0) |
1253 | goto err; | |
1254 | ||
a45c6cb8 MC |
1255 | OMAP_HSMMC_WRITE(host->base, HCTL, |
1256 | OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); | |
1257 | reg_val = OMAP_HSMMC_READ(host->base, HCTL); | |
eb250826 | 1258 | |
a45c6cb8 MC |
1259 | /* |
1260 | * If a MMC dual voltage card is detected, the set_ios fn calls | |
1261 | * this fn with VDD bit set for 1.8V. Upon card removal from the | |
70a3341a | 1262 | * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. |
a45c6cb8 | 1263 | * |
eb250826 DB |
1264 | * Cope with a bit of slop in the range ... per data sheets: |
1265 | * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, | |
1266 | * but recommended values are 1.71V to 1.89V | |
1267 | * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, | |
1268 | * but recommended values are 2.7V to 3.3V | |
1269 | * | |
1270 | * Board setup code shouldn't permit anything very out-of-range. | |
1271 | * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the | |
1272 | * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. | |
a45c6cb8 | 1273 | */ |
eb250826 | 1274 | if ((1 << vdd) <= MMC_VDD_23_24) |
a45c6cb8 | 1275 | reg_val |= SDVS18; |
eb250826 DB |
1276 | else |
1277 | reg_val |= SDVS30; | |
a45c6cb8 MC |
1278 | |
1279 | OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); | |
e13bb300 | 1280 | set_sd_bus_power(host); |
a45c6cb8 MC |
1281 | |
1282 | return 0; | |
1283 | err: | |
b1e056ae | 1284 | dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); |
a45c6cb8 MC |
1285 | return ret; |
1286 | } | |
1287 | ||
b62f6228 AH |
1288 | /* Protect the card while the cover is open */ |
1289 | static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) | |
1290 | { | |
b5cd43f0 | 1291 | if (!host->get_cover_state) |
b62f6228 AH |
1292 | return; |
1293 | ||
1294 | host->reqs_blocked = 0; | |
80412ca8 | 1295 | if (host->get_cover_state(host->dev)) { |
b62f6228 | 1296 | if (host->protect_card) { |
2cecdf00 | 1297 | dev_info(host->dev, "%s: cover is closed, " |
b62f6228 AH |
1298 | "card is now accessible\n", |
1299 | mmc_hostname(host->mmc)); | |
1300 | host->protect_card = 0; | |
1301 | } | |
1302 | } else { | |
1303 | if (!host->protect_card) { | |
2cecdf00 | 1304 | dev_info(host->dev, "%s: cover is open, " |
b62f6228 AH |
1305 | "card is now inaccessible\n", |
1306 | mmc_hostname(host->mmc)); | |
1307 | host->protect_card = 1; | |
1308 | } | |
1309 | } | |
1310 | } | |
1311 | ||
a45c6cb8 | 1312 | /* |
cde592cb | 1313 | * irq handler when (cell-phone) cover is mounted/removed |
a45c6cb8 | 1314 | */ |
cde592cb | 1315 | static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id) |
a45c6cb8 | 1316 | { |
7efab4f3 | 1317 | struct omap_hsmmc_host *host = dev_id; |
a6b2240d | 1318 | |
a6b2240d | 1319 | sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); |
249d0fa9 | 1320 | |
11227d12 AF |
1321 | omap_hsmmc_protect_card(host); |
1322 | mmc_detect_change(host->mmc, (HZ * 200) / 1000); | |
cde592cb AF |
1323 | return IRQ_HANDLED; |
1324 | } | |
1325 | ||
c5c98927 | 1326 | static void omap_hsmmc_dma_callback(void *param) |
a45c6cb8 | 1327 | { |
c5c98927 RK |
1328 | struct omap_hsmmc_host *host = param; |
1329 | struct dma_chan *chan; | |
770d7432 | 1330 | struct mmc_data *data; |
c5c98927 | 1331 | int req_in_progress; |
a45c6cb8 | 1332 | |
c5c98927 | 1333 | spin_lock_irq(&host->irq_lock); |
b417577d | 1334 | if (host->dma_ch < 0) { |
c5c98927 | 1335 | spin_unlock_irq(&host->irq_lock); |
a45c6cb8 | 1336 | return; |
b417577d | 1337 | } |
a45c6cb8 | 1338 | |
770d7432 | 1339 | data = host->mrq->data; |
c5c98927 | 1340 | chan = omap_hsmmc_get_dma_chan(host, data); |
9782aff8 | 1341 | if (!data->host_cookie) |
c5c98927 RK |
1342 | dma_unmap_sg(chan->device->dev, |
1343 | data->sg, data->sg_len, | |
feeef096 | 1344 | mmc_get_dma_dir(data)); |
b417577d AH |
1345 | |
1346 | req_in_progress = host->req_in_progress; | |
a45c6cb8 | 1347 | host->dma_ch = -1; |
c5c98927 | 1348 | spin_unlock_irq(&host->irq_lock); |
b417577d AH |
1349 | |
1350 | /* If DMA has finished after TC, complete the request */ | |
1351 | if (!req_in_progress) { | |
1352 | struct mmc_request *mrq = host->mrq; | |
1353 | ||
1354 | host->mrq = NULL; | |
1355 | mmc_request_done(host->mmc, mrq); | |
1356 | } | |
a45c6cb8 MC |
1357 | } |
1358 | ||
9782aff8 PF |
1359 | static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, |
1360 | struct mmc_data *data, | |
c5c98927 | 1361 | struct omap_hsmmc_next *next, |
26b88520 | 1362 | struct dma_chan *chan) |
9782aff8 PF |
1363 | { |
1364 | int dma_len; | |
1365 | ||
1366 | if (!next && data->host_cookie && | |
1367 | data->host_cookie != host->next_data.cookie) { | |
2cecdf00 | 1368 | dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d" |
9782aff8 PF |
1369 | " host->next_data.cookie %d\n", |
1370 | __func__, data->host_cookie, host->next_data.cookie); | |
1371 | data->host_cookie = 0; | |
1372 | } | |
1373 | ||
1374 | /* Check if next job is already prepared */ | |
b38313d6 | 1375 | if (next || data->host_cookie != host->next_data.cookie) { |
26b88520 | 1376 | dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, |
feeef096 | 1377 | mmc_get_dma_dir(data)); |
9782aff8 PF |
1378 | |
1379 | } else { | |
1380 | dma_len = host->next_data.dma_len; | |
1381 | host->next_data.dma_len = 0; | |
1382 | } | |
1383 | ||
1384 | ||
1385 | if (dma_len == 0) | |
1386 | return -EINVAL; | |
1387 | ||
1388 | if (next) { | |
1389 | next->dma_len = dma_len; | |
1390 | data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; | |
1391 | } else | |
1392 | host->dma_len = dma_len; | |
1393 | ||
1394 | return 0; | |
1395 | } | |
1396 | ||
a45c6cb8 MC |
1397 | /* |
1398 | * Routine to configure and start DMA for the MMC card | |
1399 | */ | |
9d025334 | 1400 | static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host, |
70a3341a | 1401 | struct mmc_request *req) |
a45c6cb8 | 1402 | { |
26b88520 RK |
1403 | struct dma_async_tx_descriptor *tx; |
1404 | int ret = 0, i; | |
a45c6cb8 | 1405 | struct mmc_data *data = req->data; |
c5c98927 | 1406 | struct dma_chan *chan; |
e5789608 PU |
1407 | struct dma_slave_config cfg = { |
1408 | .src_addr = host->mapbase + OMAP_HSMMC_DATA, | |
1409 | .dst_addr = host->mapbase + OMAP_HSMMC_DATA, | |
1410 | .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, | |
1411 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, | |
1412 | .src_maxburst = data->blksz / 4, | |
1413 | .dst_maxburst = data->blksz / 4, | |
1414 | }; | |
a45c6cb8 | 1415 | |
0ccd76d4 | 1416 | /* Sanity check: all the SG entries must be aligned by block size. */ |
a3f406f8 | 1417 | for (i = 0; i < data->sg_len; i++) { |
0ccd76d4 JY |
1418 | struct scatterlist *sgl; |
1419 | ||
1420 | sgl = data->sg + i; | |
1421 | if (sgl->length % data->blksz) | |
1422 | return -EINVAL; | |
1423 | } | |
1424 | if ((data->blksz % 4) != 0) | |
1425 | /* REVISIT: The MMC buffer increments only when MSB is written. | |
1426 | * Return error for blksz which is non multiple of four. | |
1427 | */ | |
1428 | return -EINVAL; | |
1429 | ||
b417577d | 1430 | BUG_ON(host->dma_ch != -1); |
a45c6cb8 | 1431 | |
c5c98927 | 1432 | chan = omap_hsmmc_get_dma_chan(host, data); |
c5c98927 | 1433 | |
26b88520 RK |
1434 | ret = dmaengine_slave_config(chan, &cfg); |
1435 | if (ret) | |
a45c6cb8 | 1436 | return ret; |
c5c98927 | 1437 | |
26b88520 | 1438 | ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan); |
9782aff8 PF |
1439 | if (ret) |
1440 | return ret; | |
a45c6cb8 | 1441 | |
26b88520 RK |
1442 | tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, |
1443 | data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, | |
1444 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
1445 | if (!tx) { | |
1446 | dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); | |
1447 | /* FIXME: cleanup */ | |
1448 | return -1; | |
1449 | } | |
a45c6cb8 | 1450 | |
26b88520 RK |
1451 | tx->callback = omap_hsmmc_dma_callback; |
1452 | tx->callback_param = host; | |
a45c6cb8 | 1453 | |
26b88520 RK |
1454 | /* Does not fail */ |
1455 | dmaengine_submit(tx); | |
c5c98927 | 1456 | |
26b88520 | 1457 | host->dma_ch = 1; |
c5c98927 | 1458 | |
a45c6cb8 MC |
1459 | return 0; |
1460 | } | |
1461 | ||
70a3341a | 1462 | static void set_data_timeout(struct omap_hsmmc_host *host, |
a53210f5 | 1463 | unsigned long long timeout_ns, |
e2bf08d6 | 1464 | unsigned int timeout_clks) |
a45c6cb8 | 1465 | { |
a53210f5 RK |
1466 | unsigned long long timeout = timeout_ns; |
1467 | unsigned int cycle_ns; | |
a45c6cb8 MC |
1468 | uint32_t reg, clkd, dto = 0; |
1469 | ||
1470 | reg = OMAP_HSMMC_READ(host->base, SYSCTL); | |
1471 | clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; | |
1472 | if (clkd == 0) | |
1473 | clkd = 1; | |
1474 | ||
6e3076c2 | 1475 | cycle_ns = 1000000000 / (host->clk_rate / clkd); |
a53210f5 | 1476 | do_div(timeout, cycle_ns); |
e2bf08d6 | 1477 | timeout += timeout_clks; |
a45c6cb8 MC |
1478 | if (timeout) { |
1479 | while ((timeout & 0x80000000) == 0) { | |
1480 | dto += 1; | |
1481 | timeout <<= 1; | |
1482 | } | |
1483 | dto = 31 - dto; | |
1484 | timeout <<= 1; | |
1485 | if (timeout && dto) | |
1486 | dto += 1; | |
1487 | if (dto >= 13) | |
1488 | dto -= 13; | |
1489 | else | |
1490 | dto = 0; | |
1491 | if (dto > 14) | |
1492 | dto = 14; | |
1493 | } | |
1494 | ||
1495 | reg &= ~DTO_MASK; | |
1496 | reg |= dto << DTO_SHIFT; | |
1497 | OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); | |
1498 | } | |
1499 | ||
9d025334 B |
1500 | static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host) |
1501 | { | |
1502 | struct mmc_request *req = host->mrq; | |
1503 | struct dma_chan *chan; | |
1504 | ||
1505 | if (!req->data) | |
1506 | return; | |
1507 | OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) | |
1508 | | (req->data->blocks << 16)); | |
1509 | set_data_timeout(host, req->data->timeout_ns, | |
1510 | req->data->timeout_clks); | |
1511 | chan = omap_hsmmc_get_dma_chan(host, req->data); | |
1512 | dma_async_issue_pending(chan); | |
1513 | } | |
1514 | ||
a45c6cb8 MC |
1515 | /* |
1516 | * Configure block length for MMC/SD cards and initiate the transfer. | |
1517 | */ | |
1518 | static int | |
70a3341a | 1519 | omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) |
a45c6cb8 MC |
1520 | { |
1521 | int ret; | |
a53210f5 | 1522 | unsigned long long timeout; |
8cc9a3e7 | 1523 | |
a45c6cb8 MC |
1524 | host->data = req->data; |
1525 | ||
1526 | if (req->data == NULL) { | |
a45c6cb8 | 1527 | OMAP_HSMMC_WRITE(host->base, BLK, 0); |
8cc9a3e7 KVA |
1528 | if (req->cmd->flags & MMC_RSP_BUSY) { |
1529 | timeout = req->cmd->busy_timeout * NSEC_PER_MSEC; | |
1530 | ||
1531 | /* | |
1532 | * Set an arbitrary 100ms data timeout for commands with | |
1533 | * busy signal and no indication of busy_timeout. | |
1534 | */ | |
1535 | if (!timeout) | |
1536 | timeout = 100000000U; | |
1537 | ||
1538 | set_data_timeout(host, timeout, 0); | |
1539 | } | |
a45c6cb8 MC |
1540 | return 0; |
1541 | } | |
1542 | ||
a45c6cb8 | 1543 | if (host->use_dma) { |
9d025334 | 1544 | ret = omap_hsmmc_setup_dma_transfer(host, req); |
a45c6cb8 | 1545 | if (ret != 0) { |
b1e056ae | 1546 | dev_err(mmc_dev(host->mmc), "MMC start dma failure\n"); |
a45c6cb8 MC |
1547 | return ret; |
1548 | } | |
1549 | } | |
1550 | return 0; | |
1551 | } | |
1552 | ||
9782aff8 PF |
1553 | static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, |
1554 | int err) | |
1555 | { | |
1556 | struct omap_hsmmc_host *host = mmc_priv(mmc); | |
1557 | struct mmc_data *data = mrq->data; | |
1558 | ||
26b88520 | 1559 | if (host->use_dma && data->host_cookie) { |
c5c98927 | 1560 | struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data); |
c5c98927 | 1561 | |
26b88520 | 1562 | dma_unmap_sg(c->device->dev, data->sg, data->sg_len, |
feeef096 | 1563 | mmc_get_dma_dir(data)); |
9782aff8 PF |
1564 | data->host_cookie = 0; |
1565 | } | |
1566 | } | |
1567 | ||
d3c6aac3 | 1568 | static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) |
9782aff8 PF |
1569 | { |
1570 | struct omap_hsmmc_host *host = mmc_priv(mmc); | |
1571 | ||
1572 | if (mrq->data->host_cookie) { | |
1573 | mrq->data->host_cookie = 0; | |
1574 | return ; | |
1575 | } | |
1576 | ||
c5c98927 RK |
1577 | if (host->use_dma) { |
1578 | struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data); | |
c5c98927 | 1579 | |
9782aff8 | 1580 | if (omap_hsmmc_pre_dma_transfer(host, mrq->data, |
26b88520 | 1581 | &host->next_data, c)) |
9782aff8 | 1582 | mrq->data->host_cookie = 0; |
c5c98927 | 1583 | } |
9782aff8 PF |
1584 | } |
1585 | ||
a45c6cb8 MC |
1586 | /* |
1587 | * Request function. for read/write operation | |
1588 | */ | |
70a3341a | 1589 | static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) |
a45c6cb8 | 1590 | { |
70a3341a | 1591 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a3f406f8 | 1592 | int err; |
a45c6cb8 | 1593 | |
b417577d AH |
1594 | BUG_ON(host->req_in_progress); |
1595 | BUG_ON(host->dma_ch != -1); | |
1596 | if (host->protect_card) { | |
1597 | if (host->reqs_blocked < 3) { | |
1598 | /* | |
1599 | * Ensure the controller is left in a consistent | |
1600 | * state by resetting the command and data state | |
1601 | * machines. | |
1602 | */ | |
1603 | omap_hsmmc_reset_controller_fsm(host, SRD); | |
1604 | omap_hsmmc_reset_controller_fsm(host, SRC); | |
1605 | host->reqs_blocked += 1; | |
1606 | } | |
1607 | req->cmd->error = -EBADF; | |
1608 | if (req->data) | |
1609 | req->data->error = -EBADF; | |
1610 | req->cmd->retries = 0; | |
1611 | mmc_request_done(mmc, req); | |
1612 | return; | |
1613 | } else if (host->reqs_blocked) | |
1614 | host->reqs_blocked = 0; | |
a45c6cb8 MC |
1615 | WARN_ON(host->mrq != NULL); |
1616 | host->mrq = req; | |
6e3076c2 | 1617 | host->clk_rate = clk_get_rate(host->fclk); |
70a3341a | 1618 | err = omap_hsmmc_prepare_data(host, req); |
a3f406f8 JL |
1619 | if (err) { |
1620 | req->cmd->error = err; | |
1621 | if (req->data) | |
1622 | req->data->error = err; | |
1623 | host->mrq = NULL; | |
1624 | mmc_request_done(mmc, req); | |
1625 | return; | |
1626 | } | |
a2e77152 | 1627 | if (req->sbc && !(host->flags & AUTO_CMD23)) { |
bf129e1c B |
1628 | omap_hsmmc_start_command(host, req->sbc, NULL); |
1629 | return; | |
1630 | } | |
a3f406f8 | 1631 | |
9d025334 | 1632 | omap_hsmmc_start_dma_transfer(host); |
70a3341a | 1633 | omap_hsmmc_start_command(host, req->cmd, req->data); |
a45c6cb8 MC |
1634 | } |
1635 | ||
a45c6cb8 | 1636 | /* Routine to configure clock values. Exposed API to core */ |
70a3341a | 1637 | static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
a45c6cb8 | 1638 | { |
70a3341a | 1639 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a3621465 | 1640 | int do_send_init_stream = 0; |
a45c6cb8 | 1641 | |
a3621465 AH |
1642 | if (ios->power_mode != host->power_mode) { |
1643 | switch (ios->power_mode) { | |
1644 | case MMC_POWER_OFF: | |
1ca4d359 | 1645 | omap_hsmmc_set_power(host, 0, 0); |
a3621465 AH |
1646 | break; |
1647 | case MMC_POWER_UP: | |
1ca4d359 | 1648 | omap_hsmmc_set_power(host, 1, ios->vdd); |
a3621465 AH |
1649 | break; |
1650 | case MMC_POWER_ON: | |
1651 | do_send_init_stream = 1; | |
1652 | break; | |
1653 | } | |
1654 | host->power_mode = ios->power_mode; | |
a45c6cb8 MC |
1655 | } |
1656 | ||
dd498eff DK |
1657 | /* FIXME: set registers based only on changes to ios */ |
1658 | ||
3796fb8a | 1659 | omap_hsmmc_set_bus_width(host); |
a45c6cb8 | 1660 | |
4621d5f8 | 1661 | if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { |
eb250826 DB |
1662 | /* Only MMC1 can interface at 3V without some flavor |
1663 | * of external transceiver; but they all handle 1.8V. | |
1664 | */ | |
a45c6cb8 | 1665 | if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && |
2cf171cb | 1666 | (ios->vdd == DUAL_VOLT_OCR_BIT)) { |
a45c6cb8 MC |
1667 | /* |
1668 | * The mmc_select_voltage fn of the core does | |
1669 | * not seem to set the power_mode to | |
1670 | * MMC_POWER_UP upon recalculating the voltage. | |
1671 | * vdd 1.8v. | |
1672 | */ | |
70a3341a DK |
1673 | if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) |
1674 | dev_dbg(mmc_dev(host->mmc), | |
a45c6cb8 MC |
1675 | "Switch operation failed\n"); |
1676 | } | |
1677 | } | |
1678 | ||
5934df2f | 1679 | omap_hsmmc_set_clock(host); |
a45c6cb8 | 1680 | |
a3621465 | 1681 | if (do_send_init_stream) |
a45c6cb8 MC |
1682 | send_init_stream(host); |
1683 | ||
3796fb8a | 1684 | omap_hsmmc_set_bus_mode(host); |
a45c6cb8 MC |
1685 | } |
1686 | ||
1687 | static int omap_hsmmc_get_cd(struct mmc_host *mmc) | |
1688 | { | |
70a3341a | 1689 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a45c6cb8 | 1690 | |
b5cd43f0 | 1691 | if (!host->card_detect) |
a45c6cb8 | 1692 | return -ENOSYS; |
80412ca8 | 1693 | return host->card_detect(host->dev); |
a45c6cb8 MC |
1694 | } |
1695 | ||
4816858c GI |
1696 | static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) |
1697 | { | |
1698 | struct omap_hsmmc_host *host = mmc_priv(mmc); | |
1699 | ||
326119c9 AF |
1700 | if (mmc_pdata(host)->init_card) |
1701 | mmc_pdata(host)->init_card(card); | |
4816858c GI |
1702 | } |
1703 | ||
2cd3a2a5 AF |
1704 | static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable) |
1705 | { | |
1706 | struct omap_hsmmc_host *host = mmc_priv(mmc); | |
5a52b08b | 1707 | u32 irq_mask, con; |
2cd3a2a5 AF |
1708 | unsigned long flags; |
1709 | ||
1710 | spin_lock_irqsave(&host->irq_lock, flags); | |
1711 | ||
5a52b08b | 1712 | con = OMAP_HSMMC_READ(host->base, CON); |
2cd3a2a5 AF |
1713 | irq_mask = OMAP_HSMMC_READ(host->base, ISE); |
1714 | if (enable) { | |
1715 | host->flags |= HSMMC_SDIO_IRQ_ENABLED; | |
1716 | irq_mask |= CIRQ_EN; | |
5a52b08b | 1717 | con |= CTPL | CLKEXTFREE; |
2cd3a2a5 AF |
1718 | } else { |
1719 | host->flags &= ~HSMMC_SDIO_IRQ_ENABLED; | |
1720 | irq_mask &= ~CIRQ_EN; | |
5a52b08b | 1721 | con &= ~(CTPL | CLKEXTFREE); |
2cd3a2a5 | 1722 | } |
5a52b08b | 1723 | OMAP_HSMMC_WRITE(host->base, CON, con); |
2cd3a2a5 AF |
1724 | OMAP_HSMMC_WRITE(host->base, IE, irq_mask); |
1725 | ||
1726 | /* | |
1727 | * if enable, piggy back detection on current request | |
1728 | * but always disable immediately | |
1729 | */ | |
1730 | if (!host->req_in_progress || !enable) | |
1731 | OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); | |
1732 | ||
1733 | /* flush posted write */ | |
1734 | OMAP_HSMMC_READ(host->base, IE); | |
1735 | ||
1736 | spin_unlock_irqrestore(&host->irq_lock, flags); | |
1737 | } | |
1738 | ||
1739 | static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host) | |
1740 | { | |
2cd3a2a5 AF |
1741 | int ret; |
1742 | ||
1743 | /* | |
1744 | * For omaps with wake-up path, wakeirq will be irq from pinctrl and | |
1745 | * for other omaps, wakeirq will be from GPIO (dat line remuxed to | |
1746 | * gpio). wakeirq is needed to detect sdio irq in runtime suspend state | |
1747 | * with functional clock disabled. | |
1748 | */ | |
1749 | if (!host->dev->of_node || !host->wake_irq) | |
1750 | return -ENODEV; | |
1751 | ||
5b83b223 | 1752 | ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq); |
2cd3a2a5 AF |
1753 | if (ret) { |
1754 | dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n"); | |
1755 | goto err; | |
1756 | } | |
1757 | ||
1758 | /* | |
1759 | * Some omaps don't have wake-up path from deeper idle states | |
1760 | * and need to remux SDIO DAT1 to GPIO for wake-up from idle. | |
1761 | */ | |
1762 | if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) { | |
455e5cd6 | 1763 | struct pinctrl *p = devm_pinctrl_get(host->dev); |
ec5ab893 DC |
1764 | if (IS_ERR(p)) { |
1765 | ret = PTR_ERR(p); | |
455e5cd6 AF |
1766 | goto err_free_irq; |
1767 | } | |
1768 | if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) { | |
1769 | dev_info(host->dev, "missing default pinctrl state\n"); | |
1770 | devm_pinctrl_put(p); | |
1771 | ret = -EINVAL; | |
1772 | goto err_free_irq; | |
1773 | } | |
1774 | ||
1775 | if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) { | |
1776 | dev_info(host->dev, "missing idle pinctrl state\n"); | |
1777 | devm_pinctrl_put(p); | |
1778 | ret = -EINVAL; | |
1779 | goto err_free_irq; | |
1780 | } | |
1781 | devm_pinctrl_put(p); | |
2cd3a2a5 AF |
1782 | } |
1783 | ||
5a52b08b B |
1784 | OMAP_HSMMC_WRITE(host->base, HCTL, |
1785 | OMAP_HSMMC_READ(host->base, HCTL) | IWE); | |
2cd3a2a5 AF |
1786 | return 0; |
1787 | ||
455e5cd6 | 1788 | err_free_irq: |
5b83b223 | 1789 | dev_pm_clear_wake_irq(host->dev); |
2cd3a2a5 AF |
1790 | err: |
1791 | dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n"); | |
1792 | host->wake_irq = 0; | |
1793 | return ret; | |
1794 | } | |
1795 | ||
70a3341a | 1796 | static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) |
1b331e69 KK |
1797 | { |
1798 | u32 hctl, capa, value; | |
1799 | ||
1800 | /* Only MMC1 supports 3.0V */ | |
4621d5f8 | 1801 | if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { |
1b331e69 KK |
1802 | hctl = SDVS30; |
1803 | capa = VS30 | VS18; | |
1804 | } else { | |
1805 | hctl = SDVS18; | |
1806 | capa = VS18; | |
1807 | } | |
1808 | ||
1809 | value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; | |
1810 | OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); | |
1811 | ||
1812 | value = OMAP_HSMMC_READ(host->base, CAPA); | |
1813 | OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); | |
1814 | ||
1b331e69 | 1815 | /* Set SD bus power bit */ |
e13bb300 | 1816 | set_sd_bus_power(host); |
1b331e69 KK |
1817 | } |
1818 | ||
afd8c29d KM |
1819 | static int omap_hsmmc_multi_io_quirk(struct mmc_card *card, |
1820 | unsigned int direction, int blk_size) | |
1821 | { | |
1822 | /* This controller can't do multiblock reads due to hw bugs */ | |
1823 | if (direction == MMC_DATA_READ) | |
1824 | return 1; | |
1825 | ||
1826 | return blk_size; | |
1827 | } | |
1828 | ||
1829 | static struct mmc_host_ops omap_hsmmc_ops = { | |
9782aff8 PF |
1830 | .post_req = omap_hsmmc_post_req, |
1831 | .pre_req = omap_hsmmc_pre_req, | |
70a3341a DK |
1832 | .request = omap_hsmmc_request, |
1833 | .set_ios = omap_hsmmc_set_ios, | |
dd498eff | 1834 | .get_cd = omap_hsmmc_get_cd, |
a49d8353 | 1835 | .get_ro = mmc_gpio_get_ro, |
4816858c | 1836 | .init_card = omap_hsmmc_init_card, |
2cd3a2a5 | 1837 | .enable_sdio_irq = omap_hsmmc_enable_sdio_irq, |
dd498eff DK |
1838 | }; |
1839 | ||
d900f712 DK |
1840 | #ifdef CONFIG_DEBUG_FS |
1841 | ||
70a3341a | 1842 | static int omap_hsmmc_regs_show(struct seq_file *s, void *data) |
d900f712 DK |
1843 | { |
1844 | struct mmc_host *mmc = s->private; | |
70a3341a | 1845 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
d900f712 | 1846 | |
bb0635f0 AF |
1847 | seq_printf(s, "mmc%d:\n", mmc->index); |
1848 | seq_printf(s, "sdio irq mode\t%s\n", | |
1849 | (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling"); | |
5e2ea617 | 1850 | |
bb0635f0 AF |
1851 | if (mmc->caps & MMC_CAP_SDIO_IRQ) { |
1852 | seq_printf(s, "sdio irq \t%s\n", | |
1853 | (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled" | |
1854 | : "disabled"); | |
1855 | } | |
1856 | seq_printf(s, "ctx_loss:\t%d\n", host->context_loss); | |
d900f712 | 1857 | |
bb0635f0 AF |
1858 | pm_runtime_get_sync(host->dev); |
1859 | seq_puts(s, "\nregs:\n"); | |
d900f712 DK |
1860 | seq_printf(s, "CON:\t\t0x%08x\n", |
1861 | OMAP_HSMMC_READ(host->base, CON)); | |
bb0635f0 AF |
1862 | seq_printf(s, "PSTATE:\t\t0x%08x\n", |
1863 | OMAP_HSMMC_READ(host->base, PSTATE)); | |
d900f712 DK |
1864 | seq_printf(s, "HCTL:\t\t0x%08x\n", |
1865 | OMAP_HSMMC_READ(host->base, HCTL)); | |
1866 | seq_printf(s, "SYSCTL:\t\t0x%08x\n", | |
1867 | OMAP_HSMMC_READ(host->base, SYSCTL)); | |
1868 | seq_printf(s, "IE:\t\t0x%08x\n", | |
1869 | OMAP_HSMMC_READ(host->base, IE)); | |
1870 | seq_printf(s, "ISE:\t\t0x%08x\n", | |
1871 | OMAP_HSMMC_READ(host->base, ISE)); | |
1872 | seq_printf(s, "CAPA:\t\t0x%08x\n", | |
1873 | OMAP_HSMMC_READ(host->base, CAPA)); | |
5e2ea617 | 1874 | |
fa4aa2d4 B |
1875 | pm_runtime_mark_last_busy(host->dev); |
1876 | pm_runtime_put_autosuspend(host->dev); | |
dd498eff | 1877 | |
d900f712 DK |
1878 | return 0; |
1879 | } | |
1880 | ||
70a3341a | 1881 | static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) |
d900f712 | 1882 | { |
70a3341a | 1883 | return single_open(file, omap_hsmmc_regs_show, inode->i_private); |
d900f712 DK |
1884 | } |
1885 | ||
1886 | static const struct file_operations mmc_regs_fops = { | |
70a3341a | 1887 | .open = omap_hsmmc_regs_open, |
d900f712 DK |
1888 | .read = seq_read, |
1889 | .llseek = seq_lseek, | |
1890 | .release = single_release, | |
1891 | }; | |
1892 | ||
70a3341a | 1893 | static void omap_hsmmc_debugfs(struct mmc_host *mmc) |
d900f712 DK |
1894 | { |
1895 | if (mmc->debugfs_root) | |
1896 | debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, | |
1897 | mmc, &mmc_regs_fops); | |
1898 | } | |
1899 | ||
1900 | #else | |
1901 | ||
70a3341a | 1902 | static void omap_hsmmc_debugfs(struct mmc_host *mmc) |
d900f712 DK |
1903 | { |
1904 | } | |
1905 | ||
1906 | #endif | |
1907 | ||
46856a68 | 1908 | #ifdef CONFIG_OF |
59445b10 NM |
1909 | static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = { |
1910 | /* See 35xx errata 2.1.1.128 in SPRZ278F */ | |
1911 | .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, | |
1912 | }; | |
1913 | ||
1914 | static const struct omap_mmc_of_data omap4_mmc_of_data = { | |
1915 | .reg_offset = 0x100, | |
1916 | }; | |
2cd3a2a5 AF |
1917 | static const struct omap_mmc_of_data am33xx_mmc_of_data = { |
1918 | .reg_offset = 0x100, | |
1919 | .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING, | |
1920 | }; | |
46856a68 RN |
1921 | |
1922 | static const struct of_device_id omap_mmc_of_match[] = { | |
1923 | { | |
1924 | .compatible = "ti,omap2-hsmmc", | |
1925 | }, | |
59445b10 NM |
1926 | { |
1927 | .compatible = "ti,omap3-pre-es3-hsmmc", | |
1928 | .data = &omap3_pre_es3_mmc_of_data, | |
1929 | }, | |
46856a68 RN |
1930 | { |
1931 | .compatible = "ti,omap3-hsmmc", | |
1932 | }, | |
1933 | { | |
1934 | .compatible = "ti,omap4-hsmmc", | |
59445b10 | 1935 | .data = &omap4_mmc_of_data, |
46856a68 | 1936 | }, |
2cd3a2a5 AF |
1937 | { |
1938 | .compatible = "ti,am33xx-hsmmc", | |
1939 | .data = &am33xx_mmc_of_data, | |
1940 | }, | |
46856a68 | 1941 | {}, |
b6d085f6 | 1942 | }; |
46856a68 RN |
1943 | MODULE_DEVICE_TABLE(of, omap_mmc_of_match); |
1944 | ||
55143438 | 1945 | static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev) |
46856a68 | 1946 | { |
db863d89 | 1947 | struct omap_hsmmc_platform_data *pdata, *legacy; |
46856a68 | 1948 | struct device_node *np = dev->of_node; |
46856a68 RN |
1949 | |
1950 | pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); | |
1951 | if (!pdata) | |
19df45bc | 1952 | return ERR_PTR(-ENOMEM); /* out of memory */ |
46856a68 | 1953 | |
db863d89 TL |
1954 | legacy = dev_get_platdata(dev); |
1955 | if (legacy && legacy->name) | |
1956 | pdata->name = legacy->name; | |
1957 | ||
46856a68 RN |
1958 | if (of_find_property(np, "ti,dual-volt", NULL)) |
1959 | pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; | |
1960 | ||
b7a5646f AF |
1961 | pdata->gpio_cd = -EINVAL; |
1962 | pdata->gpio_cod = -EINVAL; | |
fdb9de12 | 1963 | pdata->gpio_wp = -EINVAL; |
46856a68 RN |
1964 | |
1965 | if (of_find_property(np, "ti,non-removable", NULL)) { | |
326119c9 AF |
1966 | pdata->nonremovable = true; |
1967 | pdata->no_regulator_off_init = true; | |
46856a68 | 1968 | } |
46856a68 RN |
1969 | |
1970 | if (of_find_property(np, "ti,needs-special-reset", NULL)) | |
326119c9 | 1971 | pdata->features |= HSMMC_HAS_UPDATED_RESET; |
46856a68 | 1972 | |
cd587096 | 1973 | if (of_find_property(np, "ti,needs-special-hs-handling", NULL)) |
326119c9 | 1974 | pdata->features |= HSMMC_HAS_HSPE_SUPPORT; |
cd587096 | 1975 | |
46856a68 RN |
1976 | return pdata; |
1977 | } | |
1978 | #else | |
55143438 | 1979 | static inline struct omap_hsmmc_platform_data |
46856a68 RN |
1980 | *of_get_hsmmc_pdata(struct device *dev) |
1981 | { | |
19df45bc | 1982 | return ERR_PTR(-EINVAL); |
46856a68 RN |
1983 | } |
1984 | #endif | |
1985 | ||
c3be1efd | 1986 | static int omap_hsmmc_probe(struct platform_device *pdev) |
a45c6cb8 | 1987 | { |
55143438 | 1988 | struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data; |
a45c6cb8 | 1989 | struct mmc_host *mmc; |
70a3341a | 1990 | struct omap_hsmmc_host *host = NULL; |
a45c6cb8 | 1991 | struct resource *res; |
db0fefc5 | 1992 | int ret, irq; |
46856a68 | 1993 | const struct of_device_id *match; |
59445b10 | 1994 | const struct omap_mmc_of_data *data; |
77fae219 | 1995 | void __iomem *base; |
46856a68 RN |
1996 | |
1997 | match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); | |
1998 | if (match) { | |
1999 | pdata = of_get_hsmmc_pdata(&pdev->dev); | |
dc642c28 JL |
2000 | |
2001 | if (IS_ERR(pdata)) | |
2002 | return PTR_ERR(pdata); | |
2003 | ||
46856a68 | 2004 | if (match->data) { |
59445b10 NM |
2005 | data = match->data; |
2006 | pdata->reg_offset = data->reg_offset; | |
2007 | pdata->controller_flags |= data->controller_flags; | |
46856a68 RN |
2008 | } |
2009 | } | |
a45c6cb8 MC |
2010 | |
2011 | if (pdata == NULL) { | |
2012 | dev_err(&pdev->dev, "Platform Data is missing\n"); | |
2013 | return -ENXIO; | |
2014 | } | |
2015 | ||
a45c6cb8 MC |
2016 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
2017 | irq = platform_get_irq(pdev, 0); | |
2018 | if (res == NULL || irq < 0) | |
2019 | return -ENXIO; | |
2020 | ||
77fae219 B |
2021 | base = devm_ioremap_resource(&pdev->dev, res); |
2022 | if (IS_ERR(base)) | |
2023 | return PTR_ERR(base); | |
a45c6cb8 | 2024 | |
70a3341a | 2025 | mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); |
a45c6cb8 MC |
2026 | if (!mmc) { |
2027 | ret = -ENOMEM; | |
1e363e3b | 2028 | goto err; |
a45c6cb8 MC |
2029 | } |
2030 | ||
fdb9de12 N |
2031 | ret = mmc_of_parse(mmc); |
2032 | if (ret) | |
2033 | goto err1; | |
2034 | ||
a45c6cb8 MC |
2035 | host = mmc_priv(mmc); |
2036 | host->mmc = mmc; | |
2037 | host->pdata = pdata; | |
2038 | host->dev = &pdev->dev; | |
2039 | host->use_dma = 1; | |
a45c6cb8 MC |
2040 | host->dma_ch = -1; |
2041 | host->irq = irq; | |
fc307df8 | 2042 | host->mapbase = res->start + pdata->reg_offset; |
77fae219 | 2043 | host->base = base + pdata->reg_offset; |
6da20c89 | 2044 | host->power_mode = MMC_POWER_OFF; |
9782aff8 | 2045 | host->next_data.cookie = 1; |
bb2726b5 | 2046 | host->pbias_enabled = 0; |
3f77f702 | 2047 | host->vqmmc_enabled = 0; |
a45c6cb8 | 2048 | |
41afa314 | 2049 | ret = omap_hsmmc_gpio_init(mmc, host, pdata); |
1e363e3b AF |
2050 | if (ret) |
2051 | goto err_gpio; | |
2052 | ||
a45c6cb8 | 2053 | platform_set_drvdata(pdev, host); |
a45c6cb8 | 2054 | |
2cd3a2a5 AF |
2055 | if (pdev->dev.of_node) |
2056 | host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1); | |
2057 | ||
7a8c2cef | 2058 | mmc->ops = &omap_hsmmc_ops; |
dd498eff | 2059 | |
d418ed87 DM |
2060 | mmc->f_min = OMAP_MMC_MIN_CLOCK; |
2061 | ||
2062 | if (pdata->max_freq > 0) | |
2063 | mmc->f_max = pdata->max_freq; | |
fdb9de12 | 2064 | else if (mmc->f_max == 0) |
d418ed87 | 2065 | mmc->f_max = OMAP_MMC_MAX_CLOCK; |
a45c6cb8 | 2066 | |
4dffd7a2 | 2067 | spin_lock_init(&host->irq_lock); |
a45c6cb8 | 2068 | |
9618195e | 2069 | host->fclk = devm_clk_get(&pdev->dev, "fck"); |
a45c6cb8 MC |
2070 | if (IS_ERR(host->fclk)) { |
2071 | ret = PTR_ERR(host->fclk); | |
2072 | host->fclk = NULL; | |
a45c6cb8 MC |
2073 | goto err1; |
2074 | } | |
2075 | ||
9b68256c PW |
2076 | if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { |
2077 | dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); | |
afd8c29d | 2078 | omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk; |
9b68256c | 2079 | } |
dd498eff | 2080 | |
5b83b223 | 2081 | device_init_wakeup(&pdev->dev, true); |
fa4aa2d4 B |
2082 | pm_runtime_enable(host->dev); |
2083 | pm_runtime_get_sync(host->dev); | |
2084 | pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); | |
2085 | pm_runtime_use_autosuspend(host->dev); | |
a45c6cb8 | 2086 | |
92a3aebf B |
2087 | omap_hsmmc_context_save(host); |
2088 | ||
9618195e | 2089 | host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck"); |
cd03d9a8 RN |
2090 | /* |
2091 | * MMC can still work without debounce clock. | |
2092 | */ | |
2093 | if (IS_ERR(host->dbclk)) { | |
cd03d9a8 | 2094 | host->dbclk = NULL; |
94c18149 | 2095 | } else if (clk_prepare_enable(host->dbclk) != 0) { |
cd03d9a8 | 2096 | dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); |
cd03d9a8 | 2097 | host->dbclk = NULL; |
2bec0893 | 2098 | } |
a45c6cb8 | 2099 | |
0ccd76d4 JY |
2100 | /* Since we do only SG emulation, we can have as many segs |
2101 | * as we want. */ | |
a36274e0 | 2102 | mmc->max_segs = 1024; |
0ccd76d4 | 2103 | |
a45c6cb8 MC |
2104 | mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ |
2105 | mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ | |
2106 | mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; | |
2107 | mmc->max_seg_size = mmc->max_req_size; | |
2108 | ||
13189e78 | 2109 | mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | |
93caf8e6 | 2110 | MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; |
a45c6cb8 | 2111 | |
326119c9 | 2112 | mmc->caps |= mmc_pdata(host)->caps; |
3a63833e | 2113 | if (mmc->caps & MMC_CAP_8_BIT_DATA) |
a45c6cb8 MC |
2114 | mmc->caps |= MMC_CAP_4_BIT_DATA; |
2115 | ||
326119c9 | 2116 | if (mmc_pdata(host)->nonremovable) |
23d99bb9 AH |
2117 | mmc->caps |= MMC_CAP_NONREMOVABLE; |
2118 | ||
fdb9de12 | 2119 | mmc->pm_caps |= mmc_pdata(host)->pm_caps; |
6fdc75de | 2120 | |
70a3341a | 2121 | omap_hsmmc_conf_bus_power(host); |
a45c6cb8 | 2122 | |
81eef6ca PU |
2123 | host->rx_chan = dma_request_chan(&pdev->dev, "rx"); |
2124 | if (IS_ERR(host->rx_chan)) { | |
2125 | dev_err(mmc_dev(host->mmc), "RX DMA channel request failed\n"); | |
2126 | ret = PTR_ERR(host->rx_chan); | |
26b88520 RK |
2127 | goto err_irq; |
2128 | } | |
2129 | ||
81eef6ca PU |
2130 | host->tx_chan = dma_request_chan(&pdev->dev, "tx"); |
2131 | if (IS_ERR(host->tx_chan)) { | |
2132 | dev_err(mmc_dev(host->mmc), "TX DMA channel request failed\n"); | |
2133 | ret = PTR_ERR(host->tx_chan); | |
26b88520 | 2134 | goto err_irq; |
c5c98927 | 2135 | } |
a45c6cb8 MC |
2136 | |
2137 | /* Request IRQ for MMC operations */ | |
e1538ed7 | 2138 | ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0, |
a45c6cb8 MC |
2139 | mmc_hostname(mmc), host); |
2140 | if (ret) { | |
b1e056ae | 2141 | dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); |
a45c6cb8 MC |
2142 | goto err_irq; |
2143 | } | |
2144 | ||
987e05c9 KVA |
2145 | ret = omap_hsmmc_reg_get(host); |
2146 | if (ret) | |
2147 | goto err_irq; | |
db0fefc5 | 2148 | |
326119c9 | 2149 | mmc->ocr_avail = mmc_pdata(host)->ocr_mask; |
a45c6cb8 | 2150 | |
b417577d | 2151 | omap_hsmmc_disable_irq(host); |
a45c6cb8 | 2152 | |
2cd3a2a5 AF |
2153 | /* |
2154 | * For now, only support SDIO interrupt if we have a separate | |
2155 | * wake-up interrupt configured from device tree. This is because | |
2156 | * the wake-up interrupt is needed for idle state and some | |
2157 | * platforms need special quirks. And we don't want to add new | |
2158 | * legacy mux platform init code callbacks any longer as we | |
2159 | * are moving to DT based booting anyways. | |
2160 | */ | |
2161 | ret = omap_hsmmc_configure_wake_irq(host); | |
2162 | if (!ret) | |
2163 | mmc->caps |= MMC_CAP_SDIO_IRQ; | |
2164 | ||
b62f6228 AH |
2165 | omap_hsmmc_protect_card(host); |
2166 | ||
a45c6cb8 MC |
2167 | mmc_add_host(mmc); |
2168 | ||
326119c9 | 2169 | if (mmc_pdata(host)->name != NULL) { |
a45c6cb8 MC |
2170 | ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); |
2171 | if (ret < 0) | |
2172 | goto err_slot_name; | |
2173 | } | |
cde592cb | 2174 | if (host->get_cover_state) { |
a45c6cb8 | 2175 | ret = device_create_file(&mmc->class_dev, |
cde592cb | 2176 | &dev_attr_cover_switch); |
a45c6cb8 | 2177 | if (ret < 0) |
db0fefc5 | 2178 | goto err_slot_name; |
a45c6cb8 MC |
2179 | } |
2180 | ||
70a3341a | 2181 | omap_hsmmc_debugfs(mmc); |
fa4aa2d4 B |
2182 | pm_runtime_mark_last_busy(host->dev); |
2183 | pm_runtime_put_autosuspend(host->dev); | |
d900f712 | 2184 | |
a45c6cb8 MC |
2185 | return 0; |
2186 | ||
a45c6cb8 MC |
2187 | err_slot_name: |
2188 | mmc_remove_host(mmc); | |
a45c6cb8 | 2189 | err_irq: |
5b83b223 | 2190 | device_init_wakeup(&pdev->dev, false); |
81eef6ca | 2191 | if (!IS_ERR_OR_NULL(host->tx_chan)) |
c5c98927 | 2192 | dma_release_channel(host->tx_chan); |
81eef6ca | 2193 | if (!IS_ERR_OR_NULL(host->rx_chan)) |
c5c98927 | 2194 | dma_release_channel(host->rx_chan); |
814a3c0c | 2195 | pm_runtime_dont_use_autosuspend(host->dev); |
d59d77ed | 2196 | pm_runtime_put_sync(host->dev); |
37f6190d | 2197 | pm_runtime_disable(host->dev); |
9618195e | 2198 | if (host->dbclk) |
94c18149 | 2199 | clk_disable_unprepare(host->dbclk); |
a45c6cb8 | 2200 | err1: |
1e363e3b | 2201 | err_gpio: |
db0fefc5 | 2202 | mmc_free_host(mmc); |
a45c6cb8 | 2203 | err: |
a45c6cb8 MC |
2204 | return ret; |
2205 | } | |
2206 | ||
6e0ee714 | 2207 | static int omap_hsmmc_remove(struct platform_device *pdev) |
a45c6cb8 | 2208 | { |
70a3341a | 2209 | struct omap_hsmmc_host *host = platform_get_drvdata(pdev); |
a45c6cb8 | 2210 | |
927ce944 FB |
2211 | pm_runtime_get_sync(host->dev); |
2212 | mmc_remove_host(host->mmc); | |
a45c6cb8 | 2213 | |
dc28562b PU |
2214 | dma_release_channel(host->tx_chan); |
2215 | dma_release_channel(host->rx_chan); | |
c5c98927 | 2216 | |
814a3c0c | 2217 | pm_runtime_dont_use_autosuspend(host->dev); |
927ce944 FB |
2218 | pm_runtime_put_sync(host->dev); |
2219 | pm_runtime_disable(host->dev); | |
5b83b223 | 2220 | device_init_wakeup(&pdev->dev, false); |
9618195e | 2221 | if (host->dbclk) |
94c18149 | 2222 | clk_disable_unprepare(host->dbclk); |
a45c6cb8 | 2223 | |
9d1f0286 | 2224 | mmc_free_host(host->mmc); |
927ce944 | 2225 | |
a45c6cb8 MC |
2226 | return 0; |
2227 | } | |
2228 | ||
3d3bbfbd | 2229 | #ifdef CONFIG_PM_SLEEP |
a791daa1 | 2230 | static int omap_hsmmc_suspend(struct device *dev) |
a45c6cb8 | 2231 | { |
927ce944 | 2232 | struct omap_hsmmc_host *host = dev_get_drvdata(dev); |
a45c6cb8 | 2233 | |
927ce944 | 2234 | if (!host) |
a45c6cb8 MC |
2235 | return 0; |
2236 | ||
927ce944 | 2237 | pm_runtime_get_sync(host->dev); |
31f9d463 | 2238 | |
927ce944 | 2239 | if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { |
2cd3a2a5 AF |
2240 | OMAP_HSMMC_WRITE(host->base, ISE, 0); |
2241 | OMAP_HSMMC_WRITE(host->base, IE, 0); | |
2242 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); | |
927ce944 FB |
2243 | OMAP_HSMMC_WRITE(host->base, HCTL, |
2244 | OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); | |
a45c6cb8 | 2245 | } |
927ce944 | 2246 | |
cd03d9a8 | 2247 | if (host->dbclk) |
94c18149 | 2248 | clk_disable_unprepare(host->dbclk); |
3932afd5 | 2249 | |
31f9d463 | 2250 | pm_runtime_put_sync(host->dev); |
3932afd5 | 2251 | return 0; |
a45c6cb8 MC |
2252 | } |
2253 | ||
2254 | /* Routine to resume the MMC device */ | |
a791daa1 | 2255 | static int omap_hsmmc_resume(struct device *dev) |
a45c6cb8 | 2256 | { |
927ce944 FB |
2257 | struct omap_hsmmc_host *host = dev_get_drvdata(dev); |
2258 | ||
2259 | if (!host) | |
2260 | return 0; | |
a45c6cb8 | 2261 | |
927ce944 | 2262 | pm_runtime_get_sync(host->dev); |
11dd62a7 | 2263 | |
cd03d9a8 | 2264 | if (host->dbclk) |
94c18149 | 2265 | clk_prepare_enable(host->dbclk); |
2bec0893 | 2266 | |
927ce944 FB |
2267 | if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) |
2268 | omap_hsmmc_conf_bus_power(host); | |
1b331e69 | 2269 | |
927ce944 | 2270 | omap_hsmmc_protect_card(host); |
927ce944 FB |
2271 | pm_runtime_mark_last_busy(host->dev); |
2272 | pm_runtime_put_autosuspend(host->dev); | |
3932afd5 | 2273 | return 0; |
a45c6cb8 | 2274 | } |
a45c6cb8 MC |
2275 | #endif |
2276 | ||
fa4aa2d4 B |
2277 | static int omap_hsmmc_runtime_suspend(struct device *dev) |
2278 | { | |
2279 | struct omap_hsmmc_host *host; | |
2cd3a2a5 | 2280 | unsigned long flags; |
f945901f | 2281 | int ret = 0; |
fa4aa2d4 B |
2282 | |
2283 | host = platform_get_drvdata(to_platform_device(dev)); | |
2284 | omap_hsmmc_context_save(host); | |
927ce944 | 2285 | dev_dbg(dev, "disabled\n"); |
fa4aa2d4 | 2286 | |
2cd3a2a5 AF |
2287 | spin_lock_irqsave(&host->irq_lock, flags); |
2288 | if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && | |
2289 | (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { | |
2290 | /* disable sdio irq handling to prevent race */ | |
2291 | OMAP_HSMMC_WRITE(host->base, ISE, 0); | |
2292 | OMAP_HSMMC_WRITE(host->base, IE, 0); | |
f945901f AF |
2293 | |
2294 | if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) { | |
2295 | /* | |
2296 | * dat1 line low, pending sdio irq | |
2297 | * race condition: possible irq handler running on | |
2298 | * multi-core, abort | |
2299 | */ | |
2300 | dev_dbg(dev, "pending sdio irq, abort suspend\n"); | |
2301 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); | |
2302 | OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); | |
2303 | OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); | |
2304 | pm_runtime_mark_last_busy(dev); | |
2305 | ret = -EBUSY; | |
2306 | goto abort; | |
2307 | } | |
2cd3a2a5 | 2308 | |
97978a44 | 2309 | pinctrl_pm_select_idle_state(dev); |
97978a44 AF |
2310 | } else { |
2311 | pinctrl_pm_select_idle_state(dev); | |
2cd3a2a5 | 2312 | } |
97978a44 | 2313 | |
f945901f | 2314 | abort: |
2cd3a2a5 | 2315 | spin_unlock_irqrestore(&host->irq_lock, flags); |
f945901f | 2316 | return ret; |
fa4aa2d4 B |
2317 | } |
2318 | ||
2319 | static int omap_hsmmc_runtime_resume(struct device *dev) | |
2320 | { | |
2321 | struct omap_hsmmc_host *host; | |
2cd3a2a5 | 2322 | unsigned long flags; |
fa4aa2d4 B |
2323 | |
2324 | host = platform_get_drvdata(to_platform_device(dev)); | |
2325 | omap_hsmmc_context_restore(host); | |
927ce944 | 2326 | dev_dbg(dev, "enabled\n"); |
fa4aa2d4 | 2327 | |
2cd3a2a5 AF |
2328 | spin_lock_irqsave(&host->irq_lock, flags); |
2329 | if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && | |
2330 | (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { | |
2cd3a2a5 | 2331 | |
97978a44 AF |
2332 | pinctrl_pm_select_default_state(host->dev); |
2333 | ||
2334 | /* irq lost, if pinmux incorrect */ | |
2cd3a2a5 AF |
2335 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); |
2336 | OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); | |
2337 | OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); | |
97978a44 AF |
2338 | } else { |
2339 | pinctrl_pm_select_default_state(host->dev); | |
2cd3a2a5 AF |
2340 | } |
2341 | spin_unlock_irqrestore(&host->irq_lock, flags); | |
fa4aa2d4 B |
2342 | return 0; |
2343 | } | |
2344 | ||
a791daa1 | 2345 | static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { |
3d3bbfbd | 2346 | SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume) |
fa4aa2d4 B |
2347 | .runtime_suspend = omap_hsmmc_runtime_suspend, |
2348 | .runtime_resume = omap_hsmmc_runtime_resume, | |
a791daa1 KH |
2349 | }; |
2350 | ||
2351 | static struct platform_driver omap_hsmmc_driver = { | |
efa25fd3 | 2352 | .probe = omap_hsmmc_probe, |
0433c143 | 2353 | .remove = omap_hsmmc_remove, |
a45c6cb8 MC |
2354 | .driver = { |
2355 | .name = DRIVER_NAME, | |
a791daa1 | 2356 | .pm = &omap_hsmmc_dev_pm_ops, |
46856a68 | 2357 | .of_match_table = of_match_ptr(omap_mmc_of_match), |
a45c6cb8 MC |
2358 | }, |
2359 | }; | |
2360 | ||
b796450b | 2361 | module_platform_driver(omap_hsmmc_driver); |
a45c6cb8 MC |
2362 | MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); |
2363 | MODULE_LICENSE("GPL"); | |
2364 | MODULE_ALIAS("platform:" DRIVER_NAME); | |
2365 | MODULE_AUTHOR("Texas Instruments Inc"); |