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1da177e4 | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/mmci.h - ARM PrimeCell MMCI PL180/1 driver |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | #define MMCIPOWER 0x000 | |
11 | #define MCI_PWR_OFF 0x00 | |
12 | #define MCI_PWR_UP 0x02 | |
13 | #define MCI_PWR_ON 0x03 | |
14 | #define MCI_OD (1 << 6) | |
15 | #define MCI_ROD (1 << 7) | |
16 | ||
17 | #define MMCICLOCK 0x004 | |
18 | #define MCI_CLK_ENABLE (1 << 8) | |
19 | #define MCI_CLK_PWRSAVE (1 << 9) | |
20 | #define MCI_CLK_BYPASS (1 << 10) | |
771dc157 | 21 | #define MCI_4BIT_BUS (1 << 11) |
49ac215e LW |
22 | /* |
23 | * 8bit wide buses, hardware flow contronl, negative edges and clock inversion | |
24 | * supported in ST Micro U300 and Ux500 versions | |
25 | */ | |
771dc157 | 26 | #define MCI_ST_8BIT_BUS (1 << 12) |
49ac215e LW |
27 | #define MCI_ST_U300_HWFCEN (1 << 13) |
28 | #define MCI_ST_UX500_NEG_EDGE (1 << 13) | |
29 | #define MCI_ST_UX500_HWFCEN (1 << 14) | |
30 | #define MCI_ST_UX500_CLK_INV (1 << 15) | |
3a37298a PM |
31 | /* Modified PL180 on Versatile Express platform */ |
32 | #define MCI_ARM_HWFCEN (1 << 12) | |
1da177e4 LT |
33 | |
34 | #define MMCIARGUMENT 0x008 | |
35 | #define MMCICOMMAND 0x00c | |
36 | #define MCI_CPSM_RESPONSE (1 << 6) | |
37 | #define MCI_CPSM_LONGRSP (1 << 7) | |
38 | #define MCI_CPSM_INTERRUPT (1 << 8) | |
39 | #define MCI_CPSM_PENDING (1 << 9) | |
40 | #define MCI_CPSM_ENABLE (1 << 10) | |
cc30d60e LW |
41 | #define MCI_SDIO_SUSP (1 << 11) |
42 | #define MCI_ENCMD_COMPL (1 << 12) | |
43 | #define MCI_NIEN (1 << 13) | |
44 | #define MCI_CE_ATACMD (1 << 14) | |
1da177e4 LT |
45 | |
46 | #define MMCIRESPCMD 0x010 | |
47 | #define MMCIRESPONSE0 0x014 | |
48 | #define MMCIRESPONSE1 0x018 | |
49 | #define MMCIRESPONSE2 0x01c | |
50 | #define MMCIRESPONSE3 0x020 | |
51 | #define MMCIDATATIMER 0x024 | |
52 | #define MMCIDATALENGTH 0x028 | |
53 | #define MMCIDATACTRL 0x02c | |
54 | #define MCI_DPSM_ENABLE (1 << 0) | |
55 | #define MCI_DPSM_DIRECTION (1 << 1) | |
56 | #define MCI_DPSM_MODE (1 << 2) | |
57 | #define MCI_DPSM_DMAENABLE (1 << 3) | |
cc30d60e | 58 | #define MCI_DPSM_BLOCKSIZE (1 << 4) |
725343fa LW |
59 | /* Control register extensions in the ST Micro U300 and Ux500 versions */ |
60 | #define MCI_ST_DPSM_RWSTART (1 << 8) | |
61 | #define MCI_ST_DPSM_RWSTOP (1 << 9) | |
62 | #define MCI_ST_DPSM_RWMOD (1 << 10) | |
63 | #define MCI_ST_DPSM_SDIOEN (1 << 11) | |
64 | /* Control register extensions in the ST Micro Ux500 versions */ | |
65 | #define MCI_ST_DPSM_DMAREQCTL (1 << 12) | |
66 | #define MCI_ST_DPSM_DBOOTMODEEN (1 << 13) | |
67 | #define MCI_ST_DPSM_BUSYMODE (1 << 14) | |
68 | #define MCI_ST_DPSM_DDRMODE (1 << 15) | |
1da177e4 LT |
69 | |
70 | #define MMCIDATACNT 0x030 | |
71 | #define MMCISTATUS 0x034 | |
72 | #define MCI_CMDCRCFAIL (1 << 0) | |
73 | #define MCI_DATACRCFAIL (1 << 1) | |
74 | #define MCI_CMDTIMEOUT (1 << 2) | |
75 | #define MCI_DATATIMEOUT (1 << 3) | |
76 | #define MCI_TXUNDERRUN (1 << 4) | |
77 | #define MCI_RXOVERRUN (1 << 5) | |
78 | #define MCI_CMDRESPEND (1 << 6) | |
79 | #define MCI_CMDSENT (1 << 7) | |
80 | #define MCI_DATAEND (1 << 8) | |
757df746 | 81 | #define MCI_STARTBITERR (1 << 9) |
1da177e4 LT |
82 | #define MCI_DATABLOCKEND (1 << 10) |
83 | #define MCI_CMDACTIVE (1 << 11) | |
84 | #define MCI_TXACTIVE (1 << 12) | |
85 | #define MCI_RXACTIVE (1 << 13) | |
86 | #define MCI_TXFIFOHALFEMPTY (1 << 14) | |
87 | #define MCI_RXFIFOHALFFULL (1 << 15) | |
88 | #define MCI_TXFIFOFULL (1 << 16) | |
89 | #define MCI_RXFIFOFULL (1 << 17) | |
90 | #define MCI_TXFIFOEMPTY (1 << 18) | |
91 | #define MCI_RXFIFOEMPTY (1 << 19) | |
92 | #define MCI_TXDATAAVLBL (1 << 20) | |
93 | #define MCI_RXDATAAVLBL (1 << 21) | |
49ac215e LW |
94 | /* Extended status bits for the ST Micro variants */ |
95 | #define MCI_ST_SDIOIT (1 << 22) | |
96 | #define MCI_ST_CEATAEND (1 << 23) | |
1da177e4 LT |
97 | |
98 | #define MMCICLEAR 0x038 | |
99 | #define MCI_CMDCRCFAILCLR (1 << 0) | |
100 | #define MCI_DATACRCFAILCLR (1 << 1) | |
101 | #define MCI_CMDTIMEOUTCLR (1 << 2) | |
102 | #define MCI_DATATIMEOUTCLR (1 << 3) | |
103 | #define MCI_TXUNDERRUNCLR (1 << 4) | |
104 | #define MCI_RXOVERRUNCLR (1 << 5) | |
105 | #define MCI_CMDRESPENDCLR (1 << 6) | |
106 | #define MCI_CMDSENTCLR (1 << 7) | |
107 | #define MCI_DATAENDCLR (1 << 8) | |
757df746 | 108 | #define MCI_STARTBITERRCLR (1 << 9) |
1da177e4 | 109 | #define MCI_DATABLOCKENDCLR (1 << 10) |
49ac215e LW |
110 | /* Extended status bits for the ST Micro variants */ |
111 | #define MCI_ST_SDIOITC (1 << 22) | |
112 | #define MCI_ST_CEATAENDC (1 << 23) | |
1da177e4 LT |
113 | |
114 | #define MMCIMASK0 0x03c | |
115 | #define MCI_CMDCRCFAILMASK (1 << 0) | |
116 | #define MCI_DATACRCFAILMASK (1 << 1) | |
117 | #define MCI_CMDTIMEOUTMASK (1 << 2) | |
118 | #define MCI_DATATIMEOUTMASK (1 << 3) | |
119 | #define MCI_TXUNDERRUNMASK (1 << 4) | |
120 | #define MCI_RXOVERRUNMASK (1 << 5) | |
121 | #define MCI_CMDRESPENDMASK (1 << 6) | |
122 | #define MCI_CMDSENTMASK (1 << 7) | |
123 | #define MCI_DATAENDMASK (1 << 8) | |
757df746 | 124 | #define MCI_STARTBITERRMASK (1 << 9) |
1da177e4 LT |
125 | #define MCI_DATABLOCKENDMASK (1 << 10) |
126 | #define MCI_CMDACTIVEMASK (1 << 11) | |
127 | #define MCI_TXACTIVEMASK (1 << 12) | |
128 | #define MCI_RXACTIVEMASK (1 << 13) | |
129 | #define MCI_TXFIFOHALFEMPTYMASK (1 << 14) | |
130 | #define MCI_RXFIFOHALFFULLMASK (1 << 15) | |
131 | #define MCI_TXFIFOFULLMASK (1 << 16) | |
132 | #define MCI_RXFIFOFULLMASK (1 << 17) | |
133 | #define MCI_TXFIFOEMPTYMASK (1 << 18) | |
134 | #define MCI_RXFIFOEMPTYMASK (1 << 19) | |
135 | #define MCI_TXDATAAVLBLMASK (1 << 20) | |
136 | #define MCI_RXDATAAVLBLMASK (1 << 21) | |
49ac215e LW |
137 | /* Extended status bits for the ST Micro variants */ |
138 | #define MCI_ST_SDIOITMASK (1 << 22) | |
139 | #define MCI_ST_CEATAENDMASK (1 << 23) | |
1da177e4 LT |
140 | |
141 | #define MMCIMASK1 0x040 | |
142 | #define MMCIFIFOCNT 0x048 | |
143 | #define MMCIFIFO 0x080 /* to 0x0bc */ | |
144 | ||
145 | #define MCI_IRQENABLE \ | |
146 | (MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \ | |
147 | MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \ | |
757df746 | 148 | MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_STARTBITERRMASK) |
1da177e4 | 149 | |
2686b4b4 LW |
150 | /* These interrupts are directed to IRQ1 when two IRQ lines are available */ |
151 | #define MCI_IRQ1MASK \ | |
152 | (MCI_RXFIFOHALFFULLMASK | MCI_RXDATAAVLBLMASK | \ | |
153 | MCI_TXFIFOHALFEMPTYMASK) | |
154 | ||
859dd55d | 155 | #define NR_SG 128 |
1da177e4 LT |
156 | |
157 | struct clk; | |
4956e109 | 158 | struct variant_data; |
c8ebae37 | 159 | struct dma_chan; |
1da177e4 | 160 | |
58c7ccbf PF |
161 | struct mmci_host_next { |
162 | struct dma_async_tx_descriptor *dma_desc; | |
163 | struct dma_chan *dma_chan; | |
164 | s32 cookie; | |
165 | }; | |
166 | ||
1da177e4 | 167 | struct mmci_host { |
c8ebae37 | 168 | phys_addr_t phybase; |
1da177e4 LT |
169 | void __iomem *base; |
170 | struct mmc_request *mrq; | |
171 | struct mmc_command *cmd; | |
172 | struct mmc_data *data; | |
173 | struct mmc_host *mmc; | |
174 | struct clk *clk; | |
89001446 RK |
175 | int gpio_cd; |
176 | int gpio_wp; | |
148b8b39 | 177 | int gpio_cd_irq; |
2686b4b4 | 178 | bool singleirq; |
1da177e4 | 179 | |
1da177e4 LT |
180 | spinlock_t lock; |
181 | ||
182 | unsigned int mclk; | |
183 | unsigned int cclk; | |
7437cfa5 UH |
184 | u32 pwr_reg; |
185 | u32 clk_reg; | |
6ef297f8 | 186 | struct mmci_platform_data *plat; |
4956e109 | 187 | struct variant_data *variant; |
1da177e4 | 188 | |
cc30d60e LW |
189 | u8 hw_designer; |
190 | u8 hw_revision:4; | |
191 | ||
1da177e4 LT |
192 | struct timer_list timer; |
193 | unsigned int oldstat; | |
194 | ||
1da177e4 | 195 | /* pio stuff */ |
4ce1d6cb | 196 | struct sg_mapping_iter sg_miter; |
1da177e4 | 197 | unsigned int size; |
c8ebae37 | 198 | |
a9a83785 LW |
199 | /* pinctrl handles */ |
200 | struct pinctrl *pinctrl; | |
201 | struct pinctrl_state *pins_default; | |
202 | ||
c8ebae37 RK |
203 | #ifdef CONFIG_DMA_ENGINE |
204 | /* DMA stuff */ | |
205 | struct dma_chan *dma_current; | |
206 | struct dma_chan *dma_rx_channel; | |
207 | struct dma_chan *dma_tx_channel; | |
58c7ccbf PF |
208 | struct dma_async_tx_descriptor *dma_desc_current; |
209 | struct mmci_host_next next_data; | |
c8ebae37 RK |
210 | |
211 | #define dma_inprogress(host) ((host)->dma_current) | |
212 | #else | |
213 | #define dma_inprogress(host) (0) | |
214 | #endif | |
1da177e4 LT |
215 | }; |
216 |