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ARM: 5697/1: MMCI Break out clock divider setup
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / mmc / host / mmci.c
CommitLineData
1da177e4 1/*
70f10482 2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
1da177e4
LT		 3 *
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
1da177e4
LT		 10#include <linux/module.h>
11#include <linux/moduleparam.h>
12#include <linux/init.h>
13#include <linux/ioport.h>
14#include <linux/device.h>
15#include <linux/interrupt.h>
16#include <linux/delay.h>
17#include <linux/err.h>
18#include <linux/highmem.h>
019a5f56 19#include <linux/log2.h>
1da177e4 20#include <linux/mmc/host.h>
a62c80e5 21#include <linux/amba/bus.h>
f8ce2547 22#include <linux/clk.h>
bd6dee6f 23#include <linux/scatterlist.h>
89001446 24#include <linux/gpio.h>
1da177e4 25
e9c091b4 26#include <asm/cacheflush.h>
7b09cdac 27#include <asm/div64.h>
1da177e4 28#include <asm/io.h>
c6b8fdad 29#include <asm/sizes.h>
1da177e4
LT		 30#include <asm/mach/mmc.h>
31
32#include "mmci.h"
33
34#define DRIVER_NAME "mmci-pl18x"
35
1da177e4 36#define DBG(host,fmt,args...) \
d366b643 37 pr_debug("%s: %s: " fmt, mmc_hostname(host->mmc), __func__ , args)
1da177e4
LT		 38
39static unsigned int fmax = 515633;
40
a6a6464a
LW		 41/*
42 * This must be called with host->lock held
43 */
44static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
45{
46 u32 clk = 0;
47
48 if (desired) {
49 if (desired >= host->mclk) {
50 clk = MCI_CLK_BYPASS;
51 host->cclk = host->mclk;
52 } else {
53 clk = host->mclk / (2 * desired) - 1;
54 if (clk >= 256)
55 clk = 255;
56 host->cclk = host->mclk / (2 * (clk + 1));
57 }
58 if (host->hw_designer == 0x80)
59 clk |= MCI_FCEN; /* Bug fix in ST IP block */
60 clk |= MCI_CLK_ENABLE;
61 /* This hasn't proven to be worthwhile */
62 /* clk |= MCI_CLK_PWRSAVE; */
63 }
64
65 writel(clk, host->base + MMCICLOCK);
66}
67
1da177e4
LT		 68static void
69mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
70{
71 writel(0, host->base + MMCICOMMAND);
72
e47c222b
RK		 73 BUG_ON(host->data);
74
1da177e4
LT		 75 host->mrq = NULL;
76 host->cmd = NULL;
77
78 if (mrq->data)
79 mrq->data->bytes_xfered = host->data_xfered;
80
81 /*
82 * Need to drop the host lock here; mmc_request_done may call
83 * back into the driver...
84 */
85 spin_unlock(&host->lock);
86 mmc_request_done(host->mmc, mrq);
87 spin_lock(&host->lock);
88}
89
90static void mmci_stop_data(struct mmci_host *host)
91{
92 writel(0, host->base + MMCIDATACTRL);
93 writel(0, host->base + MMCIMASK1);
94 host->data = NULL;
95}
96
97static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
98{
99 unsigned int datactrl, timeout, irqmask;
7b09cdac 100 unsigned long long clks;
1da177e4 101 void __iomem *base;
3bc87f24 102 int blksz_bits;
1da177e4
LT		 103
104 DBG(host, "blksz %04x blks %04x flags %08x\n",
3bc87f24 105 data->blksz, data->blocks, data->flags);
1da177e4
LT		 106
107 host->data = data;
3bc87f24 108 host->size = data->blksz;
1da177e4
LT		 109 host->data_xfered = 0;
110
111 mmci_init_sg(host, data);
112
7b09cdac
RK		 113 clks = (unsigned long long)data->timeout_ns * host->cclk;
114 do_div(clks, 1000000000UL);
115
116 timeout = data->timeout_clks + (unsigned int)clks;
1da177e4
LT		 117
118 base = host->base;
119 writel(timeout, base + MMCIDATATIMER);
120 writel(host->size, base + MMCIDATALENGTH);
121
3bc87f24
RK		 122 blksz_bits = ffs(data->blksz) - 1;
123 BUG_ON(1 << blksz_bits != data->blksz);
124
125 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
1da177e4
LT		 126 if (data->flags & MMC_DATA_READ) {
127 datactrl |= MCI_DPSM_DIRECTION;
128 irqmask = MCI_RXFIFOHALFFULLMASK;
0425a142
RK		 129
130 /*
131 * If we have less than a FIFOSIZE of bytes to transfer,
132 * trigger a PIO interrupt as soon as any data is available.
133 */
134 if (host->size < MCI_FIFOSIZE)
135 irqmask |= MCI_RXDATAAVLBLMASK;
1da177e4
LT		 136 } else {
137 /*
138 * We don't actually need to include "FIFO empty" here
139 * since its implicit in "FIFO half empty".
140 */
141 irqmask = MCI_TXFIFOHALFEMPTYMASK;
142 }
143
144 writel(datactrl, base + MMCIDATACTRL);
145 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
146 writel(irqmask, base + MMCIMASK1);
147}
148
149static void
150mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
151{
152 void __iomem *base = host->base;
153
154 DBG(host, "op %02x arg %08x flags %08x\n",
155 cmd->opcode, cmd->arg, cmd->flags);
156
157 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
158 writel(0, base + MMCICOMMAND);
159 udelay(1);
160 }
161
162 c |= cmd->opcode | MCI_CPSM_ENABLE;
e9225176
RK		 163 if (cmd->flags & MMC_RSP_PRESENT) {
164 if (cmd->flags & MMC_RSP_136)
165 c |= MCI_CPSM_LONGRSP;
1da177e4 166 c |= MCI_CPSM_RESPONSE;
1da177e4
LT		 167 }
168 if (/*interrupt*/0)
169 c |= MCI_CPSM_INTERRUPT;
170
171 host->cmd = cmd;
172
173 writel(cmd->arg, base + MMCIARGUMENT);
174 writel(c, base + MMCICOMMAND);
175}
176
177static void
178mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
179 unsigned int status)
180{
181 if (status & MCI_DATABLOCKEND) {
3bc87f24 182 host->data_xfered += data->blksz;
1da177e4
LT		 183 }
184 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
185 if (status & MCI_DATACRCFAIL)
17b0429d 186 data->error = -EILSEQ;
1da177e4 187 else if (status & MCI_DATATIMEOUT)
17b0429d 188 data->error = -ETIMEDOUT;
1da177e4 189 else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN))
17b0429d 190 data->error = -EIO;
1da177e4 191 status |= MCI_DATAEND;
e9c091b4
RK		 192
193 /*
194 * We hit an error condition. Ensure that any data
195 * partially written to a page is properly coherent.
196 */
197 if (host->sg_len && data->flags & MMC_DATA_READ)
bd6dee6f 198 flush_dcache_page(sg_page(host->sg_ptr));
1da177e4
LT		 199 }
200 if (status & MCI_DATAEND) {
201 mmci_stop_data(host);
202
203 if (!data->stop) {
204 mmci_request_end(host, data->mrq);
205 } else {
206 mmci_start_command(host, data->stop, 0);
207 }
208 }
209}
210
211static void
212mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
213 unsigned int status)
214{
215 void __iomem *base = host->base;
216
217 host->cmd = NULL;
218
219 cmd->resp[0] = readl(base + MMCIRESPONSE0);
220 cmd->resp[1] = readl(base + MMCIRESPONSE1);
221 cmd->resp[2] = readl(base + MMCIRESPONSE2);
222 cmd->resp[3] = readl(base + MMCIRESPONSE3);
223
224 if (status & MCI_CMDTIMEOUT) {
17b0429d 225 cmd->error = -ETIMEDOUT;
1da177e4 226 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
17b0429d 227 cmd->error = -EILSEQ;
1da177e4
LT		 228 }
229
17b0429d 230 if (!cmd->data || cmd->error) {
e47c222b
RK		 231 if (host->data)
232 mmci_stop_data(host);
1da177e4
LT		 233 mmci_request_end(host, cmd->mrq);
234 } else if (!(cmd->data->flags & MMC_DATA_READ)) {
235 mmci_start_data(host, cmd->data);
236 }
237}
238
239static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
240{
241 void __iomem *base = host->base;
242 char *ptr = buffer;
243 u32 status;
26eed9a5 244 int host_remain = host->size;
1da177e4
LT		 245
246 do {
26eed9a5 247 int count = host_remain - (readl(base + MMCIFIFOCNT) << 2);
1da177e4
LT		 248
249 if (count > remain)
250 count = remain;
251
252 if (count <= 0)
253 break;
254
255 readsl(base + MMCIFIFO, ptr, count >> 2);
256
257 ptr += count;
258 remain -= count;
26eed9a5 259 host_remain -= count;
1da177e4
LT		 260
261 if (remain == 0)
262 break;
263
264 status = readl(base + MMCISTATUS);
265 } while (status & MCI_RXDATAAVLBL);
266
267 return ptr - buffer;
268}
269
270static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
271{
272 void __iomem *base = host->base;
273 char *ptr = buffer;
274
275 do {
276 unsigned int count, maxcnt;
277
278 maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE : MCI_FIFOHALFSIZE;
279 count = min(remain, maxcnt);
280
281 writesl(base + MMCIFIFO, ptr, count >> 2);
282
283 ptr += count;
284 remain -= count;
285
286 if (remain == 0)
287 break;
288
289 status = readl(base + MMCISTATUS);
290 } while (status & MCI_TXFIFOHALFEMPTY);
291
292 return ptr - buffer;
293}
294
295/*
296 * PIO data transfer IRQ handler.
297 */
7d12e780 298static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
1da177e4
LT		 299{
300 struct mmci_host *host = dev_id;
301 void __iomem *base = host->base;
302 u32 status;
303
304 status = readl(base + MMCISTATUS);
305
306 DBG(host, "irq1 %08x\n", status);
307
308 do {
309 unsigned long flags;
310 unsigned int remain, len;
311 char *buffer;
312
313 /*
314 * For write, we only need to test the half-empty flag
315 * here - if the FIFO is completely empty, then by
316 * definition it is more than half empty.
317 *
318 * For read, check for data available.
319 */
320 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
321 break;
322
323 /*
324 * Map the current scatter buffer.
325 */
326 buffer = mmci_kmap_atomic(host, &flags) + host->sg_off;
327 remain = host->sg_ptr->length - host->sg_off;
328
329 len = 0;
330 if (status & MCI_RXACTIVE)
331 len = mmci_pio_read(host, buffer, remain);
332 if (status & MCI_TXACTIVE)
333 len = mmci_pio_write(host, buffer, remain, status);
334
335 /*
336 * Unmap the buffer.
337 */
f3e2628b 338 mmci_kunmap_atomic(host, buffer, &flags);
1da177e4
LT		 339
340 host->sg_off += len;
341 host->size -= len;
342 remain -= len;
343
344 if (remain)
345 break;
346
e9c091b4
RK		 347 /*
348 * If we were reading, and we have completed this
349 * page, ensure that the data cache is coherent.
350 */
351 if (status & MCI_RXACTIVE)
bd6dee6f 352 flush_dcache_page(sg_page(host->sg_ptr));
e9c091b4 353
1da177e4
LT		 354 if (!mmci_next_sg(host))
355 break;
356
357 status = readl(base + MMCISTATUS);
358 } while (1);
359
360 /*
361 * If we're nearing the end of the read, switch to
362 * "any data available" mode.
363 */
364 if (status & MCI_RXACTIVE && host->size < MCI_FIFOSIZE)
365 writel(MCI_RXDATAAVLBLMASK, base + MMCIMASK1);
366
367 /*
368 * If we run out of data, disable the data IRQs; this
369 * prevents a race where the FIFO becomes empty before
370 * the chip itself has disabled the data path, and
371 * stops us racing with our data end IRQ.
372 */
373 if (host->size == 0) {
374 writel(0, base + MMCIMASK1);
375 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
376 }
377
378 return IRQ_HANDLED;
379}
380
381/*
382 * Handle completion of command and data transfers.
383 */
7d12e780 384static irqreturn_t mmci_irq(int irq, void *dev_id)
1da177e4
LT		 385{
386 struct mmci_host *host = dev_id;
387 u32 status;
388 int ret = 0;
389
390 spin_lock(&host->lock);
391
392 do {
393 struct mmc_command *cmd;
394 struct mmc_data *data;
395
396 status = readl(host->base + MMCISTATUS);
397 status &= readl(host->base + MMCIMASK0);
398 writel(status, host->base + MMCICLEAR);
399
400 DBG(host, "irq0 %08x\n", status);
401
402 data = host->data;
403 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|
404 MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data)
405 mmci_data_irq(host, data, status);
406
407 cmd = host->cmd;
408 if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
409 mmci_cmd_irq(host, cmd, status);
410
411 ret = 1;
412 } while (status);
413
414 spin_unlock(&host->lock);
415
416 return IRQ_RETVAL(ret);
417}
418
419static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
420{
421 struct mmci_host *host = mmc_priv(mmc);
9e943021 422 unsigned long flags;
1da177e4
LT		 423
424 WARN_ON(host->mrq != NULL);
425
019a5f56 426 if (mrq->data && !is_power_of_2(mrq->data->blksz)) {
255d01af
PO		 427 printk(KERN_ERR "%s: Unsupported block size (%d bytes)\n",
428 mmc_hostname(mmc), mrq->data->blksz);
429 mrq->cmd->error = -EINVAL;
430 mmc_request_done(mmc, mrq);
431 return;
432 }
433
9e943021 434 spin_lock_irqsave(&host->lock, flags);
1da177e4
LT		 435
436 host->mrq = mrq;
437
438 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
439 mmci_start_data(host, mrq->data);
440
441 mmci_start_command(host, mrq->cmd, 0);
442
9e943021 443 spin_unlock_irqrestore(&host->lock, flags);
1da177e4
LT		 444}
445
446static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
447{
448 struct mmci_host *host = mmc_priv(mmc);
a6a6464a
LW		 449 u32 pwr = 0;
450 unsigned long flags;
1da177e4
LT		 451
452 if (host->plat->translate_vdd)
453 pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd);
454
455 switch (ios->power_mode) {
456 case MMC_POWER_OFF:
457 break;
458 case MMC_POWER_UP:
cc30d60e 459 /* The ST version does not have this, fall through to POWER_ON */
f17a1f06 460 if (host->hw_designer != AMBA_VENDOR_ST) {
cc30d60e
LW		 461 pwr |= MCI_PWR_UP;
462 break;
463 }
1da177e4
LT		 464 case MMC_POWER_ON:
465 pwr |= MCI_PWR_ON;
466 break;
467 }
468
cc30d60e 469 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
f17a1f06 470 if (host->hw_designer != AMBA_VENDOR_ST)
cc30d60e
LW		 471 pwr |= MCI_ROD;
472 else {
473 /*
474 * The ST Micro variant use the ROD bit for something
475 * else and only has OD (Open Drain).
476 */
477 pwr |= MCI_OD;
478 }
479 }
1da177e4 480
a6a6464a
LW		 481 spin_lock_irqsave(&host->lock, flags);
482
483 mmci_set_clkreg(host, ios->clock);
1da177e4
LT		 484
485 if (host->pwr != pwr) {
486 host->pwr = pwr;
487 writel(pwr, host->base + MMCIPOWER);
488 }
a6a6464a
LW		 489
490 spin_unlock_irqrestore(&host->lock, flags);
1da177e4
LT		 491}
492
89001446
RK		 493static int mmci_get_ro(struct mmc_host *mmc)
494{
495 struct mmci_host *host = mmc_priv(mmc);
496
497 if (host->gpio_wp == -ENOSYS)
498 return -ENOSYS;
499
500 return gpio_get_value(host->gpio_wp);
501}
502
503static int mmci_get_cd(struct mmc_host *mmc)
504{
505 struct mmci_host *host = mmc_priv(mmc);
506 unsigned int status;
507
508 if (host->gpio_cd == -ENOSYS)
509 status = host->plat->status(mmc_dev(host->mmc));
510 else
511 status = gpio_get_value(host->gpio_cd);
512
513 return !status;
514}
515
ab7aefd0 516static const struct mmc_host_ops mmci_ops = {
1da177e4
LT		 517 .request = mmci_request,
518 .set_ios = mmci_set_ios,
89001446
RK		 519 .get_ro = mmci_get_ro,
520 .get_cd = mmci_get_cd,
1da177e4
LT		 521};
522
523static void mmci_check_status(unsigned long data)
524{
525 struct mmci_host *host = (struct mmci_host *)data;
89001446 526 unsigned int status = mmci_get_cd(host->mmc);
1da177e4 527
1da177e4 528 if (status ^ host->oldstat)
8dc00335 529 mmc_detect_change(host->mmc, 0);
1da177e4
LT		 530
531 host->oldstat = status;
532 mod_timer(&host->timer, jiffies + HZ);
533}
534
03fbdb15 535static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
1da177e4
LT		 536{
537 struct mmc_platform_data *plat = dev->dev.platform_data;
538 struct mmci_host *host;
539 struct mmc_host *mmc;
540 int ret;
541
542 /* must have platform data */
543 if (!plat) {
544 ret = -EINVAL;
545 goto out;
546 }
547
548 ret = amba_request_regions(dev, DRIVER_NAME);
549 if (ret)
550 goto out;
551
552 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
553 if (!mmc) {
554 ret = -ENOMEM;
555 goto rel_regions;
556 }
557
558 host = mmc_priv(mmc);
4ea580f1 559 host->mmc = mmc;
012b7d33 560
89001446
RK		 561 host->gpio_wp = -ENOSYS;
562 host->gpio_cd = -ENOSYS;
563
012b7d33
RK		 564 host->hw_designer = amba_manf(dev);
565 host->hw_revision = amba_rev(dev);
cc30d60e
LW		 566 DBG(host, "designer ID = 0x%02x\n", host->hw_designer);
567 DBG(host, "revision = 0x%01x\n", host->hw_revision);
012b7d33 568
ee569c43 569 host->clk = clk_get(&dev->dev, NULL);
1da177e4
LT		 570 if (IS_ERR(host->clk)) {
571 ret = PTR_ERR(host->clk);
572 host->clk = NULL;
573 goto host_free;
574 }
575
1da177e4
LT		 576 ret = clk_enable(host->clk);
577 if (ret)
a8d3584a 578 goto clk_free;
1da177e4
LT		 579
580 host->plat = plat;
581 host->mclk = clk_get_rate(host->clk);
c8df9a53
LW		 582 /*
583 * According to the spec, mclk is max 100 MHz,
584 * so we try to adjust the clock down to this,
585 * (if possible).
586 */
587 if (host->mclk > 100000000) {
588 ret = clk_set_rate(host->clk, 100000000);
589 if (ret < 0)
590 goto clk_disable;
591 host->mclk = clk_get_rate(host->clk);
592 DBG(host, "eventual mclk rate: %u Hz\n", host->mclk);
593 }
dc890c2d 594 host->base = ioremap(dev->res.start, resource_size(&dev->res));
1da177e4
LT		 595 if (!host->base) {
596 ret = -ENOMEM;
597 goto clk_disable;
598 }
599
600 mmc->ops = &mmci_ops;
601 mmc->f_min = (host->mclk + 511) / 512;
602 mmc->f_max = min(host->mclk, fmax);
603 mmc->ocr_avail = plat->ocr_mask;
604
605 /*
606 * We can do SGIO
607 */
608 mmc->max_hw_segs = 16;
609 mmc->max_phys_segs = NR_SG;
610
611 /*
612 * Since we only have a 16-bit data length register, we must
613 * ensure that we don't exceed 2^16-1 bytes in a single request.
1da177e4 614 */
55db890a 615 mmc->max_req_size = 65535;
1da177e4
LT		 616
617 /*
618 * Set the maximum segment size. Since we aren't doing DMA
619 * (yet) we are only limited by the data length register.
620 */
55db890a 621 mmc->max_seg_size = mmc->max_req_size;
1da177e4 622
fe4a3c7a
PO		 623 /*
624 * Block size can be up to 2048 bytes, but must be a power of two.
625 */
626 mmc->max_blk_size = 2048;
627
55db890a
PO		 628 /*
629 * No limit on the number of blocks transferred.
630 */
631 mmc->max_blk_count = mmc->max_req_size;
632
1da177e4
LT		 633 spin_lock_init(&host->lock);
634
635 writel(0, host->base + MMCIMASK0);
636 writel(0, host->base + MMCIMASK1);
637 writel(0xfff, host->base + MMCICLEAR);
638
7064d209 639#ifdef CONFIG_GPIOLIB
89001446
RK		 640 if (gpio_is_valid(plat->gpio_cd)) {
641 ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)");
642 if (ret == 0)
643 ret = gpio_direction_input(plat->gpio_cd);
644 if (ret == 0)
645 host->gpio_cd = plat->gpio_cd;
646 else if (ret != -ENOSYS)
647 goto err_gpio_cd;
648 }
649 if (gpio_is_valid(plat->gpio_wp)) {
650 ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)");
651 if (ret == 0)
652 ret = gpio_direction_input(plat->gpio_wp);
653 if (ret == 0)
654 host->gpio_wp = plat->gpio_wp;
655 else if (ret != -ENOSYS)
656 goto err_gpio_wp;
657 }
7064d209 658#endif
89001446 659
dace1453 660 ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host);
1da177e4
LT		 661 if (ret)
662 goto unmap;
663
dace1453 664 ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, DRIVER_NAME " (pio)", host);
1da177e4
LT		 665 if (ret)
666 goto irq0_free;
667
668 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
669
670 amba_set_drvdata(dev, mmc);
89001446 671 host->oldstat = mmci_get_cd(host->mmc);
1da177e4
LT		 672
673 mmc_add_host(mmc);
674
e29419ff 675 printk(KERN_INFO "%s: MMCI rev %x cfg %02x at 0x%016llx irq %d,%d\n",
d366b643 676 mmc_hostname(mmc), amba_rev(dev), amba_config(dev),
e29419ff 677 (unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]);
1da177e4
LT		 678
679 init_timer(&host->timer);
680 host->timer.data = (unsigned long)host;
681 host->timer.function = mmci_check_status;
682 host->timer.expires = jiffies + HZ;
683 add_timer(&host->timer);
684
685 return 0;
686
687 irq0_free:
688 free_irq(dev->irq[0], host);
689 unmap:
89001446
RK		 690 if (host->gpio_wp != -ENOSYS)
691 gpio_free(host->gpio_wp);
692 err_gpio_wp:
693 if (host->gpio_cd != -ENOSYS)
694 gpio_free(host->gpio_cd);
695 err_gpio_cd:
1da177e4
LT		 696 iounmap(host->base);
697 clk_disable:
698 clk_disable(host->clk);
1da177e4
LT		 699 clk_free:
700 clk_put(host->clk);
701 host_free:
702 mmc_free_host(mmc);
703 rel_regions:
704 amba_release_regions(dev);
705 out:
706 return ret;
707}
708
6dc4a47a 709static int __devexit mmci_remove(struct amba_device *dev)
1da177e4
LT		 710{
711 struct mmc_host *mmc = amba_get_drvdata(dev);
712
713 amba_set_drvdata(dev, NULL);
714
715 if (mmc) {
716 struct mmci_host *host = mmc_priv(mmc);
717
718 del_timer_sync(&host->timer);
719
720 mmc_remove_host(mmc);
721
722 writel(0, host->base + MMCIMASK0);
723 writel(0, host->base + MMCIMASK1);
724
725 writel(0, host->base + MMCICOMMAND);
726 writel(0, host->base + MMCIDATACTRL);
727
728 free_irq(dev->irq[0], host);
729 free_irq(dev->irq[1], host);
730
89001446
RK		 731 if (host->gpio_wp != -ENOSYS)
732 gpio_free(host->gpio_wp);
733 if (host->gpio_cd != -ENOSYS)
734 gpio_free(host->gpio_cd);
735
1da177e4
LT		 736 iounmap(host->base);
737 clk_disable(host->clk);
1da177e4
LT		 738 clk_put(host->clk);
739
740 mmc_free_host(mmc);
741
742 amba_release_regions(dev);
743 }
744
745 return 0;
746}
747
748#ifdef CONFIG_PM
e5378ca8 749static int mmci_suspend(struct amba_device *dev, pm_message_t state)
1da177e4
LT		 750{
751 struct mmc_host *mmc = amba_get_drvdata(dev);
752 int ret = 0;
753
754 if (mmc) {
755 struct mmci_host *host = mmc_priv(mmc);
756
757 ret = mmc_suspend_host(mmc, state);
758 if (ret == 0)
759 writel(0, host->base + MMCIMASK0);
760 }
761
762 return ret;
763}
764
765static int mmci_resume(struct amba_device *dev)
766{
767 struct mmc_host *mmc = amba_get_drvdata(dev);
768 int ret = 0;
769
770 if (mmc) {
771 struct mmci_host *host = mmc_priv(mmc);
772
773 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
774
775 ret = mmc_resume_host(mmc);
776 }
777
778 return ret;
779}
780#else
781#define mmci_suspend NULL
782#define mmci_resume NULL
783#endif
784
785static struct amba_id mmci_ids[] = {
786 {
787 .id = 0x00041180,
788 .mask = 0x000fffff,
789 },
790 {
791 .id = 0x00041181,
792 .mask = 0x000fffff,
793 },
cc30d60e
LW		 794 /* ST Micro variants */
795 {
796 .id = 0x00180180,
797 .mask = 0x00ffffff,
798 },
799 {
800 .id = 0x00280180,
801 .mask = 0x00ffffff,
802 },
1da177e4
LT		 803 { 0, 0 },
804};
805
806static struct amba_driver mmci_driver = {
807 .drv = {
808 .name = DRIVER_NAME,
809 },
810 .probe = mmci_probe,
6dc4a47a 811 .remove = __devexit_p(mmci_remove),
1da177e4
LT		 812 .suspend = mmci_suspend,
813 .resume = mmci_resume,
814 .id_table = mmci_ids,
815};
816
817static int __init mmci_init(void)
818{
819 return amba_driver_register(&mmci_driver);
820}
821
822static void __exit mmci_exit(void)
823{
824 amba_driver_unregister(&mmci_driver);
825}
826
827module_init(mmci_init);
828module_exit(mmci_exit);
829module_param(fmax, uint, 0444);
830
831MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
832MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)