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b4cff454 VB |
1 | /* |
2 | * davinci_mmc.c - TI DaVinci MMC/SD/SDIO driver | |
3 | * | |
4 | * Copyright (C) 2006 Texas Instruments. | |
5 | * Original author: Purushotam Kumar | |
6 | * Copyright (C) 2009 David Brownell | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | #include <linux/module.h> | |
24 | #include <linux/ioport.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/clk.h> | |
27 | #include <linux/err.h> | |
7e30b8de | 28 | #include <linux/cpufreq.h> |
b4cff454 VB |
29 | #include <linux/mmc/host.h> |
30 | #include <linux/io.h> | |
31 | #include <linux/irq.h> | |
32 | #include <linux/delay.h> | |
5413da81 | 33 | #include <linux/dmaengine.h> |
b4cff454 VB |
34 | #include <linux/dma-mapping.h> |
35 | #include <linux/mmc/mmc.h> | |
7b43da4c MP |
36 | #include <linux/of.h> |
37 | #include <linux/of_device.h> | |
c8301e79 | 38 | #include <linux/mmc/slot-gpio.h> |
b8789ec4 | 39 | #include <linux/interrupt.h> |
b4cff454 | 40 | |
ec2a0833 | 41 | #include <linux/platform_data/mmc-davinci.h> |
b4cff454 VB |
42 | |
43 | /* | |
44 | * Register Definitions | |
45 | */ | |
46 | #define DAVINCI_MMCCTL 0x00 /* Control Register */ | |
47 | #define DAVINCI_MMCCLK 0x04 /* Memory Clock Control Register */ | |
48 | #define DAVINCI_MMCST0 0x08 /* Status Register 0 */ | |
49 | #define DAVINCI_MMCST1 0x0C /* Status Register 1 */ | |
50 | #define DAVINCI_MMCIM 0x10 /* Interrupt Mask Register */ | |
51 | #define DAVINCI_MMCTOR 0x14 /* Response Time-Out Register */ | |
52 | #define DAVINCI_MMCTOD 0x18 /* Data Read Time-Out Register */ | |
53 | #define DAVINCI_MMCBLEN 0x1C /* Block Length Register */ | |
54 | #define DAVINCI_MMCNBLK 0x20 /* Number of Blocks Register */ | |
55 | #define DAVINCI_MMCNBLC 0x24 /* Number of Blocks Counter Register */ | |
56 | #define DAVINCI_MMCDRR 0x28 /* Data Receive Register */ | |
57 | #define DAVINCI_MMCDXR 0x2C /* Data Transmit Register */ | |
58 | #define DAVINCI_MMCCMD 0x30 /* Command Register */ | |
59 | #define DAVINCI_MMCARGHL 0x34 /* Argument Register */ | |
60 | #define DAVINCI_MMCRSP01 0x38 /* Response Register 0 and 1 */ | |
61 | #define DAVINCI_MMCRSP23 0x3C /* Response Register 0 and 1 */ | |
62 | #define DAVINCI_MMCRSP45 0x40 /* Response Register 0 and 1 */ | |
63 | #define DAVINCI_MMCRSP67 0x44 /* Response Register 0 and 1 */ | |
64 | #define DAVINCI_MMCDRSP 0x48 /* Data Response Register */ | |
65 | #define DAVINCI_MMCETOK 0x4C | |
66 | #define DAVINCI_MMCCIDX 0x50 /* Command Index Register */ | |
67 | #define DAVINCI_MMCCKC 0x54 | |
68 | #define DAVINCI_MMCTORC 0x58 | |
69 | #define DAVINCI_MMCTODC 0x5C | |
70 | #define DAVINCI_MMCBLNC 0x60 | |
71 | #define DAVINCI_SDIOCTL 0x64 | |
72 | #define DAVINCI_SDIOST0 0x68 | |
f9db92cb AS |
73 | #define DAVINCI_SDIOIEN 0x6C |
74 | #define DAVINCI_SDIOIST 0x70 | |
b4cff454 VB |
75 | #define DAVINCI_MMCFIFOCTL 0x74 /* FIFO Control Register */ |
76 | ||
77 | /* DAVINCI_MMCCTL definitions */ | |
78 | #define MMCCTL_DATRST (1 << 0) | |
79 | #define MMCCTL_CMDRST (1 << 1) | |
132f1074 | 80 | #define MMCCTL_WIDTH_8_BIT (1 << 8) |
b4cff454 VB |
81 | #define MMCCTL_WIDTH_4_BIT (1 << 2) |
82 | #define MMCCTL_DATEG_DISABLED (0 << 6) | |
83 | #define MMCCTL_DATEG_RISING (1 << 6) | |
84 | #define MMCCTL_DATEG_FALLING (2 << 6) | |
85 | #define MMCCTL_DATEG_BOTH (3 << 6) | |
86 | #define MMCCTL_PERMDR_LE (0 << 9) | |
87 | #define MMCCTL_PERMDR_BE (1 << 9) | |
88 | #define MMCCTL_PERMDX_LE (0 << 10) | |
89 | #define MMCCTL_PERMDX_BE (1 << 10) | |
90 | ||
91 | /* DAVINCI_MMCCLK definitions */ | |
92 | #define MMCCLK_CLKEN (1 << 8) | |
93 | #define MMCCLK_CLKRT_MASK (0xFF << 0) | |
94 | ||
95 | /* IRQ bit definitions, for DAVINCI_MMCST0 and DAVINCI_MMCIM */ | |
96 | #define MMCST0_DATDNE BIT(0) /* data done */ | |
97 | #define MMCST0_BSYDNE BIT(1) /* busy done */ | |
98 | #define MMCST0_RSPDNE BIT(2) /* command done */ | |
99 | #define MMCST0_TOUTRD BIT(3) /* data read timeout */ | |
100 | #define MMCST0_TOUTRS BIT(4) /* command response timeout */ | |
101 | #define MMCST0_CRCWR BIT(5) /* data write CRC error */ | |
102 | #define MMCST0_CRCRD BIT(6) /* data read CRC error */ | |
103 | #define MMCST0_CRCRS BIT(7) /* command response CRC error */ | |
104 | #define MMCST0_DXRDY BIT(9) /* data transmit ready (fifo empty) */ | |
105 | #define MMCST0_DRRDY BIT(10) /* data receive ready (data in fifo)*/ | |
106 | #define MMCST0_DATED BIT(11) /* DAT3 edge detect */ | |
107 | #define MMCST0_TRNDNE BIT(12) /* transfer done */ | |
108 | ||
109 | /* DAVINCI_MMCST1 definitions */ | |
110 | #define MMCST1_BUSY (1 << 0) | |
111 | ||
112 | /* DAVINCI_MMCCMD definitions */ | |
113 | #define MMCCMD_CMD_MASK (0x3F << 0) | |
114 | #define MMCCMD_PPLEN (1 << 7) | |
115 | #define MMCCMD_BSYEXP (1 << 8) | |
116 | #define MMCCMD_RSPFMT_MASK (3 << 9) | |
117 | #define MMCCMD_RSPFMT_NONE (0 << 9) | |
118 | #define MMCCMD_RSPFMT_R1456 (1 << 9) | |
119 | #define MMCCMD_RSPFMT_R2 (2 << 9) | |
120 | #define MMCCMD_RSPFMT_R3 (3 << 9) | |
121 | #define MMCCMD_DTRW (1 << 11) | |
122 | #define MMCCMD_STRMTP (1 << 12) | |
123 | #define MMCCMD_WDATX (1 << 13) | |
124 | #define MMCCMD_INITCK (1 << 14) | |
125 | #define MMCCMD_DCLR (1 << 15) | |
126 | #define MMCCMD_DMATRIG (1 << 16) | |
127 | ||
128 | /* DAVINCI_MMCFIFOCTL definitions */ | |
129 | #define MMCFIFOCTL_FIFORST (1 << 0) | |
130 | #define MMCFIFOCTL_FIFODIR_WR (1 << 1) | |
131 | #define MMCFIFOCTL_FIFODIR_RD (0 << 1) | |
132 | #define MMCFIFOCTL_FIFOLEV (1 << 2) /* 0 = 128 bits, 1 = 256 bits */ | |
133 | #define MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */ | |
134 | #define MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */ | |
135 | #define MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */ | |
136 | #define MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */ | |
137 | ||
f9db92cb AS |
138 | /* DAVINCI_SDIOST0 definitions */ |
139 | #define SDIOST0_DAT1_HI BIT(0) | |
140 | ||
141 | /* DAVINCI_SDIOIEN definitions */ | |
142 | #define SDIOIEN_IOINTEN BIT(0) | |
143 | ||
144 | /* DAVINCI_SDIOIST definitions */ | |
145 | #define SDIOIST_IOINT BIT(0) | |
b4cff454 VB |
146 | |
147 | /* MMCSD Init clock in Hz in opendrain mode */ | |
148 | #define MMCSD_INIT_CLOCK 200000 | |
149 | ||
150 | /* | |
151 | * One scatterlist dma "segment" is at most MAX_CCNT rw_threshold units, | |
ca2afb6d | 152 | * and we handle up to MAX_NR_SG segments. MMC_BLOCK_BOUNCE kicks in only |
a36274e0 | 153 | * for drivers with max_segs == 1, making the segments bigger (64KB) |
ca2afb6d SR |
154 | * than the page or two that's otherwise typical. nr_sg (passed from |
155 | * platform data) == 16 gives at least the same throughput boost, using | |
156 | * EDMA transfer linkage instead of spending CPU time copying pages. | |
b4cff454 VB |
157 | */ |
158 | #define MAX_CCNT ((1 << 16) - 1) | |
159 | ||
ca2afb6d | 160 | #define MAX_NR_SG 16 |
b4cff454 VB |
161 | |
162 | static unsigned rw_threshold = 32; | |
163 | module_param(rw_threshold, uint, S_IRUGO); | |
164 | MODULE_PARM_DESC(rw_threshold, | |
165 | "Read/Write threshold. Default = 32"); | |
166 | ||
ee698f50 IY |
167 | static unsigned poll_threshold = 128; |
168 | module_param(poll_threshold, uint, S_IRUGO); | |
169 | MODULE_PARM_DESC(poll_threshold, | |
170 | "Polling transaction size threshold. Default = 128"); | |
171 | ||
172 | static unsigned poll_loopcount = 32; | |
173 | module_param(poll_loopcount, uint, S_IRUGO); | |
174 | MODULE_PARM_DESC(poll_loopcount, | |
175 | "Maximum polling loop count. Default = 32"); | |
176 | ||
b4cff454 VB |
177 | static unsigned __initdata use_dma = 1; |
178 | module_param(use_dma, uint, 0); | |
179 | MODULE_PARM_DESC(use_dma, "Whether to use DMA or not. Default = 1"); | |
180 | ||
181 | struct mmc_davinci_host { | |
182 | struct mmc_command *cmd; | |
183 | struct mmc_data *data; | |
184 | struct mmc_host *mmc; | |
185 | struct clk *clk; | |
186 | unsigned int mmc_input_clk; | |
187 | void __iomem *base; | |
188 | struct resource *mem_res; | |
f9db92cb | 189 | int mmc_irq, sdio_irq; |
b4cff454 VB |
190 | unsigned char bus_mode; |
191 | ||
192 | #define DAVINCI_MMC_DATADIR_NONE 0 | |
193 | #define DAVINCI_MMC_DATADIR_READ 1 | |
194 | #define DAVINCI_MMC_DATADIR_WRITE 2 | |
195 | unsigned char data_dir; | |
196 | ||
197 | /* buffer is used during PIO of one scatterlist segment, and | |
198 | * is updated along with buffer_bytes_left. bytes_left applies | |
199 | * to all N blocks of the PIO transfer. | |
200 | */ | |
201 | u8 *buffer; | |
202 | u32 buffer_bytes_left; | |
203 | u32 bytes_left; | |
204 | ||
5413da81 MP |
205 | struct dma_chan *dma_tx; |
206 | struct dma_chan *dma_rx; | |
b4cff454 VB |
207 | bool use_dma; |
208 | bool do_dma; | |
f9db92cb | 209 | bool sdio_int; |
ee698f50 | 210 | bool active_request; |
b4cff454 | 211 | |
b4cff454 VB |
212 | /* For PIO we walk scatterlists one segment at a time. */ |
213 | unsigned int sg_len; | |
214 | struct scatterlist *sg; | |
215 | ||
216 | /* Version of the MMC/SD controller */ | |
217 | u8 version; | |
218 | /* for ns in one cycle calculation */ | |
219 | unsigned ns_in_one_cycle; | |
ca2afb6d SR |
220 | /* Number of sg segments */ |
221 | u8 nr_sg; | |
7e30b8de C |
222 | #ifdef CONFIG_CPU_FREQ |
223 | struct notifier_block freq_transition; | |
224 | #endif | |
b4cff454 VB |
225 | }; |
226 | ||
ee698f50 | 227 | static irqreturn_t mmc_davinci_irq(int irq, void *dev_id); |
b4cff454 VB |
228 | |
229 | /* PIO only */ | |
230 | static void mmc_davinci_sg_to_buf(struct mmc_davinci_host *host) | |
231 | { | |
232 | host->buffer_bytes_left = sg_dma_len(host->sg); | |
233 | host->buffer = sg_virt(host->sg); | |
234 | if (host->buffer_bytes_left > host->bytes_left) | |
235 | host->buffer_bytes_left = host->bytes_left; | |
236 | } | |
237 | ||
238 | static void davinci_fifo_data_trans(struct mmc_davinci_host *host, | |
239 | unsigned int n) | |
240 | { | |
241 | u8 *p; | |
242 | unsigned int i; | |
243 | ||
244 | if (host->buffer_bytes_left == 0) { | |
245 | host->sg = sg_next(host->data->sg); | |
246 | mmc_davinci_sg_to_buf(host); | |
247 | } | |
248 | ||
249 | p = host->buffer; | |
250 | if (n > host->buffer_bytes_left) | |
251 | n = host->buffer_bytes_left; | |
252 | host->buffer_bytes_left -= n; | |
253 | host->bytes_left -= n; | |
254 | ||
255 | /* NOTE: we never transfer more than rw_threshold bytes | |
256 | * to/from the fifo here; there's no I/O overlap. | |
257 | * This also assumes that access width( i.e. ACCWD) is 4 bytes | |
258 | */ | |
259 | if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { | |
260 | for (i = 0; i < (n >> 2); i++) { | |
261 | writel(*((u32 *)p), host->base + DAVINCI_MMCDXR); | |
262 | p = p + 4; | |
263 | } | |
264 | if (n & 3) { | |
265 | iowrite8_rep(host->base + DAVINCI_MMCDXR, p, (n & 3)); | |
266 | p = p + (n & 3); | |
267 | } | |
268 | } else { | |
269 | for (i = 0; i < (n >> 2); i++) { | |
270 | *((u32 *)p) = readl(host->base + DAVINCI_MMCDRR); | |
271 | p = p + 4; | |
272 | } | |
273 | if (n & 3) { | |
274 | ioread8_rep(host->base + DAVINCI_MMCDRR, p, (n & 3)); | |
275 | p = p + (n & 3); | |
276 | } | |
277 | } | |
278 | host->buffer = p; | |
279 | } | |
280 | ||
281 | static void mmc_davinci_start_command(struct mmc_davinci_host *host, | |
282 | struct mmc_command *cmd) | |
283 | { | |
284 | u32 cmd_reg = 0; | |
285 | u32 im_val; | |
286 | ||
287 | dev_dbg(mmc_dev(host->mmc), "CMD%d, arg 0x%08x%s\n", | |
288 | cmd->opcode, cmd->arg, | |
289 | ({ char *s; | |
290 | switch (mmc_resp_type(cmd)) { | |
291 | case MMC_RSP_R1: | |
292 | s = ", R1/R5/R6/R7 response"; | |
293 | break; | |
294 | case MMC_RSP_R1B: | |
295 | s = ", R1b response"; | |
296 | break; | |
297 | case MMC_RSP_R2: | |
298 | s = ", R2 response"; | |
299 | break; | |
300 | case MMC_RSP_R3: | |
301 | s = ", R3/R4 response"; | |
302 | break; | |
303 | default: | |
304 | s = ", (R? response)"; | |
305 | break; | |
306 | }; s; })); | |
307 | host->cmd = cmd; | |
308 | ||
309 | switch (mmc_resp_type(cmd)) { | |
310 | case MMC_RSP_R1B: | |
311 | /* There's some spec confusion about when R1B is | |
312 | * allowed, but if the card doesn't issue a BUSY | |
313 | * then it's harmless for us to allow it. | |
314 | */ | |
315 | cmd_reg |= MMCCMD_BSYEXP; | |
316 | /* FALLTHROUGH */ | |
317 | case MMC_RSP_R1: /* 48 bits, CRC */ | |
318 | cmd_reg |= MMCCMD_RSPFMT_R1456; | |
319 | break; | |
320 | case MMC_RSP_R2: /* 136 bits, CRC */ | |
321 | cmd_reg |= MMCCMD_RSPFMT_R2; | |
322 | break; | |
323 | case MMC_RSP_R3: /* 48 bits, no CRC */ | |
324 | cmd_reg |= MMCCMD_RSPFMT_R3; | |
325 | break; | |
326 | default: | |
327 | cmd_reg |= MMCCMD_RSPFMT_NONE; | |
328 | dev_dbg(mmc_dev(host->mmc), "unknown resp_type %04x\n", | |
329 | mmc_resp_type(cmd)); | |
330 | break; | |
331 | } | |
332 | ||
333 | /* Set command index */ | |
334 | cmd_reg |= cmd->opcode; | |
335 | ||
336 | /* Enable EDMA transfer triggers */ | |
337 | if (host->do_dma) | |
338 | cmd_reg |= MMCCMD_DMATRIG; | |
339 | ||
340 | if (host->version == MMC_CTLR_VERSION_2 && host->data != NULL && | |
341 | host->data_dir == DAVINCI_MMC_DATADIR_READ) | |
342 | cmd_reg |= MMCCMD_DMATRIG; | |
343 | ||
344 | /* Setting whether command involves data transfer or not */ | |
345 | if (cmd->data) | |
346 | cmd_reg |= MMCCMD_WDATX; | |
347 | ||
b4cff454 VB |
348 | /* Setting whether data read or write */ |
349 | if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) | |
350 | cmd_reg |= MMCCMD_DTRW; | |
351 | ||
352 | if (host->bus_mode == MMC_BUSMODE_PUSHPULL) | |
353 | cmd_reg |= MMCCMD_PPLEN; | |
354 | ||
355 | /* set Command timeout */ | |
356 | writel(0x1FFF, host->base + DAVINCI_MMCTOR); | |
357 | ||
358 | /* Enable interrupt (calculate here, defer until FIFO is stuffed). */ | |
359 | im_val = MMCST0_RSPDNE | MMCST0_CRCRS | MMCST0_TOUTRS; | |
360 | if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { | |
361 | im_val |= MMCST0_DATDNE | MMCST0_CRCWR; | |
362 | ||
363 | if (!host->do_dma) | |
364 | im_val |= MMCST0_DXRDY; | |
365 | } else if (host->data_dir == DAVINCI_MMC_DATADIR_READ) { | |
366 | im_val |= MMCST0_DATDNE | MMCST0_CRCRD | MMCST0_TOUTRD; | |
367 | ||
368 | if (!host->do_dma) | |
369 | im_val |= MMCST0_DRRDY; | |
370 | } | |
371 | ||
372 | /* | |
373 | * Before non-DMA WRITE commands the controller needs priming: | |
374 | * FIFO should be populated with 32 bytes i.e. whatever is the FIFO size | |
375 | */ | |
376 | if (!host->do_dma && (host->data_dir == DAVINCI_MMC_DATADIR_WRITE)) | |
377 | davinci_fifo_data_trans(host, rw_threshold); | |
378 | ||
379 | writel(cmd->arg, host->base + DAVINCI_MMCARGHL); | |
380 | writel(cmd_reg, host->base + DAVINCI_MMCCMD); | |
ee698f50 IY |
381 | |
382 | host->active_request = true; | |
383 | ||
384 | if (!host->do_dma && host->bytes_left <= poll_threshold) { | |
385 | u32 count = poll_loopcount; | |
386 | ||
387 | while (host->active_request && count--) { | |
388 | mmc_davinci_irq(0, host); | |
389 | cpu_relax(); | |
390 | } | |
391 | } | |
392 | ||
393 | if (host->active_request) | |
394 | writel(im_val, host->base + DAVINCI_MMCIM); | |
b4cff454 VB |
395 | } |
396 | ||
397 | /*----------------------------------------------------------------------*/ | |
398 | ||
399 | /* DMA infrastructure */ | |
400 | ||
401 | static void davinci_abort_dma(struct mmc_davinci_host *host) | |
402 | { | |
5413da81 | 403 | struct dma_chan *sync_dev; |
b4cff454 VB |
404 | |
405 | if (host->data_dir == DAVINCI_MMC_DATADIR_READ) | |
5413da81 | 406 | sync_dev = host->dma_rx; |
b4cff454 | 407 | else |
5413da81 | 408 | sync_dev = host->dma_tx; |
b4cff454 | 409 | |
5413da81 | 410 | dmaengine_terminate_all(sync_dev); |
b4cff454 VB |
411 | } |
412 | ||
5413da81 | 413 | static int mmc_davinci_send_dma_request(struct mmc_davinci_host *host, |
b4cff454 VB |
414 | struct mmc_data *data) |
415 | { | |
5413da81 MP |
416 | struct dma_chan *chan; |
417 | struct dma_async_tx_descriptor *desc; | |
418 | int ret = 0; | |
b4cff454 VB |
419 | |
420 | if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { | |
5413da81 MP |
421 | struct dma_slave_config dma_tx_conf = { |
422 | .direction = DMA_MEM_TO_DEV, | |
423 | .dst_addr = host->mem_res->start + DAVINCI_MMCDXR, | |
424 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, | |
425 | .dst_maxburst = | |
426 | rw_threshold / DMA_SLAVE_BUSWIDTH_4_BYTES, | |
427 | }; | |
428 | chan = host->dma_tx; | |
429 | dmaengine_slave_config(host->dma_tx, &dma_tx_conf); | |
430 | ||
431 | desc = dmaengine_prep_slave_sg(host->dma_tx, | |
432 | data->sg, | |
433 | host->sg_len, | |
434 | DMA_MEM_TO_DEV, | |
435 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
436 | if (!desc) { | |
437 | dev_dbg(mmc_dev(host->mmc), | |
438 | "failed to allocate DMA TX descriptor"); | |
439 | ret = -1; | |
440 | goto out; | |
441 | } | |
b4cff454 | 442 | } else { |
5413da81 MP |
443 | struct dma_slave_config dma_rx_conf = { |
444 | .direction = DMA_DEV_TO_MEM, | |
445 | .src_addr = host->mem_res->start + DAVINCI_MMCDRR, | |
446 | .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, | |
447 | .src_maxburst = | |
448 | rw_threshold / DMA_SLAVE_BUSWIDTH_4_BYTES, | |
449 | }; | |
450 | chan = host->dma_rx; | |
451 | dmaengine_slave_config(host->dma_rx, &dma_rx_conf); | |
452 | ||
453 | desc = dmaengine_prep_slave_sg(host->dma_rx, | |
454 | data->sg, | |
455 | host->sg_len, | |
456 | DMA_DEV_TO_MEM, | |
457 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
458 | if (!desc) { | |
459 | dev_dbg(mmc_dev(host->mmc), | |
460 | "failed to allocate DMA RX descriptor"); | |
461 | ret = -1; | |
462 | goto out; | |
463 | } | |
b4cff454 VB |
464 | } |
465 | ||
5413da81 MP |
466 | dmaengine_submit(desc); |
467 | dma_async_issue_pending(chan); | |
b4cff454 | 468 | |
5413da81 MP |
469 | out: |
470 | return ret; | |
b4cff454 VB |
471 | } |
472 | ||
473 | static int mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host, | |
474 | struct mmc_data *data) | |
475 | { | |
476 | int i; | |
477 | int mask = rw_threshold - 1; | |
5413da81 | 478 | int ret = 0; |
b4cff454 VB |
479 | |
480 | host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, | |
feeef096 | 481 | mmc_get_dma_dir(data)); |
b4cff454 VB |
482 | |
483 | /* no individual DMA segment should need a partial FIFO */ | |
484 | for (i = 0; i < host->sg_len; i++) { | |
485 | if (sg_dma_len(data->sg + i) & mask) { | |
486 | dma_unmap_sg(mmc_dev(host->mmc), | |
feeef096 HK |
487 | data->sg, data->sg_len, |
488 | mmc_get_dma_dir(data)); | |
b4cff454 VB |
489 | return -1; |
490 | } | |
491 | } | |
492 | ||
493 | host->do_dma = 1; | |
5413da81 | 494 | ret = mmc_davinci_send_dma_request(host, data); |
b4cff454 | 495 | |
5413da81 | 496 | return ret; |
b4cff454 VB |
497 | } |
498 | ||
499 | static void __init_or_module | |
500 | davinci_release_dma_channels(struct mmc_davinci_host *host) | |
501 | { | |
b4cff454 VB |
502 | if (!host->use_dma) |
503 | return; | |
504 | ||
5413da81 MP |
505 | dma_release_channel(host->dma_tx); |
506 | dma_release_channel(host->dma_rx); | |
b4cff454 VB |
507 | } |
508 | ||
509 | static int __init davinci_acquire_dma_channels(struct mmc_davinci_host *host) | |
510 | { | |
0a4d7236 PU |
511 | host->dma_tx = dma_request_chan(mmc_dev(host->mmc), "tx"); |
512 | if (IS_ERR(host->dma_tx)) { | |
5413da81 | 513 | dev_err(mmc_dev(host->mmc), "Can't get dma_tx channel\n"); |
0a4d7236 | 514 | return PTR_ERR(host->dma_tx); |
b4cff454 | 515 | } |
b4cff454 | 516 | |
0a4d7236 PU |
517 | host->dma_rx = dma_request_chan(mmc_dev(host->mmc), "rx"); |
518 | if (IS_ERR(host->dma_rx)) { | |
5413da81 | 519 | dev_err(mmc_dev(host->mmc), "Can't get dma_rx channel\n"); |
0a4d7236 PU |
520 | dma_release_channel(host->dma_tx); |
521 | return PTR_ERR(host->dma_rx); | |
b4cff454 | 522 | } |
b4cff454 VB |
523 | |
524 | return 0; | |
b4cff454 VB |
525 | } |
526 | ||
527 | /*----------------------------------------------------------------------*/ | |
528 | ||
529 | static void | |
530 | mmc_davinci_prepare_data(struct mmc_davinci_host *host, struct mmc_request *req) | |
531 | { | |
532 | int fifo_lev = (rw_threshold == 32) ? MMCFIFOCTL_FIFOLEV : 0; | |
533 | int timeout; | |
534 | struct mmc_data *data = req->data; | |
535 | ||
536 | if (host->version == MMC_CTLR_VERSION_2) | |
537 | fifo_lev = (rw_threshold == 64) ? MMCFIFOCTL_FIFOLEV : 0; | |
538 | ||
539 | host->data = data; | |
540 | if (data == NULL) { | |
541 | host->data_dir = DAVINCI_MMC_DATADIR_NONE; | |
542 | writel(0, host->base + DAVINCI_MMCBLEN); | |
543 | writel(0, host->base + DAVINCI_MMCNBLK); | |
544 | return; | |
545 | } | |
546 | ||
bbb66fcb | 547 | dev_dbg(mmc_dev(host->mmc), "%s, %d blocks of %d bytes\n", |
b4cff454 VB |
548 | (data->flags & MMC_DATA_WRITE) ? "write" : "read", |
549 | data->blocks, data->blksz); | |
550 | dev_dbg(mmc_dev(host->mmc), " DTO %d cycles + %d ns\n", | |
551 | data->timeout_clks, data->timeout_ns); | |
552 | timeout = data->timeout_clks + | |
553 | (data->timeout_ns / host->ns_in_one_cycle); | |
554 | if (timeout > 0xffff) | |
555 | timeout = 0xffff; | |
556 | ||
557 | writel(timeout, host->base + DAVINCI_MMCTOD); | |
558 | writel(data->blocks, host->base + DAVINCI_MMCNBLK); | |
559 | writel(data->blksz, host->base + DAVINCI_MMCBLEN); | |
560 | ||
561 | /* Configure the FIFO */ | |
bbb66fcb | 562 | if (data->flags & MMC_DATA_WRITE) { |
b4cff454 VB |
563 | host->data_dir = DAVINCI_MMC_DATADIR_WRITE; |
564 | writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR | MMCFIFOCTL_FIFORST, | |
565 | host->base + DAVINCI_MMCFIFOCTL); | |
566 | writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR, | |
567 | host->base + DAVINCI_MMCFIFOCTL); | |
bbb66fcb | 568 | } else { |
b4cff454 VB |
569 | host->data_dir = DAVINCI_MMC_DATADIR_READ; |
570 | writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD | MMCFIFOCTL_FIFORST, | |
571 | host->base + DAVINCI_MMCFIFOCTL); | |
572 | writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD, | |
573 | host->base + DAVINCI_MMCFIFOCTL); | |
b4cff454 VB |
574 | } |
575 | ||
576 | host->buffer = NULL; | |
577 | host->bytes_left = data->blocks * data->blksz; | |
578 | ||
579 | /* For now we try to use DMA whenever we won't need partial FIFO | |
580 | * reads or writes, either for the whole transfer (as tested here) | |
581 | * or for any individual scatterlist segment (tested when we call | |
582 | * start_dma_transfer). | |
583 | * | |
584 | * While we *could* change that, unusual block sizes are rarely | |
585 | * used. The occasional fallback to PIO should't hurt. | |
586 | */ | |
587 | if (host->use_dma && (host->bytes_left & (rw_threshold - 1)) == 0 | |
588 | && mmc_davinci_start_dma_transfer(host, data) == 0) { | |
589 | /* zero this to ensure we take no PIO paths */ | |
590 | host->bytes_left = 0; | |
591 | } else { | |
592 | /* Revert to CPU Copy */ | |
593 | host->sg_len = data->sg_len; | |
594 | host->sg = host->data->sg; | |
595 | mmc_davinci_sg_to_buf(host); | |
596 | } | |
597 | } | |
598 | ||
599 | static void mmc_davinci_request(struct mmc_host *mmc, struct mmc_request *req) | |
600 | { | |
601 | struct mmc_davinci_host *host = mmc_priv(mmc); | |
602 | unsigned long timeout = jiffies + msecs_to_jiffies(900); | |
603 | u32 mmcst1 = 0; | |
604 | ||
605 | /* Card may still be sending BUSY after a previous operation, | |
606 | * typically some kind of write. If so, we can't proceed yet. | |
607 | */ | |
608 | while (time_before(jiffies, timeout)) { | |
609 | mmcst1 = readl(host->base + DAVINCI_MMCST1); | |
610 | if (!(mmcst1 & MMCST1_BUSY)) | |
611 | break; | |
612 | cpu_relax(); | |
613 | } | |
614 | if (mmcst1 & MMCST1_BUSY) { | |
615 | dev_err(mmc_dev(host->mmc), "still BUSY? bad ... \n"); | |
616 | req->cmd->error = -ETIMEDOUT; | |
617 | mmc_request_done(mmc, req); | |
618 | return; | |
619 | } | |
620 | ||
621 | host->do_dma = 0; | |
622 | mmc_davinci_prepare_data(host, req); | |
623 | mmc_davinci_start_command(host, req->cmd); | |
624 | } | |
625 | ||
626 | static unsigned int calculate_freq_for_card(struct mmc_davinci_host *host, | |
627 | unsigned int mmc_req_freq) | |
628 | { | |
629 | unsigned int mmc_freq = 0, mmc_pclk = 0, mmc_push_pull_divisor = 0; | |
630 | ||
631 | mmc_pclk = host->mmc_input_clk; | |
632 | if (mmc_req_freq && mmc_pclk > (2 * mmc_req_freq)) | |
633 | mmc_push_pull_divisor = ((unsigned int)mmc_pclk | |
634 | / (2 * mmc_req_freq)) - 1; | |
635 | else | |
636 | mmc_push_pull_divisor = 0; | |
637 | ||
638 | mmc_freq = (unsigned int)mmc_pclk | |
639 | / (2 * (mmc_push_pull_divisor + 1)); | |
640 | ||
641 | if (mmc_freq > mmc_req_freq) | |
642 | mmc_push_pull_divisor = mmc_push_pull_divisor + 1; | |
643 | /* Convert ns to clock cycles */ | |
644 | if (mmc_req_freq <= 400000) | |
645 | host->ns_in_one_cycle = (1000000) / (((mmc_pclk | |
646 | / (2 * (mmc_push_pull_divisor + 1)))/1000)); | |
647 | else | |
648 | host->ns_in_one_cycle = (1000000) / (((mmc_pclk | |
649 | / (2 * (mmc_push_pull_divisor + 1)))/1000000)); | |
650 | ||
651 | return mmc_push_pull_divisor; | |
652 | } | |
653 | ||
7e30b8de | 654 | static void calculate_clk_divider(struct mmc_host *mmc, struct mmc_ios *ios) |
b4cff454 VB |
655 | { |
656 | unsigned int open_drain_freq = 0, mmc_pclk = 0; | |
657 | unsigned int mmc_push_pull_freq = 0; | |
658 | struct mmc_davinci_host *host = mmc_priv(mmc); | |
659 | ||
b4cff454 VB |
660 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { |
661 | u32 temp; | |
662 | ||
663 | /* Ignoring the init clock value passed for fixing the inter | |
664 | * operability with different cards. | |
665 | */ | |
666 | open_drain_freq = ((unsigned int)mmc_pclk | |
667 | / (2 * MMCSD_INIT_CLOCK)) - 1; | |
668 | ||
669 | if (open_drain_freq > 0xFF) | |
670 | open_drain_freq = 0xFF; | |
671 | ||
672 | temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK; | |
673 | temp |= open_drain_freq; | |
674 | writel(temp, host->base + DAVINCI_MMCCLK); | |
675 | ||
676 | /* Convert ns to clock cycles */ | |
677 | host->ns_in_one_cycle = (1000000) / (MMCSD_INIT_CLOCK/1000); | |
678 | } else { | |
679 | u32 temp; | |
680 | mmc_push_pull_freq = calculate_freq_for_card(host, ios->clock); | |
681 | ||
682 | if (mmc_push_pull_freq > 0xFF) | |
683 | mmc_push_pull_freq = 0xFF; | |
684 | ||
685 | temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKEN; | |
686 | writel(temp, host->base + DAVINCI_MMCCLK); | |
687 | ||
688 | udelay(10); | |
689 | ||
690 | temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK; | |
691 | temp |= mmc_push_pull_freq; | |
692 | writel(temp, host->base + DAVINCI_MMCCLK); | |
693 | ||
694 | writel(temp | MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK); | |
695 | ||
696 | udelay(10); | |
697 | } | |
7e30b8de C |
698 | } |
699 | ||
700 | static void mmc_davinci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
701 | { | |
7e30b8de | 702 | struct mmc_davinci_host *host = mmc_priv(mmc); |
4a9de8ad IY |
703 | struct platform_device *pdev = to_platform_device(mmc->parent); |
704 | struct davinci_mmc_config *config = pdev->dev.platform_data; | |
7e30b8de | 705 | |
7e30b8de C |
706 | dev_dbg(mmc_dev(host->mmc), |
707 | "clock %dHz busmode %d powermode %d Vdd %04x\n", | |
708 | ios->clock, ios->bus_mode, ios->power_mode, | |
709 | ios->vdd); | |
132f1074 | 710 | |
4a9de8ad IY |
711 | switch (ios->power_mode) { |
712 | case MMC_POWER_OFF: | |
713 | if (config && config->set_power) | |
714 | config->set_power(pdev->id, false); | |
715 | break; | |
716 | case MMC_POWER_UP: | |
717 | if (config && config->set_power) | |
718 | config->set_power(pdev->id, true); | |
719 | break; | |
720 | } | |
721 | ||
132f1074 VB |
722 | switch (ios->bus_width) { |
723 | case MMC_BUS_WIDTH_8: | |
724 | dev_dbg(mmc_dev(host->mmc), "Enabling 8 bit mode\n"); | |
725 | writel((readl(host->base + DAVINCI_MMCCTL) & | |
726 | ~MMCCTL_WIDTH_4_BIT) | MMCCTL_WIDTH_8_BIT, | |
7e30b8de | 727 | host->base + DAVINCI_MMCCTL); |
132f1074 VB |
728 | break; |
729 | case MMC_BUS_WIDTH_4: | |
730 | dev_dbg(mmc_dev(host->mmc), "Enabling 4 bit mode\n"); | |
731 | if (host->version == MMC_CTLR_VERSION_2) | |
732 | writel((readl(host->base + DAVINCI_MMCCTL) & | |
733 | ~MMCCTL_WIDTH_8_BIT) | MMCCTL_WIDTH_4_BIT, | |
734 | host->base + DAVINCI_MMCCTL); | |
735 | else | |
736 | writel(readl(host->base + DAVINCI_MMCCTL) | | |
737 | MMCCTL_WIDTH_4_BIT, | |
738 | host->base + DAVINCI_MMCCTL); | |
739 | break; | |
740 | case MMC_BUS_WIDTH_1: | |
741 | dev_dbg(mmc_dev(host->mmc), "Enabling 1 bit mode\n"); | |
742 | if (host->version == MMC_CTLR_VERSION_2) | |
743 | writel(readl(host->base + DAVINCI_MMCCTL) & | |
744 | ~(MMCCTL_WIDTH_8_BIT | MMCCTL_WIDTH_4_BIT), | |
745 | host->base + DAVINCI_MMCCTL); | |
746 | else | |
747 | writel(readl(host->base + DAVINCI_MMCCTL) & | |
748 | ~MMCCTL_WIDTH_4_BIT, | |
749 | host->base + DAVINCI_MMCCTL); | |
750 | break; | |
7e30b8de C |
751 | } |
752 | ||
753 | calculate_clk_divider(mmc, ios); | |
b4cff454 VB |
754 | |
755 | host->bus_mode = ios->bus_mode; | |
756 | if (ios->power_mode == MMC_POWER_UP) { | |
757 | unsigned long timeout = jiffies + msecs_to_jiffies(50); | |
758 | bool lose = true; | |
759 | ||
760 | /* Send clock cycles, poll completion */ | |
761 | writel(0, host->base + DAVINCI_MMCARGHL); | |
762 | writel(MMCCMD_INITCK, host->base + DAVINCI_MMCCMD); | |
763 | while (time_before(jiffies, timeout)) { | |
764 | u32 tmp = readl(host->base + DAVINCI_MMCST0); | |
765 | ||
766 | if (tmp & MMCST0_RSPDNE) { | |
767 | lose = false; | |
768 | break; | |
769 | } | |
770 | cpu_relax(); | |
771 | } | |
772 | if (lose) | |
773 | dev_warn(mmc_dev(host->mmc), "powerup timeout\n"); | |
774 | } | |
775 | ||
776 | /* FIXME on power OFF, reset things ... */ | |
777 | } | |
778 | ||
779 | static void | |
780 | mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data) | |
781 | { | |
782 | host->data = NULL; | |
783 | ||
f9db92cb AS |
784 | if (host->mmc->caps & MMC_CAP_SDIO_IRQ) { |
785 | /* | |
786 | * SDIO Interrupt Detection work-around as suggested by | |
787 | * Davinci Errata (TMS320DM355 Silicon Revision 1.1 Errata | |
788 | * 2.1.6): Signal SDIO interrupt only if it is enabled by core | |
789 | */ | |
790 | if (host->sdio_int && !(readl(host->base + DAVINCI_SDIOST0) & | |
791 | SDIOST0_DAT1_HI)) { | |
792 | writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); | |
793 | mmc_signal_sdio_irq(host->mmc); | |
794 | } | |
795 | } | |
796 | ||
b4cff454 VB |
797 | if (host->do_dma) { |
798 | davinci_abort_dma(host); | |
799 | ||
800 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, | |
feeef096 | 801 | mmc_get_dma_dir(data)); |
b4cff454 VB |
802 | host->do_dma = false; |
803 | } | |
804 | host->data_dir = DAVINCI_MMC_DATADIR_NONE; | |
805 | ||
806 | if (!data->stop || (host->cmd && host->cmd->error)) { | |
807 | mmc_request_done(host->mmc, data->mrq); | |
808 | writel(0, host->base + DAVINCI_MMCIM); | |
ee698f50 | 809 | host->active_request = false; |
b4cff454 VB |
810 | } else |
811 | mmc_davinci_start_command(host, data->stop); | |
812 | } | |
813 | ||
814 | static void mmc_davinci_cmd_done(struct mmc_davinci_host *host, | |
815 | struct mmc_command *cmd) | |
816 | { | |
817 | host->cmd = NULL; | |
818 | ||
819 | if (cmd->flags & MMC_RSP_PRESENT) { | |
820 | if (cmd->flags & MMC_RSP_136) { | |
821 | /* response type 2 */ | |
822 | cmd->resp[3] = readl(host->base + DAVINCI_MMCRSP01); | |
823 | cmd->resp[2] = readl(host->base + DAVINCI_MMCRSP23); | |
824 | cmd->resp[1] = readl(host->base + DAVINCI_MMCRSP45); | |
825 | cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67); | |
826 | } else { | |
827 | /* response types 1, 1b, 3, 4, 5, 6 */ | |
828 | cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67); | |
829 | } | |
830 | } | |
831 | ||
832 | if (host->data == NULL || cmd->error) { | |
833 | if (cmd->error == -ETIMEDOUT) | |
834 | cmd->mrq->cmd->retries = 0; | |
835 | mmc_request_done(host->mmc, cmd->mrq); | |
836 | writel(0, host->base + DAVINCI_MMCIM); | |
ee698f50 | 837 | host->active_request = false; |
b4cff454 VB |
838 | } |
839 | } | |
840 | ||
06de845f C |
841 | static inline void mmc_davinci_reset_ctrl(struct mmc_davinci_host *host, |
842 | int val) | |
b4cff454 VB |
843 | { |
844 | u32 temp; | |
845 | ||
b4cff454 | 846 | temp = readl(host->base + DAVINCI_MMCCTL); |
06de845f C |
847 | if (val) /* reset */ |
848 | temp |= MMCCTL_CMDRST | MMCCTL_DATRST; | |
849 | else /* enable */ | |
850 | temp &= ~(MMCCTL_CMDRST | MMCCTL_DATRST); | |
b4cff454 | 851 | |
b4cff454 | 852 | writel(temp, host->base + DAVINCI_MMCCTL); |
06de845f C |
853 | udelay(10); |
854 | } | |
855 | ||
856 | static void | |
857 | davinci_abort_data(struct mmc_davinci_host *host, struct mmc_data *data) | |
858 | { | |
859 | mmc_davinci_reset_ctrl(host, 1); | |
860 | mmc_davinci_reset_ctrl(host, 0); | |
b4cff454 VB |
861 | } |
862 | ||
f9db92cb AS |
863 | static irqreturn_t mmc_davinci_sdio_irq(int irq, void *dev_id) |
864 | { | |
865 | struct mmc_davinci_host *host = dev_id; | |
866 | unsigned int status; | |
867 | ||
868 | status = readl(host->base + DAVINCI_SDIOIST); | |
869 | if (status & SDIOIST_IOINT) { | |
870 | dev_dbg(mmc_dev(host->mmc), | |
871 | "SDIO interrupt status %x\n", status); | |
872 | writel(status | SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); | |
873 | mmc_signal_sdio_irq(host->mmc); | |
874 | } | |
875 | return IRQ_HANDLED; | |
876 | } | |
877 | ||
b4cff454 VB |
878 | static irqreturn_t mmc_davinci_irq(int irq, void *dev_id) |
879 | { | |
880 | struct mmc_davinci_host *host = (struct mmc_davinci_host *)dev_id; | |
881 | unsigned int status, qstatus; | |
882 | int end_command = 0; | |
883 | int end_transfer = 0; | |
884 | struct mmc_data *data = host->data; | |
885 | ||
886 | if (host->cmd == NULL && host->data == NULL) { | |
887 | status = readl(host->base + DAVINCI_MMCST0); | |
888 | dev_dbg(mmc_dev(host->mmc), | |
889 | "Spurious interrupt 0x%04x\n", status); | |
890 | /* Disable the interrupt from mmcsd */ | |
891 | writel(0, host->base + DAVINCI_MMCIM); | |
892 | return IRQ_NONE; | |
893 | } | |
894 | ||
895 | status = readl(host->base + DAVINCI_MMCST0); | |
896 | qstatus = status; | |
897 | ||
898 | /* handle FIFO first when using PIO for data. | |
899 | * bytes_left will decrease to zero as I/O progress and status will | |
900 | * read zero over iteration because this controller status | |
901 | * register(MMCST0) reports any status only once and it is cleared | |
902 | * by read. So, it is not unbouned loop even in the case of | |
903 | * non-dma. | |
904 | */ | |
be7b5622 IY |
905 | if (host->bytes_left && (status & (MMCST0_DXRDY | MMCST0_DRRDY))) { |
906 | unsigned long im_val; | |
907 | ||
908 | /* | |
909 | * If interrupts fire during the following loop, they will be | |
910 | * handled by the handler, but the PIC will still buffer these. | |
911 | * As a result, the handler will be called again to serve these | |
912 | * needlessly. In order to avoid these spurious interrupts, | |
913 | * keep interrupts masked during the loop. | |
914 | */ | |
915 | im_val = readl(host->base + DAVINCI_MMCIM); | |
916 | writel(0, host->base + DAVINCI_MMCIM); | |
917 | ||
918 | do { | |
919 | davinci_fifo_data_trans(host, rw_threshold); | |
920 | status = readl(host->base + DAVINCI_MMCST0); | |
921 | qstatus |= status; | |
922 | } while (host->bytes_left && | |
923 | (status & (MMCST0_DXRDY | MMCST0_DRRDY))); | |
924 | ||
925 | /* | |
926 | * If an interrupt is pending, it is assumed it will fire when | |
927 | * it is unmasked. This assumption is also taken when the MMCIM | |
928 | * is first set. Otherwise, writing to MMCIM after reading the | |
929 | * status is race-prone. | |
930 | */ | |
931 | writel(im_val, host->base + DAVINCI_MMCIM); | |
b4cff454 VB |
932 | } |
933 | ||
934 | if (qstatus & MMCST0_DATDNE) { | |
935 | /* All blocks sent/received, and CRC checks passed */ | |
936 | if (data != NULL) { | |
937 | if ((host->do_dma == 0) && (host->bytes_left > 0)) { | |
938 | /* if datasize < rw_threshold | |
939 | * no RX ints are generated | |
940 | */ | |
941 | davinci_fifo_data_trans(host, host->bytes_left); | |
942 | } | |
943 | end_transfer = 1; | |
944 | data->bytes_xfered = data->blocks * data->blksz; | |
945 | } else { | |
946 | dev_err(mmc_dev(host->mmc), | |
947 | "DATDNE with no host->data\n"); | |
948 | } | |
949 | } | |
950 | ||
951 | if (qstatus & MMCST0_TOUTRD) { | |
952 | /* Read data timeout */ | |
953 | data->error = -ETIMEDOUT; | |
954 | end_transfer = 1; | |
955 | ||
956 | dev_dbg(mmc_dev(host->mmc), | |
957 | "read data timeout, status %x\n", | |
958 | qstatus); | |
959 | ||
960 | davinci_abort_data(host, data); | |
961 | } | |
962 | ||
963 | if (qstatus & (MMCST0_CRCWR | MMCST0_CRCRD)) { | |
964 | /* Data CRC error */ | |
965 | data->error = -EILSEQ; | |
966 | end_transfer = 1; | |
967 | ||
968 | /* NOTE: this controller uses CRCWR to report both CRC | |
969 | * errors and timeouts (on writes). MMCDRSP values are | |
970 | * only weakly documented, but 0x9f was clearly a timeout | |
971 | * case and the two three-bit patterns in various SD specs | |
972 | * (101, 010) aren't part of it ... | |
973 | */ | |
974 | if (qstatus & MMCST0_CRCWR) { | |
975 | u32 temp = readb(host->base + DAVINCI_MMCDRSP); | |
976 | ||
977 | if (temp == 0x9f) | |
978 | data->error = -ETIMEDOUT; | |
979 | } | |
980 | dev_dbg(mmc_dev(host->mmc), "data %s %s error\n", | |
981 | (qstatus & MMCST0_CRCWR) ? "write" : "read", | |
982 | (data->error == -ETIMEDOUT) ? "timeout" : "CRC"); | |
983 | ||
984 | davinci_abort_data(host, data); | |
985 | } | |
986 | ||
987 | if (qstatus & MMCST0_TOUTRS) { | |
988 | /* Command timeout */ | |
989 | if (host->cmd) { | |
990 | dev_dbg(mmc_dev(host->mmc), | |
991 | "CMD%d timeout, status %x\n", | |
992 | host->cmd->opcode, qstatus); | |
993 | host->cmd->error = -ETIMEDOUT; | |
994 | if (data) { | |
995 | end_transfer = 1; | |
996 | davinci_abort_data(host, data); | |
997 | } else | |
998 | end_command = 1; | |
999 | } | |
1000 | } | |
1001 | ||
1002 | if (qstatus & MMCST0_CRCRS) { | |
1003 | /* Command CRC error */ | |
1004 | dev_dbg(mmc_dev(host->mmc), "Command CRC error\n"); | |
1005 | if (host->cmd) { | |
1006 | host->cmd->error = -EILSEQ; | |
1007 | end_command = 1; | |
1008 | } | |
1009 | } | |
1010 | ||
1011 | if (qstatus & MMCST0_RSPDNE) { | |
1012 | /* End of command phase */ | |
1013 | end_command = (int) host->cmd; | |
1014 | } | |
1015 | ||
1016 | if (end_command) | |
1017 | mmc_davinci_cmd_done(host, host->cmd); | |
1018 | if (end_transfer) | |
1019 | mmc_davinci_xfer_done(host, data); | |
1020 | return IRQ_HANDLED; | |
1021 | } | |
1022 | ||
1023 | static int mmc_davinci_get_cd(struct mmc_host *mmc) | |
1024 | { | |
1025 | struct platform_device *pdev = to_platform_device(mmc->parent); | |
1026 | struct davinci_mmc_config *config = pdev->dev.platform_data; | |
1027 | ||
c8301e79 | 1028 | if (config && config->get_cd) |
1029 | return config->get_cd(pdev->id); | |
1030 | ||
1031 | return mmc_gpio_get_cd(mmc); | |
b4cff454 VB |
1032 | } |
1033 | ||
1034 | static int mmc_davinci_get_ro(struct mmc_host *mmc) | |
1035 | { | |
1036 | struct platform_device *pdev = to_platform_device(mmc->parent); | |
1037 | struct davinci_mmc_config *config = pdev->dev.platform_data; | |
1038 | ||
c8301e79 | 1039 | if (config && config->get_ro) |
1040 | return config->get_ro(pdev->id); | |
1041 | ||
1042 | return mmc_gpio_get_ro(mmc); | |
b4cff454 VB |
1043 | } |
1044 | ||
f9db92cb AS |
1045 | static void mmc_davinci_enable_sdio_irq(struct mmc_host *mmc, int enable) |
1046 | { | |
1047 | struct mmc_davinci_host *host = mmc_priv(mmc); | |
1048 | ||
1049 | if (enable) { | |
1050 | if (!(readl(host->base + DAVINCI_SDIOST0) & SDIOST0_DAT1_HI)) { | |
1051 | writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); | |
1052 | mmc_signal_sdio_irq(host->mmc); | |
1053 | } else { | |
1054 | host->sdio_int = true; | |
1055 | writel(readl(host->base + DAVINCI_SDIOIEN) | | |
1056 | SDIOIEN_IOINTEN, host->base + DAVINCI_SDIOIEN); | |
1057 | } | |
1058 | } else { | |
1059 | host->sdio_int = false; | |
1060 | writel(readl(host->base + DAVINCI_SDIOIEN) & ~SDIOIEN_IOINTEN, | |
1061 | host->base + DAVINCI_SDIOIEN); | |
1062 | } | |
1063 | } | |
1064 | ||
2463941f | 1065 | static const struct mmc_host_ops mmc_davinci_ops = { |
b4cff454 VB |
1066 | .request = mmc_davinci_request, |
1067 | .set_ios = mmc_davinci_set_ios, | |
1068 | .get_cd = mmc_davinci_get_cd, | |
1069 | .get_ro = mmc_davinci_get_ro, | |
f9db92cb | 1070 | .enable_sdio_irq = mmc_davinci_enable_sdio_irq, |
b4cff454 VB |
1071 | }; |
1072 | ||
1073 | /*----------------------------------------------------------------------*/ | |
1074 | ||
7e30b8de C |
1075 | #ifdef CONFIG_CPU_FREQ |
1076 | static int mmc_davinci_cpufreq_transition(struct notifier_block *nb, | |
1077 | unsigned long val, void *data) | |
1078 | { | |
1079 | struct mmc_davinci_host *host; | |
1080 | unsigned int mmc_pclk; | |
1081 | struct mmc_host *mmc; | |
1082 | unsigned long flags; | |
1083 | ||
1084 | host = container_of(nb, struct mmc_davinci_host, freq_transition); | |
1085 | mmc = host->mmc; | |
1086 | mmc_pclk = clk_get_rate(host->clk); | |
1087 | ||
1088 | if (val == CPUFREQ_POSTCHANGE) { | |
1089 | spin_lock_irqsave(&mmc->lock, flags); | |
1090 | host->mmc_input_clk = mmc_pclk; | |
1091 | calculate_clk_divider(mmc, &mmc->ios); | |
1092 | spin_unlock_irqrestore(&mmc->lock, flags); | |
1093 | } | |
1094 | ||
1095 | return 0; | |
1096 | } | |
1097 | ||
1098 | static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host) | |
1099 | { | |
1100 | host->freq_transition.notifier_call = mmc_davinci_cpufreq_transition; | |
1101 | ||
1102 | return cpufreq_register_notifier(&host->freq_transition, | |
1103 | CPUFREQ_TRANSITION_NOTIFIER); | |
1104 | } | |
1105 | ||
1106 | static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host) | |
1107 | { | |
1108 | cpufreq_unregister_notifier(&host->freq_transition, | |
1109 | CPUFREQ_TRANSITION_NOTIFIER); | |
1110 | } | |
1111 | #else | |
1112 | static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host) | |
1113 | { | |
1114 | return 0; | |
1115 | } | |
1116 | ||
1117 | static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host) | |
1118 | { | |
1119 | } | |
1120 | #endif | |
eebec30d | 1121 | static void init_mmcsd_host(struct mmc_davinci_host *host) |
b4cff454 | 1122 | { |
b4cff454 | 1123 | |
06de845f | 1124 | mmc_davinci_reset_ctrl(host, 1); |
b4cff454 VB |
1125 | |
1126 | writel(0, host->base + DAVINCI_MMCCLK); | |
1127 | writel(MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK); | |
1128 | ||
1129 | writel(0x1FFF, host->base + DAVINCI_MMCTOR); | |
1130 | writel(0xFFFF, host->base + DAVINCI_MMCTOD); | |
1131 | ||
06de845f | 1132 | mmc_davinci_reset_ctrl(host, 0); |
b4cff454 VB |
1133 | } |
1134 | ||
ed425fc4 | 1135 | static const struct platform_device_id davinci_mmc_devtype[] = { |
d7ca4c75 MP |
1136 | { |
1137 | .name = "dm6441-mmc", | |
1138 | .driver_data = MMC_CTLR_VERSION_1, | |
1139 | }, { | |
1140 | .name = "da830-mmc", | |
1141 | .driver_data = MMC_CTLR_VERSION_2, | |
1142 | }, | |
1143 | {}, | |
1144 | }; | |
1145 | MODULE_DEVICE_TABLE(platform, davinci_mmc_devtype); | |
1146 | ||
7b43da4c MP |
1147 | static const struct of_device_id davinci_mmc_dt_ids[] = { |
1148 | { | |
1149 | .compatible = "ti,dm6441-mmc", | |
1150 | .data = &davinci_mmc_devtype[MMC_CTLR_VERSION_1], | |
1151 | }, | |
1152 | { | |
1153 | .compatible = "ti,da830-mmc", | |
1154 | .data = &davinci_mmc_devtype[MMC_CTLR_VERSION_2], | |
1155 | }, | |
1156 | {}, | |
1157 | }; | |
1158 | MODULE_DEVICE_TABLE(of, davinci_mmc_dt_ids); | |
1159 | ||
c8301e79 | 1160 | static int mmc_davinci_parse_pdata(struct mmc_host *mmc) |
b4cff454 | 1161 | { |
c8301e79 | 1162 | struct platform_device *pdev = to_platform_device(mmc->parent); |
b4cff454 | 1163 | struct davinci_mmc_config *pdata = pdev->dev.platform_data; |
c8301e79 | 1164 | struct mmc_davinci_host *host; |
6e628dad | 1165 | int ret; |
7b43da4c | 1166 | |
c8301e79 | 1167 | if (!pdata) |
1168 | return -EINVAL; | |
7b43da4c | 1169 | |
c8301e79 | 1170 | host = mmc_priv(mmc); |
1171 | if (!host) | |
1172 | return -EINVAL; | |
7b43da4c | 1173 | |
c8301e79 | 1174 | if (pdata && pdata->nr_sg) |
1175 | host->nr_sg = pdata->nr_sg - 1; | |
1176 | ||
1177 | if (pdata && (pdata->wires == 4 || pdata->wires == 0)) | |
1178 | mmc->caps |= MMC_CAP_4_BIT_DATA; | |
1179 | ||
1180 | if (pdata && (pdata->wires == 8)) | |
1181 | mmc->caps |= (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA); | |
1182 | ||
c8301e79 | 1183 | mmc->f_min = 312500; |
1184 | mmc->f_max = 25000000; | |
1185 | if (pdata && pdata->max_freq) | |
1186 | mmc->f_max = pdata->max_freq; | |
1187 | if (pdata && pdata->caps) | |
1188 | mmc->caps |= pdata->caps; | |
1189 | ||
6e628dad | 1190 | /* Register a cd gpio, if there is not one, enable polling */ |
1191 | ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL); | |
1192 | if (ret == -EPROBE_DEFER) | |
1193 | return ret; | |
1194 | else if (ret) | |
1195 | mmc->caps |= MMC_CAP_NEEDS_POLL; | |
1196 | ||
1197 | ret = mmc_gpiod_request_ro(mmc, "wp", 0, false, 0, NULL); | |
1198 | if (ret == -EPROBE_DEFER) | |
1199 | return ret; | |
1200 | ||
c8301e79 | 1201 | return 0; |
7b43da4c MP |
1202 | } |
1203 | ||
1204 | static int __init davinci_mmcsd_probe(struct platform_device *pdev) | |
1205 | { | |
c8301e79 | 1206 | const struct of_device_id *match; |
b4cff454 VB |
1207 | struct mmc_davinci_host *host = NULL; |
1208 | struct mmc_host *mmc = NULL; | |
1209 | struct resource *r, *mem = NULL; | |
62ac52b2 | 1210 | int ret, irq; |
b4cff454 | 1211 | size_t mem_size; |
d7ca4c75 | 1212 | const struct platform_device_id *id_entry; |
b4cff454 | 1213 | |
b4cff454 | 1214 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
902a8a0b | 1215 | if (!r) |
62ac52b2 | 1216 | return -ENODEV; |
902a8a0b AB |
1217 | irq = platform_get_irq(pdev, 0); |
1218 | if (irq < 0) | |
1219 | return irq; | |
b4cff454 | 1220 | |
b4cff454 | 1221 | mem_size = resource_size(r); |
62ac52b2 DL |
1222 | mem = devm_request_mem_region(&pdev->dev, r->start, mem_size, |
1223 | pdev->name); | |
b4cff454 | 1224 | if (!mem) |
62ac52b2 | 1225 | return -EBUSY; |
b4cff454 | 1226 | |
b4cff454 VB |
1227 | mmc = mmc_alloc_host(sizeof(struct mmc_davinci_host), &pdev->dev); |
1228 | if (!mmc) | |
62ac52b2 | 1229 | return -ENOMEM; |
b4cff454 VB |
1230 | |
1231 | host = mmc_priv(mmc); | |
1232 | host->mmc = mmc; /* Important */ | |
1233 | ||
b4cff454 | 1234 | host->mem_res = mem; |
62ac52b2 DL |
1235 | host->base = devm_ioremap(&pdev->dev, mem->start, mem_size); |
1236 | if (!host->base) { | |
1237 | ret = -ENOMEM; | |
1238 | goto ioremap_fail; | |
1239 | } | |
b4cff454 | 1240 | |
62ac52b2 | 1241 | host->clk = devm_clk_get(&pdev->dev, NULL); |
b4cff454 VB |
1242 | if (IS_ERR(host->clk)) { |
1243 | ret = PTR_ERR(host->clk); | |
62ac52b2 | 1244 | goto clk_get_fail; |
b4cff454 | 1245 | } |
e2f3bfbd | 1246 | ret = clk_prepare_enable(host->clk); |
62ac52b2 | 1247 | if (ret) |
e2f3bfbd | 1248 | goto clk_prepare_enable_fail; |
62ac52b2 | 1249 | |
b4cff454 VB |
1250 | host->mmc_input_clk = clk_get_rate(host->clk); |
1251 | ||
c8301e79 | 1252 | match = of_match_device(davinci_mmc_dt_ids, &pdev->dev); |
1253 | if (match) { | |
1254 | pdev->id_entry = match->data; | |
1255 | ret = mmc_of_parse(mmc); | |
1256 | if (ret) { | |
1257 | dev_err(&pdev->dev, | |
1258 | "could not parse of data: %d\n", ret); | |
1259 | goto parse_fail; | |
1260 | } | |
1261 | } else { | |
1262 | ret = mmc_davinci_parse_pdata(mmc); | |
1263 | if (ret) { | |
1264 | dev_err(&pdev->dev, | |
1265 | "could not parse platform data: %d\n", ret); | |
1266 | goto parse_fail; | |
1267 | } } | |
ca2afb6d SR |
1268 | |
1269 | if (host->nr_sg > MAX_NR_SG || !host->nr_sg) | |
1270 | host->nr_sg = MAX_NR_SG; | |
1271 | ||
c8301e79 | 1272 | init_mmcsd_host(host); |
1273 | ||
b4cff454 | 1274 | host->use_dma = use_dma; |
f9db92cb AS |
1275 | host->mmc_irq = irq; |
1276 | host->sdio_irq = platform_get_irq(pdev, 1); | |
b4cff454 | 1277 | |
0a4d7236 PU |
1278 | if (host->use_dma) { |
1279 | ret = davinci_acquire_dma_channels(host); | |
1280 | if (ret == -EPROBE_DEFER) | |
62ac52b2 | 1281 | goto dma_probe_defer; |
0a4d7236 PU |
1282 | else if (ret) |
1283 | host->use_dma = 0; | |
1284 | } | |
b4cff454 | 1285 | |
132f1074 | 1286 | mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; |
b4cff454 | 1287 | |
d7ca4c75 MP |
1288 | id_entry = platform_get_device_id(pdev); |
1289 | if (id_entry) | |
1290 | host->version = id_entry->driver_data; | |
b4cff454 VB |
1291 | |
1292 | mmc->ops = &mmc_davinci_ops; | |
b4cff454 VB |
1293 | mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; |
1294 | ||
1295 | /* With no iommu coalescing pages, each phys_seg is a hw_seg. | |
1296 | * Each hw_seg uses one EDMA parameter RAM slot, always one | |
1297 | * channel and then usually some linked slots. | |
1298 | */ | |
5413da81 | 1299 | mmc->max_segs = MAX_NR_SG; |
b4cff454 VB |
1300 | |
1301 | /* EDMA limit per hw segment (one or two MBytes) */ | |
1302 | mmc->max_seg_size = MAX_CCNT * rw_threshold; | |
1303 | ||
1304 | /* MMC/SD controller limits for multiblock requests */ | |
1305 | mmc->max_blk_size = 4095; /* BLEN is 12 bits */ | |
1306 | mmc->max_blk_count = 65535; /* NBLK is 16 bits */ | |
1307 | mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; | |
1308 | ||
a36274e0 | 1309 | dev_dbg(mmc_dev(host->mmc), "max_segs=%d\n", mmc->max_segs); |
b4cff454 VB |
1310 | dev_dbg(mmc_dev(host->mmc), "max_blk_size=%d\n", mmc->max_blk_size); |
1311 | dev_dbg(mmc_dev(host->mmc), "max_req_size=%d\n", mmc->max_req_size); | |
1312 | dev_dbg(mmc_dev(host->mmc), "max_seg_size=%d\n", mmc->max_seg_size); | |
1313 | ||
1314 | platform_set_drvdata(pdev, host); | |
1315 | ||
7e30b8de C |
1316 | ret = mmc_davinci_cpufreq_register(host); |
1317 | if (ret) { | |
1318 | dev_err(&pdev->dev, "failed to register cpufreq\n"); | |
1319 | goto cpu_freq_fail; | |
1320 | } | |
1321 | ||
b4cff454 VB |
1322 | ret = mmc_add_host(mmc); |
1323 | if (ret < 0) | |
62ac52b2 | 1324 | goto mmc_add_host_fail; |
b4cff454 | 1325 | |
62ac52b2 DL |
1326 | ret = devm_request_irq(&pdev->dev, irq, mmc_davinci_irq, 0, |
1327 | mmc_hostname(mmc), host); | |
b4cff454 | 1328 | if (ret) |
62ac52b2 | 1329 | goto request_irq_fail; |
b4cff454 | 1330 | |
f9db92cb | 1331 | if (host->sdio_irq >= 0) { |
62ac52b2 DL |
1332 | ret = devm_request_irq(&pdev->dev, host->sdio_irq, |
1333 | mmc_davinci_sdio_irq, 0, | |
1334 | mmc_hostname(mmc), host); | |
f9db92cb AS |
1335 | if (!ret) |
1336 | mmc->caps |= MMC_CAP_SDIO_IRQ; | |
1337 | } | |
1338 | ||
b4cff454 VB |
1339 | rename_region(mem, mmc_hostname(mmc)); |
1340 | ||
1341 | dev_info(mmc_dev(host->mmc), "Using %s, %d-bit mode\n", | |
1342 | host->use_dma ? "DMA" : "PIO", | |
1343 | (mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1); | |
1344 | ||
1345 | return 0; | |
1346 | ||
62ac52b2 DL |
1347 | request_irq_fail: |
1348 | mmc_remove_host(mmc); | |
1349 | mmc_add_host_fail: | |
7e30b8de C |
1350 | mmc_davinci_cpufreq_deregister(host); |
1351 | cpu_freq_fail: | |
62ac52b2 | 1352 | davinci_release_dma_channels(host); |
c8301e79 | 1353 | parse_fail: |
62ac52b2 | 1354 | dma_probe_defer: |
e2f3bfbd DL |
1355 | clk_disable_unprepare(host->clk); |
1356 | clk_prepare_enable_fail: | |
62ac52b2 DL |
1357 | clk_get_fail: |
1358 | ioremap_fail: | |
1359 | mmc_free_host(mmc); | |
b4cff454 VB |
1360 | |
1361 | return ret; | |
1362 | } | |
1363 | ||
1364 | static int __exit davinci_mmcsd_remove(struct platform_device *pdev) | |
1365 | { | |
1366 | struct mmc_davinci_host *host = platform_get_drvdata(pdev); | |
1367 | ||
62ac52b2 DL |
1368 | mmc_remove_host(host->mmc); |
1369 | mmc_davinci_cpufreq_deregister(host); | |
1370 | davinci_release_dma_channels(host); | |
e2f3bfbd | 1371 | clk_disable_unprepare(host->clk); |
62ac52b2 | 1372 | mmc_free_host(host->mmc); |
b4cff454 VB |
1373 | |
1374 | return 0; | |
1375 | } | |
1376 | ||
1377 | #ifdef CONFIG_PM | |
bbce5802 | 1378 | static int davinci_mmcsd_suspend(struct device *dev) |
b4cff454 | 1379 | { |
bbce5802 | 1380 | struct platform_device *pdev = to_platform_device(dev); |
b4cff454 VB |
1381 | struct mmc_davinci_host *host = platform_get_drvdata(pdev); |
1382 | ||
5ffdeea5 UH |
1383 | writel(0, host->base + DAVINCI_MMCIM); |
1384 | mmc_davinci_reset_ctrl(host, 1); | |
1385 | clk_disable(host->clk); | |
bbce5802 | 1386 | |
5ffdeea5 | 1387 | return 0; |
b4cff454 VB |
1388 | } |
1389 | ||
bbce5802 | 1390 | static int davinci_mmcsd_resume(struct device *dev) |
b4cff454 | 1391 | { |
bbce5802 | 1392 | struct platform_device *pdev = to_platform_device(dev); |
b4cff454 | 1393 | struct mmc_davinci_host *host = platform_get_drvdata(pdev); |
bbce5802 C |
1394 | |
1395 | clk_enable(host->clk); | |
bbce5802 | 1396 | mmc_davinci_reset_ctrl(host, 0); |
bbce5802 | 1397 | |
5ffdeea5 | 1398 | return 0; |
b4cff454 | 1399 | } |
bbce5802 C |
1400 | |
1401 | static const struct dev_pm_ops davinci_mmcsd_pm = { | |
1402 | .suspend = davinci_mmcsd_suspend, | |
1403 | .resume = davinci_mmcsd_resume, | |
1404 | }; | |
1405 | ||
1406 | #define davinci_mmcsd_pm_ops (&davinci_mmcsd_pm) | |
b4cff454 | 1407 | #else |
bbce5802 | 1408 | #define davinci_mmcsd_pm_ops NULL |
b4cff454 VB |
1409 | #endif |
1410 | ||
1411 | static struct platform_driver davinci_mmcsd_driver = { | |
1412 | .driver = { | |
1413 | .name = "davinci_mmc", | |
bbce5802 | 1414 | .pm = davinci_mmcsd_pm_ops, |
6fad5128 | 1415 | .of_match_table = davinci_mmc_dt_ids, |
b4cff454 VB |
1416 | }, |
1417 | .remove = __exit_p(davinci_mmcsd_remove), | |
d7ca4c75 | 1418 | .id_table = davinci_mmc_devtype, |
b4cff454 VB |
1419 | }; |
1420 | ||
d4bf6325 | 1421 | module_platform_driver_probe(davinci_mmcsd_driver, davinci_mmcsd_probe); |
b4cff454 VB |
1422 | |
1423 | MODULE_AUTHOR("Texas Instruments India"); | |
1424 | MODULE_LICENSE("GPL"); | |
1425 | MODULE_DESCRIPTION("MMC/SD driver for Davinci MMC controller"); | |
7f8bea7f | 1426 | MODULE_ALIAS("platform:davinci_mmc"); |
b4cff454 | 1427 |