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drivers: power: report battery voltage in AOSP compatible format
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / mmc / host / atmel-mci.c
CommitLineData
7d2be074
HS		 1/*
2 * Atmel MultiMedia Card Interface driver
3 *
4 * Copyright (C) 2004-2008 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/blkdev.h>
11#include <linux/clk.h>
deec9ae3 12#include <linux/debugfs.h>
7d2be074 13#include <linux/device.h>
65e8b083
HS		 14#include <linux/dmaengine.h>
15#include <linux/dma-mapping.h>
fbfca4b8 16#include <linux/err.h>
3c26e170 17#include <linux/gpio.h>
7d2be074
HS		 18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/ioport.h>
21#include <linux/module.h>
e919fd20
LD		 22#include <linux/of.h>
23#include <linux/of_device.h>
24#include <linux/of_gpio.h>
7d2be074
HS		 25#include <linux/platform_device.h>
26#include <linux/scatterlist.h>
deec9ae3 27#include <linux/seq_file.h>
5a0e3ad6 28#include <linux/slab.h>
deec9ae3 29#include <linux/stat.h>
e2b35f3d 30#include <linux/types.h>
bcd2360c 31#include <linux/platform_data/atmel.h>
7d2be074
HS		 32
33#include <linux/mmc/host.h>
2f1d7918 34#include <linux/mmc/sdio.h>
2635d1ba
NF		 35
36#include <mach/atmel-mci.h>
c42aa775 37#include <linux/atmel-mci.h>
796211b7 38#include <linux/atmel_pdc.h>
7d2be074 39
7d2be074
HS		 40#include <asm/io.h>
41#include <asm/unaligned.h>
42
04d699c3 43#include <mach/cpu.h>
7d2be074
HS		 44
45#include "atmel-mci-regs.h"
46
2c96a293 47#define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
65e8b083 48#define ATMCI_DMA_THRESHOLD 16
7d2be074
HS		 49
50enum {
f5177547 51 EVENT_CMD_RDY = 0,
7d2be074 52 EVENT_XFER_COMPLETE,
f5177547 53 EVENT_NOTBUSY,
c06ad258
HS		 54 EVENT_DATA_ERROR,
55};
56
57enum atmel_mci_state {
965ebf33
HS		 58 STATE_IDLE = 0,
59 STATE_SENDING_CMD,
f5177547
LD		 60 STATE_DATA_XFER,
61 STATE_WAITING_NOTBUSY,
c06ad258 62 STATE_SENDING_STOP,
f5177547 63 STATE_END_REQUEST,
7d2be074
HS		 64};
65
796211b7
LD		 66enum atmci_xfer_dir {
67 XFER_RECEIVE = 0,
68 XFER_TRANSMIT,
69};
70
71enum atmci_pdc_buf {
72 PDC_FIRST_BUF = 0,
73 PDC_SECOND_BUF,
74};
75
76struct atmel_mci_caps {
ccdfe612 77 bool has_dma_conf_reg;
796211b7
LD		 78 bool has_pdc;
79 bool has_cfg_reg;
80 bool has_cstor_reg;
81 bool has_highspeed;
82 bool has_rwproof;
faf8180b 83 bool has_odd_clk_div;
24011f34
LD		 84 bool has_bad_data_ordering;
85 bool need_reset_after_xfer;
86 bool need_blksz_mul_4;
077d4073 87 bool need_notbusy_for_read_ops;
796211b7
LD		 88};
89
65e8b083 90struct atmel_mci_dma {
65e8b083
HS		 91 struct dma_chan *chan;
92 struct dma_async_tx_descriptor *data_desc;
65e8b083
HS		 93};
94
965ebf33
HS		 95/**
96 * struct atmel_mci - MMC controller state shared between all slots
97 * @lock: Spinlock protecting the queue and associated data.
98 * @regs: Pointer to MMIO registers.
796211b7 99 * @sg: Scatterlist entry currently being processed by PIO or PDC code.
965ebf33 100 * @pio_offset: Offset into the current scatterlist entry.
7a90dcc2
LD		 101 * @buffer: Buffer used if we don't have the r/w proof capability. We
102 * don't have the time to switch pdc buffers so we have to use only
103 * one buffer for the full transaction.
104 * @buf_size: size of the buffer.
105 * @phys_buf_addr: buffer address needed for pdc.
965ebf33
HS		 106 * @cur_slot: The slot which is currently using the controller.
107 * @mrq: The request currently being processed on @cur_slot,
108 * or NULL if the controller is idle.
109 * @cmd: The command currently being sent to the card, or NULL.
110 * @data: The data currently being transferred, or NULL if no data
111 * transfer is in progress.
796211b7 112 * @data_size: just data->blocks * data->blksz.
65e8b083
HS		 113 * @dma: DMA client state.
114 * @data_chan: DMA channel being used for the current data transfer.
965ebf33
HS		 115 * @cmd_status: Snapshot of SR taken upon completion of the current
116 * command. Only valid when EVENT_CMD_COMPLETE is pending.
117 * @data_status: Snapshot of SR taken upon completion of the current
118 * data transfer. Only valid when EVENT_DATA_COMPLETE or
119 * EVENT_DATA_ERROR is pending.
120 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
121 * to be sent.
122 * @tasklet: Tasklet running the request state machine.
123 * @pending_events: Bitmask of events flagged by the interrupt handler
124 * to be processed by the tasklet.
125 * @completed_events: Bitmask of events which the state machine has
126 * processed.
127 * @state: Tasklet state.
128 * @queue: List of slots waiting for access to the controller.
129 * @need_clock_update: Update the clock rate before the next request.
130 * @need_reset: Reset controller before next request.
24011f34 131 * @timer: Timer to balance the data timeout error flag which cannot rise.
965ebf33 132 * @mode_reg: Value of the MR register.
74791a2d 133 * @cfg_reg: Value of the CFG register.
965ebf33
HS		 134 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
135 * rate and timeout calculations.
136 * @mapbase: Physical address of the MMIO registers.
137 * @mck: The peripheral bus clock hooked up to the MMC controller.
138 * @pdev: Platform device associated with the MMC controller.
139 * @slot: Slots sharing this MMC controller.
796211b7
LD		 140 * @caps: MCI capabilities depending on MCI version.
141 * @prepare_data: function to setup MCI before data transfer which
142 * depends on MCI capabilities.
143 * @submit_data: function to start data transfer which depends on MCI
144 * capabilities.
145 * @stop_transfer: function to stop data transfer which depends on MCI
146 * capabilities.
965ebf33
HS		 147 *
148 * Locking
149 * =======
150 *
151 * @lock is a softirq-safe spinlock protecting @queue as well as
152 * @cur_slot, @mrq and @state. These must always be updated
153 * at the same time while holding @lock.
154 *
155 * @lock also protects mode_reg and need_clock_update since these are
156 * used to synchronize mode register updates with the queue
157 * processing.
158 *
159 * The @mrq field of struct atmel_mci_slot is also protected by @lock,
160 * and must always be written at the same time as the slot is added to
161 * @queue.
162 *
163 * @pending_events and @completed_events are accessed using atomic bit
164 * operations, so they don't need any locking.
165 *
166 * None of the fields touched by the interrupt handler need any
167 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
168 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
169 * interrupts must be disabled and @data_status updated with a
170 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
25985edc 171 * CMDRDY interrupt must be disabled and @cmd_status updated with a
965ebf33
HS		 172 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
173 * bytes_xfered field of @data must be written. This is ensured by
174 * using barriers.
175 */
7d2be074 176struct atmel_mci {
965ebf33 177 spinlock_t lock;
7d2be074
HS		 178 void __iomem *regs;
179
180 struct scatterlist *sg;
bdbc5d0c 181 unsigned int sg_len;
7d2be074 182 unsigned int pio_offset;
7a90dcc2
LD		 183 unsigned int *buffer;
184 unsigned int buf_size;
185 dma_addr_t buf_phys_addr;
7d2be074 186
965ebf33 187 struct atmel_mci_slot *cur_slot;
7d2be074
HS		 188 struct mmc_request *mrq;
189 struct mmc_command *cmd;
190 struct mmc_data *data;
796211b7 191 unsigned int data_size;
7d2be074 192
65e8b083
HS		 193 struct atmel_mci_dma dma;
194 struct dma_chan *data_chan;
e2b35f3d 195 struct dma_slave_config dma_conf;
65e8b083 196
7d2be074
HS		 197 u32 cmd_status;
198 u32 data_status;
7d2be074
HS		 199 u32 stop_cmdr;
200
7d2be074
HS		 201 struct tasklet_struct tasklet;
202 unsigned long pending_events;
203 unsigned long completed_events;
c06ad258 204 enum atmel_mci_state state;
965ebf33 205 struct list_head queue;
7d2be074 206
965ebf33
HS		 207 bool need_clock_update;
208 bool need_reset;
24011f34 209 struct timer_list timer;
965ebf33 210 u32 mode_reg;
74791a2d 211 u32 cfg_reg;
7d2be074
HS		 212 unsigned long bus_hz;
213 unsigned long mapbase;
214 struct clk *mck;
215 struct platform_device *pdev;
965ebf33 216
2c96a293 217 struct atmel_mci_slot *slot[ATMCI_MAX_NR_SLOTS];
796211b7
LD		 218
219 struct atmel_mci_caps caps;
220
221 u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data);
222 void (*submit_data)(struct atmel_mci *host, struct mmc_data *data);
223 void (*stop_transfer)(struct atmel_mci *host);
965ebf33
HS		 224};
225
226/**
227 * struct atmel_mci_slot - MMC slot state
228 * @mmc: The mmc_host representing this slot.
229 * @host: The MMC controller this slot is using.
230 * @sdc_reg: Value of SDCR to be written before using this slot.
88ff82ed 231 * @sdio_irq: SDIO irq mask for this slot.
965ebf33
HS		 232 * @mrq: mmc_request currently being processed or waiting to be
233 * processed, or NULL when the slot is idle.
234 * @queue_node: List node for placing this node in the @queue list of
235 * &struct atmel_mci.
236 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
237 * @flags: Random state bits associated with the slot.
238 * @detect_pin: GPIO pin used for card detection, or negative if not
239 * available.
240 * @wp_pin: GPIO pin used for card write protect sending, or negative
241 * if not available.
1c1452be 242 * @detect_is_active_high: The state of the detect pin when it is active.
965ebf33
HS		 243 * @detect_timer: Timer used for debouncing @detect_pin interrupts.
244 */
245struct atmel_mci_slot {
246 struct mmc_host *mmc;
247 struct atmel_mci *host;
248
249 u32 sdc_reg;
88ff82ed 250 u32 sdio_irq;
965ebf33
HS		 251
252 struct mmc_request *mrq;
253 struct list_head queue_node;
254
255 unsigned int clock;
256 unsigned long flags;
257#define ATMCI_CARD_PRESENT 0
258#define ATMCI_CARD_NEED_INIT 1
259#define ATMCI_SHUTDOWN 2
5c2f2b9b 260#define ATMCI_SUSPENDED 3
965ebf33
HS		 261
262 int detect_pin;
263 int wp_pin;
1c1452be 264 bool detect_is_active_high;
965ebf33
HS		 265
266 struct timer_list detect_timer;
7d2be074
HS		 267};
268
7d2be074
HS		 269#define atmci_test_and_clear_pending(host, event) \
270 test_and_clear_bit(event, &host->pending_events)
7d2be074
HS		 271#define atmci_set_completed(host, event) \
272 set_bit(event, &host->completed_events)
273#define atmci_set_pending(host, event) \
274 set_bit(event, &host->pending_events)
7d2be074 275
deec9ae3
HS		 276/*
277 * The debugfs stuff below is mostly optimized away when
278 * CONFIG_DEBUG_FS is not set.
279 */
280static int atmci_req_show(struct seq_file *s, void *v)
281{
965ebf33
HS		 282 struct atmel_mci_slot *slot = s->private;
283 struct mmc_request *mrq;
deec9ae3
HS		 284 struct mmc_command *cmd;
285 struct mmc_command *stop;
286 struct mmc_data *data;
287
288 /* Make sure we get a consistent snapshot */
965ebf33
HS		 289 spin_lock_bh(&slot->host->lock);
290 mrq = slot->mrq;
deec9ae3
HS		 291
292 if (mrq) {
293 cmd = mrq->cmd;
294 data = mrq->data;
295 stop = mrq->stop;
296
297 if (cmd)
298 seq_printf(s,
299 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
300 cmd->opcode, cmd->arg, cmd->flags,
301 cmd->resp[0], cmd->resp[1], cmd->resp[2],
d586ebbb 302 cmd->resp[3], cmd->error);
deec9ae3
HS		 303 if (data)
304 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
305 data->bytes_xfered, data->blocks,
306 data->blksz, data->flags, data->error);
307 if (stop)
308 seq_printf(s,
309 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
310 stop->opcode, stop->arg, stop->flags,
311 stop->resp[0], stop->resp[1], stop->resp[2],
d586ebbb 312 stop->resp[3], stop->error);
deec9ae3
HS		 313 }
314
965ebf33 315 spin_unlock_bh(&slot->host->lock);
deec9ae3
HS		 316
317 return 0;
318}
319
320static int atmci_req_open(struct inode *inode, struct file *file)
321{
322 return single_open(file, atmci_req_show, inode->i_private);
323}
324
325static const struct file_operations atmci_req_fops = {
326 .owner = THIS_MODULE,
327 .open = atmci_req_open,
328 .read = seq_read,
329 .llseek = seq_lseek,
330 .release = single_release,
331};
332
333static void atmci_show_status_reg(struct seq_file *s,
334 const char *regname, u32 value)
335{
336 static const char *sr_bit[] = {
337 [0] = "CMDRDY",
338 [1] = "RXRDY",
339 [2] = "TXRDY",
340 [3] = "BLKE",
341 [4] = "DTIP",
342 [5] = "NOTBUSY",
04d699c3
RE		 343 [6] = "ENDRX",
344 [7] = "ENDTX",
deec9ae3
HS		 345 [8] = "SDIOIRQA",
346 [9] = "SDIOIRQB",
04d699c3
RE		 347 [12] = "SDIOWAIT",
348 [14] = "RXBUFF",
349 [15] = "TXBUFE",
deec9ae3
HS		 350 [16] = "RINDE",
351 [17] = "RDIRE",
352 [18] = "RCRCE",
353 [19] = "RENDE",
354 [20] = "RTOE",
355 [21] = "DCRCE",
356 [22] = "DTOE",
04d699c3
RE		 357 [23] = "CSTOE",
358 [24] = "BLKOVRE",
359 [25] = "DMADONE",
360 [26] = "FIFOEMPTY",
361 [27] = "XFRDONE",
deec9ae3
HS		 362 [30] = "OVRE",
363 [31] = "UNRE",
364 };
365 unsigned int i;
366
367 seq_printf(s, "%s:\t0x%08x", regname, value);
368 for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
369 if (value & (1 << i)) {
370 if (sr_bit[i])
371 seq_printf(s, " %s", sr_bit[i]);
372 else
373 seq_puts(s, " UNKNOWN");
374 }
375 }
376 seq_putc(s, '\n');
377}
378
379static int atmci_regs_show(struct seq_file *s, void *v)
380{
381 struct atmel_mci *host = s->private;
382 u32 *buf;
383
2c96a293 384 buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL);
deec9ae3
HS		 385 if (!buf)
386 return -ENOMEM;
387
965ebf33
HS		 388 /*
389 * Grab a more or less consistent snapshot. Note that we're
390 * not disabling interrupts, so IMR and SR may not be
391 * consistent.
392 */
393 spin_lock_bh(&host->lock);
87e60f2b 394 clk_enable(host->mck);
2c96a293 395 memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE);
87e60f2b 396 clk_disable(host->mck);
965ebf33 397 spin_unlock_bh(&host->lock);
deec9ae3 398
8a4de07e 399 seq_printf(s, "MR:\t0x%08x%s%s ",
2c96a293
LD		 400 buf[ATMCI_MR / 4],
401 buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "",
8a4de07e
NF		 402 buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : "");
403 if (host->caps.has_odd_clk_div)
404 seq_printf(s, "{CLKDIV,CLKODD}=%u\n",
405 ((buf[ATMCI_MR / 4] & 0xff) << 1)
406 | ((buf[ATMCI_MR / 4] >> 16) & 1));
407 else
408 seq_printf(s, "CLKDIV=%u\n",
409 (buf[ATMCI_MR / 4] & 0xff));
2c96a293
LD		 410 seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]);
411 seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]);
412 seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]);
deec9ae3 413 seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
2c96a293
LD		 414 buf[ATMCI_BLKR / 4],
415 buf[ATMCI_BLKR / 4] & 0xffff,
416 (buf[ATMCI_BLKR / 4] >> 16) & 0xffff);
796211b7 417 if (host->caps.has_cstor_reg)
2c96a293 418 seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]);
deec9ae3
HS		 419
420 /* Don't read RSPR and RDR; it will consume the data there */
421
2c96a293
LD		 422 atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
423 atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
deec9ae3 424
ccdfe612 425 if (host->caps.has_dma_conf_reg) {
74791a2d
NF		 426 u32 val;
427
2c96a293 428 val = buf[ATMCI_DMA / 4];
74791a2d
NF		 429 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
430 val, val & 3,
431 ((val >> 4) & 3) ?
432 1 << (((val >> 4) & 3) + 1) : 1,
2c96a293 433 val & ATMCI_DMAEN ? " DMAEN" : "");
796211b7
LD		 434 }
435 if (host->caps.has_cfg_reg) {
436 u32 val;
74791a2d 437
2c96a293 438 val = buf[ATMCI_CFG / 4];
74791a2d
NF		 439 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
440 val,
2c96a293
LD		 441 val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
442 val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
443 val & ATMCI_CFG_HSMODE ? " HSMODE" : "",
444 val & ATMCI_CFG_LSYNC ? " LSYNC" : "");
74791a2d
NF		 445 }
446
b17339a1
HS		 447 kfree(buf);
448
deec9ae3
HS		 449 return 0;
450}
451
452static int atmci_regs_open(struct inode *inode, struct file *file)
453{
454 return single_open(file, atmci_regs_show, inode->i_private);
455}
456
457static const struct file_operations atmci_regs_fops = {
458 .owner = THIS_MODULE,
459 .open = atmci_regs_open,
460 .read = seq_read,
461 .llseek = seq_lseek,
462 .release = single_release,
463};
464
965ebf33 465static void atmci_init_debugfs(struct atmel_mci_slot *slot)
deec9ae3 466{
965ebf33
HS		 467 struct mmc_host *mmc = slot->mmc;
468 struct atmel_mci *host = slot->host;
469 struct dentry *root;
470 struct dentry *node;
deec9ae3 471
deec9ae3
HS		 472 root = mmc->debugfs_root;
473 if (!root)
474 return;
475
476 node = debugfs_create_file("regs", S_IRUSR, root, host,
477 &atmci_regs_fops);
478 if (IS_ERR(node))
479 return;
480 if (!node)
481 goto err;
482
965ebf33 483 node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops);
deec9ae3
HS		 484 if (!node)
485 goto err;
486
c06ad258
HS		 487 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
488 if (!node)
489 goto err;
490
deec9ae3
HS		 491 node = debugfs_create_x32("pending_events", S_IRUSR, root,
492 (u32 *)&host->pending_events);
493 if (!node)
494 goto err;
495
496 node = debugfs_create_x32("completed_events", S_IRUSR, root,
497 (u32 *)&host->completed_events);
498 if (!node)
499 goto err;
500
501 return;
502
503err:
965ebf33 504 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
deec9ae3 505}
7d2be074 506
e919fd20
LD		 507#if defined(CONFIG_OF)
508static const struct of_device_id atmci_dt_ids[] = {
509 { .compatible = "atmel,hsmci" },
510 { /* sentinel */ }
511};
512
513MODULE_DEVICE_TABLE(of, atmci_dt_ids);
514
c3be1efd 515static struct mci_platform_data*
e919fd20
LD		 516atmci_of_init(struct platform_device *pdev)
517{
518 struct device_node *np = pdev->dev.of_node;
519 struct device_node *cnp;
520 struct mci_platform_data *pdata;
521 u32 slot_id;
522
523 if (!np) {
524 dev_err(&pdev->dev, "device node not found\n");
525 return ERR_PTR(-EINVAL);
526 }
527
528 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
529 if (!pdata) {
530 dev_err(&pdev->dev, "could not allocate memory for pdata\n");
531 return ERR_PTR(-ENOMEM);
532 }
533
534 for_each_child_of_node(np, cnp) {
535 if (of_property_read_u32(cnp, "reg", &slot_id)) {
536 dev_warn(&pdev->dev, "reg property is missing for %s\n",
537 cnp->full_name);
538 continue;
539 }
540
541 if (slot_id >= ATMCI_MAX_NR_SLOTS) {
542 dev_warn(&pdev->dev, "can't have more than %d slots\n",
543 ATMCI_MAX_NR_SLOTS);
544 break;
545 }
546
547 if (of_property_read_u32(cnp, "bus-width",
548 &pdata->slot[slot_id].bus_width))
549 pdata->slot[slot_id].bus_width = 1;
550
551 pdata->slot[slot_id].detect_pin =
552 of_get_named_gpio(cnp, "cd-gpios", 0);
553
554 pdata->slot[slot_id].detect_is_active_high =
555 of_property_read_bool(cnp, "cd-inverted");
556
557 pdata->slot[slot_id].wp_pin =
558 of_get_named_gpio(cnp, "wp-gpios", 0);
559 }
560
561 return pdata;
562}
563#else /* CONFIG_OF */
564static inline struct mci_platform_data*
565atmci_of_init(struct platform_device *dev)
566{
567 return ERR_PTR(-EINVAL);
568}
569#endif
570
7a90dcc2
LD		 571static inline unsigned int atmci_get_version(struct atmel_mci *host)
572{
573 return atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
574}
575
24011f34
LD		 576static void atmci_timeout_timer(unsigned long data)
577{
578 struct atmel_mci *host;
579
580 host = (struct atmel_mci *)data;
581
582 dev_dbg(&host->pdev->dev, "software timeout\n");
583
584 if (host->mrq->cmd->data) {
585 host->mrq->cmd->data->error = -ETIMEDOUT;
586 host->data = NULL;
6edfd033
LD		 587 /*
588 * With some SDIO modules, sometimes DMA transfer hangs. If
589 * stop_transfer() is not called then the DMA request is not
590 * removed, following ones are queued and never computed.
591 */
592 if (host->state == STATE_DATA_XFER)
593 host->stop_transfer(host);
24011f34
LD		 594 } else {
595 host->mrq->cmd->error = -ETIMEDOUT;
596 host->cmd = NULL;
597 }
598 host->need_reset = 1;
599 host->state = STATE_END_REQUEST;
600 smp_wmb();
601 tasklet_schedule(&host->tasklet);
602}
603
2c96a293 604static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
7d2be074
HS		 605 unsigned int ns)
606{
66292ad9
LD		 607 /*
608 * It is easier here to use us instead of ns for the timeout,
609 * it prevents from overflows during calculation.
610 */
611 unsigned int us = DIV_ROUND_UP(ns, 1000);
612
613 /* Maximum clock frequency is host->bus_hz/2 */
614 return us * (DIV_ROUND_UP(host->bus_hz, 2000000));
7d2be074
HS		 615}
616
617static void atmci_set_timeout(struct atmel_mci *host,
965ebf33 618 struct atmel_mci_slot *slot, struct mmc_data *data)
7d2be074
HS		 619{
620 static unsigned dtomul_to_shift[] = {
621 0, 4, 7, 8, 10, 12, 16, 20
622 };
623 unsigned timeout;
624 unsigned dtocyc;
625 unsigned dtomul;
626
2c96a293
LD		 627 timeout = atmci_ns_to_clocks(host, data->timeout_ns)
628 + data->timeout_clks;
7d2be074
HS		 629
630 for (dtomul = 0; dtomul < 8; dtomul++) {
631 unsigned shift = dtomul_to_shift[dtomul];
632 dtocyc = (timeout + (1 << shift) - 1) >> shift;
633 if (dtocyc < 15)
634 break;
635 }
636
637 if (dtomul >= 8) {
638 dtomul = 7;
639 dtocyc = 15;
640 }
641
965ebf33 642 dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
7d2be074 643 dtocyc << dtomul_to_shift[dtomul]);
03fc9a7f 644 atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc)));
7d2be074
HS		 645}
646
647/*
648 * Return mask with command flags to be enabled for this command.
649 */
650static u32 atmci_prepare_command(struct mmc_host *mmc,
651 struct mmc_command *cmd)
652{
653 struct mmc_data *data;
654 u32 cmdr;
655
656 cmd->error = -EINPROGRESS;
657
2c96a293 658 cmdr = ATMCI_CMDR_CMDNB(cmd->opcode);
7d2be074
HS		 659
660 if (cmd->flags & MMC_RSP_PRESENT) {
661 if (cmd->flags & MMC_RSP_136)
2c96a293 662 cmdr |= ATMCI_CMDR_RSPTYP_136BIT;
7d2be074 663 else
2c96a293 664 cmdr |= ATMCI_CMDR_RSPTYP_48BIT;
7d2be074
HS		 665 }
666
667 /*
668 * This should really be MAXLAT_5 for CMD2 and ACMD41, but
669 * it's too difficult to determine whether this is an ACMD or
670 * not. Better make it 64.
671 */
2c96a293 672 cmdr |= ATMCI_CMDR_MAXLAT_64CYC;
7d2be074
HS		 673
674 if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
2c96a293 675 cmdr |= ATMCI_CMDR_OPDCMD;
7d2be074
HS		 676
677 data = cmd->data;
678 if (data) {
2c96a293 679 cmdr |= ATMCI_CMDR_START_XFER;
2f1d7918
NF		 680
681 if (cmd->opcode == SD_IO_RW_EXTENDED) {
2c96a293 682 cmdr |= ATMCI_CMDR_SDIO_BLOCK;
2f1d7918
NF		 683 } else {
684 if (data->flags & MMC_DATA_STREAM)
2c96a293 685 cmdr |= ATMCI_CMDR_STREAM;
2f1d7918 686 else if (data->blocks > 1)
2c96a293 687 cmdr |= ATMCI_CMDR_MULTI_BLOCK;
2f1d7918 688 else
2c96a293 689 cmdr |= ATMCI_CMDR_BLOCK;
2f1d7918 690 }
7d2be074
HS		 691
692 if (data->flags & MMC_DATA_READ)
2c96a293 693 cmdr |= ATMCI_CMDR_TRDIR_READ;
7d2be074
HS		 694 }
695
696 return cmdr;
697}
698
11d1488b 699static void atmci_send_command(struct atmel_mci *host,
965ebf33 700 struct mmc_command *cmd, u32 cmd_flags)
7d2be074 701{
7d2be074
HS		 702 WARN_ON(host->cmd);
703 host->cmd = cmd;
704
965ebf33 705 dev_vdbg(&host->pdev->dev,
7d2be074
HS		 706 "start command: ARGR=0x%08x CMDR=0x%08x\n",
707 cmd->arg, cmd_flags);
708
03fc9a7f
LD		 709 atmci_writel(host, ATMCI_ARGR, cmd->arg);
710 atmci_writel(host, ATMCI_CMDR, cmd_flags);
7d2be074
HS		 711}
712
2c96a293 713static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
7d2be074 714{
6801c41a 715 dev_dbg(&host->pdev->dev, "send stop command\n");
11d1488b 716 atmci_send_command(host, data->stop, host->stop_cmdr);
03fc9a7f 717 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
7d2be074
HS		 718}
719
796211b7
LD		 720/*
721 * Configure given PDC buffer taking care of alignement issues.
722 * Update host->data_size and host->sg.
723 */
724static void atmci_pdc_set_single_buf(struct atmel_mci *host,
725 enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb)
726{
727 u32 pointer_reg, counter_reg;
7a90dcc2 728 unsigned int buf_size;
796211b7
LD		 729
730 if (dir == XFER_RECEIVE) {
731 pointer_reg = ATMEL_PDC_RPR;
732 counter_reg = ATMEL_PDC_RCR;
733 } else {
734 pointer_reg = ATMEL_PDC_TPR;
735 counter_reg = ATMEL_PDC_TCR;
736 }
737
738 if (buf_nb == PDC_SECOND_BUF) {
1ebbe3d3
LD		 739 pointer_reg += ATMEL_PDC_SCND_BUF_OFF;
740 counter_reg += ATMEL_PDC_SCND_BUF_OFF;
796211b7
LD		 741 }
742
7a90dcc2
LD		 743 if (!host->caps.has_rwproof) {
744 buf_size = host->buf_size;
745 atmci_writel(host, pointer_reg, host->buf_phys_addr);
746 } else {
747 buf_size = sg_dma_len(host->sg);
748 atmci_writel(host, pointer_reg, sg_dma_address(host->sg));
749 }
750
751 if (host->data_size <= buf_size) {
796211b7
LD		 752 if (host->data_size & 0x3) {
753 /* If size is different from modulo 4, transfer bytes */
754 atmci_writel(host, counter_reg, host->data_size);
755 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE);
756 } else {
757 /* Else transfer 32-bits words */
758 atmci_writel(host, counter_reg, host->data_size / 4);
759 }
760 host->data_size = 0;
761 } else {
762 /* We assume the size of a page is 32-bits aligned */
341fa4c3
LD		 763 atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4);
764 host->data_size -= sg_dma_len(host->sg);
796211b7
LD		 765 if (host->data_size)
766 host->sg = sg_next(host->sg);
767 }
768}
769
770/*
771 * Configure PDC buffer according to the data size ie configuring one or two
772 * buffers. Don't use this function if you want to configure only the second
773 * buffer. In this case, use atmci_pdc_set_single_buf.
774 */
775static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir)
65e8b083 776{
796211b7
LD		 777 atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF);
778 if (host->data_size)
779 atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF);
780}
781
782/*
783 * Unmap sg lists, called when transfer is finished.
784 */
785static void atmci_pdc_cleanup(struct atmel_mci *host)
786{
787 struct mmc_data *data = host->data;
65e8b083 788
009a891b 789 if (data)
796211b7
LD		 790 dma_unmap_sg(&host->pdev->dev,
791 data->sg, data->sg_len,
792 ((data->flags & MMC_DATA_WRITE)
793 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
65e8b083
HS		 794}
795
796211b7
LD		 796/*
797 * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after
798 * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY
799 * interrupt needed for both transfer directions.
800 */
801static void atmci_pdc_complete(struct atmel_mci *host)
65e8b083 802{
7a90dcc2 803 int transfer_size = host->data->blocks * host->data->blksz;
24011f34 804 int i;
7a90dcc2 805
796211b7 806 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
7a90dcc2
LD		 807
808 if ((!host->caps.has_rwproof)
24011f34
LD		 809 && (host->data->flags & MMC_DATA_READ)) {
810 if (host->caps.has_bad_data_ordering)
811 for (i = 0; i < transfer_size; i++)
812 host->buffer[i] = swab32(host->buffer[i]);
7a90dcc2
LD		 813 sg_copy_from_buffer(host->data->sg, host->data->sg_len,
814 host->buffer, transfer_size);
24011f34 815 }
7a90dcc2 816
796211b7 817 atmci_pdc_cleanup(host);
65e8b083 818
796211b7
LD		 819 /*
820 * If the card was removed, data will be NULL. No point trying
821 * to send the stop command or waiting for NBUSY in this case.
822 */
823 if (host->data) {
6801c41a
LD		 824 dev_dbg(&host->pdev->dev,
825 "(%s) set pending xfer complete\n", __func__);
65e8b083 826 atmci_set_pending(host, EVENT_XFER_COMPLETE);
796211b7 827 tasklet_schedule(&host->tasklet);
65e8b083
HS		 828 }
829}
830
796211b7
LD		 831static void atmci_dma_cleanup(struct atmel_mci *host)
832{
833 struct mmc_data *data = host->data;
834
835 if (data)
836 dma_unmap_sg(host->dma.chan->device->dev,
837 data->sg, data->sg_len,
838 ((data->flags & MMC_DATA_WRITE)
839 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
840}
841
842/*
843 * This function is called by the DMA driver from tasklet context.
844 */
65e8b083
HS		 845static void atmci_dma_complete(void *arg)
846{
847 struct atmel_mci *host = arg;
848 struct mmc_data *data = host->data;
849
850 dev_vdbg(&host->pdev->dev, "DMA complete\n");
851
ccdfe612 852 if (host->caps.has_dma_conf_reg)
74791a2d 853 /* Disable DMA hardware handshaking on MCI */
03fc9a7f 854 atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN);
74791a2d 855
65e8b083
HS		 856 atmci_dma_cleanup(host);
857
858 /*
859 * If the card was removed, data will be NULL. No point trying
860 * to send the stop command or waiting for NBUSY in this case.
861 */
862 if (data) {
6801c41a
LD		 863 dev_dbg(&host->pdev->dev,
864 "(%s) set pending xfer complete\n", __func__);
65e8b083
HS		 865 atmci_set_pending(host, EVENT_XFER_COMPLETE);
866 tasklet_schedule(&host->tasklet);
867
868 /*
869 * Regardless of what the documentation says, we have
870 * to wait for NOTBUSY even after block read
871 * operations.
872 *
873 * When the DMA transfer is complete, the controller
874 * may still be reading the CRC from the card, i.e.
875 * the data transfer is still in progress and we
876 * haven't seen all the potential error bits yet.
877 *
878 * The interrupt handler will schedule a different
879 * tasklet to finish things up when the data transfer
880 * is completely done.
881 *
882 * We may not complete the mmc request here anyway
883 * because the mmc layer may call back and cause us to
884 * violate the "don't submit new operations from the
885 * completion callback" rule of the dma engine
886 * framework.
887 */
03fc9a7f 888 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
65e8b083
HS		 889 }
890}
891
796211b7
LD		 892/*
893 * Returns a mask of interrupt flags to be enabled after the whole
894 * request has been prepared.
895 */
896static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
897{
898 u32 iflags;
899
900 data->error = -EINPROGRESS;
901
902 host->sg = data->sg;
bdbc5d0c 903 host->sg_len = data->sg_len;
796211b7
LD		 904 host->data = data;
905 host->data_chan = NULL;
906
907 iflags = ATMCI_DATA_ERROR_FLAGS;
908
909 /*
910 * Errata: MMC data write operation with less than 12
911 * bytes is impossible.
912 *
913 * Errata: MCI Transmit Data Register (TDR) FIFO
914 * corruption when length is not multiple of 4.
915 */
916 if (data->blocks * data->blksz < 12
917 || (data->blocks * data->blksz) & 3)
918 host->need_reset = true;
919
920 host->pio_offset = 0;
921 if (data->flags & MMC_DATA_READ)
922 iflags |= ATMCI_RXRDY;
923 else
924 iflags |= ATMCI_TXRDY;
925
926 return iflags;
927}
928
929/*
930 * Set interrupt flags and set block length into the MCI mode register even
931 * if this value is also accessible in the MCI block register. It seems to be
932 * necessary before the High Speed MCI version. It also map sg and configure
933 * PDC registers.
934 */
935static u32
936atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data)
937{
938 u32 iflags, tmp;
939 unsigned int sg_len;
940 enum dma_data_direction dir;
24011f34 941 int i;
796211b7
LD		 942
943 data->error = -EINPROGRESS;
944
945 host->data = data;
946 host->sg = data->sg;
947 iflags = ATMCI_DATA_ERROR_FLAGS;
948
949 /* Enable pdc mode */
950 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE);
951
952 if (data->flags & MMC_DATA_READ) {
953 dir = DMA_FROM_DEVICE;
954 iflags |= ATMCI_ENDRX | ATMCI_RXBUFF;
955 } else {
956 dir = DMA_TO_DEVICE;
f5177547 957 iflags |= ATMCI_ENDTX | ATMCI_TXBUFE | ATMCI_BLKE;
796211b7
LD		 958 }
959
960 /* Set BLKLEN */
961 tmp = atmci_readl(host, ATMCI_MR);
962 tmp &= 0x0000ffff;
963 tmp |= ATMCI_BLKLEN(data->blksz);
964 atmci_writel(host, ATMCI_MR, tmp);
965
966 /* Configure PDC */
967 host->data_size = data->blocks * data->blksz;
968 sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, dir);
7a90dcc2
LD		 969
970 if ((!host->caps.has_rwproof)
24011f34 971 && (host->data->flags & MMC_DATA_WRITE)) {
7a90dcc2
LD		 972 sg_copy_to_buffer(host->data->sg, host->data->sg_len,
973 host->buffer, host->data_size);
24011f34
LD		 974 if (host->caps.has_bad_data_ordering)
975 for (i = 0; i < host->data_size; i++)
976 host->buffer[i] = swab32(host->buffer[i]);
977 }
7a90dcc2 978
796211b7
LD		 979 if (host->data_size)
980 atmci_pdc_set_both_buf(host,
981 ((dir == DMA_FROM_DEVICE) ? XFER_RECEIVE : XFER_TRANSMIT));
982
983 return iflags;
984}
985
986static u32
74791a2d 987atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
65e8b083
HS		 988{
989 struct dma_chan *chan;
990 struct dma_async_tx_descriptor *desc;
991 struct scatterlist *sg;
992 unsigned int i;
993 enum dma_data_direction direction;
05f5799c 994 enum dma_transfer_direction slave_dirn;
657a77fa 995 unsigned int sglen;
693e5e20 996 u32 maxburst;
796211b7
LD		 997 u32 iflags;
998
999 data->error = -EINPROGRESS;
1000
1001 WARN_ON(host->data);
1002 host->sg = NULL;
1003 host->data = data;
1004
1005 iflags = ATMCI_DATA_ERROR_FLAGS;
65e8b083
HS		 1006
1007 /*
1008 * We don't do DMA on "complex" transfers, i.e. with
1009 * non-word-aligned buffers or lengths. Also, we don't bother
1010 * with all the DMA setup overhead for short transfers.
1011 */
796211b7
LD		 1012 if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
1013 return atmci_prepare_data(host, data);
65e8b083 1014 if (data->blksz & 3)
796211b7 1015 return atmci_prepare_data(host, data);
65e8b083
HS		 1016
1017 for_each_sg(data->sg, sg, data->sg_len, i) {
1018 if (sg->offset & 3 || sg->length & 3)
796211b7 1019 return atmci_prepare_data(host, data);
65e8b083
HS		 1020 }
1021
1022 /* If we don't have a channel, we can't do DMA */
1023 chan = host->dma.chan;
6f49a57a 1024 if (chan)
65e8b083 1025 host->data_chan = chan;
65e8b083
HS		 1026
1027 if (!chan)
1028 return -ENODEV;
1029
05f5799c 1030 if (data->flags & MMC_DATA_READ) {
65e8b083 1031 direction = DMA_FROM_DEVICE;
e2b35f3d 1032 host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM;
693e5e20 1033 maxburst = atmci_convert_chksize(host->dma_conf.src_maxburst);
05f5799c 1034 } else {
65e8b083 1035 direction = DMA_TO_DEVICE;
e2b35f3d 1036 host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV;
693e5e20 1037 maxburst = atmci_convert_chksize(host->dma_conf.dst_maxburst);
05f5799c 1038 }
65e8b083 1039
ccdfe612
H		 1040 if (host->caps.has_dma_conf_reg)
1041 atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) |
1042 ATMCI_DMAEN);
693e5e20 1043
266ac3f2 1044 sglen = dma_map_sg(chan->device->dev, data->sg,
796211b7 1045 data->sg_len, direction);
88ce4db3 1046
e2b35f3d 1047 dmaengine_slave_config(chan, &host->dma_conf);
16052827 1048 desc = dmaengine_prep_slave_sg(chan,
05f5799c 1049 data->sg, sglen, slave_dirn,
65e8b083
HS		 1050 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1051 if (!desc)
657a77fa 1052 goto unmap_exit;
65e8b083
HS		 1053
1054 host->dma.data_desc = desc;
1055 desc->callback = atmci_dma_complete;
1056 desc->callback_param = host;
65e8b083 1057
796211b7 1058 return iflags;
657a77fa 1059unmap_exit:
88ce4db3 1060 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, direction);
657a77fa 1061 return -ENOMEM;
65e8b083
HS		 1062}
1063
796211b7
LD		 1064static void
1065atmci_submit_data(struct atmel_mci *host, struct mmc_data *data)
1066{
1067 return;
1068}
1069
1070/*
1071 * Start PDC according to transfer direction.
1072 */
1073static void
1074atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data)
1075{
1076 if (data->flags & MMC_DATA_READ)
1077 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1078 else
1079 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1080}
1081
1082static void
1083atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
74791a2d
NF		 1084{
1085 struct dma_chan *chan = host->data_chan;
1086 struct dma_async_tx_descriptor *desc = host->dma.data_desc;
1087
1088 if (chan) {
5328906a
LW		 1089 dmaengine_submit(desc);
1090 dma_async_issue_pending(chan);
74791a2d
NF		 1091 }
1092}
1093
796211b7 1094static void atmci_stop_transfer(struct atmel_mci *host)
65e8b083 1095{
6801c41a
LD		 1096 dev_dbg(&host->pdev->dev,
1097 "(%s) set pending xfer complete\n", __func__);
65e8b083 1098 atmci_set_pending(host, EVENT_XFER_COMPLETE);
03fc9a7f 1099 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
65e8b083
HS		 1100}
1101
7d2be074 1102/*
7122bbb0 1103 * Stop data transfer because error(s) occurred.
7d2be074 1104 */
796211b7 1105static void atmci_stop_transfer_pdc(struct atmel_mci *host)
7d2be074 1106{
f5177547 1107 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
796211b7 1108}
965ebf33 1109
796211b7
LD		 1110static void atmci_stop_transfer_dma(struct atmel_mci *host)
1111{
1112 struct dma_chan *chan = host->data_chan;
965ebf33 1113
796211b7
LD		 1114 if (chan) {
1115 dmaengine_terminate_all(chan);
1116 atmci_dma_cleanup(host);
1117 } else {
1118 /* Data transfer was stopped by the interrupt handler */
6801c41a
LD		 1119 dev_dbg(&host->pdev->dev,
1120 "(%s) set pending xfer complete\n", __func__);
796211b7
LD		 1121 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1122 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
65e8b083 1123 }
7d2be074
HS		 1124}
1125
796211b7
LD		 1126/*
1127 * Start a request: prepare data if needed, prepare the command and activate
1128 * interrupts.
1129 */
965ebf33
HS		 1130static void atmci_start_request(struct atmel_mci *host,
1131 struct atmel_mci_slot *slot)
7d2be074 1132{
965ebf33 1133 struct mmc_request *mrq;
7d2be074 1134 struct mmc_command *cmd;
965ebf33 1135 struct mmc_data *data;
7d2be074 1136 u32 iflags;
965ebf33 1137 u32 cmdflags;
7d2be074 1138
965ebf33
HS		 1139 mrq = slot->mrq;
1140 host->cur_slot = slot;
7d2be074 1141 host->mrq = mrq;
965ebf33 1142
7d2be074
HS		 1143 host->pending_events = 0;
1144 host->completed_events = 0;
f5177547 1145 host->cmd_status = 0;
ca55f46e 1146 host->data_status = 0;
7d2be074 1147
6801c41a
LD		 1148 dev_dbg(&host->pdev->dev, "start request: cmd %u\n", mrq->cmd->opcode);
1149
24011f34 1150 if (host->need_reset || host->caps.need_reset_after_xfer) {
18ee684b
LD		 1151 iflags = atmci_readl(host, ATMCI_IMR);
1152 iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB);
03fc9a7f
LD		 1153 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1154 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1155 atmci_writel(host, ATMCI_MR, host->mode_reg);
796211b7 1156 if (host->caps.has_cfg_reg)
03fc9a7f 1157 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
18ee684b 1158 atmci_writel(host, ATMCI_IER, iflags);
965ebf33
HS		 1159 host->need_reset = false;
1160 }
03fc9a7f 1161 atmci_writel(host, ATMCI_SDCR, slot->sdc_reg);
965ebf33 1162
03fc9a7f 1163 iflags = atmci_readl(host, ATMCI_IMR);
2c96a293 1164 if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
f5177547 1165 dev_dbg(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
965ebf33
HS		 1166 iflags);
1167
1168 if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
1169 /* Send init sequence (74 clock cycles) */
03fc9a7f
LD		 1170 atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT);
1171 while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY))
965ebf33
HS		 1172 cpu_relax();
1173 }
74791a2d 1174 iflags = 0;
7d2be074
HS		 1175 data = mrq->data;
1176 if (data) {
965ebf33 1177 atmci_set_timeout(host, slot, data);
a252e3e3
HS		 1178
1179 /* Must set block count/size before sending command */
03fc9a7f 1180 atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks)
2c96a293 1181 | ATMCI_BLKLEN(data->blksz));
965ebf33 1182 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
2c96a293 1183 ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz));
74791a2d 1184
796211b7 1185 iflags |= host->prepare_data(host, data);
7d2be074
HS		 1186 }
1187
2c96a293 1188 iflags |= ATMCI_CMDRDY;
7d2be074 1189 cmd = mrq->cmd;
965ebf33 1190 cmdflags = atmci_prepare_command(slot->mmc, cmd);
6bf1831d
LD		 1191
1192 /*
1193 * DMA transfer should be started before sending the command to avoid
1194 * unexpected errors especially for read operations in SDIO mode.
1195 * Unfortunately, in PDC mode, command has to be sent before starting
1196 * the transfer.
1197 */
1198 if (host->submit_data != &atmci_submit_data_dma)
1199 atmci_send_command(host, cmd, cmdflags);
7d2be074
HS		 1200
1201 if (data)
796211b7 1202 host->submit_data(host, data);
7d2be074 1203
6bf1831d
LD		 1204 if (host->submit_data == &atmci_submit_data_dma)
1205 atmci_send_command(host, cmd, cmdflags);
1206
7d2be074 1207 if (mrq->stop) {
965ebf33 1208 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
2c96a293 1209 host->stop_cmdr |= ATMCI_CMDR_STOP_XFER;
7d2be074 1210 if (!(data->flags & MMC_DATA_WRITE))
2c96a293 1211 host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ;
7d2be074 1212 if (data->flags & MMC_DATA_STREAM)
2c96a293 1213 host->stop_cmdr |= ATMCI_CMDR_STREAM;
7d2be074 1214 else
2c96a293 1215 host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK;
7d2be074
HS		 1216 }
1217
1218 /*
1219 * We could have enabled interrupts earlier, but I suspect
1220 * that would open up a nice can of interesting race
1221 * conditions (e.g. command and data complete, but stop not
1222 * prepared yet.)
1223 */
03fc9a7f 1224 atmci_writel(host, ATMCI_IER, iflags);
24011f34
LD		 1225
1226 mod_timer(&host->timer, jiffies + msecs_to_jiffies(2000));
965ebf33 1227}
7d2be074 1228
965ebf33
HS		 1229static void atmci_queue_request(struct atmel_mci *host,
1230 struct atmel_mci_slot *slot, struct mmc_request *mrq)
1231{
1232 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1233 host->state);
1234
1235 spin_lock_bh(&host->lock);
1236 slot->mrq = mrq;
1237 if (host->state == STATE_IDLE) {
1238 host->state = STATE_SENDING_CMD;
1239 atmci_start_request(host, slot);
1240 } else {
6801c41a 1241 dev_dbg(&host->pdev->dev, "queue request\n");
965ebf33
HS		 1242 list_add_tail(&slot->queue_node, &host->queue);
1243 }
1244 spin_unlock_bh(&host->lock);
1245}
7d2be074 1246
965ebf33
HS		 1247static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1248{
1249 struct atmel_mci_slot *slot = mmc_priv(mmc);
1250 struct atmel_mci *host = slot->host;
1251 struct mmc_data *data;
1252
1253 WARN_ON(slot->mrq);
6801c41a 1254 dev_dbg(&host->pdev->dev, "MRQ: cmd %u\n", mrq->cmd->opcode);
965ebf33
HS		 1255
1256 /*
1257 * We may "know" the card is gone even though there's still an
1258 * electrical connection. If so, we really need to communicate
1259 * this to the MMC core since there won't be any more
1260 * interrupts as the card is completely removed. Otherwise,
1261 * the MMC core might believe the card is still there even
1262 * though the card was just removed very slowly.
1263 */
1264 if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) {
1265 mrq->cmd->error = -ENOMEDIUM;
1266 mmc_request_done(mmc, mrq);
1267 return;
1268 }
1269
1270 /* We don't support multiple blocks of weird lengths. */
1271 data = mrq->data;
1272 if (data && data->blocks > 1 && data->blksz & 3) {
1273 mrq->cmd->error = -EINVAL;
1274 mmc_request_done(mmc, mrq);
1275 }
1276
1277 atmci_queue_request(host, slot, mrq);
7d2be074
HS		 1278}
1279
1280static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1281{
965ebf33
HS		 1282 struct atmel_mci_slot *slot = mmc_priv(mmc);
1283 struct atmel_mci *host = slot->host;
1284 unsigned int i;
7d2be074 1285
2c96a293 1286 slot->sdc_reg &= ~ATMCI_SDCBUS_MASK;
945533b5
HS		 1287 switch (ios->bus_width) {
1288 case MMC_BUS_WIDTH_1:
2c96a293 1289 slot->sdc_reg |= ATMCI_SDCBUS_1BIT;
945533b5
HS		 1290 break;
1291 case MMC_BUS_WIDTH_4:
2c96a293 1292 slot->sdc_reg |= ATMCI_SDCBUS_4BIT;
945533b5
HS		 1293 break;
1294 }
1295
7d2be074 1296 if (ios->clock) {
965ebf33 1297 unsigned int clock_min = ~0U;
a72719d7 1298 int clkdiv;
7d2be074 1299
965ebf33
HS		 1300 spin_lock_bh(&host->lock);
1301 if (!host->mode_reg) {
945533b5 1302 clk_enable(host->mck);
03fc9a7f
LD		 1303 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1304 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
796211b7 1305 if (host->caps.has_cfg_reg)
03fc9a7f 1306 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
965ebf33 1307 }
945533b5 1308
965ebf33
HS		 1309 /*
1310 * Use mirror of ios->clock to prevent race with mmc
1311 * core ios update when finding the minimum.
1312 */
1313 slot->clock = ios->clock;
2c96a293 1314 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
965ebf33
HS		 1315 if (host->slot[i] && host->slot[i]->clock
1316 && host->slot[i]->clock < clock_min)
1317 clock_min = host->slot[i]->clock;
1318 }
1319
1320 /* Calculate clock divider */
faf8180b
LD		 1321 if (host->caps.has_odd_clk_div) {
1322 clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2;
a72719d7
LD		 1323 if (clkdiv < 0) {
1324 dev_warn(&mmc->class_dev,
1325 "clock %u too fast; using %lu\n",
1326 clock_min, host->bus_hz / 2);
1327 clkdiv = 0;
1328 } else if (clkdiv > 511) {
faf8180b
LD		 1329 dev_warn(&mmc->class_dev,
1330 "clock %u too slow; using %lu\n",
1331 clock_min, host->bus_hz / (511 + 2));
1332 clkdiv = 511;
1333 }
1334 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1)
1335 | ATMCI_MR_CLKODD(clkdiv & 1);
1336 } else {
1337 clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
1338 if (clkdiv > 255) {
1339 dev_warn(&mmc->class_dev,
1340 "clock %u too slow; using %lu\n",
1341 clock_min, host->bus_hz / (2 * 256));
1342 clkdiv = 255;
1343 }
1344 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
7d2be074
HS		 1345 }
1346
965ebf33
HS		 1347 /*
1348 * WRPROOF and RDPROOF prevent overruns/underruns by
1349 * stopping the clock when the FIFO is full/empty.
1350 * This state is not expected to last for long.
1351 */
796211b7 1352 if (host->caps.has_rwproof)
2c96a293 1353 host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF);
7d2be074 1354
796211b7 1355 if (host->caps.has_cfg_reg) {
99ddffd8
NF		 1356 /* setup High Speed mode in relation with card capacity */
1357 if (ios->timing == MMC_TIMING_SD_HS)
2c96a293 1358 host->cfg_reg |= ATMCI_CFG_HSMODE;
99ddffd8 1359 else
2c96a293 1360 host->cfg_reg &= ~ATMCI_CFG_HSMODE;
99ddffd8
NF		 1361 }
1362
1363 if (list_empty(&host->queue)) {
03fc9a7f 1364 atmci_writel(host, ATMCI_MR, host->mode_reg);
796211b7 1365 if (host->caps.has_cfg_reg)
03fc9a7f 1366 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
99ddffd8 1367 } else {
965ebf33 1368 host->need_clock_update = true;
99ddffd8 1369 }
965ebf33
HS		 1370
1371 spin_unlock_bh(&host->lock);
945533b5 1372 } else {
965ebf33
HS		 1373 bool any_slot_active = false;
1374
1375 spin_lock_bh(&host->lock);
1376 slot->clock = 0;
2c96a293 1377 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
965ebf33
HS		 1378 if (host->slot[i] && host->slot[i]->clock) {
1379 any_slot_active = true;
1380 break;
1381 }
945533b5 1382 }
965ebf33 1383 if (!any_slot_active) {
03fc9a7f 1384 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
965ebf33 1385 if (host->mode_reg) {
03fc9a7f 1386 atmci_readl(host, ATMCI_MR);
965ebf33
HS		 1387 clk_disable(host->mck);
1388 }
1389 host->mode_reg = 0;
1390 }
1391 spin_unlock_bh(&host->lock);
7d2be074
HS		 1392 }
1393
1394 switch (ios->power_mode) {
965ebf33
HS		 1395 case MMC_POWER_UP:
1396 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
1397 break;
7d2be074
HS		 1398 default:
1399 /*
1400 * TODO: None of the currently available AVR32-based
1401 * boards allow MMC power to be turned off. Implement
1402 * power control when this can be tested properly.
965ebf33
HS		 1403 *
1404 * We also need to hook this into the clock management
1405 * somehow so that newly inserted cards aren't
1406 * subjected to a fast clock before we have a chance
1407 * to figure out what the maximum rate is. Currently,
1408 * there's no way to avoid this, and there never will
1409 * be for boards that don't support power control.
7d2be074
HS		 1410 */
1411 break;
1412 }
1413}
1414
1415static int atmci_get_ro(struct mmc_host *mmc)
1416{
965ebf33
HS		 1417 int read_only = -ENOSYS;
1418 struct atmel_mci_slot *slot = mmc_priv(mmc);
7d2be074 1419
965ebf33
HS		 1420 if (gpio_is_valid(slot->wp_pin)) {
1421 read_only = gpio_get_value(slot->wp_pin);
7d2be074
HS		 1422 dev_dbg(&mmc->class_dev, "card is %s\n",
1423 read_only ? "read-only" : "read-write");
7d2be074
HS		 1424 }
1425
1426 return read_only;
1427}
1428
965ebf33
HS		 1429static int atmci_get_cd(struct mmc_host *mmc)
1430{
1431 int present = -ENOSYS;
1432 struct atmel_mci_slot *slot = mmc_priv(mmc);
1433
1434 if (gpio_is_valid(slot->detect_pin)) {
1c1452be
JL		 1435 present = !(gpio_get_value(slot->detect_pin) ^
1436 slot->detect_is_active_high);
965ebf33
HS		 1437 dev_dbg(&mmc->class_dev, "card is %spresent\n",
1438 present ? "" : "not ");
1439 }
1440
1441 return present;
1442}
1443
88ff82ed
AG		 1444static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1445{
1446 struct atmel_mci_slot *slot = mmc_priv(mmc);
1447 struct atmel_mci *host = slot->host;
1448
1449 if (enable)
03fc9a7f 1450 atmci_writel(host, ATMCI_IER, slot->sdio_irq);
88ff82ed 1451 else
03fc9a7f 1452 atmci_writel(host, ATMCI_IDR, slot->sdio_irq);
88ff82ed
AG		 1453}
1454
965ebf33 1455static const struct mmc_host_ops atmci_ops = {
7d2be074
HS		 1456 .request = atmci_request,
1457 .set_ios = atmci_set_ios,
1458 .get_ro = atmci_get_ro,
965ebf33 1459 .get_cd = atmci_get_cd,
88ff82ed 1460 .enable_sdio_irq = atmci_enable_sdio_irq,
7d2be074
HS		 1461};
1462
965ebf33
HS		 1463/* Called with host->lock held */
1464static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
1465 __releases(&host->lock)
1466 __acquires(&host->lock)
1467{
1468 struct atmel_mci_slot *slot = NULL;
1469 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1470
1471 WARN_ON(host->cmd || host->data);
1472
1473 /*
1474 * Update the MMC clock rate if necessary. This may be
1475 * necessary if set_ios() is called when a different slot is
25985edc 1476 * busy transferring data.
965ebf33 1477 */
99ddffd8 1478 if (host->need_clock_update) {
03fc9a7f 1479 atmci_writel(host, ATMCI_MR, host->mode_reg);
796211b7 1480 if (host->caps.has_cfg_reg)
03fc9a7f 1481 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
99ddffd8 1482 }
965ebf33
HS		 1483
1484 host->cur_slot->mrq = NULL;
1485 host->mrq = NULL;
1486 if (!list_empty(&host->queue)) {
1487 slot = list_entry(host->queue.next,
1488 struct atmel_mci_slot, queue_node);
1489 list_del(&slot->queue_node);
1490 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
1491 mmc_hostname(slot->mmc));
1492 host->state = STATE_SENDING_CMD;
1493 atmci_start_request(host, slot);
1494 } else {
1495 dev_vdbg(&host->pdev->dev, "list empty\n");
1496 host->state = STATE_IDLE;
1497 }
1498
24011f34
LD		 1499 del_timer(&host->timer);
1500
965ebf33
HS		 1501 spin_unlock(&host->lock);
1502 mmc_request_done(prev_mmc, mrq);
1503 spin_lock(&host->lock);
1504}
1505
7d2be074 1506static void atmci_command_complete(struct atmel_mci *host,
c06ad258 1507 struct mmc_command *cmd)
7d2be074 1508{
c06ad258
HS		 1509 u32 status = host->cmd_status;
1510
7d2be074 1511 /* Read the response from the card (up to 16 bytes) */
03fc9a7f
LD		 1512 cmd->resp[0] = atmci_readl(host, ATMCI_RSPR);
1513 cmd->resp[1] = atmci_readl(host, ATMCI_RSPR);
1514 cmd->resp[2] = atmci_readl(host, ATMCI_RSPR);
1515 cmd->resp[3] = atmci_readl(host, ATMCI_RSPR);
7d2be074 1516
2c96a293 1517 if (status & ATMCI_RTOE)
7d2be074 1518 cmd->error = -ETIMEDOUT;
2c96a293 1519 else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE))
7d2be074 1520 cmd->error = -EILSEQ;
2c96a293 1521 else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE))
7d2be074 1522 cmd->error = -EIO;
24011f34
LD		 1523 else if (host->mrq->data && (host->mrq->data->blksz & 3)) {
1524 if (host->caps.need_blksz_mul_4) {
1525 cmd->error = -EINVAL;
1526 host->need_reset = 1;
1527 }
1528 } else
7d2be074 1529 cmd->error = 0;
7d2be074
HS		 1530}
1531
1532static void atmci_detect_change(unsigned long data)
1533{
965ebf33
HS		 1534 struct atmel_mci_slot *slot = (struct atmel_mci_slot *)data;
1535 bool present;
1536 bool present_old;
7d2be074
HS		 1537
1538 /*
965ebf33
HS		 1539 * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
1540 * freeing the interrupt. We must not re-enable the interrupt
1541 * if it has been freed, and if we're shutting down, it
1542 * doesn't really matter whether the card is present or not.
7d2be074
HS		 1543 */
1544 smp_rmb();
965ebf33 1545 if (test_bit(ATMCI_SHUTDOWN, &slot->flags))
7d2be074
HS		 1546 return;
1547
965ebf33 1548 enable_irq(gpio_to_irq(slot->detect_pin));
1c1452be
JL		 1549 present = !(gpio_get_value(slot->detect_pin) ^
1550 slot->detect_is_active_high);
965ebf33 1551 present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
7d2be074 1552
965ebf33
HS		 1553 dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
1554 present, present_old);
7d2be074 1555
965ebf33
HS		 1556 if (present != present_old) {
1557 struct atmel_mci *host = slot->host;
1558 struct mmc_request *mrq;
1559
1560 dev_dbg(&slot->mmc->class_dev, "card %s\n",
7d2be074 1561 present ? "inserted" : "removed");
7d2be074 1562
965ebf33
HS		 1563 spin_lock(&host->lock);
1564
1565 if (!present)
1566 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1567 else
1568 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
7d2be074
HS		 1569
1570 /* Clean up queue if present */
965ebf33 1571 mrq = slot->mrq;
7d2be074 1572 if (mrq) {
965ebf33
HS		 1573 if (mrq == host->mrq) {
1574 /*
1575 * Reset controller to terminate any ongoing
1576 * commands or data transfers.
1577 */
03fc9a7f
LD		 1578 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1579 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1580 atmci_writel(host, ATMCI_MR, host->mode_reg);
796211b7 1581 if (host->caps.has_cfg_reg)
03fc9a7f 1582 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
965ebf33
HS		 1583
1584 host->data = NULL;
1585 host->cmd = NULL;
1586
1587 switch (host->state) {
1588 case STATE_IDLE:
c06ad258 1589 break;
965ebf33
HS		 1590 case STATE_SENDING_CMD:
1591 mrq->cmd->error = -ENOMEDIUM;
f5177547
LD		 1592 if (mrq->data)
1593 host->stop_transfer(host);
1594 break;
1595 case STATE_DATA_XFER:
c06ad258 1596 mrq->data->error = -ENOMEDIUM;
796211b7 1597 host->stop_transfer(host);
c06ad258 1598 break;
f5177547
LD		 1599 case STATE_WAITING_NOTBUSY:
1600 mrq->data->error = -ENOMEDIUM;
1601 break;
965ebf33
HS		 1602 case STATE_SENDING_STOP:
1603 mrq->stop->error = -ENOMEDIUM;
1604 break;
f5177547
LD		 1605 case STATE_END_REQUEST:
1606 break;
965ebf33 1607 }
7d2be074 1608
965ebf33
HS		 1609 atmci_request_end(host, mrq);
1610 } else {
1611 list_del(&slot->queue_node);
1612 mrq->cmd->error = -ENOMEDIUM;
1613 if (mrq->data)
1614 mrq->data->error = -ENOMEDIUM;
1615 if (mrq->stop)
1616 mrq->stop->error = -ENOMEDIUM;
1617
1618 spin_unlock(&host->lock);
1619 mmc_request_done(slot->mmc, mrq);
1620 spin_lock(&host->lock);
1621 }
7d2be074 1622 }
965ebf33 1623 spin_unlock(&host->lock);
7d2be074 1624
965ebf33 1625 mmc_detect_change(slot->mmc, 0);
7d2be074
HS		 1626 }
1627}
1628
1629static void atmci_tasklet_func(unsigned long priv)
1630{
965ebf33 1631 struct atmel_mci *host = (struct atmel_mci *)priv;
7d2be074
HS		 1632 struct mmc_request *mrq = host->mrq;
1633 struct mmc_data *data = host->data;
c06ad258
HS		 1634 enum atmel_mci_state state = host->state;
1635 enum atmel_mci_state prev_state;
1636 u32 status;
1637
965ebf33
HS		 1638 spin_lock(&host->lock);
1639
c06ad258 1640 state = host->state;
7d2be074 1641
965ebf33 1642 dev_vdbg(&host->pdev->dev,
c06ad258
HS		 1643 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
1644 state, host->pending_events, host->completed_events,
03fc9a7f 1645 atmci_readl(host, ATMCI_IMR));
7d2be074 1646
c06ad258
HS		 1647 do {
1648 prev_state = state;
6801c41a 1649 dev_dbg(&host->pdev->dev, "FSM: state=%d\n", state);
7d2be074 1650
c06ad258 1651 switch (state) {
965ebf33
HS		 1652 case STATE_IDLE:
1653 break;
1654
c06ad258 1655 case STATE_SENDING_CMD:
f5177547
LD		 1656 /*
1657 * Command has been sent, we are waiting for command
1658 * ready. Then we have three next states possible:
1659 * END_REQUEST by default, WAITING_NOTBUSY if it's a
1660 * command needing it or DATA_XFER if there is data.
1661 */
6801c41a 1662 dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
c06ad258 1663 if (!atmci_test_and_clear_pending(host,
f5177547 1664 EVENT_CMD_RDY))
c06ad258 1665 break;
7d2be074 1666
6801c41a 1667 dev_dbg(&host->pdev->dev, "set completed cmd ready\n");
c06ad258 1668 host->cmd = NULL;
f5177547 1669 atmci_set_completed(host, EVENT_CMD_RDY);
c06ad258 1670 atmci_command_complete(host, mrq->cmd);
f5177547 1671 if (mrq->data) {
6801c41a
LD		 1672 dev_dbg(&host->pdev->dev,
1673 "command with data transfer");
f5177547
LD		 1674 /*
1675 * If there is a command error don't start
1676 * data transfer.
1677 */
1678 if (mrq->cmd->error) {
1679 host->stop_transfer(host);
1680 host->data = NULL;
1681 atmci_writel(host, ATMCI_IDR,
1682 ATMCI_TXRDY | ATMCI_RXRDY
1683 | ATMCI_DATA_ERROR_FLAGS);
1684 state = STATE_END_REQUEST;
1685 } else
1686 state = STATE_DATA_XFER;
1687 } else if ((!mrq->data) && (mrq->cmd->flags & MMC_RSP_BUSY)) {
6801c41a
LD		 1688 dev_dbg(&host->pdev->dev,
1689 "command response need waiting notbusy");
f5177547
LD		 1690 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1691 state = STATE_WAITING_NOTBUSY;
1692 } else
1693 state = STATE_END_REQUEST;
7d2be074 1694
f5177547 1695 break;
7d2be074 1696
f5177547 1697 case STATE_DATA_XFER:
c06ad258
HS		 1698 if (atmci_test_and_clear_pending(host,
1699 EVENT_DATA_ERROR)) {
6801c41a 1700 dev_dbg(&host->pdev->dev, "set completed data error\n");
f5177547
LD		 1701 atmci_set_completed(host, EVENT_DATA_ERROR);
1702 state = STATE_END_REQUEST;
c06ad258
HS		 1703 break;
1704 }
7d2be074 1705
f5177547
LD		 1706 /*
1707 * A data transfer is in progress. The event expected
1708 * to move to the next state depends of data transfer
1709 * type (PDC or DMA). Once transfer done we can move
1710 * to the next step which is WAITING_NOTBUSY in write
1711 * case and directly SENDING_STOP in read case.
1712 */
6801c41a 1713 dev_dbg(&host->pdev->dev, "FSM: xfer complete?\n");
c06ad258
HS		 1714 if (!atmci_test_and_clear_pending(host,
1715 EVENT_XFER_COMPLETE))
1716 break;
7d2be074 1717
6801c41a
LD		 1718 dev_dbg(&host->pdev->dev,
1719 "(%s) set completed xfer complete\n",
1720 __func__);
c06ad258 1721 atmci_set_completed(host, EVENT_XFER_COMPLETE);
7d2be074 1722
077d4073
LD		 1723 if (host->caps.need_notbusy_for_read_ops ||
1724 (host->data->flags & MMC_DATA_WRITE)) {
f5177547
LD		 1725 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1726 state = STATE_WAITING_NOTBUSY;
1727 } else if (host->mrq->stop) {
1728 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
1729 atmci_send_stop_cmd(host, data);
1730 state = STATE_SENDING_STOP;
c06ad258 1731 } else {
f5177547 1732 host->data = NULL;
c06ad258
HS		 1733 data->bytes_xfered = data->blocks * data->blksz;
1734 data->error = 0;
f5177547 1735 state = STATE_END_REQUEST;
c06ad258 1736 }
f5177547 1737 break;
c06ad258 1738
f5177547
LD		 1739 case STATE_WAITING_NOTBUSY:
1740 /*
1741 * We can be in the state for two reasons: a command
1742 * requiring waiting not busy signal (stop command
1743 * included) or a write operation. In the latest case,
1744 * we need to send a stop command.
1745 */
6801c41a 1746 dev_dbg(&host->pdev->dev, "FSM: not busy?\n");
f5177547
LD		 1747 if (!atmci_test_and_clear_pending(host,
1748 EVENT_NOTBUSY))
1749 break;
7d2be074 1750
6801c41a 1751 dev_dbg(&host->pdev->dev, "set completed not busy\n");
f5177547
LD		 1752 atmci_set_completed(host, EVENT_NOTBUSY);
1753
1754 if (host->data) {
1755 /*
1756 * For some commands such as CMD53, even if
1757 * there is data transfer, there is no stop
1758 * command to send.
1759 */
1760 if (host->mrq->stop) {
1761 atmci_writel(host, ATMCI_IER,
1762 ATMCI_CMDRDY);
1763 atmci_send_stop_cmd(host, data);
1764 state = STATE_SENDING_STOP;
1765 } else {
1766 host->data = NULL;
1767 data->bytes_xfered = data->blocks
1768 * data->blksz;
1769 data->error = 0;
1770 state = STATE_END_REQUEST;
1771 }
1772 } else
1773 state = STATE_END_REQUEST;
1774 break;
c06ad258
HS		 1775
1776 case STATE_SENDING_STOP:
f5177547
LD		 1777 /*
1778 * In this state, it is important to set host->data to
1779 * NULL (which is tested in the waiting notbusy state)
1780 * in order to go to the end request state instead of
1781 * sending stop again.
1782 */
6801c41a 1783 dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
c06ad258 1784 if (!atmci_test_and_clear_pending(host,
f5177547 1785 EVENT_CMD_RDY))
c06ad258
HS		 1786 break;
1787
6801c41a 1788 dev_dbg(&host->pdev->dev, "FSM: cmd ready\n");
c06ad258 1789 host->cmd = NULL;
f5177547
LD		 1790 data->bytes_xfered = data->blocks * data->blksz;
1791 data->error = 0;
c06ad258 1792 atmci_command_complete(host, mrq->stop);
f5177547
LD		 1793 if (mrq->stop->error) {
1794 host->stop_transfer(host);
1795 atmci_writel(host, ATMCI_IDR,
1796 ATMCI_TXRDY | ATMCI_RXRDY
1797 | ATMCI_DATA_ERROR_FLAGS);
1798 state = STATE_END_REQUEST;
1799 } else {
1800 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1801 state = STATE_WAITING_NOTBUSY;
1802 }
41b4e9a1 1803 host->data = NULL;
f5177547 1804 break;
c06ad258 1805
f5177547
LD		 1806 case STATE_END_REQUEST:
1807 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY | ATMCI_RXRDY
1808 | ATMCI_DATA_ERROR_FLAGS);
1809 status = host->data_status;
1810 if (unlikely(status)) {
1811 host->stop_transfer(host);
1812 host->data = NULL;
63a23e39
RG		 1813 if (data) {
1814 if (status & ATMCI_DTOE) {
1815 data->error = -ETIMEDOUT;
1816 } else if (status & ATMCI_DCRCE) {
1817 data->error = -EILSEQ;
1818 } else {
1819 data->error = -EIO;
1820 }
f5177547
LD		 1821 }
1822 }
c06ad258 1823
f5177547
LD		 1824 atmci_request_end(host, host->mrq);
1825 state = STATE_IDLE;
c06ad258
HS		 1826 break;
1827 }
1828 } while (state != prev_state);
1829
1830 host->state = state;
965ebf33 1831
965ebf33 1832 spin_unlock(&host->lock);
7d2be074
HS		 1833}
1834
1835static void atmci_read_data_pio(struct atmel_mci *host)
1836{
1837 struct scatterlist *sg = host->sg;
1838 void *buf = sg_virt(sg);
1839 unsigned int offset = host->pio_offset;
1840 struct mmc_data *data = host->data;
1841 u32 value;
1842 u32 status;
1843 unsigned int nbytes = 0;
1844
1845 do {
03fc9a7f 1846 value = atmci_readl(host, ATMCI_RDR);
7d2be074
HS		 1847 if (likely(offset + 4 <= sg->length)) {
1848 put_unaligned(value, (u32 *)(buf + offset));
1849
1850 offset += 4;
1851 nbytes += 4;
1852
1853 if (offset == sg->length) {
5e7184ae 1854 flush_dcache_page(sg_page(sg));
7d2be074 1855 host->sg = sg = sg_next(sg);
bdbc5d0c
TB		 1856 host->sg_len--;
1857 if (!sg || !host->sg_len)
7d2be074
HS		 1858 goto done;
1859
1860 offset = 0;
1861 buf = sg_virt(sg);
1862 }
1863 } else {
1864 unsigned int remaining = sg->length - offset;
1865 memcpy(buf + offset, &value, remaining);
1866 nbytes += remaining;
1867
1868 flush_dcache_page(sg_page(sg));
1869 host->sg = sg = sg_next(sg);
bdbc5d0c
TB		 1870 host->sg_len--;
1871 if (!sg || !host->sg_len)
7d2be074
HS		 1872 goto done;
1873
1874 offset = 4 - remaining;
1875 buf = sg_virt(sg);
1876 memcpy(buf, (u8 *)&value + remaining, offset);
1877 nbytes += offset;
1878 }
1879
03fc9a7f 1880 status = atmci_readl(host, ATMCI_SR);
7d2be074 1881 if (status & ATMCI_DATA_ERROR_FLAGS) {
03fc9a7f 1882 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY
7d2be074
HS		 1883 | ATMCI_DATA_ERROR_FLAGS));
1884 host->data_status = status;
965ebf33 1885 data->bytes_xfered += nbytes;
965ebf33 1886 return;
7d2be074 1887 }
2c96a293 1888 } while (status & ATMCI_RXRDY);
7d2be074
HS		 1889
1890 host->pio_offset = offset;
1891 data->bytes_xfered += nbytes;
1892
1893 return;
1894
1895done:
03fc9a7f
LD		 1896 atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY);
1897 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
7d2be074 1898 data->bytes_xfered += nbytes;
965ebf33 1899 smp_wmb();
c06ad258 1900 atmci_set_pending(host, EVENT_XFER_COMPLETE);
7d2be074
HS		 1901}
1902
1903static void atmci_write_data_pio(struct atmel_mci *host)
1904{
1905 struct scatterlist *sg = host->sg;
1906 void *buf = sg_virt(sg);
1907 unsigned int offset = host->pio_offset;
1908 struct mmc_data *data = host->data;
1909 u32 value;
1910 u32 status;
1911 unsigned int nbytes = 0;
1912
1913 do {
1914 if (likely(offset + 4 <= sg->length)) {
1915 value = get_unaligned((u32 *)(buf + offset));
03fc9a7f 1916 atmci_writel(host, ATMCI_TDR, value);
7d2be074
HS		 1917
1918 offset += 4;
1919 nbytes += 4;
1920 if (offset == sg->length) {
1921 host->sg = sg = sg_next(sg);
bdbc5d0c
TB		 1922 host->sg_len--;
1923 if (!sg || !host->sg_len)
7d2be074
HS		 1924 goto done;
1925
1926 offset = 0;
1927 buf = sg_virt(sg);
1928 }
1929 } else {
1930 unsigned int remaining = sg->length - offset;
1931
1932 value = 0;
1933 memcpy(&value, buf + offset, remaining);
1934 nbytes += remaining;
1935
1936 host->sg = sg = sg_next(sg);
bdbc5d0c
TB		 1937 host->sg_len--;
1938 if (!sg || !host->sg_len) {
03fc9a7f 1939 atmci_writel(host, ATMCI_TDR, value);
7d2be074
HS		 1940 goto done;
1941 }
1942
1943 offset = 4 - remaining;
1944 buf = sg_virt(sg);
1945 memcpy((u8 *)&value + remaining, buf, offset);
03fc9a7f 1946 atmci_writel(host, ATMCI_TDR, value);
7d2be074
HS		 1947 nbytes += offset;
1948 }
1949
03fc9a7f 1950 status = atmci_readl(host, ATMCI_SR);
7d2be074 1951 if (status & ATMCI_DATA_ERROR_FLAGS) {
03fc9a7f 1952 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY
7d2be074
HS		 1953 | ATMCI_DATA_ERROR_FLAGS));
1954 host->data_status = status;
965ebf33 1955 data->bytes_xfered += nbytes;
965ebf33 1956 return;
7d2be074 1957 }
2c96a293 1958 } while (status & ATMCI_TXRDY);
7d2be074
HS		 1959
1960 host->pio_offset = offset;
1961 data->bytes_xfered += nbytes;
1962
1963 return;
1964
1965done:
03fc9a7f
LD		 1966 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY);
1967 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
7d2be074 1968 data->bytes_xfered += nbytes;
965ebf33 1969 smp_wmb();
c06ad258 1970 atmci_set_pending(host, EVENT_XFER_COMPLETE);
7d2be074
HS		 1971}
1972
88ff82ed
AG		 1973static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status)
1974{
1975 int i;
1976
2c96a293 1977 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
88ff82ed
AG		 1978 struct atmel_mci_slot *slot = host->slot[i];
1979 if (slot && (status & slot->sdio_irq)) {
1980 mmc_signal_sdio_irq(slot->mmc);
1981 }
1982 }
1983}
1984
1985
7d2be074
HS		 1986static irqreturn_t atmci_interrupt(int irq, void *dev_id)
1987{
965ebf33 1988 struct atmel_mci *host = dev_id;
7d2be074
HS		 1989 u32 status, mask, pending;
1990 unsigned int pass_count = 0;
1991
7d2be074 1992 do {
03fc9a7f
LD		 1993 status = atmci_readl(host, ATMCI_SR);
1994 mask = atmci_readl(host, ATMCI_IMR);
7d2be074
HS		 1995 pending = status & mask;
1996 if (!pending)
1997 break;
1998
1999 if (pending & ATMCI_DATA_ERROR_FLAGS) {
6801c41a 2000 dev_dbg(&host->pdev->dev, "IRQ: data error\n");
03fc9a7f 2001 atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS
f5177547
LD		 2002 | ATMCI_RXRDY | ATMCI_TXRDY
2003 | ATMCI_ENDRX | ATMCI_ENDTX
2004 | ATMCI_RXBUFF | ATMCI_TXBUFE);
965ebf33 2005
7d2be074 2006 host->data_status = status;
6801c41a 2007 dev_dbg(&host->pdev->dev, "set pending data error\n");
965ebf33 2008 smp_wmb();
7d2be074
HS		 2009 atmci_set_pending(host, EVENT_DATA_ERROR);
2010 tasklet_schedule(&host->tasklet);
2011 }
796211b7 2012
796211b7 2013 if (pending & ATMCI_TXBUFE) {
6801c41a 2014 dev_dbg(&host->pdev->dev, "IRQ: tx buffer empty\n");
796211b7 2015 atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE);
7e8ba228 2016 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
796211b7
LD		 2017 /*
2018 * We can receive this interruption before having configured
2019 * the second pdc buffer, so we need to reconfigure first and
2020 * second buffers again
2021 */
2022 if (host->data_size) {
2023 atmci_pdc_set_both_buf(host, XFER_TRANSMIT);
7e8ba228 2024 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
796211b7
LD		 2025 atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE);
2026 } else {
2027 atmci_pdc_complete(host);
2028 }
7e8ba228 2029 } else if (pending & ATMCI_ENDTX) {
6801c41a 2030 dev_dbg(&host->pdev->dev, "IRQ: end of tx buffer\n");
7e8ba228 2031 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
796211b7
LD		 2032
2033 if (host->data_size) {
2034 atmci_pdc_set_single_buf(host,
7e8ba228
LD		 2035 XFER_TRANSMIT, PDC_SECOND_BUF);
2036 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
796211b7
LD		 2037 }
2038 }
2039
2040 if (pending & ATMCI_RXBUFF) {
6801c41a 2041 dev_dbg(&host->pdev->dev, "IRQ: rx buffer full\n");
796211b7 2042 atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF);
7e8ba228 2043 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
796211b7
LD		 2044 /*
2045 * We can receive this interruption before having configured
2046 * the second pdc buffer, so we need to reconfigure first and
2047 * second buffers again
2048 */
2049 if (host->data_size) {
2050 atmci_pdc_set_both_buf(host, XFER_RECEIVE);
7e8ba228 2051 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
796211b7
LD		 2052 atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF);
2053 } else {
2054 atmci_pdc_complete(host);
2055 }
7e8ba228 2056 } else if (pending & ATMCI_ENDRX) {
6801c41a 2057 dev_dbg(&host->pdev->dev, "IRQ: end of rx buffer\n");
7e8ba228
LD		 2058 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2059
2060 if (host->data_size) {
2061 atmci_pdc_set_single_buf(host,
2062 XFER_RECEIVE, PDC_SECOND_BUF);
2063 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2064 }
796211b7
LD		 2065 }
2066
f5177547
LD		 2067 /*
2068 * First mci IPs, so mainly the ones having pdc, have some
2069 * issues with the notbusy signal. You can't get it after
2070 * data transmission if you have not sent a stop command.
2071 * The appropriate workaround is to use the BLKE signal.
2072 */
2073 if (pending & ATMCI_BLKE) {
6801c41a 2074 dev_dbg(&host->pdev->dev, "IRQ: blke\n");
f5177547
LD		 2075 atmci_writel(host, ATMCI_IDR, ATMCI_BLKE);
2076 smp_wmb();
6801c41a 2077 dev_dbg(&host->pdev->dev, "set pending notbusy\n");
f5177547
LD		 2078 atmci_set_pending(host, EVENT_NOTBUSY);
2079 tasklet_schedule(&host->tasklet);
2080 }
7e8ba228 2081
2c96a293 2082 if (pending & ATMCI_NOTBUSY) {
6801c41a 2083 dev_dbg(&host->pdev->dev, "IRQ: not_busy\n");
f5177547 2084 atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY);
965ebf33 2085 smp_wmb();
6801c41a 2086 dev_dbg(&host->pdev->dev, "set pending notbusy\n");
f5177547 2087 atmci_set_pending(host, EVENT_NOTBUSY);
7d2be074
HS		 2088 tasklet_schedule(&host->tasklet);
2089 }
f5177547 2090
2c96a293 2091 if (pending & ATMCI_RXRDY)
7d2be074 2092 atmci_read_data_pio(host);
2c96a293 2093 if (pending & ATMCI_TXRDY)
7d2be074
HS		 2094 atmci_write_data_pio(host);
2095
f5177547 2096 if (pending & ATMCI_CMDRDY) {
6801c41a 2097 dev_dbg(&host->pdev->dev, "IRQ: cmd ready\n");
f5177547
LD		 2098 atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY);
2099 host->cmd_status = status;
2100 smp_wmb();
6801c41a 2101 dev_dbg(&host->pdev->dev, "set pending cmd rdy\n");
f5177547
LD		 2102 atmci_set_pending(host, EVENT_CMD_RDY);
2103 tasklet_schedule(&host->tasklet);
2104 }
88ff82ed 2105
2c96a293 2106 if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
88ff82ed
AG		 2107 atmci_sdio_interrupt(host, status);
2108
7d2be074
HS		 2109 } while (pass_count++ < 5);
2110
7d2be074
HS		 2111 return pass_count ? IRQ_HANDLED : IRQ_NONE;
2112}
2113
2114static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
2115{
965ebf33 2116 struct atmel_mci_slot *slot = dev_id;
7d2be074
HS		 2117
2118 /*
2119 * Disable interrupts until the pin has stabilized and check
2120 * the state then. Use mod_timer() since we may be in the
2121 * middle of the timer routine when this interrupt triggers.
2122 */
2123 disable_irq_nosync(irq);
965ebf33 2124 mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20));
7d2be074
HS		 2125
2126 return IRQ_HANDLED;
2127}
2128
965ebf33
HS		 2129static int __init atmci_init_slot(struct atmel_mci *host,
2130 struct mci_slot_pdata *slot_data, unsigned int id,
88ff82ed 2131 u32 sdc_reg, u32 sdio_irq)
965ebf33
HS		 2132{
2133 struct mmc_host *mmc;
2134 struct atmel_mci_slot *slot;
2135
2136 mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev);
2137 if (!mmc)
2138 return -ENOMEM;
2139
2140 slot = mmc_priv(mmc);
2141 slot->mmc = mmc;
2142 slot->host = host;
2143 slot->detect_pin = slot_data->detect_pin;
2144 slot->wp_pin = slot_data->wp_pin;
1c1452be 2145 slot->detect_is_active_high = slot_data->detect_is_active_high;
965ebf33 2146 slot->sdc_reg = sdc_reg;
88ff82ed 2147 slot->sdio_irq = sdio_irq;
965ebf33 2148
e919fd20
LD		 2149 dev_dbg(&mmc->class_dev,
2150 "slot[%u]: bus_width=%u, detect_pin=%d, "
2151 "detect_is_active_high=%s, wp_pin=%d\n",
2152 id, slot_data->bus_width, slot_data->detect_pin,
2153 slot_data->detect_is_active_high ? "true" : "false",
2154 slot_data->wp_pin);
2155
965ebf33
HS		 2156 mmc->ops = &atmci_ops;
2157 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
2158 mmc->f_max = host->bus_hz / 2;
2159 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
88ff82ed
AG		 2160 if (sdio_irq)
2161 mmc->caps |= MMC_CAP_SDIO_IRQ;
796211b7 2162 if (host->caps.has_highspeed)
99ddffd8 2163 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
7a90dcc2
LD		 2164 /*
2165 * Without the read/write proof capability, it is strongly suggested to
2166 * use only one bit for data to prevent fifo underruns and overruns
2167 * which will corrupt data.
2168 */
2169 if ((slot_data->bus_width >= 4) && host->caps.has_rwproof)
965ebf33
HS		 2170 mmc->caps |= MMC_CAP_4_BIT_DATA;
2171
7a90dcc2
LD		 2172 if (atmci_get_version(host) < 0x200) {
2173 mmc->max_segs = 256;
2174 mmc->max_blk_size = 4095;
2175 mmc->max_blk_count = 256;
2176 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2177 mmc->max_seg_size = mmc->max_blk_size * mmc->max_segs;
2178 } else {
2179 mmc->max_segs = 64;
2180 mmc->max_req_size = 32768 * 512;
2181 mmc->max_blk_size = 32768;
2182 mmc->max_blk_count = 512;
2183 }
965ebf33
HS		 2184
2185 /* Assume card is present initially */
2186 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
2187 if (gpio_is_valid(slot->detect_pin)) {
2188 if (gpio_request(slot->detect_pin, "mmc_detect")) {
2189 dev_dbg(&mmc->class_dev, "no detect pin available\n");
2190 slot->detect_pin = -EBUSY;
1c1452be
JL		 2191 } else if (gpio_get_value(slot->detect_pin) ^
2192 slot->detect_is_active_high) {
965ebf33
HS		 2193 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
2194 }
2195 }
2196
2197 if (!gpio_is_valid(slot->detect_pin))
2198 mmc->caps |= MMC_CAP_NEEDS_POLL;
2199
2200 if (gpio_is_valid(slot->wp_pin)) {
2201 if (gpio_request(slot->wp_pin, "mmc_wp")) {
2202 dev_dbg(&mmc->class_dev, "no WP pin available\n");
2203 slot->wp_pin = -EBUSY;
2204 }
2205 }
2206
2207 host->slot[id] = slot;
2208 mmc_add_host(mmc);
2209
2210 if (gpio_is_valid(slot->detect_pin)) {
2211 int ret;
2212
2213 setup_timer(&slot->detect_timer, atmci_detect_change,
2214 (unsigned long)slot);
2215
2216 ret = request_irq(gpio_to_irq(slot->detect_pin),
2217 atmci_detect_interrupt,
2218 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
2219 "mmc-detect", slot);
2220 if (ret) {
2221 dev_dbg(&mmc->class_dev,
2222 "could not request IRQ %d for detect pin\n",
2223 gpio_to_irq(slot->detect_pin));
2224 gpio_free(slot->detect_pin);
2225 slot->detect_pin = -EBUSY;
2226 }
2227 }
2228
2229 atmci_init_debugfs(slot);
2230
2231 return 0;
2232}
2233
2234static void __exit atmci_cleanup_slot(struct atmel_mci_slot *slot,
2235 unsigned int id)
2236{
2237 /* Debugfs stuff is cleaned up by mmc core */
2238
2239 set_bit(ATMCI_SHUTDOWN, &slot->flags);
2240 smp_wmb();
2241
2242 mmc_remove_host(slot->mmc);
2243
2244 if (gpio_is_valid(slot->detect_pin)) {
2245 int pin = slot->detect_pin;
2246
2247 free_irq(gpio_to_irq(pin), slot);
2248 del_timer_sync(&slot->detect_timer);
2249 gpio_free(pin);
2250 }
2251 if (gpio_is_valid(slot->wp_pin))
2252 gpio_free(slot->wp_pin);
2253
2254 slot->host->slot[id] = NULL;
2255 mmc_free_host(slot->mmc);
2256}
2257
8c964df0 2258static bool atmci_filter(struct dma_chan *chan, void *pdata)
74465b4f 2259{
8c964df0
LD		 2260 struct mci_platform_data *sl_pdata = pdata;
2261 struct mci_dma_data *sl;
74465b4f 2262
8c964df0
LD		 2263 if (!sl_pdata)
2264 return false;
2265
2266 sl = sl_pdata->dma_slave;
2635d1ba
NF		 2267 if (sl && find_slave_dev(sl) == chan->device->dev) {
2268 chan->private = slave_data_ptr(sl);
7dd60251 2269 return true;
2635d1ba 2270 } else {
7dd60251 2271 return false;
2635d1ba 2272 }
74465b4f 2273}
2635d1ba 2274
ef878198 2275static bool atmci_configure_dma(struct atmel_mci *host)
2635d1ba
NF		 2276{
2277 struct mci_platform_data *pdata;
8c964df0 2278 dma_cap_mask_t mask;
2635d1ba
NF		 2279
2280 if (host == NULL)
ef878198 2281 return false;
2635d1ba
NF		 2282
2283 pdata = host->pdev->dev.platform_data;
2284
8c964df0
LD		 2285 dma_cap_zero(mask);
2286 dma_cap_set(DMA_SLAVE, mask);
ccdfe612 2287
8c964df0
LD		 2288 host->dma.chan = dma_request_slave_channel_compat(mask, atmci_filter, pdata,
2289 &host->pdev->dev, "rxtx");
ef878198
LD		 2290 if (!host->dma.chan) {
2291 dev_warn(&host->pdev->dev, "no DMA channel available\n");
2292 return false;
2293 } else {
74791a2d 2294 dev_info(&host->pdev->dev,
b81cfc41 2295 "using %s for DMA transfers\n",
74791a2d 2296 dma_chan_name(host->dma.chan));
e2b35f3d
VK		 2297
2298 host->dma_conf.src_addr = host->mapbase + ATMCI_RDR;
2299 host->dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2300 host->dma_conf.src_maxburst = 1;
2301 host->dma_conf.dst_addr = host->mapbase + ATMCI_TDR;
2302 host->dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2303 host->dma_conf.dst_maxburst = 1;
2304 host->dma_conf.device_fc = false;
ef878198
LD		 2305 return true;
2306 }
2635d1ba 2307}
796211b7 2308
796211b7
LD		 2309/*
2310 * HSMCI (High Speed MCI) module is not fully compatible with MCI module.
2311 * HSMCI provides DMA support and a new config register but no more supports
2312 * PDC.
2313 */
2314static void __init atmci_get_cap(struct atmel_mci *host)
2315{
2316 unsigned int version;
2317
2318 version = atmci_get_version(host);
2319 dev_info(&host->pdev->dev,
2320 "version: 0x%x\n", version);
2321
ccdfe612 2322 host->caps.has_dma_conf_reg = 0;
6bf2af8c 2323 host->caps.has_pdc = ATMCI_PDC_CONNECTED;
796211b7
LD		 2324 host->caps.has_cfg_reg = 0;
2325 host->caps.has_cstor_reg = 0;
2326 host->caps.has_highspeed = 0;
2327 host->caps.has_rwproof = 0;
faf8180b 2328 host->caps.has_odd_clk_div = 0;
24011f34
LD		 2329 host->caps.has_bad_data_ordering = 1;
2330 host->caps.need_reset_after_xfer = 1;
2331 host->caps.need_blksz_mul_4 = 1;
077d4073 2332 host->caps.need_notbusy_for_read_ops = 0;
796211b7
LD		 2333
2334 /* keep only major version number */
2335 switch (version & 0xf00) {
796211b7 2336 case 0x500:
faf8180b
LD		 2337 host->caps.has_odd_clk_div = 1;
2338 case 0x400:
2339 case 0x300:
ccdfe612 2340 host->caps.has_dma_conf_reg = 1;
faf8180b 2341 host->caps.has_pdc = 0;
796211b7
LD		 2342 host->caps.has_cfg_reg = 1;
2343 host->caps.has_cstor_reg = 1;
2344 host->caps.has_highspeed = 1;
faf8180b 2345 case 0x200:
796211b7 2346 host->caps.has_rwproof = 1;
24011f34 2347 host->caps.need_blksz_mul_4 = 0;
077d4073 2348 host->caps.need_notbusy_for_read_ops = 1;
faf8180b 2349 case 0x100:
24011f34
LD		 2350 host->caps.has_bad_data_ordering = 0;
2351 host->caps.need_reset_after_xfer = 0;
2352 case 0x0:
796211b7
LD		 2353 break;
2354 default:
faf8180b 2355 host->caps.has_pdc = 0;
796211b7
LD		 2356 dev_warn(&host->pdev->dev,
2357 "Unmanaged mci version, set minimum capabilities\n");
2358 break;
2359 }
2360}
74465b4f 2361
7d2be074
HS		 2362static int __init atmci_probe(struct platform_device *pdev)
2363{
2364 struct mci_platform_data *pdata;
965ebf33
HS		 2365 struct atmel_mci *host;
2366 struct resource *regs;
2367 unsigned int nr_slots;
2368 int irq;
2369 int ret;
7d2be074
HS		 2370
2371 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2372 if (!regs)
2373 return -ENXIO;
2374 pdata = pdev->dev.platform_data;
e919fd20
LD		 2375 if (!pdata) {
2376 pdata = atmci_of_init(pdev);
2377 if (IS_ERR(pdata)) {
2378 dev_err(&pdev->dev, "platform data not available\n");
2379 return PTR_ERR(pdata);
2380 }
2381 }
2382
7d2be074
HS		 2383 irq = platform_get_irq(pdev, 0);
2384 if (irq < 0)
2385 return irq;
2386
965ebf33
HS		 2387 host = kzalloc(sizeof(struct atmel_mci), GFP_KERNEL);
2388 if (!host)
7d2be074
HS		 2389 return -ENOMEM;
2390
7d2be074 2391 host->pdev = pdev;
965ebf33
HS		 2392 spin_lock_init(&host->lock);
2393 INIT_LIST_HEAD(&host->queue);
7d2be074
HS		 2394
2395 host->mck = clk_get(&pdev->dev, "mci_clk");
2396 if (IS_ERR(host->mck)) {
2397 ret = PTR_ERR(host->mck);
2398 goto err_clk_get;
2399 }
2400
2401 ret = -ENOMEM;
e8e3f6ca 2402 host->regs = ioremap(regs->start, resource_size(regs));
7d2be074
HS		 2403 if (!host->regs)
2404 goto err_ioremap;
2405
2406 clk_enable(host->mck);
03fc9a7f 2407 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
7d2be074
HS		 2408 host->bus_hz = clk_get_rate(host->mck);
2409 clk_disable(host->mck);
2410
2411 host->mapbase = regs->start;
2412
965ebf33 2413 tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host);
7d2be074 2414
89c8aa20 2415 ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host);
7d2be074
HS		 2416 if (ret)
2417 goto err_request_irq;
2418
796211b7
LD		 2419 /* Get MCI capabilities and set operations according to it */
2420 atmci_get_cap(host);
ccdfe612 2421 if (atmci_configure_dma(host)) {
796211b7
LD		 2422 host->prepare_data = &atmci_prepare_data_dma;
2423 host->submit_data = &atmci_submit_data_dma;
2424 host->stop_transfer = &atmci_stop_transfer_dma;
2425 } else if (host->caps.has_pdc) {
2426 dev_info(&pdev->dev, "using PDC\n");
2427 host->prepare_data = &atmci_prepare_data_pdc;
2428 host->submit_data = &atmci_submit_data_pdc;
2429 host->stop_transfer = &atmci_stop_transfer_pdc;
2430 } else {
ef878198 2431 dev_info(&pdev->dev, "using PIO\n");
796211b7
LD		 2432 host->prepare_data = &atmci_prepare_data;
2433 host->submit_data = &atmci_submit_data;
2434 host->stop_transfer = &atmci_stop_transfer;
2435 }
2436
7d2be074
HS		 2437 platform_set_drvdata(pdev, host);
2438
b87cc1b5
LD		 2439 setup_timer(&host->timer, atmci_timeout_timer, (unsigned long)host);
2440
965ebf33
HS		 2441 /* We need at least one slot to succeed */
2442 nr_slots = 0;
2443 ret = -ENODEV;
2444 if (pdata->slot[0].bus_width) {
2445 ret = atmci_init_slot(host, &pdata->slot[0],
2c96a293 2446 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA);
7a90dcc2 2447 if (!ret) {
965ebf33 2448 nr_slots++;
7a90dcc2
LD		 2449 host->buf_size = host->slot[0]->mmc->max_req_size;
2450 }
965ebf33
HS		 2451 }
2452 if (pdata->slot[1].bus_width) {
2453 ret = atmci_init_slot(host, &pdata->slot[1],
2c96a293 2454 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB);
7a90dcc2 2455 if (!ret) {
965ebf33 2456 nr_slots++;
7a90dcc2
LD		 2457 if (host->slot[1]->mmc->max_req_size > host->buf_size)
2458 host->buf_size =
2459 host->slot[1]->mmc->max_req_size;
2460 }
7d2be074
HS		 2461 }
2462
04d699c3
RE		 2463 if (!nr_slots) {
2464 dev_err(&pdev->dev, "init failed: no slot defined\n");
965ebf33 2465 goto err_init_slot;
04d699c3 2466 }
7d2be074 2467
7a90dcc2
LD		 2468 if (!host->caps.has_rwproof) {
2469 host->buffer = dma_alloc_coherent(&pdev->dev, host->buf_size,
2470 &host->buf_phys_addr,
2471 GFP_KERNEL);
2472 if (!host->buffer) {
2473 ret = -ENOMEM;
2474 dev_err(&pdev->dev, "buffer allocation failed\n");
2475 goto err_init_slot;
2476 }
2477 }
2478
965ebf33
HS		 2479 dev_info(&pdev->dev,
2480 "Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
2481 host->mapbase, irq, nr_slots);
deec9ae3 2482
7d2be074
HS		 2483 return 0;
2484
965ebf33 2485err_init_slot:
74465b4f
DW		 2486 if (host->dma.chan)
2487 dma_release_channel(host->dma.chan);
965ebf33 2488 free_irq(irq, host);
7d2be074
HS		 2489err_request_irq:
2490 iounmap(host->regs);
2491err_ioremap:
2492 clk_put(host->mck);
2493err_clk_get:
965ebf33 2494 kfree(host);
7d2be074
HS		 2495 return ret;
2496}
2497
2498static int __exit atmci_remove(struct platform_device *pdev)
2499{
965ebf33
HS		 2500 struct atmel_mci *host = platform_get_drvdata(pdev);
2501 unsigned int i;
7d2be074
HS		 2502
2503 platform_set_drvdata(pdev, NULL);
2504
7a90dcc2
LD		 2505 if (host->buffer)
2506 dma_free_coherent(&pdev->dev, host->buf_size,
2507 host->buffer, host->buf_phys_addr);
2508
2c96a293 2509 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
965ebf33
HS		 2510 if (host->slot[i])
2511 atmci_cleanup_slot(host->slot[i], i);
2512 }
7d2be074 2513
965ebf33 2514 clk_enable(host->mck);
03fc9a7f
LD		 2515 atmci_writel(host, ATMCI_IDR, ~0UL);
2516 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
2517 atmci_readl(host, ATMCI_SR);
965ebf33 2518 clk_disable(host->mck);
7d2be074 2519
74465b4f
DW		 2520 if (host->dma.chan)
2521 dma_release_channel(host->dma.chan);
65e8b083 2522
965ebf33
HS		 2523 free_irq(platform_get_irq(pdev, 0), host);
2524 iounmap(host->regs);
7d2be074 2525
965ebf33
HS		 2526 clk_put(host->mck);
2527 kfree(host);
7d2be074 2528
7d2be074
HS		 2529 return 0;
2530}
2531
5c2f2b9b
NF		 2532#ifdef CONFIG_PM
2533static int atmci_suspend(struct device *dev)
2534{
2535 struct atmel_mci *host = dev_get_drvdata(dev);
2536 int i;
2537
2c96a293 2538 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
5c2f2b9b
NF		 2539 struct atmel_mci_slot *slot = host->slot[i];
2540 int ret;
2541
2542 if (!slot)
2543 continue;
2544 ret = mmc_suspend_host(slot->mmc);
2545 if (ret < 0) {
2546 while (--i >= 0) {
2547 slot = host->slot[i];
2548 if (slot
2549 && test_bit(ATMCI_SUSPENDED, &slot->flags)) {
2550 mmc_resume_host(host->slot[i]->mmc);
2551 clear_bit(ATMCI_SUSPENDED, &slot->flags);
2552 }
2553 }
2554 return ret;
2555 } else {
2556 set_bit(ATMCI_SUSPENDED, &slot->flags);
2557 }
2558 }
2559
2560 return 0;
2561}
2562
2563static int atmci_resume(struct device *dev)
2564{
2565 struct atmel_mci *host = dev_get_drvdata(dev);
2566 int i;
2567 int ret = 0;
2568
2c96a293 2569 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
5c2f2b9b
NF		 2570 struct atmel_mci_slot *slot = host->slot[i];
2571 int err;
2572
2573 slot = host->slot[i];
2574 if (!slot)
2575 continue;
2576 if (!test_bit(ATMCI_SUSPENDED, &slot->flags))
2577 continue;
2578 err = mmc_resume_host(slot->mmc);
2579 if (err < 0)
2580 ret = err;
2581 else
2582 clear_bit(ATMCI_SUSPENDED, &slot->flags);
2583 }
2584
2585 return ret;
2586}
2587static SIMPLE_DEV_PM_OPS(atmci_pm, atmci_suspend, atmci_resume);
2588#define ATMCI_PM_OPS (&atmci_pm)
2589#else
2590#define ATMCI_PM_OPS NULL
2591#endif
2592
7d2be074
HS		 2593static struct platform_driver atmci_driver = {
2594 .remove = __exit_p(atmci_remove),
2595 .driver = {
2596 .name = "atmel_mci",
5c2f2b9b 2597 .pm = ATMCI_PM_OPS,
e919fd20 2598 .of_match_table = of_match_ptr(atmci_dt_ids),
7d2be074
HS		 2599 },
2600};
2601
2602static int __init atmci_init(void)
2603{
2604 return platform_driver_probe(&atmci_driver, atmci_probe);
2605}
2606
2607static void __exit atmci_exit(void)
2608{
2609 platform_driver_unregister(&atmci_driver);
2610}
2611
74465b4f 2612late_initcall(atmci_init); /* try to load after dma driver when built-in */
7d2be074
HS		 2613module_exit(atmci_exit);
2614
2615MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
e05503ef 2616MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
7d2be074 2617MODULE_LICENSE("GPL v2");
kernel source for telekom puls (alcatel/mediatek)