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65dbf343 | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/at91_mci.c - ATMEL AT91 MCI Driver |
65dbf343 AV |
3 | * |
4 | * Copyright (C) 2005 Cougar Creek Computing Devices Ltd, All Rights Reserved | |
5 | * | |
6 | * Copyright (C) 2006 Malcolm Noyes | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | /* | |
99eeb8df | 14 | This is the AT91 MCI driver that has been tested with both MMC cards |
65dbf343 AV |
15 | and SD-cards. Boards that support write protect are now supported. |
16 | The CCAT91SBC001 board does not support SD cards. | |
17 | ||
18 | The three entry points are at91_mci_request, at91_mci_set_ios | |
19 | and at91_mci_get_ro. | |
20 | ||
21 | SET IOS | |
22 | This configures the device to put it into the correct mode and clock speed | |
23 | required. | |
24 | ||
25 | MCI REQUEST | |
26 | MCI request processes the commands sent in the mmc_request structure. This | |
27 | can consist of a processing command and a stop command in the case of | |
28 | multiple block transfers. | |
29 | ||
30 | There are three main types of request, commands, reads and writes. | |
31 | ||
32 | Commands are straight forward. The command is submitted to the controller and | |
33 | the request function returns. When the controller generates an interrupt to indicate | |
34 | the command is finished, the response to the command are read and the mmc_request_done | |
35 | function called to end the request. | |
36 | ||
37 | Reads and writes work in a similar manner to normal commands but involve the PDC (DMA) | |
38 | controller to manage the transfers. | |
39 | ||
40 | A read is done from the controller directly to the scatterlist passed in from the request. | |
99eeb8df AV |
41 | Due to a bug in the AT91RM9200 controller, when a read is completed, all the words are byte |
42 | swapped in the scatterlist buffers. AT91SAM926x are not affected by this bug. | |
65dbf343 AV |
43 | |
44 | The sequence of read interrupts is: ENDRX, RXBUFF, CMDRDY | |
45 | ||
46 | A write is slightly different in that the bytes to write are read from the scatterlist | |
47 | into a dma memory buffer (this is in case the source buffer should be read only). The | |
48 | entire write buffer is then done from this single dma memory buffer. | |
49 | ||
50 | The sequence of write interrupts is: ENDTX, TXBUFE, NOTBUSY, CMDRDY | |
51 | ||
52 | GET RO | |
53 | Gets the status of the write protect pin, if available. | |
54 | */ | |
55 | ||
65dbf343 AV |
56 | #include <linux/module.h> |
57 | #include <linux/moduleparam.h> | |
58 | #include <linux/init.h> | |
59 | #include <linux/ioport.h> | |
60 | #include <linux/platform_device.h> | |
61 | #include <linux/interrupt.h> | |
62 | #include <linux/blkdev.h> | |
63 | #include <linux/delay.h> | |
64 | #include <linux/err.h> | |
65 | #include <linux/dma-mapping.h> | |
66 | #include <linux/clk.h> | |
93a3ddc2 | 67 | #include <linux/atmel_pdc.h> |
65dbf343 AV |
68 | |
69 | #include <linux/mmc/host.h> | |
65dbf343 AV |
70 | |
71 | #include <asm/io.h> | |
72 | #include <asm/irq.h> | |
6e996ee8 DB |
73 | #include <asm/gpio.h> |
74 | ||
a09e64fb RK |
75 | #include <mach/board.h> |
76 | #include <mach/cpu.h> | |
77 | #include <mach/at91_mci.h> | |
65dbf343 AV |
78 | |
79 | #define DRIVER_NAME "at91_mci" | |
80 | ||
5b27a1a5 NF |
81 | static inline int at91mci_is_mci1rev2xx(void) |
82 | { | |
83 | return ( cpu_is_at91sam9260() | |
84 | || cpu_is_at91sam9263() | |
85 | || cpu_is_at91cap9() | |
86 | || cpu_is_at91sam9rl() | |
87 | || cpu_is_at91sam9g10() | |
88 | || cpu_is_at91sam9g20() | |
89 | ); | |
90 | } | |
91 | ||
df05a303 AV |
92 | #define FL_SENT_COMMAND (1 << 0) |
93 | #define FL_SENT_STOP (1 << 1) | |
65dbf343 | 94 | |
df05a303 AV |
95 | #define AT91_MCI_ERRORS (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE \ |
96 | | AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE \ | |
37b758e8 | 97 | | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE) |
65dbf343 | 98 | |
e0b19b83 AV |
99 | #define at91_mci_read(host, reg) __raw_readl((host)->baseaddr + (reg)) |
100 | #define at91_mci_write(host, reg, val) __raw_writel((val), (host)->baseaddr + (reg)) | |
65dbf343 | 101 | |
3780d906 WM |
102 | #define MCI_BLKSIZE 512 |
103 | #define MCI_MAXBLKSIZE 4095 | |
104 | #define MCI_BLKATONCE 256 | |
105 | #define MCI_BUFSIZE (MCI_BLKSIZE * MCI_BLKATONCE) | |
65dbf343 AV |
106 | |
107 | /* | |
108 | * Low level type for this driver | |
109 | */ | |
110 | struct at91mci_host | |
111 | { | |
112 | struct mmc_host *mmc; | |
113 | struct mmc_command *cmd; | |
114 | struct mmc_request *request; | |
115 | ||
e0b19b83 | 116 | void __iomem *baseaddr; |
17ea0595 | 117 | int irq; |
e0b19b83 | 118 | |
65dbf343 AV |
119 | struct at91_mmc_data *board; |
120 | int present; | |
121 | ||
3dd3b039 AV |
122 | struct clk *mci_clk; |
123 | ||
65dbf343 AV |
124 | /* |
125 | * Flag indicating when the command has been sent. This is used to | |
126 | * work out whether or not to send the stop | |
127 | */ | |
128 | unsigned int flags; | |
129 | /* flag for current bus settings */ | |
130 | u32 bus_mode; | |
131 | ||
132 | /* DMA buffer used for transmitting */ | |
133 | unsigned int* buffer; | |
134 | dma_addr_t physical_address; | |
135 | unsigned int total_length; | |
136 | ||
137 | /* Latest in the scatterlist that has been enabled for transfer, but not freed */ | |
138 | int in_use_index; | |
139 | ||
140 | /* Latest in the scatterlist that has been enabled for transfer */ | |
141 | int transfer_index; | |
e181dce8 MP |
142 | |
143 | /* Timer for timeouts */ | |
144 | struct timer_list timer; | |
65dbf343 AV |
145 | }; |
146 | ||
c5a89c6c MP |
147 | /* |
148 | * Reset the controller and restore most of the state | |
149 | */ | |
150 | static void at91_reset_host(struct at91mci_host *host) | |
151 | { | |
152 | unsigned long flags; | |
153 | u32 mr; | |
154 | u32 sdcr; | |
155 | u32 dtor; | |
156 | u32 imr; | |
157 | ||
158 | local_irq_save(flags); | |
159 | imr = at91_mci_read(host, AT91_MCI_IMR); | |
160 | ||
161 | at91_mci_write(host, AT91_MCI_IDR, 0xffffffff); | |
162 | ||
163 | /* save current state */ | |
164 | mr = at91_mci_read(host, AT91_MCI_MR) & 0x7fff; | |
165 | sdcr = at91_mci_read(host, AT91_MCI_SDCR); | |
166 | dtor = at91_mci_read(host, AT91_MCI_DTOR); | |
167 | ||
168 | /* reset the controller */ | |
169 | at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST); | |
170 | ||
171 | /* restore state */ | |
172 | at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN); | |
173 | at91_mci_write(host, AT91_MCI_MR, mr); | |
174 | at91_mci_write(host, AT91_MCI_SDCR, sdcr); | |
175 | at91_mci_write(host, AT91_MCI_DTOR, dtor); | |
176 | at91_mci_write(host, AT91_MCI_IER, imr); | |
177 | ||
178 | /* make sure sdio interrupts will fire */ | |
179 | at91_mci_read(host, AT91_MCI_SR); | |
180 | ||
181 | local_irq_restore(flags); | |
182 | } | |
183 | ||
e181dce8 MP |
184 | static void at91_timeout_timer(unsigned long data) |
185 | { | |
186 | struct at91mci_host *host; | |
187 | ||
188 | host = (struct at91mci_host *)data; | |
189 | ||
190 | if (host->request) { | |
191 | dev_err(host->mmc->parent, "Timeout waiting end of packet\n"); | |
192 | ||
193 | if (host->cmd && host->cmd->data) { | |
194 | host->cmd->data->error = -ETIMEDOUT; | |
195 | } else { | |
196 | if (host->cmd) | |
197 | host->cmd->error = -ETIMEDOUT; | |
198 | else | |
199 | host->request->cmd->error = -ETIMEDOUT; | |
200 | } | |
201 | ||
c5a89c6c | 202 | at91_reset_host(host); |
e181dce8 MP |
203 | mmc_request_done(host->mmc, host->request); |
204 | } | |
205 | } | |
206 | ||
65dbf343 AV |
207 | /* |
208 | * Copy from sg to a dma block - used for transfers | |
209 | */ | |
e8d04d3d | 210 | static inline void at91_mci_sg_to_dma(struct at91mci_host *host, struct mmc_data *data) |
65dbf343 AV |
211 | { |
212 | unsigned int len, i, size; | |
213 | unsigned *dmabuf = host->buffer; | |
214 | ||
5385edc5 | 215 | size = data->blksz * data->blocks; |
65dbf343 AV |
216 | len = data->sg_len; |
217 | ||
5b27a1a5 NF |
218 | /* MCI1 rev2xx Data Write Operation and number of bytes erratum */ |
219 | if (at91mci_is_mci1rev2xx()) | |
5385edc5 VS |
220 | if (host->total_length == 12) |
221 | memset(dmabuf, 0, 12); | |
222 | ||
65dbf343 AV |
223 | /* |
224 | * Just loop through all entries. Size might not | |
225 | * be the entire list though so make sure that | |
226 | * we do not transfer too much. | |
227 | */ | |
228 | for (i = 0; i < len; i++) { | |
229 | struct scatterlist *sg; | |
230 | int amount; | |
65dbf343 AV |
231 | unsigned int *sgbuffer; |
232 | ||
233 | sg = &data->sg[i]; | |
234 | ||
45711f1a | 235 | sgbuffer = kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset; |
65dbf343 AV |
236 | amount = min(size, sg->length); |
237 | size -= amount; | |
65dbf343 | 238 | |
99eeb8df AV |
239 | if (cpu_is_at91rm9200()) { /* AT91RM9200 errata */ |
240 | int index; | |
241 | ||
242 | for (index = 0; index < (amount / 4); index++) | |
243 | *dmabuf++ = swab32(sgbuffer[index]); | |
5385edc5 | 244 | } else { |
0b3520f2 WM |
245 | char *tmpv = (char *)dmabuf; |
246 | memcpy(tmpv, sgbuffer, amount); | |
247 | tmpv += amount; | |
248 | dmabuf = (unsigned *)tmpv; | |
5385edc5 | 249 | } |
65dbf343 | 250 | |
752993ef | 251 | kunmap_atomic(sgbuffer, KM_BIO_SRC_IRQ); |
65dbf343 AV |
252 | |
253 | if (size == 0) | |
254 | break; | |
255 | } | |
256 | ||
257 | /* | |
258 | * Check that we didn't get a request to transfer | |
259 | * more data than can fit into the SG list. | |
260 | */ | |
261 | BUG_ON(size != 0); | |
262 | } | |
263 | ||
65dbf343 AV |
264 | /* |
265 | * Handle after a dma read | |
266 | */ | |
e8d04d3d | 267 | static void at91_mci_post_dma_read(struct at91mci_host *host) |
65dbf343 AV |
268 | { |
269 | struct mmc_command *cmd; | |
270 | struct mmc_data *data; | |
86ee26f5 WM |
271 | unsigned int len, i, size; |
272 | unsigned *dmabuf = host->buffer; | |
65dbf343 | 273 | |
b44fb7a0 | 274 | pr_debug("post dma read\n"); |
65dbf343 AV |
275 | |
276 | cmd = host->cmd; | |
277 | if (!cmd) { | |
b44fb7a0 | 278 | pr_debug("no command\n"); |
65dbf343 AV |
279 | return; |
280 | } | |
281 | ||
282 | data = cmd->data; | |
283 | if (!data) { | |
b44fb7a0 | 284 | pr_debug("no data\n"); |
65dbf343 AV |
285 | return; |
286 | } | |
287 | ||
86ee26f5 WM |
288 | size = data->blksz * data->blocks; |
289 | len = data->sg_len; | |
65dbf343 | 290 | |
86ee26f5 WM |
291 | at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_ENDRX); |
292 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_RXBUFF); | |
65dbf343 | 293 | |
86ee26f5 WM |
294 | for (i = 0; i < len; i++) { |
295 | struct scatterlist *sg; | |
296 | int amount; | |
297 | unsigned int *sgbuffer; | |
65dbf343 | 298 | |
86ee26f5 | 299 | sg = &data->sg[i]; |
65dbf343 | 300 | |
86ee26f5 WM |
301 | sgbuffer = kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset; |
302 | amount = min(size, sg->length); | |
303 | size -= amount; | |
65dbf343 | 304 | |
99eeb8df AV |
305 | if (cpu_is_at91rm9200()) { /* AT91RM9200 errata */ |
306 | int index; | |
86ee26f5 WM |
307 | for (index = 0; index < (amount / 4); index++) |
308 | sgbuffer[index] = swab32(*dmabuf++); | |
309 | } else { | |
310 | char *tmpv = (char *)dmabuf; | |
311 | memcpy(sgbuffer, tmpv, amount); | |
312 | tmpv += amount; | |
313 | dmabuf = (unsigned *)tmpv; | |
65dbf343 | 314 | } |
99eeb8df | 315 | |
752993ef | 316 | kunmap_atomic(sgbuffer, KM_BIO_SRC_IRQ); |
86ee26f5 WM |
317 | dmac_flush_range((void *)sgbuffer, ((void *)sgbuffer) + amount); |
318 | data->bytes_xfered += amount; | |
319 | if (size == 0) | |
320 | break; | |
65dbf343 AV |
321 | } |
322 | ||
b44fb7a0 | 323 | pr_debug("post dma read done\n"); |
65dbf343 AV |
324 | } |
325 | ||
326 | /* | |
327 | * Handle transmitted data | |
328 | */ | |
329 | static void at91_mci_handle_transmitted(struct at91mci_host *host) | |
330 | { | |
331 | struct mmc_command *cmd; | |
332 | struct mmc_data *data; | |
333 | ||
b44fb7a0 | 334 | pr_debug("Handling the transmit\n"); |
65dbf343 AV |
335 | |
336 | /* Disable the transfer */ | |
93a3ddc2 | 337 | at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); |
65dbf343 AV |
338 | |
339 | /* Now wait for cmd ready */ | |
e0b19b83 | 340 | at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_TXBUFE); |
65dbf343 AV |
341 | |
342 | cmd = host->cmd; | |
343 | if (!cmd) return; | |
344 | ||
345 | data = cmd->data; | |
346 | if (!data) return; | |
347 | ||
be0192aa | 348 | if (cmd->data->blocks > 1) { |
ed99c541 NF |
349 | pr_debug("multiple write : wait for BLKE...\n"); |
350 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_BLKE); | |
351 | } else | |
352 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY); | |
4ac24a87 NF |
353 | } |
354 | ||
355 | /* | |
356 | * Update bytes tranfered count during a write operation | |
357 | */ | |
358 | static void at91_mci_update_bytes_xfered(struct at91mci_host *host) | |
359 | { | |
360 | struct mmc_data *data; | |
ed99c541 | 361 | |
4ac24a87 NF |
362 | /* always deal with the effective request (and not the current cmd) */ |
363 | ||
364 | if (host->request->cmd && host->request->cmd->error != 0) | |
365 | return; | |
366 | ||
367 | if (host->request->data) { | |
368 | data = host->request->data; | |
369 | if (data->flags & MMC_DATA_WRITE) { | |
370 | /* card is in IDLE mode now */ | |
371 | pr_debug("-> bytes_xfered %d, total_length = %d\n", | |
372 | data->bytes_xfered, host->total_length); | |
5385edc5 | 373 | data->bytes_xfered = data->blksz * data->blocks; |
4ac24a87 NF |
374 | } |
375 | } | |
65dbf343 AV |
376 | } |
377 | ||
4ac24a87 | 378 | |
ed99c541 NF |
379 | /*Handle after command sent ready*/ |
380 | static int at91_mci_handle_cmdrdy(struct at91mci_host *host) | |
381 | { | |
382 | if (!host->cmd) | |
383 | return 1; | |
384 | else if (!host->cmd->data) { | |
385 | if (host->flags & FL_SENT_STOP) { | |
386 | /*After multi block write, we must wait for NOTBUSY*/ | |
387 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY); | |
388 | } else return 1; | |
389 | } else if (host->cmd->data->flags & MMC_DATA_WRITE) { | |
390 | /*After sendding multi-block-write command, start DMA transfer*/ | |
4ac24a87 | 391 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_TXBUFE | AT91_MCI_BLKE); |
ed99c541 NF |
392 | at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); |
393 | } | |
394 | ||
395 | /* command not completed, have to wait */ | |
396 | return 0; | |
397 | } | |
398 | ||
399 | ||
65dbf343 AV |
400 | /* |
401 | * Enable the controller | |
402 | */ | |
e0b19b83 | 403 | static void at91_mci_enable(struct at91mci_host *host) |
65dbf343 | 404 | { |
ed99c541 NF |
405 | unsigned int mr; |
406 | ||
e0b19b83 | 407 | at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN); |
f3a8efa9 | 408 | at91_mci_write(host, AT91_MCI_IDR, 0xffffffff); |
e0b19b83 | 409 | at91_mci_write(host, AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC); |
ed99c541 NF |
410 | mr = AT91_MCI_PDCMODE | 0x34a; |
411 | ||
5b27a1a5 | 412 | if (at91mci_is_mci1rev2xx()) |
ed99c541 NF |
413 | mr |= AT91_MCI_RDPROOF | AT91_MCI_WRPROOF; |
414 | ||
415 | at91_mci_write(host, AT91_MCI_MR, mr); | |
99eeb8df AV |
416 | |
417 | /* use Slot A or B (only one at same time) */ | |
418 | at91_mci_write(host, AT91_MCI_SDCR, host->board->slot_b); | |
65dbf343 AV |
419 | } |
420 | ||
421 | /* | |
422 | * Disable the controller | |
423 | */ | |
e0b19b83 | 424 | static void at91_mci_disable(struct at91mci_host *host) |
65dbf343 | 425 | { |
e0b19b83 | 426 | at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST); |
65dbf343 AV |
427 | } |
428 | ||
429 | /* | |
430 | * Send a command | |
65dbf343 | 431 | */ |
ed99c541 | 432 | static void at91_mci_send_command(struct at91mci_host *host, struct mmc_command *cmd) |
65dbf343 AV |
433 | { |
434 | unsigned int cmdr, mr; | |
435 | unsigned int block_length; | |
436 | struct mmc_data *data = cmd->data; | |
437 | ||
438 | unsigned int blocks; | |
439 | unsigned int ier = 0; | |
440 | ||
441 | host->cmd = cmd; | |
442 | ||
ed99c541 | 443 | /* Needed for leaving busy state before CMD1 */ |
e0b19b83 | 444 | if ((at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->opcode == 1)) { |
b44fb7a0 | 445 | pr_debug("Clearing timeout\n"); |
e0b19b83 AV |
446 | at91_mci_write(host, AT91_MCI_ARGR, 0); |
447 | at91_mci_write(host, AT91_MCI_CMDR, AT91_MCI_OPDCMD); | |
448 | while (!(at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_CMDRDY)) { | |
65dbf343 | 449 | /* spin */ |
e0b19b83 | 450 | pr_debug("Clearing: SR = %08X\n", at91_mci_read(host, AT91_MCI_SR)); |
65dbf343 AV |
451 | } |
452 | } | |
ed99c541 | 453 | |
65dbf343 AV |
454 | cmdr = cmd->opcode; |
455 | ||
456 | if (mmc_resp_type(cmd) == MMC_RSP_NONE) | |
457 | cmdr |= AT91_MCI_RSPTYP_NONE; | |
458 | else { | |
459 | /* if a response is expected then allow maximum response latancy */ | |
460 | cmdr |= AT91_MCI_MAXLAT; | |
461 | /* set 136 bit response for R2, 48 bit response otherwise */ | |
462 | if (mmc_resp_type(cmd) == MMC_RSP_R2) | |
463 | cmdr |= AT91_MCI_RSPTYP_136; | |
464 | else | |
465 | cmdr |= AT91_MCI_RSPTYP_48; | |
466 | } | |
467 | ||
468 | if (data) { | |
1d4de9ed | 469 | |
9da3cbaf VS |
470 | if (cpu_is_at91rm9200() || cpu_is_at91sam9261()) { |
471 | if (data->blksz & 0x3) { | |
472 | pr_debug("Unsupported block size\n"); | |
473 | cmd->error = -EINVAL; | |
474 | mmc_request_done(host->mmc, host->request); | |
475 | return; | |
476 | } | |
477 | if (data->flags & MMC_DATA_STREAM) { | |
478 | pr_debug("Stream commands not supported\n"); | |
479 | cmd->error = -EINVAL; | |
480 | mmc_request_done(host->mmc, host->request); | |
481 | return; | |
482 | } | |
1d4de9ed MP |
483 | } |
484 | ||
a3fd4a1b | 485 | block_length = data->blksz; |
65dbf343 AV |
486 | blocks = data->blocks; |
487 | ||
488 | /* always set data start - also set direction flag for read */ | |
489 | if (data->flags & MMC_DATA_READ) | |
490 | cmdr |= (AT91_MCI_TRDIR | AT91_MCI_TRCMD_START); | |
491 | else if (data->flags & MMC_DATA_WRITE) | |
492 | cmdr |= AT91_MCI_TRCMD_START; | |
493 | ||
494 | if (data->flags & MMC_DATA_STREAM) | |
495 | cmdr |= AT91_MCI_TRTYP_STREAM; | |
be0192aa | 496 | if (data->blocks > 1) |
65dbf343 AV |
497 | cmdr |= AT91_MCI_TRTYP_MULTIPLE; |
498 | } | |
499 | else { | |
500 | block_length = 0; | |
501 | blocks = 0; | |
502 | } | |
503 | ||
b6cedb38 | 504 | if (host->flags & FL_SENT_STOP) |
65dbf343 AV |
505 | cmdr |= AT91_MCI_TRCMD_STOP; |
506 | ||
507 | if (host->bus_mode == MMC_BUSMODE_OPENDRAIN) | |
508 | cmdr |= AT91_MCI_OPDCMD; | |
509 | ||
510 | /* | |
511 | * Set the arguments and send the command | |
512 | */ | |
f3a8efa9 | 513 | pr_debug("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n", |
e0b19b83 | 514 | cmd->opcode, cmdr, cmd->arg, blocks, block_length, at91_mci_read(host, AT91_MCI_MR)); |
65dbf343 AV |
515 | |
516 | if (!data) { | |
93a3ddc2 AV |
517 | at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS | ATMEL_PDC_RXTDIS); |
518 | at91_mci_write(host, ATMEL_PDC_RPR, 0); | |
519 | at91_mci_write(host, ATMEL_PDC_RCR, 0); | |
520 | at91_mci_write(host, ATMEL_PDC_RNPR, 0); | |
521 | at91_mci_write(host, ATMEL_PDC_RNCR, 0); | |
522 | at91_mci_write(host, ATMEL_PDC_TPR, 0); | |
523 | at91_mci_write(host, ATMEL_PDC_TCR, 0); | |
524 | at91_mci_write(host, ATMEL_PDC_TNPR, 0); | |
525 | at91_mci_write(host, ATMEL_PDC_TNCR, 0); | |
ed99c541 NF |
526 | ier = AT91_MCI_CMDRDY; |
527 | } else { | |
528 | /* zero block length and PDC mode */ | |
12bd2575 | 529 | mr = at91_mci_read(host, AT91_MCI_MR) & 0x5fff; |
80f92546 MP |
530 | mr |= (data->blksz & 0x3) ? AT91_MCI_PDCFBYTE : 0; |
531 | mr |= (block_length << 16); | |
532 | mr |= AT91_MCI_PDCMODE; | |
533 | at91_mci_write(host, AT91_MCI_MR, mr); | |
e0b19b83 | 534 | |
9da3cbaf | 535 | if (!(cpu_is_at91rm9200() || cpu_is_at91sam9261())) |
c5a89c6c MP |
536 | at91_mci_write(host, AT91_MCI_BLKR, |
537 | AT91_MCI_BLKR_BCNT(blocks) | | |
538 | AT91_MCI_BLKR_BLKLEN(block_length)); | |
539 | ||
ed99c541 NF |
540 | /* |
541 | * Disable the PDC controller | |
542 | */ | |
543 | at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); | |
65dbf343 | 544 | |
ed99c541 NF |
545 | if (cmdr & AT91_MCI_TRCMD_START) { |
546 | data->bytes_xfered = 0; | |
547 | host->transfer_index = 0; | |
548 | host->in_use_index = 0; | |
549 | if (cmdr & AT91_MCI_TRDIR) { | |
550 | /* | |
551 | * Handle a read | |
552 | */ | |
ed99c541 NF |
553 | host->total_length = 0; |
554 | ||
86ee26f5 WM |
555 | at91_mci_write(host, ATMEL_PDC_RPR, host->physical_address); |
556 | at91_mci_write(host, ATMEL_PDC_RCR, (data->blksz & 0x3) ? | |
557 | (blocks * block_length) : (blocks * block_length) / 4); | |
558 | at91_mci_write(host, ATMEL_PDC_RNPR, 0); | |
559 | at91_mci_write(host, ATMEL_PDC_RNCR, 0); | |
560 | ||
ed99c541 NF |
561 | ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */; |
562 | } | |
563 | else { | |
564 | /* | |
565 | * Handle a write | |
566 | */ | |
567 | host->total_length = block_length * blocks; | |
5385edc5 | 568 | /* |
5b27a1a5 | 569 | * MCI1 rev2xx Data Write Operation and |
5385edc5 VS |
570 | * number of bytes erratum |
571 | */ | |
5b27a1a5 | 572 | if (at91mci_is_mci1rev2xx()) |
5385edc5 VS |
573 | if (host->total_length < 12) |
574 | host->total_length = 12; | |
e385ea63 | 575 | |
ed99c541 NF |
576 | at91_mci_sg_to_dma(host, data); |
577 | ||
578 | pr_debug("Transmitting %d bytes\n", host->total_length); | |
579 | ||
580 | at91_mci_write(host, ATMEL_PDC_TPR, host->physical_address); | |
80f92546 MP |
581 | at91_mci_write(host, ATMEL_PDC_TCR, (data->blksz & 0x3) ? |
582 | host->total_length : host->total_length / 4); | |
583 | ||
ed99c541 NF |
584 | ier = AT91_MCI_CMDRDY; |
585 | } | |
65dbf343 AV |
586 | } |
587 | } | |
588 | ||
589 | /* | |
590 | * Send the command and then enable the PDC - not the other way round as | |
591 | * the data sheet says | |
592 | */ | |
593 | ||
e0b19b83 AV |
594 | at91_mci_write(host, AT91_MCI_ARGR, cmd->arg); |
595 | at91_mci_write(host, AT91_MCI_CMDR, cmdr); | |
65dbf343 AV |
596 | |
597 | if (cmdr & AT91_MCI_TRCMD_START) { | |
598 | if (cmdr & AT91_MCI_TRDIR) | |
93a3ddc2 | 599 | at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN); |
65dbf343 | 600 | } |
65dbf343 | 601 | |
ed99c541 | 602 | /* Enable selected interrupts */ |
df05a303 | 603 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_ERRORS | ier); |
65dbf343 AV |
604 | } |
605 | ||
606 | /* | |
607 | * Process the next step in the request | |
608 | */ | |
e8d04d3d | 609 | static void at91_mci_process_next(struct at91mci_host *host) |
65dbf343 AV |
610 | { |
611 | if (!(host->flags & FL_SENT_COMMAND)) { | |
612 | host->flags |= FL_SENT_COMMAND; | |
ed99c541 | 613 | at91_mci_send_command(host, host->request->cmd); |
65dbf343 AV |
614 | } |
615 | else if ((!(host->flags & FL_SENT_STOP)) && host->request->stop) { | |
616 | host->flags |= FL_SENT_STOP; | |
ed99c541 | 617 | at91_mci_send_command(host, host->request->stop); |
e181dce8 MP |
618 | } else { |
619 | del_timer(&host->timer); | |
c5a89c6c MP |
620 | /* the at91rm9200 mci controller hangs after some transfers, |
621 | * and the workaround is to reset it after each transfer. | |
622 | */ | |
623 | if (cpu_is_at91rm9200()) | |
624 | at91_reset_host(host); | |
65dbf343 | 625 | mmc_request_done(host->mmc, host->request); |
e181dce8 | 626 | } |
65dbf343 AV |
627 | } |
628 | ||
629 | /* | |
630 | * Handle a command that has been completed | |
631 | */ | |
ba7deeed | 632 | static void at91_mci_completed_command(struct at91mci_host *host, unsigned int status) |
65dbf343 AV |
633 | { |
634 | struct mmc_command *cmd = host->cmd; | |
fa1fe010 | 635 | struct mmc_data *data = cmd->data; |
65dbf343 | 636 | |
7a6588ba | 637 | at91_mci_write(host, AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); |
65dbf343 | 638 | |
e0b19b83 AV |
639 | cmd->resp[0] = at91_mci_read(host, AT91_MCI_RSPR(0)); |
640 | cmd->resp[1] = at91_mci_read(host, AT91_MCI_RSPR(1)); | |
641 | cmd->resp[2] = at91_mci_read(host, AT91_MCI_RSPR(2)); | |
642 | cmd->resp[3] = at91_mci_read(host, AT91_MCI_RSPR(3)); | |
65dbf343 | 643 | |
ba7deeed NF |
644 | pr_debug("Status = %08X/%08x [%08X %08X %08X %08X]\n", |
645 | status, at91_mci_read(host, AT91_MCI_SR), | |
646 | cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); | |
65dbf343 | 647 | |
9e3866b5 | 648 | if (status & AT91_MCI_ERRORS) { |
b6cedb38 | 649 | if ((status & AT91_MCI_RCRCE) && !(mmc_resp_type(cmd) & MMC_RSP_CRC)) { |
17b0429d | 650 | cmd->error = 0; |
65dbf343 AV |
651 | } |
652 | else { | |
fa1fe010 NF |
653 | if (status & (AT91_MCI_DTOE | AT91_MCI_DCRCE)) { |
654 | if (data) { | |
655 | if (status & AT91_MCI_DTOE) | |
656 | data->error = -ETIMEDOUT; | |
657 | else if (status & AT91_MCI_DCRCE) | |
658 | data->error = -EILSEQ; | |
659 | } | |
660 | } else { | |
661 | if (status & AT91_MCI_RTOE) | |
662 | cmd->error = -ETIMEDOUT; | |
663 | else if (status & AT91_MCI_RCRCE) | |
664 | cmd->error = -EILSEQ; | |
665 | else | |
666 | cmd->error = -EIO; | |
667 | } | |
65dbf343 | 668 | |
fa1fe010 NF |
669 | pr_debug("Error detected and set to %d/%d (cmd = %d, retries = %d)\n", |
670 | cmd->error, data ? data->error : 0, | |
671 | cmd->opcode, cmd->retries); | |
65dbf343 AV |
672 | } |
673 | } | |
674 | else | |
17b0429d | 675 | cmd->error = 0; |
65dbf343 | 676 | |
e8d04d3d | 677 | at91_mci_process_next(host); |
65dbf343 AV |
678 | } |
679 | ||
680 | /* | |
681 | * Handle an MMC request | |
682 | */ | |
683 | static void at91_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
684 | { | |
685 | struct at91mci_host *host = mmc_priv(mmc); | |
686 | host->request = mrq; | |
687 | host->flags = 0; | |
688 | ||
a04ac5b9 WM |
689 | /* more than 1s timeout needed with slow SD cards */ |
690 | mod_timer(&host->timer, jiffies + msecs_to_jiffies(2000)); | |
e181dce8 | 691 | |
e8d04d3d | 692 | at91_mci_process_next(host); |
65dbf343 AV |
693 | } |
694 | ||
695 | /* | |
696 | * Set the IOS | |
697 | */ | |
698 | static void at91_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
699 | { | |
700 | int clkdiv; | |
701 | struct at91mci_host *host = mmc_priv(mmc); | |
3dd3b039 | 702 | unsigned long at91_master_clock = clk_get_rate(host->mci_clk); |
65dbf343 | 703 | |
b44fb7a0 | 704 | host->bus_mode = ios->bus_mode; |
65dbf343 AV |
705 | |
706 | if (ios->clock == 0) { | |
707 | /* Disable the MCI controller */ | |
e0b19b83 | 708 | at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS); |
65dbf343 AV |
709 | clkdiv = 0; |
710 | } | |
711 | else { | |
712 | /* Enable the MCI controller */ | |
e0b19b83 | 713 | at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN); |
65dbf343 AV |
714 | |
715 | if ((at91_master_clock % (ios->clock * 2)) == 0) | |
716 | clkdiv = ((at91_master_clock / ios->clock) / 2) - 1; | |
717 | else | |
718 | clkdiv = (at91_master_clock / ios->clock) / 2; | |
719 | ||
b44fb7a0 | 720 | pr_debug("clkdiv = %d. mcck = %ld\n", clkdiv, |
65dbf343 AV |
721 | at91_master_clock / (2 * (clkdiv + 1))); |
722 | } | |
723 | if (ios->bus_width == MMC_BUS_WIDTH_4 && host->board->wire4) { | |
b44fb7a0 | 724 | pr_debug("MMC: Setting controller bus width to 4\n"); |
e0b19b83 | 725 | at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) | AT91_MCI_SDCBUS); |
65dbf343 AV |
726 | } |
727 | else { | |
b44fb7a0 | 728 | pr_debug("MMC: Setting controller bus width to 1\n"); |
e0b19b83 | 729 | at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS); |
65dbf343 AV |
730 | } |
731 | ||
732 | /* Set the clock divider */ | |
e0b19b83 | 733 | at91_mci_write(host, AT91_MCI_MR, (at91_mci_read(host, AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv); |
65dbf343 AV |
734 | |
735 | /* maybe switch power to the card */ | |
b44fb7a0 | 736 | if (host->board->vcc_pin) { |
65dbf343 AV |
737 | switch (ios->power_mode) { |
738 | case MMC_POWER_OFF: | |
6e996ee8 | 739 | gpio_set_value(host->board->vcc_pin, 0); |
65dbf343 AV |
740 | break; |
741 | case MMC_POWER_UP: | |
6e996ee8 | 742 | gpio_set_value(host->board->vcc_pin, 1); |
65dbf343 | 743 | break; |
e5c0ef90 MP |
744 | case MMC_POWER_ON: |
745 | break; | |
746 | default: | |
747 | WARN_ON(1); | |
65dbf343 AV |
748 | } |
749 | } | |
750 | } | |
751 | ||
752 | /* | |
753 | * Handle an interrupt | |
754 | */ | |
7d12e780 | 755 | static irqreturn_t at91_mci_irq(int irq, void *devid) |
65dbf343 AV |
756 | { |
757 | struct at91mci_host *host = devid; | |
758 | int completed = 0; | |
df05a303 | 759 | unsigned int int_status, int_mask; |
65dbf343 | 760 | |
e0b19b83 | 761 | int_status = at91_mci_read(host, AT91_MCI_SR); |
df05a303 | 762 | int_mask = at91_mci_read(host, AT91_MCI_IMR); |
37b758e8 | 763 | |
f3a8efa9 | 764 | pr_debug("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask, |
df05a303 | 765 | int_status & int_mask); |
37b758e8 | 766 | |
df05a303 AV |
767 | int_status = int_status & int_mask; |
768 | ||
769 | if (int_status & AT91_MCI_ERRORS) { | |
65dbf343 | 770 | completed = 1; |
37b758e8 | 771 | |
df05a303 AV |
772 | if (int_status & AT91_MCI_UNRE) |
773 | pr_debug("MMC: Underrun error\n"); | |
774 | if (int_status & AT91_MCI_OVRE) | |
775 | pr_debug("MMC: Overrun error\n"); | |
776 | if (int_status & AT91_MCI_DTOE) | |
777 | pr_debug("MMC: Data timeout\n"); | |
778 | if (int_status & AT91_MCI_DCRCE) | |
779 | pr_debug("MMC: CRC error in data\n"); | |
780 | if (int_status & AT91_MCI_RTOE) | |
781 | pr_debug("MMC: Response timeout\n"); | |
782 | if (int_status & AT91_MCI_RENDE) | |
783 | pr_debug("MMC: Response end bit error\n"); | |
784 | if (int_status & AT91_MCI_RCRCE) | |
785 | pr_debug("MMC: Response CRC error\n"); | |
786 | if (int_status & AT91_MCI_RDIRE) | |
787 | pr_debug("MMC: Response direction error\n"); | |
788 | if (int_status & AT91_MCI_RINDE) | |
789 | pr_debug("MMC: Response index error\n"); | |
790 | } else { | |
791 | /* Only continue processing if no errors */ | |
65dbf343 | 792 | |
65dbf343 | 793 | if (int_status & AT91_MCI_TXBUFE) { |
b44fb7a0 | 794 | pr_debug("TX buffer empty\n"); |
65dbf343 AV |
795 | at91_mci_handle_transmitted(host); |
796 | } | |
797 | ||
ed99c541 NF |
798 | if (int_status & AT91_MCI_ENDRX) { |
799 | pr_debug("ENDRX\n"); | |
800 | at91_mci_post_dma_read(host); | |
801 | } | |
802 | ||
65dbf343 | 803 | if (int_status & AT91_MCI_RXBUFF) { |
b44fb7a0 | 804 | pr_debug("RX buffer full\n"); |
ed99c541 NF |
805 | at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); |
806 | at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_RXBUFF | AT91_MCI_ENDRX); | |
807 | completed = 1; | |
65dbf343 AV |
808 | } |
809 | ||
df05a303 | 810 | if (int_status & AT91_MCI_ENDTX) |
b44fb7a0 | 811 | pr_debug("Transmit has ended\n"); |
65dbf343 | 812 | |
65dbf343 | 813 | if (int_status & AT91_MCI_NOTBUSY) { |
b44fb7a0 | 814 | pr_debug("Card is ready\n"); |
4ac24a87 | 815 | at91_mci_update_bytes_xfered(host); |
ed99c541 | 816 | completed = 1; |
65dbf343 AV |
817 | } |
818 | ||
df05a303 | 819 | if (int_status & AT91_MCI_DTIP) |
b44fb7a0 | 820 | pr_debug("Data transfer in progress\n"); |
65dbf343 | 821 | |
ed99c541 | 822 | if (int_status & AT91_MCI_BLKE) { |
b44fb7a0 | 823 | pr_debug("Block transfer has ended\n"); |
4ac24a87 NF |
824 | if (host->request->data && host->request->data->blocks > 1) { |
825 | /* multi block write : complete multi write | |
826 | * command and send stop */ | |
827 | completed = 1; | |
828 | } else { | |
829 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY); | |
830 | } | |
ed99c541 | 831 | } |
65dbf343 | 832 | |
7a6588ba EB |
833 | if (int_status & AT91_MCI_SDIOIRQA) |
834 | mmc_signal_sdio_irq(host->mmc); | |
835 | ||
836 | if (int_status & AT91_MCI_SDIOIRQB) | |
837 | mmc_signal_sdio_irq(host->mmc); | |
838 | ||
df05a303 | 839 | if (int_status & AT91_MCI_TXRDY) |
b44fb7a0 | 840 | pr_debug("Ready to transmit\n"); |
65dbf343 | 841 | |
df05a303 | 842 | if (int_status & AT91_MCI_RXRDY) |
b44fb7a0 | 843 | pr_debug("Ready to receive\n"); |
65dbf343 AV |
844 | |
845 | if (int_status & AT91_MCI_CMDRDY) { | |
b44fb7a0 | 846 | pr_debug("Command ready\n"); |
ed99c541 | 847 | completed = at91_mci_handle_cmdrdy(host); |
65dbf343 AV |
848 | } |
849 | } | |
65dbf343 AV |
850 | |
851 | if (completed) { | |
b44fb7a0 | 852 | pr_debug("Completed command\n"); |
7a6588ba | 853 | at91_mci_write(host, AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); |
ba7deeed | 854 | at91_mci_completed_command(host, int_status); |
df05a303 | 855 | } else |
7a6588ba | 856 | at91_mci_write(host, AT91_MCI_IDR, int_status & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); |
65dbf343 AV |
857 | |
858 | return IRQ_HANDLED; | |
859 | } | |
860 | ||
7d12e780 | 861 | static irqreturn_t at91_mmc_det_irq(int irq, void *_host) |
65dbf343 AV |
862 | { |
863 | struct at91mci_host *host = _host; | |
6e996ee8 | 864 | int present = !gpio_get_value(irq_to_gpio(irq)); |
65dbf343 AV |
865 | |
866 | /* | |
867 | * we expect this irq on both insert and remove, | |
868 | * and use a short delay to debounce. | |
869 | */ | |
870 | if (present != host->present) { | |
871 | host->present = present; | |
b44fb7a0 | 872 | pr_debug("%s: card %s\n", mmc_hostname(host->mmc), |
65dbf343 AV |
873 | present ? "insert" : "remove"); |
874 | if (!present) { | |
b44fb7a0 | 875 | pr_debug("****** Resetting SD-card bus width ******\n"); |
99eeb8df | 876 | at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS); |
65dbf343 | 877 | } |
a04ac5b9 WM |
878 | /* 0.5s needed because of early card detect switch firing */ |
879 | mmc_detect_change(host->mmc, msecs_to_jiffies(500)); | |
65dbf343 AV |
880 | } |
881 | return IRQ_HANDLED; | |
882 | } | |
883 | ||
a26b498c | 884 | static int at91_mci_get_ro(struct mmc_host *mmc) |
65dbf343 | 885 | { |
65dbf343 AV |
886 | struct at91mci_host *host = mmc_priv(mmc); |
887 | ||
08f80bb5 AV |
888 | if (host->board->wp_pin) |
889 | return !!gpio_get_value(host->board->wp_pin); | |
890 | /* | |
891 | * Board doesn't support read only detection; let the mmc core | |
892 | * decide what to do. | |
893 | */ | |
894 | return -ENOSYS; | |
65dbf343 AV |
895 | } |
896 | ||
7a6588ba EB |
897 | static void at91_mci_enable_sdio_irq(struct mmc_host *mmc, int enable) |
898 | { | |
899 | struct at91mci_host *host = mmc_priv(mmc); | |
900 | ||
901 | pr_debug("%s: sdio_irq %c : %s\n", mmc_hostname(host->mmc), | |
902 | host->board->slot_b ? 'B':'A', enable ? "enable" : "disable"); | |
903 | at91_mci_write(host, enable ? AT91_MCI_IER : AT91_MCI_IDR, | |
904 | host->board->slot_b ? AT91_MCI_SDIOIRQB : AT91_MCI_SDIOIRQA); | |
905 | ||
906 | } | |
907 | ||
ab7aefd0 | 908 | static const struct mmc_host_ops at91_mci_ops = { |
65dbf343 AV |
909 | .request = at91_mci_request, |
910 | .set_ios = at91_mci_set_ios, | |
911 | .get_ro = at91_mci_get_ro, | |
7a6588ba | 912 | .enable_sdio_irq = at91_mci_enable_sdio_irq, |
65dbf343 AV |
913 | }; |
914 | ||
915 | /* | |
916 | * Probe for the device | |
917 | */ | |
a26b498c | 918 | static int __init at91_mci_probe(struct platform_device *pdev) |
65dbf343 AV |
919 | { |
920 | struct mmc_host *mmc; | |
921 | struct at91mci_host *host; | |
17ea0595 | 922 | struct resource *res; |
65dbf343 AV |
923 | int ret; |
924 | ||
17ea0595 AV |
925 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
926 | if (!res) | |
927 | return -ENXIO; | |
928 | ||
929 | if (!request_mem_region(res->start, res->end - res->start + 1, DRIVER_NAME)) | |
930 | return -EBUSY; | |
931 | ||
65dbf343 AV |
932 | mmc = mmc_alloc_host(sizeof(struct at91mci_host), &pdev->dev); |
933 | if (!mmc) { | |
6e996ee8 DB |
934 | ret = -ENOMEM; |
935 | dev_dbg(&pdev->dev, "couldn't allocate mmc host\n"); | |
936 | goto fail6; | |
65dbf343 AV |
937 | } |
938 | ||
939 | mmc->ops = &at91_mci_ops; | |
940 | mmc->f_min = 375000; | |
941 | mmc->f_max = 25000000; | |
942 | mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; | |
541e7ef0 | 943 | mmc->caps = 0; |
65dbf343 | 944 | |
3780d906 WM |
945 | mmc->max_blk_size = MCI_MAXBLKSIZE; |
946 | mmc->max_blk_count = MCI_BLKATONCE; | |
947 | mmc->max_req_size = MCI_BUFSIZE; | |
9af13be2 WM |
948 | mmc->max_phys_segs = MCI_BLKATONCE; |
949 | mmc->max_hw_segs = MCI_BLKATONCE; | |
950 | mmc->max_seg_size = MCI_BUFSIZE; | |
fe4a3c7a | 951 | |
65dbf343 AV |
952 | host = mmc_priv(mmc); |
953 | host->mmc = mmc; | |
65dbf343 AV |
954 | host->bus_mode = 0; |
955 | host->board = pdev->dev.platform_data; | |
956 | if (host->board->wire4) { | |
5b27a1a5 | 957 | if (at91mci_is_mci1rev2xx()) |
ed99c541 NF |
958 | mmc->caps |= MMC_CAP_4_BIT_DATA; |
959 | else | |
6e996ee8 | 960 | dev_warn(&pdev->dev, "4 wire bus mode not supported" |
ed99c541 | 961 | " - using 1 wire\n"); |
65dbf343 AV |
962 | } |
963 | ||
3780d906 WM |
964 | host->buffer = dma_alloc_coherent(&pdev->dev, MCI_BUFSIZE, |
965 | &host->physical_address, GFP_KERNEL); | |
966 | if (!host->buffer) { | |
967 | ret = -ENOMEM; | |
968 | dev_err(&pdev->dev, "Can't allocate transmit buffer\n"); | |
969 | goto fail5; | |
970 | } | |
971 | ||
541e7ef0 | 972 | /* Add SDIO capability when available */ |
5b27a1a5 NF |
973 | if (at91mci_is_mci1rev2xx()) { |
974 | /* at91mci MCI1 rev2xx sdio interrupt erratum */ | |
541e7ef0 NF |
975 | if (host->board->wire4 || !host->board->slot_b) |
976 | mmc->caps |= MMC_CAP_SDIO_IRQ; | |
977 | } | |
978 | ||
6e996ee8 DB |
979 | /* |
980 | * Reserve GPIOs ... board init code makes sure these pins are set | |
981 | * up as GPIOs with the right direction (input, except for vcc) | |
982 | */ | |
983 | if (host->board->det_pin) { | |
984 | ret = gpio_request(host->board->det_pin, "mmc_detect"); | |
985 | if (ret < 0) { | |
986 | dev_dbg(&pdev->dev, "couldn't claim card detect pin\n"); | |
3780d906 | 987 | goto fail4b; |
6e996ee8 DB |
988 | } |
989 | } | |
990 | if (host->board->wp_pin) { | |
991 | ret = gpio_request(host->board->wp_pin, "mmc_wp"); | |
992 | if (ret < 0) { | |
993 | dev_dbg(&pdev->dev, "couldn't claim wp sense pin\n"); | |
994 | goto fail4; | |
995 | } | |
996 | } | |
997 | if (host->board->vcc_pin) { | |
998 | ret = gpio_request(host->board->vcc_pin, "mmc_vcc"); | |
999 | if (ret < 0) { | |
1000 | dev_dbg(&pdev->dev, "couldn't claim vcc switch pin\n"); | |
1001 | goto fail3; | |
1002 | } | |
1003 | } | |
1004 | ||
65dbf343 AV |
1005 | /* |
1006 | * Get Clock | |
1007 | */ | |
3dd3b039 AV |
1008 | host->mci_clk = clk_get(&pdev->dev, "mci_clk"); |
1009 | if (IS_ERR(host->mci_clk)) { | |
6e996ee8 DB |
1010 | ret = -ENODEV; |
1011 | dev_dbg(&pdev->dev, "no mci_clk?\n"); | |
1012 | goto fail2; | |
65dbf343 | 1013 | } |
65dbf343 | 1014 | |
17ea0595 AV |
1015 | /* |
1016 | * Map I/O region | |
1017 | */ | |
1018 | host->baseaddr = ioremap(res->start, res->end - res->start + 1); | |
1019 | if (!host->baseaddr) { | |
6e996ee8 DB |
1020 | ret = -ENOMEM; |
1021 | goto fail1; | |
17ea0595 | 1022 | } |
e0b19b83 AV |
1023 | |
1024 | /* | |
1025 | * Reset hardware | |
1026 | */ | |
3dd3b039 | 1027 | clk_enable(host->mci_clk); /* Enable the peripheral clock */ |
e0b19b83 AV |
1028 | at91_mci_disable(host); |
1029 | at91_mci_enable(host); | |
1030 | ||
65dbf343 AV |
1031 | /* |
1032 | * Allocate the MCI interrupt | |
1033 | */ | |
17ea0595 | 1034 | host->irq = platform_get_irq(pdev, 0); |
6e996ee8 DB |
1035 | ret = request_irq(host->irq, at91_mci_irq, IRQF_SHARED, |
1036 | mmc_hostname(mmc), host); | |
65dbf343 | 1037 | if (ret) { |
6e996ee8 DB |
1038 | dev_dbg(&pdev->dev, "request MCI interrupt failed\n"); |
1039 | goto fail0; | |
65dbf343 AV |
1040 | } |
1041 | ||
99ba0405 NF |
1042 | setup_timer(&host->timer, at91_timeout_timer, (unsigned long)host); |
1043 | ||
65dbf343 AV |
1044 | platform_set_drvdata(pdev, mmc); |
1045 | ||
1046 | /* | |
1047 | * Add host to MMC layer | |
1048 | */ | |
63b66438 | 1049 | if (host->board->det_pin) { |
6e996ee8 | 1050 | host->present = !gpio_get_value(host->board->det_pin); |
63b66438 | 1051 | } |
65dbf343 AV |
1052 | else |
1053 | host->present = -1; | |
1054 | ||
1055 | mmc_add_host(mmc); | |
1056 | ||
1057 | /* | |
1058 | * monitor card insertion/removal if we can | |
1059 | */ | |
1060 | if (host->board->det_pin) { | |
6e996ee8 DB |
1061 | ret = request_irq(gpio_to_irq(host->board->det_pin), |
1062 | at91_mmc_det_irq, 0, mmc_hostname(mmc), host); | |
65dbf343 | 1063 | if (ret) |
6e996ee8 DB |
1064 | dev_warn(&pdev->dev, "request MMC detect irq failed\n"); |
1065 | else | |
1066 | device_init_wakeup(&pdev->dev, 1); | |
65dbf343 AV |
1067 | } |
1068 | ||
f3a8efa9 | 1069 | pr_debug("Added MCI driver\n"); |
65dbf343 AV |
1070 | |
1071 | return 0; | |
6e996ee8 DB |
1072 | |
1073 | fail0: | |
1074 | clk_disable(host->mci_clk); | |
1075 | iounmap(host->baseaddr); | |
1076 | fail1: | |
1077 | clk_put(host->mci_clk); | |
1078 | fail2: | |
1079 | if (host->board->vcc_pin) | |
1080 | gpio_free(host->board->vcc_pin); | |
1081 | fail3: | |
1082 | if (host->board->wp_pin) | |
1083 | gpio_free(host->board->wp_pin); | |
1084 | fail4: | |
1085 | if (host->board->det_pin) | |
1086 | gpio_free(host->board->det_pin); | |
3780d906 WM |
1087 | fail4b: |
1088 | if (host->buffer) | |
1089 | dma_free_coherent(&pdev->dev, MCI_BUFSIZE, | |
1090 | host->buffer, host->physical_address); | |
6e996ee8 DB |
1091 | fail5: |
1092 | mmc_free_host(mmc); | |
1093 | fail6: | |
1094 | release_mem_region(res->start, res->end - res->start + 1); | |
1095 | dev_err(&pdev->dev, "probe failed, err %d\n", ret); | |
1096 | return ret; | |
65dbf343 AV |
1097 | } |
1098 | ||
1099 | /* | |
1100 | * Remove a device | |
1101 | */ | |
a26b498c | 1102 | static int __exit at91_mci_remove(struct platform_device *pdev) |
65dbf343 AV |
1103 | { |
1104 | struct mmc_host *mmc = platform_get_drvdata(pdev); | |
1105 | struct at91mci_host *host; | |
17ea0595 | 1106 | struct resource *res; |
65dbf343 AV |
1107 | |
1108 | if (!mmc) | |
1109 | return -1; | |
1110 | ||
1111 | host = mmc_priv(mmc); | |
1112 | ||
3780d906 WM |
1113 | if (host->buffer) |
1114 | dma_free_coherent(&pdev->dev, MCI_BUFSIZE, | |
1115 | host->buffer, host->physical_address); | |
1116 | ||
e0cda54e | 1117 | if (host->board->det_pin) { |
6e996ee8 DB |
1118 | if (device_can_wakeup(&pdev->dev)) |
1119 | free_irq(gpio_to_irq(host->board->det_pin), host); | |
63b66438 | 1120 | device_init_wakeup(&pdev->dev, 0); |
6e996ee8 | 1121 | gpio_free(host->board->det_pin); |
65dbf343 AV |
1122 | } |
1123 | ||
e0b19b83 | 1124 | at91_mci_disable(host); |
e181dce8 | 1125 | del_timer_sync(&host->timer); |
17ea0595 AV |
1126 | mmc_remove_host(mmc); |
1127 | free_irq(host->irq, host); | |
65dbf343 | 1128 | |
3dd3b039 AV |
1129 | clk_disable(host->mci_clk); /* Disable the peripheral clock */ |
1130 | clk_put(host->mci_clk); | |
65dbf343 | 1131 | |
6e996ee8 DB |
1132 | if (host->board->vcc_pin) |
1133 | gpio_free(host->board->vcc_pin); | |
1134 | if (host->board->wp_pin) | |
1135 | gpio_free(host->board->wp_pin); | |
1136 | ||
17ea0595 AV |
1137 | iounmap(host->baseaddr); |
1138 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1139 | release_mem_region(res->start, res->end - res->start + 1); | |
65dbf343 | 1140 | |
17ea0595 AV |
1141 | mmc_free_host(mmc); |
1142 | platform_set_drvdata(pdev, NULL); | |
b44fb7a0 | 1143 | pr_debug("MCI Removed\n"); |
65dbf343 AV |
1144 | |
1145 | return 0; | |
1146 | } | |
1147 | ||
1148 | #ifdef CONFIG_PM | |
1149 | static int at91_mci_suspend(struct platform_device *pdev, pm_message_t state) | |
1150 | { | |
1151 | struct mmc_host *mmc = platform_get_drvdata(pdev); | |
63b66438 | 1152 | struct at91mci_host *host = mmc_priv(mmc); |
65dbf343 AV |
1153 | int ret = 0; |
1154 | ||
e0cda54e | 1155 | if (host->board->det_pin && device_may_wakeup(&pdev->dev)) |
63b66438 MP |
1156 | enable_irq_wake(host->board->det_pin); |
1157 | ||
65dbf343 AV |
1158 | if (mmc) |
1159 | ret = mmc_suspend_host(mmc, state); | |
1160 | ||
1161 | return ret; | |
1162 | } | |
1163 | ||
1164 | static int at91_mci_resume(struct platform_device *pdev) | |
1165 | { | |
1166 | struct mmc_host *mmc = platform_get_drvdata(pdev); | |
63b66438 | 1167 | struct at91mci_host *host = mmc_priv(mmc); |
65dbf343 AV |
1168 | int ret = 0; |
1169 | ||
e0cda54e | 1170 | if (host->board->det_pin && device_may_wakeup(&pdev->dev)) |
63b66438 MP |
1171 | disable_irq_wake(host->board->det_pin); |
1172 | ||
65dbf343 AV |
1173 | if (mmc) |
1174 | ret = mmc_resume_host(mmc); | |
1175 | ||
1176 | return ret; | |
1177 | } | |
1178 | #else | |
1179 | #define at91_mci_suspend NULL | |
1180 | #define at91_mci_resume NULL | |
1181 | #endif | |
1182 | ||
1183 | static struct platform_driver at91_mci_driver = { | |
a26b498c | 1184 | .remove = __exit_p(at91_mci_remove), |
65dbf343 AV |
1185 | .suspend = at91_mci_suspend, |
1186 | .resume = at91_mci_resume, | |
1187 | .driver = { | |
1188 | .name = DRIVER_NAME, | |
1189 | .owner = THIS_MODULE, | |
1190 | }, | |
1191 | }; | |
1192 | ||
1193 | static int __init at91_mci_init(void) | |
1194 | { | |
a26b498c | 1195 | return platform_driver_probe(&at91_mci_driver, at91_mci_probe); |
65dbf343 AV |
1196 | } |
1197 | ||
1198 | static void __exit at91_mci_exit(void) | |
1199 | { | |
1200 | platform_driver_unregister(&at91_mci_driver); | |
1201 | } | |
1202 | ||
1203 | module_init(at91_mci_init); | |
1204 | module_exit(at91_mci_exit); | |
1205 | ||
1206 | MODULE_DESCRIPTION("AT91 Multimedia Card Interface driver"); | |
1207 | MODULE_AUTHOR("Nick Randell"); | |
1208 | MODULE_LICENSE("GPL"); | |
bc65c724 | 1209 | MODULE_ALIAS("platform:at91_mci"); |