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65dbf343 | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/at91_mci.c - ATMEL AT91 MCI Driver |
65dbf343 AV |
3 | * |
4 | * Copyright (C) 2005 Cougar Creek Computing Devices Ltd, All Rights Reserved | |
5 | * | |
6 | * Copyright (C) 2006 Malcolm Noyes | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | /* | |
99eeb8df | 14 | This is the AT91 MCI driver that has been tested with both MMC cards |
65dbf343 AV |
15 | and SD-cards. Boards that support write protect are now supported. |
16 | The CCAT91SBC001 board does not support SD cards. | |
17 | ||
18 | The three entry points are at91_mci_request, at91_mci_set_ios | |
19 | and at91_mci_get_ro. | |
20 | ||
21 | SET IOS | |
22 | This configures the device to put it into the correct mode and clock speed | |
23 | required. | |
24 | ||
25 | MCI REQUEST | |
26 | MCI request processes the commands sent in the mmc_request structure. This | |
27 | can consist of a processing command and a stop command in the case of | |
28 | multiple block transfers. | |
29 | ||
30 | There are three main types of request, commands, reads and writes. | |
31 | ||
32 | Commands are straight forward. The command is submitted to the controller and | |
33 | the request function returns. When the controller generates an interrupt to indicate | |
34 | the command is finished, the response to the command are read and the mmc_request_done | |
35 | function called to end the request. | |
36 | ||
37 | Reads and writes work in a similar manner to normal commands but involve the PDC (DMA) | |
38 | controller to manage the transfers. | |
39 | ||
40 | A read is done from the controller directly to the scatterlist passed in from the request. | |
99eeb8df AV |
41 | Due to a bug in the AT91RM9200 controller, when a read is completed, all the words are byte |
42 | swapped in the scatterlist buffers. AT91SAM926x are not affected by this bug. | |
65dbf343 AV |
43 | |
44 | The sequence of read interrupts is: ENDRX, RXBUFF, CMDRDY | |
45 | ||
46 | A write is slightly different in that the bytes to write are read from the scatterlist | |
47 | into a dma memory buffer (this is in case the source buffer should be read only). The | |
48 | entire write buffer is then done from this single dma memory buffer. | |
49 | ||
50 | The sequence of write interrupts is: ENDTX, TXBUFE, NOTBUSY, CMDRDY | |
51 | ||
52 | GET RO | |
53 | Gets the status of the write protect pin, if available. | |
54 | */ | |
55 | ||
65dbf343 AV |
56 | #include <linux/module.h> |
57 | #include <linux/moduleparam.h> | |
58 | #include <linux/init.h> | |
59 | #include <linux/ioport.h> | |
60 | #include <linux/platform_device.h> | |
61 | #include <linux/interrupt.h> | |
62 | #include <linux/blkdev.h> | |
63 | #include <linux/delay.h> | |
64 | #include <linux/err.h> | |
65 | #include <linux/dma-mapping.h> | |
66 | #include <linux/clk.h> | |
93a3ddc2 | 67 | #include <linux/atmel_pdc.h> |
65dbf343 AV |
68 | |
69 | #include <linux/mmc/host.h> | |
65dbf343 AV |
70 | |
71 | #include <asm/io.h> | |
72 | #include <asm/irq.h> | |
6e996ee8 DB |
73 | #include <asm/gpio.h> |
74 | ||
65dbf343 AV |
75 | #include <asm/mach/mmc.h> |
76 | #include <asm/arch/board.h> | |
99eeb8df | 77 | #include <asm/arch/cpu.h> |
55d8baee | 78 | #include <asm/arch/at91_mci.h> |
65dbf343 AV |
79 | |
80 | #define DRIVER_NAME "at91_mci" | |
81 | ||
df05a303 AV |
82 | #define FL_SENT_COMMAND (1 << 0) |
83 | #define FL_SENT_STOP (1 << 1) | |
65dbf343 | 84 | |
df05a303 AV |
85 | #define AT91_MCI_ERRORS (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE \ |
86 | | AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE \ | |
37b758e8 | 87 | | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE) |
65dbf343 | 88 | |
e0b19b83 AV |
89 | #define at91_mci_read(host, reg) __raw_readl((host)->baseaddr + (reg)) |
90 | #define at91_mci_write(host, reg, val) __raw_writel((val), (host)->baseaddr + (reg)) | |
65dbf343 | 91 | |
65dbf343 AV |
92 | |
93 | /* | |
94 | * Low level type for this driver | |
95 | */ | |
96 | struct at91mci_host | |
97 | { | |
98 | struct mmc_host *mmc; | |
99 | struct mmc_command *cmd; | |
100 | struct mmc_request *request; | |
101 | ||
e0b19b83 | 102 | void __iomem *baseaddr; |
17ea0595 | 103 | int irq; |
e0b19b83 | 104 | |
65dbf343 AV |
105 | struct at91_mmc_data *board; |
106 | int present; | |
107 | ||
3dd3b039 AV |
108 | struct clk *mci_clk; |
109 | ||
65dbf343 AV |
110 | /* |
111 | * Flag indicating when the command has been sent. This is used to | |
112 | * work out whether or not to send the stop | |
113 | */ | |
114 | unsigned int flags; | |
115 | /* flag for current bus settings */ | |
116 | u32 bus_mode; | |
117 | ||
118 | /* DMA buffer used for transmitting */ | |
119 | unsigned int* buffer; | |
120 | dma_addr_t physical_address; | |
121 | unsigned int total_length; | |
122 | ||
123 | /* Latest in the scatterlist that has been enabled for transfer, but not freed */ | |
124 | int in_use_index; | |
125 | ||
126 | /* Latest in the scatterlist that has been enabled for transfer */ | |
127 | int transfer_index; | |
e181dce8 MP |
128 | |
129 | /* Timer for timeouts */ | |
130 | struct timer_list timer; | |
65dbf343 AV |
131 | }; |
132 | ||
c5a89c6c MP |
133 | /* |
134 | * Reset the controller and restore most of the state | |
135 | */ | |
136 | static void at91_reset_host(struct at91mci_host *host) | |
137 | { | |
138 | unsigned long flags; | |
139 | u32 mr; | |
140 | u32 sdcr; | |
141 | u32 dtor; | |
142 | u32 imr; | |
143 | ||
144 | local_irq_save(flags); | |
145 | imr = at91_mci_read(host, AT91_MCI_IMR); | |
146 | ||
147 | at91_mci_write(host, AT91_MCI_IDR, 0xffffffff); | |
148 | ||
149 | /* save current state */ | |
150 | mr = at91_mci_read(host, AT91_MCI_MR) & 0x7fff; | |
151 | sdcr = at91_mci_read(host, AT91_MCI_SDCR); | |
152 | dtor = at91_mci_read(host, AT91_MCI_DTOR); | |
153 | ||
154 | /* reset the controller */ | |
155 | at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST); | |
156 | ||
157 | /* restore state */ | |
158 | at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN); | |
159 | at91_mci_write(host, AT91_MCI_MR, mr); | |
160 | at91_mci_write(host, AT91_MCI_SDCR, sdcr); | |
161 | at91_mci_write(host, AT91_MCI_DTOR, dtor); | |
162 | at91_mci_write(host, AT91_MCI_IER, imr); | |
163 | ||
164 | /* make sure sdio interrupts will fire */ | |
165 | at91_mci_read(host, AT91_MCI_SR); | |
166 | ||
167 | local_irq_restore(flags); | |
168 | } | |
169 | ||
e181dce8 MP |
170 | static void at91_timeout_timer(unsigned long data) |
171 | { | |
172 | struct at91mci_host *host; | |
173 | ||
174 | host = (struct at91mci_host *)data; | |
175 | ||
176 | if (host->request) { | |
177 | dev_err(host->mmc->parent, "Timeout waiting end of packet\n"); | |
178 | ||
179 | if (host->cmd && host->cmd->data) { | |
180 | host->cmd->data->error = -ETIMEDOUT; | |
181 | } else { | |
182 | if (host->cmd) | |
183 | host->cmd->error = -ETIMEDOUT; | |
184 | else | |
185 | host->request->cmd->error = -ETIMEDOUT; | |
186 | } | |
187 | ||
c5a89c6c | 188 | at91_reset_host(host); |
e181dce8 MP |
189 | mmc_request_done(host->mmc, host->request); |
190 | } | |
191 | } | |
192 | ||
65dbf343 AV |
193 | /* |
194 | * Copy from sg to a dma block - used for transfers | |
195 | */ | |
e8d04d3d | 196 | static inline void at91_mci_sg_to_dma(struct at91mci_host *host, struct mmc_data *data) |
65dbf343 AV |
197 | { |
198 | unsigned int len, i, size; | |
199 | unsigned *dmabuf = host->buffer; | |
200 | ||
201 | size = host->total_length; | |
202 | len = data->sg_len; | |
203 | ||
204 | /* | |
205 | * Just loop through all entries. Size might not | |
206 | * be the entire list though so make sure that | |
207 | * we do not transfer too much. | |
208 | */ | |
209 | for (i = 0; i < len; i++) { | |
210 | struct scatterlist *sg; | |
211 | int amount; | |
65dbf343 AV |
212 | unsigned int *sgbuffer; |
213 | ||
214 | sg = &data->sg[i]; | |
215 | ||
45711f1a | 216 | sgbuffer = kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset; |
65dbf343 AV |
217 | amount = min(size, sg->length); |
218 | size -= amount; | |
65dbf343 | 219 | |
99eeb8df AV |
220 | if (cpu_is_at91rm9200()) { /* AT91RM9200 errata */ |
221 | int index; | |
222 | ||
223 | for (index = 0; index < (amount / 4); index++) | |
224 | *dmabuf++ = swab32(sgbuffer[index]); | |
225 | } | |
226 | else | |
227 | memcpy(dmabuf, sgbuffer, amount); | |
65dbf343 AV |
228 | |
229 | kunmap_atomic(sgbuffer, KM_BIO_SRC_IRQ); | |
230 | ||
231 | if (size == 0) | |
232 | break; | |
233 | } | |
234 | ||
235 | /* | |
236 | * Check that we didn't get a request to transfer | |
237 | * more data than can fit into the SG list. | |
238 | */ | |
239 | BUG_ON(size != 0); | |
240 | } | |
241 | ||
242 | /* | |
243 | * Prepare a dma read | |
244 | */ | |
e8d04d3d | 245 | static void at91_mci_pre_dma_read(struct at91mci_host *host) |
65dbf343 AV |
246 | { |
247 | int i; | |
248 | struct scatterlist *sg; | |
249 | struct mmc_command *cmd; | |
250 | struct mmc_data *data; | |
251 | ||
b44fb7a0 | 252 | pr_debug("pre dma read\n"); |
65dbf343 AV |
253 | |
254 | cmd = host->cmd; | |
255 | if (!cmd) { | |
b44fb7a0 | 256 | pr_debug("no command\n"); |
65dbf343 AV |
257 | return; |
258 | } | |
259 | ||
260 | data = cmd->data; | |
261 | if (!data) { | |
b44fb7a0 | 262 | pr_debug("no data\n"); |
65dbf343 AV |
263 | return; |
264 | } | |
265 | ||
266 | for (i = 0; i < 2; i++) { | |
267 | /* nothing left to transfer */ | |
268 | if (host->transfer_index >= data->sg_len) { | |
b44fb7a0 | 269 | pr_debug("Nothing left to transfer (index = %d)\n", host->transfer_index); |
65dbf343 AV |
270 | break; |
271 | } | |
272 | ||
273 | /* Check to see if this needs filling */ | |
274 | if (i == 0) { | |
93a3ddc2 | 275 | if (at91_mci_read(host, ATMEL_PDC_RCR) != 0) { |
b44fb7a0 | 276 | pr_debug("Transfer active in current\n"); |
65dbf343 AV |
277 | continue; |
278 | } | |
279 | } | |
280 | else { | |
93a3ddc2 | 281 | if (at91_mci_read(host, ATMEL_PDC_RNCR) != 0) { |
b44fb7a0 | 282 | pr_debug("Transfer active in next\n"); |
65dbf343 AV |
283 | continue; |
284 | } | |
285 | } | |
286 | ||
287 | /* Setup the next transfer */ | |
b44fb7a0 | 288 | pr_debug("Using transfer index %d\n", host->transfer_index); |
65dbf343 AV |
289 | |
290 | sg = &data->sg[host->transfer_index++]; | |
b44fb7a0 | 291 | pr_debug("sg = %p\n", sg); |
65dbf343 | 292 | |
45711f1a | 293 | sg->dma_address = dma_map_page(NULL, sg_page(sg), sg->offset, sg->length, DMA_FROM_DEVICE); |
65dbf343 | 294 | |
b44fb7a0 | 295 | pr_debug("dma address = %08X, length = %d\n", sg->dma_address, sg->length); |
65dbf343 AV |
296 | |
297 | if (i == 0) { | |
93a3ddc2 | 298 | at91_mci_write(host, ATMEL_PDC_RPR, sg->dma_address); |
80f92546 | 299 | at91_mci_write(host, ATMEL_PDC_RCR, (data->blksz & 0x3) ? sg->length : sg->length / 4); |
65dbf343 AV |
300 | } |
301 | else { | |
93a3ddc2 | 302 | at91_mci_write(host, ATMEL_PDC_RNPR, sg->dma_address); |
80f92546 | 303 | at91_mci_write(host, ATMEL_PDC_RNCR, (data->blksz & 0x3) ? sg->length : sg->length / 4); |
65dbf343 AV |
304 | } |
305 | } | |
306 | ||
b44fb7a0 | 307 | pr_debug("pre dma read done\n"); |
65dbf343 AV |
308 | } |
309 | ||
310 | /* | |
311 | * Handle after a dma read | |
312 | */ | |
e8d04d3d | 313 | static void at91_mci_post_dma_read(struct at91mci_host *host) |
65dbf343 AV |
314 | { |
315 | struct mmc_command *cmd; | |
316 | struct mmc_data *data; | |
317 | ||
b44fb7a0 | 318 | pr_debug("post dma read\n"); |
65dbf343 AV |
319 | |
320 | cmd = host->cmd; | |
321 | if (!cmd) { | |
b44fb7a0 | 322 | pr_debug("no command\n"); |
65dbf343 AV |
323 | return; |
324 | } | |
325 | ||
326 | data = cmd->data; | |
327 | if (!data) { | |
b44fb7a0 | 328 | pr_debug("no data\n"); |
65dbf343 AV |
329 | return; |
330 | } | |
331 | ||
332 | while (host->in_use_index < host->transfer_index) { | |
65dbf343 AV |
333 | struct scatterlist *sg; |
334 | ||
b44fb7a0 | 335 | pr_debug("finishing index %d\n", host->in_use_index); |
65dbf343 AV |
336 | |
337 | sg = &data->sg[host->in_use_index++]; | |
338 | ||
b44fb7a0 | 339 | pr_debug("Unmapping page %08X\n", sg->dma_address); |
65dbf343 AV |
340 | |
341 | dma_unmap_page(NULL, sg->dma_address, sg->length, DMA_FROM_DEVICE); | |
342 | ||
65dbf343 AV |
343 | data->bytes_xfered += sg->length; |
344 | ||
99eeb8df | 345 | if (cpu_is_at91rm9200()) { /* AT91RM9200 errata */ |
ed99c541 | 346 | unsigned int *buffer; |
99eeb8df | 347 | int index; |
65dbf343 | 348 | |
ed99c541 | 349 | /* Swap the contents of the buffer */ |
45711f1a | 350 | buffer = kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset; |
ed99c541 NF |
351 | pr_debug("buffer = %p, length = %d\n", buffer, sg->length); |
352 | ||
99eeb8df AV |
353 | for (index = 0; index < (sg->length / 4); index++) |
354 | buffer[index] = swab32(buffer[index]); | |
ed99c541 NF |
355 | |
356 | kunmap_atomic(buffer, KM_BIO_SRC_IRQ); | |
65dbf343 | 357 | } |
99eeb8df | 358 | |
45711f1a | 359 | flush_dcache_page(sg_page(sg)); |
65dbf343 AV |
360 | } |
361 | ||
362 | /* Is there another transfer to trigger? */ | |
363 | if (host->transfer_index < data->sg_len) | |
e8d04d3d | 364 | at91_mci_pre_dma_read(host); |
65dbf343 | 365 | else { |
ed99c541 | 366 | at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_ENDRX); |
e0b19b83 | 367 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_RXBUFF); |
65dbf343 AV |
368 | } |
369 | ||
b44fb7a0 | 370 | pr_debug("post dma read done\n"); |
65dbf343 AV |
371 | } |
372 | ||
373 | /* | |
374 | * Handle transmitted data | |
375 | */ | |
376 | static void at91_mci_handle_transmitted(struct at91mci_host *host) | |
377 | { | |
378 | struct mmc_command *cmd; | |
379 | struct mmc_data *data; | |
380 | ||
b44fb7a0 | 381 | pr_debug("Handling the transmit\n"); |
65dbf343 AV |
382 | |
383 | /* Disable the transfer */ | |
93a3ddc2 | 384 | at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); |
65dbf343 AV |
385 | |
386 | /* Now wait for cmd ready */ | |
e0b19b83 | 387 | at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_TXBUFE); |
65dbf343 AV |
388 | |
389 | cmd = host->cmd; | |
390 | if (!cmd) return; | |
391 | ||
392 | data = cmd->data; | |
393 | if (!data) return; | |
394 | ||
be0192aa | 395 | if (cmd->data->blocks > 1) { |
ed99c541 NF |
396 | pr_debug("multiple write : wait for BLKE...\n"); |
397 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_BLKE); | |
398 | } else | |
399 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY); | |
400 | ||
65dbf343 AV |
401 | data->bytes_xfered = host->total_length; |
402 | } | |
403 | ||
ed99c541 NF |
404 | /*Handle after command sent ready*/ |
405 | static int at91_mci_handle_cmdrdy(struct at91mci_host *host) | |
406 | { | |
407 | if (!host->cmd) | |
408 | return 1; | |
409 | else if (!host->cmd->data) { | |
410 | if (host->flags & FL_SENT_STOP) { | |
411 | /*After multi block write, we must wait for NOTBUSY*/ | |
412 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY); | |
413 | } else return 1; | |
414 | } else if (host->cmd->data->flags & MMC_DATA_WRITE) { | |
415 | /*After sendding multi-block-write command, start DMA transfer*/ | |
416 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_TXBUFE); | |
417 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_BLKE); | |
418 | at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); | |
419 | } | |
420 | ||
421 | /* command not completed, have to wait */ | |
422 | return 0; | |
423 | } | |
424 | ||
425 | ||
65dbf343 AV |
426 | /* |
427 | * Enable the controller | |
428 | */ | |
e0b19b83 | 429 | static void at91_mci_enable(struct at91mci_host *host) |
65dbf343 | 430 | { |
ed99c541 NF |
431 | unsigned int mr; |
432 | ||
e0b19b83 | 433 | at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN); |
f3a8efa9 | 434 | at91_mci_write(host, AT91_MCI_IDR, 0xffffffff); |
e0b19b83 | 435 | at91_mci_write(host, AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC); |
ed99c541 NF |
436 | mr = AT91_MCI_PDCMODE | 0x34a; |
437 | ||
438 | if (cpu_is_at91sam9260() || cpu_is_at91sam9263()) | |
439 | mr |= AT91_MCI_RDPROOF | AT91_MCI_WRPROOF; | |
440 | ||
441 | at91_mci_write(host, AT91_MCI_MR, mr); | |
99eeb8df AV |
442 | |
443 | /* use Slot A or B (only one at same time) */ | |
444 | at91_mci_write(host, AT91_MCI_SDCR, host->board->slot_b); | |
65dbf343 AV |
445 | } |
446 | ||
447 | /* | |
448 | * Disable the controller | |
449 | */ | |
e0b19b83 | 450 | static void at91_mci_disable(struct at91mci_host *host) |
65dbf343 | 451 | { |
e0b19b83 | 452 | at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST); |
65dbf343 AV |
453 | } |
454 | ||
455 | /* | |
456 | * Send a command | |
65dbf343 | 457 | */ |
ed99c541 | 458 | static void at91_mci_send_command(struct at91mci_host *host, struct mmc_command *cmd) |
65dbf343 AV |
459 | { |
460 | unsigned int cmdr, mr; | |
461 | unsigned int block_length; | |
462 | struct mmc_data *data = cmd->data; | |
463 | ||
464 | unsigned int blocks; | |
465 | unsigned int ier = 0; | |
466 | ||
467 | host->cmd = cmd; | |
468 | ||
ed99c541 | 469 | /* Needed for leaving busy state before CMD1 */ |
e0b19b83 | 470 | if ((at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->opcode == 1)) { |
b44fb7a0 | 471 | pr_debug("Clearing timeout\n"); |
e0b19b83 AV |
472 | at91_mci_write(host, AT91_MCI_ARGR, 0); |
473 | at91_mci_write(host, AT91_MCI_CMDR, AT91_MCI_OPDCMD); | |
474 | while (!(at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_CMDRDY)) { | |
65dbf343 | 475 | /* spin */ |
e0b19b83 | 476 | pr_debug("Clearing: SR = %08X\n", at91_mci_read(host, AT91_MCI_SR)); |
65dbf343 AV |
477 | } |
478 | } | |
ed99c541 | 479 | |
65dbf343 AV |
480 | cmdr = cmd->opcode; |
481 | ||
482 | if (mmc_resp_type(cmd) == MMC_RSP_NONE) | |
483 | cmdr |= AT91_MCI_RSPTYP_NONE; | |
484 | else { | |
485 | /* if a response is expected then allow maximum response latancy */ | |
486 | cmdr |= AT91_MCI_MAXLAT; | |
487 | /* set 136 bit response for R2, 48 bit response otherwise */ | |
488 | if (mmc_resp_type(cmd) == MMC_RSP_R2) | |
489 | cmdr |= AT91_MCI_RSPTYP_136; | |
490 | else | |
491 | cmdr |= AT91_MCI_RSPTYP_48; | |
492 | } | |
493 | ||
494 | if (data) { | |
1d4de9ed | 495 | |
80f92546 | 496 | if ( cpu_is_at91rm9200() && (data->blksz & 0x3) ) { |
1d4de9ed MP |
497 | pr_debug("Unsupported block size\n"); |
498 | cmd->error = -EINVAL; | |
499 | mmc_request_done(host->mmc, host->request); | |
500 | return; | |
501 | } | |
502 | ||
a3fd4a1b | 503 | block_length = data->blksz; |
65dbf343 AV |
504 | blocks = data->blocks; |
505 | ||
506 | /* always set data start - also set direction flag for read */ | |
507 | if (data->flags & MMC_DATA_READ) | |
508 | cmdr |= (AT91_MCI_TRDIR | AT91_MCI_TRCMD_START); | |
509 | else if (data->flags & MMC_DATA_WRITE) | |
510 | cmdr |= AT91_MCI_TRCMD_START; | |
511 | ||
512 | if (data->flags & MMC_DATA_STREAM) | |
513 | cmdr |= AT91_MCI_TRTYP_STREAM; | |
be0192aa | 514 | if (data->blocks > 1) |
65dbf343 AV |
515 | cmdr |= AT91_MCI_TRTYP_MULTIPLE; |
516 | } | |
517 | else { | |
518 | block_length = 0; | |
519 | blocks = 0; | |
520 | } | |
521 | ||
b6cedb38 | 522 | if (host->flags & FL_SENT_STOP) |
65dbf343 AV |
523 | cmdr |= AT91_MCI_TRCMD_STOP; |
524 | ||
525 | if (host->bus_mode == MMC_BUSMODE_OPENDRAIN) | |
526 | cmdr |= AT91_MCI_OPDCMD; | |
527 | ||
528 | /* | |
529 | * Set the arguments and send the command | |
530 | */ | |
f3a8efa9 | 531 | pr_debug("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n", |
e0b19b83 | 532 | cmd->opcode, cmdr, cmd->arg, blocks, block_length, at91_mci_read(host, AT91_MCI_MR)); |
65dbf343 AV |
533 | |
534 | if (!data) { | |
93a3ddc2 AV |
535 | at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS | ATMEL_PDC_RXTDIS); |
536 | at91_mci_write(host, ATMEL_PDC_RPR, 0); | |
537 | at91_mci_write(host, ATMEL_PDC_RCR, 0); | |
538 | at91_mci_write(host, ATMEL_PDC_RNPR, 0); | |
539 | at91_mci_write(host, ATMEL_PDC_RNCR, 0); | |
540 | at91_mci_write(host, ATMEL_PDC_TPR, 0); | |
541 | at91_mci_write(host, ATMEL_PDC_TCR, 0); | |
542 | at91_mci_write(host, ATMEL_PDC_TNPR, 0); | |
543 | at91_mci_write(host, ATMEL_PDC_TNCR, 0); | |
ed99c541 NF |
544 | ier = AT91_MCI_CMDRDY; |
545 | } else { | |
546 | /* zero block length and PDC mode */ | |
547 | mr = at91_mci_read(host, AT91_MCI_MR) & 0x7fff; | |
80f92546 MP |
548 | mr |= (data->blksz & 0x3) ? AT91_MCI_PDCFBYTE : 0; |
549 | mr |= (block_length << 16); | |
550 | mr |= AT91_MCI_PDCMODE; | |
551 | at91_mci_write(host, AT91_MCI_MR, mr); | |
e0b19b83 | 552 | |
c5a89c6c MP |
553 | if (!cpu_is_at91rm9200()) |
554 | at91_mci_write(host, AT91_MCI_BLKR, | |
555 | AT91_MCI_BLKR_BCNT(blocks) | | |
556 | AT91_MCI_BLKR_BLKLEN(block_length)); | |
557 | ||
ed99c541 NF |
558 | /* |
559 | * Disable the PDC controller | |
560 | */ | |
561 | at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); | |
65dbf343 | 562 | |
ed99c541 NF |
563 | if (cmdr & AT91_MCI_TRCMD_START) { |
564 | data->bytes_xfered = 0; | |
565 | host->transfer_index = 0; | |
566 | host->in_use_index = 0; | |
567 | if (cmdr & AT91_MCI_TRDIR) { | |
568 | /* | |
569 | * Handle a read | |
570 | */ | |
571 | host->buffer = NULL; | |
572 | host->total_length = 0; | |
573 | ||
574 | at91_mci_pre_dma_read(host); | |
575 | ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */; | |
576 | } | |
577 | else { | |
578 | /* | |
579 | * Handle a write | |
580 | */ | |
581 | host->total_length = block_length * blocks; | |
582 | host->buffer = dma_alloc_coherent(NULL, | |
583 | host->total_length, | |
584 | &host->physical_address, GFP_KERNEL); | |
585 | ||
586 | at91_mci_sg_to_dma(host, data); | |
587 | ||
588 | pr_debug("Transmitting %d bytes\n", host->total_length); | |
589 | ||
590 | at91_mci_write(host, ATMEL_PDC_TPR, host->physical_address); | |
80f92546 MP |
591 | at91_mci_write(host, ATMEL_PDC_TCR, (data->blksz & 0x3) ? |
592 | host->total_length : host->total_length / 4); | |
593 | ||
ed99c541 NF |
594 | ier = AT91_MCI_CMDRDY; |
595 | } | |
65dbf343 AV |
596 | } |
597 | } | |
598 | ||
599 | /* | |
600 | * Send the command and then enable the PDC - not the other way round as | |
601 | * the data sheet says | |
602 | */ | |
603 | ||
e0b19b83 AV |
604 | at91_mci_write(host, AT91_MCI_ARGR, cmd->arg); |
605 | at91_mci_write(host, AT91_MCI_CMDR, cmdr); | |
65dbf343 AV |
606 | |
607 | if (cmdr & AT91_MCI_TRCMD_START) { | |
608 | if (cmdr & AT91_MCI_TRDIR) | |
93a3ddc2 | 609 | at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN); |
65dbf343 | 610 | } |
65dbf343 | 611 | |
ed99c541 | 612 | /* Enable selected interrupts */ |
df05a303 | 613 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_ERRORS | ier); |
65dbf343 AV |
614 | } |
615 | ||
616 | /* | |
617 | * Process the next step in the request | |
618 | */ | |
e8d04d3d | 619 | static void at91_mci_process_next(struct at91mci_host *host) |
65dbf343 AV |
620 | { |
621 | if (!(host->flags & FL_SENT_COMMAND)) { | |
622 | host->flags |= FL_SENT_COMMAND; | |
ed99c541 | 623 | at91_mci_send_command(host, host->request->cmd); |
65dbf343 AV |
624 | } |
625 | else if ((!(host->flags & FL_SENT_STOP)) && host->request->stop) { | |
626 | host->flags |= FL_SENT_STOP; | |
ed99c541 | 627 | at91_mci_send_command(host, host->request->stop); |
e181dce8 MP |
628 | } else { |
629 | del_timer(&host->timer); | |
c5a89c6c MP |
630 | /* the at91rm9200 mci controller hangs after some transfers, |
631 | * and the workaround is to reset it after each transfer. | |
632 | */ | |
633 | if (cpu_is_at91rm9200()) | |
634 | at91_reset_host(host); | |
65dbf343 | 635 | mmc_request_done(host->mmc, host->request); |
e181dce8 | 636 | } |
65dbf343 AV |
637 | } |
638 | ||
639 | /* | |
640 | * Handle a command that has been completed | |
641 | */ | |
e8d04d3d | 642 | static void at91_mci_completed_command(struct at91mci_host *host) |
65dbf343 AV |
643 | { |
644 | struct mmc_command *cmd = host->cmd; | |
645 | unsigned int status; | |
646 | ||
e0b19b83 | 647 | at91_mci_write(host, AT91_MCI_IDR, 0xffffffff); |
65dbf343 | 648 | |
e0b19b83 AV |
649 | cmd->resp[0] = at91_mci_read(host, AT91_MCI_RSPR(0)); |
650 | cmd->resp[1] = at91_mci_read(host, AT91_MCI_RSPR(1)); | |
651 | cmd->resp[2] = at91_mci_read(host, AT91_MCI_RSPR(2)); | |
652 | cmd->resp[3] = at91_mci_read(host, AT91_MCI_RSPR(3)); | |
65dbf343 AV |
653 | |
654 | if (host->buffer) { | |
655 | dma_free_coherent(NULL, host->total_length, host->buffer, host->physical_address); | |
656 | host->buffer = NULL; | |
657 | } | |
658 | ||
e0b19b83 | 659 | status = at91_mci_read(host, AT91_MCI_SR); |
65dbf343 | 660 | |
b44fb7a0 | 661 | pr_debug("Status = %08X [%08X %08X %08X %08X]\n", |
65dbf343 AV |
662 | status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); |
663 | ||
9e3866b5 | 664 | if (status & AT91_MCI_ERRORS) { |
b6cedb38 | 665 | if ((status & AT91_MCI_RCRCE) && !(mmc_resp_type(cmd) & MMC_RSP_CRC)) { |
17b0429d | 666 | cmd->error = 0; |
65dbf343 AV |
667 | } |
668 | else { | |
669 | if (status & (AT91_MCI_RTOE | AT91_MCI_DTOE)) | |
17b0429d | 670 | cmd->error = -ETIMEDOUT; |
65dbf343 | 671 | else if (status & (AT91_MCI_RCRCE | AT91_MCI_DCRCE)) |
17b0429d | 672 | cmd->error = -EILSEQ; |
65dbf343 | 673 | else |
17b0429d | 674 | cmd->error = -EIO; |
65dbf343 | 675 | |
b44fb7a0 | 676 | pr_debug("Error detected and set to %d (cmd = %d, retries = %d)\n", |
65dbf343 AV |
677 | cmd->error, cmd->opcode, cmd->retries); |
678 | } | |
679 | } | |
680 | else | |
17b0429d | 681 | cmd->error = 0; |
65dbf343 | 682 | |
e8d04d3d | 683 | at91_mci_process_next(host); |
65dbf343 AV |
684 | } |
685 | ||
686 | /* | |
687 | * Handle an MMC request | |
688 | */ | |
689 | static void at91_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
690 | { | |
691 | struct at91mci_host *host = mmc_priv(mmc); | |
692 | host->request = mrq; | |
693 | host->flags = 0; | |
694 | ||
e181dce8 MP |
695 | mod_timer(&host->timer, jiffies + HZ); |
696 | ||
e8d04d3d | 697 | at91_mci_process_next(host); |
65dbf343 AV |
698 | } |
699 | ||
700 | /* | |
701 | * Set the IOS | |
702 | */ | |
703 | static void at91_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
704 | { | |
705 | int clkdiv; | |
706 | struct at91mci_host *host = mmc_priv(mmc); | |
3dd3b039 | 707 | unsigned long at91_master_clock = clk_get_rate(host->mci_clk); |
65dbf343 | 708 | |
b44fb7a0 | 709 | host->bus_mode = ios->bus_mode; |
65dbf343 AV |
710 | |
711 | if (ios->clock == 0) { | |
712 | /* Disable the MCI controller */ | |
e0b19b83 | 713 | at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS); |
65dbf343 AV |
714 | clkdiv = 0; |
715 | } | |
716 | else { | |
717 | /* Enable the MCI controller */ | |
e0b19b83 | 718 | at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN); |
65dbf343 AV |
719 | |
720 | if ((at91_master_clock % (ios->clock * 2)) == 0) | |
721 | clkdiv = ((at91_master_clock / ios->clock) / 2) - 1; | |
722 | else | |
723 | clkdiv = (at91_master_clock / ios->clock) / 2; | |
724 | ||
b44fb7a0 | 725 | pr_debug("clkdiv = %d. mcck = %ld\n", clkdiv, |
65dbf343 AV |
726 | at91_master_clock / (2 * (clkdiv + 1))); |
727 | } | |
728 | if (ios->bus_width == MMC_BUS_WIDTH_4 && host->board->wire4) { | |
b44fb7a0 | 729 | pr_debug("MMC: Setting controller bus width to 4\n"); |
e0b19b83 | 730 | at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) | AT91_MCI_SDCBUS); |
65dbf343 AV |
731 | } |
732 | else { | |
b44fb7a0 | 733 | pr_debug("MMC: Setting controller bus width to 1\n"); |
e0b19b83 | 734 | at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS); |
65dbf343 AV |
735 | } |
736 | ||
737 | /* Set the clock divider */ | |
e0b19b83 | 738 | at91_mci_write(host, AT91_MCI_MR, (at91_mci_read(host, AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv); |
65dbf343 AV |
739 | |
740 | /* maybe switch power to the card */ | |
b44fb7a0 | 741 | if (host->board->vcc_pin) { |
65dbf343 AV |
742 | switch (ios->power_mode) { |
743 | case MMC_POWER_OFF: | |
6e996ee8 | 744 | gpio_set_value(host->board->vcc_pin, 0); |
65dbf343 AV |
745 | break; |
746 | case MMC_POWER_UP: | |
6e996ee8 | 747 | gpio_set_value(host->board->vcc_pin, 1); |
65dbf343 | 748 | break; |
e5c0ef90 MP |
749 | case MMC_POWER_ON: |
750 | break; | |
751 | default: | |
752 | WARN_ON(1); | |
65dbf343 AV |
753 | } |
754 | } | |
755 | } | |
756 | ||
757 | /* | |
758 | * Handle an interrupt | |
759 | */ | |
7d12e780 | 760 | static irqreturn_t at91_mci_irq(int irq, void *devid) |
65dbf343 AV |
761 | { |
762 | struct at91mci_host *host = devid; | |
763 | int completed = 0; | |
df05a303 | 764 | unsigned int int_status, int_mask; |
65dbf343 | 765 | |
e0b19b83 | 766 | int_status = at91_mci_read(host, AT91_MCI_SR); |
df05a303 | 767 | int_mask = at91_mci_read(host, AT91_MCI_IMR); |
37b758e8 | 768 | |
f3a8efa9 | 769 | pr_debug("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask, |
df05a303 | 770 | int_status & int_mask); |
37b758e8 | 771 | |
df05a303 AV |
772 | int_status = int_status & int_mask; |
773 | ||
774 | if (int_status & AT91_MCI_ERRORS) { | |
65dbf343 | 775 | completed = 1; |
37b758e8 | 776 | |
df05a303 AV |
777 | if (int_status & AT91_MCI_UNRE) |
778 | pr_debug("MMC: Underrun error\n"); | |
779 | if (int_status & AT91_MCI_OVRE) | |
780 | pr_debug("MMC: Overrun error\n"); | |
781 | if (int_status & AT91_MCI_DTOE) | |
782 | pr_debug("MMC: Data timeout\n"); | |
783 | if (int_status & AT91_MCI_DCRCE) | |
784 | pr_debug("MMC: CRC error in data\n"); | |
785 | if (int_status & AT91_MCI_RTOE) | |
786 | pr_debug("MMC: Response timeout\n"); | |
787 | if (int_status & AT91_MCI_RENDE) | |
788 | pr_debug("MMC: Response end bit error\n"); | |
789 | if (int_status & AT91_MCI_RCRCE) | |
790 | pr_debug("MMC: Response CRC error\n"); | |
791 | if (int_status & AT91_MCI_RDIRE) | |
792 | pr_debug("MMC: Response direction error\n"); | |
793 | if (int_status & AT91_MCI_RINDE) | |
794 | pr_debug("MMC: Response index error\n"); | |
795 | } else { | |
796 | /* Only continue processing if no errors */ | |
65dbf343 | 797 | |
65dbf343 | 798 | if (int_status & AT91_MCI_TXBUFE) { |
b44fb7a0 | 799 | pr_debug("TX buffer empty\n"); |
65dbf343 AV |
800 | at91_mci_handle_transmitted(host); |
801 | } | |
802 | ||
ed99c541 NF |
803 | if (int_status & AT91_MCI_ENDRX) { |
804 | pr_debug("ENDRX\n"); | |
805 | at91_mci_post_dma_read(host); | |
806 | } | |
807 | ||
65dbf343 | 808 | if (int_status & AT91_MCI_RXBUFF) { |
b44fb7a0 | 809 | pr_debug("RX buffer full\n"); |
ed99c541 NF |
810 | at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); |
811 | at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_RXBUFF | AT91_MCI_ENDRX); | |
812 | completed = 1; | |
65dbf343 AV |
813 | } |
814 | ||
df05a303 | 815 | if (int_status & AT91_MCI_ENDTX) |
b44fb7a0 | 816 | pr_debug("Transmit has ended\n"); |
65dbf343 | 817 | |
65dbf343 | 818 | if (int_status & AT91_MCI_NOTBUSY) { |
b44fb7a0 | 819 | pr_debug("Card is ready\n"); |
ed99c541 | 820 | completed = 1; |
65dbf343 AV |
821 | } |
822 | ||
df05a303 | 823 | if (int_status & AT91_MCI_DTIP) |
b44fb7a0 | 824 | pr_debug("Data transfer in progress\n"); |
65dbf343 | 825 | |
ed99c541 | 826 | if (int_status & AT91_MCI_BLKE) { |
b44fb7a0 | 827 | pr_debug("Block transfer has ended\n"); |
ed99c541 NF |
828 | completed = 1; |
829 | } | |
65dbf343 | 830 | |
df05a303 | 831 | if (int_status & AT91_MCI_TXRDY) |
b44fb7a0 | 832 | pr_debug("Ready to transmit\n"); |
65dbf343 | 833 | |
df05a303 | 834 | if (int_status & AT91_MCI_RXRDY) |
b44fb7a0 | 835 | pr_debug("Ready to receive\n"); |
65dbf343 AV |
836 | |
837 | if (int_status & AT91_MCI_CMDRDY) { | |
b44fb7a0 | 838 | pr_debug("Command ready\n"); |
ed99c541 | 839 | completed = at91_mci_handle_cmdrdy(host); |
65dbf343 AV |
840 | } |
841 | } | |
65dbf343 AV |
842 | |
843 | if (completed) { | |
b44fb7a0 | 844 | pr_debug("Completed command\n"); |
e0b19b83 | 845 | at91_mci_write(host, AT91_MCI_IDR, 0xffffffff); |
e8d04d3d | 846 | at91_mci_completed_command(host); |
df05a303 AV |
847 | } else |
848 | at91_mci_write(host, AT91_MCI_IDR, int_status); | |
65dbf343 AV |
849 | |
850 | return IRQ_HANDLED; | |
851 | } | |
852 | ||
7d12e780 | 853 | static irqreturn_t at91_mmc_det_irq(int irq, void *_host) |
65dbf343 AV |
854 | { |
855 | struct at91mci_host *host = _host; | |
6e996ee8 | 856 | int present = !gpio_get_value(irq_to_gpio(irq)); |
65dbf343 AV |
857 | |
858 | /* | |
859 | * we expect this irq on both insert and remove, | |
860 | * and use a short delay to debounce. | |
861 | */ | |
862 | if (present != host->present) { | |
863 | host->present = present; | |
b44fb7a0 | 864 | pr_debug("%s: card %s\n", mmc_hostname(host->mmc), |
65dbf343 AV |
865 | present ? "insert" : "remove"); |
866 | if (!present) { | |
b44fb7a0 | 867 | pr_debug("****** Resetting SD-card bus width ******\n"); |
99eeb8df | 868 | at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS); |
65dbf343 AV |
869 | } |
870 | mmc_detect_change(host->mmc, msecs_to_jiffies(100)); | |
871 | } | |
872 | return IRQ_HANDLED; | |
873 | } | |
874 | ||
a26b498c | 875 | static int at91_mci_get_ro(struct mmc_host *mmc) |
65dbf343 | 876 | { |
65dbf343 AV |
877 | struct at91mci_host *host = mmc_priv(mmc); |
878 | ||
08f80bb5 AV |
879 | if (host->board->wp_pin) |
880 | return !!gpio_get_value(host->board->wp_pin); | |
881 | /* | |
882 | * Board doesn't support read only detection; let the mmc core | |
883 | * decide what to do. | |
884 | */ | |
885 | return -ENOSYS; | |
65dbf343 AV |
886 | } |
887 | ||
ab7aefd0 | 888 | static const struct mmc_host_ops at91_mci_ops = { |
65dbf343 AV |
889 | .request = at91_mci_request, |
890 | .set_ios = at91_mci_set_ios, | |
891 | .get_ro = at91_mci_get_ro, | |
892 | }; | |
893 | ||
894 | /* | |
895 | * Probe for the device | |
896 | */ | |
a26b498c | 897 | static int __init at91_mci_probe(struct platform_device *pdev) |
65dbf343 AV |
898 | { |
899 | struct mmc_host *mmc; | |
900 | struct at91mci_host *host; | |
17ea0595 | 901 | struct resource *res; |
65dbf343 AV |
902 | int ret; |
903 | ||
17ea0595 AV |
904 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
905 | if (!res) | |
906 | return -ENXIO; | |
907 | ||
908 | if (!request_mem_region(res->start, res->end - res->start + 1, DRIVER_NAME)) | |
909 | return -EBUSY; | |
910 | ||
65dbf343 AV |
911 | mmc = mmc_alloc_host(sizeof(struct at91mci_host), &pdev->dev); |
912 | if (!mmc) { | |
6e996ee8 DB |
913 | ret = -ENOMEM; |
914 | dev_dbg(&pdev->dev, "couldn't allocate mmc host\n"); | |
915 | goto fail6; | |
65dbf343 AV |
916 | } |
917 | ||
918 | mmc->ops = &at91_mci_ops; | |
919 | mmc->f_min = 375000; | |
920 | mmc->f_max = 25000000; | |
921 | mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; | |
922 | ||
fe4a3c7a | 923 | mmc->max_blk_size = 4095; |
55db890a | 924 | mmc->max_blk_count = mmc->max_req_size; |
fe4a3c7a | 925 | |
65dbf343 AV |
926 | host = mmc_priv(mmc); |
927 | host->mmc = mmc; | |
928 | host->buffer = NULL; | |
929 | host->bus_mode = 0; | |
930 | host->board = pdev->dev.platform_data; | |
931 | if (host->board->wire4) { | |
ed99c541 NF |
932 | if (cpu_is_at91sam9260() || cpu_is_at91sam9263()) |
933 | mmc->caps |= MMC_CAP_4_BIT_DATA; | |
934 | else | |
6e996ee8 | 935 | dev_warn(&pdev->dev, "4 wire bus mode not supported" |
ed99c541 | 936 | " - using 1 wire\n"); |
65dbf343 AV |
937 | } |
938 | ||
6e996ee8 DB |
939 | /* |
940 | * Reserve GPIOs ... board init code makes sure these pins are set | |
941 | * up as GPIOs with the right direction (input, except for vcc) | |
942 | */ | |
943 | if (host->board->det_pin) { | |
944 | ret = gpio_request(host->board->det_pin, "mmc_detect"); | |
945 | if (ret < 0) { | |
946 | dev_dbg(&pdev->dev, "couldn't claim card detect pin\n"); | |
947 | goto fail5; | |
948 | } | |
949 | } | |
950 | if (host->board->wp_pin) { | |
951 | ret = gpio_request(host->board->wp_pin, "mmc_wp"); | |
952 | if (ret < 0) { | |
953 | dev_dbg(&pdev->dev, "couldn't claim wp sense pin\n"); | |
954 | goto fail4; | |
955 | } | |
956 | } | |
957 | if (host->board->vcc_pin) { | |
958 | ret = gpio_request(host->board->vcc_pin, "mmc_vcc"); | |
959 | if (ret < 0) { | |
960 | dev_dbg(&pdev->dev, "couldn't claim vcc switch pin\n"); | |
961 | goto fail3; | |
962 | } | |
963 | } | |
964 | ||
65dbf343 AV |
965 | /* |
966 | * Get Clock | |
967 | */ | |
3dd3b039 AV |
968 | host->mci_clk = clk_get(&pdev->dev, "mci_clk"); |
969 | if (IS_ERR(host->mci_clk)) { | |
6e996ee8 DB |
970 | ret = -ENODEV; |
971 | dev_dbg(&pdev->dev, "no mci_clk?\n"); | |
972 | goto fail2; | |
65dbf343 | 973 | } |
65dbf343 | 974 | |
17ea0595 AV |
975 | /* |
976 | * Map I/O region | |
977 | */ | |
978 | host->baseaddr = ioremap(res->start, res->end - res->start + 1); | |
979 | if (!host->baseaddr) { | |
6e996ee8 DB |
980 | ret = -ENOMEM; |
981 | goto fail1; | |
17ea0595 | 982 | } |
e0b19b83 AV |
983 | |
984 | /* | |
985 | * Reset hardware | |
986 | */ | |
3dd3b039 | 987 | clk_enable(host->mci_clk); /* Enable the peripheral clock */ |
e0b19b83 AV |
988 | at91_mci_disable(host); |
989 | at91_mci_enable(host); | |
990 | ||
65dbf343 AV |
991 | /* |
992 | * Allocate the MCI interrupt | |
993 | */ | |
17ea0595 | 994 | host->irq = platform_get_irq(pdev, 0); |
6e996ee8 DB |
995 | ret = request_irq(host->irq, at91_mci_irq, IRQF_SHARED, |
996 | mmc_hostname(mmc), host); | |
65dbf343 | 997 | if (ret) { |
6e996ee8 DB |
998 | dev_dbg(&pdev->dev, "request MCI interrupt failed\n"); |
999 | goto fail0; | |
65dbf343 AV |
1000 | } |
1001 | ||
1002 | platform_set_drvdata(pdev, mmc); | |
1003 | ||
1004 | /* | |
1005 | * Add host to MMC layer | |
1006 | */ | |
63b66438 | 1007 | if (host->board->det_pin) { |
6e996ee8 | 1008 | host->present = !gpio_get_value(host->board->det_pin); |
63b66438 | 1009 | } |
65dbf343 AV |
1010 | else |
1011 | host->present = -1; | |
1012 | ||
1013 | mmc_add_host(mmc); | |
1014 | ||
e181dce8 MP |
1015 | setup_timer(&host->timer, at91_timeout_timer, (unsigned long)host); |
1016 | ||
65dbf343 AV |
1017 | /* |
1018 | * monitor card insertion/removal if we can | |
1019 | */ | |
1020 | if (host->board->det_pin) { | |
6e996ee8 DB |
1021 | ret = request_irq(gpio_to_irq(host->board->det_pin), |
1022 | at91_mmc_det_irq, 0, mmc_hostname(mmc), host); | |
65dbf343 | 1023 | if (ret) |
6e996ee8 DB |
1024 | dev_warn(&pdev->dev, "request MMC detect irq failed\n"); |
1025 | else | |
1026 | device_init_wakeup(&pdev->dev, 1); | |
65dbf343 AV |
1027 | } |
1028 | ||
f3a8efa9 | 1029 | pr_debug("Added MCI driver\n"); |
65dbf343 AV |
1030 | |
1031 | return 0; | |
6e996ee8 DB |
1032 | |
1033 | fail0: | |
1034 | clk_disable(host->mci_clk); | |
1035 | iounmap(host->baseaddr); | |
1036 | fail1: | |
1037 | clk_put(host->mci_clk); | |
1038 | fail2: | |
1039 | if (host->board->vcc_pin) | |
1040 | gpio_free(host->board->vcc_pin); | |
1041 | fail3: | |
1042 | if (host->board->wp_pin) | |
1043 | gpio_free(host->board->wp_pin); | |
1044 | fail4: | |
1045 | if (host->board->det_pin) | |
1046 | gpio_free(host->board->det_pin); | |
1047 | fail5: | |
1048 | mmc_free_host(mmc); | |
1049 | fail6: | |
1050 | release_mem_region(res->start, res->end - res->start + 1); | |
1051 | dev_err(&pdev->dev, "probe failed, err %d\n", ret); | |
1052 | return ret; | |
65dbf343 AV |
1053 | } |
1054 | ||
1055 | /* | |
1056 | * Remove a device | |
1057 | */ | |
a26b498c | 1058 | static int __exit at91_mci_remove(struct platform_device *pdev) |
65dbf343 AV |
1059 | { |
1060 | struct mmc_host *mmc = platform_get_drvdata(pdev); | |
1061 | struct at91mci_host *host; | |
17ea0595 | 1062 | struct resource *res; |
65dbf343 AV |
1063 | |
1064 | if (!mmc) | |
1065 | return -1; | |
1066 | ||
1067 | host = mmc_priv(mmc); | |
1068 | ||
e0cda54e | 1069 | if (host->board->det_pin) { |
6e996ee8 DB |
1070 | if (device_can_wakeup(&pdev->dev)) |
1071 | free_irq(gpio_to_irq(host->board->det_pin), host); | |
63b66438 | 1072 | device_init_wakeup(&pdev->dev, 0); |
6e996ee8 | 1073 | gpio_free(host->board->det_pin); |
65dbf343 AV |
1074 | } |
1075 | ||
e0b19b83 | 1076 | at91_mci_disable(host); |
e181dce8 | 1077 | del_timer_sync(&host->timer); |
17ea0595 AV |
1078 | mmc_remove_host(mmc); |
1079 | free_irq(host->irq, host); | |
65dbf343 | 1080 | |
3dd3b039 AV |
1081 | clk_disable(host->mci_clk); /* Disable the peripheral clock */ |
1082 | clk_put(host->mci_clk); | |
65dbf343 | 1083 | |
6e996ee8 DB |
1084 | if (host->board->vcc_pin) |
1085 | gpio_free(host->board->vcc_pin); | |
1086 | if (host->board->wp_pin) | |
1087 | gpio_free(host->board->wp_pin); | |
1088 | ||
17ea0595 AV |
1089 | iounmap(host->baseaddr); |
1090 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1091 | release_mem_region(res->start, res->end - res->start + 1); | |
65dbf343 | 1092 | |
17ea0595 AV |
1093 | mmc_free_host(mmc); |
1094 | platform_set_drvdata(pdev, NULL); | |
b44fb7a0 | 1095 | pr_debug("MCI Removed\n"); |
65dbf343 AV |
1096 | |
1097 | return 0; | |
1098 | } | |
1099 | ||
1100 | #ifdef CONFIG_PM | |
1101 | static int at91_mci_suspend(struct platform_device *pdev, pm_message_t state) | |
1102 | { | |
1103 | struct mmc_host *mmc = platform_get_drvdata(pdev); | |
63b66438 | 1104 | struct at91mci_host *host = mmc_priv(mmc); |
65dbf343 AV |
1105 | int ret = 0; |
1106 | ||
e0cda54e | 1107 | if (host->board->det_pin && device_may_wakeup(&pdev->dev)) |
63b66438 MP |
1108 | enable_irq_wake(host->board->det_pin); |
1109 | ||
65dbf343 AV |
1110 | if (mmc) |
1111 | ret = mmc_suspend_host(mmc, state); | |
1112 | ||
1113 | return ret; | |
1114 | } | |
1115 | ||
1116 | static int at91_mci_resume(struct platform_device *pdev) | |
1117 | { | |
1118 | struct mmc_host *mmc = platform_get_drvdata(pdev); | |
63b66438 | 1119 | struct at91mci_host *host = mmc_priv(mmc); |
65dbf343 AV |
1120 | int ret = 0; |
1121 | ||
e0cda54e | 1122 | if (host->board->det_pin && device_may_wakeup(&pdev->dev)) |
63b66438 MP |
1123 | disable_irq_wake(host->board->det_pin); |
1124 | ||
65dbf343 AV |
1125 | if (mmc) |
1126 | ret = mmc_resume_host(mmc); | |
1127 | ||
1128 | return ret; | |
1129 | } | |
1130 | #else | |
1131 | #define at91_mci_suspend NULL | |
1132 | #define at91_mci_resume NULL | |
1133 | #endif | |
1134 | ||
1135 | static struct platform_driver at91_mci_driver = { | |
a26b498c | 1136 | .remove = __exit_p(at91_mci_remove), |
65dbf343 AV |
1137 | .suspend = at91_mci_suspend, |
1138 | .resume = at91_mci_resume, | |
1139 | .driver = { | |
1140 | .name = DRIVER_NAME, | |
1141 | .owner = THIS_MODULE, | |
1142 | }, | |
1143 | }; | |
1144 | ||
1145 | static int __init at91_mci_init(void) | |
1146 | { | |
a26b498c | 1147 | return platform_driver_probe(&at91_mci_driver, at91_mci_probe); |
65dbf343 AV |
1148 | } |
1149 | ||
1150 | static void __exit at91_mci_exit(void) | |
1151 | { | |
1152 | platform_driver_unregister(&at91_mci_driver); | |
1153 | } | |
1154 | ||
1155 | module_init(at91_mci_init); | |
1156 | module_exit(at91_mci_exit); | |
1157 | ||
1158 | MODULE_DESCRIPTION("AT91 Multimedia Card Interface driver"); | |
1159 | MODULE_AUTHOR("Nick Randell"); | |
1160 | MODULE_LICENSE("GPL"); | |
bc65c724 | 1161 | MODULE_ALIAS("platform:at91_mci"); |