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65dbf343 | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/at91_mci.c - ATMEL AT91 MCI Driver |
65dbf343 AV |
3 | * |
4 | * Copyright (C) 2005 Cougar Creek Computing Devices Ltd, All Rights Reserved | |
5 | * | |
6 | * Copyright (C) 2006 Malcolm Noyes | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | /* | |
99eeb8df | 14 | This is the AT91 MCI driver that has been tested with both MMC cards |
65dbf343 AV |
15 | and SD-cards. Boards that support write protect are now supported. |
16 | The CCAT91SBC001 board does not support SD cards. | |
17 | ||
18 | The three entry points are at91_mci_request, at91_mci_set_ios | |
19 | and at91_mci_get_ro. | |
20 | ||
21 | SET IOS | |
22 | This configures the device to put it into the correct mode and clock speed | |
23 | required. | |
24 | ||
25 | MCI REQUEST | |
26 | MCI request processes the commands sent in the mmc_request structure. This | |
27 | can consist of a processing command and a stop command in the case of | |
28 | multiple block transfers. | |
29 | ||
30 | There are three main types of request, commands, reads and writes. | |
31 | ||
32 | Commands are straight forward. The command is submitted to the controller and | |
33 | the request function returns. When the controller generates an interrupt to indicate | |
34 | the command is finished, the response to the command are read and the mmc_request_done | |
35 | function called to end the request. | |
36 | ||
37 | Reads and writes work in a similar manner to normal commands but involve the PDC (DMA) | |
38 | controller to manage the transfers. | |
39 | ||
40 | A read is done from the controller directly to the scatterlist passed in from the request. | |
99eeb8df AV |
41 | Due to a bug in the AT91RM9200 controller, when a read is completed, all the words are byte |
42 | swapped in the scatterlist buffers. AT91SAM926x are not affected by this bug. | |
65dbf343 AV |
43 | |
44 | The sequence of read interrupts is: ENDRX, RXBUFF, CMDRDY | |
45 | ||
46 | A write is slightly different in that the bytes to write are read from the scatterlist | |
47 | into a dma memory buffer (this is in case the source buffer should be read only). The | |
48 | entire write buffer is then done from this single dma memory buffer. | |
49 | ||
50 | The sequence of write interrupts is: ENDTX, TXBUFE, NOTBUSY, CMDRDY | |
51 | ||
52 | GET RO | |
53 | Gets the status of the write protect pin, if available. | |
54 | */ | |
55 | ||
65dbf343 AV |
56 | #include <linux/module.h> |
57 | #include <linux/moduleparam.h> | |
58 | #include <linux/init.h> | |
59 | #include <linux/ioport.h> | |
60 | #include <linux/platform_device.h> | |
61 | #include <linux/interrupt.h> | |
62 | #include <linux/blkdev.h> | |
63 | #include <linux/delay.h> | |
64 | #include <linux/err.h> | |
65 | #include <linux/dma-mapping.h> | |
66 | #include <linux/clk.h> | |
93a3ddc2 | 67 | #include <linux/atmel_pdc.h> |
5a0e3ad6 | 68 | #include <linux/gfp.h> |
65dbf343 AV |
69 | |
70 | #include <linux/mmc/host.h> | |
65dbf343 AV |
71 | |
72 | #include <asm/io.h> | |
73 | #include <asm/irq.h> | |
6e996ee8 DB |
74 | #include <asm/gpio.h> |
75 | ||
a09e64fb RK |
76 | #include <mach/board.h> |
77 | #include <mach/cpu.h> | |
78 | #include <mach/at91_mci.h> | |
65dbf343 AV |
79 | |
80 | #define DRIVER_NAME "at91_mci" | |
81 | ||
5b27a1a5 NF |
82 | static inline int at91mci_is_mci1rev2xx(void) |
83 | { | |
84 | return ( cpu_is_at91sam9260() | |
85 | || cpu_is_at91sam9263() | |
86 | || cpu_is_at91cap9() | |
87 | || cpu_is_at91sam9rl() | |
88 | || cpu_is_at91sam9g10() | |
89 | || cpu_is_at91sam9g20() | |
90 | ); | |
91 | } | |
92 | ||
df05a303 AV |
93 | #define FL_SENT_COMMAND (1 << 0) |
94 | #define FL_SENT_STOP (1 << 1) | |
65dbf343 | 95 | |
df05a303 AV |
96 | #define AT91_MCI_ERRORS (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE \ |
97 | | AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE \ | |
37b758e8 | 98 | | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE) |
65dbf343 | 99 | |
e0b19b83 AV |
100 | #define at91_mci_read(host, reg) __raw_readl((host)->baseaddr + (reg)) |
101 | #define at91_mci_write(host, reg, val) __raw_writel((val), (host)->baseaddr + (reg)) | |
65dbf343 | 102 | |
3780d906 WM |
103 | #define MCI_BLKSIZE 512 |
104 | #define MCI_MAXBLKSIZE 4095 | |
105 | #define MCI_BLKATONCE 256 | |
106 | #define MCI_BUFSIZE (MCI_BLKSIZE * MCI_BLKATONCE) | |
65dbf343 AV |
107 | |
108 | /* | |
109 | * Low level type for this driver | |
110 | */ | |
111 | struct at91mci_host | |
112 | { | |
113 | struct mmc_host *mmc; | |
114 | struct mmc_command *cmd; | |
115 | struct mmc_request *request; | |
116 | ||
e0b19b83 | 117 | void __iomem *baseaddr; |
17ea0595 | 118 | int irq; |
e0b19b83 | 119 | |
65dbf343 AV |
120 | struct at91_mmc_data *board; |
121 | int present; | |
122 | ||
3dd3b039 AV |
123 | struct clk *mci_clk; |
124 | ||
65dbf343 AV |
125 | /* |
126 | * Flag indicating when the command has been sent. This is used to | |
127 | * work out whether or not to send the stop | |
128 | */ | |
129 | unsigned int flags; | |
130 | /* flag for current bus settings */ | |
131 | u32 bus_mode; | |
132 | ||
133 | /* DMA buffer used for transmitting */ | |
134 | unsigned int* buffer; | |
135 | dma_addr_t physical_address; | |
136 | unsigned int total_length; | |
137 | ||
138 | /* Latest in the scatterlist that has been enabled for transfer, but not freed */ | |
139 | int in_use_index; | |
140 | ||
141 | /* Latest in the scatterlist that has been enabled for transfer */ | |
142 | int transfer_index; | |
e181dce8 MP |
143 | |
144 | /* Timer for timeouts */ | |
145 | struct timer_list timer; | |
65dbf343 AV |
146 | }; |
147 | ||
c5a89c6c MP |
148 | /* |
149 | * Reset the controller and restore most of the state | |
150 | */ | |
151 | static void at91_reset_host(struct at91mci_host *host) | |
152 | { | |
153 | unsigned long flags; | |
154 | u32 mr; | |
155 | u32 sdcr; | |
156 | u32 dtor; | |
157 | u32 imr; | |
158 | ||
159 | local_irq_save(flags); | |
160 | imr = at91_mci_read(host, AT91_MCI_IMR); | |
161 | ||
162 | at91_mci_write(host, AT91_MCI_IDR, 0xffffffff); | |
163 | ||
164 | /* save current state */ | |
165 | mr = at91_mci_read(host, AT91_MCI_MR) & 0x7fff; | |
166 | sdcr = at91_mci_read(host, AT91_MCI_SDCR); | |
167 | dtor = at91_mci_read(host, AT91_MCI_DTOR); | |
168 | ||
169 | /* reset the controller */ | |
170 | at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST); | |
171 | ||
172 | /* restore state */ | |
173 | at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN); | |
174 | at91_mci_write(host, AT91_MCI_MR, mr); | |
175 | at91_mci_write(host, AT91_MCI_SDCR, sdcr); | |
176 | at91_mci_write(host, AT91_MCI_DTOR, dtor); | |
177 | at91_mci_write(host, AT91_MCI_IER, imr); | |
178 | ||
179 | /* make sure sdio interrupts will fire */ | |
180 | at91_mci_read(host, AT91_MCI_SR); | |
181 | ||
182 | local_irq_restore(flags); | |
183 | } | |
184 | ||
e181dce8 MP |
185 | static void at91_timeout_timer(unsigned long data) |
186 | { | |
187 | struct at91mci_host *host; | |
188 | ||
189 | host = (struct at91mci_host *)data; | |
190 | ||
191 | if (host->request) { | |
192 | dev_err(host->mmc->parent, "Timeout waiting end of packet\n"); | |
193 | ||
194 | if (host->cmd && host->cmd->data) { | |
195 | host->cmd->data->error = -ETIMEDOUT; | |
196 | } else { | |
197 | if (host->cmd) | |
198 | host->cmd->error = -ETIMEDOUT; | |
199 | else | |
200 | host->request->cmd->error = -ETIMEDOUT; | |
201 | } | |
202 | ||
c5a89c6c | 203 | at91_reset_host(host); |
e181dce8 MP |
204 | mmc_request_done(host->mmc, host->request); |
205 | } | |
206 | } | |
207 | ||
65dbf343 AV |
208 | /* |
209 | * Copy from sg to a dma block - used for transfers | |
210 | */ | |
e8d04d3d | 211 | static inline void at91_mci_sg_to_dma(struct at91mci_host *host, struct mmc_data *data) |
65dbf343 AV |
212 | { |
213 | unsigned int len, i, size; | |
214 | unsigned *dmabuf = host->buffer; | |
215 | ||
5385edc5 | 216 | size = data->blksz * data->blocks; |
65dbf343 AV |
217 | len = data->sg_len; |
218 | ||
5b27a1a5 NF |
219 | /* MCI1 rev2xx Data Write Operation and number of bytes erratum */ |
220 | if (at91mci_is_mci1rev2xx()) | |
5385edc5 VS |
221 | if (host->total_length == 12) |
222 | memset(dmabuf, 0, 12); | |
223 | ||
65dbf343 AV |
224 | /* |
225 | * Just loop through all entries. Size might not | |
226 | * be the entire list though so make sure that | |
227 | * we do not transfer too much. | |
228 | */ | |
229 | for (i = 0; i < len; i++) { | |
230 | struct scatterlist *sg; | |
231 | int amount; | |
65dbf343 AV |
232 | unsigned int *sgbuffer; |
233 | ||
234 | sg = &data->sg[i]; | |
235 | ||
45711f1a | 236 | sgbuffer = kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset; |
65dbf343 AV |
237 | amount = min(size, sg->length); |
238 | size -= amount; | |
65dbf343 | 239 | |
99eeb8df AV |
240 | if (cpu_is_at91rm9200()) { /* AT91RM9200 errata */ |
241 | int index; | |
242 | ||
243 | for (index = 0; index < (amount / 4); index++) | |
244 | *dmabuf++ = swab32(sgbuffer[index]); | |
5385edc5 | 245 | } else { |
0b3520f2 WM |
246 | char *tmpv = (char *)dmabuf; |
247 | memcpy(tmpv, sgbuffer, amount); | |
248 | tmpv += amount; | |
249 | dmabuf = (unsigned *)tmpv; | |
5385edc5 | 250 | } |
65dbf343 | 251 | |
752993ef | 252 | kunmap_atomic(sgbuffer, KM_BIO_SRC_IRQ); |
65dbf343 AV |
253 | |
254 | if (size == 0) | |
255 | break; | |
256 | } | |
257 | ||
258 | /* | |
259 | * Check that we didn't get a request to transfer | |
260 | * more data than can fit into the SG list. | |
261 | */ | |
262 | BUG_ON(size != 0); | |
263 | } | |
264 | ||
65dbf343 AV |
265 | /* |
266 | * Handle after a dma read | |
267 | */ | |
e8d04d3d | 268 | static void at91_mci_post_dma_read(struct at91mci_host *host) |
65dbf343 AV |
269 | { |
270 | struct mmc_command *cmd; | |
271 | struct mmc_data *data; | |
86ee26f5 WM |
272 | unsigned int len, i, size; |
273 | unsigned *dmabuf = host->buffer; | |
65dbf343 | 274 | |
b44fb7a0 | 275 | pr_debug("post dma read\n"); |
65dbf343 AV |
276 | |
277 | cmd = host->cmd; | |
278 | if (!cmd) { | |
b44fb7a0 | 279 | pr_debug("no command\n"); |
65dbf343 AV |
280 | return; |
281 | } | |
282 | ||
283 | data = cmd->data; | |
284 | if (!data) { | |
b44fb7a0 | 285 | pr_debug("no data\n"); |
65dbf343 AV |
286 | return; |
287 | } | |
288 | ||
86ee26f5 WM |
289 | size = data->blksz * data->blocks; |
290 | len = data->sg_len; | |
65dbf343 | 291 | |
86ee26f5 WM |
292 | at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_ENDRX); |
293 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_RXBUFF); | |
65dbf343 | 294 | |
86ee26f5 WM |
295 | for (i = 0; i < len; i++) { |
296 | struct scatterlist *sg; | |
297 | int amount; | |
298 | unsigned int *sgbuffer; | |
65dbf343 | 299 | |
86ee26f5 | 300 | sg = &data->sg[i]; |
65dbf343 | 301 | |
86ee26f5 WM |
302 | sgbuffer = kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset; |
303 | amount = min(size, sg->length); | |
304 | size -= amount; | |
65dbf343 | 305 | |
99eeb8df AV |
306 | if (cpu_is_at91rm9200()) { /* AT91RM9200 errata */ |
307 | int index; | |
86ee26f5 WM |
308 | for (index = 0; index < (amount / 4); index++) |
309 | sgbuffer[index] = swab32(*dmabuf++); | |
310 | } else { | |
311 | char *tmpv = (char *)dmabuf; | |
312 | memcpy(sgbuffer, tmpv, amount); | |
313 | tmpv += amount; | |
314 | dmabuf = (unsigned *)tmpv; | |
65dbf343 | 315 | } |
99eeb8df | 316 | |
bdef2fe8 | 317 | flush_kernel_dcache_page(sg_page(sg)); |
752993ef | 318 | kunmap_atomic(sgbuffer, KM_BIO_SRC_IRQ); |
86ee26f5 WM |
319 | data->bytes_xfered += amount; |
320 | if (size == 0) | |
321 | break; | |
65dbf343 AV |
322 | } |
323 | ||
b44fb7a0 | 324 | pr_debug("post dma read done\n"); |
65dbf343 AV |
325 | } |
326 | ||
327 | /* | |
328 | * Handle transmitted data | |
329 | */ | |
330 | static void at91_mci_handle_transmitted(struct at91mci_host *host) | |
331 | { | |
332 | struct mmc_command *cmd; | |
333 | struct mmc_data *data; | |
334 | ||
b44fb7a0 | 335 | pr_debug("Handling the transmit\n"); |
65dbf343 AV |
336 | |
337 | /* Disable the transfer */ | |
93a3ddc2 | 338 | at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); |
65dbf343 AV |
339 | |
340 | /* Now wait for cmd ready */ | |
e0b19b83 | 341 | at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_TXBUFE); |
65dbf343 AV |
342 | |
343 | cmd = host->cmd; | |
344 | if (!cmd) return; | |
345 | ||
346 | data = cmd->data; | |
347 | if (!data) return; | |
348 | ||
be0192aa | 349 | if (cmd->data->blocks > 1) { |
ed99c541 NF |
350 | pr_debug("multiple write : wait for BLKE...\n"); |
351 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_BLKE); | |
352 | } else | |
353 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY); | |
4ac24a87 NF |
354 | } |
355 | ||
356 | /* | |
357 | * Update bytes tranfered count during a write operation | |
358 | */ | |
359 | static void at91_mci_update_bytes_xfered(struct at91mci_host *host) | |
360 | { | |
361 | struct mmc_data *data; | |
ed99c541 | 362 | |
4ac24a87 NF |
363 | /* always deal with the effective request (and not the current cmd) */ |
364 | ||
365 | if (host->request->cmd && host->request->cmd->error != 0) | |
366 | return; | |
367 | ||
368 | if (host->request->data) { | |
369 | data = host->request->data; | |
370 | if (data->flags & MMC_DATA_WRITE) { | |
371 | /* card is in IDLE mode now */ | |
372 | pr_debug("-> bytes_xfered %d, total_length = %d\n", | |
373 | data->bytes_xfered, host->total_length); | |
5385edc5 | 374 | data->bytes_xfered = data->blksz * data->blocks; |
4ac24a87 NF |
375 | } |
376 | } | |
65dbf343 AV |
377 | } |
378 | ||
4ac24a87 | 379 | |
ed99c541 NF |
380 | /*Handle after command sent ready*/ |
381 | static int at91_mci_handle_cmdrdy(struct at91mci_host *host) | |
382 | { | |
383 | if (!host->cmd) | |
384 | return 1; | |
385 | else if (!host->cmd->data) { | |
386 | if (host->flags & FL_SENT_STOP) { | |
387 | /*After multi block write, we must wait for NOTBUSY*/ | |
388 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY); | |
389 | } else return 1; | |
390 | } else if (host->cmd->data->flags & MMC_DATA_WRITE) { | |
391 | /*After sendding multi-block-write command, start DMA transfer*/ | |
4ac24a87 | 392 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_TXBUFE | AT91_MCI_BLKE); |
ed99c541 NF |
393 | at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); |
394 | } | |
395 | ||
396 | /* command not completed, have to wait */ | |
397 | return 0; | |
398 | } | |
399 | ||
400 | ||
65dbf343 AV |
401 | /* |
402 | * Enable the controller | |
403 | */ | |
e0b19b83 | 404 | static void at91_mci_enable(struct at91mci_host *host) |
65dbf343 | 405 | { |
ed99c541 NF |
406 | unsigned int mr; |
407 | ||
e0b19b83 | 408 | at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN); |
f3a8efa9 | 409 | at91_mci_write(host, AT91_MCI_IDR, 0xffffffff); |
e0b19b83 | 410 | at91_mci_write(host, AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC); |
ed99c541 NF |
411 | mr = AT91_MCI_PDCMODE | 0x34a; |
412 | ||
5b27a1a5 | 413 | if (at91mci_is_mci1rev2xx()) |
ed99c541 NF |
414 | mr |= AT91_MCI_RDPROOF | AT91_MCI_WRPROOF; |
415 | ||
416 | at91_mci_write(host, AT91_MCI_MR, mr); | |
99eeb8df AV |
417 | |
418 | /* use Slot A or B (only one at same time) */ | |
419 | at91_mci_write(host, AT91_MCI_SDCR, host->board->slot_b); | |
65dbf343 AV |
420 | } |
421 | ||
422 | /* | |
423 | * Disable the controller | |
424 | */ | |
e0b19b83 | 425 | static void at91_mci_disable(struct at91mci_host *host) |
65dbf343 | 426 | { |
e0b19b83 | 427 | at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST); |
65dbf343 AV |
428 | } |
429 | ||
430 | /* | |
431 | * Send a command | |
65dbf343 | 432 | */ |
ed99c541 | 433 | static void at91_mci_send_command(struct at91mci_host *host, struct mmc_command *cmd) |
65dbf343 AV |
434 | { |
435 | unsigned int cmdr, mr; | |
436 | unsigned int block_length; | |
437 | struct mmc_data *data = cmd->data; | |
438 | ||
439 | unsigned int blocks; | |
440 | unsigned int ier = 0; | |
441 | ||
442 | host->cmd = cmd; | |
443 | ||
ed99c541 | 444 | /* Needed for leaving busy state before CMD1 */ |
e0b19b83 | 445 | if ((at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->opcode == 1)) { |
b44fb7a0 | 446 | pr_debug("Clearing timeout\n"); |
e0b19b83 AV |
447 | at91_mci_write(host, AT91_MCI_ARGR, 0); |
448 | at91_mci_write(host, AT91_MCI_CMDR, AT91_MCI_OPDCMD); | |
449 | while (!(at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_CMDRDY)) { | |
65dbf343 | 450 | /* spin */ |
e0b19b83 | 451 | pr_debug("Clearing: SR = %08X\n", at91_mci_read(host, AT91_MCI_SR)); |
65dbf343 AV |
452 | } |
453 | } | |
ed99c541 | 454 | |
65dbf343 AV |
455 | cmdr = cmd->opcode; |
456 | ||
457 | if (mmc_resp_type(cmd) == MMC_RSP_NONE) | |
458 | cmdr |= AT91_MCI_RSPTYP_NONE; | |
459 | else { | |
460 | /* if a response is expected then allow maximum response latancy */ | |
461 | cmdr |= AT91_MCI_MAXLAT; | |
462 | /* set 136 bit response for R2, 48 bit response otherwise */ | |
463 | if (mmc_resp_type(cmd) == MMC_RSP_R2) | |
464 | cmdr |= AT91_MCI_RSPTYP_136; | |
465 | else | |
466 | cmdr |= AT91_MCI_RSPTYP_48; | |
467 | } | |
468 | ||
469 | if (data) { | |
1d4de9ed | 470 | |
9da3cbaf VS |
471 | if (cpu_is_at91rm9200() || cpu_is_at91sam9261()) { |
472 | if (data->blksz & 0x3) { | |
473 | pr_debug("Unsupported block size\n"); | |
474 | cmd->error = -EINVAL; | |
475 | mmc_request_done(host->mmc, host->request); | |
476 | return; | |
477 | } | |
478 | if (data->flags & MMC_DATA_STREAM) { | |
479 | pr_debug("Stream commands not supported\n"); | |
480 | cmd->error = -EINVAL; | |
481 | mmc_request_done(host->mmc, host->request); | |
482 | return; | |
483 | } | |
1d4de9ed MP |
484 | } |
485 | ||
a3fd4a1b | 486 | block_length = data->blksz; |
65dbf343 AV |
487 | blocks = data->blocks; |
488 | ||
489 | /* always set data start - also set direction flag for read */ | |
490 | if (data->flags & MMC_DATA_READ) | |
491 | cmdr |= (AT91_MCI_TRDIR | AT91_MCI_TRCMD_START); | |
492 | else if (data->flags & MMC_DATA_WRITE) | |
493 | cmdr |= AT91_MCI_TRCMD_START; | |
494 | ||
495 | if (data->flags & MMC_DATA_STREAM) | |
496 | cmdr |= AT91_MCI_TRTYP_STREAM; | |
be0192aa | 497 | if (data->blocks > 1) |
65dbf343 AV |
498 | cmdr |= AT91_MCI_TRTYP_MULTIPLE; |
499 | } | |
500 | else { | |
501 | block_length = 0; | |
502 | blocks = 0; | |
503 | } | |
504 | ||
b6cedb38 | 505 | if (host->flags & FL_SENT_STOP) |
65dbf343 AV |
506 | cmdr |= AT91_MCI_TRCMD_STOP; |
507 | ||
508 | if (host->bus_mode == MMC_BUSMODE_OPENDRAIN) | |
509 | cmdr |= AT91_MCI_OPDCMD; | |
510 | ||
511 | /* | |
512 | * Set the arguments and send the command | |
513 | */ | |
f3a8efa9 | 514 | pr_debug("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n", |
e0b19b83 | 515 | cmd->opcode, cmdr, cmd->arg, blocks, block_length, at91_mci_read(host, AT91_MCI_MR)); |
65dbf343 AV |
516 | |
517 | if (!data) { | |
93a3ddc2 AV |
518 | at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS | ATMEL_PDC_RXTDIS); |
519 | at91_mci_write(host, ATMEL_PDC_RPR, 0); | |
520 | at91_mci_write(host, ATMEL_PDC_RCR, 0); | |
521 | at91_mci_write(host, ATMEL_PDC_RNPR, 0); | |
522 | at91_mci_write(host, ATMEL_PDC_RNCR, 0); | |
523 | at91_mci_write(host, ATMEL_PDC_TPR, 0); | |
524 | at91_mci_write(host, ATMEL_PDC_TCR, 0); | |
525 | at91_mci_write(host, ATMEL_PDC_TNPR, 0); | |
526 | at91_mci_write(host, ATMEL_PDC_TNCR, 0); | |
ed99c541 NF |
527 | ier = AT91_MCI_CMDRDY; |
528 | } else { | |
529 | /* zero block length and PDC mode */ | |
12bd2575 | 530 | mr = at91_mci_read(host, AT91_MCI_MR) & 0x5fff; |
80f92546 MP |
531 | mr |= (data->blksz & 0x3) ? AT91_MCI_PDCFBYTE : 0; |
532 | mr |= (block_length << 16); | |
533 | mr |= AT91_MCI_PDCMODE; | |
534 | at91_mci_write(host, AT91_MCI_MR, mr); | |
e0b19b83 | 535 | |
9da3cbaf | 536 | if (!(cpu_is_at91rm9200() || cpu_is_at91sam9261())) |
c5a89c6c MP |
537 | at91_mci_write(host, AT91_MCI_BLKR, |
538 | AT91_MCI_BLKR_BCNT(blocks) | | |
539 | AT91_MCI_BLKR_BLKLEN(block_length)); | |
540 | ||
ed99c541 NF |
541 | /* |
542 | * Disable the PDC controller | |
543 | */ | |
544 | at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); | |
65dbf343 | 545 | |
ed99c541 NF |
546 | if (cmdr & AT91_MCI_TRCMD_START) { |
547 | data->bytes_xfered = 0; | |
548 | host->transfer_index = 0; | |
549 | host->in_use_index = 0; | |
550 | if (cmdr & AT91_MCI_TRDIR) { | |
551 | /* | |
552 | * Handle a read | |
553 | */ | |
ed99c541 NF |
554 | host->total_length = 0; |
555 | ||
86ee26f5 WM |
556 | at91_mci_write(host, ATMEL_PDC_RPR, host->physical_address); |
557 | at91_mci_write(host, ATMEL_PDC_RCR, (data->blksz & 0x3) ? | |
558 | (blocks * block_length) : (blocks * block_length) / 4); | |
559 | at91_mci_write(host, ATMEL_PDC_RNPR, 0); | |
560 | at91_mci_write(host, ATMEL_PDC_RNCR, 0); | |
561 | ||
ed99c541 NF |
562 | ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */; |
563 | } | |
564 | else { | |
565 | /* | |
566 | * Handle a write | |
567 | */ | |
568 | host->total_length = block_length * blocks; | |
5385edc5 | 569 | /* |
5b27a1a5 | 570 | * MCI1 rev2xx Data Write Operation and |
5385edc5 VS |
571 | * number of bytes erratum |
572 | */ | |
5b27a1a5 | 573 | if (at91mci_is_mci1rev2xx()) |
5385edc5 VS |
574 | if (host->total_length < 12) |
575 | host->total_length = 12; | |
e385ea63 | 576 | |
ed99c541 NF |
577 | at91_mci_sg_to_dma(host, data); |
578 | ||
579 | pr_debug("Transmitting %d bytes\n", host->total_length); | |
580 | ||
581 | at91_mci_write(host, ATMEL_PDC_TPR, host->physical_address); | |
80f92546 MP |
582 | at91_mci_write(host, ATMEL_PDC_TCR, (data->blksz & 0x3) ? |
583 | host->total_length : host->total_length / 4); | |
584 | ||
ed99c541 NF |
585 | ier = AT91_MCI_CMDRDY; |
586 | } | |
65dbf343 AV |
587 | } |
588 | } | |
589 | ||
590 | /* | |
591 | * Send the command and then enable the PDC - not the other way round as | |
592 | * the data sheet says | |
593 | */ | |
594 | ||
e0b19b83 AV |
595 | at91_mci_write(host, AT91_MCI_ARGR, cmd->arg); |
596 | at91_mci_write(host, AT91_MCI_CMDR, cmdr); | |
65dbf343 AV |
597 | |
598 | if (cmdr & AT91_MCI_TRCMD_START) { | |
599 | if (cmdr & AT91_MCI_TRDIR) | |
93a3ddc2 | 600 | at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN); |
65dbf343 | 601 | } |
65dbf343 | 602 | |
ed99c541 | 603 | /* Enable selected interrupts */ |
df05a303 | 604 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_ERRORS | ier); |
65dbf343 AV |
605 | } |
606 | ||
607 | /* | |
608 | * Process the next step in the request | |
609 | */ | |
e8d04d3d | 610 | static void at91_mci_process_next(struct at91mci_host *host) |
65dbf343 AV |
611 | { |
612 | if (!(host->flags & FL_SENT_COMMAND)) { | |
613 | host->flags |= FL_SENT_COMMAND; | |
ed99c541 | 614 | at91_mci_send_command(host, host->request->cmd); |
65dbf343 AV |
615 | } |
616 | else if ((!(host->flags & FL_SENT_STOP)) && host->request->stop) { | |
617 | host->flags |= FL_SENT_STOP; | |
ed99c541 | 618 | at91_mci_send_command(host, host->request->stop); |
e181dce8 MP |
619 | } else { |
620 | del_timer(&host->timer); | |
c5a89c6c MP |
621 | /* the at91rm9200 mci controller hangs after some transfers, |
622 | * and the workaround is to reset it after each transfer. | |
623 | */ | |
624 | if (cpu_is_at91rm9200()) | |
625 | at91_reset_host(host); | |
65dbf343 | 626 | mmc_request_done(host->mmc, host->request); |
e181dce8 | 627 | } |
65dbf343 AV |
628 | } |
629 | ||
630 | /* | |
631 | * Handle a command that has been completed | |
632 | */ | |
ba7deeed | 633 | static void at91_mci_completed_command(struct at91mci_host *host, unsigned int status) |
65dbf343 AV |
634 | { |
635 | struct mmc_command *cmd = host->cmd; | |
fa1fe010 | 636 | struct mmc_data *data = cmd->data; |
65dbf343 | 637 | |
7a6588ba | 638 | at91_mci_write(host, AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); |
65dbf343 | 639 | |
e0b19b83 AV |
640 | cmd->resp[0] = at91_mci_read(host, AT91_MCI_RSPR(0)); |
641 | cmd->resp[1] = at91_mci_read(host, AT91_MCI_RSPR(1)); | |
642 | cmd->resp[2] = at91_mci_read(host, AT91_MCI_RSPR(2)); | |
643 | cmd->resp[3] = at91_mci_read(host, AT91_MCI_RSPR(3)); | |
65dbf343 | 644 | |
ba7deeed NF |
645 | pr_debug("Status = %08X/%08x [%08X %08X %08X %08X]\n", |
646 | status, at91_mci_read(host, AT91_MCI_SR), | |
647 | cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); | |
65dbf343 | 648 | |
9e3866b5 | 649 | if (status & AT91_MCI_ERRORS) { |
b6cedb38 | 650 | if ((status & AT91_MCI_RCRCE) && !(mmc_resp_type(cmd) & MMC_RSP_CRC)) { |
17b0429d | 651 | cmd->error = 0; |
65dbf343 AV |
652 | } |
653 | else { | |
fa1fe010 NF |
654 | if (status & (AT91_MCI_DTOE | AT91_MCI_DCRCE)) { |
655 | if (data) { | |
656 | if (status & AT91_MCI_DTOE) | |
657 | data->error = -ETIMEDOUT; | |
658 | else if (status & AT91_MCI_DCRCE) | |
659 | data->error = -EILSEQ; | |
660 | } | |
661 | } else { | |
662 | if (status & AT91_MCI_RTOE) | |
663 | cmd->error = -ETIMEDOUT; | |
664 | else if (status & AT91_MCI_RCRCE) | |
665 | cmd->error = -EILSEQ; | |
666 | else | |
667 | cmd->error = -EIO; | |
668 | } | |
65dbf343 | 669 | |
fa1fe010 NF |
670 | pr_debug("Error detected and set to %d/%d (cmd = %d, retries = %d)\n", |
671 | cmd->error, data ? data->error : 0, | |
672 | cmd->opcode, cmd->retries); | |
65dbf343 AV |
673 | } |
674 | } | |
675 | else | |
17b0429d | 676 | cmd->error = 0; |
65dbf343 | 677 | |
e8d04d3d | 678 | at91_mci_process_next(host); |
65dbf343 AV |
679 | } |
680 | ||
681 | /* | |
682 | * Handle an MMC request | |
683 | */ | |
684 | static void at91_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
685 | { | |
686 | struct at91mci_host *host = mmc_priv(mmc); | |
687 | host->request = mrq; | |
688 | host->flags = 0; | |
689 | ||
a04ac5b9 WM |
690 | /* more than 1s timeout needed with slow SD cards */ |
691 | mod_timer(&host->timer, jiffies + msecs_to_jiffies(2000)); | |
e181dce8 | 692 | |
e8d04d3d | 693 | at91_mci_process_next(host); |
65dbf343 AV |
694 | } |
695 | ||
696 | /* | |
697 | * Set the IOS | |
698 | */ | |
699 | static void at91_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
700 | { | |
701 | int clkdiv; | |
702 | struct at91mci_host *host = mmc_priv(mmc); | |
3dd3b039 | 703 | unsigned long at91_master_clock = clk_get_rate(host->mci_clk); |
65dbf343 | 704 | |
b44fb7a0 | 705 | host->bus_mode = ios->bus_mode; |
65dbf343 AV |
706 | |
707 | if (ios->clock == 0) { | |
708 | /* Disable the MCI controller */ | |
e0b19b83 | 709 | at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS); |
65dbf343 AV |
710 | clkdiv = 0; |
711 | } | |
712 | else { | |
713 | /* Enable the MCI controller */ | |
e0b19b83 | 714 | at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN); |
65dbf343 AV |
715 | |
716 | if ((at91_master_clock % (ios->clock * 2)) == 0) | |
717 | clkdiv = ((at91_master_clock / ios->clock) / 2) - 1; | |
718 | else | |
719 | clkdiv = (at91_master_clock / ios->clock) / 2; | |
720 | ||
b44fb7a0 | 721 | pr_debug("clkdiv = %d. mcck = %ld\n", clkdiv, |
65dbf343 AV |
722 | at91_master_clock / (2 * (clkdiv + 1))); |
723 | } | |
724 | if (ios->bus_width == MMC_BUS_WIDTH_4 && host->board->wire4) { | |
b44fb7a0 | 725 | pr_debug("MMC: Setting controller bus width to 4\n"); |
e0b19b83 | 726 | at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) | AT91_MCI_SDCBUS); |
65dbf343 AV |
727 | } |
728 | else { | |
b44fb7a0 | 729 | pr_debug("MMC: Setting controller bus width to 1\n"); |
e0b19b83 | 730 | at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS); |
65dbf343 AV |
731 | } |
732 | ||
733 | /* Set the clock divider */ | |
e0b19b83 | 734 | at91_mci_write(host, AT91_MCI_MR, (at91_mci_read(host, AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv); |
65dbf343 AV |
735 | |
736 | /* maybe switch power to the card */ | |
b44fb7a0 | 737 | if (host->board->vcc_pin) { |
65dbf343 AV |
738 | switch (ios->power_mode) { |
739 | case MMC_POWER_OFF: | |
6e996ee8 | 740 | gpio_set_value(host->board->vcc_pin, 0); |
65dbf343 AV |
741 | break; |
742 | case MMC_POWER_UP: | |
6e996ee8 | 743 | gpio_set_value(host->board->vcc_pin, 1); |
65dbf343 | 744 | break; |
e5c0ef90 MP |
745 | case MMC_POWER_ON: |
746 | break; | |
747 | default: | |
748 | WARN_ON(1); | |
65dbf343 AV |
749 | } |
750 | } | |
751 | } | |
752 | ||
753 | /* | |
754 | * Handle an interrupt | |
755 | */ | |
7d12e780 | 756 | static irqreturn_t at91_mci_irq(int irq, void *devid) |
65dbf343 AV |
757 | { |
758 | struct at91mci_host *host = devid; | |
759 | int completed = 0; | |
df05a303 | 760 | unsigned int int_status, int_mask; |
65dbf343 | 761 | |
e0b19b83 | 762 | int_status = at91_mci_read(host, AT91_MCI_SR); |
df05a303 | 763 | int_mask = at91_mci_read(host, AT91_MCI_IMR); |
37b758e8 | 764 | |
f3a8efa9 | 765 | pr_debug("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask, |
df05a303 | 766 | int_status & int_mask); |
37b758e8 | 767 | |
df05a303 AV |
768 | int_status = int_status & int_mask; |
769 | ||
770 | if (int_status & AT91_MCI_ERRORS) { | |
65dbf343 | 771 | completed = 1; |
37b758e8 | 772 | |
df05a303 AV |
773 | if (int_status & AT91_MCI_UNRE) |
774 | pr_debug("MMC: Underrun error\n"); | |
775 | if (int_status & AT91_MCI_OVRE) | |
776 | pr_debug("MMC: Overrun error\n"); | |
777 | if (int_status & AT91_MCI_DTOE) | |
778 | pr_debug("MMC: Data timeout\n"); | |
779 | if (int_status & AT91_MCI_DCRCE) | |
780 | pr_debug("MMC: CRC error in data\n"); | |
781 | if (int_status & AT91_MCI_RTOE) | |
782 | pr_debug("MMC: Response timeout\n"); | |
783 | if (int_status & AT91_MCI_RENDE) | |
784 | pr_debug("MMC: Response end bit error\n"); | |
785 | if (int_status & AT91_MCI_RCRCE) | |
786 | pr_debug("MMC: Response CRC error\n"); | |
787 | if (int_status & AT91_MCI_RDIRE) | |
788 | pr_debug("MMC: Response direction error\n"); | |
789 | if (int_status & AT91_MCI_RINDE) | |
790 | pr_debug("MMC: Response index error\n"); | |
791 | } else { | |
792 | /* Only continue processing if no errors */ | |
65dbf343 | 793 | |
65dbf343 | 794 | if (int_status & AT91_MCI_TXBUFE) { |
b44fb7a0 | 795 | pr_debug("TX buffer empty\n"); |
65dbf343 AV |
796 | at91_mci_handle_transmitted(host); |
797 | } | |
798 | ||
ed99c541 NF |
799 | if (int_status & AT91_MCI_ENDRX) { |
800 | pr_debug("ENDRX\n"); | |
801 | at91_mci_post_dma_read(host); | |
802 | } | |
803 | ||
65dbf343 | 804 | if (int_status & AT91_MCI_RXBUFF) { |
b44fb7a0 | 805 | pr_debug("RX buffer full\n"); |
ed99c541 NF |
806 | at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); |
807 | at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_RXBUFF | AT91_MCI_ENDRX); | |
808 | completed = 1; | |
65dbf343 AV |
809 | } |
810 | ||
df05a303 | 811 | if (int_status & AT91_MCI_ENDTX) |
b44fb7a0 | 812 | pr_debug("Transmit has ended\n"); |
65dbf343 | 813 | |
65dbf343 | 814 | if (int_status & AT91_MCI_NOTBUSY) { |
b44fb7a0 | 815 | pr_debug("Card is ready\n"); |
4ac24a87 | 816 | at91_mci_update_bytes_xfered(host); |
ed99c541 | 817 | completed = 1; |
65dbf343 AV |
818 | } |
819 | ||
df05a303 | 820 | if (int_status & AT91_MCI_DTIP) |
b44fb7a0 | 821 | pr_debug("Data transfer in progress\n"); |
65dbf343 | 822 | |
ed99c541 | 823 | if (int_status & AT91_MCI_BLKE) { |
b44fb7a0 | 824 | pr_debug("Block transfer has ended\n"); |
4ac24a87 NF |
825 | if (host->request->data && host->request->data->blocks > 1) { |
826 | /* multi block write : complete multi write | |
827 | * command and send stop */ | |
828 | completed = 1; | |
829 | } else { | |
830 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY); | |
831 | } | |
ed99c541 | 832 | } |
65dbf343 | 833 | |
7a6588ba EB |
834 | if (int_status & AT91_MCI_SDIOIRQA) |
835 | mmc_signal_sdio_irq(host->mmc); | |
836 | ||
837 | if (int_status & AT91_MCI_SDIOIRQB) | |
838 | mmc_signal_sdio_irq(host->mmc); | |
839 | ||
df05a303 | 840 | if (int_status & AT91_MCI_TXRDY) |
b44fb7a0 | 841 | pr_debug("Ready to transmit\n"); |
65dbf343 | 842 | |
df05a303 | 843 | if (int_status & AT91_MCI_RXRDY) |
b44fb7a0 | 844 | pr_debug("Ready to receive\n"); |
65dbf343 AV |
845 | |
846 | if (int_status & AT91_MCI_CMDRDY) { | |
b44fb7a0 | 847 | pr_debug("Command ready\n"); |
ed99c541 | 848 | completed = at91_mci_handle_cmdrdy(host); |
65dbf343 AV |
849 | } |
850 | } | |
65dbf343 AV |
851 | |
852 | if (completed) { | |
b44fb7a0 | 853 | pr_debug("Completed command\n"); |
7a6588ba | 854 | at91_mci_write(host, AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); |
ba7deeed | 855 | at91_mci_completed_command(host, int_status); |
df05a303 | 856 | } else |
7a6588ba | 857 | at91_mci_write(host, AT91_MCI_IDR, int_status & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); |
65dbf343 AV |
858 | |
859 | return IRQ_HANDLED; | |
860 | } | |
861 | ||
7d12e780 | 862 | static irqreturn_t at91_mmc_det_irq(int irq, void *_host) |
65dbf343 AV |
863 | { |
864 | struct at91mci_host *host = _host; | |
6e996ee8 | 865 | int present = !gpio_get_value(irq_to_gpio(irq)); |
65dbf343 AV |
866 | |
867 | /* | |
868 | * we expect this irq on both insert and remove, | |
869 | * and use a short delay to debounce. | |
870 | */ | |
871 | if (present != host->present) { | |
872 | host->present = present; | |
b44fb7a0 | 873 | pr_debug("%s: card %s\n", mmc_hostname(host->mmc), |
65dbf343 AV |
874 | present ? "insert" : "remove"); |
875 | if (!present) { | |
b44fb7a0 | 876 | pr_debug("****** Resetting SD-card bus width ******\n"); |
99eeb8df | 877 | at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS); |
65dbf343 | 878 | } |
a04ac5b9 WM |
879 | /* 0.5s needed because of early card detect switch firing */ |
880 | mmc_detect_change(host->mmc, msecs_to_jiffies(500)); | |
65dbf343 AV |
881 | } |
882 | return IRQ_HANDLED; | |
883 | } | |
884 | ||
a26b498c | 885 | static int at91_mci_get_ro(struct mmc_host *mmc) |
65dbf343 | 886 | { |
65dbf343 AV |
887 | struct at91mci_host *host = mmc_priv(mmc); |
888 | ||
08f80bb5 AV |
889 | if (host->board->wp_pin) |
890 | return !!gpio_get_value(host->board->wp_pin); | |
891 | /* | |
892 | * Board doesn't support read only detection; let the mmc core | |
893 | * decide what to do. | |
894 | */ | |
895 | return -ENOSYS; | |
65dbf343 AV |
896 | } |
897 | ||
7a6588ba EB |
898 | static void at91_mci_enable_sdio_irq(struct mmc_host *mmc, int enable) |
899 | { | |
900 | struct at91mci_host *host = mmc_priv(mmc); | |
901 | ||
902 | pr_debug("%s: sdio_irq %c : %s\n", mmc_hostname(host->mmc), | |
903 | host->board->slot_b ? 'B':'A', enable ? "enable" : "disable"); | |
904 | at91_mci_write(host, enable ? AT91_MCI_IER : AT91_MCI_IDR, | |
905 | host->board->slot_b ? AT91_MCI_SDIOIRQB : AT91_MCI_SDIOIRQA); | |
906 | ||
907 | } | |
908 | ||
ab7aefd0 | 909 | static const struct mmc_host_ops at91_mci_ops = { |
65dbf343 AV |
910 | .request = at91_mci_request, |
911 | .set_ios = at91_mci_set_ios, | |
912 | .get_ro = at91_mci_get_ro, | |
7a6588ba | 913 | .enable_sdio_irq = at91_mci_enable_sdio_irq, |
65dbf343 AV |
914 | }; |
915 | ||
916 | /* | |
917 | * Probe for the device | |
918 | */ | |
a26b498c | 919 | static int __init at91_mci_probe(struct platform_device *pdev) |
65dbf343 AV |
920 | { |
921 | struct mmc_host *mmc; | |
922 | struct at91mci_host *host; | |
17ea0595 | 923 | struct resource *res; |
65dbf343 AV |
924 | int ret; |
925 | ||
17ea0595 AV |
926 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
927 | if (!res) | |
928 | return -ENXIO; | |
929 | ||
930 | if (!request_mem_region(res->start, res->end - res->start + 1, DRIVER_NAME)) | |
931 | return -EBUSY; | |
932 | ||
65dbf343 AV |
933 | mmc = mmc_alloc_host(sizeof(struct at91mci_host), &pdev->dev); |
934 | if (!mmc) { | |
6e996ee8 DB |
935 | ret = -ENOMEM; |
936 | dev_dbg(&pdev->dev, "couldn't allocate mmc host\n"); | |
937 | goto fail6; | |
65dbf343 AV |
938 | } |
939 | ||
940 | mmc->ops = &at91_mci_ops; | |
941 | mmc->f_min = 375000; | |
942 | mmc->f_max = 25000000; | |
943 | mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; | |
541e7ef0 | 944 | mmc->caps = 0; |
65dbf343 | 945 | |
3780d906 WM |
946 | mmc->max_blk_size = MCI_MAXBLKSIZE; |
947 | mmc->max_blk_count = MCI_BLKATONCE; | |
948 | mmc->max_req_size = MCI_BUFSIZE; | |
9af13be2 WM |
949 | mmc->max_phys_segs = MCI_BLKATONCE; |
950 | mmc->max_hw_segs = MCI_BLKATONCE; | |
951 | mmc->max_seg_size = MCI_BUFSIZE; | |
fe4a3c7a | 952 | |
65dbf343 AV |
953 | host = mmc_priv(mmc); |
954 | host->mmc = mmc; | |
65dbf343 AV |
955 | host->bus_mode = 0; |
956 | host->board = pdev->dev.platform_data; | |
957 | if (host->board->wire4) { | |
5b27a1a5 | 958 | if (at91mci_is_mci1rev2xx()) |
ed99c541 NF |
959 | mmc->caps |= MMC_CAP_4_BIT_DATA; |
960 | else | |
6e996ee8 | 961 | dev_warn(&pdev->dev, "4 wire bus mode not supported" |
ed99c541 | 962 | " - using 1 wire\n"); |
65dbf343 AV |
963 | } |
964 | ||
3780d906 WM |
965 | host->buffer = dma_alloc_coherent(&pdev->dev, MCI_BUFSIZE, |
966 | &host->physical_address, GFP_KERNEL); | |
967 | if (!host->buffer) { | |
968 | ret = -ENOMEM; | |
969 | dev_err(&pdev->dev, "Can't allocate transmit buffer\n"); | |
970 | goto fail5; | |
971 | } | |
972 | ||
541e7ef0 | 973 | /* Add SDIO capability when available */ |
5b27a1a5 NF |
974 | if (at91mci_is_mci1rev2xx()) { |
975 | /* at91mci MCI1 rev2xx sdio interrupt erratum */ | |
541e7ef0 NF |
976 | if (host->board->wire4 || !host->board->slot_b) |
977 | mmc->caps |= MMC_CAP_SDIO_IRQ; | |
978 | } | |
979 | ||
6e996ee8 DB |
980 | /* |
981 | * Reserve GPIOs ... board init code makes sure these pins are set | |
982 | * up as GPIOs with the right direction (input, except for vcc) | |
983 | */ | |
984 | if (host->board->det_pin) { | |
985 | ret = gpio_request(host->board->det_pin, "mmc_detect"); | |
986 | if (ret < 0) { | |
987 | dev_dbg(&pdev->dev, "couldn't claim card detect pin\n"); | |
3780d906 | 988 | goto fail4b; |
6e996ee8 DB |
989 | } |
990 | } | |
991 | if (host->board->wp_pin) { | |
992 | ret = gpio_request(host->board->wp_pin, "mmc_wp"); | |
993 | if (ret < 0) { | |
994 | dev_dbg(&pdev->dev, "couldn't claim wp sense pin\n"); | |
995 | goto fail4; | |
996 | } | |
997 | } | |
998 | if (host->board->vcc_pin) { | |
999 | ret = gpio_request(host->board->vcc_pin, "mmc_vcc"); | |
1000 | if (ret < 0) { | |
1001 | dev_dbg(&pdev->dev, "couldn't claim vcc switch pin\n"); | |
1002 | goto fail3; | |
1003 | } | |
1004 | } | |
1005 | ||
65dbf343 AV |
1006 | /* |
1007 | * Get Clock | |
1008 | */ | |
3dd3b039 AV |
1009 | host->mci_clk = clk_get(&pdev->dev, "mci_clk"); |
1010 | if (IS_ERR(host->mci_clk)) { | |
6e996ee8 DB |
1011 | ret = -ENODEV; |
1012 | dev_dbg(&pdev->dev, "no mci_clk?\n"); | |
1013 | goto fail2; | |
65dbf343 | 1014 | } |
65dbf343 | 1015 | |
17ea0595 AV |
1016 | /* |
1017 | * Map I/O region | |
1018 | */ | |
1019 | host->baseaddr = ioremap(res->start, res->end - res->start + 1); | |
1020 | if (!host->baseaddr) { | |
6e996ee8 DB |
1021 | ret = -ENOMEM; |
1022 | goto fail1; | |
17ea0595 | 1023 | } |
e0b19b83 AV |
1024 | |
1025 | /* | |
1026 | * Reset hardware | |
1027 | */ | |
3dd3b039 | 1028 | clk_enable(host->mci_clk); /* Enable the peripheral clock */ |
e0b19b83 AV |
1029 | at91_mci_disable(host); |
1030 | at91_mci_enable(host); | |
1031 | ||
65dbf343 AV |
1032 | /* |
1033 | * Allocate the MCI interrupt | |
1034 | */ | |
17ea0595 | 1035 | host->irq = platform_get_irq(pdev, 0); |
6e996ee8 DB |
1036 | ret = request_irq(host->irq, at91_mci_irq, IRQF_SHARED, |
1037 | mmc_hostname(mmc), host); | |
65dbf343 | 1038 | if (ret) { |
6e996ee8 DB |
1039 | dev_dbg(&pdev->dev, "request MCI interrupt failed\n"); |
1040 | goto fail0; | |
65dbf343 AV |
1041 | } |
1042 | ||
99ba0405 NF |
1043 | setup_timer(&host->timer, at91_timeout_timer, (unsigned long)host); |
1044 | ||
65dbf343 AV |
1045 | platform_set_drvdata(pdev, mmc); |
1046 | ||
1047 | /* | |
1048 | * Add host to MMC layer | |
1049 | */ | |
63b66438 | 1050 | if (host->board->det_pin) { |
6e996ee8 | 1051 | host->present = !gpio_get_value(host->board->det_pin); |
63b66438 | 1052 | } |
65dbf343 AV |
1053 | else |
1054 | host->present = -1; | |
1055 | ||
1056 | mmc_add_host(mmc); | |
1057 | ||
1058 | /* | |
1059 | * monitor card insertion/removal if we can | |
1060 | */ | |
1061 | if (host->board->det_pin) { | |
6e996ee8 DB |
1062 | ret = request_irq(gpio_to_irq(host->board->det_pin), |
1063 | at91_mmc_det_irq, 0, mmc_hostname(mmc), host); | |
65dbf343 | 1064 | if (ret) |
6e996ee8 DB |
1065 | dev_warn(&pdev->dev, "request MMC detect irq failed\n"); |
1066 | else | |
1067 | device_init_wakeup(&pdev->dev, 1); | |
65dbf343 AV |
1068 | } |
1069 | ||
f3a8efa9 | 1070 | pr_debug("Added MCI driver\n"); |
65dbf343 AV |
1071 | |
1072 | return 0; | |
6e996ee8 DB |
1073 | |
1074 | fail0: | |
1075 | clk_disable(host->mci_clk); | |
1076 | iounmap(host->baseaddr); | |
1077 | fail1: | |
1078 | clk_put(host->mci_clk); | |
1079 | fail2: | |
1080 | if (host->board->vcc_pin) | |
1081 | gpio_free(host->board->vcc_pin); | |
1082 | fail3: | |
1083 | if (host->board->wp_pin) | |
1084 | gpio_free(host->board->wp_pin); | |
1085 | fail4: | |
1086 | if (host->board->det_pin) | |
1087 | gpio_free(host->board->det_pin); | |
3780d906 WM |
1088 | fail4b: |
1089 | if (host->buffer) | |
1090 | dma_free_coherent(&pdev->dev, MCI_BUFSIZE, | |
1091 | host->buffer, host->physical_address); | |
6e996ee8 DB |
1092 | fail5: |
1093 | mmc_free_host(mmc); | |
1094 | fail6: | |
1095 | release_mem_region(res->start, res->end - res->start + 1); | |
1096 | dev_err(&pdev->dev, "probe failed, err %d\n", ret); | |
1097 | return ret; | |
65dbf343 AV |
1098 | } |
1099 | ||
1100 | /* | |
1101 | * Remove a device | |
1102 | */ | |
a26b498c | 1103 | static int __exit at91_mci_remove(struct platform_device *pdev) |
65dbf343 AV |
1104 | { |
1105 | struct mmc_host *mmc = platform_get_drvdata(pdev); | |
1106 | struct at91mci_host *host; | |
17ea0595 | 1107 | struct resource *res; |
65dbf343 AV |
1108 | |
1109 | if (!mmc) | |
1110 | return -1; | |
1111 | ||
1112 | host = mmc_priv(mmc); | |
1113 | ||
3780d906 WM |
1114 | if (host->buffer) |
1115 | dma_free_coherent(&pdev->dev, MCI_BUFSIZE, | |
1116 | host->buffer, host->physical_address); | |
1117 | ||
e0cda54e | 1118 | if (host->board->det_pin) { |
6e996ee8 DB |
1119 | if (device_can_wakeup(&pdev->dev)) |
1120 | free_irq(gpio_to_irq(host->board->det_pin), host); | |
63b66438 | 1121 | device_init_wakeup(&pdev->dev, 0); |
6e996ee8 | 1122 | gpio_free(host->board->det_pin); |
65dbf343 AV |
1123 | } |
1124 | ||
e0b19b83 | 1125 | at91_mci_disable(host); |
e181dce8 | 1126 | del_timer_sync(&host->timer); |
17ea0595 AV |
1127 | mmc_remove_host(mmc); |
1128 | free_irq(host->irq, host); | |
65dbf343 | 1129 | |
3dd3b039 AV |
1130 | clk_disable(host->mci_clk); /* Disable the peripheral clock */ |
1131 | clk_put(host->mci_clk); | |
65dbf343 | 1132 | |
6e996ee8 DB |
1133 | if (host->board->vcc_pin) |
1134 | gpio_free(host->board->vcc_pin); | |
1135 | if (host->board->wp_pin) | |
1136 | gpio_free(host->board->wp_pin); | |
1137 | ||
17ea0595 AV |
1138 | iounmap(host->baseaddr); |
1139 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1140 | release_mem_region(res->start, res->end - res->start + 1); | |
65dbf343 | 1141 | |
17ea0595 AV |
1142 | mmc_free_host(mmc); |
1143 | platform_set_drvdata(pdev, NULL); | |
b44fb7a0 | 1144 | pr_debug("MCI Removed\n"); |
65dbf343 AV |
1145 | |
1146 | return 0; | |
1147 | } | |
1148 | ||
1149 | #ifdef CONFIG_PM | |
1150 | static int at91_mci_suspend(struct platform_device *pdev, pm_message_t state) | |
1151 | { | |
1152 | struct mmc_host *mmc = platform_get_drvdata(pdev); | |
63b66438 | 1153 | struct at91mci_host *host = mmc_priv(mmc); |
65dbf343 AV |
1154 | int ret = 0; |
1155 | ||
e0cda54e | 1156 | if (host->board->det_pin && device_may_wakeup(&pdev->dev)) |
63b66438 MP |
1157 | enable_irq_wake(host->board->det_pin); |
1158 | ||
65dbf343 AV |
1159 | if (mmc) |
1160 | ret = mmc_suspend_host(mmc, state); | |
1161 | ||
1162 | return ret; | |
1163 | } | |
1164 | ||
1165 | static int at91_mci_resume(struct platform_device *pdev) | |
1166 | { | |
1167 | struct mmc_host *mmc = platform_get_drvdata(pdev); | |
63b66438 | 1168 | struct at91mci_host *host = mmc_priv(mmc); |
65dbf343 AV |
1169 | int ret = 0; |
1170 | ||
e0cda54e | 1171 | if (host->board->det_pin && device_may_wakeup(&pdev->dev)) |
63b66438 MP |
1172 | disable_irq_wake(host->board->det_pin); |
1173 | ||
65dbf343 AV |
1174 | if (mmc) |
1175 | ret = mmc_resume_host(mmc); | |
1176 | ||
1177 | return ret; | |
1178 | } | |
1179 | #else | |
1180 | #define at91_mci_suspend NULL | |
1181 | #define at91_mci_resume NULL | |
1182 | #endif | |
1183 | ||
1184 | static struct platform_driver at91_mci_driver = { | |
a26b498c | 1185 | .remove = __exit_p(at91_mci_remove), |
65dbf343 AV |
1186 | .suspend = at91_mci_suspend, |
1187 | .resume = at91_mci_resume, | |
1188 | .driver = { | |
1189 | .name = DRIVER_NAME, | |
1190 | .owner = THIS_MODULE, | |
1191 | }, | |
1192 | }; | |
1193 | ||
1194 | static int __init at91_mci_init(void) | |
1195 | { | |
a26b498c | 1196 | return platform_driver_probe(&at91_mci_driver, at91_mci_probe); |
65dbf343 AV |
1197 | } |
1198 | ||
1199 | static void __exit at91_mci_exit(void) | |
1200 | { | |
1201 | platform_driver_unregister(&at91_mci_driver); | |
1202 | } | |
1203 | ||
1204 | module_init(at91_mci_init); | |
1205 | module_exit(at91_mci_exit); | |
1206 | ||
1207 | MODULE_DESCRIPTION("AT91 Multimedia Card Interface driver"); | |
1208 | MODULE_AUTHOR("Nick Randell"); | |
1209 | MODULE_LICENSE("GPL"); | |
bc65c724 | 1210 | MODULE_ALIAS("platform:at91_mci"); |