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65dbf343 | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/at91_mci.c - ATMEL AT91 MCI Driver |
65dbf343 AV |
3 | * |
4 | * Copyright (C) 2005 Cougar Creek Computing Devices Ltd, All Rights Reserved | |
5 | * | |
6 | * Copyright (C) 2006 Malcolm Noyes | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | /* | |
99eeb8df | 14 | This is the AT91 MCI driver that has been tested with both MMC cards |
65dbf343 AV |
15 | and SD-cards. Boards that support write protect are now supported. |
16 | The CCAT91SBC001 board does not support SD cards. | |
17 | ||
18 | The three entry points are at91_mci_request, at91_mci_set_ios | |
19 | and at91_mci_get_ro. | |
20 | ||
21 | SET IOS | |
22 | This configures the device to put it into the correct mode and clock speed | |
23 | required. | |
24 | ||
25 | MCI REQUEST | |
26 | MCI request processes the commands sent in the mmc_request structure. This | |
27 | can consist of a processing command and a stop command in the case of | |
28 | multiple block transfers. | |
29 | ||
30 | There are three main types of request, commands, reads and writes. | |
31 | ||
32 | Commands are straight forward. The command is submitted to the controller and | |
33 | the request function returns. When the controller generates an interrupt to indicate | |
34 | the command is finished, the response to the command are read and the mmc_request_done | |
35 | function called to end the request. | |
36 | ||
37 | Reads and writes work in a similar manner to normal commands but involve the PDC (DMA) | |
38 | controller to manage the transfers. | |
39 | ||
40 | A read is done from the controller directly to the scatterlist passed in from the request. | |
99eeb8df AV |
41 | Due to a bug in the AT91RM9200 controller, when a read is completed, all the words are byte |
42 | swapped in the scatterlist buffers. AT91SAM926x are not affected by this bug. | |
65dbf343 AV |
43 | |
44 | The sequence of read interrupts is: ENDRX, RXBUFF, CMDRDY | |
45 | ||
46 | A write is slightly different in that the bytes to write are read from the scatterlist | |
47 | into a dma memory buffer (this is in case the source buffer should be read only). The | |
48 | entire write buffer is then done from this single dma memory buffer. | |
49 | ||
50 | The sequence of write interrupts is: ENDTX, TXBUFE, NOTBUSY, CMDRDY | |
51 | ||
52 | GET RO | |
53 | Gets the status of the write protect pin, if available. | |
54 | */ | |
55 | ||
65dbf343 AV |
56 | #include <linux/module.h> |
57 | #include <linux/moduleparam.h> | |
58 | #include <linux/init.h> | |
59 | #include <linux/ioport.h> | |
60 | #include <linux/platform_device.h> | |
61 | #include <linux/interrupt.h> | |
62 | #include <linux/blkdev.h> | |
63 | #include <linux/delay.h> | |
64 | #include <linux/err.h> | |
65 | #include <linux/dma-mapping.h> | |
66 | #include <linux/clk.h> | |
93a3ddc2 | 67 | #include <linux/atmel_pdc.h> |
65dbf343 AV |
68 | |
69 | #include <linux/mmc/host.h> | |
65dbf343 AV |
70 | |
71 | #include <asm/io.h> | |
72 | #include <asm/irq.h> | |
6e996ee8 DB |
73 | #include <asm/gpio.h> |
74 | ||
a09e64fb RK |
75 | #include <mach/board.h> |
76 | #include <mach/cpu.h> | |
77 | #include <mach/at91_mci.h> | |
65dbf343 AV |
78 | |
79 | #define DRIVER_NAME "at91_mci" | |
80 | ||
df05a303 AV |
81 | #define FL_SENT_COMMAND (1 << 0) |
82 | #define FL_SENT_STOP (1 << 1) | |
65dbf343 | 83 | |
df05a303 AV |
84 | #define AT91_MCI_ERRORS (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE \ |
85 | | AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE \ | |
37b758e8 | 86 | | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE) |
65dbf343 | 87 | |
e0b19b83 AV |
88 | #define at91_mci_read(host, reg) __raw_readl((host)->baseaddr + (reg)) |
89 | #define at91_mci_write(host, reg, val) __raw_writel((val), (host)->baseaddr + (reg)) | |
65dbf343 | 90 | |
3780d906 WM |
91 | #define MCI_BLKSIZE 512 |
92 | #define MCI_MAXBLKSIZE 4095 | |
93 | #define MCI_BLKATONCE 256 | |
94 | #define MCI_BUFSIZE (MCI_BLKSIZE * MCI_BLKATONCE) | |
65dbf343 AV |
95 | |
96 | /* | |
97 | * Low level type for this driver | |
98 | */ | |
99 | struct at91mci_host | |
100 | { | |
101 | struct mmc_host *mmc; | |
102 | struct mmc_command *cmd; | |
103 | struct mmc_request *request; | |
104 | ||
e0b19b83 | 105 | void __iomem *baseaddr; |
17ea0595 | 106 | int irq; |
e0b19b83 | 107 | |
65dbf343 AV |
108 | struct at91_mmc_data *board; |
109 | int present; | |
110 | ||
3dd3b039 AV |
111 | struct clk *mci_clk; |
112 | ||
65dbf343 AV |
113 | /* |
114 | * Flag indicating when the command has been sent. This is used to | |
115 | * work out whether or not to send the stop | |
116 | */ | |
117 | unsigned int flags; | |
118 | /* flag for current bus settings */ | |
119 | u32 bus_mode; | |
120 | ||
121 | /* DMA buffer used for transmitting */ | |
122 | unsigned int* buffer; | |
123 | dma_addr_t physical_address; | |
124 | unsigned int total_length; | |
125 | ||
126 | /* Latest in the scatterlist that has been enabled for transfer, but not freed */ | |
127 | int in_use_index; | |
128 | ||
129 | /* Latest in the scatterlist that has been enabled for transfer */ | |
130 | int transfer_index; | |
e181dce8 MP |
131 | |
132 | /* Timer for timeouts */ | |
133 | struct timer_list timer; | |
65dbf343 AV |
134 | }; |
135 | ||
c5a89c6c MP |
136 | /* |
137 | * Reset the controller and restore most of the state | |
138 | */ | |
139 | static void at91_reset_host(struct at91mci_host *host) | |
140 | { | |
141 | unsigned long flags; | |
142 | u32 mr; | |
143 | u32 sdcr; | |
144 | u32 dtor; | |
145 | u32 imr; | |
146 | ||
147 | local_irq_save(flags); | |
148 | imr = at91_mci_read(host, AT91_MCI_IMR); | |
149 | ||
150 | at91_mci_write(host, AT91_MCI_IDR, 0xffffffff); | |
151 | ||
152 | /* save current state */ | |
153 | mr = at91_mci_read(host, AT91_MCI_MR) & 0x7fff; | |
154 | sdcr = at91_mci_read(host, AT91_MCI_SDCR); | |
155 | dtor = at91_mci_read(host, AT91_MCI_DTOR); | |
156 | ||
157 | /* reset the controller */ | |
158 | at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST); | |
159 | ||
160 | /* restore state */ | |
161 | at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN); | |
162 | at91_mci_write(host, AT91_MCI_MR, mr); | |
163 | at91_mci_write(host, AT91_MCI_SDCR, sdcr); | |
164 | at91_mci_write(host, AT91_MCI_DTOR, dtor); | |
165 | at91_mci_write(host, AT91_MCI_IER, imr); | |
166 | ||
167 | /* make sure sdio interrupts will fire */ | |
168 | at91_mci_read(host, AT91_MCI_SR); | |
169 | ||
170 | local_irq_restore(flags); | |
171 | } | |
172 | ||
e181dce8 MP |
173 | static void at91_timeout_timer(unsigned long data) |
174 | { | |
175 | struct at91mci_host *host; | |
176 | ||
177 | host = (struct at91mci_host *)data; | |
178 | ||
179 | if (host->request) { | |
180 | dev_err(host->mmc->parent, "Timeout waiting end of packet\n"); | |
181 | ||
182 | if (host->cmd && host->cmd->data) { | |
183 | host->cmd->data->error = -ETIMEDOUT; | |
184 | } else { | |
185 | if (host->cmd) | |
186 | host->cmd->error = -ETIMEDOUT; | |
187 | else | |
188 | host->request->cmd->error = -ETIMEDOUT; | |
189 | } | |
190 | ||
c5a89c6c | 191 | at91_reset_host(host); |
e181dce8 MP |
192 | mmc_request_done(host->mmc, host->request); |
193 | } | |
194 | } | |
195 | ||
65dbf343 AV |
196 | /* |
197 | * Copy from sg to a dma block - used for transfers | |
198 | */ | |
e8d04d3d | 199 | static inline void at91_mci_sg_to_dma(struct at91mci_host *host, struct mmc_data *data) |
65dbf343 AV |
200 | { |
201 | unsigned int len, i, size; | |
202 | unsigned *dmabuf = host->buffer; | |
203 | ||
5385edc5 | 204 | size = data->blksz * data->blocks; |
65dbf343 AV |
205 | len = data->sg_len; |
206 | ||
5385edc5 VS |
207 | /* AT91SAM926[0/3] Data Write Operation and number of bytes erratum */ |
208 | if (cpu_is_at91sam9260() || cpu_is_at91sam9263()) | |
209 | if (host->total_length == 12) | |
210 | memset(dmabuf, 0, 12); | |
211 | ||
65dbf343 AV |
212 | /* |
213 | * Just loop through all entries. Size might not | |
214 | * be the entire list though so make sure that | |
215 | * we do not transfer too much. | |
216 | */ | |
217 | for (i = 0; i < len; i++) { | |
218 | struct scatterlist *sg; | |
219 | int amount; | |
65dbf343 AV |
220 | unsigned int *sgbuffer; |
221 | ||
222 | sg = &data->sg[i]; | |
223 | ||
45711f1a | 224 | sgbuffer = kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset; |
65dbf343 AV |
225 | amount = min(size, sg->length); |
226 | size -= amount; | |
65dbf343 | 227 | |
99eeb8df AV |
228 | if (cpu_is_at91rm9200()) { /* AT91RM9200 errata */ |
229 | int index; | |
230 | ||
231 | for (index = 0; index < (amount / 4); index++) | |
232 | *dmabuf++ = swab32(sgbuffer[index]); | |
5385edc5 | 233 | } else { |
0b3520f2 WM |
234 | char *tmpv = (char *)dmabuf; |
235 | memcpy(tmpv, sgbuffer, amount); | |
236 | tmpv += amount; | |
237 | dmabuf = (unsigned *)tmpv; | |
5385edc5 | 238 | } |
65dbf343 | 239 | |
0b3520f2 | 240 | kunmap_atomic(((void *)sgbuffer) - sg->offset, KM_BIO_SRC_IRQ); |
65dbf343 AV |
241 | |
242 | if (size == 0) | |
243 | break; | |
244 | } | |
245 | ||
246 | /* | |
247 | * Check that we didn't get a request to transfer | |
248 | * more data than can fit into the SG list. | |
249 | */ | |
250 | BUG_ON(size != 0); | |
251 | } | |
252 | ||
65dbf343 AV |
253 | /* |
254 | * Handle after a dma read | |
255 | */ | |
e8d04d3d | 256 | static void at91_mci_post_dma_read(struct at91mci_host *host) |
65dbf343 AV |
257 | { |
258 | struct mmc_command *cmd; | |
259 | struct mmc_data *data; | |
86ee26f5 WM |
260 | unsigned int len, i, size; |
261 | unsigned *dmabuf = host->buffer; | |
65dbf343 | 262 | |
b44fb7a0 | 263 | pr_debug("post dma read\n"); |
65dbf343 AV |
264 | |
265 | cmd = host->cmd; | |
266 | if (!cmd) { | |
b44fb7a0 | 267 | pr_debug("no command\n"); |
65dbf343 AV |
268 | return; |
269 | } | |
270 | ||
271 | data = cmd->data; | |
272 | if (!data) { | |
b44fb7a0 | 273 | pr_debug("no data\n"); |
65dbf343 AV |
274 | return; |
275 | } | |
276 | ||
86ee26f5 WM |
277 | size = data->blksz * data->blocks; |
278 | len = data->sg_len; | |
65dbf343 | 279 | |
86ee26f5 WM |
280 | at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_ENDRX); |
281 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_RXBUFF); | |
65dbf343 | 282 | |
86ee26f5 WM |
283 | for (i = 0; i < len; i++) { |
284 | struct scatterlist *sg; | |
285 | int amount; | |
286 | unsigned int *sgbuffer; | |
65dbf343 | 287 | |
86ee26f5 | 288 | sg = &data->sg[i]; |
65dbf343 | 289 | |
86ee26f5 WM |
290 | sgbuffer = kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset; |
291 | amount = min(size, sg->length); | |
292 | size -= amount; | |
65dbf343 | 293 | |
99eeb8df AV |
294 | if (cpu_is_at91rm9200()) { /* AT91RM9200 errata */ |
295 | int index; | |
86ee26f5 WM |
296 | for (index = 0; index < (amount / 4); index++) |
297 | sgbuffer[index] = swab32(*dmabuf++); | |
298 | } else { | |
299 | char *tmpv = (char *)dmabuf; | |
300 | memcpy(sgbuffer, tmpv, amount); | |
301 | tmpv += amount; | |
302 | dmabuf = (unsigned *)tmpv; | |
65dbf343 | 303 | } |
99eeb8df | 304 | |
86ee26f5 WM |
305 | kunmap_atomic(((void *)sgbuffer)-sg->offset, KM_BIO_SRC_IRQ); |
306 | dmac_flush_range((void *)sgbuffer, ((void *)sgbuffer) + amount); | |
307 | data->bytes_xfered += amount; | |
308 | if (size == 0) | |
309 | break; | |
65dbf343 AV |
310 | } |
311 | ||
b44fb7a0 | 312 | pr_debug("post dma read done\n"); |
65dbf343 AV |
313 | } |
314 | ||
315 | /* | |
316 | * Handle transmitted data | |
317 | */ | |
318 | static void at91_mci_handle_transmitted(struct at91mci_host *host) | |
319 | { | |
320 | struct mmc_command *cmd; | |
321 | struct mmc_data *data; | |
322 | ||
b44fb7a0 | 323 | pr_debug("Handling the transmit\n"); |
65dbf343 AV |
324 | |
325 | /* Disable the transfer */ | |
93a3ddc2 | 326 | at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); |
65dbf343 AV |
327 | |
328 | /* Now wait for cmd ready */ | |
e0b19b83 | 329 | at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_TXBUFE); |
65dbf343 AV |
330 | |
331 | cmd = host->cmd; | |
332 | if (!cmd) return; | |
333 | ||
334 | data = cmd->data; | |
335 | if (!data) return; | |
336 | ||
be0192aa | 337 | if (cmd->data->blocks > 1) { |
ed99c541 NF |
338 | pr_debug("multiple write : wait for BLKE...\n"); |
339 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_BLKE); | |
340 | } else | |
341 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY); | |
4ac24a87 NF |
342 | } |
343 | ||
344 | /* | |
345 | * Update bytes tranfered count during a write operation | |
346 | */ | |
347 | static void at91_mci_update_bytes_xfered(struct at91mci_host *host) | |
348 | { | |
349 | struct mmc_data *data; | |
ed99c541 | 350 | |
4ac24a87 NF |
351 | /* always deal with the effective request (and not the current cmd) */ |
352 | ||
353 | if (host->request->cmd && host->request->cmd->error != 0) | |
354 | return; | |
355 | ||
356 | if (host->request->data) { | |
357 | data = host->request->data; | |
358 | if (data->flags & MMC_DATA_WRITE) { | |
359 | /* card is in IDLE mode now */ | |
360 | pr_debug("-> bytes_xfered %d, total_length = %d\n", | |
361 | data->bytes_xfered, host->total_length); | |
5385edc5 | 362 | data->bytes_xfered = data->blksz * data->blocks; |
4ac24a87 NF |
363 | } |
364 | } | |
65dbf343 AV |
365 | } |
366 | ||
4ac24a87 | 367 | |
ed99c541 NF |
368 | /*Handle after command sent ready*/ |
369 | static int at91_mci_handle_cmdrdy(struct at91mci_host *host) | |
370 | { | |
371 | if (!host->cmd) | |
372 | return 1; | |
373 | else if (!host->cmd->data) { | |
374 | if (host->flags & FL_SENT_STOP) { | |
375 | /*After multi block write, we must wait for NOTBUSY*/ | |
376 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY); | |
377 | } else return 1; | |
378 | } else if (host->cmd->data->flags & MMC_DATA_WRITE) { | |
379 | /*After sendding multi-block-write command, start DMA transfer*/ | |
4ac24a87 | 380 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_TXBUFE | AT91_MCI_BLKE); |
ed99c541 NF |
381 | at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); |
382 | } | |
383 | ||
384 | /* command not completed, have to wait */ | |
385 | return 0; | |
386 | } | |
387 | ||
388 | ||
65dbf343 AV |
389 | /* |
390 | * Enable the controller | |
391 | */ | |
e0b19b83 | 392 | static void at91_mci_enable(struct at91mci_host *host) |
65dbf343 | 393 | { |
ed99c541 NF |
394 | unsigned int mr; |
395 | ||
e0b19b83 | 396 | at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN); |
f3a8efa9 | 397 | at91_mci_write(host, AT91_MCI_IDR, 0xffffffff); |
e0b19b83 | 398 | at91_mci_write(host, AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC); |
ed99c541 NF |
399 | mr = AT91_MCI_PDCMODE | 0x34a; |
400 | ||
401 | if (cpu_is_at91sam9260() || cpu_is_at91sam9263()) | |
402 | mr |= AT91_MCI_RDPROOF | AT91_MCI_WRPROOF; | |
403 | ||
404 | at91_mci_write(host, AT91_MCI_MR, mr); | |
99eeb8df AV |
405 | |
406 | /* use Slot A or B (only one at same time) */ | |
407 | at91_mci_write(host, AT91_MCI_SDCR, host->board->slot_b); | |
65dbf343 AV |
408 | } |
409 | ||
410 | /* | |
411 | * Disable the controller | |
412 | */ | |
e0b19b83 | 413 | static void at91_mci_disable(struct at91mci_host *host) |
65dbf343 | 414 | { |
e0b19b83 | 415 | at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST); |
65dbf343 AV |
416 | } |
417 | ||
418 | /* | |
419 | * Send a command | |
65dbf343 | 420 | */ |
ed99c541 | 421 | static void at91_mci_send_command(struct at91mci_host *host, struct mmc_command *cmd) |
65dbf343 AV |
422 | { |
423 | unsigned int cmdr, mr; | |
424 | unsigned int block_length; | |
425 | struct mmc_data *data = cmd->data; | |
426 | ||
427 | unsigned int blocks; | |
428 | unsigned int ier = 0; | |
429 | ||
430 | host->cmd = cmd; | |
431 | ||
ed99c541 | 432 | /* Needed for leaving busy state before CMD1 */ |
e0b19b83 | 433 | if ((at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->opcode == 1)) { |
b44fb7a0 | 434 | pr_debug("Clearing timeout\n"); |
e0b19b83 AV |
435 | at91_mci_write(host, AT91_MCI_ARGR, 0); |
436 | at91_mci_write(host, AT91_MCI_CMDR, AT91_MCI_OPDCMD); | |
437 | while (!(at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_CMDRDY)) { | |
65dbf343 | 438 | /* spin */ |
e0b19b83 | 439 | pr_debug("Clearing: SR = %08X\n", at91_mci_read(host, AT91_MCI_SR)); |
65dbf343 AV |
440 | } |
441 | } | |
ed99c541 | 442 | |
65dbf343 AV |
443 | cmdr = cmd->opcode; |
444 | ||
445 | if (mmc_resp_type(cmd) == MMC_RSP_NONE) | |
446 | cmdr |= AT91_MCI_RSPTYP_NONE; | |
447 | else { | |
448 | /* if a response is expected then allow maximum response latancy */ | |
449 | cmdr |= AT91_MCI_MAXLAT; | |
450 | /* set 136 bit response for R2, 48 bit response otherwise */ | |
451 | if (mmc_resp_type(cmd) == MMC_RSP_R2) | |
452 | cmdr |= AT91_MCI_RSPTYP_136; | |
453 | else | |
454 | cmdr |= AT91_MCI_RSPTYP_48; | |
455 | } | |
456 | ||
457 | if (data) { | |
1d4de9ed | 458 | |
9da3cbaf VS |
459 | if (cpu_is_at91rm9200() || cpu_is_at91sam9261()) { |
460 | if (data->blksz & 0x3) { | |
461 | pr_debug("Unsupported block size\n"); | |
462 | cmd->error = -EINVAL; | |
463 | mmc_request_done(host->mmc, host->request); | |
464 | return; | |
465 | } | |
466 | if (data->flags & MMC_DATA_STREAM) { | |
467 | pr_debug("Stream commands not supported\n"); | |
468 | cmd->error = -EINVAL; | |
469 | mmc_request_done(host->mmc, host->request); | |
470 | return; | |
471 | } | |
1d4de9ed MP |
472 | } |
473 | ||
a3fd4a1b | 474 | block_length = data->blksz; |
65dbf343 AV |
475 | blocks = data->blocks; |
476 | ||
477 | /* always set data start - also set direction flag for read */ | |
478 | if (data->flags & MMC_DATA_READ) | |
479 | cmdr |= (AT91_MCI_TRDIR | AT91_MCI_TRCMD_START); | |
480 | else if (data->flags & MMC_DATA_WRITE) | |
481 | cmdr |= AT91_MCI_TRCMD_START; | |
482 | ||
483 | if (data->flags & MMC_DATA_STREAM) | |
484 | cmdr |= AT91_MCI_TRTYP_STREAM; | |
be0192aa | 485 | if (data->blocks > 1) |
65dbf343 AV |
486 | cmdr |= AT91_MCI_TRTYP_MULTIPLE; |
487 | } | |
488 | else { | |
489 | block_length = 0; | |
490 | blocks = 0; | |
491 | } | |
492 | ||
b6cedb38 | 493 | if (host->flags & FL_SENT_STOP) |
65dbf343 AV |
494 | cmdr |= AT91_MCI_TRCMD_STOP; |
495 | ||
496 | if (host->bus_mode == MMC_BUSMODE_OPENDRAIN) | |
497 | cmdr |= AT91_MCI_OPDCMD; | |
498 | ||
499 | /* | |
500 | * Set the arguments and send the command | |
501 | */ | |
f3a8efa9 | 502 | pr_debug("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n", |
e0b19b83 | 503 | cmd->opcode, cmdr, cmd->arg, blocks, block_length, at91_mci_read(host, AT91_MCI_MR)); |
65dbf343 AV |
504 | |
505 | if (!data) { | |
93a3ddc2 AV |
506 | at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS | ATMEL_PDC_RXTDIS); |
507 | at91_mci_write(host, ATMEL_PDC_RPR, 0); | |
508 | at91_mci_write(host, ATMEL_PDC_RCR, 0); | |
509 | at91_mci_write(host, ATMEL_PDC_RNPR, 0); | |
510 | at91_mci_write(host, ATMEL_PDC_RNCR, 0); | |
511 | at91_mci_write(host, ATMEL_PDC_TPR, 0); | |
512 | at91_mci_write(host, ATMEL_PDC_TCR, 0); | |
513 | at91_mci_write(host, ATMEL_PDC_TNPR, 0); | |
514 | at91_mci_write(host, ATMEL_PDC_TNCR, 0); | |
ed99c541 NF |
515 | ier = AT91_MCI_CMDRDY; |
516 | } else { | |
517 | /* zero block length and PDC mode */ | |
12bd2575 | 518 | mr = at91_mci_read(host, AT91_MCI_MR) & 0x5fff; |
80f92546 MP |
519 | mr |= (data->blksz & 0x3) ? AT91_MCI_PDCFBYTE : 0; |
520 | mr |= (block_length << 16); | |
521 | mr |= AT91_MCI_PDCMODE; | |
522 | at91_mci_write(host, AT91_MCI_MR, mr); | |
e0b19b83 | 523 | |
9da3cbaf | 524 | if (!(cpu_is_at91rm9200() || cpu_is_at91sam9261())) |
c5a89c6c MP |
525 | at91_mci_write(host, AT91_MCI_BLKR, |
526 | AT91_MCI_BLKR_BCNT(blocks) | | |
527 | AT91_MCI_BLKR_BLKLEN(block_length)); | |
528 | ||
ed99c541 NF |
529 | /* |
530 | * Disable the PDC controller | |
531 | */ | |
532 | at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); | |
65dbf343 | 533 | |
ed99c541 NF |
534 | if (cmdr & AT91_MCI_TRCMD_START) { |
535 | data->bytes_xfered = 0; | |
536 | host->transfer_index = 0; | |
537 | host->in_use_index = 0; | |
538 | if (cmdr & AT91_MCI_TRDIR) { | |
539 | /* | |
540 | * Handle a read | |
541 | */ | |
ed99c541 NF |
542 | host->total_length = 0; |
543 | ||
86ee26f5 WM |
544 | at91_mci_write(host, ATMEL_PDC_RPR, host->physical_address); |
545 | at91_mci_write(host, ATMEL_PDC_RCR, (data->blksz & 0x3) ? | |
546 | (blocks * block_length) : (blocks * block_length) / 4); | |
547 | at91_mci_write(host, ATMEL_PDC_RNPR, 0); | |
548 | at91_mci_write(host, ATMEL_PDC_RNCR, 0); | |
549 | ||
ed99c541 NF |
550 | ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */; |
551 | } | |
552 | else { | |
553 | /* | |
554 | * Handle a write | |
555 | */ | |
556 | host->total_length = block_length * blocks; | |
5385edc5 VS |
557 | /* |
558 | * AT91SAM926[0/3] Data Write Operation and | |
559 | * number of bytes erratum | |
560 | */ | |
561 | if (cpu_is_at91sam9260 () || cpu_is_at91sam9263()) | |
562 | if (host->total_length < 12) | |
563 | host->total_length = 12; | |
e385ea63 | 564 | |
ed99c541 NF |
565 | at91_mci_sg_to_dma(host, data); |
566 | ||
567 | pr_debug("Transmitting %d bytes\n", host->total_length); | |
568 | ||
569 | at91_mci_write(host, ATMEL_PDC_TPR, host->physical_address); | |
80f92546 MP |
570 | at91_mci_write(host, ATMEL_PDC_TCR, (data->blksz & 0x3) ? |
571 | host->total_length : host->total_length / 4); | |
572 | ||
ed99c541 NF |
573 | ier = AT91_MCI_CMDRDY; |
574 | } | |
65dbf343 AV |
575 | } |
576 | } | |
577 | ||
578 | /* | |
579 | * Send the command and then enable the PDC - not the other way round as | |
580 | * the data sheet says | |
581 | */ | |
582 | ||
e0b19b83 AV |
583 | at91_mci_write(host, AT91_MCI_ARGR, cmd->arg); |
584 | at91_mci_write(host, AT91_MCI_CMDR, cmdr); | |
65dbf343 AV |
585 | |
586 | if (cmdr & AT91_MCI_TRCMD_START) { | |
587 | if (cmdr & AT91_MCI_TRDIR) | |
93a3ddc2 | 588 | at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN); |
65dbf343 | 589 | } |
65dbf343 | 590 | |
ed99c541 | 591 | /* Enable selected interrupts */ |
df05a303 | 592 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_ERRORS | ier); |
65dbf343 AV |
593 | } |
594 | ||
595 | /* | |
596 | * Process the next step in the request | |
597 | */ | |
e8d04d3d | 598 | static void at91_mci_process_next(struct at91mci_host *host) |
65dbf343 AV |
599 | { |
600 | if (!(host->flags & FL_SENT_COMMAND)) { | |
601 | host->flags |= FL_SENT_COMMAND; | |
ed99c541 | 602 | at91_mci_send_command(host, host->request->cmd); |
65dbf343 AV |
603 | } |
604 | else if ((!(host->flags & FL_SENT_STOP)) && host->request->stop) { | |
605 | host->flags |= FL_SENT_STOP; | |
ed99c541 | 606 | at91_mci_send_command(host, host->request->stop); |
e181dce8 MP |
607 | } else { |
608 | del_timer(&host->timer); | |
c5a89c6c MP |
609 | /* the at91rm9200 mci controller hangs after some transfers, |
610 | * and the workaround is to reset it after each transfer. | |
611 | */ | |
612 | if (cpu_is_at91rm9200()) | |
613 | at91_reset_host(host); | |
65dbf343 | 614 | mmc_request_done(host->mmc, host->request); |
e181dce8 | 615 | } |
65dbf343 AV |
616 | } |
617 | ||
618 | /* | |
619 | * Handle a command that has been completed | |
620 | */ | |
ba7deeed | 621 | static void at91_mci_completed_command(struct at91mci_host *host, unsigned int status) |
65dbf343 AV |
622 | { |
623 | struct mmc_command *cmd = host->cmd; | |
fa1fe010 | 624 | struct mmc_data *data = cmd->data; |
65dbf343 | 625 | |
7a6588ba | 626 | at91_mci_write(host, AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); |
65dbf343 | 627 | |
e0b19b83 AV |
628 | cmd->resp[0] = at91_mci_read(host, AT91_MCI_RSPR(0)); |
629 | cmd->resp[1] = at91_mci_read(host, AT91_MCI_RSPR(1)); | |
630 | cmd->resp[2] = at91_mci_read(host, AT91_MCI_RSPR(2)); | |
631 | cmd->resp[3] = at91_mci_read(host, AT91_MCI_RSPR(3)); | |
65dbf343 | 632 | |
ba7deeed NF |
633 | pr_debug("Status = %08X/%08x [%08X %08X %08X %08X]\n", |
634 | status, at91_mci_read(host, AT91_MCI_SR), | |
635 | cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); | |
65dbf343 | 636 | |
9e3866b5 | 637 | if (status & AT91_MCI_ERRORS) { |
b6cedb38 | 638 | if ((status & AT91_MCI_RCRCE) && !(mmc_resp_type(cmd) & MMC_RSP_CRC)) { |
17b0429d | 639 | cmd->error = 0; |
65dbf343 AV |
640 | } |
641 | else { | |
fa1fe010 NF |
642 | if (status & (AT91_MCI_DTOE | AT91_MCI_DCRCE)) { |
643 | if (data) { | |
644 | if (status & AT91_MCI_DTOE) | |
645 | data->error = -ETIMEDOUT; | |
646 | else if (status & AT91_MCI_DCRCE) | |
647 | data->error = -EILSEQ; | |
648 | } | |
649 | } else { | |
650 | if (status & AT91_MCI_RTOE) | |
651 | cmd->error = -ETIMEDOUT; | |
652 | else if (status & AT91_MCI_RCRCE) | |
653 | cmd->error = -EILSEQ; | |
654 | else | |
655 | cmd->error = -EIO; | |
656 | } | |
65dbf343 | 657 | |
fa1fe010 NF |
658 | pr_debug("Error detected and set to %d/%d (cmd = %d, retries = %d)\n", |
659 | cmd->error, data ? data->error : 0, | |
660 | cmd->opcode, cmd->retries); | |
65dbf343 AV |
661 | } |
662 | } | |
663 | else | |
17b0429d | 664 | cmd->error = 0; |
65dbf343 | 665 | |
e8d04d3d | 666 | at91_mci_process_next(host); |
65dbf343 AV |
667 | } |
668 | ||
669 | /* | |
670 | * Handle an MMC request | |
671 | */ | |
672 | static void at91_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
673 | { | |
674 | struct at91mci_host *host = mmc_priv(mmc); | |
675 | host->request = mrq; | |
676 | host->flags = 0; | |
677 | ||
a04ac5b9 WM |
678 | /* more than 1s timeout needed with slow SD cards */ |
679 | mod_timer(&host->timer, jiffies + msecs_to_jiffies(2000)); | |
e181dce8 | 680 | |
e8d04d3d | 681 | at91_mci_process_next(host); |
65dbf343 AV |
682 | } |
683 | ||
684 | /* | |
685 | * Set the IOS | |
686 | */ | |
687 | static void at91_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
688 | { | |
689 | int clkdiv; | |
690 | struct at91mci_host *host = mmc_priv(mmc); | |
3dd3b039 | 691 | unsigned long at91_master_clock = clk_get_rate(host->mci_clk); |
65dbf343 | 692 | |
b44fb7a0 | 693 | host->bus_mode = ios->bus_mode; |
65dbf343 AV |
694 | |
695 | if (ios->clock == 0) { | |
696 | /* Disable the MCI controller */ | |
e0b19b83 | 697 | at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS); |
65dbf343 AV |
698 | clkdiv = 0; |
699 | } | |
700 | else { | |
701 | /* Enable the MCI controller */ | |
e0b19b83 | 702 | at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN); |
65dbf343 AV |
703 | |
704 | if ((at91_master_clock % (ios->clock * 2)) == 0) | |
705 | clkdiv = ((at91_master_clock / ios->clock) / 2) - 1; | |
706 | else | |
707 | clkdiv = (at91_master_clock / ios->clock) / 2; | |
708 | ||
b44fb7a0 | 709 | pr_debug("clkdiv = %d. mcck = %ld\n", clkdiv, |
65dbf343 AV |
710 | at91_master_clock / (2 * (clkdiv + 1))); |
711 | } | |
712 | if (ios->bus_width == MMC_BUS_WIDTH_4 && host->board->wire4) { | |
b44fb7a0 | 713 | pr_debug("MMC: Setting controller bus width to 4\n"); |
e0b19b83 | 714 | at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) | AT91_MCI_SDCBUS); |
65dbf343 AV |
715 | } |
716 | else { | |
b44fb7a0 | 717 | pr_debug("MMC: Setting controller bus width to 1\n"); |
e0b19b83 | 718 | at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS); |
65dbf343 AV |
719 | } |
720 | ||
721 | /* Set the clock divider */ | |
e0b19b83 | 722 | at91_mci_write(host, AT91_MCI_MR, (at91_mci_read(host, AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv); |
65dbf343 AV |
723 | |
724 | /* maybe switch power to the card */ | |
b44fb7a0 | 725 | if (host->board->vcc_pin) { |
65dbf343 AV |
726 | switch (ios->power_mode) { |
727 | case MMC_POWER_OFF: | |
6e996ee8 | 728 | gpio_set_value(host->board->vcc_pin, 0); |
65dbf343 AV |
729 | break; |
730 | case MMC_POWER_UP: | |
6e996ee8 | 731 | gpio_set_value(host->board->vcc_pin, 1); |
65dbf343 | 732 | break; |
e5c0ef90 MP |
733 | case MMC_POWER_ON: |
734 | break; | |
735 | default: | |
736 | WARN_ON(1); | |
65dbf343 AV |
737 | } |
738 | } | |
739 | } | |
740 | ||
741 | /* | |
742 | * Handle an interrupt | |
743 | */ | |
7d12e780 | 744 | static irqreturn_t at91_mci_irq(int irq, void *devid) |
65dbf343 AV |
745 | { |
746 | struct at91mci_host *host = devid; | |
747 | int completed = 0; | |
df05a303 | 748 | unsigned int int_status, int_mask; |
65dbf343 | 749 | |
e0b19b83 | 750 | int_status = at91_mci_read(host, AT91_MCI_SR); |
df05a303 | 751 | int_mask = at91_mci_read(host, AT91_MCI_IMR); |
37b758e8 | 752 | |
f3a8efa9 | 753 | pr_debug("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask, |
df05a303 | 754 | int_status & int_mask); |
37b758e8 | 755 | |
df05a303 AV |
756 | int_status = int_status & int_mask; |
757 | ||
758 | if (int_status & AT91_MCI_ERRORS) { | |
65dbf343 | 759 | completed = 1; |
37b758e8 | 760 | |
df05a303 AV |
761 | if (int_status & AT91_MCI_UNRE) |
762 | pr_debug("MMC: Underrun error\n"); | |
763 | if (int_status & AT91_MCI_OVRE) | |
764 | pr_debug("MMC: Overrun error\n"); | |
765 | if (int_status & AT91_MCI_DTOE) | |
766 | pr_debug("MMC: Data timeout\n"); | |
767 | if (int_status & AT91_MCI_DCRCE) | |
768 | pr_debug("MMC: CRC error in data\n"); | |
769 | if (int_status & AT91_MCI_RTOE) | |
770 | pr_debug("MMC: Response timeout\n"); | |
771 | if (int_status & AT91_MCI_RENDE) | |
772 | pr_debug("MMC: Response end bit error\n"); | |
773 | if (int_status & AT91_MCI_RCRCE) | |
774 | pr_debug("MMC: Response CRC error\n"); | |
775 | if (int_status & AT91_MCI_RDIRE) | |
776 | pr_debug("MMC: Response direction error\n"); | |
777 | if (int_status & AT91_MCI_RINDE) | |
778 | pr_debug("MMC: Response index error\n"); | |
779 | } else { | |
780 | /* Only continue processing if no errors */ | |
65dbf343 | 781 | |
65dbf343 | 782 | if (int_status & AT91_MCI_TXBUFE) { |
b44fb7a0 | 783 | pr_debug("TX buffer empty\n"); |
65dbf343 AV |
784 | at91_mci_handle_transmitted(host); |
785 | } | |
786 | ||
ed99c541 NF |
787 | if (int_status & AT91_MCI_ENDRX) { |
788 | pr_debug("ENDRX\n"); | |
789 | at91_mci_post_dma_read(host); | |
790 | } | |
791 | ||
65dbf343 | 792 | if (int_status & AT91_MCI_RXBUFF) { |
b44fb7a0 | 793 | pr_debug("RX buffer full\n"); |
ed99c541 NF |
794 | at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); |
795 | at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_RXBUFF | AT91_MCI_ENDRX); | |
796 | completed = 1; | |
65dbf343 AV |
797 | } |
798 | ||
df05a303 | 799 | if (int_status & AT91_MCI_ENDTX) |
b44fb7a0 | 800 | pr_debug("Transmit has ended\n"); |
65dbf343 | 801 | |
65dbf343 | 802 | if (int_status & AT91_MCI_NOTBUSY) { |
b44fb7a0 | 803 | pr_debug("Card is ready\n"); |
4ac24a87 | 804 | at91_mci_update_bytes_xfered(host); |
ed99c541 | 805 | completed = 1; |
65dbf343 AV |
806 | } |
807 | ||
df05a303 | 808 | if (int_status & AT91_MCI_DTIP) |
b44fb7a0 | 809 | pr_debug("Data transfer in progress\n"); |
65dbf343 | 810 | |
ed99c541 | 811 | if (int_status & AT91_MCI_BLKE) { |
b44fb7a0 | 812 | pr_debug("Block transfer has ended\n"); |
4ac24a87 NF |
813 | if (host->request->data && host->request->data->blocks > 1) { |
814 | /* multi block write : complete multi write | |
815 | * command and send stop */ | |
816 | completed = 1; | |
817 | } else { | |
818 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY); | |
819 | } | |
ed99c541 | 820 | } |
65dbf343 | 821 | |
7a6588ba EB |
822 | if (int_status & AT91_MCI_SDIOIRQA) |
823 | mmc_signal_sdio_irq(host->mmc); | |
824 | ||
825 | if (int_status & AT91_MCI_SDIOIRQB) | |
826 | mmc_signal_sdio_irq(host->mmc); | |
827 | ||
df05a303 | 828 | if (int_status & AT91_MCI_TXRDY) |
b44fb7a0 | 829 | pr_debug("Ready to transmit\n"); |
65dbf343 | 830 | |
df05a303 | 831 | if (int_status & AT91_MCI_RXRDY) |
b44fb7a0 | 832 | pr_debug("Ready to receive\n"); |
65dbf343 AV |
833 | |
834 | if (int_status & AT91_MCI_CMDRDY) { | |
b44fb7a0 | 835 | pr_debug("Command ready\n"); |
ed99c541 | 836 | completed = at91_mci_handle_cmdrdy(host); |
65dbf343 AV |
837 | } |
838 | } | |
65dbf343 AV |
839 | |
840 | if (completed) { | |
b44fb7a0 | 841 | pr_debug("Completed command\n"); |
7a6588ba | 842 | at91_mci_write(host, AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); |
ba7deeed | 843 | at91_mci_completed_command(host, int_status); |
df05a303 | 844 | } else |
7a6588ba | 845 | at91_mci_write(host, AT91_MCI_IDR, int_status & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); |
65dbf343 AV |
846 | |
847 | return IRQ_HANDLED; | |
848 | } | |
849 | ||
7d12e780 | 850 | static irqreturn_t at91_mmc_det_irq(int irq, void *_host) |
65dbf343 AV |
851 | { |
852 | struct at91mci_host *host = _host; | |
6e996ee8 | 853 | int present = !gpio_get_value(irq_to_gpio(irq)); |
65dbf343 AV |
854 | |
855 | /* | |
856 | * we expect this irq on both insert and remove, | |
857 | * and use a short delay to debounce. | |
858 | */ | |
859 | if (present != host->present) { | |
860 | host->present = present; | |
b44fb7a0 | 861 | pr_debug("%s: card %s\n", mmc_hostname(host->mmc), |
65dbf343 AV |
862 | present ? "insert" : "remove"); |
863 | if (!present) { | |
b44fb7a0 | 864 | pr_debug("****** Resetting SD-card bus width ******\n"); |
99eeb8df | 865 | at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS); |
65dbf343 | 866 | } |
a04ac5b9 WM |
867 | /* 0.5s needed because of early card detect switch firing */ |
868 | mmc_detect_change(host->mmc, msecs_to_jiffies(500)); | |
65dbf343 AV |
869 | } |
870 | return IRQ_HANDLED; | |
871 | } | |
872 | ||
a26b498c | 873 | static int at91_mci_get_ro(struct mmc_host *mmc) |
65dbf343 | 874 | { |
65dbf343 AV |
875 | struct at91mci_host *host = mmc_priv(mmc); |
876 | ||
08f80bb5 AV |
877 | if (host->board->wp_pin) |
878 | return !!gpio_get_value(host->board->wp_pin); | |
879 | /* | |
880 | * Board doesn't support read only detection; let the mmc core | |
881 | * decide what to do. | |
882 | */ | |
883 | return -ENOSYS; | |
65dbf343 AV |
884 | } |
885 | ||
7a6588ba EB |
886 | static void at91_mci_enable_sdio_irq(struct mmc_host *mmc, int enable) |
887 | { | |
888 | struct at91mci_host *host = mmc_priv(mmc); | |
889 | ||
890 | pr_debug("%s: sdio_irq %c : %s\n", mmc_hostname(host->mmc), | |
891 | host->board->slot_b ? 'B':'A', enable ? "enable" : "disable"); | |
892 | at91_mci_write(host, enable ? AT91_MCI_IER : AT91_MCI_IDR, | |
893 | host->board->slot_b ? AT91_MCI_SDIOIRQB : AT91_MCI_SDIOIRQA); | |
894 | ||
895 | } | |
896 | ||
ab7aefd0 | 897 | static const struct mmc_host_ops at91_mci_ops = { |
65dbf343 AV |
898 | .request = at91_mci_request, |
899 | .set_ios = at91_mci_set_ios, | |
900 | .get_ro = at91_mci_get_ro, | |
7a6588ba | 901 | .enable_sdio_irq = at91_mci_enable_sdio_irq, |
65dbf343 AV |
902 | }; |
903 | ||
904 | /* | |
905 | * Probe for the device | |
906 | */ | |
a26b498c | 907 | static int __init at91_mci_probe(struct platform_device *pdev) |
65dbf343 AV |
908 | { |
909 | struct mmc_host *mmc; | |
910 | struct at91mci_host *host; | |
17ea0595 | 911 | struct resource *res; |
65dbf343 AV |
912 | int ret; |
913 | ||
17ea0595 AV |
914 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
915 | if (!res) | |
916 | return -ENXIO; | |
917 | ||
918 | if (!request_mem_region(res->start, res->end - res->start + 1, DRIVER_NAME)) | |
919 | return -EBUSY; | |
920 | ||
65dbf343 AV |
921 | mmc = mmc_alloc_host(sizeof(struct at91mci_host), &pdev->dev); |
922 | if (!mmc) { | |
6e996ee8 DB |
923 | ret = -ENOMEM; |
924 | dev_dbg(&pdev->dev, "couldn't allocate mmc host\n"); | |
925 | goto fail6; | |
65dbf343 AV |
926 | } |
927 | ||
928 | mmc->ops = &at91_mci_ops; | |
929 | mmc->f_min = 375000; | |
930 | mmc->f_max = 25000000; | |
931 | mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; | |
23af6039 | 932 | mmc->caps = MMC_CAP_SDIO_IRQ; |
65dbf343 | 933 | |
3780d906 WM |
934 | mmc->max_blk_size = MCI_MAXBLKSIZE; |
935 | mmc->max_blk_count = MCI_BLKATONCE; | |
936 | mmc->max_req_size = MCI_BUFSIZE; | |
fe4a3c7a | 937 | |
65dbf343 AV |
938 | host = mmc_priv(mmc); |
939 | host->mmc = mmc; | |
65dbf343 AV |
940 | host->bus_mode = 0; |
941 | host->board = pdev->dev.platform_data; | |
942 | if (host->board->wire4) { | |
ed99c541 NF |
943 | if (cpu_is_at91sam9260() || cpu_is_at91sam9263()) |
944 | mmc->caps |= MMC_CAP_4_BIT_DATA; | |
945 | else | |
6e996ee8 | 946 | dev_warn(&pdev->dev, "4 wire bus mode not supported" |
ed99c541 | 947 | " - using 1 wire\n"); |
65dbf343 AV |
948 | } |
949 | ||
3780d906 WM |
950 | host->buffer = dma_alloc_coherent(&pdev->dev, MCI_BUFSIZE, |
951 | &host->physical_address, GFP_KERNEL); | |
952 | if (!host->buffer) { | |
953 | ret = -ENOMEM; | |
954 | dev_err(&pdev->dev, "Can't allocate transmit buffer\n"); | |
955 | goto fail5; | |
956 | } | |
957 | ||
6e996ee8 DB |
958 | /* |
959 | * Reserve GPIOs ... board init code makes sure these pins are set | |
960 | * up as GPIOs with the right direction (input, except for vcc) | |
961 | */ | |
962 | if (host->board->det_pin) { | |
963 | ret = gpio_request(host->board->det_pin, "mmc_detect"); | |
964 | if (ret < 0) { | |
965 | dev_dbg(&pdev->dev, "couldn't claim card detect pin\n"); | |
3780d906 | 966 | goto fail4b; |
6e996ee8 DB |
967 | } |
968 | } | |
969 | if (host->board->wp_pin) { | |
970 | ret = gpio_request(host->board->wp_pin, "mmc_wp"); | |
971 | if (ret < 0) { | |
972 | dev_dbg(&pdev->dev, "couldn't claim wp sense pin\n"); | |
973 | goto fail4; | |
974 | } | |
975 | } | |
976 | if (host->board->vcc_pin) { | |
977 | ret = gpio_request(host->board->vcc_pin, "mmc_vcc"); | |
978 | if (ret < 0) { | |
979 | dev_dbg(&pdev->dev, "couldn't claim vcc switch pin\n"); | |
980 | goto fail3; | |
981 | } | |
982 | } | |
983 | ||
65dbf343 AV |
984 | /* |
985 | * Get Clock | |
986 | */ | |
3dd3b039 AV |
987 | host->mci_clk = clk_get(&pdev->dev, "mci_clk"); |
988 | if (IS_ERR(host->mci_clk)) { | |
6e996ee8 DB |
989 | ret = -ENODEV; |
990 | dev_dbg(&pdev->dev, "no mci_clk?\n"); | |
991 | goto fail2; | |
65dbf343 | 992 | } |
65dbf343 | 993 | |
17ea0595 AV |
994 | /* |
995 | * Map I/O region | |
996 | */ | |
997 | host->baseaddr = ioremap(res->start, res->end - res->start + 1); | |
998 | if (!host->baseaddr) { | |
6e996ee8 DB |
999 | ret = -ENOMEM; |
1000 | goto fail1; | |
17ea0595 | 1001 | } |
e0b19b83 AV |
1002 | |
1003 | /* | |
1004 | * Reset hardware | |
1005 | */ | |
3dd3b039 | 1006 | clk_enable(host->mci_clk); /* Enable the peripheral clock */ |
e0b19b83 AV |
1007 | at91_mci_disable(host); |
1008 | at91_mci_enable(host); | |
1009 | ||
65dbf343 AV |
1010 | /* |
1011 | * Allocate the MCI interrupt | |
1012 | */ | |
17ea0595 | 1013 | host->irq = platform_get_irq(pdev, 0); |
6e996ee8 DB |
1014 | ret = request_irq(host->irq, at91_mci_irq, IRQF_SHARED, |
1015 | mmc_hostname(mmc), host); | |
65dbf343 | 1016 | if (ret) { |
6e996ee8 DB |
1017 | dev_dbg(&pdev->dev, "request MCI interrupt failed\n"); |
1018 | goto fail0; | |
65dbf343 AV |
1019 | } |
1020 | ||
99ba0405 NF |
1021 | setup_timer(&host->timer, at91_timeout_timer, (unsigned long)host); |
1022 | ||
65dbf343 AV |
1023 | platform_set_drvdata(pdev, mmc); |
1024 | ||
1025 | /* | |
1026 | * Add host to MMC layer | |
1027 | */ | |
63b66438 | 1028 | if (host->board->det_pin) { |
6e996ee8 | 1029 | host->present = !gpio_get_value(host->board->det_pin); |
63b66438 | 1030 | } |
65dbf343 AV |
1031 | else |
1032 | host->present = -1; | |
1033 | ||
1034 | mmc_add_host(mmc); | |
1035 | ||
1036 | /* | |
1037 | * monitor card insertion/removal if we can | |
1038 | */ | |
1039 | if (host->board->det_pin) { | |
6e996ee8 DB |
1040 | ret = request_irq(gpio_to_irq(host->board->det_pin), |
1041 | at91_mmc_det_irq, 0, mmc_hostname(mmc), host); | |
65dbf343 | 1042 | if (ret) |
6e996ee8 DB |
1043 | dev_warn(&pdev->dev, "request MMC detect irq failed\n"); |
1044 | else | |
1045 | device_init_wakeup(&pdev->dev, 1); | |
65dbf343 AV |
1046 | } |
1047 | ||
f3a8efa9 | 1048 | pr_debug("Added MCI driver\n"); |
65dbf343 AV |
1049 | |
1050 | return 0; | |
6e996ee8 DB |
1051 | |
1052 | fail0: | |
1053 | clk_disable(host->mci_clk); | |
1054 | iounmap(host->baseaddr); | |
1055 | fail1: | |
1056 | clk_put(host->mci_clk); | |
1057 | fail2: | |
1058 | if (host->board->vcc_pin) | |
1059 | gpio_free(host->board->vcc_pin); | |
1060 | fail3: | |
1061 | if (host->board->wp_pin) | |
1062 | gpio_free(host->board->wp_pin); | |
1063 | fail4: | |
1064 | if (host->board->det_pin) | |
1065 | gpio_free(host->board->det_pin); | |
3780d906 WM |
1066 | fail4b: |
1067 | if (host->buffer) | |
1068 | dma_free_coherent(&pdev->dev, MCI_BUFSIZE, | |
1069 | host->buffer, host->physical_address); | |
6e996ee8 DB |
1070 | fail5: |
1071 | mmc_free_host(mmc); | |
1072 | fail6: | |
1073 | release_mem_region(res->start, res->end - res->start + 1); | |
1074 | dev_err(&pdev->dev, "probe failed, err %d\n", ret); | |
1075 | return ret; | |
65dbf343 AV |
1076 | } |
1077 | ||
1078 | /* | |
1079 | * Remove a device | |
1080 | */ | |
a26b498c | 1081 | static int __exit at91_mci_remove(struct platform_device *pdev) |
65dbf343 AV |
1082 | { |
1083 | struct mmc_host *mmc = platform_get_drvdata(pdev); | |
1084 | struct at91mci_host *host; | |
17ea0595 | 1085 | struct resource *res; |
65dbf343 AV |
1086 | |
1087 | if (!mmc) | |
1088 | return -1; | |
1089 | ||
1090 | host = mmc_priv(mmc); | |
1091 | ||
3780d906 WM |
1092 | if (host->buffer) |
1093 | dma_free_coherent(&pdev->dev, MCI_BUFSIZE, | |
1094 | host->buffer, host->physical_address); | |
1095 | ||
e0cda54e | 1096 | if (host->board->det_pin) { |
6e996ee8 DB |
1097 | if (device_can_wakeup(&pdev->dev)) |
1098 | free_irq(gpio_to_irq(host->board->det_pin), host); | |
63b66438 | 1099 | device_init_wakeup(&pdev->dev, 0); |
6e996ee8 | 1100 | gpio_free(host->board->det_pin); |
65dbf343 AV |
1101 | } |
1102 | ||
e0b19b83 | 1103 | at91_mci_disable(host); |
e181dce8 | 1104 | del_timer_sync(&host->timer); |
17ea0595 AV |
1105 | mmc_remove_host(mmc); |
1106 | free_irq(host->irq, host); | |
65dbf343 | 1107 | |
3dd3b039 AV |
1108 | clk_disable(host->mci_clk); /* Disable the peripheral clock */ |
1109 | clk_put(host->mci_clk); | |
65dbf343 | 1110 | |
6e996ee8 DB |
1111 | if (host->board->vcc_pin) |
1112 | gpio_free(host->board->vcc_pin); | |
1113 | if (host->board->wp_pin) | |
1114 | gpio_free(host->board->wp_pin); | |
1115 | ||
17ea0595 AV |
1116 | iounmap(host->baseaddr); |
1117 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1118 | release_mem_region(res->start, res->end - res->start + 1); | |
65dbf343 | 1119 | |
17ea0595 AV |
1120 | mmc_free_host(mmc); |
1121 | platform_set_drvdata(pdev, NULL); | |
b44fb7a0 | 1122 | pr_debug("MCI Removed\n"); |
65dbf343 AV |
1123 | |
1124 | return 0; | |
1125 | } | |
1126 | ||
1127 | #ifdef CONFIG_PM | |
1128 | static int at91_mci_suspend(struct platform_device *pdev, pm_message_t state) | |
1129 | { | |
1130 | struct mmc_host *mmc = platform_get_drvdata(pdev); | |
63b66438 | 1131 | struct at91mci_host *host = mmc_priv(mmc); |
65dbf343 AV |
1132 | int ret = 0; |
1133 | ||
e0cda54e | 1134 | if (host->board->det_pin && device_may_wakeup(&pdev->dev)) |
63b66438 MP |
1135 | enable_irq_wake(host->board->det_pin); |
1136 | ||
65dbf343 AV |
1137 | if (mmc) |
1138 | ret = mmc_suspend_host(mmc, state); | |
1139 | ||
1140 | return ret; | |
1141 | } | |
1142 | ||
1143 | static int at91_mci_resume(struct platform_device *pdev) | |
1144 | { | |
1145 | struct mmc_host *mmc = platform_get_drvdata(pdev); | |
63b66438 | 1146 | struct at91mci_host *host = mmc_priv(mmc); |
65dbf343 AV |
1147 | int ret = 0; |
1148 | ||
e0cda54e | 1149 | if (host->board->det_pin && device_may_wakeup(&pdev->dev)) |
63b66438 MP |
1150 | disable_irq_wake(host->board->det_pin); |
1151 | ||
65dbf343 AV |
1152 | if (mmc) |
1153 | ret = mmc_resume_host(mmc); | |
1154 | ||
1155 | return ret; | |
1156 | } | |
1157 | #else | |
1158 | #define at91_mci_suspend NULL | |
1159 | #define at91_mci_resume NULL | |
1160 | #endif | |
1161 | ||
1162 | static struct platform_driver at91_mci_driver = { | |
a26b498c | 1163 | .remove = __exit_p(at91_mci_remove), |
65dbf343 AV |
1164 | .suspend = at91_mci_suspend, |
1165 | .resume = at91_mci_resume, | |
1166 | .driver = { | |
1167 | .name = DRIVER_NAME, | |
1168 | .owner = THIS_MODULE, | |
1169 | }, | |
1170 | }; | |
1171 | ||
1172 | static int __init at91_mci_init(void) | |
1173 | { | |
a26b498c | 1174 | return platform_driver_probe(&at91_mci_driver, at91_mci_probe); |
65dbf343 AV |
1175 | } |
1176 | ||
1177 | static void __exit at91_mci_exit(void) | |
1178 | { | |
1179 | platform_driver_unregister(&at91_mci_driver); | |
1180 | } | |
1181 | ||
1182 | module_init(at91_mci_init); | |
1183 | module_exit(at91_mci_exit); | |
1184 | ||
1185 | MODULE_DESCRIPTION("AT91 Multimedia Card Interface driver"); | |
1186 | MODULE_AUTHOR("Nick Randell"); | |
1187 | MODULE_LICENSE("GPL"); | |
bc65c724 | 1188 | MODULE_ALIAS("platform:at91_mci"); |