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65dbf343 | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/at91_mci.c - ATMEL AT91 MCI Driver |
65dbf343 AV |
3 | * |
4 | * Copyright (C) 2005 Cougar Creek Computing Devices Ltd, All Rights Reserved | |
5 | * | |
6 | * Copyright (C) 2006 Malcolm Noyes | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | /* | |
99eeb8df | 14 | This is the AT91 MCI driver that has been tested with both MMC cards |
65dbf343 AV |
15 | and SD-cards. Boards that support write protect are now supported. |
16 | The CCAT91SBC001 board does not support SD cards. | |
17 | ||
18 | The three entry points are at91_mci_request, at91_mci_set_ios | |
19 | and at91_mci_get_ro. | |
20 | ||
21 | SET IOS | |
22 | This configures the device to put it into the correct mode and clock speed | |
23 | required. | |
24 | ||
25 | MCI REQUEST | |
26 | MCI request processes the commands sent in the mmc_request structure. This | |
27 | can consist of a processing command and a stop command in the case of | |
28 | multiple block transfers. | |
29 | ||
30 | There are three main types of request, commands, reads and writes. | |
31 | ||
32 | Commands are straight forward. The command is submitted to the controller and | |
33 | the request function returns. When the controller generates an interrupt to indicate | |
34 | the command is finished, the response to the command are read and the mmc_request_done | |
35 | function called to end the request. | |
36 | ||
37 | Reads and writes work in a similar manner to normal commands but involve the PDC (DMA) | |
38 | controller to manage the transfers. | |
39 | ||
40 | A read is done from the controller directly to the scatterlist passed in from the request. | |
99eeb8df AV |
41 | Due to a bug in the AT91RM9200 controller, when a read is completed, all the words are byte |
42 | swapped in the scatterlist buffers. AT91SAM926x are not affected by this bug. | |
65dbf343 AV |
43 | |
44 | The sequence of read interrupts is: ENDRX, RXBUFF, CMDRDY | |
45 | ||
46 | A write is slightly different in that the bytes to write are read from the scatterlist | |
47 | into a dma memory buffer (this is in case the source buffer should be read only). The | |
48 | entire write buffer is then done from this single dma memory buffer. | |
49 | ||
50 | The sequence of write interrupts is: ENDTX, TXBUFE, NOTBUSY, CMDRDY | |
51 | ||
52 | GET RO | |
53 | Gets the status of the write protect pin, if available. | |
54 | */ | |
55 | ||
65dbf343 AV |
56 | #include <linux/module.h> |
57 | #include <linux/moduleparam.h> | |
58 | #include <linux/init.h> | |
59 | #include <linux/ioport.h> | |
60 | #include <linux/platform_device.h> | |
61 | #include <linux/interrupt.h> | |
62 | #include <linux/blkdev.h> | |
63 | #include <linux/delay.h> | |
64 | #include <linux/err.h> | |
65 | #include <linux/dma-mapping.h> | |
66 | #include <linux/clk.h> | |
93a3ddc2 | 67 | #include <linux/atmel_pdc.h> |
65dbf343 AV |
68 | |
69 | #include <linux/mmc/host.h> | |
65dbf343 AV |
70 | |
71 | #include <asm/io.h> | |
72 | #include <asm/irq.h> | |
6e996ee8 DB |
73 | #include <asm/gpio.h> |
74 | ||
a09e64fb RK |
75 | #include <mach/board.h> |
76 | #include <mach/cpu.h> | |
77 | #include <mach/at91_mci.h> | |
65dbf343 AV |
78 | |
79 | #define DRIVER_NAME "at91_mci" | |
80 | ||
df05a303 AV |
81 | #define FL_SENT_COMMAND (1 << 0) |
82 | #define FL_SENT_STOP (1 << 1) | |
65dbf343 | 83 | |
df05a303 AV |
84 | #define AT91_MCI_ERRORS (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE \ |
85 | | AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE \ | |
37b758e8 | 86 | | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE) |
65dbf343 | 87 | |
e0b19b83 AV |
88 | #define at91_mci_read(host, reg) __raw_readl((host)->baseaddr + (reg)) |
89 | #define at91_mci_write(host, reg, val) __raw_writel((val), (host)->baseaddr + (reg)) | |
65dbf343 | 90 | |
65dbf343 AV |
91 | |
92 | /* | |
93 | * Low level type for this driver | |
94 | */ | |
95 | struct at91mci_host | |
96 | { | |
97 | struct mmc_host *mmc; | |
98 | struct mmc_command *cmd; | |
99 | struct mmc_request *request; | |
100 | ||
e0b19b83 | 101 | void __iomem *baseaddr; |
17ea0595 | 102 | int irq; |
e0b19b83 | 103 | |
65dbf343 AV |
104 | struct at91_mmc_data *board; |
105 | int present; | |
106 | ||
3dd3b039 AV |
107 | struct clk *mci_clk; |
108 | ||
65dbf343 AV |
109 | /* |
110 | * Flag indicating when the command has been sent. This is used to | |
111 | * work out whether or not to send the stop | |
112 | */ | |
113 | unsigned int flags; | |
114 | /* flag for current bus settings */ | |
115 | u32 bus_mode; | |
116 | ||
117 | /* DMA buffer used for transmitting */ | |
118 | unsigned int* buffer; | |
119 | dma_addr_t physical_address; | |
120 | unsigned int total_length; | |
121 | ||
122 | /* Latest in the scatterlist that has been enabled for transfer, but not freed */ | |
123 | int in_use_index; | |
124 | ||
125 | /* Latest in the scatterlist that has been enabled for transfer */ | |
126 | int transfer_index; | |
e181dce8 MP |
127 | |
128 | /* Timer for timeouts */ | |
129 | struct timer_list timer; | |
65dbf343 AV |
130 | }; |
131 | ||
c5a89c6c MP |
132 | /* |
133 | * Reset the controller and restore most of the state | |
134 | */ | |
135 | static void at91_reset_host(struct at91mci_host *host) | |
136 | { | |
137 | unsigned long flags; | |
138 | u32 mr; | |
139 | u32 sdcr; | |
140 | u32 dtor; | |
141 | u32 imr; | |
142 | ||
143 | local_irq_save(flags); | |
144 | imr = at91_mci_read(host, AT91_MCI_IMR); | |
145 | ||
146 | at91_mci_write(host, AT91_MCI_IDR, 0xffffffff); | |
147 | ||
148 | /* save current state */ | |
149 | mr = at91_mci_read(host, AT91_MCI_MR) & 0x7fff; | |
150 | sdcr = at91_mci_read(host, AT91_MCI_SDCR); | |
151 | dtor = at91_mci_read(host, AT91_MCI_DTOR); | |
152 | ||
153 | /* reset the controller */ | |
154 | at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST); | |
155 | ||
156 | /* restore state */ | |
157 | at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN); | |
158 | at91_mci_write(host, AT91_MCI_MR, mr); | |
159 | at91_mci_write(host, AT91_MCI_SDCR, sdcr); | |
160 | at91_mci_write(host, AT91_MCI_DTOR, dtor); | |
161 | at91_mci_write(host, AT91_MCI_IER, imr); | |
162 | ||
163 | /* make sure sdio interrupts will fire */ | |
164 | at91_mci_read(host, AT91_MCI_SR); | |
165 | ||
166 | local_irq_restore(flags); | |
167 | } | |
168 | ||
e181dce8 MP |
169 | static void at91_timeout_timer(unsigned long data) |
170 | { | |
171 | struct at91mci_host *host; | |
172 | ||
173 | host = (struct at91mci_host *)data; | |
174 | ||
175 | if (host->request) { | |
176 | dev_err(host->mmc->parent, "Timeout waiting end of packet\n"); | |
177 | ||
178 | if (host->cmd && host->cmd->data) { | |
179 | host->cmd->data->error = -ETIMEDOUT; | |
180 | } else { | |
181 | if (host->cmd) | |
182 | host->cmd->error = -ETIMEDOUT; | |
183 | else | |
184 | host->request->cmd->error = -ETIMEDOUT; | |
185 | } | |
186 | ||
c5a89c6c | 187 | at91_reset_host(host); |
e181dce8 MP |
188 | mmc_request_done(host->mmc, host->request); |
189 | } | |
190 | } | |
191 | ||
65dbf343 AV |
192 | /* |
193 | * Copy from sg to a dma block - used for transfers | |
194 | */ | |
e8d04d3d | 195 | static inline void at91_mci_sg_to_dma(struct at91mci_host *host, struct mmc_data *data) |
65dbf343 AV |
196 | { |
197 | unsigned int len, i, size; | |
198 | unsigned *dmabuf = host->buffer; | |
199 | ||
5385edc5 | 200 | size = data->blksz * data->blocks; |
65dbf343 AV |
201 | len = data->sg_len; |
202 | ||
5385edc5 VS |
203 | /* AT91SAM926[0/3] Data Write Operation and number of bytes erratum */ |
204 | if (cpu_is_at91sam9260() || cpu_is_at91sam9263()) | |
205 | if (host->total_length == 12) | |
206 | memset(dmabuf, 0, 12); | |
207 | ||
65dbf343 AV |
208 | /* |
209 | * Just loop through all entries. Size might not | |
210 | * be the entire list though so make sure that | |
211 | * we do not transfer too much. | |
212 | */ | |
213 | for (i = 0; i < len; i++) { | |
214 | struct scatterlist *sg; | |
215 | int amount; | |
65dbf343 AV |
216 | unsigned int *sgbuffer; |
217 | ||
218 | sg = &data->sg[i]; | |
219 | ||
45711f1a | 220 | sgbuffer = kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset; |
65dbf343 AV |
221 | amount = min(size, sg->length); |
222 | size -= amount; | |
65dbf343 | 223 | |
99eeb8df AV |
224 | if (cpu_is_at91rm9200()) { /* AT91RM9200 errata */ |
225 | int index; | |
226 | ||
227 | for (index = 0; index < (amount / 4); index++) | |
228 | *dmabuf++ = swab32(sgbuffer[index]); | |
5385edc5 | 229 | } else { |
0b3520f2 WM |
230 | char *tmpv = (char *)dmabuf; |
231 | memcpy(tmpv, sgbuffer, amount); | |
232 | tmpv += amount; | |
233 | dmabuf = (unsigned *)tmpv; | |
5385edc5 | 234 | } |
65dbf343 | 235 | |
0b3520f2 | 236 | kunmap_atomic(((void *)sgbuffer) - sg->offset, KM_BIO_SRC_IRQ); |
65dbf343 AV |
237 | |
238 | if (size == 0) | |
239 | break; | |
240 | } | |
241 | ||
242 | /* | |
243 | * Check that we didn't get a request to transfer | |
244 | * more data than can fit into the SG list. | |
245 | */ | |
246 | BUG_ON(size != 0); | |
247 | } | |
248 | ||
249 | /* | |
250 | * Prepare a dma read | |
251 | */ | |
e8d04d3d | 252 | static void at91_mci_pre_dma_read(struct at91mci_host *host) |
65dbf343 AV |
253 | { |
254 | int i; | |
255 | struct scatterlist *sg; | |
256 | struct mmc_command *cmd; | |
257 | struct mmc_data *data; | |
258 | ||
b44fb7a0 | 259 | pr_debug("pre dma read\n"); |
65dbf343 AV |
260 | |
261 | cmd = host->cmd; | |
262 | if (!cmd) { | |
b44fb7a0 | 263 | pr_debug("no command\n"); |
65dbf343 AV |
264 | return; |
265 | } | |
266 | ||
267 | data = cmd->data; | |
268 | if (!data) { | |
b44fb7a0 | 269 | pr_debug("no data\n"); |
65dbf343 AV |
270 | return; |
271 | } | |
272 | ||
273 | for (i = 0; i < 2; i++) { | |
274 | /* nothing left to transfer */ | |
275 | if (host->transfer_index >= data->sg_len) { | |
b44fb7a0 | 276 | pr_debug("Nothing left to transfer (index = %d)\n", host->transfer_index); |
65dbf343 AV |
277 | break; |
278 | } | |
279 | ||
280 | /* Check to see if this needs filling */ | |
281 | if (i == 0) { | |
93a3ddc2 | 282 | if (at91_mci_read(host, ATMEL_PDC_RCR) != 0) { |
b44fb7a0 | 283 | pr_debug("Transfer active in current\n"); |
65dbf343 AV |
284 | continue; |
285 | } | |
286 | } | |
287 | else { | |
93a3ddc2 | 288 | if (at91_mci_read(host, ATMEL_PDC_RNCR) != 0) { |
b44fb7a0 | 289 | pr_debug("Transfer active in next\n"); |
65dbf343 AV |
290 | continue; |
291 | } | |
292 | } | |
293 | ||
294 | /* Setup the next transfer */ | |
b44fb7a0 | 295 | pr_debug("Using transfer index %d\n", host->transfer_index); |
65dbf343 AV |
296 | |
297 | sg = &data->sg[host->transfer_index++]; | |
b44fb7a0 | 298 | pr_debug("sg = %p\n", sg); |
65dbf343 | 299 | |
45711f1a | 300 | sg->dma_address = dma_map_page(NULL, sg_page(sg), sg->offset, sg->length, DMA_FROM_DEVICE); |
65dbf343 | 301 | |
b44fb7a0 | 302 | pr_debug("dma address = %08X, length = %d\n", sg->dma_address, sg->length); |
65dbf343 AV |
303 | |
304 | if (i == 0) { | |
93a3ddc2 | 305 | at91_mci_write(host, ATMEL_PDC_RPR, sg->dma_address); |
80f92546 | 306 | at91_mci_write(host, ATMEL_PDC_RCR, (data->blksz & 0x3) ? sg->length : sg->length / 4); |
65dbf343 AV |
307 | } |
308 | else { | |
93a3ddc2 | 309 | at91_mci_write(host, ATMEL_PDC_RNPR, sg->dma_address); |
80f92546 | 310 | at91_mci_write(host, ATMEL_PDC_RNCR, (data->blksz & 0x3) ? sg->length : sg->length / 4); |
65dbf343 AV |
311 | } |
312 | } | |
313 | ||
b44fb7a0 | 314 | pr_debug("pre dma read done\n"); |
65dbf343 AV |
315 | } |
316 | ||
317 | /* | |
318 | * Handle after a dma read | |
319 | */ | |
e8d04d3d | 320 | static void at91_mci_post_dma_read(struct at91mci_host *host) |
65dbf343 AV |
321 | { |
322 | struct mmc_command *cmd; | |
323 | struct mmc_data *data; | |
324 | ||
b44fb7a0 | 325 | pr_debug("post dma read\n"); |
65dbf343 AV |
326 | |
327 | cmd = host->cmd; | |
328 | if (!cmd) { | |
b44fb7a0 | 329 | pr_debug("no command\n"); |
65dbf343 AV |
330 | return; |
331 | } | |
332 | ||
333 | data = cmd->data; | |
334 | if (!data) { | |
b44fb7a0 | 335 | pr_debug("no data\n"); |
65dbf343 AV |
336 | return; |
337 | } | |
338 | ||
339 | while (host->in_use_index < host->transfer_index) { | |
65dbf343 AV |
340 | struct scatterlist *sg; |
341 | ||
b44fb7a0 | 342 | pr_debug("finishing index %d\n", host->in_use_index); |
65dbf343 AV |
343 | |
344 | sg = &data->sg[host->in_use_index++]; | |
345 | ||
b44fb7a0 | 346 | pr_debug("Unmapping page %08X\n", sg->dma_address); |
65dbf343 AV |
347 | |
348 | dma_unmap_page(NULL, sg->dma_address, sg->length, DMA_FROM_DEVICE); | |
349 | ||
99eeb8df | 350 | if (cpu_is_at91rm9200()) { /* AT91RM9200 errata */ |
ed99c541 | 351 | unsigned int *buffer; |
99eeb8df | 352 | int index; |
65dbf343 | 353 | |
ed99c541 | 354 | /* Swap the contents of the buffer */ |
45711f1a | 355 | buffer = kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset; |
ed99c541 NF |
356 | pr_debug("buffer = %p, length = %d\n", buffer, sg->length); |
357 | ||
99eeb8df AV |
358 | for (index = 0; index < (sg->length / 4); index++) |
359 | buffer[index] = swab32(buffer[index]); | |
ed99c541 NF |
360 | |
361 | kunmap_atomic(buffer, KM_BIO_SRC_IRQ); | |
65dbf343 | 362 | } |
99eeb8df | 363 | |
45711f1a | 364 | flush_dcache_page(sg_page(sg)); |
4ac24a87 NF |
365 | |
366 | data->bytes_xfered += sg->length; | |
65dbf343 AV |
367 | } |
368 | ||
369 | /* Is there another transfer to trigger? */ | |
370 | if (host->transfer_index < data->sg_len) | |
e8d04d3d | 371 | at91_mci_pre_dma_read(host); |
65dbf343 | 372 | else { |
ed99c541 | 373 | at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_ENDRX); |
e0b19b83 | 374 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_RXBUFF); |
65dbf343 AV |
375 | } |
376 | ||
b44fb7a0 | 377 | pr_debug("post dma read done\n"); |
65dbf343 AV |
378 | } |
379 | ||
380 | /* | |
381 | * Handle transmitted data | |
382 | */ | |
383 | static void at91_mci_handle_transmitted(struct at91mci_host *host) | |
384 | { | |
385 | struct mmc_command *cmd; | |
386 | struct mmc_data *data; | |
387 | ||
b44fb7a0 | 388 | pr_debug("Handling the transmit\n"); |
65dbf343 AV |
389 | |
390 | /* Disable the transfer */ | |
93a3ddc2 | 391 | at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); |
65dbf343 AV |
392 | |
393 | /* Now wait for cmd ready */ | |
e0b19b83 | 394 | at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_TXBUFE); |
65dbf343 AV |
395 | |
396 | cmd = host->cmd; | |
397 | if (!cmd) return; | |
398 | ||
399 | data = cmd->data; | |
400 | if (!data) return; | |
401 | ||
be0192aa | 402 | if (cmd->data->blocks > 1) { |
ed99c541 NF |
403 | pr_debug("multiple write : wait for BLKE...\n"); |
404 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_BLKE); | |
405 | } else | |
406 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY); | |
4ac24a87 NF |
407 | } |
408 | ||
409 | /* | |
410 | * Update bytes tranfered count during a write operation | |
411 | */ | |
412 | static void at91_mci_update_bytes_xfered(struct at91mci_host *host) | |
413 | { | |
414 | struct mmc_data *data; | |
ed99c541 | 415 | |
4ac24a87 NF |
416 | /* always deal with the effective request (and not the current cmd) */ |
417 | ||
418 | if (host->request->cmd && host->request->cmd->error != 0) | |
419 | return; | |
420 | ||
421 | if (host->request->data) { | |
422 | data = host->request->data; | |
423 | if (data->flags & MMC_DATA_WRITE) { | |
424 | /* card is in IDLE mode now */ | |
425 | pr_debug("-> bytes_xfered %d, total_length = %d\n", | |
426 | data->bytes_xfered, host->total_length); | |
5385edc5 | 427 | data->bytes_xfered = data->blksz * data->blocks; |
4ac24a87 NF |
428 | } |
429 | } | |
65dbf343 AV |
430 | } |
431 | ||
4ac24a87 | 432 | |
ed99c541 NF |
433 | /*Handle after command sent ready*/ |
434 | static int at91_mci_handle_cmdrdy(struct at91mci_host *host) | |
435 | { | |
436 | if (!host->cmd) | |
437 | return 1; | |
438 | else if (!host->cmd->data) { | |
439 | if (host->flags & FL_SENT_STOP) { | |
440 | /*After multi block write, we must wait for NOTBUSY*/ | |
441 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY); | |
442 | } else return 1; | |
443 | } else if (host->cmd->data->flags & MMC_DATA_WRITE) { | |
444 | /*After sendding multi-block-write command, start DMA transfer*/ | |
4ac24a87 | 445 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_TXBUFE | AT91_MCI_BLKE); |
ed99c541 NF |
446 | at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); |
447 | } | |
448 | ||
449 | /* command not completed, have to wait */ | |
450 | return 0; | |
451 | } | |
452 | ||
453 | ||
65dbf343 AV |
454 | /* |
455 | * Enable the controller | |
456 | */ | |
e0b19b83 | 457 | static void at91_mci_enable(struct at91mci_host *host) |
65dbf343 | 458 | { |
ed99c541 NF |
459 | unsigned int mr; |
460 | ||
e0b19b83 | 461 | at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN); |
f3a8efa9 | 462 | at91_mci_write(host, AT91_MCI_IDR, 0xffffffff); |
e0b19b83 | 463 | at91_mci_write(host, AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC); |
ed99c541 NF |
464 | mr = AT91_MCI_PDCMODE | 0x34a; |
465 | ||
466 | if (cpu_is_at91sam9260() || cpu_is_at91sam9263()) | |
467 | mr |= AT91_MCI_RDPROOF | AT91_MCI_WRPROOF; | |
468 | ||
469 | at91_mci_write(host, AT91_MCI_MR, mr); | |
99eeb8df AV |
470 | |
471 | /* use Slot A or B (only one at same time) */ | |
472 | at91_mci_write(host, AT91_MCI_SDCR, host->board->slot_b); | |
65dbf343 AV |
473 | } |
474 | ||
475 | /* | |
476 | * Disable the controller | |
477 | */ | |
e0b19b83 | 478 | static void at91_mci_disable(struct at91mci_host *host) |
65dbf343 | 479 | { |
e0b19b83 | 480 | at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST); |
65dbf343 AV |
481 | } |
482 | ||
483 | /* | |
484 | * Send a command | |
65dbf343 | 485 | */ |
ed99c541 | 486 | static void at91_mci_send_command(struct at91mci_host *host, struct mmc_command *cmd) |
65dbf343 AV |
487 | { |
488 | unsigned int cmdr, mr; | |
489 | unsigned int block_length; | |
490 | struct mmc_data *data = cmd->data; | |
491 | ||
492 | unsigned int blocks; | |
493 | unsigned int ier = 0; | |
494 | ||
495 | host->cmd = cmd; | |
496 | ||
ed99c541 | 497 | /* Needed for leaving busy state before CMD1 */ |
e0b19b83 | 498 | if ((at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->opcode == 1)) { |
b44fb7a0 | 499 | pr_debug("Clearing timeout\n"); |
e0b19b83 AV |
500 | at91_mci_write(host, AT91_MCI_ARGR, 0); |
501 | at91_mci_write(host, AT91_MCI_CMDR, AT91_MCI_OPDCMD); | |
502 | while (!(at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_CMDRDY)) { | |
65dbf343 | 503 | /* spin */ |
e0b19b83 | 504 | pr_debug("Clearing: SR = %08X\n", at91_mci_read(host, AT91_MCI_SR)); |
65dbf343 AV |
505 | } |
506 | } | |
ed99c541 | 507 | |
65dbf343 AV |
508 | cmdr = cmd->opcode; |
509 | ||
510 | if (mmc_resp_type(cmd) == MMC_RSP_NONE) | |
511 | cmdr |= AT91_MCI_RSPTYP_NONE; | |
512 | else { | |
513 | /* if a response is expected then allow maximum response latancy */ | |
514 | cmdr |= AT91_MCI_MAXLAT; | |
515 | /* set 136 bit response for R2, 48 bit response otherwise */ | |
516 | if (mmc_resp_type(cmd) == MMC_RSP_R2) | |
517 | cmdr |= AT91_MCI_RSPTYP_136; | |
518 | else | |
519 | cmdr |= AT91_MCI_RSPTYP_48; | |
520 | } | |
521 | ||
522 | if (data) { | |
1d4de9ed | 523 | |
9da3cbaf VS |
524 | if (cpu_is_at91rm9200() || cpu_is_at91sam9261()) { |
525 | if (data->blksz & 0x3) { | |
526 | pr_debug("Unsupported block size\n"); | |
527 | cmd->error = -EINVAL; | |
528 | mmc_request_done(host->mmc, host->request); | |
529 | return; | |
530 | } | |
531 | if (data->flags & MMC_DATA_STREAM) { | |
532 | pr_debug("Stream commands not supported\n"); | |
533 | cmd->error = -EINVAL; | |
534 | mmc_request_done(host->mmc, host->request); | |
535 | return; | |
536 | } | |
1d4de9ed MP |
537 | } |
538 | ||
a3fd4a1b | 539 | block_length = data->blksz; |
65dbf343 AV |
540 | blocks = data->blocks; |
541 | ||
542 | /* always set data start - also set direction flag for read */ | |
543 | if (data->flags & MMC_DATA_READ) | |
544 | cmdr |= (AT91_MCI_TRDIR | AT91_MCI_TRCMD_START); | |
545 | else if (data->flags & MMC_DATA_WRITE) | |
546 | cmdr |= AT91_MCI_TRCMD_START; | |
547 | ||
548 | if (data->flags & MMC_DATA_STREAM) | |
549 | cmdr |= AT91_MCI_TRTYP_STREAM; | |
be0192aa | 550 | if (data->blocks > 1) |
65dbf343 AV |
551 | cmdr |= AT91_MCI_TRTYP_MULTIPLE; |
552 | } | |
553 | else { | |
554 | block_length = 0; | |
555 | blocks = 0; | |
556 | } | |
557 | ||
b6cedb38 | 558 | if (host->flags & FL_SENT_STOP) |
65dbf343 AV |
559 | cmdr |= AT91_MCI_TRCMD_STOP; |
560 | ||
561 | if (host->bus_mode == MMC_BUSMODE_OPENDRAIN) | |
562 | cmdr |= AT91_MCI_OPDCMD; | |
563 | ||
564 | /* | |
565 | * Set the arguments and send the command | |
566 | */ | |
f3a8efa9 | 567 | pr_debug("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n", |
e0b19b83 | 568 | cmd->opcode, cmdr, cmd->arg, blocks, block_length, at91_mci_read(host, AT91_MCI_MR)); |
65dbf343 AV |
569 | |
570 | if (!data) { | |
93a3ddc2 AV |
571 | at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS | ATMEL_PDC_RXTDIS); |
572 | at91_mci_write(host, ATMEL_PDC_RPR, 0); | |
573 | at91_mci_write(host, ATMEL_PDC_RCR, 0); | |
574 | at91_mci_write(host, ATMEL_PDC_RNPR, 0); | |
575 | at91_mci_write(host, ATMEL_PDC_RNCR, 0); | |
576 | at91_mci_write(host, ATMEL_PDC_TPR, 0); | |
577 | at91_mci_write(host, ATMEL_PDC_TCR, 0); | |
578 | at91_mci_write(host, ATMEL_PDC_TNPR, 0); | |
579 | at91_mci_write(host, ATMEL_PDC_TNCR, 0); | |
ed99c541 NF |
580 | ier = AT91_MCI_CMDRDY; |
581 | } else { | |
582 | /* zero block length and PDC mode */ | |
12bd2575 | 583 | mr = at91_mci_read(host, AT91_MCI_MR) & 0x5fff; |
80f92546 MP |
584 | mr |= (data->blksz & 0x3) ? AT91_MCI_PDCFBYTE : 0; |
585 | mr |= (block_length << 16); | |
586 | mr |= AT91_MCI_PDCMODE; | |
587 | at91_mci_write(host, AT91_MCI_MR, mr); | |
e0b19b83 | 588 | |
9da3cbaf | 589 | if (!(cpu_is_at91rm9200() || cpu_is_at91sam9261())) |
c5a89c6c MP |
590 | at91_mci_write(host, AT91_MCI_BLKR, |
591 | AT91_MCI_BLKR_BCNT(blocks) | | |
592 | AT91_MCI_BLKR_BLKLEN(block_length)); | |
593 | ||
ed99c541 NF |
594 | /* |
595 | * Disable the PDC controller | |
596 | */ | |
597 | at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); | |
65dbf343 | 598 | |
ed99c541 NF |
599 | if (cmdr & AT91_MCI_TRCMD_START) { |
600 | data->bytes_xfered = 0; | |
601 | host->transfer_index = 0; | |
602 | host->in_use_index = 0; | |
603 | if (cmdr & AT91_MCI_TRDIR) { | |
604 | /* | |
605 | * Handle a read | |
606 | */ | |
607 | host->buffer = NULL; | |
608 | host->total_length = 0; | |
609 | ||
610 | at91_mci_pre_dma_read(host); | |
611 | ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */; | |
612 | } | |
613 | else { | |
614 | /* | |
615 | * Handle a write | |
616 | */ | |
617 | host->total_length = block_length * blocks; | |
5385edc5 VS |
618 | /* |
619 | * AT91SAM926[0/3] Data Write Operation and | |
620 | * number of bytes erratum | |
621 | */ | |
622 | if (cpu_is_at91sam9260 () || cpu_is_at91sam9263()) | |
623 | if (host->total_length < 12) | |
624 | host->total_length = 12; | |
e385ea63 DB |
625 | |
626 | host->buffer = kmalloc(host->total_length, GFP_KERNEL); | |
627 | if (!host->buffer) { | |
628 | pr_debug("Can't alloc tx buffer\n"); | |
629 | cmd->error = -ENOMEM; | |
630 | mmc_request_done(host->mmc, host->request); | |
631 | return; | |
632 | } | |
ed99c541 NF |
633 | |
634 | at91_mci_sg_to_dma(host, data); | |
635 | ||
e385ea63 DB |
636 | host->physical_address = dma_map_single(NULL, |
637 | host->buffer, host->total_length, | |
638 | DMA_TO_DEVICE); | |
639 | ||
ed99c541 NF |
640 | pr_debug("Transmitting %d bytes\n", host->total_length); |
641 | ||
642 | at91_mci_write(host, ATMEL_PDC_TPR, host->physical_address); | |
80f92546 MP |
643 | at91_mci_write(host, ATMEL_PDC_TCR, (data->blksz & 0x3) ? |
644 | host->total_length : host->total_length / 4); | |
645 | ||
ed99c541 NF |
646 | ier = AT91_MCI_CMDRDY; |
647 | } | |
65dbf343 AV |
648 | } |
649 | } | |
650 | ||
651 | /* | |
652 | * Send the command and then enable the PDC - not the other way round as | |
653 | * the data sheet says | |
654 | */ | |
655 | ||
e0b19b83 AV |
656 | at91_mci_write(host, AT91_MCI_ARGR, cmd->arg); |
657 | at91_mci_write(host, AT91_MCI_CMDR, cmdr); | |
65dbf343 AV |
658 | |
659 | if (cmdr & AT91_MCI_TRCMD_START) { | |
660 | if (cmdr & AT91_MCI_TRDIR) | |
93a3ddc2 | 661 | at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN); |
65dbf343 | 662 | } |
65dbf343 | 663 | |
ed99c541 | 664 | /* Enable selected interrupts */ |
df05a303 | 665 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_ERRORS | ier); |
65dbf343 AV |
666 | } |
667 | ||
668 | /* | |
669 | * Process the next step in the request | |
670 | */ | |
e8d04d3d | 671 | static void at91_mci_process_next(struct at91mci_host *host) |
65dbf343 AV |
672 | { |
673 | if (!(host->flags & FL_SENT_COMMAND)) { | |
674 | host->flags |= FL_SENT_COMMAND; | |
ed99c541 | 675 | at91_mci_send_command(host, host->request->cmd); |
65dbf343 AV |
676 | } |
677 | else if ((!(host->flags & FL_SENT_STOP)) && host->request->stop) { | |
678 | host->flags |= FL_SENT_STOP; | |
ed99c541 | 679 | at91_mci_send_command(host, host->request->stop); |
e181dce8 MP |
680 | } else { |
681 | del_timer(&host->timer); | |
c5a89c6c MP |
682 | /* the at91rm9200 mci controller hangs after some transfers, |
683 | * and the workaround is to reset it after each transfer. | |
684 | */ | |
685 | if (cpu_is_at91rm9200()) | |
686 | at91_reset_host(host); | |
65dbf343 | 687 | mmc_request_done(host->mmc, host->request); |
e181dce8 | 688 | } |
65dbf343 AV |
689 | } |
690 | ||
691 | /* | |
692 | * Handle a command that has been completed | |
693 | */ | |
ba7deeed | 694 | static void at91_mci_completed_command(struct at91mci_host *host, unsigned int status) |
65dbf343 AV |
695 | { |
696 | struct mmc_command *cmd = host->cmd; | |
fa1fe010 | 697 | struct mmc_data *data = cmd->data; |
65dbf343 | 698 | |
7a6588ba | 699 | at91_mci_write(host, AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); |
65dbf343 | 700 | |
e0b19b83 AV |
701 | cmd->resp[0] = at91_mci_read(host, AT91_MCI_RSPR(0)); |
702 | cmd->resp[1] = at91_mci_read(host, AT91_MCI_RSPR(1)); | |
703 | cmd->resp[2] = at91_mci_read(host, AT91_MCI_RSPR(2)); | |
704 | cmd->resp[3] = at91_mci_read(host, AT91_MCI_RSPR(3)); | |
65dbf343 AV |
705 | |
706 | if (host->buffer) { | |
e385ea63 DB |
707 | dma_unmap_single(NULL, |
708 | host->physical_address, host->total_length, | |
709 | DMA_TO_DEVICE); | |
710 | kfree(host->buffer); | |
65dbf343 AV |
711 | host->buffer = NULL; |
712 | } | |
713 | ||
ba7deeed NF |
714 | pr_debug("Status = %08X/%08x [%08X %08X %08X %08X]\n", |
715 | status, at91_mci_read(host, AT91_MCI_SR), | |
716 | cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); | |
65dbf343 | 717 | |
9e3866b5 | 718 | if (status & AT91_MCI_ERRORS) { |
b6cedb38 | 719 | if ((status & AT91_MCI_RCRCE) && !(mmc_resp_type(cmd) & MMC_RSP_CRC)) { |
17b0429d | 720 | cmd->error = 0; |
65dbf343 AV |
721 | } |
722 | else { | |
fa1fe010 NF |
723 | if (status & (AT91_MCI_DTOE | AT91_MCI_DCRCE)) { |
724 | if (data) { | |
725 | if (status & AT91_MCI_DTOE) | |
726 | data->error = -ETIMEDOUT; | |
727 | else if (status & AT91_MCI_DCRCE) | |
728 | data->error = -EILSEQ; | |
729 | } | |
730 | } else { | |
731 | if (status & AT91_MCI_RTOE) | |
732 | cmd->error = -ETIMEDOUT; | |
733 | else if (status & AT91_MCI_RCRCE) | |
734 | cmd->error = -EILSEQ; | |
735 | else | |
736 | cmd->error = -EIO; | |
737 | } | |
65dbf343 | 738 | |
fa1fe010 NF |
739 | pr_debug("Error detected and set to %d/%d (cmd = %d, retries = %d)\n", |
740 | cmd->error, data ? data->error : 0, | |
741 | cmd->opcode, cmd->retries); | |
65dbf343 AV |
742 | } |
743 | } | |
744 | else | |
17b0429d | 745 | cmd->error = 0; |
65dbf343 | 746 | |
e8d04d3d | 747 | at91_mci_process_next(host); |
65dbf343 AV |
748 | } |
749 | ||
750 | /* | |
751 | * Handle an MMC request | |
752 | */ | |
753 | static void at91_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
754 | { | |
755 | struct at91mci_host *host = mmc_priv(mmc); | |
756 | host->request = mrq; | |
757 | host->flags = 0; | |
758 | ||
e181dce8 MP |
759 | mod_timer(&host->timer, jiffies + HZ); |
760 | ||
e8d04d3d | 761 | at91_mci_process_next(host); |
65dbf343 AV |
762 | } |
763 | ||
764 | /* | |
765 | * Set the IOS | |
766 | */ | |
767 | static void at91_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
768 | { | |
769 | int clkdiv; | |
770 | struct at91mci_host *host = mmc_priv(mmc); | |
3dd3b039 | 771 | unsigned long at91_master_clock = clk_get_rate(host->mci_clk); |
65dbf343 | 772 | |
b44fb7a0 | 773 | host->bus_mode = ios->bus_mode; |
65dbf343 AV |
774 | |
775 | if (ios->clock == 0) { | |
776 | /* Disable the MCI controller */ | |
e0b19b83 | 777 | at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS); |
65dbf343 AV |
778 | clkdiv = 0; |
779 | } | |
780 | else { | |
781 | /* Enable the MCI controller */ | |
e0b19b83 | 782 | at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN); |
65dbf343 AV |
783 | |
784 | if ((at91_master_clock % (ios->clock * 2)) == 0) | |
785 | clkdiv = ((at91_master_clock / ios->clock) / 2) - 1; | |
786 | else | |
787 | clkdiv = (at91_master_clock / ios->clock) / 2; | |
788 | ||
b44fb7a0 | 789 | pr_debug("clkdiv = %d. mcck = %ld\n", clkdiv, |
65dbf343 AV |
790 | at91_master_clock / (2 * (clkdiv + 1))); |
791 | } | |
792 | if (ios->bus_width == MMC_BUS_WIDTH_4 && host->board->wire4) { | |
b44fb7a0 | 793 | pr_debug("MMC: Setting controller bus width to 4\n"); |
e0b19b83 | 794 | at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) | AT91_MCI_SDCBUS); |
65dbf343 AV |
795 | } |
796 | else { | |
b44fb7a0 | 797 | pr_debug("MMC: Setting controller bus width to 1\n"); |
e0b19b83 | 798 | at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS); |
65dbf343 AV |
799 | } |
800 | ||
801 | /* Set the clock divider */ | |
e0b19b83 | 802 | at91_mci_write(host, AT91_MCI_MR, (at91_mci_read(host, AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv); |
65dbf343 AV |
803 | |
804 | /* maybe switch power to the card */ | |
b44fb7a0 | 805 | if (host->board->vcc_pin) { |
65dbf343 AV |
806 | switch (ios->power_mode) { |
807 | case MMC_POWER_OFF: | |
6e996ee8 | 808 | gpio_set_value(host->board->vcc_pin, 0); |
65dbf343 AV |
809 | break; |
810 | case MMC_POWER_UP: | |
6e996ee8 | 811 | gpio_set_value(host->board->vcc_pin, 1); |
65dbf343 | 812 | break; |
e5c0ef90 MP |
813 | case MMC_POWER_ON: |
814 | break; | |
815 | default: | |
816 | WARN_ON(1); | |
65dbf343 AV |
817 | } |
818 | } | |
819 | } | |
820 | ||
821 | /* | |
822 | * Handle an interrupt | |
823 | */ | |
7d12e780 | 824 | static irqreturn_t at91_mci_irq(int irq, void *devid) |
65dbf343 AV |
825 | { |
826 | struct at91mci_host *host = devid; | |
827 | int completed = 0; | |
df05a303 | 828 | unsigned int int_status, int_mask; |
65dbf343 | 829 | |
e0b19b83 | 830 | int_status = at91_mci_read(host, AT91_MCI_SR); |
df05a303 | 831 | int_mask = at91_mci_read(host, AT91_MCI_IMR); |
37b758e8 | 832 | |
f3a8efa9 | 833 | pr_debug("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask, |
df05a303 | 834 | int_status & int_mask); |
37b758e8 | 835 | |
df05a303 AV |
836 | int_status = int_status & int_mask; |
837 | ||
838 | if (int_status & AT91_MCI_ERRORS) { | |
65dbf343 | 839 | completed = 1; |
37b758e8 | 840 | |
df05a303 AV |
841 | if (int_status & AT91_MCI_UNRE) |
842 | pr_debug("MMC: Underrun error\n"); | |
843 | if (int_status & AT91_MCI_OVRE) | |
844 | pr_debug("MMC: Overrun error\n"); | |
845 | if (int_status & AT91_MCI_DTOE) | |
846 | pr_debug("MMC: Data timeout\n"); | |
847 | if (int_status & AT91_MCI_DCRCE) | |
848 | pr_debug("MMC: CRC error in data\n"); | |
849 | if (int_status & AT91_MCI_RTOE) | |
850 | pr_debug("MMC: Response timeout\n"); | |
851 | if (int_status & AT91_MCI_RENDE) | |
852 | pr_debug("MMC: Response end bit error\n"); | |
853 | if (int_status & AT91_MCI_RCRCE) | |
854 | pr_debug("MMC: Response CRC error\n"); | |
855 | if (int_status & AT91_MCI_RDIRE) | |
856 | pr_debug("MMC: Response direction error\n"); | |
857 | if (int_status & AT91_MCI_RINDE) | |
858 | pr_debug("MMC: Response index error\n"); | |
859 | } else { | |
860 | /* Only continue processing if no errors */ | |
65dbf343 | 861 | |
65dbf343 | 862 | if (int_status & AT91_MCI_TXBUFE) { |
b44fb7a0 | 863 | pr_debug("TX buffer empty\n"); |
65dbf343 AV |
864 | at91_mci_handle_transmitted(host); |
865 | } | |
866 | ||
ed99c541 NF |
867 | if (int_status & AT91_MCI_ENDRX) { |
868 | pr_debug("ENDRX\n"); | |
869 | at91_mci_post_dma_read(host); | |
870 | } | |
871 | ||
65dbf343 | 872 | if (int_status & AT91_MCI_RXBUFF) { |
b44fb7a0 | 873 | pr_debug("RX buffer full\n"); |
ed99c541 NF |
874 | at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS); |
875 | at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_RXBUFF | AT91_MCI_ENDRX); | |
876 | completed = 1; | |
65dbf343 AV |
877 | } |
878 | ||
df05a303 | 879 | if (int_status & AT91_MCI_ENDTX) |
b44fb7a0 | 880 | pr_debug("Transmit has ended\n"); |
65dbf343 | 881 | |
65dbf343 | 882 | if (int_status & AT91_MCI_NOTBUSY) { |
b44fb7a0 | 883 | pr_debug("Card is ready\n"); |
4ac24a87 | 884 | at91_mci_update_bytes_xfered(host); |
ed99c541 | 885 | completed = 1; |
65dbf343 AV |
886 | } |
887 | ||
df05a303 | 888 | if (int_status & AT91_MCI_DTIP) |
b44fb7a0 | 889 | pr_debug("Data transfer in progress\n"); |
65dbf343 | 890 | |
ed99c541 | 891 | if (int_status & AT91_MCI_BLKE) { |
b44fb7a0 | 892 | pr_debug("Block transfer has ended\n"); |
4ac24a87 NF |
893 | if (host->request->data && host->request->data->blocks > 1) { |
894 | /* multi block write : complete multi write | |
895 | * command and send stop */ | |
896 | completed = 1; | |
897 | } else { | |
898 | at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY); | |
899 | } | |
ed99c541 | 900 | } |
65dbf343 | 901 | |
7a6588ba EB |
902 | if (int_status & AT91_MCI_SDIOIRQA) |
903 | mmc_signal_sdio_irq(host->mmc); | |
904 | ||
905 | if (int_status & AT91_MCI_SDIOIRQB) | |
906 | mmc_signal_sdio_irq(host->mmc); | |
907 | ||
df05a303 | 908 | if (int_status & AT91_MCI_TXRDY) |
b44fb7a0 | 909 | pr_debug("Ready to transmit\n"); |
65dbf343 | 910 | |
df05a303 | 911 | if (int_status & AT91_MCI_RXRDY) |
b44fb7a0 | 912 | pr_debug("Ready to receive\n"); |
65dbf343 AV |
913 | |
914 | if (int_status & AT91_MCI_CMDRDY) { | |
b44fb7a0 | 915 | pr_debug("Command ready\n"); |
ed99c541 | 916 | completed = at91_mci_handle_cmdrdy(host); |
65dbf343 AV |
917 | } |
918 | } | |
65dbf343 AV |
919 | |
920 | if (completed) { | |
b44fb7a0 | 921 | pr_debug("Completed command\n"); |
7a6588ba | 922 | at91_mci_write(host, AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); |
ba7deeed | 923 | at91_mci_completed_command(host, int_status); |
df05a303 | 924 | } else |
7a6588ba | 925 | at91_mci_write(host, AT91_MCI_IDR, int_status & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); |
65dbf343 AV |
926 | |
927 | return IRQ_HANDLED; | |
928 | } | |
929 | ||
7d12e780 | 930 | static irqreturn_t at91_mmc_det_irq(int irq, void *_host) |
65dbf343 AV |
931 | { |
932 | struct at91mci_host *host = _host; | |
6e996ee8 | 933 | int present = !gpio_get_value(irq_to_gpio(irq)); |
65dbf343 AV |
934 | |
935 | /* | |
936 | * we expect this irq on both insert and remove, | |
937 | * and use a short delay to debounce. | |
938 | */ | |
939 | if (present != host->present) { | |
940 | host->present = present; | |
b44fb7a0 | 941 | pr_debug("%s: card %s\n", mmc_hostname(host->mmc), |
65dbf343 AV |
942 | present ? "insert" : "remove"); |
943 | if (!present) { | |
b44fb7a0 | 944 | pr_debug("****** Resetting SD-card bus width ******\n"); |
99eeb8df | 945 | at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS); |
65dbf343 AV |
946 | } |
947 | mmc_detect_change(host->mmc, msecs_to_jiffies(100)); | |
948 | } | |
949 | return IRQ_HANDLED; | |
950 | } | |
951 | ||
a26b498c | 952 | static int at91_mci_get_ro(struct mmc_host *mmc) |
65dbf343 | 953 | { |
65dbf343 AV |
954 | struct at91mci_host *host = mmc_priv(mmc); |
955 | ||
08f80bb5 AV |
956 | if (host->board->wp_pin) |
957 | return !!gpio_get_value(host->board->wp_pin); | |
958 | /* | |
959 | * Board doesn't support read only detection; let the mmc core | |
960 | * decide what to do. | |
961 | */ | |
962 | return -ENOSYS; | |
65dbf343 AV |
963 | } |
964 | ||
7a6588ba EB |
965 | static void at91_mci_enable_sdio_irq(struct mmc_host *mmc, int enable) |
966 | { | |
967 | struct at91mci_host *host = mmc_priv(mmc); | |
968 | ||
969 | pr_debug("%s: sdio_irq %c : %s\n", mmc_hostname(host->mmc), | |
970 | host->board->slot_b ? 'B':'A', enable ? "enable" : "disable"); | |
971 | at91_mci_write(host, enable ? AT91_MCI_IER : AT91_MCI_IDR, | |
972 | host->board->slot_b ? AT91_MCI_SDIOIRQB : AT91_MCI_SDIOIRQA); | |
973 | ||
974 | } | |
975 | ||
ab7aefd0 | 976 | static const struct mmc_host_ops at91_mci_ops = { |
65dbf343 AV |
977 | .request = at91_mci_request, |
978 | .set_ios = at91_mci_set_ios, | |
979 | .get_ro = at91_mci_get_ro, | |
7a6588ba | 980 | .enable_sdio_irq = at91_mci_enable_sdio_irq, |
65dbf343 AV |
981 | }; |
982 | ||
983 | /* | |
984 | * Probe for the device | |
985 | */ | |
a26b498c | 986 | static int __init at91_mci_probe(struct platform_device *pdev) |
65dbf343 AV |
987 | { |
988 | struct mmc_host *mmc; | |
989 | struct at91mci_host *host; | |
17ea0595 | 990 | struct resource *res; |
65dbf343 AV |
991 | int ret; |
992 | ||
17ea0595 AV |
993 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
994 | if (!res) | |
995 | return -ENXIO; | |
996 | ||
997 | if (!request_mem_region(res->start, res->end - res->start + 1, DRIVER_NAME)) | |
998 | return -EBUSY; | |
999 | ||
65dbf343 AV |
1000 | mmc = mmc_alloc_host(sizeof(struct at91mci_host), &pdev->dev); |
1001 | if (!mmc) { | |
6e996ee8 DB |
1002 | ret = -ENOMEM; |
1003 | dev_dbg(&pdev->dev, "couldn't allocate mmc host\n"); | |
1004 | goto fail6; | |
65dbf343 AV |
1005 | } |
1006 | ||
1007 | mmc->ops = &at91_mci_ops; | |
1008 | mmc->f_min = 375000; | |
1009 | mmc->f_max = 25000000; | |
1010 | mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; | |
23af6039 | 1011 | mmc->caps = MMC_CAP_SDIO_IRQ; |
65dbf343 | 1012 | |
fe4a3c7a | 1013 | mmc->max_blk_size = 4095; |
55db890a | 1014 | mmc->max_blk_count = mmc->max_req_size; |
fe4a3c7a | 1015 | |
65dbf343 AV |
1016 | host = mmc_priv(mmc); |
1017 | host->mmc = mmc; | |
1018 | host->buffer = NULL; | |
1019 | host->bus_mode = 0; | |
1020 | host->board = pdev->dev.platform_data; | |
1021 | if (host->board->wire4) { | |
ed99c541 NF |
1022 | if (cpu_is_at91sam9260() || cpu_is_at91sam9263()) |
1023 | mmc->caps |= MMC_CAP_4_BIT_DATA; | |
1024 | else | |
6e996ee8 | 1025 | dev_warn(&pdev->dev, "4 wire bus mode not supported" |
ed99c541 | 1026 | " - using 1 wire\n"); |
65dbf343 AV |
1027 | } |
1028 | ||
6e996ee8 DB |
1029 | /* |
1030 | * Reserve GPIOs ... board init code makes sure these pins are set | |
1031 | * up as GPIOs with the right direction (input, except for vcc) | |
1032 | */ | |
1033 | if (host->board->det_pin) { | |
1034 | ret = gpio_request(host->board->det_pin, "mmc_detect"); | |
1035 | if (ret < 0) { | |
1036 | dev_dbg(&pdev->dev, "couldn't claim card detect pin\n"); | |
1037 | goto fail5; | |
1038 | } | |
1039 | } | |
1040 | if (host->board->wp_pin) { | |
1041 | ret = gpio_request(host->board->wp_pin, "mmc_wp"); | |
1042 | if (ret < 0) { | |
1043 | dev_dbg(&pdev->dev, "couldn't claim wp sense pin\n"); | |
1044 | goto fail4; | |
1045 | } | |
1046 | } | |
1047 | if (host->board->vcc_pin) { | |
1048 | ret = gpio_request(host->board->vcc_pin, "mmc_vcc"); | |
1049 | if (ret < 0) { | |
1050 | dev_dbg(&pdev->dev, "couldn't claim vcc switch pin\n"); | |
1051 | goto fail3; | |
1052 | } | |
1053 | } | |
1054 | ||
65dbf343 AV |
1055 | /* |
1056 | * Get Clock | |
1057 | */ | |
3dd3b039 AV |
1058 | host->mci_clk = clk_get(&pdev->dev, "mci_clk"); |
1059 | if (IS_ERR(host->mci_clk)) { | |
6e996ee8 DB |
1060 | ret = -ENODEV; |
1061 | dev_dbg(&pdev->dev, "no mci_clk?\n"); | |
1062 | goto fail2; | |
65dbf343 | 1063 | } |
65dbf343 | 1064 | |
17ea0595 AV |
1065 | /* |
1066 | * Map I/O region | |
1067 | */ | |
1068 | host->baseaddr = ioremap(res->start, res->end - res->start + 1); | |
1069 | if (!host->baseaddr) { | |
6e996ee8 DB |
1070 | ret = -ENOMEM; |
1071 | goto fail1; | |
17ea0595 | 1072 | } |
e0b19b83 AV |
1073 | |
1074 | /* | |
1075 | * Reset hardware | |
1076 | */ | |
3dd3b039 | 1077 | clk_enable(host->mci_clk); /* Enable the peripheral clock */ |
e0b19b83 AV |
1078 | at91_mci_disable(host); |
1079 | at91_mci_enable(host); | |
1080 | ||
65dbf343 AV |
1081 | /* |
1082 | * Allocate the MCI interrupt | |
1083 | */ | |
17ea0595 | 1084 | host->irq = platform_get_irq(pdev, 0); |
6e996ee8 DB |
1085 | ret = request_irq(host->irq, at91_mci_irq, IRQF_SHARED, |
1086 | mmc_hostname(mmc), host); | |
65dbf343 | 1087 | if (ret) { |
6e996ee8 DB |
1088 | dev_dbg(&pdev->dev, "request MCI interrupt failed\n"); |
1089 | goto fail0; | |
65dbf343 AV |
1090 | } |
1091 | ||
99ba0405 NF |
1092 | setup_timer(&host->timer, at91_timeout_timer, (unsigned long)host); |
1093 | ||
65dbf343 AV |
1094 | platform_set_drvdata(pdev, mmc); |
1095 | ||
1096 | /* | |
1097 | * Add host to MMC layer | |
1098 | */ | |
63b66438 | 1099 | if (host->board->det_pin) { |
6e996ee8 | 1100 | host->present = !gpio_get_value(host->board->det_pin); |
63b66438 | 1101 | } |
65dbf343 AV |
1102 | else |
1103 | host->present = -1; | |
1104 | ||
1105 | mmc_add_host(mmc); | |
1106 | ||
1107 | /* | |
1108 | * monitor card insertion/removal if we can | |
1109 | */ | |
1110 | if (host->board->det_pin) { | |
6e996ee8 DB |
1111 | ret = request_irq(gpio_to_irq(host->board->det_pin), |
1112 | at91_mmc_det_irq, 0, mmc_hostname(mmc), host); | |
65dbf343 | 1113 | if (ret) |
6e996ee8 DB |
1114 | dev_warn(&pdev->dev, "request MMC detect irq failed\n"); |
1115 | else | |
1116 | device_init_wakeup(&pdev->dev, 1); | |
65dbf343 AV |
1117 | } |
1118 | ||
f3a8efa9 | 1119 | pr_debug("Added MCI driver\n"); |
65dbf343 AV |
1120 | |
1121 | return 0; | |
6e996ee8 DB |
1122 | |
1123 | fail0: | |
1124 | clk_disable(host->mci_clk); | |
1125 | iounmap(host->baseaddr); | |
1126 | fail1: | |
1127 | clk_put(host->mci_clk); | |
1128 | fail2: | |
1129 | if (host->board->vcc_pin) | |
1130 | gpio_free(host->board->vcc_pin); | |
1131 | fail3: | |
1132 | if (host->board->wp_pin) | |
1133 | gpio_free(host->board->wp_pin); | |
1134 | fail4: | |
1135 | if (host->board->det_pin) | |
1136 | gpio_free(host->board->det_pin); | |
1137 | fail5: | |
1138 | mmc_free_host(mmc); | |
1139 | fail6: | |
1140 | release_mem_region(res->start, res->end - res->start + 1); | |
1141 | dev_err(&pdev->dev, "probe failed, err %d\n", ret); | |
1142 | return ret; | |
65dbf343 AV |
1143 | } |
1144 | ||
1145 | /* | |
1146 | * Remove a device | |
1147 | */ | |
a26b498c | 1148 | static int __exit at91_mci_remove(struct platform_device *pdev) |
65dbf343 AV |
1149 | { |
1150 | struct mmc_host *mmc = platform_get_drvdata(pdev); | |
1151 | struct at91mci_host *host; | |
17ea0595 | 1152 | struct resource *res; |
65dbf343 AV |
1153 | |
1154 | if (!mmc) | |
1155 | return -1; | |
1156 | ||
1157 | host = mmc_priv(mmc); | |
1158 | ||
e0cda54e | 1159 | if (host->board->det_pin) { |
6e996ee8 DB |
1160 | if (device_can_wakeup(&pdev->dev)) |
1161 | free_irq(gpio_to_irq(host->board->det_pin), host); | |
63b66438 | 1162 | device_init_wakeup(&pdev->dev, 0); |
6e996ee8 | 1163 | gpio_free(host->board->det_pin); |
65dbf343 AV |
1164 | } |
1165 | ||
e0b19b83 | 1166 | at91_mci_disable(host); |
e181dce8 | 1167 | del_timer_sync(&host->timer); |
17ea0595 AV |
1168 | mmc_remove_host(mmc); |
1169 | free_irq(host->irq, host); | |
65dbf343 | 1170 | |
3dd3b039 AV |
1171 | clk_disable(host->mci_clk); /* Disable the peripheral clock */ |
1172 | clk_put(host->mci_clk); | |
65dbf343 | 1173 | |
6e996ee8 DB |
1174 | if (host->board->vcc_pin) |
1175 | gpio_free(host->board->vcc_pin); | |
1176 | if (host->board->wp_pin) | |
1177 | gpio_free(host->board->wp_pin); | |
1178 | ||
17ea0595 AV |
1179 | iounmap(host->baseaddr); |
1180 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1181 | release_mem_region(res->start, res->end - res->start + 1); | |
65dbf343 | 1182 | |
17ea0595 AV |
1183 | mmc_free_host(mmc); |
1184 | platform_set_drvdata(pdev, NULL); | |
b44fb7a0 | 1185 | pr_debug("MCI Removed\n"); |
65dbf343 AV |
1186 | |
1187 | return 0; | |
1188 | } | |
1189 | ||
1190 | #ifdef CONFIG_PM | |
1191 | static int at91_mci_suspend(struct platform_device *pdev, pm_message_t state) | |
1192 | { | |
1193 | struct mmc_host *mmc = platform_get_drvdata(pdev); | |
63b66438 | 1194 | struct at91mci_host *host = mmc_priv(mmc); |
65dbf343 AV |
1195 | int ret = 0; |
1196 | ||
e0cda54e | 1197 | if (host->board->det_pin && device_may_wakeup(&pdev->dev)) |
63b66438 MP |
1198 | enable_irq_wake(host->board->det_pin); |
1199 | ||
65dbf343 AV |
1200 | if (mmc) |
1201 | ret = mmc_suspend_host(mmc, state); | |
1202 | ||
1203 | return ret; | |
1204 | } | |
1205 | ||
1206 | static int at91_mci_resume(struct platform_device *pdev) | |
1207 | { | |
1208 | struct mmc_host *mmc = platform_get_drvdata(pdev); | |
63b66438 | 1209 | struct at91mci_host *host = mmc_priv(mmc); |
65dbf343 AV |
1210 | int ret = 0; |
1211 | ||
e0cda54e | 1212 | if (host->board->det_pin && device_may_wakeup(&pdev->dev)) |
63b66438 MP |
1213 | disable_irq_wake(host->board->det_pin); |
1214 | ||
65dbf343 AV |
1215 | if (mmc) |
1216 | ret = mmc_resume_host(mmc); | |
1217 | ||
1218 | return ret; | |
1219 | } | |
1220 | #else | |
1221 | #define at91_mci_suspend NULL | |
1222 | #define at91_mci_resume NULL | |
1223 | #endif | |
1224 | ||
1225 | static struct platform_driver at91_mci_driver = { | |
a26b498c | 1226 | .remove = __exit_p(at91_mci_remove), |
65dbf343 AV |
1227 | .suspend = at91_mci_suspend, |
1228 | .resume = at91_mci_resume, | |
1229 | .driver = { | |
1230 | .name = DRIVER_NAME, | |
1231 | .owner = THIS_MODULE, | |
1232 | }, | |
1233 | }; | |
1234 | ||
1235 | static int __init at91_mci_init(void) | |
1236 | { | |
a26b498c | 1237 | return platform_driver_probe(&at91_mci_driver, at91_mci_probe); |
65dbf343 AV |
1238 | } |
1239 | ||
1240 | static void __exit at91_mci_exit(void) | |
1241 | { | |
1242 | platform_driver_unregister(&at91_mci_driver); | |
1243 | } | |
1244 | ||
1245 | module_init(at91_mci_init); | |
1246 | module_exit(at91_mci_exit); | |
1247 | ||
1248 | MODULE_DESCRIPTION("AT91 Multimedia Card Interface driver"); | |
1249 | MODULE_AUTHOR("Nick Randell"); | |
1250 | MODULE_LICENSE("GPL"); | |
bc65c724 | 1251 | MODULE_ALIAS("platform:at91_mci"); |