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f204e0b8 IM |
1 | /* |
2 | * Copyright 2014 IBM Corp. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version | |
7 | * 2 of the License, or (at your option) any later version. | |
8 | */ | |
9 | ||
10 | #include <linux/workqueue.h> | |
174cd4b1 | 11 | #include <linux/sched/signal.h> |
6e84f315 | 12 | #include <linux/sched/mm.h> |
f204e0b8 IM |
13 | #include <linux/pid.h> |
14 | #include <linux/mm.h> | |
15 | #include <linux/moduleparam.h> | |
16 | ||
17 | #undef MODULE_PARAM_PREFIX | |
18 | #define MODULE_PARAM_PREFIX "cxl" "." | |
19 | #include <asm/current.h> | |
20 | #include <asm/copro.h> | |
21 | #include <asm/mmu.h> | |
22 | ||
23 | #include "cxl.h" | |
9bcf28cd | 24 | #include "trace.h" |
f204e0b8 | 25 | |
eb01d4c2 IM |
26 | static bool sste_matches(struct cxl_sste *sste, struct copro_slb *slb) |
27 | { | |
28 | return ((sste->vsid_data == cpu_to_be64(slb->vsid)) && | |
29 | (sste->esid_data == cpu_to_be64(slb->esid))); | |
30 | } | |
31 | ||
32 | /* | |
33 | * This finds a free SSTE for the given SLB, or returns NULL if it's already in | |
34 | * the segment table. | |
35 | */ | |
b03a7f57 IM |
36 | static struct cxl_sste* find_free_sste(struct cxl_context *ctx, |
37 | struct copro_slb *slb) | |
f204e0b8 | 38 | { |
eb01d4c2 | 39 | struct cxl_sste *primary, *sste, *ret = NULL; |
b03a7f57 | 40 | unsigned int mask = (ctx->sst_size >> 7) - 1; /* SSTP0[SegTableSize] */ |
5100a9d6 | 41 | unsigned int entry; |
b03a7f57 IM |
42 | unsigned int hash; |
43 | ||
44 | if (slb->vsid & SLB_VSID_B_1T) | |
45 | hash = (slb->esid >> SID_SHIFT_1T) & mask; | |
46 | else /* 256M */ | |
47 | hash = (slb->esid >> SID_SHIFT) & mask; | |
f204e0b8 | 48 | |
b03a7f57 IM |
49 | primary = ctx->sstp + (hash << 3); |
50 | ||
51 | for (entry = 0, sste = primary; entry < 8; entry++, sste++) { | |
eb01d4c2 IM |
52 | if (!ret && !(be64_to_cpu(sste->esid_data) & SLB_ESID_V)) |
53 | ret = sste; | |
54 | if (sste_matches(sste, slb)) | |
55 | return NULL; | |
f204e0b8 | 56 | } |
eb01d4c2 IM |
57 | if (ret) |
58 | return ret; | |
b03a7f57 | 59 | |
f204e0b8 | 60 | /* Nothing free, select an entry to cast out */ |
eb01d4c2 | 61 | ret = primary + ctx->sst_lru; |
b03a7f57 | 62 | ctx->sst_lru = (ctx->sst_lru + 1) & 0x7; |
f204e0b8 | 63 | |
eb01d4c2 | 64 | return ret; |
f204e0b8 IM |
65 | } |
66 | ||
67 | static void cxl_load_segment(struct cxl_context *ctx, struct copro_slb *slb) | |
68 | { | |
69 | /* mask is the group index, we search primary and secondary here. */ | |
f204e0b8 | 70 | struct cxl_sste *sste; |
f204e0b8 IM |
71 | unsigned long flags; |
72 | ||
f204e0b8 | 73 | spin_lock_irqsave(&ctx->sste_lock, flags); |
b03a7f57 | 74 | sste = find_free_sste(ctx, slb); |
eb01d4c2 IM |
75 | if (!sste) |
76 | goto out_unlock; | |
f204e0b8 IM |
77 | |
78 | pr_devel("CXL Populating SST[%li]: %#llx %#llx\n", | |
79 | sste - ctx->sstp, slb->vsid, slb->esid); | |
9bcf28cd | 80 | trace_cxl_ste_write(ctx, sste - ctx->sstp, slb->esid, slb->vsid); |
f204e0b8 IM |
81 | |
82 | sste->vsid_data = cpu_to_be64(slb->vsid); | |
83 | sste->esid_data = cpu_to_be64(slb->esid); | |
eb01d4c2 | 84 | out_unlock: |
f204e0b8 IM |
85 | spin_unlock_irqrestore(&ctx->sste_lock, flags); |
86 | } | |
87 | ||
88 | static int cxl_fault_segment(struct cxl_context *ctx, struct mm_struct *mm, | |
89 | u64 ea) | |
90 | { | |
91 | struct copro_slb slb = {0,0}; | |
92 | int rc; | |
93 | ||
94 | if (!(rc = copro_calculate_slb(mm, ea, &slb))) { | |
95 | cxl_load_segment(ctx, &slb); | |
96 | } | |
97 | ||
98 | return rc; | |
99 | } | |
100 | ||
101 | static void cxl_ack_ae(struct cxl_context *ctx) | |
102 | { | |
103 | unsigned long flags; | |
104 | ||
5be587b1 | 105 | cxl_ops->ack_irq(ctx, CXL_PSL_TFC_An_AE, 0); |
f204e0b8 IM |
106 | |
107 | spin_lock_irqsave(&ctx->lock, flags); | |
108 | ctx->pending_fault = true; | |
109 | ctx->fault_addr = ctx->dar; | |
110 | ctx->fault_dsisr = ctx->dsisr; | |
111 | spin_unlock_irqrestore(&ctx->lock, flags); | |
112 | ||
113 | wake_up_all(&ctx->wq); | |
114 | } | |
115 | ||
116 | static int cxl_handle_segment_miss(struct cxl_context *ctx, | |
117 | struct mm_struct *mm, u64 ea) | |
118 | { | |
119 | int rc; | |
120 | ||
121 | pr_devel("CXL interrupt: Segment fault pe: %i ea: %#llx\n", ctx->pe, ea); | |
9bcf28cd | 122 | trace_cxl_ste_miss(ctx, ea); |
f204e0b8 IM |
123 | |
124 | if ((rc = cxl_fault_segment(ctx, mm, ea))) | |
125 | cxl_ack_ae(ctx); | |
126 | else { | |
127 | ||
128 | mb(); /* Order seg table write to TFC MMIO write */ | |
5be587b1 | 129 | cxl_ops->ack_irq(ctx, CXL_PSL_TFC_An_R, 0); |
f204e0b8 IM |
130 | } |
131 | ||
132 | return IRQ_HANDLED; | |
133 | } | |
134 | ||
135 | static void cxl_handle_page_fault(struct cxl_context *ctx, | |
136 | struct mm_struct *mm, u64 dsisr, u64 dar) | |
137 | { | |
138 | unsigned flt = 0; | |
139 | int result; | |
aefa5688 | 140 | unsigned long access, flags, inv_flags = 0; |
f204e0b8 | 141 | |
9bcf28cd IM |
142 | trace_cxl_pte_miss(ctx, dsisr, dar); |
143 | ||
f204e0b8 IM |
144 | if ((result = copro_handle_mm_fault(mm, dar, dsisr, &flt))) { |
145 | pr_devel("copro_handle_mm_fault failed: %#x\n", result); | |
146 | return cxl_ack_ae(ctx); | |
147 | } | |
148 | ||
f24be42a CL |
149 | if (!radix_enabled()) { |
150 | /* | |
151 | * update_mmu_cache() will not have loaded the hash since current->trap | |
152 | * is not a 0x400 or 0x300, so just call hash_page_mm() here. | |
153 | */ | |
154 | access = _PAGE_PRESENT | _PAGE_READ; | |
155 | if (dsisr & CXL_PSL_DSISR_An_S) | |
156 | access |= _PAGE_WRITE; | |
157 | ||
158 | access |= _PAGE_PRIVILEGED; | |
159 | if ((!ctx->kernel) || (REGION_ID(dar) == USER_REGION_ID)) | |
160 | access &= ~_PAGE_PRIVILEGED; | |
161 | ||
162 | if (dsisr & DSISR_NOHPTE) | |
163 | inv_flags |= HPTE_NOHPTE_UPDATE; | |
164 | ||
165 | local_irq_save(flags); | |
166 | hash_page_mm(mm, dar, access, 0x300, inv_flags); | |
167 | local_irq_restore(flags); | |
168 | } | |
f204e0b8 | 169 | pr_devel("Page fault successfully handled for pe: %i!\n", ctx->pe); |
5be587b1 | 170 | cxl_ops->ack_irq(ctx, CXL_PSL_TFC_An_R, 0); |
f204e0b8 IM |
171 | } |
172 | ||
7b8ad495 | 173 | /* |
6dd2d234 CL |
174 | * Returns the mm_struct corresponding to the context ctx. |
175 | * mm_users == 0, the context may be in the process of being closed. | |
7b8ad495 VJ |
176 | */ |
177 | static struct mm_struct *get_mem_context(struct cxl_context *ctx) | |
178 | { | |
6dd2d234 | 179 | if (ctx->mm == NULL) |
7b8ad495 | 180 | return NULL; |
7b8ad495 | 181 | |
6dd2d234 CL |
182 | if (!atomic_inc_not_zero(&ctx->mm->mm_users)) |
183 | return NULL; | |
7b8ad495 | 184 | |
6dd2d234 | 185 | return ctx->mm; |
7b8ad495 VJ |
186 | } |
187 | ||
f24be42a CL |
188 | static bool cxl_is_segment_miss(struct cxl_context *ctx, u64 dsisr) |
189 | { | |
797625de | 190 | if ((cxl_is_power8() && (dsisr & CXL_PSL_DSISR_An_DS))) |
f24be42a CL |
191 | return true; |
192 | ||
193 | return false; | |
194 | } | |
195 | ||
196 | static bool cxl_is_page_fault(struct cxl_context *ctx, u64 dsisr) | |
197 | { | |
797625de | 198 | u64 crs; /* Translation Checkout Response Status */ |
f24be42a | 199 | |
797625de | 200 | if ((cxl_is_power8()) && (dsisr & CXL_PSL_DSISR_An_DM)) |
f24be42a | 201 | return true; |
7b8ad495 | 202 | |
797625de CL |
203 | if (cxl_is_power9()) { |
204 | crs = (dsisr & CXL_PSL9_DSISR_An_CO_MASK); | |
205 | if ((crs == CXL_PSL9_DSISR_An_PF_SLR) || | |
206 | (crs == CXL_PSL9_DSISR_An_PF_RGC) || | |
207 | (crs == CXL_PSL9_DSISR_An_PF_RGP) || | |
208 | (crs == CXL_PSL9_DSISR_An_PF_HRH) || | |
209 | (crs == CXL_PSL9_DSISR_An_PF_STEG) || | |
210 | (crs == CXL_PSL9_DSISR_An_URTCH)) { | |
211 | return true; | |
212 | } | |
213 | } | |
214 | ||
f24be42a CL |
215 | return false; |
216 | } | |
7b8ad495 | 217 | |
f204e0b8 IM |
218 | void cxl_handle_fault(struct work_struct *fault_work) |
219 | { | |
220 | struct cxl_context *ctx = | |
221 | container_of(fault_work, struct cxl_context, fault_work); | |
222 | u64 dsisr = ctx->dsisr; | |
223 | u64 dar = ctx->dar; | |
a6b07d82 | 224 | struct mm_struct *mm = NULL; |
f204e0b8 | 225 | |
ea2d1f95 FB |
226 | if (cpu_has_feature(CPU_FTR_HVMODE)) { |
227 | if (cxl_p2n_read(ctx->afu, CXL_PSL_DSISR_An) != dsisr || | |
228 | cxl_p2n_read(ctx->afu, CXL_PSL_DAR_An) != dar || | |
229 | cxl_p2n_read(ctx->afu, CXL_PSL_PEHandle_An) != ctx->pe) { | |
230 | /* Most likely explanation is harmless - a dedicated | |
231 | * process has detached and these were cleared by the | |
232 | * PSL purge, but warn about it just in case | |
233 | */ | |
234 | dev_notice(&ctx->afu->dev, "cxl_handle_fault: Translation fault regs changed\n"); | |
235 | return; | |
236 | } | |
f204e0b8 IM |
237 | } |
238 | ||
13da7046 IM |
239 | /* Early return if the context is being / has been detached */ |
240 | if (ctx->status == CLOSED) { | |
241 | cxl_ack_ae(ctx); | |
242 | return; | |
243 | } | |
244 | ||
f204e0b8 IM |
245 | pr_devel("CXL BOTTOM HALF handling fault for afu pe: %i. " |
246 | "DSISR: %#llx DAR: %#llx\n", ctx->pe, dsisr, dar); | |
247 | ||
a6b07d82 | 248 | if (!ctx->kernel) { |
7b8ad495 VJ |
249 | |
250 | mm = get_mem_context(ctx); | |
7b8ad495 VJ |
251 | if (mm == NULL) { |
252 | pr_devel("%s: unable to get mm for pe=%d pid=%i\n", | |
253 | __func__, ctx->pe, pid_nr(ctx->pid)); | |
a6b07d82 MN |
254 | cxl_ack_ae(ctx); |
255 | return; | |
7b8ad495 VJ |
256 | } else { |
257 | pr_devel("Handling page fault for pe=%d pid=%i\n", | |
258 | ctx->pe, pid_nr(ctx->pid)); | |
a6b07d82 | 259 | } |
f204e0b8 IM |
260 | } |
261 | ||
f24be42a | 262 | if (cxl_is_segment_miss(ctx, dsisr)) |
f204e0b8 | 263 | cxl_handle_segment_miss(ctx, mm, dar); |
f24be42a | 264 | else if (cxl_is_page_fault(ctx, dsisr)) |
f204e0b8 IM |
265 | cxl_handle_page_fault(ctx, mm, dsisr, dar); |
266 | else | |
267 | WARN(1, "cxl_handle_fault has nothing to handle\n"); | |
268 | ||
a6b07d82 MN |
269 | if (mm) |
270 | mmput(mm); | |
f204e0b8 IM |
271 | } |
272 | ||
273 | static void cxl_prefault_one(struct cxl_context *ctx, u64 ea) | |
274 | { | |
f204e0b8 IM |
275 | struct mm_struct *mm; |
276 | ||
7b8ad495 VJ |
277 | mm = get_mem_context(ctx); |
278 | if (mm == NULL) { | |
f204e0b8 IM |
279 | pr_devel("cxl_prefault_one unable to get mm %i\n", |
280 | pid_nr(ctx->pid)); | |
f204e0b8 IM |
281 | return; |
282 | } | |
283 | ||
7b8ad495 | 284 | cxl_fault_segment(ctx, mm, ea); |
f204e0b8 IM |
285 | |
286 | mmput(mm); | |
f204e0b8 IM |
287 | } |
288 | ||
289 | static u64 next_segment(u64 ea, u64 vsid) | |
290 | { | |
291 | if (vsid & SLB_VSID_B_1T) | |
292 | ea |= (1ULL << 40) - 1; | |
293 | else | |
294 | ea |= (1ULL << 28) - 1; | |
295 | ||
296 | return ea + 1; | |
297 | } | |
298 | ||
299 | static void cxl_prefault_vma(struct cxl_context *ctx) | |
300 | { | |
301 | u64 ea, last_esid = 0; | |
302 | struct copro_slb slb; | |
303 | struct vm_area_struct *vma; | |
304 | int rc; | |
f204e0b8 IM |
305 | struct mm_struct *mm; |
306 | ||
7b8ad495 VJ |
307 | mm = get_mem_context(ctx); |
308 | if (mm == NULL) { | |
f204e0b8 IM |
309 | pr_devel("cxl_prefault_vm unable to get mm %i\n", |
310 | pid_nr(ctx->pid)); | |
7b8ad495 | 311 | return; |
f204e0b8 IM |
312 | } |
313 | ||
314 | down_read(&mm->mmap_sem); | |
315 | for (vma = mm->mmap; vma; vma = vma->vm_next) { | |
316 | for (ea = vma->vm_start; ea < vma->vm_end; | |
317 | ea = next_segment(ea, slb.vsid)) { | |
318 | rc = copro_calculate_slb(mm, ea, &slb); | |
319 | if (rc) | |
320 | continue; | |
321 | ||
322 | if (last_esid == slb.esid) | |
323 | continue; | |
324 | ||
325 | cxl_load_segment(ctx, &slb); | |
326 | last_esid = slb.esid; | |
327 | } | |
328 | } | |
329 | up_read(&mm->mmap_sem); | |
330 | ||
331 | mmput(mm); | |
f204e0b8 IM |
332 | } |
333 | ||
334 | void cxl_prefault(struct cxl_context *ctx, u64 wed) | |
335 | { | |
336 | switch (ctx->afu->prefault_mode) { | |
337 | case CXL_PREFAULT_WED: | |
338 | cxl_prefault_one(ctx, wed); | |
339 | break; | |
340 | case CXL_PREFAULT_ALL: | |
341 | cxl_prefault_vma(ctx); | |
342 | break; | |
343 | default: | |
344 | break; | |
345 | } | |
346 | } |