Commit | Line | Data |
---|---|---|
01ed260f MB |
1 | /* |
2 | * wm8994-regmap.c -- Register map data for WM8994 series devices | |
3 | * | |
4 | * Copyright 2011 Wolfson Microelectronics PLC. | |
5 | * | |
6 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | */ | |
14 | ||
15 | #include <linux/mfd/wm8994/registers.h> | |
16 | #include <linux/regmap.h> | |
17 | ||
18 | #include "wm8994.h" | |
19 | ||
20 | static struct reg_default wm1811_defaults[] = { | |
21 | { 0x0000, 0x1811 }, /* R0 - Software Reset */ | |
22 | { 0x0001, 0x0000 }, /* R1 - Power Management (1) */ | |
23 | { 0x0002, 0x6000 }, /* R2 - Power Management (2) */ | |
24 | { 0x0003, 0x0000 }, /* R3 - Power Management (3) */ | |
25 | { 0x0004, 0x0000 }, /* R4 - Power Management (4) */ | |
26 | { 0x0005, 0x0000 }, /* R5 - Power Management (5) */ | |
27 | { 0x0006, 0x0000 }, /* R6 - Power Management (6) */ | |
28 | { 0x0015, 0x0000 }, /* R21 - Input Mixer (1) */ | |
29 | { 0x0018, 0x008B }, /* R24 - Left Line Input 1&2 Volume */ | |
30 | { 0x0019, 0x008B }, /* R25 - Left Line Input 3&4 Volume */ | |
31 | { 0x001A, 0x008B }, /* R26 - Right Line Input 1&2 Volume */ | |
32 | { 0x001B, 0x008B }, /* R27 - Right Line Input 3&4 Volume */ | |
33 | { 0x001C, 0x006D }, /* R28 - Left Output Volume */ | |
34 | { 0x001D, 0x006D }, /* R29 - Right Output Volume */ | |
35 | { 0x001E, 0x0066 }, /* R30 - Line Outputs Volume */ | |
36 | { 0x001F, 0x0020 }, /* R31 - HPOUT2 Volume */ | |
37 | { 0x0020, 0x0079 }, /* R32 - Left OPGA Volume */ | |
38 | { 0x0021, 0x0079 }, /* R33 - Right OPGA Volume */ | |
39 | { 0x0022, 0x0003 }, /* R34 - SPKMIXL Attenuation */ | |
40 | { 0x0023, 0x0003 }, /* R35 - SPKMIXR Attenuation */ | |
41 | { 0x0024, 0x0011 }, /* R36 - SPKOUT Mixers */ | |
42 | { 0x0025, 0x0140 }, /* R37 - ClassD */ | |
43 | { 0x0026, 0x0079 }, /* R38 - Speaker Volume Left */ | |
44 | { 0x0027, 0x0079 }, /* R39 - Speaker Volume Right */ | |
45 | { 0x0028, 0x0000 }, /* R40 - Input Mixer (2) */ | |
46 | { 0x0029, 0x0000 }, /* R41 - Input Mixer (3) */ | |
47 | { 0x002A, 0x0000 }, /* R42 - Input Mixer (4) */ | |
48 | { 0x002B, 0x0000 }, /* R43 - Input Mixer (5) */ | |
49 | { 0x002C, 0x0000 }, /* R44 - Input Mixer (6) */ | |
50 | { 0x002D, 0x0000 }, /* R45 - Output Mixer (1) */ | |
51 | { 0x002E, 0x0000 }, /* R46 - Output Mixer (2) */ | |
52 | { 0x002F, 0x0000 }, /* R47 - Output Mixer (3) */ | |
53 | { 0x0030, 0x0000 }, /* R48 - Output Mixer (4) */ | |
54 | { 0x0031, 0x0000 }, /* R49 - Output Mixer (5) */ | |
55 | { 0x0032, 0x0000 }, /* R50 - Output Mixer (6) */ | |
56 | { 0x0033, 0x0000 }, /* R51 - HPOUT2 Mixer */ | |
57 | { 0x0034, 0x0000 }, /* R52 - Line Mixer (1) */ | |
58 | { 0x0035, 0x0000 }, /* R53 - Line Mixer (2) */ | |
59 | { 0x0036, 0x0000 }, /* R54 - Speaker Mixer */ | |
60 | { 0x0037, 0x0000 }, /* R55 - Additional Control */ | |
61 | { 0x0038, 0x0000 }, /* R56 - AntiPOP (1) */ | |
62 | { 0x0039, 0x0180 }, /* R57 - AntiPOP (2) */ | |
63 | { 0x003B, 0x000D }, /* R59 - LDO 1 */ | |
64 | { 0x003C, 0x0003 }, /* R60 - LDO 2 */ | |
65 | { 0x003D, 0x0039 }, /* R61 - MICBIAS1 */ | |
66 | { 0x003E, 0x0039 }, /* R62 - MICBIAS2 */ | |
67 | { 0x004C, 0x1F25 }, /* R76 - Charge Pump (1) */ | |
68 | { 0x004D, 0xAB19 }, /* R77 - Charge Pump (2) */ | |
69 | { 0x0051, 0x0004 }, /* R81 - Class W (1) */ | |
70 | { 0x0054, 0x0000 }, /* R84 - DC Servo (1) */ | |
71 | { 0x0055, 0x054A }, /* R85 - DC Servo (2) */ | |
72 | { 0x0058, 0x0000 }, /* R88 - DC Servo Readback */ | |
73 | { 0x0059, 0x0000 }, /* R89 - DC Servo (4) */ | |
74 | { 0x0060, 0x0000 }, /* R96 - Analogue HP (1) */ | |
75 | { 0x00C5, 0x0000 }, /* R197 - Class D Test (5) */ | |
76 | { 0x00D0, 0x7600 }, /* R208 - Mic Detect 1 */ | |
77 | { 0x00D1, 0x007F }, /* R209 - Mic Detect 2 */ | |
78 | { 0x00D2, 0x0000 }, /* R210 - Mic Detect 3 */ | |
79 | { 0x0100, 0x0100 }, /* R256 - Chip Revision */ | |
80 | { 0x0101, 0x8004 }, /* R257 - Control Interface */ | |
81 | { 0x0200, 0x0000 }, /* R512 - AIF1 Clocking (1) */ | |
82 | { 0x0201, 0x0000 }, /* R513 - AIF1 Clocking (2) */ | |
83 | { 0x0204, 0x0000 }, /* R516 - AIF2 Clocking (1) */ | |
84 | { 0x0205, 0x0000 }, /* R517 - AIF2 Clocking (2) */ | |
85 | { 0x0208, 0x0000 }, /* R520 - Clocking (1) */ | |
86 | { 0x0209, 0x0000 }, /* R521 - Clocking (2) */ | |
87 | { 0x0210, 0x0083 }, /* R528 - AIF1 Rate */ | |
88 | { 0x0211, 0x0083 }, /* R529 - AIF2 Rate */ | |
89 | { 0x0212, 0x0000 }, /* R530 - Rate Status */ | |
90 | { 0x0220, 0x0000 }, /* R544 - FLL1 Control (1) */ | |
91 | { 0x0221, 0x0000 }, /* R545 - FLL1 Control (2) */ | |
92 | { 0x0222, 0x0000 }, /* R546 - FLL1 Control (3) */ | |
93 | { 0x0223, 0x0000 }, /* R547 - FLL1 Control (4) */ | |
94 | { 0x0224, 0x0C80 }, /* R548 - FLL1 Control (5) */ | |
95 | { 0x0226, 0x0000 }, /* R550 - FLL1 EFS 1 */ | |
96 | { 0x0227, 0x0006 }, /* R551 - FLL1 EFS 2 */ | |
97 | { 0x0240, 0x0000 }, /* R576 - FLL2Control (1) */ | |
98 | { 0x0241, 0x0000 }, /* R577 - FLL2Control (2) */ | |
99 | { 0x0242, 0x0000 }, /* R578 - FLL2Control (3) */ | |
100 | { 0x0243, 0x0000 }, /* R579 - FLL2 Control (4) */ | |
101 | { 0x0244, 0x0C80 }, /* R580 - FLL2Control (5) */ | |
102 | { 0x0246, 0x0000 }, /* R582 - FLL2 EFS 1 */ | |
103 | { 0x0247, 0x0006 }, /* R583 - FLL2 EFS 2 */ | |
104 | { 0x0300, 0x4050 }, /* R768 - AIF1 Control (1) */ | |
105 | { 0x0301, 0x4000 }, /* R769 - AIF1 Control (2) */ | |
106 | { 0x0302, 0x0000 }, /* R770 - AIF1 Master/Slave */ | |
107 | { 0x0303, 0x0040 }, /* R771 - AIF1 BCLK */ | |
108 | { 0x0304, 0x0040 }, /* R772 - AIF1ADC LRCLK */ | |
109 | { 0x0305, 0x0040 }, /* R773 - AIF1DAC LRCLK */ | |
110 | { 0x0306, 0x0004 }, /* R774 - AIF1DAC Data */ | |
111 | { 0x0307, 0x0100 }, /* R775 - AIF1ADC Data */ | |
112 | { 0x0310, 0x4050 }, /* R784 - AIF2 Control (1) */ | |
113 | { 0x0311, 0x4000 }, /* R785 - AIF2 Control (2) */ | |
114 | { 0x0312, 0x0000 }, /* R786 - AIF2 Master/Slave */ | |
115 | { 0x0313, 0x0040 }, /* R787 - AIF2 BCLK */ | |
116 | { 0x0314, 0x0040 }, /* R788 - AIF2ADC LRCLK */ | |
117 | { 0x0315, 0x0040 }, /* R789 - AIF2DAC LRCLK */ | |
118 | { 0x0316, 0x0000 }, /* R790 - AIF2DAC Data */ | |
119 | { 0x0317, 0x0000 }, /* R791 - AIF2ADC Data */ | |
120 | { 0x0318, 0x0003 }, /* R792 - AIF2TX Control */ | |
121 | { 0x0320, 0x0040 }, /* R800 - AIF3 Control (1) */ | |
122 | { 0x0321, 0x0000 }, /* R801 - AIF3 Control (2) */ | |
123 | { 0x0322, 0x0000 }, /* R802 - AIF3DAC Data */ | |
124 | { 0x0323, 0x0000 }, /* R803 - AIF3ADC Data */ | |
125 | { 0x0400, 0x00C0 }, /* R1024 - AIF1 ADC1 Left Volume */ | |
126 | { 0x0401, 0x00C0 }, /* R1025 - AIF1 ADC1 Right Volume */ | |
127 | { 0x0402, 0x00C0 }, /* R1026 - AIF1 DAC1 Left Volume */ | |
128 | { 0x0403, 0x00C0 }, /* R1027 - AIF1 DAC1 Right Volume */ | |
129 | { 0x0410, 0x0000 }, /* R1040 - AIF1 ADC1 Filters */ | |
130 | { 0x0420, 0x0200 }, /* R1056 - AIF1 DAC1 Filters (1) */ | |
131 | { 0x0421, 0x0010 }, /* R1057 - AIF1 DAC1 Filters (2) */ | |
132 | { 0x0430, 0x0068 }, /* R1072 - AIF1 DAC1 Noise Gate */ | |
133 | { 0x0440, 0x0098 }, /* R1088 - AIF1 DRC1 (1) */ | |
134 | { 0x0441, 0x0845 }, /* R1089 - AIF1 DRC1 (2) */ | |
135 | { 0x0442, 0x0000 }, /* R1090 - AIF1 DRC1 (3) */ | |
136 | { 0x0443, 0x0000 }, /* R1091 - AIF1 DRC1 (4) */ | |
137 | { 0x0444, 0x0000 }, /* R1092 - AIF1 DRC1 (5) */ | |
138 | { 0x0480, 0x6318 }, /* R1152 - AIF1 DAC1 EQ Gains (1) */ | |
139 | { 0x0481, 0x6300 }, /* R1153 - AIF1 DAC1 EQ Gains (2) */ | |
140 | { 0x0482, 0x0FCA }, /* R1154 - AIF1 DAC1 EQ Band 1 A */ | |
141 | { 0x0483, 0x0400 }, /* R1155 - AIF1 DAC1 EQ Band 1 B */ | |
142 | { 0x0484, 0x00D8 }, /* R1156 - AIF1 DAC1 EQ Band 1 PG */ | |
143 | { 0x0485, 0x1EB5 }, /* R1157 - AIF1 DAC1 EQ Band 2 A */ | |
144 | { 0x0486, 0xF145 }, /* R1158 - AIF1 DAC1 EQ Band 2 B */ | |
145 | { 0x0487, 0x0B75 }, /* R1159 - AIF1 DAC1 EQ Band 2 C */ | |
146 | { 0x0488, 0x01C5 }, /* R1160 - AIF1 DAC1 EQ Band 2 PG */ | |
147 | { 0x0489, 0x1C58 }, /* R1161 - AIF1 DAC1 EQ Band 3 A */ | |
148 | { 0x048A, 0xF373 }, /* R1162 - AIF1 DAC1 EQ Band 3 B */ | |
149 | { 0x048B, 0x0A54 }, /* R1163 - AIF1 DAC1 EQ Band 3 C */ | |
150 | { 0x048C, 0x0558 }, /* R1164 - AIF1 DAC1 EQ Band 3 PG */ | |
151 | { 0x048D, 0x168E }, /* R1165 - AIF1 DAC1 EQ Band 4 A */ | |
152 | { 0x048E, 0xF829 }, /* R1166 - AIF1 DAC1 EQ Band 4 B */ | |
153 | { 0x048F, 0x07AD }, /* R1167 - AIF1 DAC1 EQ Band 4 C */ | |
154 | { 0x0490, 0x1103 }, /* R1168 - AIF1 DAC1 EQ Band 4 PG */ | |
155 | { 0x0491, 0x0564 }, /* R1169 - AIF1 DAC1 EQ Band 5 A */ | |
156 | { 0x0492, 0x0559 }, /* R1170 - AIF1 DAC1 EQ Band 5 B */ | |
157 | { 0x0493, 0x4000 }, /* R1171 - AIF1 DAC1 EQ Band 5 PG */ | |
158 | { 0x0494, 0x0000 }, /* R1172 - AIF1 DAC1 EQ Band 1 C */ | |
159 | { 0x0500, 0x00C0 }, /* R1280 - AIF2 ADC Left Volume */ | |
160 | { 0x0501, 0x00C0 }, /* R1281 - AIF2 ADC Right Volume */ | |
161 | { 0x0502, 0x00C0 }, /* R1282 - AIF2 DAC Left Volume */ | |
162 | { 0x0503, 0x00C0 }, /* R1283 - AIF2 DAC Right Volume */ | |
163 | { 0x0510, 0x0000 }, /* R1296 - AIF2 ADC Filters */ | |
164 | { 0x0520, 0x0200 }, /* R1312 - AIF2 DAC Filters (1) */ | |
165 | { 0x0521, 0x0010 }, /* R1313 - AIF2 DAC Filters (2) */ | |
166 | { 0x0530, 0x0068 }, /* R1328 - AIF2 DAC Noise Gate */ | |
167 | { 0x0540, 0x0098 }, /* R1344 - AIF2 DRC (1) */ | |
168 | { 0x0541, 0x0845 }, /* R1345 - AIF2 DRC (2) */ | |
169 | { 0x0542, 0x0000 }, /* R1346 - AIF2 DRC (3) */ | |
170 | { 0x0543, 0x0000 }, /* R1347 - AIF2 DRC (4) */ | |
171 | { 0x0544, 0x0000 }, /* R1348 - AIF2 DRC (5) */ | |
172 | { 0x0580, 0x6318 }, /* R1408 - AIF2 EQ Gains (1) */ | |
173 | { 0x0581, 0x6300 }, /* R1409 - AIF2 EQ Gains (2) */ | |
174 | { 0x0582, 0x0FCA }, /* R1410 - AIF2 EQ Band 1 A */ | |
175 | { 0x0583, 0x0400 }, /* R1411 - AIF2 EQ Band 1 B */ | |
176 | { 0x0584, 0x00D8 }, /* R1412 - AIF2 EQ Band 1 PG */ | |
177 | { 0x0585, 0x1EB5 }, /* R1413 - AIF2 EQ Band 2 A */ | |
178 | { 0x0586, 0xF145 }, /* R1414 - AIF2 EQ Band 2 B */ | |
179 | { 0x0587, 0x0B75 }, /* R1415 - AIF2 EQ Band 2 C */ | |
180 | { 0x0588, 0x01C5 }, /* R1416 - AIF2 EQ Band 2 PG */ | |
181 | { 0x0589, 0x1C58 }, /* R1417 - AIF2 EQ Band 3 A */ | |
182 | { 0x058A, 0xF373 }, /* R1418 - AIF2 EQ Band 3 B */ | |
183 | { 0x058B, 0x0A54 }, /* R1419 - AIF2 EQ Band 3 C */ | |
184 | { 0x058C, 0x0558 }, /* R1420 - AIF2 EQ Band 3 PG */ | |
185 | { 0x058D, 0x168E }, /* R1421 - AIF2 EQ Band 4 A */ | |
186 | { 0x058E, 0xF829 }, /* R1422 - AIF2 EQ Band 4 B */ | |
187 | { 0x058F, 0x07AD }, /* R1423 - AIF2 EQ Band 4 C */ | |
188 | { 0x0590, 0x1103 }, /* R1424 - AIF2 EQ Band 4 PG */ | |
189 | { 0x0591, 0x0564 }, /* R1425 - AIF2 EQ Band 5 A */ | |
190 | { 0x0592, 0x0559 }, /* R1426 - AIF2 EQ Band 5 B */ | |
191 | { 0x0593, 0x4000 }, /* R1427 - AIF2 EQ Band 5 PG */ | |
192 | { 0x0594, 0x0000 }, /* R1428 - AIF2 EQ Band 1 C */ | |
193 | { 0x0600, 0x0000 }, /* R1536 - DAC1 Mixer Volumes */ | |
194 | { 0x0601, 0x0000 }, /* R1537 - DAC1 Left Mixer Routing */ | |
195 | { 0x0602, 0x0000 }, /* R1538 - DAC1 Right Mixer Routing */ | |
196 | { 0x0603, 0x0000 }, /* R1539 - AIF2ADC Mixer Volumes */ | |
197 | { 0x0604, 0x0000 }, /* R1540 - AIF2ADC Left Mixer Routing */ | |
198 | { 0x0605, 0x0000 }, /* R1541 - AIF2ADC Right Mixer Routing */ | |
199 | { 0x0606, 0x0000 }, /* R1542 - AIF1 ADC1 Left Mixer Routing */ | |
200 | { 0x0607, 0x0000 }, /* R1543 - AIF1 ADC1 Right Mixer Routing */ | |
201 | { 0x0610, 0x02C0 }, /* R1552 - DAC1 Left Volume */ | |
202 | { 0x0611, 0x02C0 }, /* R1553 - DAC1 Right Volume */ | |
203 | { 0x0612, 0x02C0 }, /* R1554 - AIF2TX Left Volume */ | |
204 | { 0x0613, 0x02C0 }, /* R1555 - AIF2TX Right Volume */ | |
205 | { 0x0614, 0x0000 }, /* R1556 - DAC Softmute */ | |
206 | { 0x0620, 0x0002 }, /* R1568 - Oversampling */ | |
207 | { 0x0621, 0x0000 }, /* R1569 - Sidetone */ | |
208 | { 0x0700, 0x8100 }, /* R1792 - GPIO 1 */ | |
209 | { 0x0701, 0xA101 }, /* R1793 - Pull Control (MCLK2) */ | |
210 | { 0x0702, 0xA101 }, /* R1794 - Pull Control (BCLK2) */ | |
211 | { 0x0703, 0xA101 }, /* R1795 - Pull Control (DACLRCLK2) */ | |
212 | { 0x0704, 0xA101 }, /* R1796 - Pull Control (DACDAT2) */ | |
213 | { 0x0705, 0xA101 }, /* R1797 - GPIO 6 */ | |
214 | { 0x0707, 0xA101 }, /* R1799 - GPIO 8 */ | |
215 | { 0x0708, 0xA101 }, /* R1800 - GPIO 9 */ | |
216 | { 0x0709, 0xA101 }, /* R1801 - GPIO 10 */ | |
217 | { 0x070A, 0xA101 }, /* R1802 - GPIO 11 */ | |
218 | { 0x0720, 0x0000 }, /* R1824 - Pull Control (1) */ | |
219 | { 0x0721, 0x0156 }, /* R1825 - Pull Control (2) */ | |
220 | { 0x0730, 0x0000 }, /* R1840 - Interrupt Status 1 */ | |
221 | { 0x0731, 0x0000 }, /* R1841 - Interrupt Status 2 */ | |
222 | { 0x0732, 0x0000 }, /* R1842 - Interrupt Raw Status 2 */ | |
223 | { 0x0738, 0x07FF }, /* R1848 - Interrupt Status 1 Mask */ | |
224 | { 0x0739, 0xDFEF }, /* R1849 - Interrupt Status 2 Mask */ | |
225 | { 0x0740, 0x0000 }, /* R1856 - Interrupt Control */ | |
226 | { 0x0748, 0x003F }, /* R1864 - IRQ Debounce */ | |
227 | }; | |
228 | ||
229 | static struct reg_default wm8994_defaults[] = { | |
230 | { 0x0000, 0x8994 }, /* R0 - Software Reset */ | |
231 | { 0x0001, 0x0000 }, /* R1 - Power Management (1) */ | |
232 | { 0x0002, 0x6000 }, /* R2 - Power Management (2) */ | |
233 | { 0x0003, 0x0000 }, /* R3 - Power Management (3) */ | |
234 | { 0x0004, 0x0000 }, /* R4 - Power Management (4) */ | |
235 | { 0x0005, 0x0000 }, /* R5 - Power Management (5) */ | |
236 | { 0x0006, 0x0000 }, /* R6 - Power Management (6) */ | |
237 | { 0x0015, 0x0000 }, /* R21 - Input Mixer (1) */ | |
238 | { 0x0018, 0x008B }, /* R24 - Left Line Input 1&2 Volume */ | |
239 | { 0x0019, 0x008B }, /* R25 - Left Line Input 3&4 Volume */ | |
240 | { 0x001A, 0x008B }, /* R26 - Right Line Input 1&2 Volume */ | |
241 | { 0x001B, 0x008B }, /* R27 - Right Line Input 3&4 Volume */ | |
242 | { 0x001C, 0x006D }, /* R28 - Left Output Volume */ | |
243 | { 0x001D, 0x006D }, /* R29 - Right Output Volume */ | |
244 | { 0x001E, 0x0066 }, /* R30 - Line Outputs Volume */ | |
245 | { 0x001F, 0x0020 }, /* R31 - HPOUT2 Volume */ | |
246 | { 0x0020, 0x0079 }, /* R32 - Left OPGA Volume */ | |
247 | { 0x0021, 0x0079 }, /* R33 - Right OPGA Volume */ | |
248 | { 0x0022, 0x0003 }, /* R34 - SPKMIXL Attenuation */ | |
249 | { 0x0023, 0x0003 }, /* R35 - SPKMIXR Attenuation */ | |
250 | { 0x0024, 0x0011 }, /* R36 - SPKOUT Mixers */ | |
251 | { 0x0025, 0x0140 }, /* R37 - ClassD */ | |
252 | { 0x0026, 0x0079 }, /* R38 - Speaker Volume Left */ | |
253 | { 0x0027, 0x0079 }, /* R39 - Speaker Volume Right */ | |
254 | { 0x0028, 0x0000 }, /* R40 - Input Mixer (2) */ | |
255 | { 0x0029, 0x0000 }, /* R41 - Input Mixer (3) */ | |
256 | { 0x002A, 0x0000 }, /* R42 - Input Mixer (4) */ | |
257 | { 0x002B, 0x0000 }, /* R43 - Input Mixer (5) */ | |
258 | { 0x002C, 0x0000 }, /* R44 - Input Mixer (6) */ | |
259 | { 0x002D, 0x0000 }, /* R45 - Output Mixer (1) */ | |
260 | { 0x002E, 0x0000 }, /* R46 - Output Mixer (2) */ | |
261 | { 0x002F, 0x0000 }, /* R47 - Output Mixer (3) */ | |
262 | { 0x0030, 0x0000 }, /* R48 - Output Mixer (4) */ | |
263 | { 0x0031, 0x0000 }, /* R49 - Output Mixer (5) */ | |
264 | { 0x0032, 0x0000 }, /* R50 - Output Mixer (6) */ | |
265 | { 0x0033, 0x0000 }, /* R51 - HPOUT2 Mixer */ | |
266 | { 0x0034, 0x0000 }, /* R52 - Line Mixer (1) */ | |
267 | { 0x0035, 0x0000 }, /* R53 - Line Mixer (2) */ | |
268 | { 0x0036, 0x0000 }, /* R54 - Speaker Mixer */ | |
269 | { 0x0037, 0x0000 }, /* R55 - Additional Control */ | |
270 | { 0x0038, 0x0000 }, /* R56 - AntiPOP (1) */ | |
271 | { 0x0039, 0x0000 }, /* R57 - AntiPOP (2) */ | |
272 | { 0x003A, 0x0000 }, /* R58 - MICBIAS */ | |
273 | { 0x003B, 0x000D }, /* R59 - LDO 1 */ | |
274 | { 0x003C, 0x0003 }, /* R60 - LDO 2 */ | |
275 | { 0x004C, 0x1F25 }, /* R76 - Charge Pump (1) */ | |
276 | { 0x0051, 0x0004 }, /* R81 - Class W (1) */ | |
277 | { 0x0054, 0x0000 }, /* R84 - DC Servo (1) */ | |
278 | { 0x0055, 0x054A }, /* R85 - DC Servo (2) */ | |
279 | { 0x0057, 0x0000 }, /* R87 - DC Servo (4) */ | |
280 | { 0x0058, 0x0000 }, /* R88 - DC Servo Readback */ | |
281 | { 0x0060, 0x0000 }, /* R96 - Analogue HP (1) */ | |
282 | { 0x0100, 0x0003 }, /* R256 - Chip Revision */ | |
283 | { 0x0101, 0x8004 }, /* R257 - Control Interface */ | |
284 | { 0x0110, 0x0000 }, /* R272 - Write Sequencer Ctrl (1) */ | |
285 | { 0x0111, 0x0000 }, /* R273 - Write Sequencer Ctrl (2) */ | |
286 | { 0x0200, 0x0000 }, /* R512 - AIF1 Clocking (1) */ | |
287 | { 0x0201, 0x0000 }, /* R513 - AIF1 Clocking (2) */ | |
288 | { 0x0204, 0x0000 }, /* R516 - AIF2 Clocking (1) */ | |
289 | { 0x0205, 0x0000 }, /* R517 - AIF2 Clocking (2) */ | |
290 | { 0x0208, 0x0000 }, /* R520 - Clocking (1) */ | |
291 | { 0x0209, 0x0000 }, /* R521 - Clocking (2) */ | |
292 | { 0x0210, 0x0083 }, /* R528 - AIF1 Rate */ | |
293 | { 0x0211, 0x0083 }, /* R529 - AIF2 Rate */ | |
294 | { 0x0212, 0x0000 }, /* R530 - Rate Status */ | |
295 | { 0x0220, 0x0000 }, /* R544 - FLL1 Control (1) */ | |
296 | { 0x0221, 0x0000 }, /* R545 - FLL1 Control (2) */ | |
297 | { 0x0222, 0x0000 }, /* R546 - FLL1 Control (3) */ | |
298 | { 0x0223, 0x0000 }, /* R547 - FLL1 Control (4) */ | |
299 | { 0x0224, 0x0C80 }, /* R548 - FLL1 Control (5) */ | |
300 | { 0x0240, 0x0000 }, /* R576 - FLL2 Control (1) */ | |
301 | { 0x0241, 0x0000 }, /* R577 - FLL2 Control (2) */ | |
302 | { 0x0242, 0x0000 }, /* R578 - FLL2 Control (3) */ | |
303 | { 0x0243, 0x0000 }, /* R579 - FLL2 Control (4) */ | |
304 | { 0x0244, 0x0C80 }, /* R580 - FLL2 Control (5) */ | |
305 | { 0x0300, 0x4050 }, /* R768 - AIF1 Control (1) */ | |
306 | { 0x0301, 0x4000 }, /* R769 - AIF1 Control (2) */ | |
307 | { 0x0302, 0x0000 }, /* R770 - AIF1 Master/Slave */ | |
308 | { 0x0303, 0x0040 }, /* R771 - AIF1 BCLK */ | |
309 | { 0x0304, 0x0040 }, /* R772 - AIF1ADC LRCLK */ | |
310 | { 0x0305, 0x0040 }, /* R773 - AIF1DAC LRCLK */ | |
311 | { 0x0306, 0x0004 }, /* R774 - AIF1DAC Data */ | |
312 | { 0x0307, 0x0100 }, /* R775 - AIF1ADC Data */ | |
313 | { 0x0310, 0x4050 }, /* R784 - AIF2 Control (1) */ | |
314 | { 0x0311, 0x4000 }, /* R785 - AIF2 Control (2) */ | |
315 | { 0x0312, 0x0000 }, /* R786 - AIF2 Master/Slave */ | |
316 | { 0x0313, 0x0040 }, /* R787 - AIF2 BCLK */ | |
317 | { 0x0314, 0x0040 }, /* R788 - AIF2ADC LRCLK */ | |
318 | { 0x0315, 0x0040 }, /* R789 - AIF2DAC LRCLK */ | |
319 | { 0x0316, 0x0000 }, /* R790 - AIF2DAC Data */ | |
320 | { 0x0317, 0x0000 }, /* R791 - AIF2ADC Data */ | |
321 | { 0x0400, 0x00C0 }, /* R1024 - AIF1 ADC1 Left Volume */ | |
322 | { 0x0401, 0x00C0 }, /* R1025 - AIF1 ADC1 Right Volume */ | |
323 | { 0x0402, 0x00C0 }, /* R1026 - AIF1 DAC1 Left Volume */ | |
324 | { 0x0403, 0x00C0 }, /* R1027 - AIF1 DAC1 Right Volume */ | |
325 | { 0x0404, 0x00C0 }, /* R1028 - AIF1 ADC2 Left Volume */ | |
326 | { 0x0405, 0x00C0 }, /* R1029 - AIF1 ADC2 Right Volume */ | |
327 | { 0x0406, 0x00C0 }, /* R1030 - AIF1 DAC2 Left Volume */ | |
328 | { 0x0407, 0x00C0 }, /* R1031 - AIF1 DAC2 Right Volume */ | |
329 | { 0x0410, 0x0000 }, /* R1040 - AIF1 ADC1 Filters */ | |
330 | { 0x0411, 0x0000 }, /* R1041 - AIF1 ADC2 Filters */ | |
331 | { 0x0420, 0x0200 }, /* R1056 - AIF1 DAC1 Filters (1) */ | |
332 | { 0x0421, 0x0010 }, /* R1057 - AIF1 DAC1 Filters (2) */ | |
333 | { 0x0422, 0x0200 }, /* R1058 - AIF1 DAC2 Filters (1) */ | |
334 | { 0x0423, 0x0010 }, /* R1059 - AIF1 DAC2 Filters (2) */ | |
335 | { 0x0440, 0x0098 }, /* R1088 - AIF1 DRC1 (1) */ | |
336 | { 0x0441, 0x0845 }, /* R1089 - AIF1 DRC1 (2) */ | |
337 | { 0x0442, 0x0000 }, /* R1090 - AIF1 DRC1 (3) */ | |
338 | { 0x0443, 0x0000 }, /* R1091 - AIF1 DRC1 (4) */ | |
339 | { 0x0444, 0x0000 }, /* R1092 - AIF1 DRC1 (5) */ | |
340 | { 0x0450, 0x0098 }, /* R1104 - AIF1 DRC2 (1) */ | |
341 | { 0x0451, 0x0845 }, /* R1105 - AIF1 DRC2 (2) */ | |
342 | { 0x0452, 0x0000 }, /* R1106 - AIF1 DRC2 (3) */ | |
343 | { 0x0453, 0x0000 }, /* R1107 - AIF1 DRC2 (4) */ | |
344 | { 0x0454, 0x0000 }, /* R1108 - AIF1 DRC2 (5) */ | |
345 | { 0x0480, 0x6318 }, /* R1152 - AIF1 DAC1 EQ Gains (1) */ | |
346 | { 0x0481, 0x6300 }, /* R1153 - AIF1 DAC1 EQ Gains (2) */ | |
347 | { 0x0482, 0x0FCA }, /* R1154 - AIF1 DAC1 EQ Band 1 A */ | |
348 | { 0x0483, 0x0400 }, /* R1155 - AIF1 DAC1 EQ Band 1 B */ | |
349 | { 0x0484, 0x00D8 }, /* R1156 - AIF1 DAC1 EQ Band 1 PG */ | |
350 | { 0x0485, 0x1EB5 }, /* R1157 - AIF1 DAC1 EQ Band 2 A */ | |
351 | { 0x0486, 0xF145 }, /* R1158 - AIF1 DAC1 EQ Band 2 B */ | |
352 | { 0x0487, 0x0B75 }, /* R1159 - AIF1 DAC1 EQ Band 2 C */ | |
353 | { 0x0488, 0x01C5 }, /* R1160 - AIF1 DAC1 EQ Band 2 PG */ | |
354 | { 0x0489, 0x1C58 }, /* R1161 - AIF1 DAC1 EQ Band 3 A */ | |
355 | { 0x048A, 0xF373 }, /* R1162 - AIF1 DAC1 EQ Band 3 B */ | |
356 | { 0x048B, 0x0A54 }, /* R1163 - AIF1 DAC1 EQ Band 3 C */ | |
357 | { 0x048C, 0x0558 }, /* R1164 - AIF1 DAC1 EQ Band 3 PG */ | |
358 | { 0x048D, 0x168E }, /* R1165 - AIF1 DAC1 EQ Band 4 A */ | |
359 | { 0x048E, 0xF829 }, /* R1166 - AIF1 DAC1 EQ Band 4 B */ | |
360 | { 0x048F, 0x07AD }, /* R1167 - AIF1 DAC1 EQ Band 4 C */ | |
361 | { 0x0490, 0x1103 }, /* R1168 - AIF1 DAC1 EQ Band 4 PG */ | |
362 | { 0x0491, 0x0564 }, /* R1169 - AIF1 DAC1 EQ Band 5 A */ | |
363 | { 0x0492, 0x0559 }, /* R1170 - AIF1 DAC1 EQ Band 5 B */ | |
364 | { 0x0493, 0x4000 }, /* R1171 - AIF1 DAC1 EQ Band 5 PG */ | |
365 | { 0x04A0, 0x6318 }, /* R1184 - AIF1 DAC2 EQ Gains (1) */ | |
366 | { 0x04A1, 0x6300 }, /* R1185 - AIF1 DAC2 EQ Gains (2) */ | |
367 | { 0x04A2, 0x0FCA }, /* R1186 - AIF1 DAC2 EQ Band 1 A */ | |
368 | { 0x04A3, 0x0400 }, /* R1187 - AIF1 DAC2 EQ Band 1 B */ | |
369 | { 0x04A4, 0x00D8 }, /* R1188 - AIF1 DAC2 EQ Band 1 PG */ | |
370 | { 0x04A5, 0x1EB5 }, /* R1189 - AIF1 DAC2 EQ Band 2 A */ | |
371 | { 0x04A6, 0xF145 }, /* R1190 - AIF1 DAC2 EQ Band 2 B */ | |
372 | { 0x04A7, 0x0B75 }, /* R1191 - AIF1 DAC2 EQ Band 2 C */ | |
373 | { 0x04A8, 0x01C5 }, /* R1192 - AIF1 DAC2 EQ Band 2 PG */ | |
374 | { 0x04A9, 0x1C58 }, /* R1193 - AIF1 DAC2 EQ Band 3 A */ | |
375 | { 0x04AA, 0xF373 }, /* R1194 - AIF1 DAC2 EQ Band 3 B */ | |
376 | { 0x04AB, 0x0A54 }, /* R1195 - AIF1 DAC2 EQ Band 3 C */ | |
377 | { 0x04AC, 0x0558 }, /* R1196 - AIF1 DAC2 EQ Band 3 PG */ | |
378 | { 0x04AD, 0x168E }, /* R1197 - AIF1 DAC2 EQ Band 4 A */ | |
379 | { 0x04AE, 0xF829 }, /* R1198 - AIF1 DAC2 EQ Band 4 B */ | |
380 | { 0x04AF, 0x07AD }, /* R1199 - AIF1 DAC2 EQ Band 4 C */ | |
381 | { 0x04B0, 0x1103 }, /* R1200 - AIF1 DAC2 EQ Band 4 PG */ | |
382 | { 0x04B1, 0x0564 }, /* R1201 - AIF1 DAC2 EQ Band 5 A */ | |
383 | { 0x04B2, 0x0559 }, /* R1202 - AIF1 DAC2 EQ Band 5 B */ | |
384 | { 0x04B3, 0x4000 }, /* R1203 - AIF1 DAC2 EQ Band 5 PG */ | |
385 | { 0x0500, 0x00C0 }, /* R1280 - AIF2 ADC Left Volume */ | |
386 | { 0x0501, 0x00C0 }, /* R1281 - AIF2 ADC Right Volume */ | |
387 | { 0x0502, 0x00C0 }, /* R1282 - AIF2 DAC Left Volume */ | |
388 | { 0x0503, 0x00C0 }, /* R1283 - AIF2 DAC Right Volume */ | |
389 | { 0x0510, 0x0000 }, /* R1296 - AIF2 ADC Filters */ | |
390 | { 0x0520, 0x0200 }, /* R1312 - AIF2 DAC Filters (1) */ | |
391 | { 0x0521, 0x0010 }, /* R1313 - AIF2 DAC Filters (2) */ | |
392 | { 0x0540, 0x0098 }, /* R1344 - AIF2 DRC (1) */ | |
393 | { 0x0541, 0x0845 }, /* R1345 - AIF2 DRC (2) */ | |
394 | { 0x0542, 0x0000 }, /* R1346 - AIF2 DRC (3) */ | |
395 | { 0x0543, 0x0000 }, /* R1347 - AIF2 DRC (4) */ | |
396 | { 0x0544, 0x0000 }, /* R1348 - AIF2 DRC (5) */ | |
397 | { 0x0580, 0x6318 }, /* R1408 - AIF2 EQ Gains (1) */ | |
398 | { 0x0581, 0x6300 }, /* R1409 - AIF2 EQ Gains (2) */ | |
399 | { 0x0582, 0x0FCA }, /* R1410 - AIF2 EQ Band 1 A */ | |
400 | { 0x0583, 0x0400 }, /* R1411 - AIF2 EQ Band 1 B */ | |
401 | { 0x0584, 0x00D8 }, /* R1412 - AIF2 EQ Band 1 PG */ | |
402 | { 0x0585, 0x1EB5 }, /* R1413 - AIF2 EQ Band 2 A */ | |
403 | { 0x0586, 0xF145 }, /* R1414 - AIF2 EQ Band 2 B */ | |
404 | { 0x0587, 0x0B75 }, /* R1415 - AIF2 EQ Band 2 C */ | |
405 | { 0x0588, 0x01C5 }, /* R1416 - AIF2 EQ Band 2 PG */ | |
406 | { 0x0589, 0x1C58 }, /* R1417 - AIF2 EQ Band 3 A */ | |
407 | { 0x058A, 0xF373 }, /* R1418 - AIF2 EQ Band 3 B */ | |
408 | { 0x058B, 0x0A54 }, /* R1419 - AIF2 EQ Band 3 C */ | |
409 | { 0x058C, 0x0558 }, /* R1420 - AIF2 EQ Band 3 PG */ | |
410 | { 0x058D, 0x168E }, /* R1421 - AIF2 EQ Band 4 A */ | |
411 | { 0x058E, 0xF829 }, /* R1422 - AIF2 EQ Band 4 B */ | |
412 | { 0x058F, 0x07AD }, /* R1423 - AIF2 EQ Band 4 C */ | |
413 | { 0x0590, 0x1103 }, /* R1424 - AIF2 EQ Band 4 PG */ | |
414 | { 0x0591, 0x0564 }, /* R1425 - AIF2 EQ Band 5 A */ | |
415 | { 0x0592, 0x0559 }, /* R1426 - AIF2 EQ Band 5 B */ | |
416 | { 0x0593, 0x4000 }, /* R1427 - AIF2 EQ Band 5 PG */ | |
417 | { 0x0600, 0x0000 }, /* R1536 - DAC1 Mixer Volumes */ | |
418 | { 0x0601, 0x0000 }, /* R1537 - DAC1 Left Mixer Routing */ | |
419 | { 0x0602, 0x0000 }, /* R1538 - DAC1 Right Mixer Routing */ | |
420 | { 0x0603, 0x0000 }, /* R1539 - DAC2 Mixer Volumes */ | |
421 | { 0x0604, 0x0000 }, /* R1540 - DAC2 Left Mixer Routing */ | |
422 | { 0x0605, 0x0000 }, /* R1541 - DAC2 Right Mixer Routing */ | |
423 | { 0x0606, 0x0000 }, /* R1542 - AIF1 ADC1 Left Mixer Routing */ | |
424 | { 0x0607, 0x0000 }, /* R1543 - AIF1 ADC1 Right Mixer Routing */ | |
425 | { 0x0608, 0x0000 }, /* R1544 - AIF1 ADC2 Left Mixer Routing */ | |
426 | { 0x0609, 0x0000 }, /* R1545 - AIF1 ADC2 Right mixer Routing */ | |
427 | { 0x0610, 0x02C0 }, /* R1552 - DAC1 Left Volume */ | |
428 | { 0x0611, 0x02C0 }, /* R1553 - DAC1 Right Volume */ | |
429 | { 0x0612, 0x02C0 }, /* R1554 - DAC2 Left Volume */ | |
430 | { 0x0613, 0x02C0 }, /* R1555 - DAC2 Right Volume */ | |
431 | { 0x0614, 0x0000 }, /* R1556 - DAC Softmute */ | |
432 | { 0x0620, 0x0002 }, /* R1568 - Oversampling */ | |
433 | { 0x0621, 0x0000 }, /* R1569 - Sidetone */ | |
434 | { 0x0700, 0x8100 }, /* R1792 - GPIO 1 */ | |
435 | { 0x0701, 0xA101 }, /* R1793 - GPIO 2 */ | |
436 | { 0x0702, 0xA101 }, /* R1794 - GPIO 3 */ | |
437 | { 0x0703, 0xA101 }, /* R1795 - GPIO 4 */ | |
438 | { 0x0704, 0xA101 }, /* R1796 - GPIO 5 */ | |
439 | { 0x0705, 0xA101 }, /* R1797 - GPIO 6 */ | |
440 | { 0x0706, 0xA101 }, /* R1798 - GPIO 7 */ | |
441 | { 0x0707, 0xA101 }, /* R1799 - GPIO 8 */ | |
442 | { 0x0708, 0xA101 }, /* R1800 - GPIO 9 */ | |
443 | { 0x0709, 0xA101 }, /* R1801 - GPIO 10 */ | |
444 | { 0x070A, 0xA101 }, /* R1802 - GPIO 11 */ | |
445 | { 0x0720, 0x0000 }, /* R1824 - Pull Control (1) */ | |
446 | { 0x0721, 0x0156 }, /* R1825 - Pull Control (2) */ | |
447 | { 0x0730, 0x0000 }, /* R1840 - Interrupt Status 1 */ | |
448 | { 0x0731, 0x0000 }, /* R1841 - Interrupt Status 2 */ | |
449 | { 0x0732, 0x0000 }, /* R1842 - Interrupt Raw Status 2 */ | |
450 | { 0x0738, 0x07FF }, /* R1848 - Interrupt Status 1 Mask */ | |
451 | { 0x0739, 0xFFFF }, /* R1849 - Interrupt Status 2 Mask */ | |
452 | { 0x0740, 0x0000 }, /* R1856 - Interrupt Control */ | |
453 | { 0x0748, 0x003F }, /* R1864 - IRQ Debounce */ | |
454 | }; | |
455 | ||
456 | static struct reg_default wm8958_defaults[] = { | |
457 | { 0x0000, 0x8958 }, /* R0 - Software Reset */ | |
458 | { 0x0001, 0x0000 }, /* R1 - Power Management (1) */ | |
459 | { 0x0002, 0x6000 }, /* R2 - Power Management (2) */ | |
460 | { 0x0003, 0x0000 }, /* R3 - Power Management (3) */ | |
461 | { 0x0004, 0x0000 }, /* R4 - Power Management (4) */ | |
462 | { 0x0005, 0x0000 }, /* R5 - Power Management (5) */ | |
463 | { 0x0006, 0x0000 }, /* R6 - Power Management (6) */ | |
464 | { 0x0015, 0x0000 }, /* R21 - Input Mixer (1) */ | |
465 | { 0x0018, 0x008B }, /* R24 - Left Line Input 1&2 Volume */ | |
466 | { 0x0019, 0x008B }, /* R25 - Left Line Input 3&4 Volume */ | |
467 | { 0x001A, 0x008B }, /* R26 - Right Line Input 1&2 Volume */ | |
468 | { 0x001B, 0x008B }, /* R27 - Right Line Input 3&4 Volume */ | |
469 | { 0x001C, 0x006D }, /* R28 - Left Output Volume */ | |
470 | { 0x001D, 0x006D }, /* R29 - Right Output Volume */ | |
471 | { 0x001E, 0x0066 }, /* R30 - Line Outputs Volume */ | |
472 | { 0x001F, 0x0020 }, /* R31 - HPOUT2 Volume */ | |
473 | { 0x0020, 0x0079 }, /* R32 - Left OPGA Volume */ | |
474 | { 0x0021, 0x0079 }, /* R33 - Right OPGA Volume */ | |
475 | { 0x0022, 0x0003 }, /* R34 - SPKMIXL Attenuation */ | |
476 | { 0x0023, 0x0003 }, /* R35 - SPKMIXR Attenuation */ | |
477 | { 0x0024, 0x0011 }, /* R36 - SPKOUT Mixers */ | |
478 | { 0x0025, 0x0140 }, /* R37 - ClassD */ | |
479 | { 0x0026, 0x0079 }, /* R38 - Speaker Volume Left */ | |
480 | { 0x0027, 0x0079 }, /* R39 - Speaker Volume Right */ | |
481 | { 0x0028, 0x0000 }, /* R40 - Input Mixer (2) */ | |
482 | { 0x0029, 0x0000 }, /* R41 - Input Mixer (3) */ | |
483 | { 0x002A, 0x0000 }, /* R42 - Input Mixer (4) */ | |
484 | { 0x002B, 0x0000 }, /* R43 - Input Mixer (5) */ | |
485 | { 0x002C, 0x0000 }, /* R44 - Input Mixer (6) */ | |
486 | { 0x002D, 0x0000 }, /* R45 - Output Mixer (1) */ | |
487 | { 0x002E, 0x0000 }, /* R46 - Output Mixer (2) */ | |
488 | { 0x002F, 0x0000 }, /* R47 - Output Mixer (3) */ | |
489 | { 0x0030, 0x0000 }, /* R48 - Output Mixer (4) */ | |
490 | { 0x0031, 0x0000 }, /* R49 - Output Mixer (5) */ | |
491 | { 0x0032, 0x0000 }, /* R50 - Output Mixer (6) */ | |
492 | { 0x0033, 0x0000 }, /* R51 - HPOUT2 Mixer */ | |
493 | { 0x0034, 0x0000 }, /* R52 - Line Mixer (1) */ | |
494 | { 0x0035, 0x0000 }, /* R53 - Line Mixer (2) */ | |
495 | { 0x0036, 0x0000 }, /* R54 - Speaker Mixer */ | |
496 | { 0x0037, 0x0000 }, /* R55 - Additional Control */ | |
497 | { 0x0038, 0x0000 }, /* R56 - AntiPOP (1) */ | |
498 | { 0x0039, 0x0180 }, /* R57 - AntiPOP (2) */ | |
499 | { 0x003B, 0x000D }, /* R59 - LDO 1 */ | |
500 | { 0x003C, 0x0005 }, /* R60 - LDO 2 */ | |
501 | { 0x003D, 0x0039 }, /* R61 - MICBIAS1 */ | |
502 | { 0x003E, 0x0039 }, /* R62 - MICBIAS2 */ | |
503 | { 0x004C, 0x1F25 }, /* R76 - Charge Pump (1) */ | |
504 | { 0x004D, 0xAB19 }, /* R77 - Charge Pump (2) */ | |
505 | { 0x0051, 0x0004 }, /* R81 - Class W (1) */ | |
506 | { 0x0055, 0x054A }, /* R85 - DC Servo (2) */ | |
507 | { 0x0057, 0x0000 }, /* R87 - DC Servo (4) */ | |
508 | { 0x0060, 0x0000 }, /* R96 - Analogue HP (1) */ | |
509 | { 0x00C5, 0x0000 }, /* R197 - Class D Test (5) */ | |
510 | { 0x00D0, 0x5600 }, /* R208 - Mic Detect 1 */ | |
511 | { 0x00D1, 0x007F }, /* R209 - Mic Detect 2 */ | |
512 | { 0x0101, 0x8004 }, /* R257 - Control Interface */ | |
513 | { 0x0110, 0x0000 }, /* R272 - Write Sequencer Ctrl (1) */ | |
514 | { 0x0111, 0x0000 }, /* R273 - Write Sequencer Ctrl (2) */ | |
515 | { 0x0200, 0x0000 }, /* R512 - AIF1 Clocking (1) */ | |
516 | { 0x0201, 0x0000 }, /* R513 - AIF1 Clocking (2) */ | |
517 | { 0x0204, 0x0000 }, /* R516 - AIF2 Clocking (1) */ | |
518 | { 0x0205, 0x0000 }, /* R517 - AIF2 Clocking (2) */ | |
519 | { 0x0208, 0x0000 }, /* R520 - Clocking (1) */ | |
520 | { 0x0209, 0x0000 }, /* R521 - Clocking (2) */ | |
521 | { 0x0210, 0x0083 }, /* R528 - AIF1 Rate */ | |
522 | { 0x0211, 0x0083 }, /* R529 - AIF2 Rate */ | |
523 | { 0x0220, 0x0000 }, /* R544 - FLL1 Control (1) */ | |
524 | { 0x0221, 0x0000 }, /* R545 - FLL1 Control (2) */ | |
525 | { 0x0222, 0x0000 }, /* R546 - FLL1 Control (3) */ | |
526 | { 0x0223, 0x0000 }, /* R547 - FLL1 Control (4) */ | |
527 | { 0x0224, 0x0C80 }, /* R548 - FLL1 Control (5) */ | |
528 | { 0x0226, 0x0000 }, /* R550 - FLL1 EFS 1 */ | |
529 | { 0x0227, 0x0006 }, /* R551 - FLL1 EFS 2 */ | |
530 | { 0x0240, 0x0000 }, /* R576 - FLL2Control (1) */ | |
531 | { 0x0241, 0x0000 }, /* R577 - FLL2Control (2) */ | |
532 | { 0x0242, 0x0000 }, /* R578 - FLL2Control (3) */ | |
533 | { 0x0243, 0x0000 }, /* R579 - FLL2 Control (4) */ | |
534 | { 0x0244, 0x0C80 }, /* R580 - FLL2Control (5) */ | |
535 | { 0x0246, 0x0000 }, /* R582 - FLL2 EFS 1 */ | |
536 | { 0x0247, 0x0006 }, /* R583 - FLL2 EFS 2 */ | |
537 | { 0x0300, 0x4050 }, /* R768 - AIF1 Control (1) */ | |
538 | { 0x0301, 0x4000 }, /* R769 - AIF1 Control (2) */ | |
539 | { 0x0302, 0x0000 }, /* R770 - AIF1 Master/Slave */ | |
540 | { 0x0303, 0x0040 }, /* R771 - AIF1 BCLK */ | |
541 | { 0x0304, 0x0040 }, /* R772 - AIF1ADC LRCLK */ | |
542 | { 0x0305, 0x0040 }, /* R773 - AIF1DAC LRCLK */ | |
543 | { 0x0306, 0x0004 }, /* R774 - AIF1DAC Data */ | |
544 | { 0x0307, 0x0100 }, /* R775 - AIF1ADC Data */ | |
545 | { 0x0310, 0x4053 }, /* R784 - AIF2 Control (1) */ | |
546 | { 0x0311, 0x4000 }, /* R785 - AIF2 Control (2) */ | |
547 | { 0x0312, 0x0000 }, /* R786 - AIF2 Master/Slave */ | |
548 | { 0x0313, 0x0040 }, /* R787 - AIF2 BCLK */ | |
549 | { 0x0314, 0x0040 }, /* R788 - AIF2ADC LRCLK */ | |
550 | { 0x0315, 0x0040 }, /* R789 - AIF2DAC LRCLK */ | |
551 | { 0x0316, 0x0000 }, /* R790 - AIF2DAC Data */ | |
552 | { 0x0317, 0x0000 }, /* R791 - AIF2ADC Data */ | |
553 | { 0x0320, 0x0040 }, /* R800 - AIF3 Control (1) */ | |
554 | { 0x0321, 0x0000 }, /* R801 - AIF3 Control (2) */ | |
555 | { 0x0322, 0x0000 }, /* R802 - AIF3DAC Data */ | |
556 | { 0x0323, 0x0000 }, /* R803 - AIF3ADC Data */ | |
557 | { 0x0400, 0x00C0 }, /* R1024 - AIF1 ADC1 Left Volume */ | |
558 | { 0x0401, 0x00C0 }, /* R1025 - AIF1 ADC1 Right Volume */ | |
559 | { 0x0402, 0x00C0 }, /* R1026 - AIF1 DAC1 Left Volume */ | |
560 | { 0x0403, 0x00C0 }, /* R1027 - AIF1 DAC1 Right Volume */ | |
561 | { 0x0404, 0x00C0 }, /* R1028 - AIF1 ADC2 Left Volume */ | |
562 | { 0x0405, 0x00C0 }, /* R1029 - AIF1 ADC2 Right Volume */ | |
563 | { 0x0406, 0x00C0 }, /* R1030 - AIF1 DAC2 Left Volume */ | |
564 | { 0x0407, 0x00C0 }, /* R1031 - AIF1 DAC2 Right Volume */ | |
565 | { 0x0410, 0x0000 }, /* R1040 - AIF1 ADC1 Filters */ | |
566 | { 0x0411, 0x0000 }, /* R1041 - AIF1 ADC2 Filters */ | |
567 | { 0x0420, 0x0200 }, /* R1056 - AIF1 DAC1 Filters (1) */ | |
568 | { 0x0421, 0x0010 }, /* R1057 - AIF1 DAC1 Filters (2) */ | |
569 | { 0x0422, 0x0200 }, /* R1058 - AIF1 DAC2 Filters (1) */ | |
570 | { 0x0423, 0x0010 }, /* R1059 - AIF1 DAC2 Filters (2) */ | |
571 | { 0x0430, 0x0068 }, /* R1072 - AIF1 DAC1 Noise Gate */ | |
572 | { 0x0431, 0x0068 }, /* R1073 - AIF1 DAC2 Noise Gate */ | |
573 | { 0x0440, 0x0098 }, /* R1088 - AIF1 DRC1 (1) */ | |
574 | { 0x0441, 0x0845 }, /* R1089 - AIF1 DRC1 (2) */ | |
575 | { 0x0442, 0x0000 }, /* R1090 - AIF1 DRC1 (3) */ | |
576 | { 0x0443, 0x0000 }, /* R1091 - AIF1 DRC1 (4) */ | |
577 | { 0x0444, 0x0000 }, /* R1092 - AIF1 DRC1 (5) */ | |
578 | { 0x0450, 0x0098 }, /* R1104 - AIF1 DRC2 (1) */ | |
579 | { 0x0451, 0x0845 }, /* R1105 - AIF1 DRC2 (2) */ | |
580 | { 0x0452, 0x0000 }, /* R1106 - AIF1 DRC2 (3) */ | |
581 | { 0x0453, 0x0000 }, /* R1107 - AIF1 DRC2 (4) */ | |
582 | { 0x0454, 0x0000 }, /* R1108 - AIF1 DRC2 (5) */ | |
583 | { 0x0480, 0x6318 }, /* R1152 - AIF1 DAC1 EQ Gains (1) */ | |
584 | { 0x0481, 0x6300 }, /* R1153 - AIF1 DAC1 EQ Gains (2) */ | |
585 | { 0x0482, 0x0FCA }, /* R1154 - AIF1 DAC1 EQ Band 1 A */ | |
586 | { 0x0483, 0x0400 }, /* R1155 - AIF1 DAC1 EQ Band 1 B */ | |
587 | { 0x0484, 0x00D8 }, /* R1156 - AIF1 DAC1 EQ Band 1 PG */ | |
588 | { 0x0485, 0x1EB5 }, /* R1157 - AIF1 DAC1 EQ Band 2 A */ | |
589 | { 0x0486, 0xF145 }, /* R1158 - AIF1 DAC1 EQ Band 2 B */ | |
590 | { 0x0487, 0x0B75 }, /* R1159 - AIF1 DAC1 EQ Band 2 C */ | |
591 | { 0x0488, 0x01C5 }, /* R1160 - AIF1 DAC1 EQ Band 2 PG */ | |
592 | { 0x0489, 0x1C58 }, /* R1161 - AIF1 DAC1 EQ Band 3 A */ | |
593 | { 0x048A, 0xF373 }, /* R1162 - AIF1 DAC1 EQ Band 3 B */ | |
594 | { 0x048B, 0x0A54 }, /* R1163 - AIF1 DAC1 EQ Band 3 C */ | |
595 | { 0x048C, 0x0558 }, /* R1164 - AIF1 DAC1 EQ Band 3 PG */ | |
596 | { 0x048D, 0x168E }, /* R1165 - AIF1 DAC1 EQ Band 4 A */ | |
597 | { 0x048E, 0xF829 }, /* R1166 - AIF1 DAC1 EQ Band 4 B */ | |
598 | { 0x048F, 0x07AD }, /* R1167 - AIF1 DAC1 EQ Band 4 C */ | |
599 | { 0x0490, 0x1103 }, /* R1168 - AIF1 DAC1 EQ Band 4 PG */ | |
600 | { 0x0491, 0x0564 }, /* R1169 - AIF1 DAC1 EQ Band 5 A */ | |
601 | { 0x0492, 0x0559 }, /* R1170 - AIF1 DAC1 EQ Band 5 B */ | |
602 | { 0x0493, 0x4000 }, /* R1171 - AIF1 DAC1 EQ Band 5 PG */ | |
603 | { 0x0494, 0x0000 }, /* R1172 - AIF1 DAC1 EQ Band 1 C */ | |
604 | { 0x04A0, 0x6318 }, /* R1184 - AIF1 DAC2 EQ Gains (1) */ | |
605 | { 0x04A1, 0x6300 }, /* R1185 - AIF1 DAC2 EQ Gains (2) */ | |
606 | { 0x04A2, 0x0FCA }, /* R1186 - AIF1 DAC2 EQ Band 1 A */ | |
607 | { 0x04A3, 0x0400 }, /* R1187 - AIF1 DAC2 EQ Band 1 B */ | |
608 | { 0x04A4, 0x00D8 }, /* R1188 - AIF1 DAC2 EQ Band 1 PG */ | |
609 | { 0x04A5, 0x1EB5 }, /* R1189 - AIF1 DAC2 EQ Band 2 A */ | |
610 | { 0x04A6, 0xF145 }, /* R1190 - AIF1 DAC2 EQ Band 2 B */ | |
611 | { 0x04A7, 0x0B75 }, /* R1191 - AIF1 DAC2 EQ Band 2 C */ | |
612 | { 0x04A8, 0x01C5 }, /* R1192 - AIF1 DAC2 EQ Band 2 PG */ | |
613 | { 0x04A9, 0x1C58 }, /* R1193 - AIF1 DAC2 EQ Band 3 A */ | |
614 | { 0x04AA, 0xF373 }, /* R1194 - AIF1 DAC2 EQ Band 3 B */ | |
615 | { 0x04AB, 0x0A54 }, /* R1195 - AIF1 DAC2 EQ Band 3 C */ | |
616 | { 0x04AC, 0x0558 }, /* R1196 - AIF1 DAC2 EQ Band 3 PG */ | |
617 | { 0x04AD, 0x168E }, /* R1197 - AIF1 DAC2 EQ Band 4 A */ | |
618 | { 0x04AE, 0xF829 }, /* R1198 - AIF1 DAC2 EQ Band 4 B */ | |
619 | { 0x04AF, 0x07AD }, /* R1199 - AIF1 DAC2 EQ Band 4 C */ | |
620 | { 0x04B0, 0x1103 }, /* R1200 - AIF1 DAC2 EQ Band 4 PG */ | |
621 | { 0x04B1, 0x0564 }, /* R1201 - AIF1 DAC2 EQ Band 5 A */ | |
622 | { 0x04B2, 0x0559 }, /* R1202 - AIF1 DAC2 EQ Band 5 B */ | |
623 | { 0x04B3, 0x4000 }, /* R1203 - AIF1 DAC2 EQ Band 5 PG */ | |
624 | { 0x04B4, 0x0000 }, /* R1204 - AIF1 DAC2EQ Band 1 C */ | |
625 | { 0x0500, 0x00C0 }, /* R1280 - AIF2 ADC Left Volume */ | |
626 | { 0x0501, 0x00C0 }, /* R1281 - AIF2 ADC Right Volume */ | |
627 | { 0x0502, 0x00C0 }, /* R1282 - AIF2 DAC Left Volume */ | |
628 | { 0x0503, 0x00C0 }, /* R1283 - AIF2 DAC Right Volume */ | |
629 | { 0x0510, 0x0000 }, /* R1296 - AIF2 ADC Filters */ | |
630 | { 0x0520, 0x0200 }, /* R1312 - AIF2 DAC Filters (1) */ | |
631 | { 0x0521, 0x0010 }, /* R1313 - AIF2 DAC Filters (2) */ | |
632 | { 0x0530, 0x0068 }, /* R1328 - AIF2 DAC Noise Gate */ | |
633 | { 0x0540, 0x0098 }, /* R1344 - AIF2 DRC (1) */ | |
634 | { 0x0541, 0x0845 }, /* R1345 - AIF2 DRC (2) */ | |
635 | { 0x0542, 0x0000 }, /* R1346 - AIF2 DRC (3) */ | |
636 | { 0x0543, 0x0000 }, /* R1347 - AIF2 DRC (4) */ | |
637 | { 0x0544, 0x0000 }, /* R1348 - AIF2 DRC (5) */ | |
638 | { 0x0580, 0x6318 }, /* R1408 - AIF2 EQ Gains (1) */ | |
639 | { 0x0581, 0x6300 }, /* R1409 - AIF2 EQ Gains (2) */ | |
640 | { 0x0582, 0x0FCA }, /* R1410 - AIF2 EQ Band 1 A */ | |
641 | { 0x0583, 0x0400 }, /* R1411 - AIF2 EQ Band 1 B */ | |
642 | { 0x0584, 0x00D8 }, /* R1412 - AIF2 EQ Band 1 PG */ | |
643 | { 0x0585, 0x1EB5 }, /* R1413 - AIF2 EQ Band 2 A */ | |
644 | { 0x0586, 0xF145 }, /* R1414 - AIF2 EQ Band 2 B */ | |
645 | { 0x0587, 0x0B75 }, /* R1415 - AIF2 EQ Band 2 C */ | |
646 | { 0x0588, 0x01C5 }, /* R1416 - AIF2 EQ Band 2 PG */ | |
647 | { 0x0589, 0x1C58 }, /* R1417 - AIF2 EQ Band 3 A */ | |
648 | { 0x058A, 0xF373 }, /* R1418 - AIF2 EQ Band 3 B */ | |
649 | { 0x058B, 0x0A54 }, /* R1419 - AIF2 EQ Band 3 C */ | |
650 | { 0x058C, 0x0558 }, /* R1420 - AIF2 EQ Band 3 PG */ | |
651 | { 0x058D, 0x168E }, /* R1421 - AIF2 EQ Band 4 A */ | |
652 | { 0x058E, 0xF829 }, /* R1422 - AIF2 EQ Band 4 B */ | |
653 | { 0x058F, 0x07AD }, /* R1423 - AIF2 EQ Band 4 C */ | |
654 | { 0x0590, 0x1103 }, /* R1424 - AIF2 EQ Band 4 PG */ | |
655 | { 0x0591, 0x0564 }, /* R1425 - AIF2 EQ Band 5 A */ | |
656 | { 0x0592, 0x0559 }, /* R1426 - AIF2 EQ Band 5 B */ | |
657 | { 0x0593, 0x4000 }, /* R1427 - AIF2 EQ Band 5 PG */ | |
658 | { 0x0594, 0x0000 }, /* R1428 - AIF2 EQ Band 1 C */ | |
659 | { 0x0600, 0x0000 }, /* R1536 - DAC1 Mixer Volumes */ | |
660 | { 0x0601, 0x0000 }, /* R1537 - DAC1 Left Mixer Routing */ | |
661 | { 0x0602, 0x0000 }, /* R1538 - DAC1 Right Mixer Routing */ | |
662 | { 0x0603, 0x0000 }, /* R1539 - DAC2 Mixer Volumes */ | |
663 | { 0x0604, 0x0000 }, /* R1540 - DAC2 Left Mixer Routing */ | |
664 | { 0x0605, 0x0000 }, /* R1541 - DAC2 Right Mixer Routing */ | |
665 | { 0x0606, 0x0000 }, /* R1542 - AIF1 ADC1 Left Mixer Routing */ | |
666 | { 0x0607, 0x0000 }, /* R1543 - AIF1 ADC1 Right Mixer Routing */ | |
667 | { 0x0608, 0x0000 }, /* R1544 - AIF1 ADC2 Left Mixer Routing */ | |
668 | { 0x0609, 0x0000 }, /* R1545 - AIF1 ADC2 Right mixer Routing */ | |
669 | { 0x0610, 0x02C0 }, /* R1552 - DAC1 Left Volume */ | |
670 | { 0x0611, 0x02C0 }, /* R1553 - DAC1 Right Volume */ | |
671 | { 0x0612, 0x02C0 }, /* R1554 - DAC2 Left Volume */ | |
672 | { 0x0613, 0x02C0 }, /* R1555 - DAC2 Right Volume */ | |
673 | { 0x0614, 0x0000 }, /* R1556 - DAC Softmute */ | |
674 | { 0x0620, 0x0002 }, /* R1568 - Oversampling */ | |
675 | { 0x0621, 0x0000 }, /* R1569 - Sidetone */ | |
676 | { 0x0700, 0x8100 }, /* R1792 - GPIO 1 */ | |
677 | { 0x0701, 0xA101 }, /* R1793 - Pull Control (MCLK2) */ | |
678 | { 0x0702, 0xA101 }, /* R1794 - Pull Control (BCLK2) */ | |
679 | { 0x0703, 0xA101 }, /* R1795 - Pull Control (DACLRCLK2) */ | |
680 | { 0x0704, 0xA101 }, /* R1796 - Pull Control (DACDAT2) */ | |
681 | { 0x0705, 0xA101 }, /* R1797 - GPIO 6 */ | |
682 | { 0x0707, 0xA101 }, /* R1799 - GPIO 8 */ | |
683 | { 0x0708, 0xA101 }, /* R1800 - GPIO 9 */ | |
684 | { 0x0709, 0xA101 }, /* R1801 - GPIO 10 */ | |
685 | { 0x070A, 0xA101 }, /* R1802 - GPIO 11 */ | |
686 | { 0x0720, 0x0000 }, /* R1824 - Pull Control (1) */ | |
687 | { 0x0721, 0x0156 }, /* R1825 - Pull Control (2) */ | |
688 | { 0x0738, 0x07FF }, /* R1848 - Interrupt Status 1 Mask */ | |
689 | { 0x0739, 0xFFEF }, /* R1849 - Interrupt Status 2 Mask */ | |
690 | { 0x0740, 0x0000 }, /* R1856 - Interrupt Control */ | |
691 | { 0x0748, 0x003F }, /* R1864 - IRQ Debounce */ | |
692 | { 0x0900, 0x1C00 }, /* R2304 - DSP2_Program */ | |
693 | { 0x0901, 0x0000 }, /* R2305 - DSP2_Config */ | |
694 | { 0x0A0D, 0x0000 }, /* R2573 - DSP2_ExecControl */ | |
695 | { 0x2400, 0x003F }, /* R9216 - MBC Band 1 K (1) */ | |
696 | { 0x2401, 0x8BD8 }, /* R9217 - MBC Band 1 K (2) */ | |
697 | { 0x2402, 0x0032 }, /* R9218 - MBC Band 1 N1 (1) */ | |
698 | { 0x2403, 0xF52D }, /* R9219 - MBC Band 1 N1 (2) */ | |
699 | { 0x2404, 0x0065 }, /* R9220 - MBC Band 1 N2 (1) */ | |
700 | { 0x2405, 0xAC8C }, /* R9221 - MBC Band 1 N2 (2) */ | |
701 | { 0x2406, 0x006B }, /* R9222 - MBC Band 1 N3 (1) */ | |
702 | { 0x2407, 0xE087 }, /* R9223 - MBC Band 1 N3 (2) */ | |
703 | { 0x2408, 0x0072 }, /* R9224 - MBC Band 1 N4 (1) */ | |
704 | { 0x2409, 0x1483 }, /* R9225 - MBC Band 1 N4 (2) */ | |
705 | { 0x240A, 0x0072 }, /* R9226 - MBC Band 1 N5 (1) */ | |
706 | { 0x240B, 0x1483 }, /* R9227 - MBC Band 1 N5 (2) */ | |
707 | { 0x240C, 0x0043 }, /* R9228 - MBC Band 1 X1 (1) */ | |
708 | { 0x240D, 0x3525 }, /* R9229 - MBC Band 1 X1 (2) */ | |
709 | { 0x240E, 0x0006 }, /* R9230 - MBC Band 1 X2 (1) */ | |
710 | { 0x240F, 0x6A4A }, /* R9231 - MBC Band 1 X2 (2) */ | |
711 | { 0x2410, 0x0043 }, /* R9232 - MBC Band 1 X3 (1) */ | |
712 | { 0x2411, 0x6079 }, /* R9233 - MBC Band 1 X3 (2) */ | |
713 | { 0x2412, 0x000C }, /* R9234 - MBC Band 1 Attack (1) */ | |
714 | { 0x2413, 0xCCCD }, /* R9235 - MBC Band 1 Attack (2) */ | |
715 | { 0x2414, 0x0000 }, /* R9236 - MBC Band 1 Decay (1) */ | |
716 | { 0x2415, 0x0800 }, /* R9237 - MBC Band 1 Decay (2) */ | |
717 | { 0x2416, 0x003F }, /* R9238 - MBC Band 2 K (1) */ | |
718 | { 0x2417, 0x8BD8 }, /* R9239 - MBC Band 2 K (2) */ | |
719 | { 0x2418, 0x0032 }, /* R9240 - MBC Band 2 N1 (1) */ | |
720 | { 0x2419, 0xF52D }, /* R9241 - MBC Band 2 N1 (2) */ | |
721 | { 0x241A, 0x0065 }, /* R9242 - MBC Band 2 N2 (1) */ | |
722 | { 0x241B, 0xAC8C }, /* R9243 - MBC Band 2 N2 (2) */ | |
723 | { 0x241C, 0x006B }, /* R9244 - MBC Band 2 N3 (1) */ | |
724 | { 0x241D, 0xE087 }, /* R9245 - MBC Band 2 N3 (2) */ | |
725 | { 0x241E, 0x0072 }, /* R9246 - MBC Band 2 N4 (1) */ | |
726 | { 0x241F, 0x1483 }, /* R9247 - MBC Band 2 N4 (2) */ | |
727 | { 0x2420, 0x0072 }, /* R9248 - MBC Band 2 N5 (1) */ | |
728 | { 0x2421, 0x1483 }, /* R9249 - MBC Band 2 N5 (2) */ | |
729 | { 0x2422, 0x0043 }, /* R9250 - MBC Band 2 X1 (1) */ | |
730 | { 0x2423, 0x3525 }, /* R9251 - MBC Band 2 X1 (2) */ | |
731 | { 0x2424, 0x0006 }, /* R9252 - MBC Band 2 X2 (1) */ | |
732 | { 0x2425, 0x6A4A }, /* R9253 - MBC Band 2 X2 (2) */ | |
733 | { 0x2426, 0x0043 }, /* R9254 - MBC Band 2 X3 (1) */ | |
734 | { 0x2427, 0x6079 }, /* R9255 - MBC Band 2 X3 (2) */ | |
735 | { 0x2428, 0x000C }, /* R9256 - MBC Band 2 Attack (1) */ | |
736 | { 0x2429, 0xCCCD }, /* R9257 - MBC Band 2 Attack (2) */ | |
737 | { 0x242A, 0x0000 }, /* R9258 - MBC Band 2 Decay (1) */ | |
738 | { 0x242B, 0x0800 }, /* R9259 - MBC Band 2 Decay (2) */ | |
739 | { 0x242C, 0x005A }, /* R9260 - MBC_B2_PG2 (1) */ | |
740 | { 0x242D, 0x7EFA }, /* R9261 - MBC_B2_PG2 (2) */ | |
741 | { 0x242E, 0x005A }, /* R9262 - MBC_B1_PG2 (1) */ | |
742 | { 0x242F, 0x7EFA }, /* R9263 - MBC_B1_PG2 (2) */ | |
743 | { 0x2600, 0x00A7 }, /* R9728 - MBC Crossover (1) */ | |
744 | { 0x2601, 0x0D1C }, /* R9729 - MBC Crossover (2) */ | |
745 | { 0x2602, 0x0083 }, /* R9730 - MBC HPF (1) */ | |
746 | { 0x2603, 0x98AD }, /* R9731 - MBC HPF (2) */ | |
747 | { 0x2606, 0x0008 }, /* R9734 - MBC LPF (1) */ | |
748 | { 0x2607, 0xE7A2 }, /* R9735 - MBC LPF (2) */ | |
749 | { 0x260A, 0x0055 }, /* R9738 - MBC RMS Limit (1) */ | |
750 | { 0x260B, 0x8C4B }, /* R9739 - MBC RMS Limit (2) */ | |
751 | }; | |
752 | ||
753 | static bool wm1811_readable_register(struct device *dev, unsigned int reg) | |
754 | { | |
755 | switch (reg) { | |
756 | case WM8994_SOFTWARE_RESET: | |
757 | case WM8994_POWER_MANAGEMENT_1: | |
758 | case WM8994_POWER_MANAGEMENT_2: | |
759 | case WM8994_POWER_MANAGEMENT_3: | |
760 | case WM8994_POWER_MANAGEMENT_4: | |
761 | case WM8994_POWER_MANAGEMENT_5: | |
762 | case WM8994_POWER_MANAGEMENT_6: | |
763 | case WM8994_INPUT_MIXER_1: | |
764 | case WM8994_LEFT_LINE_INPUT_1_2_VOLUME: | |
765 | case WM8994_LEFT_LINE_INPUT_3_4_VOLUME: | |
766 | case WM8994_RIGHT_LINE_INPUT_1_2_VOLUME: | |
767 | case WM8994_RIGHT_LINE_INPUT_3_4_VOLUME: | |
768 | case WM8994_LEFT_OUTPUT_VOLUME: | |
769 | case WM8994_RIGHT_OUTPUT_VOLUME: | |
770 | case WM8994_LINE_OUTPUTS_VOLUME: | |
771 | case WM8994_HPOUT2_VOLUME: | |
772 | case WM8994_LEFT_OPGA_VOLUME: | |
773 | case WM8994_RIGHT_OPGA_VOLUME: | |
774 | case WM8994_SPKMIXL_ATTENUATION: | |
775 | case WM8994_SPKMIXR_ATTENUATION: | |
776 | case WM8994_SPKOUT_MIXERS: | |
777 | case WM8994_CLASSD: | |
778 | case WM8994_SPEAKER_VOLUME_LEFT: | |
779 | case WM8994_SPEAKER_VOLUME_RIGHT: | |
780 | case WM8994_INPUT_MIXER_2: | |
781 | case WM8994_INPUT_MIXER_3: | |
782 | case WM8994_INPUT_MIXER_4: | |
783 | case WM8994_INPUT_MIXER_5: | |
784 | case WM8994_INPUT_MIXER_6: | |
785 | case WM8994_OUTPUT_MIXER_1: | |
786 | case WM8994_OUTPUT_MIXER_2: | |
787 | case WM8994_OUTPUT_MIXER_3: | |
788 | case WM8994_OUTPUT_MIXER_4: | |
789 | case WM8994_OUTPUT_MIXER_5: | |
790 | case WM8994_OUTPUT_MIXER_6: | |
791 | case WM8994_HPOUT2_MIXER: | |
792 | case WM8994_LINE_MIXER_1: | |
793 | case WM8994_LINE_MIXER_2: | |
794 | case WM8994_SPEAKER_MIXER: | |
795 | case WM8994_ADDITIONAL_CONTROL: | |
796 | case WM8994_ANTIPOP_1: | |
797 | case WM8994_ANTIPOP_2: | |
798 | case WM8994_LDO_1: | |
799 | case WM8994_LDO_2: | |
800 | case WM8958_MICBIAS1: | |
801 | case WM8958_MICBIAS2: | |
802 | case WM8994_CHARGE_PUMP_1: | |
803 | case WM8958_CHARGE_PUMP_2: | |
804 | case WM8994_CLASS_W_1: | |
805 | case WM8994_DC_SERVO_1: | |
806 | case WM8994_DC_SERVO_2: | |
807 | case WM8994_DC_SERVO_READBACK: | |
808 | case WM8994_DC_SERVO_4: | |
809 | case WM8994_ANALOGUE_HP_1: | |
810 | case WM8958_MIC_DETECT_1: | |
811 | case WM8958_MIC_DETECT_2: | |
812 | case WM8958_MIC_DETECT_3: | |
813 | case WM8994_CHIP_REVISION: | |
814 | case WM8994_CONTROL_INTERFACE: | |
815 | case WM8994_AIF1_CLOCKING_1: | |
816 | case WM8994_AIF1_CLOCKING_2: | |
817 | case WM8994_AIF2_CLOCKING_1: | |
818 | case WM8994_AIF2_CLOCKING_2: | |
819 | case WM8994_CLOCKING_1: | |
820 | case WM8994_CLOCKING_2: | |
821 | case WM8994_AIF1_RATE: | |
822 | case WM8994_AIF2_RATE: | |
823 | case WM8994_RATE_STATUS: | |
824 | case WM8994_FLL1_CONTROL_1: | |
825 | case WM8994_FLL1_CONTROL_2: | |
826 | case WM8994_FLL1_CONTROL_3: | |
827 | case WM8994_FLL1_CONTROL_4: | |
828 | case WM8994_FLL1_CONTROL_5: | |
829 | case WM8958_FLL1_EFS_1: | |
830 | case WM8958_FLL1_EFS_2: | |
831 | case WM8994_FLL2_CONTROL_1: | |
832 | case WM8994_FLL2_CONTROL_2: | |
833 | case WM8994_FLL2_CONTROL_3: | |
834 | case WM8994_FLL2_CONTROL_4: | |
835 | case WM8994_FLL2_CONTROL_5: | |
836 | case WM8958_FLL2_EFS_1: | |
837 | case WM8958_FLL2_EFS_2: | |
838 | case WM8994_AIF1_CONTROL_1: | |
839 | case WM8994_AIF1_CONTROL_2: | |
840 | case WM8994_AIF1_MASTER_SLAVE: | |
841 | case WM8994_AIF1_BCLK: | |
842 | case WM8994_AIF1ADC_LRCLK: | |
843 | case WM8994_AIF1DAC_LRCLK: | |
844 | case WM8994_AIF1DAC_DATA: | |
845 | case WM8994_AIF1ADC_DATA: | |
846 | case WM8994_AIF2_CONTROL_1: | |
847 | case WM8994_AIF2_CONTROL_2: | |
848 | case WM8994_AIF2_MASTER_SLAVE: | |
849 | case WM8994_AIF2_BCLK: | |
850 | case WM8994_AIF2ADC_LRCLK: | |
851 | case WM8994_AIF2DAC_LRCLK: | |
852 | case WM8994_AIF2DAC_DATA: | |
853 | case WM8994_AIF2ADC_DATA: | |
854 | case WM1811_AIF2TX_CONTROL: | |
855 | case WM8958_AIF3_CONTROL_1: | |
856 | case WM8958_AIF3_CONTROL_2: | |
857 | case WM8958_AIF3DAC_DATA: | |
858 | case WM8958_AIF3ADC_DATA: | |
859 | case WM8994_AIF1_ADC1_LEFT_VOLUME: | |
860 | case WM8994_AIF1_ADC1_RIGHT_VOLUME: | |
861 | case WM8994_AIF1_DAC1_LEFT_VOLUME: | |
862 | case WM8994_AIF1_DAC1_RIGHT_VOLUME: | |
863 | case WM8994_AIF1_ADC1_FILTERS: | |
864 | case WM8994_AIF1_DAC1_FILTERS_1: | |
865 | case WM8994_AIF1_DAC1_FILTERS_2: | |
866 | case WM8958_AIF1_DAC1_NOISE_GATE: | |
867 | case WM8994_AIF1_DRC1_1: | |
868 | case WM8994_AIF1_DRC1_2: | |
869 | case WM8994_AIF1_DRC1_3: | |
870 | case WM8994_AIF1_DRC1_4: | |
871 | case WM8994_AIF1_DRC1_5: | |
872 | case WM8994_AIF1_DAC1_EQ_GAINS_1: | |
873 | case WM8994_AIF1_DAC1_EQ_GAINS_2: | |
874 | case WM8994_AIF1_DAC1_EQ_BAND_1_A: | |
875 | case WM8994_AIF1_DAC1_EQ_BAND_1_B: | |
876 | case WM8994_AIF1_DAC1_EQ_BAND_1_PG: | |
877 | case WM8994_AIF1_DAC1_EQ_BAND_2_A: | |
878 | case WM8994_AIF1_DAC1_EQ_BAND_2_B: | |
879 | case WM8994_AIF1_DAC1_EQ_BAND_2_C: | |
880 | case WM8994_AIF1_DAC1_EQ_BAND_2_PG: | |
881 | case WM8994_AIF1_DAC1_EQ_BAND_3_A: | |
882 | case WM8994_AIF1_DAC1_EQ_BAND_3_B: | |
883 | case WM8994_AIF1_DAC1_EQ_BAND_3_C: | |
884 | case WM8994_AIF1_DAC1_EQ_BAND_3_PG: | |
885 | case WM8994_AIF1_DAC1_EQ_BAND_4_A: | |
886 | case WM8994_AIF1_DAC1_EQ_BAND_4_B: | |
887 | case WM8994_AIF1_DAC1_EQ_BAND_4_C: | |
888 | case WM8994_AIF1_DAC1_EQ_BAND_4_PG: | |
889 | case WM8994_AIF1_DAC1_EQ_BAND_5_A: | |
890 | case WM8994_AIF1_DAC1_EQ_BAND_5_B: | |
891 | case WM8994_AIF1_DAC1_EQ_BAND_5_PG: | |
892 | case WM8994_AIF1_DAC1_EQ_BAND_1_C: | |
893 | case WM8994_AIF2_ADC_LEFT_VOLUME: | |
894 | case WM8994_AIF2_ADC_RIGHT_VOLUME: | |
895 | case WM8994_AIF2_DAC_LEFT_VOLUME: | |
896 | case WM8994_AIF2_DAC_RIGHT_VOLUME: | |
897 | case WM8994_AIF2_ADC_FILTERS: | |
898 | case WM8994_AIF2_DAC_FILTERS_1: | |
899 | case WM8994_AIF2_DAC_FILTERS_2: | |
900 | case WM8958_AIF2_DAC_NOISE_GATE: | |
901 | case WM8994_AIF2_DRC_1: | |
902 | case WM8994_AIF2_DRC_2: | |
903 | case WM8994_AIF2_DRC_3: | |
904 | case WM8994_AIF2_DRC_4: | |
905 | case WM8994_AIF2_DRC_5: | |
906 | case WM8994_AIF2_EQ_GAINS_1: | |
907 | case WM8994_AIF2_EQ_GAINS_2: | |
908 | case WM8994_AIF2_EQ_BAND_1_A: | |
909 | case WM8994_AIF2_EQ_BAND_1_B: | |
910 | case WM8994_AIF2_EQ_BAND_1_PG: | |
911 | case WM8994_AIF2_EQ_BAND_2_A: | |
912 | case WM8994_AIF2_EQ_BAND_2_B: | |
913 | case WM8994_AIF2_EQ_BAND_2_C: | |
914 | case WM8994_AIF2_EQ_BAND_2_PG: | |
915 | case WM8994_AIF2_EQ_BAND_3_A: | |
916 | case WM8994_AIF2_EQ_BAND_3_B: | |
917 | case WM8994_AIF2_EQ_BAND_3_C: | |
918 | case WM8994_AIF2_EQ_BAND_3_PG: | |
919 | case WM8994_AIF2_EQ_BAND_4_A: | |
920 | case WM8994_AIF2_EQ_BAND_4_B: | |
921 | case WM8994_AIF2_EQ_BAND_4_C: | |
922 | case WM8994_AIF2_EQ_BAND_4_PG: | |
923 | case WM8994_AIF2_EQ_BAND_5_A: | |
924 | case WM8994_AIF2_EQ_BAND_5_B: | |
925 | case WM8994_AIF2_EQ_BAND_5_PG: | |
926 | case WM8994_AIF2_EQ_BAND_1_C: | |
927 | case WM8994_DAC1_MIXER_VOLUMES: | |
928 | case WM8994_DAC1_LEFT_MIXER_ROUTING: | |
929 | case WM8994_DAC1_RIGHT_MIXER_ROUTING: | |
930 | case WM8994_DAC2_MIXER_VOLUMES: | |
931 | case WM8994_DAC2_LEFT_MIXER_ROUTING: | |
932 | case WM8994_DAC2_RIGHT_MIXER_ROUTING: | |
933 | case WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING: | |
934 | case WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING: | |
935 | case WM8994_DAC1_LEFT_VOLUME: | |
936 | case WM8994_DAC1_RIGHT_VOLUME: | |
937 | case WM8994_DAC2_LEFT_VOLUME: | |
938 | case WM8994_DAC2_RIGHT_VOLUME: | |
939 | case WM8994_DAC_SOFTMUTE: | |
940 | case WM8994_OVERSAMPLING: | |
941 | case WM8994_SIDETONE: | |
942 | case WM8994_GPIO_1: | |
943 | case WM8994_GPIO_2: | |
944 | case WM8994_GPIO_3: | |
945 | case WM8994_GPIO_4: | |
946 | case WM8994_GPIO_5: | |
947 | case WM8994_GPIO_6: | |
948 | case WM8994_GPIO_8: | |
949 | case WM8994_GPIO_9: | |
950 | case WM8994_GPIO_10: | |
951 | case WM8994_GPIO_11: | |
952 | case WM8994_PULL_CONTROL_1: | |
953 | case WM8994_PULL_CONTROL_2: | |
954 | case WM8994_INTERRUPT_STATUS_1: | |
955 | case WM8994_INTERRUPT_STATUS_2: | |
956 | case WM8994_INTERRUPT_RAW_STATUS_2: | |
957 | case WM8994_INTERRUPT_STATUS_1_MASK: | |
958 | case WM8994_INTERRUPT_STATUS_2_MASK: | |
959 | case WM8994_INTERRUPT_CONTROL: | |
960 | case WM8994_IRQ_DEBOUNCE: | |
961 | return true; | |
962 | default: | |
963 | return false; | |
964 | } | |
965 | } | |
966 | ||
967 | static bool wm8994_readable_register(struct device *dev, unsigned int reg) | |
968 | { | |
969 | switch (reg) { | |
970 | case WM8994_DC_SERVO_READBACK: | |
971 | case WM8994_WRITE_SEQUENCER_CTRL_1: | |
972 | case WM8994_WRITE_SEQUENCER_CTRL_2: | |
973 | case WM8994_AIF1_ADC2_LEFT_VOLUME: | |
974 | case WM8994_AIF1_ADC2_RIGHT_VOLUME: | |
975 | case WM8994_AIF1_DAC2_LEFT_VOLUME: | |
976 | case WM8994_AIF1_DAC2_RIGHT_VOLUME: | |
977 | case WM8994_AIF1_ADC2_FILTERS: | |
978 | case WM8994_AIF1_DAC2_FILTERS_1: | |
979 | case WM8994_AIF1_DAC2_FILTERS_2: | |
980 | case WM8958_AIF1_DAC2_NOISE_GATE: | |
981 | case WM8994_AIF1_DRC2_1: | |
982 | case WM8994_AIF1_DRC2_2: | |
983 | case WM8994_AIF1_DRC2_3: | |
984 | case WM8994_AIF1_DRC2_4: | |
985 | case WM8994_AIF1_DRC2_5: | |
986 | case WM8994_AIF1_DAC2_EQ_GAINS_1: | |
987 | case WM8994_AIF1_DAC2_EQ_GAINS_2: | |
988 | case WM8994_AIF1_DAC2_EQ_BAND_1_A: | |
989 | case WM8994_AIF1_DAC2_EQ_BAND_1_B: | |
990 | case WM8994_AIF1_DAC2_EQ_BAND_1_PG: | |
991 | case WM8994_AIF1_DAC2_EQ_BAND_2_A: | |
992 | case WM8994_AIF1_DAC2_EQ_BAND_2_B: | |
993 | case WM8994_AIF1_DAC2_EQ_BAND_2_C: | |
994 | case WM8994_AIF1_DAC2_EQ_BAND_2_PG: | |
995 | case WM8994_AIF1_DAC2_EQ_BAND_3_A: | |
996 | case WM8994_AIF1_DAC2_EQ_BAND_3_B: | |
997 | case WM8994_AIF1_DAC2_EQ_BAND_3_C: | |
998 | case WM8994_AIF1_DAC2_EQ_BAND_3_PG: | |
999 | case WM8994_AIF1_DAC2_EQ_BAND_4_A: | |
1000 | case WM8994_AIF1_DAC2_EQ_BAND_4_B: | |
1001 | case WM8994_AIF1_DAC2_EQ_BAND_4_C: | |
1002 | case WM8994_AIF1_DAC2_EQ_BAND_4_PG: | |
1003 | case WM8994_AIF1_DAC2_EQ_BAND_5_A: | |
1004 | case WM8994_AIF1_DAC2_EQ_BAND_5_B: | |
1005 | case WM8994_AIF1_DAC2_EQ_BAND_5_PG: | |
1006 | case WM8994_AIF1_DAC2_EQ_BAND_1_C: | |
1007 | case WM8994_DAC2_MIXER_VOLUMES: | |
1008 | case WM8994_DAC2_LEFT_MIXER_ROUTING: | |
1009 | case WM8994_DAC2_RIGHT_MIXER_ROUTING: | |
1010 | case WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING: | |
1011 | case WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING: | |
1012 | case WM8994_DAC2_LEFT_VOLUME: | |
1013 | case WM8994_DAC2_RIGHT_VOLUME: | |
1014 | return true; | |
1015 | default: | |
1016 | return wm1811_readable_register(dev, reg); | |
1017 | } | |
1018 | } | |
1019 | ||
1020 | static bool wm8958_readable_register(struct device *dev, unsigned int reg) | |
1021 | { | |
1022 | switch (reg) { | |
1023 | case WM8958_DSP2_PROGRAM: | |
1024 | case WM8958_DSP2_CONFIG: | |
1025 | case WM8958_DSP2_MAGICNUM: | |
1026 | case WM8958_DSP2_RELEASEYEAR: | |
1027 | case WM8958_DSP2_RELEASEMONTHDAY: | |
1028 | case WM8958_DSP2_RELEASETIME: | |
1029 | case WM8958_DSP2_VERMAJMIN: | |
1030 | case WM8958_DSP2_VERBUILD: | |
1031 | case WM8958_DSP2_TESTREG: | |
1032 | case WM8958_DSP2_XORREG: | |
1033 | case WM8958_DSP2_SHIFTMAXX: | |
1034 | case WM8958_DSP2_SHIFTMAXY: | |
1035 | case WM8958_DSP2_SHIFTMAXZ: | |
1036 | case WM8958_DSP2_SHIFTMAXEXTLO: | |
1037 | case WM8958_DSP2_AESSELECT: | |
1038 | case WM8958_DSP2_EXECCONTROL: | |
1039 | case WM8958_DSP2_SAMPLEBREAK: | |
1040 | case WM8958_DSP2_COUNTBREAK: | |
1041 | case WM8958_DSP2_INTSTATUS: | |
1042 | case WM8958_DSP2_EVENTSTATUS: | |
1043 | case WM8958_DSP2_INTMASK: | |
1044 | case WM8958_DSP2_CONFIGDWIDTH: | |
1045 | case WM8958_DSP2_CONFIGINSTR: | |
1046 | case WM8958_DSP2_CONFIGDMEM: | |
1047 | case WM8958_DSP2_CONFIGDELAYS: | |
1048 | case WM8958_DSP2_CONFIGNUMIO: | |
1049 | case WM8958_DSP2_CONFIGEXTDEPTH: | |
1050 | case WM8958_DSP2_CONFIGMULTIPLIER: | |
1051 | case WM8958_DSP2_CONFIGCTRLDWIDTH: | |
1052 | case WM8958_DSP2_CONFIGPIPELINE: | |
1053 | case WM8958_DSP2_SHIFTMAXEXTHI: | |
1054 | case WM8958_DSP2_SWVERSIONREG: | |
1055 | case WM8958_DSP2_CONFIGXMEM: | |
1056 | case WM8958_DSP2_CONFIGYMEM: | |
1057 | case WM8958_DSP2_CONFIGZMEM: | |
1058 | case WM8958_FW_BUILD_1: | |
1059 | case WM8958_FW_BUILD_0: | |
1060 | case WM8958_FW_ID_1: | |
1061 | case WM8958_FW_ID_0: | |
1062 | case WM8958_FW_MAJOR_1: | |
1063 | case WM8958_FW_MAJOR_0: | |
1064 | case WM8958_FW_MINOR_1: | |
1065 | case WM8958_FW_MINOR_0: | |
1066 | case WM8958_FW_PATCH_1: | |
1067 | case WM8958_FW_PATCH_0: | |
1068 | case WM8958_MBC_BAND_1_K_1: | |
1069 | case WM8958_MBC_BAND_1_K_2: | |
1070 | case WM8958_MBC_BAND_1_N1_1: | |
1071 | case WM8958_MBC_BAND_1_N1_2: | |
1072 | case WM8958_MBC_BAND_1_N2_1: | |
1073 | case WM8958_MBC_BAND_1_N2_2: | |
1074 | case WM8958_MBC_BAND_1_N3_1: | |
1075 | case WM8958_MBC_BAND_1_N3_2: | |
1076 | case WM8958_MBC_BAND_1_N4_1: | |
1077 | case WM8958_MBC_BAND_1_N4_2: | |
1078 | case WM8958_MBC_BAND_1_N5_1: | |
1079 | case WM8958_MBC_BAND_1_N5_2: | |
1080 | case WM8958_MBC_BAND_1_X1_1: | |
1081 | case WM8958_MBC_BAND_1_X1_2: | |
1082 | case WM8958_MBC_BAND_1_X2_1: | |
1083 | case WM8958_MBC_BAND_1_X2_2: | |
1084 | case WM8958_MBC_BAND_1_X3_1: | |
1085 | case WM8958_MBC_BAND_1_X3_2: | |
1086 | case WM8958_MBC_BAND_1_ATTACK_1: | |
1087 | case WM8958_MBC_BAND_1_ATTACK_2: | |
1088 | case WM8958_MBC_BAND_1_DECAY_1: | |
1089 | case WM8958_MBC_BAND_1_DECAY_2: | |
1090 | case WM8958_MBC_BAND_2_K_1: | |
1091 | case WM8958_MBC_BAND_2_K_2: | |
1092 | case WM8958_MBC_BAND_2_N1_1: | |
1093 | case WM8958_MBC_BAND_2_N1_2: | |
1094 | case WM8958_MBC_BAND_2_N2_1: | |
1095 | case WM8958_MBC_BAND_2_N2_2: | |
1096 | case WM8958_MBC_BAND_2_N3_1: | |
1097 | case WM8958_MBC_BAND_2_N3_2: | |
1098 | case WM8958_MBC_BAND_2_N4_1: | |
1099 | case WM8958_MBC_BAND_2_N4_2: | |
1100 | case WM8958_MBC_BAND_2_N5_1: | |
1101 | case WM8958_MBC_BAND_2_N5_2: | |
1102 | case WM8958_MBC_BAND_2_X1_1: | |
1103 | case WM8958_MBC_BAND_2_X1_2: | |
1104 | case WM8958_MBC_BAND_2_X2_1: | |
1105 | case WM8958_MBC_BAND_2_X2_2: | |
1106 | case WM8958_MBC_BAND_2_X3_1: | |
1107 | case WM8958_MBC_BAND_2_X3_2: | |
1108 | case WM8958_MBC_BAND_2_ATTACK_1: | |
1109 | case WM8958_MBC_BAND_2_ATTACK_2: | |
1110 | case WM8958_MBC_BAND_2_DECAY_1: | |
1111 | case WM8958_MBC_BAND_2_DECAY_2: | |
1112 | case WM8958_MBC_B2_PG2_1: | |
1113 | case WM8958_MBC_B2_PG2_2: | |
1114 | case WM8958_MBC_B1_PG2_1: | |
1115 | case WM8958_MBC_B1_PG2_2: | |
1116 | case WM8958_MBC_CROSSOVER_1: | |
1117 | case WM8958_MBC_CROSSOVER_2: | |
1118 | case WM8958_MBC_HPF_1: | |
1119 | case WM8958_MBC_HPF_2: | |
1120 | case WM8958_MBC_LPF_1: | |
1121 | case WM8958_MBC_LPF_2: | |
1122 | case WM8958_MBC_RMS_LIMIT_1: | |
1123 | case WM8958_MBC_RMS_LIMIT_2: | |
1124 | return true; | |
1125 | default: | |
1126 | return wm8994_readable_register(dev, reg); | |
1127 | } | |
1128 | } | |
1129 | ||
1130 | static bool wm8994_volatile_register(struct device *dev, unsigned int reg) | |
1131 | { | |
1132 | switch (reg) { | |
1133 | case WM8994_SOFTWARE_RESET: | |
1134 | case WM8994_DC_SERVO_1: | |
1135 | case WM8994_DC_SERVO_READBACK: | |
1136 | case WM8994_RATE_STATUS: | |
1137 | case WM8958_MIC_DETECT_3: | |
1138 | case WM8994_DC_SERVO_4E: | |
1139 | case WM8994_CHIP_REVISION: | |
1140 | case WM8994_INTERRUPT_STATUS_1: | |
1141 | case WM8994_INTERRUPT_STATUS_2: | |
1142 | return true; | |
1143 | default: | |
1144 | return false; | |
1145 | } | |
1146 | } | |
1147 | ||
1148 | static bool wm8958_volatile_register(struct device *dev, unsigned int reg) | |
1149 | { | |
1150 | switch (reg) { | |
1151 | case WM8958_DSP2_MAGICNUM: | |
1152 | case WM8958_DSP2_RELEASEYEAR: | |
1153 | case WM8958_DSP2_RELEASEMONTHDAY: | |
1154 | case WM8958_DSP2_RELEASETIME: | |
1155 | case WM8958_DSP2_VERMAJMIN: | |
1156 | case WM8958_DSP2_VERBUILD: | |
1157 | case WM8958_DSP2_EXECCONTROL: | |
1158 | case WM8958_DSP2_SWVERSIONREG: | |
1159 | case WM8958_DSP2_CONFIGXMEM: | |
1160 | case WM8958_DSP2_CONFIGYMEM: | |
1161 | case WM8958_DSP2_CONFIGZMEM: | |
1162 | case WM8958_FW_BUILD_1: | |
1163 | case WM8958_FW_BUILD_0: | |
1164 | case WM8958_FW_ID_1: | |
1165 | case WM8958_FW_ID_0: | |
1166 | case WM8958_FW_MAJOR_1: | |
1167 | case WM8958_FW_MAJOR_0: | |
1168 | case WM8958_FW_MINOR_1: | |
1169 | case WM8958_FW_MINOR_0: | |
1170 | case WM8958_FW_PATCH_1: | |
1171 | case WM8958_FW_PATCH_0: | |
1172 | return true; | |
1173 | default: | |
1174 | return wm8994_volatile_register(dev, reg); | |
1175 | } | |
1176 | } | |
1177 | ||
1178 | struct regmap_config wm1811_regmap_config = { | |
1179 | .reg_bits = 16, | |
1180 | .val_bits = 16, | |
1181 | ||
1182 | .cache_type = REGCACHE_RBTREE, | |
1183 | ||
1184 | .reg_defaults = wm1811_defaults, | |
1185 | .num_reg_defaults = ARRAY_SIZE(wm1811_defaults), | |
1186 | ||
1187 | .max_register = WM8994_MAX_REGISTER, | |
1188 | .volatile_reg = wm8994_volatile_register, | |
1189 | .readable_reg = wm1811_readable_register, | |
1190 | }; | |
1191 | ||
1192 | struct regmap_config wm8994_regmap_config = { | |
1193 | .reg_bits = 16, | |
1194 | .val_bits = 16, | |
1195 | ||
1196 | .cache_type = REGCACHE_RBTREE, | |
1197 | ||
1198 | .reg_defaults = wm8994_defaults, | |
1199 | .num_reg_defaults = ARRAY_SIZE(wm8994_defaults), | |
1200 | ||
1201 | .max_register = WM8994_MAX_REGISTER, | |
1202 | .volatile_reg = wm8994_volatile_register, | |
1203 | .readable_reg = wm8994_readable_register, | |
1204 | }; | |
1205 | ||
1206 | struct regmap_config wm8958_regmap_config = { | |
1207 | .reg_bits = 16, | |
1208 | .val_bits = 16, | |
1209 | ||
1210 | .cache_type = REGCACHE_RBTREE, | |
1211 | ||
1212 | .reg_defaults = wm8958_defaults, | |
1213 | .num_reg_defaults = ARRAY_SIZE(wm8958_defaults), | |
1214 | ||
1215 | .max_register = WM8994_MAX_REGISTER, | |
1216 | .volatile_reg = wm8958_volatile_register, | |
1217 | .readable_reg = wm8958_readable_register, | |
1218 | }; | |
34697898 MB |
1219 | |
1220 | struct regmap_config wm8994_base_regmap_config = { | |
1221 | .reg_bits = 16, | |
1222 | .val_bits = 16, | |
1223 | }; |