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d5dc17c7 JY |
1 | /* |
2 | * s2mpb02-irq.c - Interrupt controller support for S2MPB02 | |
3 | * | |
4 | * Copyright (C) 2014 Samsung Electronics Co.Ltd | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | * | |
20 | * This driver is based on max77804-irq.c | |
21 | */ | |
22 | ||
23 | #include <linux/err.h> | |
24 | #include <linux/irq.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/gpio.h> | |
27 | #include <linux/mfd/s2mpb02.h> | |
28 | #include <linux/mfd/s2mpb02-regulator.h> | |
29 | ||
30 | static const u8 s2mpb02_mask_reg[] = { | |
31 | [LED_INT] = S2MPB02_REG_INT1M, | |
32 | }; | |
33 | ||
34 | struct s2mpb02_irq_data { | |
35 | int mask; | |
36 | enum s2mpb02_irq_source group; | |
37 | }; | |
38 | ||
39 | static const struct s2mpb02_irq_data s2mpb02_irqs[] = { | |
40 | [S2MPB02_LED_IRQ_IRLED_END] = { | |
41 | .group = LED_INT, | |
42 | .mask = 1 << 5 | |
43 | }, | |
44 | }; | |
45 | ||
46 | static void s2mpb02_irq_lock(struct irq_data *data) | |
47 | { | |
48 | struct s2mpb02_dev *s2mpb02 = irq_get_chip_data(data->irq); | |
49 | ||
50 | mutex_lock(&s2mpb02->irqlock); | |
51 | } | |
52 | ||
53 | static void s2mpb02_irq_sync_unlock(struct irq_data *data) | |
54 | { | |
55 | struct s2mpb02_dev *s2mpb02 = irq_get_chip_data(data->irq); | |
56 | int i; | |
57 | ||
58 | for (i = 0; i < S2MPB02_IRQ_GROUP_NR; i++) { | |
59 | u8 mask_reg = s2mpb02_mask_reg[i]; | |
60 | struct i2c_client *i2c = s2mpb02->i2c; | |
61 | ||
62 | if (mask_reg == S2MPB02_REG_INVALID || IS_ERR_OR_NULL(i2c)) | |
63 | continue; | |
64 | s2mpb02->irq_masks_cache[i] = s2mpb02->irq_masks_cur[i]; | |
65 | ||
66 | s2mpb02_write_reg(i2c, s2mpb02_mask_reg[i], | |
67 | s2mpb02->irq_masks_cur[i]); | |
68 | } | |
69 | ||
70 | mutex_unlock(&s2mpb02->irqlock); | |
71 | } | |
72 | ||
73 | static const inline struct s2mpb02_irq_data * | |
74 | irq_to_s2mpb02_irq(struct s2mpb02_dev *s2mpb02, int irq) | |
75 | { | |
76 | return &s2mpb02_irqs[irq - s2mpb02->irq_base]; | |
77 | } | |
78 | ||
79 | static void s2mpb02_irq_mask(struct irq_data *data) | |
80 | { | |
81 | struct s2mpb02_dev *s2mpb02 = irq_get_chip_data(data->irq); | |
82 | const struct s2mpb02_irq_data *irq_data = | |
83 | irq_to_s2mpb02_irq(s2mpb02, data->irq); | |
84 | ||
85 | if (irq_data->group >= S2MPB02_IRQ_GROUP_NR) | |
86 | return; | |
87 | ||
88 | s2mpb02->irq_masks_cur[irq_data->group] |= irq_data->mask; | |
89 | } | |
90 | ||
91 | static void s2mpb02_irq_unmask(struct irq_data *data) | |
92 | { | |
93 | struct s2mpb02_dev *s2mpb02 = irq_get_chip_data(data->irq); | |
94 | const struct s2mpb02_irq_data *irq_data = | |
95 | irq_to_s2mpb02_irq(s2mpb02, data->irq); | |
96 | ||
97 | if (irq_data->group >= S2MPB02_IRQ_GROUP_NR) | |
98 | return; | |
99 | ||
100 | s2mpb02->irq_masks_cur[irq_data->group] &= ~irq_data->mask; | |
101 | } | |
102 | ||
103 | static struct irq_chip s2mpb02_irq_chip = { | |
104 | .name = MFD_DEV_NAME, | |
105 | .irq_bus_lock = s2mpb02_irq_lock, | |
106 | .irq_bus_sync_unlock = s2mpb02_irq_sync_unlock, | |
107 | .irq_mask = s2mpb02_irq_mask, | |
108 | .irq_unmask = s2mpb02_irq_unmask, | |
109 | }; | |
110 | ||
111 | static irqreturn_t s2mpb02_irq_thread(int irq, void *data) | |
112 | { | |
113 | struct s2mpb02_dev *s2mpb02 = data; | |
114 | u8 irq_reg[S2MPB02_IRQ_GROUP_NR] = {0}; | |
115 | int i, ret; | |
116 | ||
117 | pr_debug("%s: irq gpio pre-state(0x%02x)\n", __func__, | |
118 | gpio_get_value(s2mpb02->irq_gpio)); | |
119 | ||
120 | /* LED_INT */ | |
121 | ret = s2mpb02_read_reg(s2mpb02->i2c, | |
122 | S2MPB02_REG_INT1, &irq_reg[LED_INT]); | |
123 | pr_info("%s: led interrupt(0x%02x)\n", | |
124 | __func__, irq_reg[LED_INT]); | |
125 | ||
126 | pr_debug("%s: irq gpio post-state(0x%02x)\n", __func__, | |
127 | gpio_get_value(s2mpb02->irq_gpio)); | |
128 | ||
129 | /* Apply masking */ | |
130 | for (i = 0; i < S2MPB02_IRQ_GROUP_NR; i++) | |
131 | irq_reg[i] &= ~s2mpb02->irq_masks_cur[i]; | |
132 | ||
133 | /* Report */ | |
134 | for (i = 0; i < S2MPB02_IRQ_NR; i++) { | |
135 | if (irq_reg[s2mpb02_irqs[i].group] & s2mpb02_irqs[i].mask) | |
136 | handle_nested_irq(s2mpb02->irq_base + i); | |
137 | } | |
138 | ||
139 | return IRQ_HANDLED; | |
140 | } | |
141 | ||
142 | int s2mpb02_irq_init(struct s2mpb02_dev *s2mpb02) | |
143 | { | |
144 | int i; | |
145 | int ret; | |
146 | ||
147 | if (!s2mpb02->irq_gpio) { | |
148 | s2mpb02->irq_base = 0; | |
149 | return 0; | |
150 | } | |
151 | ||
152 | if (s2mpb02->irq_base < 0) { | |
153 | pr_err("%s:%s No interrupt base specified.\n", | |
154 | MFD_DEV_NAME, __func__); | |
155 | return 0; | |
156 | } | |
157 | ||
158 | mutex_init(&s2mpb02->irqlock); | |
159 | ||
160 | s2mpb02->irq = gpio_to_irq(s2mpb02->irq_gpio); | |
161 | pr_info("%s:%s irq=%d, irq->gpio=%d\n", MFD_DEV_NAME, __func__, | |
162 | s2mpb02->irq, s2mpb02->irq_gpio); | |
163 | ||
164 | ret = gpio_request(s2mpb02->irq_gpio, "sub_pmic_irq"); | |
165 | if (ret) { | |
166 | pr_err("%s:%s failed requesting gpio %d\n", | |
167 | MFD_DEV_NAME, __func__, s2mpb02->irq_gpio); | |
168 | goto err; | |
169 | } | |
170 | gpio_direction_input(s2mpb02->irq_gpio); | |
171 | gpio_free(s2mpb02->irq_gpio); | |
172 | ||
173 | /* Mask interrupt sources */ | |
174 | for (i = 0; i < S2MPB02_IRQ_GROUP_NR; i++) { | |
175 | struct i2c_client *i2c; | |
176 | ||
177 | s2mpb02->irq_masks_cur[i] = 0xff; | |
178 | s2mpb02->irq_masks_cache[i] = 0xff; | |
179 | ||
180 | i2c = s2mpb02->i2c; | |
181 | ||
182 | if (IS_ERR_OR_NULL(i2c)) | |
183 | continue; | |
184 | if (s2mpb02_mask_reg[i] == S2MPB02_REG_INVALID) | |
185 | continue; | |
186 | s2mpb02_write_reg(i2c, s2mpb02_mask_reg[i], 0xff); | |
187 | } | |
188 | ||
189 | /* Register with genirq */ | |
190 | for (i = 0; i < S2MPB02_IRQ_NR; i++) { | |
191 | int cur_irq = i + s2mpb02->irq_base; | |
192 | ret = irq_set_chip_data(cur_irq, s2mpb02); | |
193 | if (ret) { | |
194 | dev_err(s2mpb02->dev, | |
195 | "Failed to irq_set_chip_data %d: %d\n", | |
196 | s2mpb02->irq, ret); | |
197 | goto err; | |
198 | } | |
199 | irq_set_chip_and_handler(cur_irq, &s2mpb02_irq_chip, | |
200 | handle_edge_irq); | |
201 | irq_set_nested_thread(cur_irq, 1); | |
202 | #ifdef CONFIG_ARM | |
203 | set_irq_flags(cur_irq, IRQF_VALID); | |
204 | #else | |
205 | irq_set_noprobe(cur_irq); | |
206 | #endif | |
207 | } | |
208 | ||
209 | ret = request_threaded_irq(s2mpb02->irq, NULL, s2mpb02_irq_thread, | |
210 | IRQF_TRIGGER_LOW | IRQF_ONESHOT, "s2mpb02-irq", s2mpb02); | |
211 | if (ret) { | |
212 | pr_err("%s:%s Failed to request IRQ %d: %d\n", MFD_DEV_NAME, | |
213 | __func__, s2mpb02->irq, ret); | |
214 | goto err; | |
215 | } | |
216 | ||
217 | return 0; | |
218 | err: | |
219 | mutex_destroy(&s2mpb02->i2c_lock); | |
220 | return ret; | |
221 | } | |
222 | ||
223 | void s2mpb02_irq_exit(struct s2mpb02_dev *s2mpb02) | |
224 | { | |
225 | if (s2mpb02->irq) | |
226 | free_irq(s2mpb02->irq, s2mpb02); | |
227 | } | |
228 |