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mfd: Make omap-usb-host TLL mode work again
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / mfd / omap-usb-host.c
CommitLineData
17cdd29d
KM		 1/**
2 * omap-usb-host.c - The USBHS core driver for OMAP EHCI & OHCI
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com
5 * Author: Keshava Munegowda <keshava_mgowda@ti.com>
6 *
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 of
9 * the License as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19#include <linux/kernel.h>
20#include <linux/types.h>
21#include <linux/slab.h>
22#include <linux/delay.h>
23#include <linux/platform_device.h>
24#include <linux/clk.h>
25#include <linux/dma-mapping.h>
26#include <linux/spinlock.h>
27#include <linux/gpio.h>
17cdd29d
KM		 28#include <plat/usb.h>
29
30#define USBHS_DRIVER_NAME "usbhs-omap"
31#define OMAP_EHCI_DEVICE "ehci-omap"
32#define OMAP_OHCI_DEVICE "ohci-omap3"
33
34/* OMAP USBHOST Register addresses */
35
36/* TLL Register Set */
37#define OMAP_USBTLL_REVISION (0x00)
38#define OMAP_USBTLL_SYSCONFIG (0x10)
39#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8)
40#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3)
41#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2)
42#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1)
43#define OMAP_USBTLL_SYSCONFIG_AUTOIDLE (1 << 0)
44
45#define OMAP_USBTLL_SYSSTATUS (0x14)
46#define OMAP_USBTLL_SYSSTATUS_RESETDONE (1 << 0)
47
48#define OMAP_USBTLL_IRQSTATUS (0x18)
49#define OMAP_USBTLL_IRQENABLE (0x1C)
50
51#define OMAP_TLL_SHARED_CONF (0x30)
52#define OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN (1 << 6)
53#define OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN (1 << 5)
54#define OMAP_TLL_SHARED_CONF_USB_DIVRATION (1 << 2)
55#define OMAP_TLL_SHARED_CONF_FCLK_REQ (1 << 1)
56#define OMAP_TLL_SHARED_CONF_FCLK_IS_ON (1 << 0)
57
58#define OMAP_TLL_CHANNEL_CONF(num) (0x040 + 0x004 * num)
59#define OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT 24
60#define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF (1 << 11)
61#define OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE (1 << 10)
62#define OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE (1 << 9)
63#define OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE (1 << 8)
64#define OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS (1 << 1)
65#define OMAP_TLL_CHANNEL_CONF_CHANEN (1 << 0)
66
67#define OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0 0x0
68#define OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM 0x1
69#define OMAP_TLL_FSLSMODE_3PIN_PHY 0x2
70#define OMAP_TLL_FSLSMODE_4PIN_PHY 0x3
71#define OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0 0x4
72#define OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM 0x5
73#define OMAP_TLL_FSLSMODE_3PIN_TLL 0x6
74#define OMAP_TLL_FSLSMODE_4PIN_TLL 0x7
75#define OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0 0xA
76#define OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM 0xB
77
78#define OMAP_TLL_ULPI_FUNCTION_CTRL(num) (0x804 + 0x100 * num)
79#define OMAP_TLL_ULPI_INTERFACE_CTRL(num) (0x807 + 0x100 * num)
80#define OMAP_TLL_ULPI_OTG_CTRL(num) (0x80A + 0x100 * num)
81#define OMAP_TLL_ULPI_INT_EN_RISE(num) (0x80D + 0x100 * num)
82#define OMAP_TLL_ULPI_INT_EN_FALL(num) (0x810 + 0x100 * num)
83#define OMAP_TLL_ULPI_INT_STATUS(num) (0x813 + 0x100 * num)
84#define OMAP_TLL_ULPI_INT_LATCH(num) (0x814 + 0x100 * num)
85#define OMAP_TLL_ULPI_DEBUG(num) (0x815 + 0x100 * num)
86#define OMAP_TLL_ULPI_SCRATCH_REGISTER(num) (0x816 + 0x100 * num)
87
88#define OMAP_TLL_CHANNEL_COUNT 3
89#define OMAP_TLL_CHANNEL_1_EN_MASK (1 << 0)
90#define OMAP_TLL_CHANNEL_2_EN_MASK (1 << 1)
91#define OMAP_TLL_CHANNEL_3_EN_MASK (1 << 2)
92
93/* UHH Register Set */
94#define OMAP_UHH_REVISION (0x00)
95#define OMAP_UHH_SYSCONFIG (0x10)
96#define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12)
97#define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8)
98#define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3)
99#define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2)
100#define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1)
101#define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0)
102
103#define OMAP_UHH_SYSSTATUS (0x14)
104#define OMAP_UHH_HOSTCONFIG (0x40)
105#define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0)
106#define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0)
107#define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11)
108#define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12)
109#define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2)
110#define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3)
111#define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4)
112#define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5)
113#define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8)
114#define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9)
115#define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10)
116#define OMAP4_UHH_HOSTCONFIG_APP_START_CLK (1 << 31)
117
118/* OMAP4-specific defines */
119#define OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR (3 << 2)
120#define OMAP4_UHH_SYSCONFIG_NOIDLE (1 << 2)
121#define OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR (3 << 4)
122#define OMAP4_UHH_SYSCONFIG_NOSTDBY (1 << 4)
123#define OMAP4_UHH_SYSCONFIG_SOFTRESET (1 << 0)
124
125#define OMAP4_P1_MODE_CLEAR (3 << 16)
126#define OMAP4_P1_MODE_TLL (1 << 16)
127#define OMAP4_P1_MODE_HSIC (3 << 16)
128#define OMAP4_P2_MODE_CLEAR (3 << 18)
129#define OMAP4_P2_MODE_TLL (1 << 18)
130#define OMAP4_P2_MODE_HSIC (3 << 18)
131
132#define OMAP_REV2_TLL_CHANNEL_COUNT 2
133
134#define OMAP_UHH_DEBUG_CSR (0x44)
135
136/* Values of UHH_REVISION - Note: these are not given in the TRM */
137#define OMAP_USBHS_REV1 0x00000010 /* OMAP3 */
138#define OMAP_USBHS_REV2 0x50700100 /* OMAP4 */
139
140#define is_omap_usbhs_rev1(x) (x->usbhs_rev == OMAP_USBHS_REV1)
141#define is_omap_usbhs_rev2(x) (x->usbhs_rev == OMAP_USBHS_REV2)
142
143#define is_ehci_phy_mode(x) (x == OMAP_EHCI_PORT_MODE_PHY)
144#define is_ehci_tll_mode(x) (x == OMAP_EHCI_PORT_MODE_TLL)
145#define is_ehci_hsic_mode(x) (x == OMAP_EHCI_PORT_MODE_HSIC)
146
147
148struct usbhs_hcd_omap {
8f2df014
KM		 149 struct clk *usbhost_ick;
150 struct clk *usbhost_hs_fck;
151 struct clk *usbhost_fs_fck;
17cdd29d
KM		 152 struct clk *xclk60mhsp1_ck;
153 struct clk *xclk60mhsp2_ck;
154 struct clk *utmi_p1_fck;
155 struct clk *usbhost_p1_fck;
156 struct clk *usbtll_p1_fck;
157 struct clk *utmi_p2_fck;
158 struct clk *usbhost_p2_fck;
159 struct clk *usbtll_p2_fck;
160 struct clk *init_60m_fclk;
8f2df014
KM		 161 struct clk *usbtll_fck;
162 struct clk *usbtll_ick;
17cdd29d
KM		 163
164 void __iomem *uhh_base;
165 void __iomem *tll_base;
166
167 struct usbhs_omap_platform_data platdata;
168
169 u32 usbhs_rev;
170 spinlock_t lock;
171 int count;
172};
173/*-------------------------------------------------------------------------*/
174
175const char usbhs_driver_name[] = USBHS_DRIVER_NAME;
176static u64 usbhs_dmamask = ~(u32)0;
177
178/*-------------------------------------------------------------------------*/
179
180static inline void usbhs_write(void __iomem *base, u32 reg, u32 val)
181{
182 __raw_writel(val, base + reg);
183}
184
185static inline u32 usbhs_read(void __iomem *base, u32 reg)
186{
187 return __raw_readl(base + reg);
188}
189
190static inline void usbhs_writeb(void __iomem *base, u8 reg, u8 val)
191{
192 __raw_writeb(val, base + reg);
193}
194
195static inline u8 usbhs_readb(void __iomem *base, u8 reg)
196{
197 return __raw_readb(base + reg);
198}
199
200/*-------------------------------------------------------------------------*/
201
202static struct platform_device *omap_usbhs_alloc_child(const char *name,
203 struct resource *res, int num_resources, void *pdata,
204 size_t pdata_size, struct device *dev)
205{
206 struct platform_device *child;
207 int ret;
208
209 child = platform_device_alloc(name, 0);
210
211 if (!child) {
212 dev_err(dev, "platform_device_alloc %s failed\n", name);
213 goto err_end;
214 }
215
216 ret = platform_device_add_resources(child, res, num_resources);
217 if (ret) {
218 dev_err(dev, "platform_device_add_resources failed\n");
219 goto err_alloc;
220 }
221
222 ret = platform_device_add_data(child, pdata, pdata_size);
223 if (ret) {
224 dev_err(dev, "platform_device_add_data failed\n");
225 goto err_alloc;
226 }
227
228 child->dev.dma_mask = &usbhs_dmamask;
229 child->dev.coherent_dma_mask = 0xffffffff;
230 child->dev.parent = dev;
231
232 ret = platform_device_add(child);
233 if (ret) {
234 dev_err(dev, "platform_device_add failed\n");
235 goto err_alloc;
236 }
237
238 return child;
239
240err_alloc:
241 platform_device_put(child);
242
243err_end:
244 return NULL;
245}
246
247static int omap_usbhs_alloc_children(struct platform_device *pdev)
248{
249 struct device *dev = &pdev->dev;
250 struct usbhs_hcd_omap *omap;
251 struct ehci_hcd_omap_platform_data *ehci_data;
252 struct ohci_hcd_omap_platform_data *ohci_data;
253 struct platform_device *ehci;
254 struct platform_device *ohci;
255 struct resource *res;
256 struct resource resources[2];
257 int ret;
258
259 omap = platform_get_drvdata(pdev);
260 ehci_data = omap->platdata.ehci_data;
261 ohci_data = omap->platdata.ohci_data;
262
263 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ehci");
264 if (!res) {
265 dev_err(dev, "EHCI get resource IORESOURCE_MEM failed\n");
266 ret = -ENODEV;
267 goto err_end;
268 }
269 resources[0] = *res;
270
271 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ehci-irq");
272 if (!res) {
273 dev_err(dev, " EHCI get resource IORESOURCE_IRQ failed\n");
274 ret = -ENODEV;
275 goto err_end;
276 }
277 resources[1] = *res;
278
279 ehci = omap_usbhs_alloc_child(OMAP_EHCI_DEVICE, resources, 2, ehci_data,
280 sizeof(*ehci_data), dev);
281
282 if (!ehci) {
283 dev_err(dev, "omap_usbhs_alloc_child failed\n");
d910774f 284 ret = -ENOMEM;
17cdd29d
KM		 285 goto err_end;
286 }
287
288 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ohci");
289 if (!res) {
290 dev_err(dev, "OHCI get resource IORESOURCE_MEM failed\n");
291 ret = -ENODEV;
292 goto err_ehci;
293 }
294 resources[0] = *res;
295
296 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ohci-irq");
297 if (!res) {
298 dev_err(dev, "OHCI get resource IORESOURCE_IRQ failed\n");
299 ret = -ENODEV;
300 goto err_ehci;
301 }
302 resources[1] = *res;
303
304 ohci = omap_usbhs_alloc_child(OMAP_OHCI_DEVICE, resources, 2, ohci_data,
305 sizeof(*ohci_data), dev);
306 if (!ohci) {
307 dev_err(dev, "omap_usbhs_alloc_child failed\n");
d910774f 308 ret = -ENOMEM;
17cdd29d
KM		 309 goto err_ehci;
310 }
311
312 return 0;
313
314err_ehci:
d910774f 315 platform_device_unregister(ehci);
17cdd29d
KM		 316
317err_end:
318 return ret;
319}
320
321/**
322 * usbhs_omap_probe - initialize TI-based HCDs
323 *
324 * Allocates basic resources for this USB host controller.
325 */
326static int __devinit usbhs_omap_probe(struct platform_device *pdev)
327{
328 struct device *dev = &pdev->dev;
329 struct usbhs_omap_platform_data *pdata = dev->platform_data;
330 struct usbhs_hcd_omap *omap;
331 struct resource *res;
332 int ret = 0;
333 int i;
334
335 if (!pdata) {
25985edc 336 dev_err(dev, "Missing platform data\n");
17cdd29d
KM		 337 ret = -ENOMEM;
338 goto end_probe;
339 }
340
341 omap = kzalloc(sizeof(*omap), GFP_KERNEL);
342 if (!omap) {
343 dev_err(dev, "Memory allocation failed\n");
344 ret = -ENOMEM;
345 goto end_probe;
346 }
347
348 spin_lock_init(&omap->lock);
349
350 for (i = 0; i < OMAP3_HS_USB_PORTS; i++)
351 omap->platdata.port_mode[i] = pdata->port_mode[i];
352
353 omap->platdata.ehci_data = pdata->ehci_data;
354 omap->platdata.ohci_data = pdata->ohci_data;
355
8f2df014
KM		 356 omap->usbhost_ick = clk_get(dev, "usbhost_ick");
357 if (IS_ERR(omap->usbhost_ick)) {
358 ret = PTR_ERR(omap->usbhost_ick);
359 dev_err(dev, "usbhost_ick failed error:%d\n", ret);
360 goto err_end;
361 }
362
363 omap->usbhost_hs_fck = clk_get(dev, "hs_fck");
364 if (IS_ERR(omap->usbhost_hs_fck)) {
365 ret = PTR_ERR(omap->usbhost_hs_fck);
366 dev_err(dev, "usbhost_hs_fck failed error:%d\n", ret);
367 goto err_usbhost_ick;
368 }
369
370 omap->usbhost_fs_fck = clk_get(dev, "fs_fck");
371 if (IS_ERR(omap->usbhost_fs_fck)) {
372 ret = PTR_ERR(omap->usbhost_fs_fck);
373 dev_err(dev, "usbhost_fs_fck failed error:%d\n", ret);
374 goto err_usbhost_hs_fck;
375 }
376
377 omap->usbtll_fck = clk_get(dev, "usbtll_fck");
378 if (IS_ERR(omap->usbtll_fck)) {
379 ret = PTR_ERR(omap->usbtll_fck);
380 dev_err(dev, "usbtll_fck failed error:%d\n", ret);
381 goto err_usbhost_fs_fck;
382 }
383
384 omap->usbtll_ick = clk_get(dev, "usbtll_ick");
385 if (IS_ERR(omap->usbtll_ick)) {
386 ret = PTR_ERR(omap->usbtll_ick);
387 dev_err(dev, "usbtll_ick failed error:%d\n", ret);
388 goto err_usbtll_fck;
389 }
17cdd29d
KM		 390
391 omap->utmi_p1_fck = clk_get(dev, "utmi_p1_gfclk");
392 if (IS_ERR(omap->utmi_p1_fck)) {
393 ret = PTR_ERR(omap->utmi_p1_fck);
394 dev_err(dev, "utmi_p1_gfclk failed error:%d\n", ret);
8f2df014 395 goto err_usbtll_ick;
17cdd29d
KM		 396 }
397
398 omap->xclk60mhsp1_ck = clk_get(dev, "xclk60mhsp1_ck");
399 if (IS_ERR(omap->xclk60mhsp1_ck)) {
400 ret = PTR_ERR(omap->xclk60mhsp1_ck);
401 dev_err(dev, "xclk60mhsp1_ck failed error:%d\n", ret);
402 goto err_utmi_p1_fck;
403 }
404
405 omap->utmi_p2_fck = clk_get(dev, "utmi_p2_gfclk");
406 if (IS_ERR(omap->utmi_p2_fck)) {
407 ret = PTR_ERR(omap->utmi_p2_fck);
408 dev_err(dev, "utmi_p2_gfclk failed error:%d\n", ret);
409 goto err_xclk60mhsp1_ck;
410 }
411
412 omap->xclk60mhsp2_ck = clk_get(dev, "xclk60mhsp2_ck");
413 if (IS_ERR(omap->xclk60mhsp2_ck)) {
414 ret = PTR_ERR(omap->xclk60mhsp2_ck);
415 dev_err(dev, "xclk60mhsp2_ck failed error:%d\n", ret);
416 goto err_utmi_p2_fck;
417 }
418
419 omap->usbhost_p1_fck = clk_get(dev, "usb_host_hs_utmi_p1_clk");
420 if (IS_ERR(omap->usbhost_p1_fck)) {
421 ret = PTR_ERR(omap->usbhost_p1_fck);
422 dev_err(dev, "usbhost_p1_fck failed error:%d\n", ret);
423 goto err_xclk60mhsp2_ck;
424 }
425
426 omap->usbtll_p1_fck = clk_get(dev, "usb_tll_hs_usb_ch0_clk");
427 if (IS_ERR(omap->usbtll_p1_fck)) {
428 ret = PTR_ERR(omap->usbtll_p1_fck);
429 dev_err(dev, "usbtll_p1_fck failed error:%d\n", ret);
430 goto err_usbhost_p1_fck;
431 }
432
433 omap->usbhost_p2_fck = clk_get(dev, "usb_host_hs_utmi_p2_clk");
434 if (IS_ERR(omap->usbhost_p2_fck)) {
435 ret = PTR_ERR(omap->usbhost_p2_fck);
436 dev_err(dev, "usbhost_p2_fck failed error:%d\n", ret);
437 goto err_usbtll_p1_fck;
438 }
439
440 omap->usbtll_p2_fck = clk_get(dev, "usb_tll_hs_usb_ch1_clk");
441 if (IS_ERR(omap->usbtll_p2_fck)) {
442 ret = PTR_ERR(omap->usbtll_p2_fck);
443 dev_err(dev, "usbtll_p2_fck failed error:%d\n", ret);
444 goto err_usbhost_p2_fck;
445 }
446
447 omap->init_60m_fclk = clk_get(dev, "init_60m_fclk");
448 if (IS_ERR(omap->init_60m_fclk)) {
449 ret = PTR_ERR(omap->init_60m_fclk);
450 dev_err(dev, "init_60m_fclk failed error:%d\n", ret);
451 goto err_usbtll_p2_fck;
452 }
453
454 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "uhh");
455 if (!res) {
456 dev_err(dev, "UHH EHCI get resource failed\n");
457 ret = -ENODEV;
458 goto err_init_60m_fclk;
459 }
460
461 omap->uhh_base = ioremap(res->start, resource_size(res));
462 if (!omap->uhh_base) {
463 dev_err(dev, "UHH ioremap failed\n");
464 ret = -ENOMEM;
465 goto err_init_60m_fclk;
466 }
467
468 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tll");
469 if (!res) {
470 dev_err(dev, "UHH EHCI get resource failed\n");
471 ret = -ENODEV;
472 goto err_tll;
473 }
474
475 omap->tll_base = ioremap(res->start, resource_size(res));
476 if (!omap->tll_base) {
477 dev_err(dev, "TLL ioremap failed\n");
478 ret = -ENOMEM;
479 goto err_tll;
480 }
481
482 platform_set_drvdata(pdev, omap);
483
484 ret = omap_usbhs_alloc_children(pdev);
485 if (ret) {
486 dev_err(dev, "omap_usbhs_alloc_children failed\n");
487 goto err_alloc;
488 }
489
490 goto end_probe;
491
492err_alloc:
493 iounmap(omap->tll_base);
494
495err_tll:
496 iounmap(omap->uhh_base);
497
498err_init_60m_fclk:
499 clk_put(omap->init_60m_fclk);
500
501err_usbtll_p2_fck:
502 clk_put(omap->usbtll_p2_fck);
503
504err_usbhost_p2_fck:
505 clk_put(omap->usbhost_p2_fck);
506
507err_usbtll_p1_fck:
508 clk_put(omap->usbtll_p1_fck);
509
510err_usbhost_p1_fck:
511 clk_put(omap->usbhost_p1_fck);
512
513err_xclk60mhsp2_ck:
514 clk_put(omap->xclk60mhsp2_ck);
515
516err_utmi_p2_fck:
517 clk_put(omap->utmi_p2_fck);
518
519err_xclk60mhsp1_ck:
520 clk_put(omap->xclk60mhsp1_ck);
521
522err_utmi_p1_fck:
523 clk_put(omap->utmi_p1_fck);
524
8f2df014
KM		 525err_usbtll_ick:
526 clk_put(omap->usbtll_ick);
527
528err_usbtll_fck:
529 clk_put(omap->usbtll_fck);
530
531err_usbhost_fs_fck:
532 clk_put(omap->usbhost_fs_fck);
533
534err_usbhost_hs_fck:
535 clk_put(omap->usbhost_hs_fck);
536
537err_usbhost_ick:
538 clk_put(omap->usbhost_ick);
539
17cdd29d
KM		 540err_end:
541 kfree(omap);
542
543end_probe:
544 return ret;
545}
546
547/**
548 * usbhs_omap_remove - shutdown processing for UHH & TLL HCDs
549 * @pdev: USB Host Controller being removed
550 *
551 * Reverses the effect of usbhs_omap_probe().
552 */
553static int __devexit usbhs_omap_remove(struct platform_device *pdev)
554{
555 struct usbhs_hcd_omap *omap = platform_get_drvdata(pdev);
556
557 if (omap->count != 0) {
558 dev_err(&pdev->dev,
559 "Either EHCI or OHCI is still using usbhs core\n");
560 return -EBUSY;
561 }
562
563 iounmap(omap->tll_base);
564 iounmap(omap->uhh_base);
565 clk_put(omap->init_60m_fclk);
566 clk_put(omap->usbtll_p2_fck);
567 clk_put(omap->usbhost_p2_fck);
568 clk_put(omap->usbtll_p1_fck);
569 clk_put(omap->usbhost_p1_fck);
570 clk_put(omap->xclk60mhsp2_ck);
571 clk_put(omap->utmi_p2_fck);
572 clk_put(omap->xclk60mhsp1_ck);
573 clk_put(omap->utmi_p1_fck);
8f2df014
KM		 574 clk_put(omap->usbtll_ick);
575 clk_put(omap->usbtll_fck);
576 clk_put(omap->usbhost_fs_fck);
577 clk_put(omap->usbhost_hs_fck);
578 clk_put(omap->usbhost_ick);
17cdd29d
KM		 579 kfree(omap);
580
581 return 0;
582}
583
584static bool is_ohci_port(enum usbhs_omap_port_mode pmode)
585{
586 switch (pmode) {
587 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
588 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
589 case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
590 case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
591 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
592 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
593 case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
594 case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
595 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
596 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
597 return true;
598
599 default:
600 return false;
601 }
602}
603
604/*
605 * convert the port-mode enum to a value we can use in the FSLSMODE
606 * field of USBTLL_CHANNEL_CONF
607 */
608static unsigned ohci_omap3_fslsmode(enum usbhs_omap_port_mode mode)
609{
610 switch (mode) {
611 case OMAP_USBHS_PORT_MODE_UNUSED:
612 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
613 return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0;
614
615 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
616 return OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM;
617
618 case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
619 return OMAP_TLL_FSLSMODE_3PIN_PHY;
620
621 case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
622 return OMAP_TLL_FSLSMODE_4PIN_PHY;
623
624 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
625 return OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0;
626
627 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
628 return OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM;
629
630 case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
631 return OMAP_TLL_FSLSMODE_3PIN_TLL;
632
633 case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
634 return OMAP_TLL_FSLSMODE_4PIN_TLL;
635
636 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
637 return OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0;
638
639 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
640 return OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM;
641 default:
642 pr_warning("Invalid port mode, using default\n");
643 return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0;
644 }
645}
646
647static void usbhs_omap_tll_init(struct device *dev, u8 tll_channel_count)
648{
649 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
650 struct usbhs_omap_platform_data *pdata = dev->platform_data;
651 unsigned reg;
652 int i;
653
654 /* Program Common TLL register */
655 reg = usbhs_read(omap->tll_base, OMAP_TLL_SHARED_CONF);
656 reg |= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON
657 | OMAP_TLL_SHARED_CONF_USB_DIVRATION);
658 reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN;
659 reg &= ~OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN;
660
661 usbhs_write(omap->tll_base, OMAP_TLL_SHARED_CONF, reg);
662
663 /* Enable channels now */
664 for (i = 0; i < tll_channel_count; i++) {
665 reg = usbhs_read(omap->tll_base,
666 OMAP_TLL_CHANNEL_CONF(i));
667
668 if (is_ohci_port(pdata->port_mode[i])) {
669 reg |= ohci_omap3_fslsmode(pdata->port_mode[i])
670 << OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT;
671 reg |= OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS;
672 } else if (pdata->port_mode[i] == OMAP_EHCI_PORT_MODE_TLL) {
673
674 /* Disable AutoIdle, BitStuffing and use SDR Mode */
675 reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE
676 | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
677 | OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE);
678
17cdd29d
KM		 679 } else
680 continue;
681
682 reg |= OMAP_TLL_CHANNEL_CONF_CHANEN;
683 usbhs_write(omap->tll_base,
684 OMAP_TLL_CHANNEL_CONF(i), reg);
685
686 usbhs_writeb(omap->tll_base,
687 OMAP_TLL_ULPI_SCRATCH_REGISTER(i), 0xbe);
688 }
689}
690
691static int usbhs_enable(struct device *dev)
692{
693 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
694 struct usbhs_omap_platform_data *pdata = &omap->platdata;
695 unsigned long flags = 0;
696 int ret = 0;
8f2df014 697 unsigned long timeout;
17cdd29d
KM		 698 unsigned reg;
699
700 dev_dbg(dev, "starting TI HSUSB Controller\n");
701 if (!pdata) {
702 dev_dbg(dev, "missing platform_data\n");
d11536e4 703 return -ENODEV;
17cdd29d
KM		 704 }
705
706 spin_lock_irqsave(&omap->lock, flags);
707 if (omap->count > 0)
708 goto end_count;
709
8f2df014
KM		 710 clk_enable(omap->usbhost_ick);
711 clk_enable(omap->usbhost_hs_fck);
712 clk_enable(omap->usbhost_fs_fck);
713 clk_enable(omap->usbtll_fck);
714 clk_enable(omap->usbtll_ick);
17cdd29d
KM		 715
716 if (pdata->ehci_data->phy_reset) {
717 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) {
718 gpio_request(pdata->ehci_data->reset_gpio_port[0],
719 "USB1 PHY reset");
720 gpio_direction_output
557f447f 721 (pdata->ehci_data->reset_gpio_port[0], 0);
17cdd29d
KM		 722 }
723
724 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1])) {
725 gpio_request(pdata->ehci_data->reset_gpio_port[1],
726 "USB2 PHY reset");
727 gpio_direction_output
557f447f 728 (pdata->ehci_data->reset_gpio_port[1], 0);
17cdd29d
KM		 729 }
730
731 /* Hold the PHY in RESET for enough time till DIR is high */
732 udelay(10);
733 }
734
735 omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION);
736 dev_dbg(dev, "OMAP UHH_REVISION 0x%x\n", omap->usbhs_rev);
737
8f2df014
KM		 738 /* perform TLL soft reset, and wait until reset is complete */
739 usbhs_write(omap->tll_base, OMAP_USBTLL_SYSCONFIG,
740 OMAP_USBTLL_SYSCONFIG_SOFTRESET);
741
742 /* Wait for TLL reset to complete */
743 timeout = jiffies + msecs_to_jiffies(1000);
744 while (!(usbhs_read(omap->tll_base, OMAP_USBTLL_SYSSTATUS)
745 & OMAP_USBTLL_SYSSTATUS_RESETDONE)) {
746 cpu_relax();
747
748 if (time_after(jiffies, timeout)) {
749 dev_dbg(dev, "operation timed out\n");
750 ret = -EINVAL;
751 goto err_tll;
752 }
753 }
754
755 dev_dbg(dev, "TLL RESET DONE\n");
756
757 /* (1<<3) = no idle mode only for initial debugging */
758 usbhs_write(omap->tll_base, OMAP_USBTLL_SYSCONFIG,
759 OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
760 OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
761 OMAP_USBTLL_SYSCONFIG_AUTOIDLE);
762
763 /* Put UHH in NoIdle/NoStandby mode */
764 reg = usbhs_read(omap->uhh_base, OMAP_UHH_SYSCONFIG);
765 if (is_omap_usbhs_rev1(omap)) {
766 reg |= (OMAP_UHH_SYSCONFIG_ENAWAKEUP
767 | OMAP_UHH_SYSCONFIG_SIDLEMODE
768 | OMAP_UHH_SYSCONFIG_CACTIVITY
769 | OMAP_UHH_SYSCONFIG_MIDLEMODE);
770 reg &= ~OMAP_UHH_SYSCONFIG_AUTOIDLE;
771
772
773 } else if (is_omap_usbhs_rev2(omap)) {
774 reg &= ~OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR;
775 reg |= OMAP4_UHH_SYSCONFIG_NOIDLE;
776 reg &= ~OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR;
777 reg |= OMAP4_UHH_SYSCONFIG_NOSTDBY;
778 }
779
780 usbhs_write(omap->uhh_base, OMAP_UHH_SYSCONFIG, reg);
781
17cdd29d
KM		 782 reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
783 /* setup ULPI bypass and burst configurations */
784 reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
785 | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
786 | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN);
787 reg |= OMAP4_UHH_HOSTCONFIG_APP_START_CLK;
788 reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN;
789
790 if (is_omap_usbhs_rev1(omap)) {
791 if (pdata->port_mode[0] == OMAP_USBHS_PORT_MODE_UNUSED)
792 reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS;
793 if (pdata->port_mode[1] == OMAP_USBHS_PORT_MODE_UNUSED)
794 reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS;
795 if (pdata->port_mode[2] == OMAP_USBHS_PORT_MODE_UNUSED)
796 reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS;
797
798 /* Bypass the TLL module for PHY mode operation */
799 if (cpu_is_omap3430() && (omap_rev() <= OMAP3430_REV_ES2_1)) {
800 dev_dbg(dev, "OMAP3 ES version <= ES2.1\n");
801 if (is_ehci_phy_mode(pdata->port_mode[0]) ||
802 is_ehci_phy_mode(pdata->port_mode[1]) ||
803 is_ehci_phy_mode(pdata->port_mode[2]))
804 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
805 else
806 reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
807 } else {
808 dev_dbg(dev, "OMAP3 ES version > ES2.1\n");
809 if (is_ehci_phy_mode(pdata->port_mode[0]))
810 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
811 else
812 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
813 if (is_ehci_phy_mode(pdata->port_mode[1]))
814 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
815 else
816 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
817 if (is_ehci_phy_mode(pdata->port_mode[2]))
818 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
819 else
820 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
821 }
822 } else if (is_omap_usbhs_rev2(omap)) {
823 /* Clear port mode fields for PHY mode*/
824 reg &= ~OMAP4_P1_MODE_CLEAR;
825 reg &= ~OMAP4_P2_MODE_CLEAR;
826
827 if (is_ehci_phy_mode(pdata->port_mode[0])) {
828 ret = clk_set_parent(omap->utmi_p1_fck,
829 omap->xclk60mhsp1_ck);
830 if (ret != 0) {
831 dev_err(dev, "xclk60mhsp1_ck set parent"
832 "failed error:%d\n", ret);
833 goto err_tll;
834 }
835 } else if (is_ehci_tll_mode(pdata->port_mode[0])) {
836 ret = clk_set_parent(omap->utmi_p1_fck,
837 omap->init_60m_fclk);
838 if (ret != 0) {
839 dev_err(dev, "init_60m_fclk set parent"
840 "failed error:%d\n", ret);
841 goto err_tll;
842 }
843 clk_enable(omap->usbhost_p1_fck);
844 clk_enable(omap->usbtll_p1_fck);
845 }
846
847 if (is_ehci_phy_mode(pdata->port_mode[1])) {
848 ret = clk_set_parent(omap->utmi_p2_fck,
849 omap->xclk60mhsp2_ck);
850 if (ret != 0) {
851 dev_err(dev, "xclk60mhsp1_ck set parent"
852 "failed error:%d\n", ret);
853 goto err_tll;
854 }
855 } else if (is_ehci_tll_mode(pdata->port_mode[1])) {
856 ret = clk_set_parent(omap->utmi_p2_fck,
857 omap->init_60m_fclk);
858 if (ret != 0) {
859 dev_err(dev, "init_60m_fclk set parent"
860 "failed error:%d\n", ret);
861 goto err_tll;
862 }
863 clk_enable(omap->usbhost_p2_fck);
864 clk_enable(omap->usbtll_p2_fck);
865 }
866
867 clk_enable(omap->utmi_p1_fck);
868 clk_enable(omap->utmi_p2_fck);
869
870 if (is_ehci_tll_mode(pdata->port_mode[0]) ||
871 (is_ohci_port(pdata->port_mode[0])))
872 reg |= OMAP4_P1_MODE_TLL;
873 else if (is_ehci_hsic_mode(pdata->port_mode[0]))
874 reg |= OMAP4_P1_MODE_HSIC;
875
876 if (is_ehci_tll_mode(pdata->port_mode[1]) ||
877 (is_ohci_port(pdata->port_mode[1])))
878 reg |= OMAP4_P2_MODE_TLL;
879 else if (is_ehci_hsic_mode(pdata->port_mode[1]))
880 reg |= OMAP4_P2_MODE_HSIC;
881 }
882
883 usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg);
884 dev_dbg(dev, "UHH setup done, uhh_hostconfig=%x\n", reg);
885
886 if (is_ehci_tll_mode(pdata->port_mode[0]) ||
887 is_ehci_tll_mode(pdata->port_mode[1]) ||
888 is_ehci_tll_mode(pdata->port_mode[2]) ||
889 (is_ohci_port(pdata->port_mode[0])) ||
890 (is_ohci_port(pdata->port_mode[1])) ||
891 (is_ohci_port(pdata->port_mode[2]))) {
892
893 /* Enable UTMI mode for required TLL channels */
894 if (is_omap_usbhs_rev2(omap))
895 usbhs_omap_tll_init(dev, OMAP_REV2_TLL_CHANNEL_COUNT);
896 else
897 usbhs_omap_tll_init(dev, OMAP_TLL_CHANNEL_COUNT);
898 }
899
900 if (pdata->ehci_data->phy_reset) {
901 /* Hold the PHY in RESET for enough time till
902 * PHY is settled and ready
903 */
904 udelay(10);
905
906 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0]))
907 gpio_set_value
557f447f 908 (pdata->ehci_data->reset_gpio_port[0], 1);
17cdd29d
KM		 909
910 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1]))
911 gpio_set_value
557f447f 912 (pdata->ehci_data->reset_gpio_port[1], 1);
17cdd29d
KM		 913 }
914
915end_count:
916 omap->count++;
d11536e4
AL		 917 spin_unlock_irqrestore(&omap->lock, flags);
918 return 0;
17cdd29d
KM		 919
920err_tll:
921 if (pdata->ehci_data->phy_reset) {
922 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0]))
923 gpio_free(pdata->ehci_data->reset_gpio_port[0]);
924
925 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1]))
926 gpio_free(pdata->ehci_data->reset_gpio_port[1]);
927 }
8f2df014
KM		 928
929 clk_disable(omap->usbtll_ick);
930 clk_disable(omap->usbtll_fck);
931 clk_disable(omap->usbhost_fs_fck);
932 clk_disable(omap->usbhost_hs_fck);
933 clk_disable(omap->usbhost_ick);
934 spin_unlock_irqrestore(&omap->lock, flags);
17cdd29d
KM		 935 return ret;
936}
937
938static void usbhs_disable(struct device *dev)
939{
940 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
941 struct usbhs_omap_platform_data *pdata = &omap->platdata;
942 unsigned long flags = 0;
943 unsigned long timeout;
944
945 dev_dbg(dev, "stopping TI HSUSB Controller\n");
946
947 spin_lock_irqsave(&omap->lock, flags);
948
949 if (omap->count == 0)
950 goto end_disble;
951
952 omap->count--;
953
954 if (omap->count != 0)
955 goto end_disble;
956
957 /* Reset OMAP modules for insmod/rmmod to work */
958 usbhs_write(omap->uhh_base, OMAP_UHH_SYSCONFIG,
959 is_omap_usbhs_rev2(omap) ?
960 OMAP4_UHH_SYSCONFIG_SOFTRESET :
961 OMAP_UHH_SYSCONFIG_SOFTRESET);
962
963 timeout = jiffies + msecs_to_jiffies(100);
964 while (!(usbhs_read(omap->uhh_base, OMAP_UHH_SYSSTATUS)
965 & (1 << 0))) {
966 cpu_relax();
967
968 if (time_after(jiffies, timeout))
969 dev_dbg(dev, "operation timed out\n");
970 }
971
972 while (!(usbhs_read(omap->uhh_base, OMAP_UHH_SYSSTATUS)
973 & (1 << 1))) {
974 cpu_relax();
975
976 if (time_after(jiffies, timeout))
977 dev_dbg(dev, "operation timed out\n");
978 }
979
980 while (!(usbhs_read(omap->uhh_base, OMAP_UHH_SYSSTATUS)
981 & (1 << 2))) {
982 cpu_relax();
983
984 if (time_after(jiffies, timeout))
985 dev_dbg(dev, "operation timed out\n");
986 }
987
988 usbhs_write(omap->tll_base, OMAP_USBTLL_SYSCONFIG, (1 << 1));
989
990 while (!(usbhs_read(omap->tll_base, OMAP_USBTLL_SYSSTATUS)
991 & (1 << 0))) {
992 cpu_relax();
993
994 if (time_after(jiffies, timeout))
995 dev_dbg(dev, "operation timed out\n");
996 }
997
6eb6fbbf
KM		 998 if (is_omap_usbhs_rev2(omap)) {
999 if (is_ehci_tll_mode(pdata->port_mode[0]))
e2e49d57 1000 clk_disable(omap->usbtll_p1_fck);
6eb6fbbf 1001 if (is_ehci_tll_mode(pdata->port_mode[1]))
e2e49d57 1002 clk_disable(omap->usbtll_p2_fck);
6eb6fbbf
KM		 1003 clk_disable(omap->utmi_p2_fck);
1004 clk_disable(omap->utmi_p1_fck);
17cdd29d
KM		 1005 }
1006
8f2df014
KM		 1007 clk_disable(omap->usbtll_ick);
1008 clk_disable(omap->usbtll_fck);
1009 clk_disable(omap->usbhost_fs_fck);
1010 clk_disable(omap->usbhost_hs_fck);
1011 clk_disable(omap->usbhost_ick);
17cdd29d 1012
6eb6fbbf
KM		 1013 /* The gpio_free migh sleep; so unlock the spinlock */
1014 spin_unlock_irqrestore(&omap->lock, flags);
1015
1016 if (pdata->ehci_data->phy_reset) {
1017 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0]))
1018 gpio_free(pdata->ehci_data->reset_gpio_port[0]);
1019
1020 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1]))
1021 gpio_free(pdata->ehci_data->reset_gpio_port[1]);
1022 }
1023 return;
1024
17cdd29d
KM		 1025end_disble:
1026 spin_unlock_irqrestore(&omap->lock, flags);
1027}
1028
1029int omap_usbhs_enable(struct device *dev)
1030{
1031 return usbhs_enable(dev->parent);
1032}
1033EXPORT_SYMBOL_GPL(omap_usbhs_enable);
1034
1035void omap_usbhs_disable(struct device *dev)
1036{
1037 usbhs_disable(dev->parent);
1038}
1039EXPORT_SYMBOL_GPL(omap_usbhs_disable);
1040
1041static struct platform_driver usbhs_omap_driver = {
1042 .driver = {
1043 .name = (char *)usbhs_driver_name,
1044 .owner = THIS_MODULE,
1045 },
1046 .remove = __exit_p(usbhs_omap_remove),
1047};
1048
1049MODULE_AUTHOR("Keshava Munegowda <keshava_mgowda@ti.com>");
1050MODULE_ALIAS("platform:" USBHS_DRIVER_NAME);
1051MODULE_LICENSE("GPL v2");
1052MODULE_DESCRIPTION("usb host common core driver for omap EHCI and OHCI");
1053
1054static int __init omap_usbhs_drvinit(void)
1055{
1056 return platform_driver_probe(&usbhs_omap_driver, usbhs_omap_probe);
1057}
1058
1059/*
1060 * init before ehci and ohci drivers;
1061 * The usbhs core driver should be initialized much before
1062 * the omap ehci and ohci probe functions are called.
1063 */
1064fs_initcall(omap_usbhs_drvinit);
1065
1066static void __exit omap_usbhs_drvexit(void)
1067{
1068 platform_driver_unregister(&usbhs_omap_driver);
1069}
1070module_exit(omap_usbhs_drvexit);
kernel source for telekom puls (alcatel/mediatek)