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e3726fcf | 1 | /* |
e0befb23 MP |
2 | * Copyright (C) STMicroelectronics 2009 |
3 | * Copyright (C) ST-Ericsson SA 2010 | |
e3726fcf LW |
4 | * |
5 | * License Terms: GNU General Public License v2 | |
e0befb23 MP |
6 | * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> |
7 | * Author: Sundar Iyer <sundar.iyer@stericsson.com> | |
e3726fcf LW |
8 | * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> |
9 | * | |
e0befb23 MP |
10 | * U8500 PRCM Unit interface driver |
11 | * | |
e3726fcf | 12 | */ |
e3726fcf | 13 | #include <linux/module.h> |
3df57bcf MN |
14 | #include <linux/kernel.h> |
15 | #include <linux/delay.h> | |
e3726fcf LW |
16 | #include <linux/errno.h> |
17 | #include <linux/err.h> | |
3df57bcf | 18 | #include <linux/spinlock.h> |
e3726fcf | 19 | #include <linux/io.h> |
3df57bcf | 20 | #include <linux/slab.h> |
e3726fcf LW |
21 | #include <linux/mutex.h> |
22 | #include <linux/completion.h> | |
3df57bcf | 23 | #include <linux/irq.h> |
e3726fcf LW |
24 | #include <linux/jiffies.h> |
25 | #include <linux/bitops.h> | |
3df57bcf MN |
26 | #include <linux/fs.h> |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/uaccess.h> | |
29 | #include <linux/mfd/core.h> | |
73180f85 | 30 | #include <linux/mfd/dbx500-prcmu.h> |
1032fbfd BJ |
31 | #include <linux/regulator/db8500-prcmu.h> |
32 | #include <linux/regulator/machine.h> | |
3df57bcf MN |
33 | #include <mach/hardware.h> |
34 | #include <mach/irqs.h> | |
35 | #include <mach/db8500-regs.h> | |
36 | #include <mach/id.h> | |
73180f85 | 37 | #include "dbx500-prcmu-regs.h" |
3df57bcf MN |
38 | |
39 | /* Offset for the firmware version within the TCPM */ | |
40 | #define PRCMU_FW_VERSION_OFFSET 0xA4 | |
41 | ||
3df57bcf MN |
42 | /* Index of different voltages to be used when accessing AVSData */ |
43 | #define PRCM_AVS_BASE 0x2FC | |
44 | #define PRCM_AVS_VBB_RET (PRCM_AVS_BASE + 0x0) | |
45 | #define PRCM_AVS_VBB_MAX_OPP (PRCM_AVS_BASE + 0x1) | |
46 | #define PRCM_AVS_VBB_100_OPP (PRCM_AVS_BASE + 0x2) | |
47 | #define PRCM_AVS_VBB_50_OPP (PRCM_AVS_BASE + 0x3) | |
48 | #define PRCM_AVS_VARM_MAX_OPP (PRCM_AVS_BASE + 0x4) | |
49 | #define PRCM_AVS_VARM_100_OPP (PRCM_AVS_BASE + 0x5) | |
50 | #define PRCM_AVS_VARM_50_OPP (PRCM_AVS_BASE + 0x6) | |
51 | #define PRCM_AVS_VARM_RET (PRCM_AVS_BASE + 0x7) | |
52 | #define PRCM_AVS_VAPE_100_OPP (PRCM_AVS_BASE + 0x8) | |
53 | #define PRCM_AVS_VAPE_50_OPP (PRCM_AVS_BASE + 0x9) | |
54 | #define PRCM_AVS_VMOD_100_OPP (PRCM_AVS_BASE + 0xA) | |
55 | #define PRCM_AVS_VMOD_50_OPP (PRCM_AVS_BASE + 0xB) | |
56 | #define PRCM_AVS_VSAFE (PRCM_AVS_BASE + 0xC) | |
57 | ||
58 | #define PRCM_AVS_VOLTAGE 0 | |
59 | #define PRCM_AVS_VOLTAGE_MASK 0x3f | |
60 | #define PRCM_AVS_ISSLOWSTARTUP 6 | |
61 | #define PRCM_AVS_ISSLOWSTARTUP_MASK (1 << PRCM_AVS_ISSLOWSTARTUP) | |
62 | #define PRCM_AVS_ISMODEENABLE 7 | |
63 | #define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE) | |
64 | ||
65 | #define PRCM_BOOT_STATUS 0xFFF | |
66 | #define PRCM_ROMCODE_A2P 0xFFE | |
67 | #define PRCM_ROMCODE_P2A 0xFFD | |
68 | #define PRCM_XP70_CUR_PWR_STATE 0xFFC /* 4 BYTES */ | |
69 | ||
70 | #define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */ | |
71 | ||
72 | #define _PRCM_MBOX_HEADER 0xFE8 /* 16 bytes */ | |
73 | #define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0) | |
74 | #define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1) | |
75 | #define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2) | |
76 | #define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3) | |
77 | #define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4) | |
78 | #define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5) | |
79 | #define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8) | |
80 | ||
81 | /* Req Mailboxes */ | |
82 | #define PRCM_REQ_MB0 0xFDC /* 12 bytes */ | |
83 | #define PRCM_REQ_MB1 0xFD0 /* 12 bytes */ | |
84 | #define PRCM_REQ_MB2 0xFC0 /* 16 bytes */ | |
85 | #define PRCM_REQ_MB3 0xE4C /* 372 bytes */ | |
86 | #define PRCM_REQ_MB4 0xE48 /* 4 bytes */ | |
87 | #define PRCM_REQ_MB5 0xE44 /* 4 bytes */ | |
88 | ||
89 | /* Ack Mailboxes */ | |
90 | #define PRCM_ACK_MB0 0xE08 /* 52 bytes */ | |
91 | #define PRCM_ACK_MB1 0xE04 /* 4 bytes */ | |
92 | #define PRCM_ACK_MB2 0xE00 /* 4 bytes */ | |
93 | #define PRCM_ACK_MB3 0xDFC /* 4 bytes */ | |
94 | #define PRCM_ACK_MB4 0xDF8 /* 4 bytes */ | |
95 | #define PRCM_ACK_MB5 0xDF4 /* 4 bytes */ | |
96 | ||
97 | /* Mailbox 0 headers */ | |
98 | #define MB0H_POWER_STATE_TRANS 0 | |
99 | #define MB0H_CONFIG_WAKEUPS_EXE 1 | |
100 | #define MB0H_READ_WAKEUP_ACK 3 | |
101 | #define MB0H_CONFIG_WAKEUPS_SLEEP 4 | |
102 | ||
103 | #define MB0H_WAKEUP_EXE 2 | |
104 | #define MB0H_WAKEUP_SLEEP 5 | |
105 | ||
106 | /* Mailbox 0 REQs */ | |
107 | #define PRCM_REQ_MB0_AP_POWER_STATE (PRCM_REQ_MB0 + 0x0) | |
108 | #define PRCM_REQ_MB0_AP_PLL_STATE (PRCM_REQ_MB0 + 0x1) | |
109 | #define PRCM_REQ_MB0_ULP_CLOCK_STATE (PRCM_REQ_MB0 + 0x2) | |
110 | #define PRCM_REQ_MB0_DO_NOT_WFI (PRCM_REQ_MB0 + 0x3) | |
111 | #define PRCM_REQ_MB0_WAKEUP_8500 (PRCM_REQ_MB0 + 0x4) | |
112 | #define PRCM_REQ_MB0_WAKEUP_4500 (PRCM_REQ_MB0 + 0x8) | |
113 | ||
114 | /* Mailbox 0 ACKs */ | |
115 | #define PRCM_ACK_MB0_AP_PWRSTTR_STATUS (PRCM_ACK_MB0 + 0x0) | |
116 | #define PRCM_ACK_MB0_READ_POINTER (PRCM_ACK_MB0 + 0x1) | |
117 | #define PRCM_ACK_MB0_WAKEUP_0_8500 (PRCM_ACK_MB0 + 0x4) | |
118 | #define PRCM_ACK_MB0_WAKEUP_0_4500 (PRCM_ACK_MB0 + 0x8) | |
119 | #define PRCM_ACK_MB0_WAKEUP_1_8500 (PRCM_ACK_MB0 + 0x1C) | |
120 | #define PRCM_ACK_MB0_WAKEUP_1_4500 (PRCM_ACK_MB0 + 0x20) | |
121 | #define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20 | |
122 | ||
123 | /* Mailbox 1 headers */ | |
124 | #define MB1H_ARM_APE_OPP 0x0 | |
125 | #define MB1H_RESET_MODEM 0x2 | |
126 | #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3 | |
127 | #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4 | |
128 | #define MB1H_RELEASE_USB_WAKEUP 0x5 | |
a592c2e2 | 129 | #define MB1H_PLL_ON_OFF 0x6 |
3df57bcf MN |
130 | |
131 | /* Mailbox 1 Requests */ | |
132 | #define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0) | |
133 | #define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1) | |
a592c2e2 | 134 | #define PRCM_REQ_MB1_PLL_ON_OFF (PRCM_REQ_MB1 + 0x4) |
6b6fae2b MN |
135 | #define PLL_SOC0_OFF 0x1 |
136 | #define PLL_SOC0_ON 0x2 | |
a592c2e2 MN |
137 | #define PLL_SOC1_OFF 0x4 |
138 | #define PLL_SOC1_ON 0x8 | |
3df57bcf MN |
139 | |
140 | /* Mailbox 1 ACKs */ | |
141 | #define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0) | |
142 | #define PRCM_ACK_MB1_CURRENT_APE_OPP (PRCM_ACK_MB1 + 0x1) | |
143 | #define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2) | |
144 | #define PRCM_ACK_MB1_DVFS_STATUS (PRCM_ACK_MB1 + 0x3) | |
145 | ||
146 | /* Mailbox 2 headers */ | |
147 | #define MB2H_DPS 0x0 | |
148 | #define MB2H_AUTO_PWR 0x1 | |
149 | ||
150 | /* Mailbox 2 REQs */ | |
151 | #define PRCM_REQ_MB2_SVA_MMDSP (PRCM_REQ_MB2 + 0x0) | |
152 | #define PRCM_REQ_MB2_SVA_PIPE (PRCM_REQ_MB2 + 0x1) | |
153 | #define PRCM_REQ_MB2_SIA_MMDSP (PRCM_REQ_MB2 + 0x2) | |
154 | #define PRCM_REQ_MB2_SIA_PIPE (PRCM_REQ_MB2 + 0x3) | |
155 | #define PRCM_REQ_MB2_SGA (PRCM_REQ_MB2 + 0x4) | |
156 | #define PRCM_REQ_MB2_B2R2_MCDE (PRCM_REQ_MB2 + 0x5) | |
157 | #define PRCM_REQ_MB2_ESRAM12 (PRCM_REQ_MB2 + 0x6) | |
158 | #define PRCM_REQ_MB2_ESRAM34 (PRCM_REQ_MB2 + 0x7) | |
159 | #define PRCM_REQ_MB2_AUTO_PM_SLEEP (PRCM_REQ_MB2 + 0x8) | |
160 | #define PRCM_REQ_MB2_AUTO_PM_IDLE (PRCM_REQ_MB2 + 0xC) | |
161 | ||
162 | /* Mailbox 2 ACKs */ | |
163 | #define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0) | |
164 | #define HWACC_PWR_ST_OK 0xFE | |
165 | ||
166 | /* Mailbox 3 headers */ | |
167 | #define MB3H_ANC 0x0 | |
168 | #define MB3H_SIDETONE 0x1 | |
169 | #define MB3H_SYSCLK 0xE | |
170 | ||
171 | /* Mailbox 3 Requests */ | |
172 | #define PRCM_REQ_MB3_ANC_FIR_COEFF (PRCM_REQ_MB3 + 0x0) | |
173 | #define PRCM_REQ_MB3_ANC_IIR_COEFF (PRCM_REQ_MB3 + 0x20) | |
174 | #define PRCM_REQ_MB3_ANC_SHIFTER (PRCM_REQ_MB3 + 0x60) | |
175 | #define PRCM_REQ_MB3_ANC_WARP (PRCM_REQ_MB3 + 0x64) | |
176 | #define PRCM_REQ_MB3_SIDETONE_FIR_GAIN (PRCM_REQ_MB3 + 0x68) | |
177 | #define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C) | |
178 | #define PRCM_REQ_MB3_SYSCLK_MGT (PRCM_REQ_MB3 + 0x16C) | |
179 | ||
180 | /* Mailbox 4 headers */ | |
181 | #define MB4H_DDR_INIT 0x0 | |
182 | #define MB4H_MEM_ST 0x1 | |
183 | #define MB4H_HOTDOG 0x12 | |
184 | #define MB4H_HOTMON 0x13 | |
185 | #define MB4H_HOT_PERIOD 0x14 | |
a592c2e2 MN |
186 | #define MB4H_A9WDOG_CONF 0x16 |
187 | #define MB4H_A9WDOG_EN 0x17 | |
188 | #define MB4H_A9WDOG_DIS 0x18 | |
189 | #define MB4H_A9WDOG_LOAD 0x19 | |
190 | #define MB4H_A9WDOG_KICK 0x20 | |
3df57bcf MN |
191 | |
192 | /* Mailbox 4 Requests */ | |
193 | #define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE (PRCM_REQ_MB4 + 0x0) | |
194 | #define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE (PRCM_REQ_MB4 + 0x1) | |
195 | #define PRCM_REQ_MB4_ESRAM0_ST (PRCM_REQ_MB4 + 0x3) | |
196 | #define PRCM_REQ_MB4_HOTDOG_THRESHOLD (PRCM_REQ_MB4 + 0x0) | |
197 | #define PRCM_REQ_MB4_HOTMON_LOW (PRCM_REQ_MB4 + 0x0) | |
198 | #define PRCM_REQ_MB4_HOTMON_HIGH (PRCM_REQ_MB4 + 0x1) | |
199 | #define PRCM_REQ_MB4_HOTMON_CONFIG (PRCM_REQ_MB4 + 0x2) | |
200 | #define PRCM_REQ_MB4_HOT_PERIOD (PRCM_REQ_MB4 + 0x0) | |
201 | #define HOTMON_CONFIG_LOW BIT(0) | |
202 | #define HOTMON_CONFIG_HIGH BIT(1) | |
a592c2e2 MN |
203 | #define PRCM_REQ_MB4_A9WDOG_0 (PRCM_REQ_MB4 + 0x0) |
204 | #define PRCM_REQ_MB4_A9WDOG_1 (PRCM_REQ_MB4 + 0x1) | |
205 | #define PRCM_REQ_MB4_A9WDOG_2 (PRCM_REQ_MB4 + 0x2) | |
206 | #define PRCM_REQ_MB4_A9WDOG_3 (PRCM_REQ_MB4 + 0x3) | |
207 | #define A9WDOG_AUTO_OFF_EN BIT(7) | |
208 | #define A9WDOG_AUTO_OFF_DIS 0 | |
209 | #define A9WDOG_ID_MASK 0xf | |
3df57bcf MN |
210 | |
211 | /* Mailbox 5 Requests */ | |
212 | #define PRCM_REQ_MB5_I2C_SLAVE_OP (PRCM_REQ_MB5 + 0x0) | |
213 | #define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1) | |
214 | #define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2) | |
215 | #define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3) | |
216 | #define PRCMU_I2C_WRITE(slave) \ | |
217 | (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0)) | |
218 | #define PRCMU_I2C_READ(slave) \ | |
219 | (((slave) << 1) | BIT(0) | (cpu_is_u8500v2() ? BIT(6) : 0)) | |
220 | #define PRCMU_I2C_STOP_EN BIT(3) | |
221 | ||
222 | /* Mailbox 5 ACKs */ | |
223 | #define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1) | |
224 | #define PRCM_ACK_MB5_I2C_VAL (PRCM_ACK_MB5 + 0x3) | |
225 | #define I2C_WR_OK 0x1 | |
226 | #define I2C_RD_OK 0x2 | |
227 | ||
228 | #define NUM_MB 8 | |
229 | #define MBOX_BIT BIT | |
230 | #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1) | |
231 | ||
232 | /* | |
233 | * Wakeups/IRQs | |
234 | */ | |
235 | ||
236 | #define WAKEUP_BIT_RTC BIT(0) | |
237 | #define WAKEUP_BIT_RTT0 BIT(1) | |
238 | #define WAKEUP_BIT_RTT1 BIT(2) | |
239 | #define WAKEUP_BIT_HSI0 BIT(3) | |
240 | #define WAKEUP_BIT_HSI1 BIT(4) | |
241 | #define WAKEUP_BIT_CA_WAKE BIT(5) | |
242 | #define WAKEUP_BIT_USB BIT(6) | |
243 | #define WAKEUP_BIT_ABB BIT(7) | |
244 | #define WAKEUP_BIT_ABB_FIFO BIT(8) | |
245 | #define WAKEUP_BIT_SYSCLK_OK BIT(9) | |
246 | #define WAKEUP_BIT_CA_SLEEP BIT(10) | |
247 | #define WAKEUP_BIT_AC_WAKE_ACK BIT(11) | |
248 | #define WAKEUP_BIT_SIDE_TONE_OK BIT(12) | |
249 | #define WAKEUP_BIT_ANC_OK BIT(13) | |
250 | #define WAKEUP_BIT_SW_ERROR BIT(14) | |
251 | #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15) | |
252 | #define WAKEUP_BIT_ARM BIT(17) | |
253 | #define WAKEUP_BIT_HOTMON_LOW BIT(18) | |
254 | #define WAKEUP_BIT_HOTMON_HIGH BIT(19) | |
255 | #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20) | |
256 | #define WAKEUP_BIT_GPIO0 BIT(23) | |
257 | #define WAKEUP_BIT_GPIO1 BIT(24) | |
258 | #define WAKEUP_BIT_GPIO2 BIT(25) | |
259 | #define WAKEUP_BIT_GPIO3 BIT(26) | |
260 | #define WAKEUP_BIT_GPIO4 BIT(27) | |
261 | #define WAKEUP_BIT_GPIO5 BIT(28) | |
262 | #define WAKEUP_BIT_GPIO6 BIT(29) | |
263 | #define WAKEUP_BIT_GPIO7 BIT(30) | |
264 | #define WAKEUP_BIT_GPIO8 BIT(31) | |
265 | ||
b58d12fe MN |
266 | static struct { |
267 | bool valid; | |
268 | struct prcmu_fw_version version; | |
269 | } fw_info; | |
270 | ||
3df57bcf MN |
271 | /* |
272 | * This vector maps irq numbers to the bits in the bit field used in | |
273 | * communication with the PRCMU firmware. | |
274 | * | |
275 | * The reason for having this is to keep the irq numbers contiguous even though | |
276 | * the bits in the bit field are not. (The bits also have a tendency to move | |
277 | * around, to further complicate matters.) | |
278 | */ | |
279 | #define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name) - IRQ_PRCMU_BASE) | |
280 | #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name) | |
281 | static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = { | |
282 | IRQ_ENTRY(RTC), | |
283 | IRQ_ENTRY(RTT0), | |
284 | IRQ_ENTRY(RTT1), | |
285 | IRQ_ENTRY(HSI0), | |
286 | IRQ_ENTRY(HSI1), | |
287 | IRQ_ENTRY(CA_WAKE), | |
288 | IRQ_ENTRY(USB), | |
289 | IRQ_ENTRY(ABB), | |
290 | IRQ_ENTRY(ABB_FIFO), | |
291 | IRQ_ENTRY(CA_SLEEP), | |
292 | IRQ_ENTRY(ARM), | |
293 | IRQ_ENTRY(HOTMON_LOW), | |
294 | IRQ_ENTRY(HOTMON_HIGH), | |
295 | IRQ_ENTRY(MODEM_SW_RESET_REQ), | |
296 | IRQ_ENTRY(GPIO0), | |
297 | IRQ_ENTRY(GPIO1), | |
298 | IRQ_ENTRY(GPIO2), | |
299 | IRQ_ENTRY(GPIO3), | |
300 | IRQ_ENTRY(GPIO4), | |
301 | IRQ_ENTRY(GPIO5), | |
302 | IRQ_ENTRY(GPIO6), | |
303 | IRQ_ENTRY(GPIO7), | |
304 | IRQ_ENTRY(GPIO8) | |
305 | }; | |
306 | ||
307 | #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1) | |
308 | #define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name) | |
309 | static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = { | |
310 | WAKEUP_ENTRY(RTC), | |
311 | WAKEUP_ENTRY(RTT0), | |
312 | WAKEUP_ENTRY(RTT1), | |
313 | WAKEUP_ENTRY(HSI0), | |
314 | WAKEUP_ENTRY(HSI1), | |
315 | WAKEUP_ENTRY(USB), | |
316 | WAKEUP_ENTRY(ABB), | |
317 | WAKEUP_ENTRY(ABB_FIFO), | |
318 | WAKEUP_ENTRY(ARM) | |
319 | }; | |
320 | ||
321 | /* | |
322 | * mb0_transfer - state needed for mailbox 0 communication. | |
323 | * @lock: The transaction lock. | |
324 | * @dbb_events_lock: A lock used to handle concurrent access to (parts of) | |
325 | * the request data. | |
326 | * @mask_work: Work structure used for (un)masking wakeup interrupts. | |
327 | * @req: Request data that need to persist between requests. | |
328 | */ | |
329 | static struct { | |
330 | spinlock_t lock; | |
331 | spinlock_t dbb_irqs_lock; | |
332 | struct work_struct mask_work; | |
333 | struct mutex ac_wake_lock; | |
334 | struct completion ac_wake_work; | |
335 | struct { | |
336 | u32 dbb_irqs; | |
337 | u32 dbb_wakeups; | |
338 | u32 abb_events; | |
339 | } req; | |
340 | } mb0_transfer; | |
341 | ||
342 | /* | |
343 | * mb1_transfer - state needed for mailbox 1 communication. | |
344 | * @lock: The transaction lock. | |
345 | * @work: The transaction completion structure. | |
4d64d2e3 | 346 | * @ape_opp: The current APE OPP. |
3df57bcf MN |
347 | * @ack: Reply ("acknowledge") data. |
348 | */ | |
349 | static struct { | |
350 | struct mutex lock; | |
351 | struct completion work; | |
4d64d2e3 | 352 | u8 ape_opp; |
3df57bcf MN |
353 | struct { |
354 | u8 header; | |
355 | u8 arm_opp; | |
356 | u8 ape_opp; | |
357 | u8 ape_voltage_status; | |
358 | } ack; | |
359 | } mb1_transfer; | |
360 | ||
361 | /* | |
362 | * mb2_transfer - state needed for mailbox 2 communication. | |
363 | * @lock: The transaction lock. | |
364 | * @work: The transaction completion structure. | |
365 | * @auto_pm_lock: The autonomous power management configuration lock. | |
366 | * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled. | |
367 | * @req: Request data that need to persist between requests. | |
368 | * @ack: Reply ("acknowledge") data. | |
369 | */ | |
370 | static struct { | |
371 | struct mutex lock; | |
372 | struct completion work; | |
373 | spinlock_t auto_pm_lock; | |
374 | bool auto_pm_enabled; | |
375 | struct { | |
376 | u8 status; | |
377 | } ack; | |
378 | } mb2_transfer; | |
379 | ||
380 | /* | |
381 | * mb3_transfer - state needed for mailbox 3 communication. | |
382 | * @lock: The request lock. | |
383 | * @sysclk_lock: A lock used to handle concurrent sysclk requests. | |
384 | * @sysclk_work: Work structure used for sysclk requests. | |
385 | */ | |
386 | static struct { | |
387 | spinlock_t lock; | |
388 | struct mutex sysclk_lock; | |
389 | struct completion sysclk_work; | |
390 | } mb3_transfer; | |
391 | ||
392 | /* | |
393 | * mb4_transfer - state needed for mailbox 4 communication. | |
394 | * @lock: The transaction lock. | |
395 | * @work: The transaction completion structure. | |
396 | */ | |
397 | static struct { | |
398 | struct mutex lock; | |
399 | struct completion work; | |
400 | } mb4_transfer; | |
401 | ||
402 | /* | |
403 | * mb5_transfer - state needed for mailbox 5 communication. | |
404 | * @lock: The transaction lock. | |
405 | * @work: The transaction completion structure. | |
406 | * @ack: Reply ("acknowledge") data. | |
407 | */ | |
408 | static struct { | |
409 | struct mutex lock; | |
410 | struct completion work; | |
411 | struct { | |
412 | u8 status; | |
413 | u8 value; | |
414 | } ack; | |
415 | } mb5_transfer; | |
416 | ||
417 | static atomic_t ac_wake_req_state = ATOMIC_INIT(0); | |
418 | ||
419 | /* Spinlocks */ | |
420 | static DEFINE_SPINLOCK(clkout_lock); | |
421 | static DEFINE_SPINLOCK(gpiocr_lock); | |
422 | ||
423 | /* Global var to runtime determine TCDM base for v2 or v1 */ | |
424 | static __iomem void *tcdm_base; | |
425 | ||
426 | struct clk_mgt { | |
6b6fae2b | 427 | void __iomem *reg; |
3df57bcf | 428 | u32 pllsw; |
6b6fae2b MN |
429 | int branch; |
430 | bool clk38div; | |
431 | }; | |
432 | ||
433 | enum { | |
434 | PLL_RAW, | |
435 | PLL_FIX, | |
436 | PLL_DIV | |
3df57bcf MN |
437 | }; |
438 | ||
439 | static DEFINE_SPINLOCK(clk_mgt_lock); | |
440 | ||
6b6fae2b MN |
441 | #define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \ |
442 | { (PRCM_##_name##_MGT), 0 , _branch, _clk38div} | |
3df57bcf | 443 | struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = { |
6b6fae2b MN |
444 | CLK_MGT_ENTRY(SGACLK, PLL_DIV, false), |
445 | CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true), | |
446 | CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true), | |
447 | CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true), | |
448 | CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true), | |
449 | CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true), | |
450 | CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true), | |
451 | CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true), | |
452 | CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true), | |
453 | CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true), | |
454 | CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true), | |
455 | CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true), | |
456 | CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true), | |
457 | CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true), | |
458 | CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true), | |
459 | CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true), | |
460 | CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true), | |
461 | CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false), | |
462 | CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true), | |
463 | CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true), | |
464 | CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true), | |
465 | CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true), | |
466 | CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false), | |
467 | CLK_MGT_ENTRY(DMACLK, PLL_DIV, true), | |
468 | CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true), | |
469 | CLK_MGT_ENTRY(TVCLK, PLL_FIX, true), | |
470 | CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true), | |
471 | CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true), | |
472 | CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false), | |
473 | }; | |
474 | ||
475 | struct dsiclk { | |
476 | u32 divsel_mask; | |
477 | u32 divsel_shift; | |
478 | u32 divsel; | |
479 | }; | |
480 | ||
481 | static struct dsiclk dsiclk[2] = { | |
482 | { | |
483 | .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK, | |
484 | .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT, | |
485 | .divsel = PRCM_DSI_PLLOUT_SEL_PHI, | |
486 | }, | |
487 | { | |
488 | .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK, | |
489 | .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT, | |
490 | .divsel = PRCM_DSI_PLLOUT_SEL_PHI, | |
491 | } | |
492 | }; | |
493 | ||
494 | struct dsiescclk { | |
495 | u32 en; | |
496 | u32 div_mask; | |
497 | u32 div_shift; | |
498 | }; | |
499 | ||
500 | static struct dsiescclk dsiescclk[3] = { | |
501 | { | |
502 | .en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN, | |
503 | .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK, | |
504 | .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT, | |
505 | }, | |
506 | { | |
507 | .en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN, | |
508 | .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK, | |
509 | .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT, | |
510 | }, | |
511 | { | |
512 | .en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN, | |
513 | .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK, | |
514 | .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT, | |
515 | } | |
3df57bcf MN |
516 | }; |
517 | ||
0837bb72 MN |
518 | static struct regulator *hwacc_regulator[NUM_HW_ACC]; |
519 | static struct regulator *hwacc_ret_regulator[NUM_HW_ACC]; | |
520 | ||
521 | static bool hwacc_enabled[NUM_HW_ACC]; | |
522 | static bool hwacc_ret_enabled[NUM_HW_ACC]; | |
523 | ||
524 | static const char *hwacc_regulator_name[NUM_HW_ACC] = { | |
525 | [HW_ACC_SVAMMDSP] = "hwacc-sva-mmdsp", | |
526 | [HW_ACC_SVAPIPE] = "hwacc-sva-pipe", | |
527 | [HW_ACC_SIAMMDSP] = "hwacc-sia-mmdsp", | |
528 | [HW_ACC_SIAPIPE] = "hwacc-sia-pipe", | |
529 | [HW_ACC_SGA] = "hwacc-sga", | |
530 | [HW_ACC_B2R2] = "hwacc-b2r2", | |
531 | [HW_ACC_MCDE] = "hwacc-mcde", | |
532 | [HW_ACC_ESRAM1] = "hwacc-esram1", | |
533 | [HW_ACC_ESRAM2] = "hwacc-esram2", | |
534 | [HW_ACC_ESRAM3] = "hwacc-esram3", | |
535 | [HW_ACC_ESRAM4] = "hwacc-esram4", | |
536 | }; | |
537 | ||
538 | static const char *hwacc_ret_regulator_name[NUM_HW_ACC] = { | |
539 | [HW_ACC_SVAMMDSP] = "hwacc-sva-mmdsp-ret", | |
540 | [HW_ACC_SIAMMDSP] = "hwacc-sia-mmdsp-ret", | |
541 | [HW_ACC_ESRAM1] = "hwacc-esram1-ret", | |
542 | [HW_ACC_ESRAM2] = "hwacc-esram2-ret", | |
543 | [HW_ACC_ESRAM3] = "hwacc-esram3-ret", | |
544 | [HW_ACC_ESRAM4] = "hwacc-esram4-ret", | |
545 | }; | |
546 | ||
3df57bcf MN |
547 | /* |
548 | * Used by MCDE to setup all necessary PRCMU registers | |
549 | */ | |
550 | #define PRCMU_RESET_DSIPLL 0x00004000 | |
551 | #define PRCMU_UNCLAMP_DSIPLL 0x00400800 | |
552 | ||
553 | #define PRCMU_CLK_PLL_DIV_SHIFT 0 | |
554 | #define PRCMU_CLK_PLL_SW_SHIFT 5 | |
555 | #define PRCMU_CLK_38 (1 << 9) | |
556 | #define PRCMU_CLK_38_SRC (1 << 10) | |
557 | #define PRCMU_CLK_38_DIV (1 << 11) | |
558 | ||
559 | /* PLLDIV=12, PLLSW=4 (PLLDDR) */ | |
560 | #define PRCMU_DSI_CLOCK_SETTING 0x0000008C | |
561 | ||
3df57bcf MN |
562 | /* DPI 50000000 Hz */ |
563 | #define PRCMU_DPI_CLOCK_SETTING ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \ | |
564 | (16 << PRCMU_CLK_PLL_DIV_SHIFT)) | |
565 | #define PRCMU_DSI_LP_CLOCK_SETTING 0x00000E00 | |
566 | ||
567 | /* D=101, N=1, R=4, SELDIV2=0 */ | |
568 | #define PRCMU_PLLDSI_FREQ_SETTING 0x00040165 | |
569 | ||
3df57bcf MN |
570 | #define PRCMU_ENABLE_PLLDSI 0x00000001 |
571 | #define PRCMU_DISABLE_PLLDSI 0x00000000 | |
572 | #define PRCMU_RELEASE_RESET_DSS 0x0000400C | |
573 | #define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000202 | |
574 | /* ESC clk, div0=1, div1=1, div2=3 */ | |
575 | #define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x07030101 | |
576 | #define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00030101 | |
577 | #define PRCMU_DSI_RESET_SW 0x00000007 | |
578 | ||
579 | #define PRCMU_PLLDSI_LOCKP_LOCKED 0x3 | |
580 | ||
73180f85 | 581 | int db8500_prcmu_enable_dsipll(void) |
3df57bcf MN |
582 | { |
583 | int i; | |
3df57bcf MN |
584 | |
585 | /* Clear DSIPLL_RESETN */ | |
c553b3ca | 586 | writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR); |
3df57bcf | 587 | /* Unclamp DSIPLL in/out */ |
c553b3ca | 588 | writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR); |
3df57bcf | 589 | |
3df57bcf | 590 | /* Set DSI PLL FREQ */ |
c72fe851 | 591 | writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ); |
c553b3ca | 592 | writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL); |
3df57bcf | 593 | /* Enable Escape clocks */ |
c553b3ca | 594 | writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); |
3df57bcf MN |
595 | |
596 | /* Start DSI PLL */ | |
c553b3ca | 597 | writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE); |
3df57bcf | 598 | /* Reset DSI PLL */ |
c553b3ca | 599 | writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET); |
3df57bcf | 600 | for (i = 0; i < 10; i++) { |
c553b3ca | 601 | if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED) |
3df57bcf MN |
602 | == PRCMU_PLLDSI_LOCKP_LOCKED) |
603 | break; | |
604 | udelay(100); | |
605 | } | |
606 | /* Set DSIPLL_RESETN */ | |
c553b3ca | 607 | writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET); |
3df57bcf MN |
608 | return 0; |
609 | } | |
610 | ||
73180f85 | 611 | int db8500_prcmu_disable_dsipll(void) |
3df57bcf MN |
612 | { |
613 | /* Disable dsi pll */ | |
c553b3ca | 614 | writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE); |
3df57bcf | 615 | /* Disable escapeclock */ |
c553b3ca | 616 | writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); |
3df57bcf MN |
617 | return 0; |
618 | } | |
619 | ||
73180f85 | 620 | int db8500_prcmu_set_display_clocks(void) |
3df57bcf MN |
621 | { |
622 | unsigned long flags; | |
3df57bcf MN |
623 | |
624 | spin_lock_irqsave(&clk_mgt_lock, flags); | |
625 | ||
626 | /* Grab the HW semaphore. */ | |
c553b3ca | 627 | while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) |
3df57bcf MN |
628 | cpu_relax(); |
629 | ||
c72fe851 | 630 | writel(PRCMU_DSI_CLOCK_SETTING, PRCM_HDMICLK_MGT); |
c553b3ca MN |
631 | writel(PRCMU_DSI_LP_CLOCK_SETTING, PRCM_TVCLK_MGT); |
632 | writel(PRCMU_DPI_CLOCK_SETTING, PRCM_LCDCLK_MGT); | |
3df57bcf MN |
633 | |
634 | /* Release the HW semaphore. */ | |
c553b3ca | 635 | writel(0, PRCM_SEM); |
3df57bcf MN |
636 | |
637 | spin_unlock_irqrestore(&clk_mgt_lock, flags); | |
638 | ||
639 | return 0; | |
640 | } | |
641 | ||
642 | /** | |
643 | * prcmu_enable_spi2 - Enables pin muxing for SPI2 on OtherAlternateC1. | |
644 | */ | |
645 | void prcmu_enable_spi2(void) | |
646 | { | |
647 | u32 reg; | |
648 | unsigned long flags; | |
649 | ||
650 | spin_lock_irqsave(&gpiocr_lock, flags); | |
c553b3ca MN |
651 | reg = readl(PRCM_GPIOCR); |
652 | writel(reg | PRCM_GPIOCR_SPI2_SELECT, PRCM_GPIOCR); | |
3df57bcf MN |
653 | spin_unlock_irqrestore(&gpiocr_lock, flags); |
654 | } | |
655 | ||
656 | /** | |
657 | * prcmu_disable_spi2 - Disables pin muxing for SPI2 on OtherAlternateC1. | |
658 | */ | |
659 | void prcmu_disable_spi2(void) | |
660 | { | |
661 | u32 reg; | |
662 | unsigned long flags; | |
663 | ||
664 | spin_lock_irqsave(&gpiocr_lock, flags); | |
c553b3ca MN |
665 | reg = readl(PRCM_GPIOCR); |
666 | writel(reg & ~PRCM_GPIOCR_SPI2_SELECT, PRCM_GPIOCR); | |
3df57bcf MN |
667 | spin_unlock_irqrestore(&gpiocr_lock, flags); |
668 | } | |
669 | ||
b58d12fe MN |
670 | struct prcmu_fw_version *prcmu_get_fw_version(void) |
671 | { | |
672 | return fw_info.valid ? &fw_info.version : NULL; | |
673 | } | |
674 | ||
3df57bcf MN |
675 | bool prcmu_has_arm_maxopp(void) |
676 | { | |
677 | return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) & | |
678 | PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK; | |
679 | } | |
680 | ||
3df57bcf MN |
681 | /** |
682 | * prcmu_get_boot_status - PRCMU boot status checking | |
683 | * Returns: the current PRCMU boot status | |
684 | */ | |
685 | int prcmu_get_boot_status(void) | |
686 | { | |
687 | return readb(tcdm_base + PRCM_BOOT_STATUS); | |
688 | } | |
689 | ||
690 | /** | |
691 | * prcmu_set_rc_a2p - This function is used to run few power state sequences | |
692 | * @val: Value to be set, i.e. transition requested | |
693 | * Returns: 0 on success, -EINVAL on invalid argument | |
694 | * | |
695 | * This function is used to run the following power state sequences - | |
696 | * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep | |
697 | */ | |
698 | int prcmu_set_rc_a2p(enum romcode_write val) | |
699 | { | |
700 | if (val < RDY_2_DS || val > RDY_2_XP70_RST) | |
701 | return -EINVAL; | |
702 | writeb(val, (tcdm_base + PRCM_ROMCODE_A2P)); | |
703 | return 0; | |
704 | } | |
705 | ||
706 | /** | |
707 | * prcmu_get_rc_p2a - This function is used to get power state sequences | |
708 | * Returns: the power transition that has last happened | |
709 | * | |
710 | * This function can return the following transitions- | |
711 | * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep | |
712 | */ | |
713 | enum romcode_read prcmu_get_rc_p2a(void) | |
714 | { | |
715 | return readb(tcdm_base + PRCM_ROMCODE_P2A); | |
716 | } | |
717 | ||
718 | /** | |
719 | * prcmu_get_current_mode - Return the current XP70 power mode | |
720 | * Returns: Returns the current AP(ARM) power mode: init, | |
721 | * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset | |
722 | */ | |
723 | enum ap_pwrst prcmu_get_xp70_current_state(void) | |
724 | { | |
725 | return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE); | |
726 | } | |
727 | ||
728 | /** | |
729 | * prcmu_config_clkout - Configure one of the programmable clock outputs. | |
730 | * @clkout: The CLKOUT number (0 or 1). | |
731 | * @source: The clock to be used (one of the PRCMU_CLKSRC_*). | |
732 | * @div: The divider to be applied. | |
733 | * | |
734 | * Configures one of the programmable clock outputs (CLKOUTs). | |
735 | * @div should be in the range [1,63] to request a configuration, or 0 to | |
736 | * inform that the configuration is no longer requested. | |
737 | */ | |
738 | int prcmu_config_clkout(u8 clkout, u8 source, u8 div) | |
739 | { | |
740 | static int requests[2]; | |
741 | int r = 0; | |
742 | unsigned long flags; | |
743 | u32 val; | |
744 | u32 bits; | |
745 | u32 mask; | |
746 | u32 div_mask; | |
747 | ||
748 | BUG_ON(clkout > 1); | |
749 | BUG_ON(div > 63); | |
750 | BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009)); | |
751 | ||
752 | if (!div && !requests[clkout]) | |
753 | return -EINVAL; | |
754 | ||
755 | switch (clkout) { | |
756 | case 0: | |
757 | div_mask = PRCM_CLKOCR_CLKODIV0_MASK; | |
758 | mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK); | |
759 | bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) | | |
760 | (div << PRCM_CLKOCR_CLKODIV0_SHIFT)); | |
761 | break; | |
762 | case 1: | |
763 | div_mask = PRCM_CLKOCR_CLKODIV1_MASK; | |
764 | mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK | | |
765 | PRCM_CLKOCR_CLK1TYPE); | |
766 | bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) | | |
767 | (div << PRCM_CLKOCR_CLKODIV1_SHIFT)); | |
768 | break; | |
769 | } | |
770 | bits &= mask; | |
771 | ||
772 | spin_lock_irqsave(&clkout_lock, flags); | |
773 | ||
c553b3ca | 774 | val = readl(PRCM_CLKOCR); |
3df57bcf MN |
775 | if (val & div_mask) { |
776 | if (div) { | |
777 | if ((val & mask) != bits) { | |
778 | r = -EBUSY; | |
779 | goto unlock_and_return; | |
780 | } | |
781 | } else { | |
782 | if ((val & mask & ~div_mask) != bits) { | |
783 | r = -EINVAL; | |
784 | goto unlock_and_return; | |
785 | } | |
786 | } | |
787 | } | |
c553b3ca | 788 | writel((bits | (val & ~mask)), PRCM_CLKOCR); |
3df57bcf MN |
789 | requests[clkout] += (div ? 1 : -1); |
790 | ||
791 | unlock_and_return: | |
792 | spin_unlock_irqrestore(&clkout_lock, flags); | |
793 | ||
794 | return r; | |
795 | } | |
796 | ||
73180f85 | 797 | int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll) |
3df57bcf MN |
798 | { |
799 | unsigned long flags; | |
800 | ||
801 | BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state)); | |
802 | ||
803 | spin_lock_irqsave(&mb0_transfer.lock, flags); | |
804 | ||
c553b3ca | 805 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) |
3df57bcf MN |
806 | cpu_relax(); |
807 | ||
808 | writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); | |
809 | writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE)); | |
810 | writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE)); | |
811 | writeb((keep_ulp_clk ? 1 : 0), | |
812 | (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE)); | |
813 | writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI)); | |
c553b3ca | 814 | writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
815 | |
816 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); | |
817 | ||
818 | return 0; | |
819 | } | |
820 | ||
4d64d2e3 MN |
821 | u8 db8500_prcmu_get_power_state_result(void) |
822 | { | |
823 | return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS); | |
824 | } | |
825 | ||
3df57bcf MN |
826 | /* This function should only be called while mb0_transfer.lock is held. */ |
827 | static void config_wakeups(void) | |
828 | { | |
829 | const u8 header[2] = { | |
830 | MB0H_CONFIG_WAKEUPS_EXE, | |
831 | MB0H_CONFIG_WAKEUPS_SLEEP | |
832 | }; | |
833 | static u32 last_dbb_events; | |
834 | static u32 last_abb_events; | |
835 | u32 dbb_events; | |
836 | u32 abb_events; | |
837 | unsigned int i; | |
838 | ||
839 | dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups; | |
840 | dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK); | |
841 | ||
842 | abb_events = mb0_transfer.req.abb_events; | |
843 | ||
844 | if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events)) | |
845 | return; | |
846 | ||
847 | for (i = 0; i < 2; i++) { | |
c553b3ca | 848 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) |
3df57bcf MN |
849 | cpu_relax(); |
850 | writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500)); | |
851 | writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500)); | |
852 | writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); | |
c553b3ca | 853 | writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
854 | } |
855 | last_dbb_events = dbb_events; | |
856 | last_abb_events = abb_events; | |
857 | } | |
858 | ||
73180f85 | 859 | void db8500_prcmu_enable_wakeups(u32 wakeups) |
3df57bcf MN |
860 | { |
861 | unsigned long flags; | |
862 | u32 bits; | |
863 | int i; | |
864 | ||
865 | BUG_ON(wakeups != (wakeups & VALID_WAKEUPS)); | |
866 | ||
867 | for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) { | |
868 | if (wakeups & BIT(i)) | |
869 | bits |= prcmu_wakeup_bit[i]; | |
870 | } | |
871 | ||
872 | spin_lock_irqsave(&mb0_transfer.lock, flags); | |
873 | ||
874 | mb0_transfer.req.dbb_wakeups = bits; | |
875 | config_wakeups(); | |
876 | ||
877 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); | |
878 | } | |
879 | ||
73180f85 | 880 | void db8500_prcmu_config_abb_event_readout(u32 abb_events) |
3df57bcf MN |
881 | { |
882 | unsigned long flags; | |
883 | ||
884 | spin_lock_irqsave(&mb0_transfer.lock, flags); | |
885 | ||
886 | mb0_transfer.req.abb_events = abb_events; | |
887 | config_wakeups(); | |
888 | ||
889 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); | |
890 | } | |
891 | ||
73180f85 | 892 | void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) |
3df57bcf MN |
893 | { |
894 | if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) | |
895 | *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500); | |
896 | else | |
897 | *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500); | |
898 | } | |
899 | ||
900 | /** | |
73180f85 | 901 | * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP |
3df57bcf MN |
902 | * @opp: The new ARM operating point to which transition is to be made |
903 | * Returns: 0 on success, non-zero on failure | |
904 | * | |
905 | * This function sets the the operating point of the ARM. | |
906 | */ | |
73180f85 | 907 | int db8500_prcmu_set_arm_opp(u8 opp) |
3df57bcf MN |
908 | { |
909 | int r; | |
910 | ||
911 | if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK) | |
912 | return -EINVAL; | |
913 | ||
914 | r = 0; | |
915 | ||
916 | mutex_lock(&mb1_transfer.lock); | |
917 | ||
c553b3ca | 918 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
3df57bcf MN |
919 | cpu_relax(); |
920 | ||
921 | writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); | |
922 | writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); | |
923 | writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP)); | |
924 | ||
c553b3ca | 925 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
926 | wait_for_completion(&mb1_transfer.work); |
927 | ||
928 | if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) || | |
929 | (mb1_transfer.ack.arm_opp != opp)) | |
930 | r = -EIO; | |
931 | ||
932 | mutex_unlock(&mb1_transfer.lock); | |
933 | ||
934 | return r; | |
935 | } | |
936 | ||
937 | /** | |
73180f85 | 938 | * db8500_prcmu_get_arm_opp - get the current ARM OPP |
3df57bcf MN |
939 | * |
940 | * Returns: the current ARM OPP | |
941 | */ | |
73180f85 | 942 | int db8500_prcmu_get_arm_opp(void) |
3df57bcf MN |
943 | { |
944 | return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP); | |
945 | } | |
946 | ||
947 | /** | |
0508901c | 948 | * db8500_prcmu_get_ddr_opp - get the current DDR OPP |
3df57bcf MN |
949 | * |
950 | * Returns: the current DDR OPP | |
951 | */ | |
0508901c | 952 | int db8500_prcmu_get_ddr_opp(void) |
3df57bcf | 953 | { |
c553b3ca | 954 | return readb(PRCM_DDR_SUBSYS_APE_MINBW); |
3df57bcf MN |
955 | } |
956 | ||
957 | /** | |
0508901c | 958 | * db8500_set_ddr_opp - set the appropriate DDR OPP |
3df57bcf MN |
959 | * @opp: The new DDR operating point to which transition is to be made |
960 | * Returns: 0 on success, non-zero on failure | |
961 | * | |
962 | * This function sets the operating point of the DDR. | |
963 | */ | |
0508901c | 964 | int db8500_prcmu_set_ddr_opp(u8 opp) |
3df57bcf MN |
965 | { |
966 | if (opp < DDR_100_OPP || opp > DDR_25_OPP) | |
967 | return -EINVAL; | |
968 | /* Changing the DDR OPP can hang the hardware pre-v21 */ | |
969 | if (cpu_is_u8500v20_or_later() && !cpu_is_u8500v20()) | |
c553b3ca | 970 | writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW); |
3df57bcf MN |
971 | |
972 | return 0; | |
973 | } | |
6b6fae2b | 974 | |
4d64d2e3 MN |
975 | /* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */ |
976 | static void request_even_slower_clocks(bool enable) | |
977 | { | |
978 | void __iomem *clock_reg[] = { | |
979 | PRCM_ACLK_MGT, | |
980 | PRCM_DMACLK_MGT | |
981 | }; | |
982 | unsigned long flags; | |
983 | unsigned int i; | |
984 | ||
985 | spin_lock_irqsave(&clk_mgt_lock, flags); | |
986 | ||
987 | /* Grab the HW semaphore. */ | |
988 | while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) | |
989 | cpu_relax(); | |
990 | ||
991 | for (i = 0; i < ARRAY_SIZE(clock_reg); i++) { | |
992 | u32 val; | |
993 | u32 div; | |
994 | ||
995 | val = readl(clock_reg[i]); | |
996 | div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK); | |
997 | if (enable) { | |
998 | if ((div <= 1) || (div > 15)) { | |
999 | pr_err("prcmu: Bad clock divider %d in %s\n", | |
1000 | div, __func__); | |
1001 | goto unlock_and_return; | |
1002 | } | |
1003 | div <<= 1; | |
1004 | } else { | |
1005 | if (div <= 2) | |
1006 | goto unlock_and_return; | |
1007 | div >>= 1; | |
1008 | } | |
1009 | val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) | | |
1010 | (div & PRCM_CLK_MGT_CLKPLLDIV_MASK)); | |
1011 | writel(val, clock_reg[i]); | |
1012 | } | |
1013 | ||
1014 | unlock_and_return: | |
1015 | /* Release the HW semaphore. */ | |
1016 | writel(0, PRCM_SEM); | |
1017 | ||
1018 | spin_unlock_irqrestore(&clk_mgt_lock, flags); | |
1019 | } | |
1020 | ||
3df57bcf | 1021 | /** |
0508901c | 1022 | * db8500_set_ape_opp - set the appropriate APE OPP |
3df57bcf MN |
1023 | * @opp: The new APE operating point to which transition is to be made |
1024 | * Returns: 0 on success, non-zero on failure | |
1025 | * | |
1026 | * This function sets the operating point of the APE. | |
1027 | */ | |
0508901c | 1028 | int db8500_prcmu_set_ape_opp(u8 opp) |
3df57bcf MN |
1029 | { |
1030 | int r = 0; | |
1031 | ||
4d64d2e3 MN |
1032 | if (opp == mb1_transfer.ape_opp) |
1033 | return 0; | |
1034 | ||
3df57bcf MN |
1035 | mutex_lock(&mb1_transfer.lock); |
1036 | ||
4d64d2e3 MN |
1037 | if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP) |
1038 | request_even_slower_clocks(false); | |
1039 | ||
1040 | if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP)) | |
1041 | goto skip_message; | |
1042 | ||
c553b3ca | 1043 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
3df57bcf MN |
1044 | cpu_relax(); |
1045 | ||
1046 | writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); | |
1047 | writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP)); | |
4d64d2e3 MN |
1048 | writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp), |
1049 | (tcdm_base + PRCM_REQ_MB1_APE_OPP)); | |
3df57bcf | 1050 | |
c553b3ca | 1051 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
1052 | wait_for_completion(&mb1_transfer.work); |
1053 | ||
1054 | if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) || | |
1055 | (mb1_transfer.ack.ape_opp != opp)) | |
1056 | r = -EIO; | |
1057 | ||
4d64d2e3 MN |
1058 | skip_message: |
1059 | if ((!r && (opp == APE_50_PARTLY_25_OPP)) || | |
1060 | (r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP))) | |
1061 | request_even_slower_clocks(true); | |
1062 | if (!r) | |
1063 | mb1_transfer.ape_opp = opp; | |
1064 | ||
3df57bcf MN |
1065 | mutex_unlock(&mb1_transfer.lock); |
1066 | ||
1067 | return r; | |
1068 | } | |
1069 | ||
1070 | /** | |
0508901c | 1071 | * db8500_prcmu_get_ape_opp - get the current APE OPP |
3df57bcf MN |
1072 | * |
1073 | * Returns: the current APE OPP | |
1074 | */ | |
0508901c | 1075 | int db8500_prcmu_get_ape_opp(void) |
3df57bcf MN |
1076 | { |
1077 | return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP); | |
1078 | } | |
1079 | ||
1080 | /** | |
1081 | * prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage | |
1082 | * @enable: true to request the higher voltage, false to drop a request. | |
1083 | * | |
1084 | * Calls to this function to enable and disable requests must be balanced. | |
1085 | */ | |
1086 | int prcmu_request_ape_opp_100_voltage(bool enable) | |
1087 | { | |
1088 | int r = 0; | |
1089 | u8 header; | |
1090 | static unsigned int requests; | |
1091 | ||
1092 | mutex_lock(&mb1_transfer.lock); | |
1093 | ||
1094 | if (enable) { | |
1095 | if (0 != requests++) | |
1096 | goto unlock_and_return; | |
1097 | header = MB1H_REQUEST_APE_OPP_100_VOLT; | |
1098 | } else { | |
1099 | if (requests == 0) { | |
1100 | r = -EIO; | |
1101 | goto unlock_and_return; | |
1102 | } else if (1 != requests--) { | |
1103 | goto unlock_and_return; | |
1104 | } | |
1105 | header = MB1H_RELEASE_APE_OPP_100_VOLT; | |
1106 | } | |
1107 | ||
c553b3ca | 1108 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
3df57bcf MN |
1109 | cpu_relax(); |
1110 | ||
1111 | writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); | |
1112 | ||
c553b3ca | 1113 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
1114 | wait_for_completion(&mb1_transfer.work); |
1115 | ||
1116 | if ((mb1_transfer.ack.header != header) || | |
1117 | ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) | |
1118 | r = -EIO; | |
1119 | ||
1120 | unlock_and_return: | |
1121 | mutex_unlock(&mb1_transfer.lock); | |
1122 | ||
1123 | return r; | |
1124 | } | |
1125 | ||
1126 | /** | |
1127 | * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup | |
1128 | * | |
1129 | * This function releases the power state requirements of a USB wakeup. | |
1130 | */ | |
1131 | int prcmu_release_usb_wakeup_state(void) | |
1132 | { | |
1133 | int r = 0; | |
1134 | ||
1135 | mutex_lock(&mb1_transfer.lock); | |
1136 | ||
c553b3ca | 1137 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
3df57bcf MN |
1138 | cpu_relax(); |
1139 | ||
1140 | writeb(MB1H_RELEASE_USB_WAKEUP, | |
1141 | (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); | |
1142 | ||
c553b3ca | 1143 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
1144 | wait_for_completion(&mb1_transfer.work); |
1145 | ||
1146 | if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) || | |
1147 | ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0)) | |
1148 | r = -EIO; | |
1149 | ||
1150 | mutex_unlock(&mb1_transfer.lock); | |
1151 | ||
1152 | return r; | |
1153 | } | |
1154 | ||
0837bb72 MN |
1155 | static int request_pll(u8 clock, bool enable) |
1156 | { | |
1157 | int r = 0; | |
1158 | ||
6b6fae2b MN |
1159 | if (clock == PRCMU_PLLSOC0) |
1160 | clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF); | |
1161 | else if (clock == PRCMU_PLLSOC1) | |
0837bb72 MN |
1162 | clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF); |
1163 | else | |
1164 | return -EINVAL; | |
1165 | ||
1166 | mutex_lock(&mb1_transfer.lock); | |
1167 | ||
1168 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) | |
1169 | cpu_relax(); | |
1170 | ||
1171 | writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); | |
1172 | writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF)); | |
1173 | ||
1174 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); | |
1175 | wait_for_completion(&mb1_transfer.work); | |
1176 | ||
1177 | if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF) | |
1178 | r = -EIO; | |
1179 | ||
1180 | mutex_unlock(&mb1_transfer.lock); | |
1181 | ||
1182 | return r; | |
1183 | } | |
1184 | ||
0b9199e3 BJ |
1185 | /** |
1186 | * prcmu_set_hwacc - set the power state of a h/w accelerator | |
1187 | * @hwacc_dev: The hardware accelerator (enum hw_acc_dev). | |
1188 | * @state: The new power state (enum hw_acc_state). | |
1189 | * | |
1190 | * This function sets the power state of a hardware accelerator. | |
1191 | * This function should not be called from interrupt context. | |
1192 | * | |
1193 | * NOTE! Deprecated, to be removed when all users switched over to use the | |
1194 | * regulator framework API. | |
1195 | */ | |
1196 | int prcmu_set_hwacc(u16 hwacc_dev, u8 state) | |
1197 | { | |
1198 | int r = 0; | |
1199 | bool ram_retention = false; | |
1200 | bool enable, enable_ret; | |
1201 | ||
1202 | /* check argument */ | |
1203 | BUG_ON(hwacc_dev >= NUM_HW_ACC); | |
1204 | ||
1205 | /* get state of switches */ | |
1206 | enable = hwacc_enabled[hwacc_dev]; | |
1207 | enable_ret = hwacc_ret_enabled[hwacc_dev]; | |
1208 | ||
1209 | /* set flag if retention is possible */ | |
1210 | switch (hwacc_dev) { | |
1211 | case HW_ACC_SVAMMDSP: | |
1212 | case HW_ACC_SIAMMDSP: | |
1213 | case HW_ACC_ESRAM1: | |
1214 | case HW_ACC_ESRAM2: | |
1215 | case HW_ACC_ESRAM3: | |
1216 | case HW_ACC_ESRAM4: | |
1217 | ram_retention = true; | |
1218 | break; | |
1219 | } | |
1220 | ||
1221 | /* check argument */ | |
1222 | BUG_ON(state > HW_ON); | |
1223 | BUG_ON(state == HW_OFF_RAMRET && !ram_retention); | |
1224 | ||
1225 | /* modify enable flags */ | |
1226 | switch (state) { | |
1227 | case HW_OFF: | |
1228 | enable_ret = false; | |
1229 | enable = false; | |
1230 | break; | |
1231 | case HW_ON: | |
1232 | enable = true; | |
1233 | break; | |
1234 | case HW_OFF_RAMRET: | |
1235 | enable_ret = true; | |
1236 | enable = false; | |
1237 | break; | |
1238 | } | |
1239 | ||
1240 | /* get regulator (lazy) */ | |
1241 | if (hwacc_regulator[hwacc_dev] == NULL) { | |
1242 | hwacc_regulator[hwacc_dev] = regulator_get(NULL, | |
1243 | hwacc_regulator_name[hwacc_dev]); | |
1244 | if (IS_ERR(hwacc_regulator[hwacc_dev])) { | |
1245 | pr_err("prcmu: failed to get supply %s\n", | |
1246 | hwacc_regulator_name[hwacc_dev]); | |
1247 | r = PTR_ERR(hwacc_regulator[hwacc_dev]); | |
1248 | goto out; | |
1249 | } | |
1250 | } | |
1251 | ||
1252 | if (ram_retention) { | |
1253 | if (hwacc_ret_regulator[hwacc_dev] == NULL) { | |
1254 | hwacc_ret_regulator[hwacc_dev] = regulator_get(NULL, | |
1255 | hwacc_ret_regulator_name[hwacc_dev]); | |
1256 | if (IS_ERR(hwacc_ret_regulator[hwacc_dev])) { | |
1257 | pr_err("prcmu: failed to get supply %s\n", | |
1258 | hwacc_ret_regulator_name[hwacc_dev]); | |
1259 | r = PTR_ERR(hwacc_ret_regulator[hwacc_dev]); | |
1260 | goto out; | |
1261 | } | |
1262 | } | |
1263 | } | |
1264 | ||
1265 | /* set regulators */ | |
1266 | if (ram_retention) { | |
1267 | if (enable_ret && !hwacc_ret_enabled[hwacc_dev]) { | |
1268 | r = regulator_enable(hwacc_ret_regulator[hwacc_dev]); | |
1269 | if (r < 0) { | |
1270 | pr_err("prcmu_set_hwacc: ret enable failed\n"); | |
1271 | goto out; | |
1272 | } | |
1273 | hwacc_ret_enabled[hwacc_dev] = true; | |
1274 | } | |
1275 | } | |
1276 | ||
1277 | if (enable && !hwacc_enabled[hwacc_dev]) { | |
1278 | r = regulator_enable(hwacc_regulator[hwacc_dev]); | |
1279 | if (r < 0) { | |
1280 | pr_err("prcmu_set_hwacc: enable failed\n"); | |
1281 | goto out; | |
1282 | } | |
1283 | hwacc_enabled[hwacc_dev] = true; | |
1284 | } | |
1285 | ||
1286 | if (!enable && hwacc_enabled[hwacc_dev]) { | |
1287 | r = regulator_disable(hwacc_regulator[hwacc_dev]); | |
1288 | if (r < 0) { | |
1289 | pr_err("prcmu_set_hwacc: disable failed\n"); | |
1290 | goto out; | |
1291 | } | |
1292 | hwacc_enabled[hwacc_dev] = false; | |
1293 | } | |
1294 | ||
1295 | if (ram_retention) { | |
1296 | if (!enable_ret && hwacc_ret_enabled[hwacc_dev]) { | |
1297 | r = regulator_disable(hwacc_ret_regulator[hwacc_dev]); | |
1298 | if (r < 0) { | |
1299 | pr_err("prcmu_set_hwacc: ret disable failed\n"); | |
1300 | goto out; | |
1301 | } | |
1302 | hwacc_ret_enabled[hwacc_dev] = false; | |
1303 | } | |
1304 | } | |
1305 | ||
1306 | out: | |
1307 | return r; | |
1308 | } | |
1309 | EXPORT_SYMBOL(prcmu_set_hwacc); | |
1310 | ||
3df57bcf | 1311 | /** |
73180f85 | 1312 | * db8500_prcmu_set_epod - set the state of a EPOD (power domain) |
3df57bcf MN |
1313 | * @epod_id: The EPOD to set |
1314 | * @epod_state: The new EPOD state | |
1315 | * | |
1316 | * This function sets the state of a EPOD (power domain). It may not be called | |
1317 | * from interrupt context. | |
1318 | */ | |
73180f85 | 1319 | int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state) |
3df57bcf MN |
1320 | { |
1321 | int r = 0; | |
1322 | bool ram_retention = false; | |
1323 | int i; | |
1324 | ||
1325 | /* check argument */ | |
1326 | BUG_ON(epod_id >= NUM_EPOD_ID); | |
1327 | ||
1328 | /* set flag if retention is possible */ | |
1329 | switch (epod_id) { | |
1330 | case EPOD_ID_SVAMMDSP: | |
1331 | case EPOD_ID_SIAMMDSP: | |
1332 | case EPOD_ID_ESRAM12: | |
1333 | case EPOD_ID_ESRAM34: | |
1334 | ram_retention = true; | |
1335 | break; | |
1336 | } | |
1337 | ||
1338 | /* check argument */ | |
1339 | BUG_ON(epod_state > EPOD_STATE_ON); | |
1340 | BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention); | |
1341 | ||
1342 | /* get lock */ | |
1343 | mutex_lock(&mb2_transfer.lock); | |
1344 | ||
1345 | /* wait for mailbox */ | |
c553b3ca | 1346 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2)) |
3df57bcf MN |
1347 | cpu_relax(); |
1348 | ||
1349 | /* fill in mailbox */ | |
1350 | for (i = 0; i < NUM_EPOD_ID; i++) | |
1351 | writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i)); | |
1352 | writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id)); | |
1353 | ||
1354 | writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2)); | |
1355 | ||
c553b3ca | 1356 | writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
1357 | |
1358 | /* | |
1359 | * The current firmware version does not handle errors correctly, | |
1360 | * and we cannot recover if there is an error. | |
1361 | * This is expected to change when the firmware is updated. | |
1362 | */ | |
1363 | if (!wait_for_completion_timeout(&mb2_transfer.work, | |
1364 | msecs_to_jiffies(20000))) { | |
1365 | pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", | |
1366 | __func__); | |
1367 | r = -EIO; | |
1368 | goto unlock_and_return; | |
1369 | } | |
1370 | ||
1371 | if (mb2_transfer.ack.status != HWACC_PWR_ST_OK) | |
1372 | r = -EIO; | |
1373 | ||
1374 | unlock_and_return: | |
1375 | mutex_unlock(&mb2_transfer.lock); | |
1376 | return r; | |
1377 | } | |
1378 | ||
1379 | /** | |
1380 | * prcmu_configure_auto_pm - Configure autonomous power management. | |
1381 | * @sleep: Configuration for ApSleep. | |
1382 | * @idle: Configuration for ApIdle. | |
1383 | */ | |
1384 | void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep, | |
1385 | struct prcmu_auto_pm_config *idle) | |
1386 | { | |
1387 | u32 sleep_cfg; | |
1388 | u32 idle_cfg; | |
1389 | unsigned long flags; | |
e3726fcf | 1390 | |
3df57bcf | 1391 | BUG_ON((sleep == NULL) || (idle == NULL)); |
650c2a21 | 1392 | |
3df57bcf MN |
1393 | sleep_cfg = (sleep->sva_auto_pm_enable & 0xF); |
1394 | sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF)); | |
1395 | sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF)); | |
1396 | sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF)); | |
1397 | sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF)); | |
1398 | sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF)); | |
e3726fcf | 1399 | |
3df57bcf MN |
1400 | idle_cfg = (idle->sva_auto_pm_enable & 0xF); |
1401 | idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF)); | |
1402 | idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF)); | |
1403 | idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF)); | |
1404 | idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF)); | |
1405 | idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF)); | |
e3726fcf | 1406 | |
3df57bcf | 1407 | spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags); |
e0befb23 | 1408 | |
3df57bcf MN |
1409 | /* |
1410 | * The autonomous power management configuration is done through | |
1411 | * fields in mailbox 2, but these fields are only used as shared | |
1412 | * variables - i.e. there is no need to send a message. | |
1413 | */ | |
1414 | writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP)); | |
1415 | writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE)); | |
e0befb23 | 1416 | |
3df57bcf MN |
1417 | mb2_transfer.auto_pm_enabled = |
1418 | ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) || | |
1419 | (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) || | |
1420 | (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) || | |
1421 | (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON)); | |
e0befb23 | 1422 | |
3df57bcf MN |
1423 | spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags); |
1424 | } | |
1425 | EXPORT_SYMBOL(prcmu_configure_auto_pm); | |
e3726fcf | 1426 | |
3df57bcf MN |
1427 | bool prcmu_is_auto_pm_enabled(void) |
1428 | { | |
1429 | return mb2_transfer.auto_pm_enabled; | |
1430 | } | |
e0befb23 | 1431 | |
3df57bcf MN |
1432 | static int request_sysclk(bool enable) |
1433 | { | |
1434 | int r; | |
1435 | unsigned long flags; | |
e3726fcf | 1436 | |
3df57bcf | 1437 | r = 0; |
e3726fcf | 1438 | |
3df57bcf | 1439 | mutex_lock(&mb3_transfer.sysclk_lock); |
e0befb23 | 1440 | |
3df57bcf | 1441 | spin_lock_irqsave(&mb3_transfer.lock, flags); |
e0befb23 | 1442 | |
c553b3ca | 1443 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3)) |
3df57bcf | 1444 | cpu_relax(); |
e0befb23 | 1445 | |
3df57bcf | 1446 | writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT)); |
e3726fcf | 1447 | |
3df57bcf | 1448 | writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3)); |
c553b3ca | 1449 | writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET); |
e3726fcf | 1450 | |
3df57bcf MN |
1451 | spin_unlock_irqrestore(&mb3_transfer.lock, flags); |
1452 | ||
1453 | /* | |
1454 | * The firmware only sends an ACK if we want to enable the | |
1455 | * SysClk, and it succeeds. | |
1456 | */ | |
1457 | if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work, | |
1458 | msecs_to_jiffies(20000))) { | |
1459 | pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", | |
1460 | __func__); | |
1461 | r = -EIO; | |
1462 | } | |
1463 | ||
1464 | mutex_unlock(&mb3_transfer.sysclk_lock); | |
1465 | ||
1466 | return r; | |
1467 | } | |
1468 | ||
1469 | static int request_timclk(bool enable) | |
1470 | { | |
1471 | u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK); | |
1472 | ||
1473 | if (!enable) | |
1474 | val |= PRCM_TCR_STOP_TIMERS; | |
c553b3ca | 1475 | writel(val, PRCM_TCR); |
3df57bcf MN |
1476 | |
1477 | return 0; | |
1478 | } | |
1479 | ||
6b6fae2b | 1480 | static int request_clock(u8 clock, bool enable) |
3df57bcf MN |
1481 | { |
1482 | u32 val; | |
1483 | unsigned long flags; | |
1484 | ||
1485 | spin_lock_irqsave(&clk_mgt_lock, flags); | |
1486 | ||
1487 | /* Grab the HW semaphore. */ | |
c553b3ca | 1488 | while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) |
3df57bcf MN |
1489 | cpu_relax(); |
1490 | ||
6b6fae2b | 1491 | val = readl(clk_mgt[clock].reg); |
3df57bcf MN |
1492 | if (enable) { |
1493 | val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw); | |
1494 | } else { | |
1495 | clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); | |
1496 | val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK); | |
1497 | } | |
6b6fae2b | 1498 | writel(val, clk_mgt[clock].reg); |
3df57bcf MN |
1499 | |
1500 | /* Release the HW semaphore. */ | |
c553b3ca | 1501 | writel(0, PRCM_SEM); |
3df57bcf MN |
1502 | |
1503 | spin_unlock_irqrestore(&clk_mgt_lock, flags); | |
1504 | ||
1505 | return 0; | |
1506 | } | |
1507 | ||
0837bb72 MN |
1508 | static int request_sga_clock(u8 clock, bool enable) |
1509 | { | |
1510 | u32 val; | |
1511 | int ret; | |
1512 | ||
1513 | if (enable) { | |
1514 | val = readl(PRCM_CGATING_BYPASS); | |
1515 | writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS); | |
1516 | } | |
1517 | ||
6b6fae2b | 1518 | ret = request_clock(clock, enable); |
0837bb72 MN |
1519 | |
1520 | if (!ret && !enable) { | |
1521 | val = readl(PRCM_CGATING_BYPASS); | |
1522 | writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS); | |
1523 | } | |
1524 | ||
1525 | return ret; | |
1526 | } | |
1527 | ||
6b6fae2b MN |
1528 | static inline bool plldsi_locked(void) |
1529 | { | |
1530 | return (readl(PRCM_PLLDSI_LOCKP) & | |
1531 | (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 | | |
1532 | PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) == | |
1533 | (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 | | |
1534 | PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3); | |
1535 | } | |
1536 | ||
1537 | static int request_plldsi(bool enable) | |
1538 | { | |
1539 | int r = 0; | |
1540 | u32 val; | |
1541 | ||
1542 | writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP | | |
1543 | PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ? | |
1544 | PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET)); | |
1545 | ||
1546 | val = readl(PRCM_PLLDSI_ENABLE); | |
1547 | if (enable) | |
1548 | val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; | |
1549 | else | |
1550 | val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; | |
1551 | writel(val, PRCM_PLLDSI_ENABLE); | |
1552 | ||
1553 | if (enable) { | |
1554 | unsigned int i; | |
1555 | bool locked = plldsi_locked(); | |
1556 | ||
1557 | for (i = 10; !locked && (i > 0); --i) { | |
1558 | udelay(100); | |
1559 | locked = plldsi_locked(); | |
1560 | } | |
1561 | if (locked) { | |
1562 | writel(PRCM_APE_RESETN_DSIPLL_RESETN, | |
1563 | PRCM_APE_RESETN_SET); | |
1564 | } else { | |
1565 | writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP | | |
1566 | PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), | |
1567 | PRCM_MMIP_LS_CLAMP_SET); | |
1568 | val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE; | |
1569 | writel(val, PRCM_PLLDSI_ENABLE); | |
1570 | r = -EAGAIN; | |
1571 | } | |
1572 | } else { | |
1573 | writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR); | |
1574 | } | |
1575 | return r; | |
1576 | } | |
1577 | ||
1578 | static int request_dsiclk(u8 n, bool enable) | |
1579 | { | |
1580 | u32 val; | |
1581 | ||
1582 | val = readl(PRCM_DSI_PLLOUT_SEL); | |
1583 | val &= ~dsiclk[n].divsel_mask; | |
1584 | val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) << | |
1585 | dsiclk[n].divsel_shift); | |
1586 | writel(val, PRCM_DSI_PLLOUT_SEL); | |
1587 | return 0; | |
1588 | } | |
1589 | ||
1590 | static int request_dsiescclk(u8 n, bool enable) | |
1591 | { | |
1592 | u32 val; | |
1593 | ||
1594 | val = readl(PRCM_DSITVCLK_DIV); | |
1595 | enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en); | |
1596 | writel(val, PRCM_DSITVCLK_DIV); | |
1597 | return 0; | |
1598 | } | |
1599 | ||
3df57bcf | 1600 | /** |
73180f85 | 1601 | * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled. |
3df57bcf MN |
1602 | * @clock: The clock for which the request is made. |
1603 | * @enable: Whether the clock should be enabled (true) or disabled (false). | |
1604 | * | |
1605 | * This function should only be used by the clock implementation. | |
1606 | * Do not use it from any other place! | |
1607 | */ | |
73180f85 | 1608 | int db8500_prcmu_request_clock(u8 clock, bool enable) |
3df57bcf | 1609 | { |
6b6fae2b | 1610 | if (clock == PRCMU_SGACLK) |
0837bb72 | 1611 | return request_sga_clock(clock, enable); |
6b6fae2b MN |
1612 | else if (clock < PRCMU_NUM_REG_CLOCKS) |
1613 | return request_clock(clock, enable); | |
1614 | else if (clock == PRCMU_TIMCLK) | |
3df57bcf | 1615 | return request_timclk(enable); |
6b6fae2b MN |
1616 | else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) |
1617 | return request_dsiclk((clock - PRCMU_DSI0CLK), enable); | |
1618 | else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) | |
1619 | return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable); | |
1620 | else if (clock == PRCMU_PLLDSI) | |
1621 | return request_plldsi(enable); | |
1622 | else if (clock == PRCMU_SYSCLK) | |
3df57bcf | 1623 | return request_sysclk(enable); |
6b6fae2b | 1624 | else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1)) |
0837bb72 | 1625 | return request_pll(clock, enable); |
6b6fae2b MN |
1626 | else |
1627 | return -EINVAL; | |
1628 | } | |
1629 | ||
1630 | static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate, | |
1631 | int branch) | |
1632 | { | |
1633 | u64 rate; | |
1634 | u32 val; | |
1635 | u32 d; | |
1636 | u32 div = 1; | |
1637 | ||
1638 | val = readl(reg); | |
1639 | ||
1640 | rate = src_rate; | |
1641 | rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT); | |
1642 | ||
1643 | d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT); | |
1644 | if (d > 1) | |
1645 | div *= d; | |
1646 | ||
1647 | d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT); | |
1648 | if (d > 1) | |
1649 | div *= d; | |
1650 | ||
1651 | if (val & PRCM_PLL_FREQ_SELDIV2) | |
1652 | div *= 2; | |
1653 | ||
1654 | if ((branch == PLL_FIX) || ((branch == PLL_DIV) && | |
1655 | (val & PRCM_PLL_FREQ_DIV2EN) && | |
1656 | ((reg == PRCM_PLLSOC0_FREQ) || | |
1657 | (reg == PRCM_PLLDDR_FREQ)))) | |
1658 | div *= 2; | |
1659 | ||
1660 | (void)do_div(rate, div); | |
1661 | ||
1662 | return (unsigned long)rate; | |
1663 | } | |
1664 | ||
1665 | #define ROOT_CLOCK_RATE 38400000 | |
1666 | ||
1667 | static unsigned long clock_rate(u8 clock) | |
1668 | { | |
1669 | u32 val; | |
1670 | u32 pllsw; | |
1671 | unsigned long rate = ROOT_CLOCK_RATE; | |
1672 | ||
1673 | val = readl(clk_mgt[clock].reg); | |
1674 | ||
1675 | if (val & PRCM_CLK_MGT_CLK38) { | |
1676 | if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV)) | |
1677 | rate /= 2; | |
1678 | return rate; | |
1679 | } | |
1680 | ||
1681 | val |= clk_mgt[clock].pllsw; | |
1682 | pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); | |
1683 | ||
1684 | if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0) | |
1685 | rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch); | |
1686 | else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1) | |
1687 | rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch); | |
1688 | else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR) | |
1689 | rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch); | |
1690 | else | |
1691 | return 0; | |
1692 | ||
1693 | if ((clock == PRCMU_SGACLK) && | |
1694 | (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) { | |
1695 | u64 r = (rate * 10); | |
1696 | ||
1697 | (void)do_div(r, 25); | |
1698 | return (unsigned long)r; | |
1699 | } | |
1700 | val &= PRCM_CLK_MGT_CLKPLLDIV_MASK; | |
1701 | if (val) | |
1702 | return rate / val; | |
1703 | else | |
1704 | return 0; | |
1705 | } | |
1706 | ||
1707 | static unsigned long dsiclk_rate(u8 n) | |
1708 | { | |
1709 | u32 divsel; | |
1710 | u32 div = 1; | |
1711 | ||
1712 | divsel = readl(PRCM_DSI_PLLOUT_SEL); | |
1713 | divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift); | |
1714 | ||
1715 | if (divsel == PRCM_DSI_PLLOUT_SEL_OFF) | |
1716 | divsel = dsiclk[n].divsel; | |
1717 | ||
1718 | switch (divsel) { | |
1719 | case PRCM_DSI_PLLOUT_SEL_PHI_4: | |
1720 | div *= 2; | |
1721 | case PRCM_DSI_PLLOUT_SEL_PHI_2: | |
1722 | div *= 2; | |
1723 | case PRCM_DSI_PLLOUT_SEL_PHI: | |
1724 | return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), | |
1725 | PLL_RAW) / div; | |
e62ccf3a | 1726 | default: |
6b6fae2b | 1727 | return 0; |
e62ccf3a | 1728 | } |
6b6fae2b MN |
1729 | } |
1730 | ||
1731 | static unsigned long dsiescclk_rate(u8 n) | |
1732 | { | |
1733 | u32 div; | |
1734 | ||
1735 | div = readl(PRCM_DSITVCLK_DIV); | |
1736 | div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift)); | |
1737 | return clock_rate(PRCMU_TVCLK) / max((u32)1, div); | |
1738 | } | |
1739 | ||
1740 | unsigned long prcmu_clock_rate(u8 clock) | |
1741 | { | |
e62ccf3a | 1742 | if (clock < PRCMU_NUM_REG_CLOCKS) |
6b6fae2b MN |
1743 | return clock_rate(clock); |
1744 | else if (clock == PRCMU_TIMCLK) | |
1745 | return ROOT_CLOCK_RATE / 16; | |
1746 | else if (clock == PRCMU_SYSCLK) | |
1747 | return ROOT_CLOCK_RATE; | |
1748 | else if (clock == PRCMU_PLLSOC0) | |
1749 | return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW); | |
1750 | else if (clock == PRCMU_PLLSOC1) | |
1751 | return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW); | |
1752 | else if (clock == PRCMU_PLLDDR) | |
1753 | return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW); | |
1754 | else if (clock == PRCMU_PLLDSI) | |
1755 | return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), | |
1756 | PLL_RAW); | |
1757 | else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) | |
1758 | return dsiclk_rate(clock - PRCMU_DSI0CLK); | |
1759 | else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) | |
1760 | return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK); | |
1761 | else | |
1762 | return 0; | |
1763 | } | |
1764 | ||
1765 | static unsigned long clock_source_rate(u32 clk_mgt_val, int branch) | |
1766 | { | |
1767 | if (clk_mgt_val & PRCM_CLK_MGT_CLK38) | |
1768 | return ROOT_CLOCK_RATE; | |
1769 | clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK; | |
1770 | if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0) | |
1771 | return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch); | |
1772 | else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1) | |
1773 | return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch); | |
1774 | else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR) | |
1775 | return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch); | |
1776 | else | |
1777 | return 0; | |
1778 | } | |
1779 | ||
1780 | static u32 clock_divider(unsigned long src_rate, unsigned long rate) | |
1781 | { | |
1782 | u32 div; | |
1783 | ||
1784 | div = (src_rate / rate); | |
1785 | if (div == 0) | |
1786 | return 1; | |
1787 | if (rate < (src_rate / div)) | |
1788 | div++; | |
1789 | return div; | |
1790 | } | |
1791 | ||
1792 | static long round_clock_rate(u8 clock, unsigned long rate) | |
1793 | { | |
1794 | u32 val; | |
1795 | u32 div; | |
1796 | unsigned long src_rate; | |
1797 | long rounded_rate; | |
1798 | ||
1799 | val = readl(clk_mgt[clock].reg); | |
1800 | src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), | |
1801 | clk_mgt[clock].branch); | |
1802 | div = clock_divider(src_rate, rate); | |
1803 | if (val & PRCM_CLK_MGT_CLK38) { | |
1804 | if (clk_mgt[clock].clk38div) { | |
1805 | if (div > 2) | |
1806 | div = 2; | |
1807 | } else { | |
1808 | div = 1; | |
1809 | } | |
1810 | } else if ((clock == PRCMU_SGACLK) && (div == 3)) { | |
1811 | u64 r = (src_rate * 10); | |
1812 | ||
1813 | (void)do_div(r, 25); | |
1814 | if (r <= rate) | |
1815 | return (unsigned long)r; | |
1816 | } | |
1817 | rounded_rate = (src_rate / min(div, (u32)31)); | |
1818 | ||
1819 | return rounded_rate; | |
1820 | } | |
1821 | ||
1822 | #define MIN_PLL_VCO_RATE 600000000ULL | |
1823 | #define MAX_PLL_VCO_RATE 1680640000ULL | |
1824 | ||
1825 | static long round_plldsi_rate(unsigned long rate) | |
1826 | { | |
1827 | long rounded_rate = 0; | |
1828 | unsigned long src_rate; | |
1829 | unsigned long rem; | |
1830 | u32 r; | |
1831 | ||
1832 | src_rate = clock_rate(PRCMU_HDMICLK); | |
1833 | rem = rate; | |
1834 | ||
1835 | for (r = 7; (rem > 0) && (r > 0); r--) { | |
1836 | u64 d; | |
1837 | ||
1838 | d = (r * rate); | |
1839 | (void)do_div(d, src_rate); | |
1840 | if (d < 6) | |
1841 | d = 6; | |
1842 | else if (d > 255) | |
1843 | d = 255; | |
1844 | d *= src_rate; | |
1845 | if (((2 * d) < (r * MIN_PLL_VCO_RATE)) || | |
1846 | ((r * MAX_PLL_VCO_RATE) < (2 * d))) | |
1847 | continue; | |
1848 | (void)do_div(d, r); | |
1849 | if (rate < d) { | |
1850 | if (rounded_rate == 0) | |
1851 | rounded_rate = (long)d; | |
1852 | break; | |
1853 | } | |
1854 | if ((rate - d) < rem) { | |
1855 | rem = (rate - d); | |
1856 | rounded_rate = (long)d; | |
1857 | } | |
1858 | } | |
1859 | return rounded_rate; | |
1860 | } | |
1861 | ||
1862 | static long round_dsiclk_rate(unsigned long rate) | |
1863 | { | |
1864 | u32 div; | |
1865 | unsigned long src_rate; | |
1866 | long rounded_rate; | |
1867 | ||
1868 | src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), | |
1869 | PLL_RAW); | |
1870 | div = clock_divider(src_rate, rate); | |
1871 | rounded_rate = (src_rate / ((div > 2) ? 4 : div)); | |
1872 | ||
1873 | return rounded_rate; | |
1874 | } | |
1875 | ||
1876 | static long round_dsiescclk_rate(unsigned long rate) | |
1877 | { | |
1878 | u32 div; | |
1879 | unsigned long src_rate; | |
1880 | long rounded_rate; | |
1881 | ||
1882 | src_rate = clock_rate(PRCMU_TVCLK); | |
1883 | div = clock_divider(src_rate, rate); | |
1884 | rounded_rate = (src_rate / min(div, (u32)255)); | |
1885 | ||
1886 | return rounded_rate; | |
1887 | } | |
1888 | ||
1889 | long prcmu_round_clock_rate(u8 clock, unsigned long rate) | |
1890 | { | |
1891 | if (clock < PRCMU_NUM_REG_CLOCKS) | |
1892 | return round_clock_rate(clock, rate); | |
1893 | else if (clock == PRCMU_PLLDSI) | |
1894 | return round_plldsi_rate(rate); | |
1895 | else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) | |
1896 | return round_dsiclk_rate(rate); | |
1897 | else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) | |
1898 | return round_dsiescclk_rate(rate); | |
1899 | else | |
1900 | return (long)prcmu_clock_rate(clock); | |
1901 | } | |
1902 | ||
1903 | static void set_clock_rate(u8 clock, unsigned long rate) | |
1904 | { | |
1905 | u32 val; | |
1906 | u32 div; | |
1907 | unsigned long src_rate; | |
1908 | unsigned long flags; | |
1909 | ||
1910 | spin_lock_irqsave(&clk_mgt_lock, flags); | |
1911 | ||
1912 | /* Grab the HW semaphore. */ | |
1913 | while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) | |
1914 | cpu_relax(); | |
1915 | ||
1916 | val = readl(clk_mgt[clock].reg); | |
1917 | src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), | |
1918 | clk_mgt[clock].branch); | |
1919 | div = clock_divider(src_rate, rate); | |
1920 | if (val & PRCM_CLK_MGT_CLK38) { | |
1921 | if (clk_mgt[clock].clk38div) { | |
1922 | if (div > 1) | |
1923 | val |= PRCM_CLK_MGT_CLK38DIV; | |
1924 | else | |
1925 | val &= ~PRCM_CLK_MGT_CLK38DIV; | |
1926 | } | |
1927 | } else if (clock == PRCMU_SGACLK) { | |
1928 | val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK | | |
1929 | PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN); | |
1930 | if (div == 3) { | |
1931 | u64 r = (src_rate * 10); | |
1932 | ||
1933 | (void)do_div(r, 25); | |
1934 | if (r <= rate) { | |
1935 | val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN; | |
1936 | div = 0; | |
1937 | } | |
1938 | } | |
1939 | val |= min(div, (u32)31); | |
1940 | } else { | |
1941 | val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK; | |
1942 | val |= min(div, (u32)31); | |
1943 | } | |
1944 | writel(val, clk_mgt[clock].reg); | |
1945 | ||
1946 | /* Release the HW semaphore. */ | |
1947 | writel(0, PRCM_SEM); | |
1948 | ||
1949 | spin_unlock_irqrestore(&clk_mgt_lock, flags); | |
1950 | } | |
1951 | ||
1952 | static int set_plldsi_rate(unsigned long rate) | |
1953 | { | |
1954 | unsigned long src_rate; | |
1955 | unsigned long rem; | |
1956 | u32 pll_freq = 0; | |
1957 | u32 r; | |
1958 | ||
1959 | src_rate = clock_rate(PRCMU_HDMICLK); | |
1960 | rem = rate; | |
1961 | ||
1962 | for (r = 7; (rem > 0) && (r > 0); r--) { | |
1963 | u64 d; | |
1964 | u64 hwrate; | |
1965 | ||
1966 | d = (r * rate); | |
1967 | (void)do_div(d, src_rate); | |
1968 | if (d < 6) | |
1969 | d = 6; | |
1970 | else if (d > 255) | |
1971 | d = 255; | |
1972 | hwrate = (d * src_rate); | |
1973 | if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) || | |
1974 | ((r * MAX_PLL_VCO_RATE) < (2 * hwrate))) | |
1975 | continue; | |
1976 | (void)do_div(hwrate, r); | |
1977 | if (rate < hwrate) { | |
1978 | if (pll_freq == 0) | |
1979 | pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) | | |
1980 | (r << PRCM_PLL_FREQ_R_SHIFT)); | |
1981 | break; | |
1982 | } | |
1983 | if ((rate - hwrate) < rem) { | |
1984 | rem = (rate - hwrate); | |
1985 | pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) | | |
1986 | (r << PRCM_PLL_FREQ_R_SHIFT)); | |
1987 | } | |
1988 | } | |
1989 | if (pll_freq == 0) | |
1990 | return -EINVAL; | |
1991 | ||
1992 | pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT); | |
1993 | writel(pll_freq, PRCM_PLLDSI_FREQ); | |
1994 | ||
1995 | return 0; | |
1996 | } | |
1997 | ||
1998 | static void set_dsiclk_rate(u8 n, unsigned long rate) | |
1999 | { | |
2000 | u32 val; | |
2001 | u32 div; | |
2002 | ||
2003 | div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ, | |
2004 | clock_rate(PRCMU_HDMICLK), PLL_RAW), rate); | |
2005 | ||
2006 | dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI : | |
2007 | (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 : | |
2008 | /* else */ PRCM_DSI_PLLOUT_SEL_PHI_4; | |
2009 | ||
2010 | val = readl(PRCM_DSI_PLLOUT_SEL); | |
2011 | val &= ~dsiclk[n].divsel_mask; | |
2012 | val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift); | |
2013 | writel(val, PRCM_DSI_PLLOUT_SEL); | |
2014 | } | |
2015 | ||
2016 | static void set_dsiescclk_rate(u8 n, unsigned long rate) | |
2017 | { | |
2018 | u32 val; | |
2019 | u32 div; | |
2020 | ||
2021 | div = clock_divider(clock_rate(PRCMU_TVCLK), rate); | |
2022 | val = readl(PRCM_DSITVCLK_DIV); | |
2023 | val &= ~dsiescclk[n].div_mask; | |
2024 | val |= (min(div, (u32)255) << dsiescclk[n].div_shift); | |
2025 | writel(val, PRCM_DSITVCLK_DIV); | |
2026 | } | |
2027 | ||
2028 | int prcmu_set_clock_rate(u8 clock, unsigned long rate) | |
2029 | { | |
2030 | if (clock < PRCMU_NUM_REG_CLOCKS) | |
2031 | set_clock_rate(clock, rate); | |
2032 | else if (clock == PRCMU_PLLDSI) | |
2033 | return set_plldsi_rate(rate); | |
2034 | else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) | |
2035 | set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate); | |
2036 | else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) | |
2037 | set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate); | |
2038 | return 0; | |
3df57bcf MN |
2039 | } |
2040 | ||
73180f85 | 2041 | int db8500_prcmu_config_esram0_deep_sleep(u8 state) |
3df57bcf MN |
2042 | { |
2043 | if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) || | |
2044 | (state < ESRAM0_DEEP_SLEEP_STATE_OFF)) | |
2045 | return -EINVAL; | |
2046 | ||
2047 | mutex_lock(&mb4_transfer.lock); | |
2048 | ||
c553b3ca | 2049 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) |
3df57bcf MN |
2050 | cpu_relax(); |
2051 | ||
2052 | writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); | |
2053 | writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON), | |
2054 | (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE)); | |
2055 | writeb(DDR_PWR_STATE_ON, | |
2056 | (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE)); | |
2057 | writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST)); | |
2058 | ||
c553b3ca | 2059 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
2060 | wait_for_completion(&mb4_transfer.work); |
2061 | ||
2062 | mutex_unlock(&mb4_transfer.lock); | |
2063 | ||
2064 | return 0; | |
2065 | } | |
2066 | ||
0508901c | 2067 | int db8500_prcmu_config_hotdog(u8 threshold) |
3df57bcf MN |
2068 | { |
2069 | mutex_lock(&mb4_transfer.lock); | |
2070 | ||
c553b3ca | 2071 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) |
3df57bcf MN |
2072 | cpu_relax(); |
2073 | ||
2074 | writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD)); | |
2075 | writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); | |
2076 | ||
c553b3ca | 2077 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
2078 | wait_for_completion(&mb4_transfer.work); |
2079 | ||
2080 | mutex_unlock(&mb4_transfer.lock); | |
2081 | ||
2082 | return 0; | |
2083 | } | |
2084 | ||
0508901c | 2085 | int db8500_prcmu_config_hotmon(u8 low, u8 high) |
3df57bcf MN |
2086 | { |
2087 | mutex_lock(&mb4_transfer.lock); | |
2088 | ||
c553b3ca | 2089 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) |
3df57bcf MN |
2090 | cpu_relax(); |
2091 | ||
2092 | writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW)); | |
2093 | writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH)); | |
2094 | writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH), | |
2095 | (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG)); | |
2096 | writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); | |
2097 | ||
c553b3ca | 2098 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
2099 | wait_for_completion(&mb4_transfer.work); |
2100 | ||
2101 | mutex_unlock(&mb4_transfer.lock); | |
2102 | ||
2103 | return 0; | |
2104 | } | |
2105 | ||
2106 | static int config_hot_period(u16 val) | |
2107 | { | |
2108 | mutex_lock(&mb4_transfer.lock); | |
2109 | ||
c553b3ca | 2110 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) |
3df57bcf MN |
2111 | cpu_relax(); |
2112 | ||
2113 | writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD)); | |
2114 | writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); | |
2115 | ||
c553b3ca | 2116 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
2117 | wait_for_completion(&mb4_transfer.work); |
2118 | ||
2119 | mutex_unlock(&mb4_transfer.lock); | |
2120 | ||
2121 | return 0; | |
2122 | } | |
2123 | ||
0508901c | 2124 | int db8500_prcmu_start_temp_sense(u16 cycles32k) |
3df57bcf MN |
2125 | { |
2126 | if (cycles32k == 0xFFFF) | |
2127 | return -EINVAL; | |
2128 | ||
2129 | return config_hot_period(cycles32k); | |
2130 | } | |
2131 | ||
0508901c | 2132 | int db8500_prcmu_stop_temp_sense(void) |
3df57bcf MN |
2133 | { |
2134 | return config_hot_period(0xFFFF); | |
2135 | } | |
2136 | ||
84165b80 JA |
2137 | static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3) |
2138 | { | |
2139 | ||
2140 | mutex_lock(&mb4_transfer.lock); | |
2141 | ||
2142 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4)) | |
2143 | cpu_relax(); | |
2144 | ||
2145 | writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0)); | |
2146 | writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1)); | |
2147 | writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2)); | |
2148 | writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3)); | |
2149 | ||
2150 | writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4)); | |
2151 | ||
2152 | writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET); | |
2153 | wait_for_completion(&mb4_transfer.work); | |
2154 | ||
2155 | mutex_unlock(&mb4_transfer.lock); | |
2156 | ||
2157 | return 0; | |
2158 | ||
2159 | } | |
2160 | ||
0508901c | 2161 | int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off) |
84165b80 JA |
2162 | { |
2163 | BUG_ON(num == 0 || num > 0xf); | |
2164 | return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0, | |
2165 | sleep_auto_off ? A9WDOG_AUTO_OFF_EN : | |
2166 | A9WDOG_AUTO_OFF_DIS); | |
2167 | } | |
2168 | ||
0508901c | 2169 | int db8500_prcmu_enable_a9wdog(u8 id) |
84165b80 JA |
2170 | { |
2171 | return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0); | |
2172 | } | |
2173 | ||
0508901c | 2174 | int db8500_prcmu_disable_a9wdog(u8 id) |
84165b80 JA |
2175 | { |
2176 | return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0); | |
2177 | } | |
2178 | ||
0508901c | 2179 | int db8500_prcmu_kick_a9wdog(u8 id) |
84165b80 JA |
2180 | { |
2181 | return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0); | |
2182 | } | |
2183 | ||
2184 | /* | |
2185 | * timeout is 28 bit, in ms. | |
2186 | */ | |
0508901c | 2187 | int db8500_prcmu_load_a9wdog(u8 id, u32 timeout) |
84165b80 | 2188 | { |
84165b80 JA |
2189 | return prcmu_a9wdog(MB4H_A9WDOG_LOAD, |
2190 | (id & A9WDOG_ID_MASK) | | |
2191 | /* | |
2192 | * Put the lowest 28 bits of timeout at | |
2193 | * offset 4. Four first bits are used for id. | |
2194 | */ | |
2195 | (u8)((timeout << 4) & 0xf0), | |
2196 | (u8)((timeout >> 4) & 0xff), | |
2197 | (u8)((timeout >> 12) & 0xff), | |
2198 | (u8)((timeout >> 20) & 0xff)); | |
2199 | } | |
2200 | ||
e3726fcf LW |
2201 | /** |
2202 | * prcmu_abb_read() - Read register value(s) from the ABB. | |
2203 | * @slave: The I2C slave address. | |
2204 | * @reg: The (start) register address. | |
2205 | * @value: The read out value(s). | |
2206 | * @size: The number of registers to read. | |
2207 | * | |
2208 | * Reads register value(s) from the ABB. | |
2209 | * @size has to be 1 for the current firmware version. | |
2210 | */ | |
2211 | int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) | |
2212 | { | |
2213 | int r; | |
2214 | ||
2215 | if (size != 1) | |
2216 | return -EINVAL; | |
2217 | ||
3df57bcf | 2218 | mutex_lock(&mb5_transfer.lock); |
e3726fcf | 2219 | |
c553b3ca | 2220 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) |
e3726fcf LW |
2221 | cpu_relax(); |
2222 | ||
3df57bcf MN |
2223 | writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); |
2224 | writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); | |
2225 | writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); | |
2226 | writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); | |
2227 | ||
c553b3ca | 2228 | writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); |
e3726fcf | 2229 | |
e3726fcf | 2230 | if (!wait_for_completion_timeout(&mb5_transfer.work, |
3df57bcf MN |
2231 | msecs_to_jiffies(20000))) { |
2232 | pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", | |
2233 | __func__); | |
e3726fcf | 2234 | r = -EIO; |
3df57bcf MN |
2235 | } else { |
2236 | r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO); | |
e3726fcf | 2237 | } |
3df57bcf | 2238 | |
e3726fcf LW |
2239 | if (!r) |
2240 | *value = mb5_transfer.ack.value; | |
2241 | ||
e3726fcf | 2242 | mutex_unlock(&mb5_transfer.lock); |
3df57bcf | 2243 | |
e3726fcf LW |
2244 | return r; |
2245 | } | |
e3726fcf LW |
2246 | |
2247 | /** | |
2248 | * prcmu_abb_write() - Write register value(s) to the ABB. | |
2249 | * @slave: The I2C slave address. | |
2250 | * @reg: The (start) register address. | |
2251 | * @value: The value(s) to write. | |
2252 | * @size: The number of registers to write. | |
2253 | * | |
2254 | * Reads register value(s) from the ABB. | |
2255 | * @size has to be 1 for the current firmware version. | |
2256 | */ | |
2257 | int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) | |
2258 | { | |
2259 | int r; | |
2260 | ||
2261 | if (size != 1) | |
2262 | return -EINVAL; | |
2263 | ||
3df57bcf | 2264 | mutex_lock(&mb5_transfer.lock); |
e3726fcf | 2265 | |
c553b3ca | 2266 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) |
e3726fcf LW |
2267 | cpu_relax(); |
2268 | ||
3df57bcf MN |
2269 | writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP)); |
2270 | writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS)); | |
2271 | writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG)); | |
2272 | writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL)); | |
2273 | ||
c553b3ca | 2274 | writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); |
e3726fcf | 2275 | |
e3726fcf | 2276 | if (!wait_for_completion_timeout(&mb5_transfer.work, |
3df57bcf MN |
2277 | msecs_to_jiffies(20000))) { |
2278 | pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n", | |
2279 | __func__); | |
e3726fcf | 2280 | r = -EIO; |
3df57bcf MN |
2281 | } else { |
2282 | r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO); | |
e3726fcf | 2283 | } |
e3726fcf | 2284 | |
e3726fcf | 2285 | mutex_unlock(&mb5_transfer.lock); |
3df57bcf | 2286 | |
e3726fcf LW |
2287 | return r; |
2288 | } | |
e3726fcf | 2289 | |
3df57bcf MN |
2290 | /** |
2291 | * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem | |
2292 | */ | |
2293 | void prcmu_ac_wake_req(void) | |
e0befb23 | 2294 | { |
3df57bcf | 2295 | u32 val; |
d6e3002e | 2296 | u32 status; |
e0befb23 | 2297 | |
3df57bcf | 2298 | mutex_lock(&mb0_transfer.ac_wake_lock); |
e0befb23 | 2299 | |
c553b3ca | 2300 | val = readl(PRCM_HOSTACCESS_REQ); |
3df57bcf MN |
2301 | if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ) |
2302 | goto unlock_and_return; | |
e0befb23 | 2303 | |
3df57bcf | 2304 | atomic_set(&ac_wake_req_state, 1); |
e0befb23 | 2305 | |
d6e3002e | 2306 | retry: |
c553b3ca | 2307 | writel((val | PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ), PRCM_HOSTACCESS_REQ); |
e0befb23 | 2308 | |
3df57bcf | 2309 | if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, |
d6e3002e | 2310 | msecs_to_jiffies(5000))) { |
57265bc1 | 2311 | pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n", |
d6e3002e MN |
2312 | __func__); |
2313 | goto unlock_and_return; | |
2314 | } | |
2315 | ||
2316 | /* | |
2317 | * The modem can generate an AC_WAKE_ACK, and then still go to sleep. | |
2318 | * As a workaround, we wait, and then check that the modem is indeed | |
2319 | * awake (in terms of the value of the PRCM_MOD_AWAKE_STATUS | |
2320 | * register, which may not be the whole truth). | |
2321 | */ | |
2322 | udelay(400); | |
2323 | status = (readl(PRCM_MOD_AWAKE_STATUS) & BITS(0, 2)); | |
2324 | if (status != (PRCM_MOD_AWAKE_STATUS_PRCM_MOD_AAPD_AWAKE | | |
2325 | PRCM_MOD_AWAKE_STATUS_PRCM_MOD_COREPD_AWAKE)) { | |
2326 | pr_err("prcmu: %s received ack, but modem not awake (0x%X).\n", | |
2327 | __func__, status); | |
2328 | udelay(1200); | |
2329 | writel(val, PRCM_HOSTACCESS_REQ); | |
2330 | if (wait_for_completion_timeout(&mb0_transfer.ac_wake_work, | |
2331 | msecs_to_jiffies(5000))) | |
2332 | goto retry; | |
57265bc1 | 2333 | pr_crit("prcmu: %s timed out (5 s) waiting for AC_SLEEP_ACK.\n", |
3df57bcf MN |
2334 | __func__); |
2335 | } | |
e0befb23 | 2336 | |
3df57bcf MN |
2337 | unlock_and_return: |
2338 | mutex_unlock(&mb0_transfer.ac_wake_lock); | |
e0befb23 MP |
2339 | } |
2340 | ||
2341 | /** | |
3df57bcf | 2342 | * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem |
e0befb23 | 2343 | */ |
3df57bcf | 2344 | void prcmu_ac_sleep_req() |
e0befb23 | 2345 | { |
3df57bcf MN |
2346 | u32 val; |
2347 | ||
2348 | mutex_lock(&mb0_transfer.ac_wake_lock); | |
2349 | ||
c553b3ca | 2350 | val = readl(PRCM_HOSTACCESS_REQ); |
3df57bcf MN |
2351 | if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)) |
2352 | goto unlock_and_return; | |
2353 | ||
2354 | writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ), | |
c553b3ca | 2355 | PRCM_HOSTACCESS_REQ); |
3df57bcf MN |
2356 | |
2357 | if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work, | |
d6e3002e | 2358 | msecs_to_jiffies(5000))) { |
57265bc1 | 2359 | pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n", |
3df57bcf MN |
2360 | __func__); |
2361 | } | |
2362 | ||
2363 | atomic_set(&ac_wake_req_state, 0); | |
2364 | ||
2365 | unlock_and_return: | |
2366 | mutex_unlock(&mb0_transfer.ac_wake_lock); | |
e0befb23 | 2367 | } |
e0befb23 | 2368 | |
73180f85 | 2369 | bool db8500_prcmu_is_ac_wake_requested(void) |
e0befb23 | 2370 | { |
3df57bcf | 2371 | return (atomic_read(&ac_wake_req_state) != 0); |
e0befb23 | 2372 | } |
e0befb23 MP |
2373 | |
2374 | /** | |
73180f85 | 2375 | * db8500_prcmu_system_reset - System reset |
e0befb23 | 2376 | * |
73180f85 | 2377 | * Saves the reset reason code and then sets the APE_SOFTRST register which |
3df57bcf | 2378 | * fires interrupt to fw |
e0befb23 | 2379 | */ |
73180f85 | 2380 | void db8500_prcmu_system_reset(u16 reset_code) |
e0befb23 | 2381 | { |
3df57bcf | 2382 | writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON)); |
c553b3ca | 2383 | writel(1, PRCM_APE_SOFTRST); |
e0befb23 | 2384 | } |
e0befb23 | 2385 | |
597045de SR |
2386 | /** |
2387 | * db8500_prcmu_get_reset_code - Retrieve SW reset reason code | |
2388 | * | |
2389 | * Retrieves the reset reason code stored by prcmu_system_reset() before | |
2390 | * last restart. | |
2391 | */ | |
2392 | u16 db8500_prcmu_get_reset_code(void) | |
2393 | { | |
2394 | return readw(tcdm_base + PRCM_SW_RST_REASON); | |
2395 | } | |
2396 | ||
e0befb23 | 2397 | /** |
0508901c | 2398 | * db8500_prcmu_reset_modem - ask the PRCMU to reset modem |
e0befb23 | 2399 | */ |
0508901c | 2400 | void db8500_prcmu_modem_reset(void) |
e0befb23 | 2401 | { |
3df57bcf MN |
2402 | mutex_lock(&mb1_transfer.lock); |
2403 | ||
c553b3ca | 2404 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) |
3df57bcf MN |
2405 | cpu_relax(); |
2406 | ||
2407 | writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1)); | |
c553b3ca | 2408 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
2409 | wait_for_completion(&mb1_transfer.work); |
2410 | ||
2411 | /* | |
2412 | * No need to check return from PRCMU as modem should go in reset state | |
2413 | * This state is already managed by upper layer | |
2414 | */ | |
2415 | ||
2416 | mutex_unlock(&mb1_transfer.lock); | |
e0befb23 | 2417 | } |
e0befb23 | 2418 | |
3df57bcf | 2419 | static void ack_dbb_wakeup(void) |
e0befb23 | 2420 | { |
3df57bcf MN |
2421 | unsigned long flags; |
2422 | ||
2423 | spin_lock_irqsave(&mb0_transfer.lock, flags); | |
2424 | ||
c553b3ca | 2425 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0)) |
3df57bcf MN |
2426 | cpu_relax(); |
2427 | ||
2428 | writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0)); | |
c553b3ca | 2429 | writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET); |
3df57bcf MN |
2430 | |
2431 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); | |
e0befb23 | 2432 | } |
e0befb23 | 2433 | |
3df57bcf | 2434 | static inline void print_unknown_header_warning(u8 n, u8 header) |
e0befb23 | 2435 | { |
3df57bcf MN |
2436 | pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n", |
2437 | header, n); | |
e0befb23 MP |
2438 | } |
2439 | ||
3df57bcf | 2440 | static bool read_mailbox_0(void) |
e3726fcf | 2441 | { |
3df57bcf MN |
2442 | bool r; |
2443 | u32 ev; | |
2444 | unsigned int n; | |
2445 | u8 header; | |
2446 | ||
2447 | header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0); | |
2448 | switch (header) { | |
2449 | case MB0H_WAKEUP_EXE: | |
2450 | case MB0H_WAKEUP_SLEEP: | |
2451 | if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1) | |
2452 | ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500); | |
2453 | else | |
2454 | ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500); | |
2455 | ||
2456 | if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK)) | |
2457 | complete(&mb0_transfer.ac_wake_work); | |
2458 | if (ev & WAKEUP_BIT_SYSCLK_OK) | |
2459 | complete(&mb3_transfer.sysclk_work); | |
2460 | ||
2461 | ev &= mb0_transfer.req.dbb_irqs; | |
2462 | ||
2463 | for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) { | |
2464 | if (ev & prcmu_irq_bit[n]) | |
2465 | generic_handle_irq(IRQ_PRCMU_BASE + n); | |
2466 | } | |
2467 | r = true; | |
2468 | break; | |
2469 | default: | |
2470 | print_unknown_header_warning(0, header); | |
2471 | r = false; | |
2472 | break; | |
2473 | } | |
c553b3ca | 2474 | writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR); |
3df57bcf | 2475 | return r; |
e3726fcf LW |
2476 | } |
2477 | ||
3df57bcf | 2478 | static bool read_mailbox_1(void) |
e3726fcf | 2479 | { |
3df57bcf MN |
2480 | mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1); |
2481 | mb1_transfer.ack.arm_opp = readb(tcdm_base + | |
2482 | PRCM_ACK_MB1_CURRENT_ARM_OPP); | |
2483 | mb1_transfer.ack.ape_opp = readb(tcdm_base + | |
2484 | PRCM_ACK_MB1_CURRENT_APE_OPP); | |
2485 | mb1_transfer.ack.ape_voltage_status = readb(tcdm_base + | |
2486 | PRCM_ACK_MB1_APE_VOLTAGE_STATUS); | |
c553b3ca | 2487 | writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR); |
e0befb23 | 2488 | complete(&mb1_transfer.work); |
3df57bcf | 2489 | return false; |
e3726fcf LW |
2490 | } |
2491 | ||
3df57bcf | 2492 | static bool read_mailbox_2(void) |
e3726fcf | 2493 | { |
3df57bcf | 2494 | mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS); |
c553b3ca | 2495 | writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR); |
3df57bcf MN |
2496 | complete(&mb2_transfer.work); |
2497 | return false; | |
e3726fcf LW |
2498 | } |
2499 | ||
3df57bcf | 2500 | static bool read_mailbox_3(void) |
e3726fcf | 2501 | { |
c553b3ca | 2502 | writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR); |
3df57bcf | 2503 | return false; |
e3726fcf LW |
2504 | } |
2505 | ||
3df57bcf | 2506 | static bool read_mailbox_4(void) |
e3726fcf | 2507 | { |
3df57bcf MN |
2508 | u8 header; |
2509 | bool do_complete = true; | |
2510 | ||
2511 | header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4); | |
2512 | switch (header) { | |
2513 | case MB4H_MEM_ST: | |
2514 | case MB4H_HOTDOG: | |
2515 | case MB4H_HOTMON: | |
2516 | case MB4H_HOT_PERIOD: | |
a592c2e2 MN |
2517 | case MB4H_A9WDOG_CONF: |
2518 | case MB4H_A9WDOG_EN: | |
2519 | case MB4H_A9WDOG_DIS: | |
2520 | case MB4H_A9WDOG_LOAD: | |
2521 | case MB4H_A9WDOG_KICK: | |
3df57bcf MN |
2522 | break; |
2523 | default: | |
2524 | print_unknown_header_warning(4, header); | |
2525 | do_complete = false; | |
2526 | break; | |
2527 | } | |
2528 | ||
c553b3ca | 2529 | writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR); |
3df57bcf MN |
2530 | |
2531 | if (do_complete) | |
2532 | complete(&mb4_transfer.work); | |
2533 | ||
2534 | return false; | |
e3726fcf LW |
2535 | } |
2536 | ||
3df57bcf | 2537 | static bool read_mailbox_5(void) |
e3726fcf | 2538 | { |
3df57bcf MN |
2539 | mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS); |
2540 | mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL); | |
c553b3ca | 2541 | writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR); |
e3726fcf | 2542 | complete(&mb5_transfer.work); |
3df57bcf | 2543 | return false; |
e3726fcf LW |
2544 | } |
2545 | ||
3df57bcf | 2546 | static bool read_mailbox_6(void) |
e3726fcf | 2547 | { |
c553b3ca | 2548 | writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR); |
3df57bcf | 2549 | return false; |
e3726fcf LW |
2550 | } |
2551 | ||
3df57bcf | 2552 | static bool read_mailbox_7(void) |
e3726fcf | 2553 | { |
c553b3ca | 2554 | writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR); |
3df57bcf | 2555 | return false; |
e3726fcf LW |
2556 | } |
2557 | ||
3df57bcf | 2558 | static bool (* const read_mailbox[NUM_MB])(void) = { |
e3726fcf LW |
2559 | read_mailbox_0, |
2560 | read_mailbox_1, | |
2561 | read_mailbox_2, | |
2562 | read_mailbox_3, | |
2563 | read_mailbox_4, | |
2564 | read_mailbox_5, | |
2565 | read_mailbox_6, | |
2566 | read_mailbox_7 | |
2567 | }; | |
2568 | ||
2569 | static irqreturn_t prcmu_irq_handler(int irq, void *data) | |
2570 | { | |
2571 | u32 bits; | |
2572 | u8 n; | |
3df57bcf | 2573 | irqreturn_t r; |
e3726fcf | 2574 | |
c553b3ca | 2575 | bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS); |
e3726fcf LW |
2576 | if (unlikely(!bits)) |
2577 | return IRQ_NONE; | |
2578 | ||
3df57bcf | 2579 | r = IRQ_HANDLED; |
e3726fcf LW |
2580 | for (n = 0; bits; n++) { |
2581 | if (bits & MBOX_BIT(n)) { | |
2582 | bits -= MBOX_BIT(n); | |
3df57bcf MN |
2583 | if (read_mailbox[n]()) |
2584 | r = IRQ_WAKE_THREAD; | |
e3726fcf LW |
2585 | } |
2586 | } | |
3df57bcf MN |
2587 | return r; |
2588 | } | |
2589 | ||
2590 | static irqreturn_t prcmu_irq_thread_fn(int irq, void *data) | |
2591 | { | |
2592 | ack_dbb_wakeup(); | |
e3726fcf LW |
2593 | return IRQ_HANDLED; |
2594 | } | |
2595 | ||
3df57bcf MN |
2596 | static void prcmu_mask_work(struct work_struct *work) |
2597 | { | |
2598 | unsigned long flags; | |
2599 | ||
2600 | spin_lock_irqsave(&mb0_transfer.lock, flags); | |
2601 | ||
2602 | config_wakeups(); | |
2603 | ||
2604 | spin_unlock_irqrestore(&mb0_transfer.lock, flags); | |
2605 | } | |
2606 | ||
2607 | static void prcmu_irq_mask(struct irq_data *d) | |
2608 | { | |
2609 | unsigned long flags; | |
2610 | ||
2611 | spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags); | |
2612 | ||
2613 | mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE]; | |
2614 | ||
2615 | spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags); | |
2616 | ||
2617 | if (d->irq != IRQ_PRCMU_CA_SLEEP) | |
2618 | schedule_work(&mb0_transfer.mask_work); | |
2619 | } | |
2620 | ||
2621 | static void prcmu_irq_unmask(struct irq_data *d) | |
2622 | { | |
2623 | unsigned long flags; | |
2624 | ||
2625 | spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags); | |
2626 | ||
2627 | mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE]; | |
2628 | ||
2629 | spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags); | |
2630 | ||
2631 | if (d->irq != IRQ_PRCMU_CA_SLEEP) | |
2632 | schedule_work(&mb0_transfer.mask_work); | |
2633 | } | |
2634 | ||
2635 | static void noop(struct irq_data *d) | |
2636 | { | |
2637 | } | |
2638 | ||
2639 | static struct irq_chip prcmu_irq_chip = { | |
2640 | .name = "prcmu", | |
2641 | .irq_disable = prcmu_irq_mask, | |
2642 | .irq_ack = noop, | |
2643 | .irq_mask = prcmu_irq_mask, | |
2644 | .irq_unmask = prcmu_irq_unmask, | |
2645 | }; | |
2646 | ||
b58d12fe MN |
2647 | static char *fw_project_name(u8 project) |
2648 | { | |
2649 | switch (project) { | |
2650 | case PRCMU_FW_PROJECT_U8500: | |
2651 | return "U8500"; | |
2652 | case PRCMU_FW_PROJECT_U8500_C2: | |
2653 | return "U8500 C2"; | |
2654 | case PRCMU_FW_PROJECT_U9500: | |
2655 | return "U9500"; | |
2656 | case PRCMU_FW_PROJECT_U9500_C2: | |
2657 | return "U9500 C2"; | |
2658 | default: | |
2659 | return "Unknown"; | |
2660 | } | |
2661 | } | |
2662 | ||
73180f85 | 2663 | void __init db8500_prcmu_early_init(void) |
fcbd458e | 2664 | { |
3df57bcf | 2665 | unsigned int i; |
3e2762c8 | 2666 | if (cpu_is_u8500v2()) { |
3df57bcf MN |
2667 | void *tcpm_base = ioremap_nocache(U8500_PRCMU_TCPM_BASE, SZ_4K); |
2668 | ||
2669 | if (tcpm_base != NULL) { | |
3e2762c8 | 2670 | u32 version; |
3df57bcf | 2671 | version = readl(tcpm_base + PRCMU_FW_VERSION_OFFSET); |
b58d12fe MN |
2672 | fw_info.version.project = version & 0xFF; |
2673 | fw_info.version.api_version = (version >> 8) & 0xFF; | |
2674 | fw_info.version.func_version = (version >> 16) & 0xFF; | |
2675 | fw_info.version.errata = (version >> 24) & 0xFF; | |
2676 | fw_info.valid = true; | |
2677 | pr_info("PRCMU firmware: %s, version %d.%d.%d\n", | |
2678 | fw_project_name(fw_info.version.project), | |
3df57bcf MN |
2679 | (version >> 8) & 0xFF, (version >> 16) & 0xFF, |
2680 | (version >> 24) & 0xFF); | |
2681 | iounmap(tcpm_base); | |
2682 | } | |
2683 | ||
fcbd458e MW |
2684 | tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE); |
2685 | } else { | |
2686 | pr_err("prcmu: Unsupported chip version\n"); | |
2687 | BUG(); | |
2688 | } | |
e0befb23 | 2689 | |
3df57bcf MN |
2690 | spin_lock_init(&mb0_transfer.lock); |
2691 | spin_lock_init(&mb0_transfer.dbb_irqs_lock); | |
2692 | mutex_init(&mb0_transfer.ac_wake_lock); | |
2693 | init_completion(&mb0_transfer.ac_wake_work); | |
e0befb23 MP |
2694 | mutex_init(&mb1_transfer.lock); |
2695 | init_completion(&mb1_transfer.work); | |
4d64d2e3 | 2696 | mb1_transfer.ape_opp = APE_NO_CHANGE; |
3df57bcf MN |
2697 | mutex_init(&mb2_transfer.lock); |
2698 | init_completion(&mb2_transfer.work); | |
2699 | spin_lock_init(&mb2_transfer.auto_pm_lock); | |
2700 | spin_lock_init(&mb3_transfer.lock); | |
2701 | mutex_init(&mb3_transfer.sysclk_lock); | |
2702 | init_completion(&mb3_transfer.sysclk_work); | |
2703 | mutex_init(&mb4_transfer.lock); | |
2704 | init_completion(&mb4_transfer.work); | |
e3726fcf LW |
2705 | mutex_init(&mb5_transfer.lock); |
2706 | init_completion(&mb5_transfer.work); | |
2707 | ||
3df57bcf MN |
2708 | INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work); |
2709 | ||
2710 | /* Initalize irqs. */ | |
2711 | for (i = 0; i < NUM_PRCMU_WAKEUPS; i++) { | |
2712 | unsigned int irq; | |
2713 | ||
2714 | irq = IRQ_PRCMU_BASE + i; | |
2715 | irq_set_chip_and_handler(irq, &prcmu_irq_chip, | |
2716 | handle_simple_irq); | |
2717 | set_irq_flags(irq, IRQF_VALID); | |
2718 | } | |
2719 | } | |
2720 | ||
0508901c | 2721 | static void __init init_prcm_registers(void) |
d65e12d7 MN |
2722 | { |
2723 | u32 val; | |
2724 | ||
2725 | val = readl(PRCM_A9PL_FORCE_CLKEN); | |
2726 | val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN | | |
2727 | PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN); | |
2728 | writel(val, (PRCM_A9PL_FORCE_CLKEN)); | |
2729 | } | |
2730 | ||
1032fbfd BJ |
2731 | /* |
2732 | * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC | |
2733 | */ | |
2734 | static struct regulator_consumer_supply db8500_vape_consumers[] = { | |
2735 | REGULATOR_SUPPLY("v-ape", NULL), | |
2736 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"), | |
2737 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"), | |
2738 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"), | |
2739 | REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"), | |
2740 | /* "v-mmc" changed to "vcore" in the mainline kernel */ | |
2741 | REGULATOR_SUPPLY("vcore", "sdi0"), | |
2742 | REGULATOR_SUPPLY("vcore", "sdi1"), | |
2743 | REGULATOR_SUPPLY("vcore", "sdi2"), | |
2744 | REGULATOR_SUPPLY("vcore", "sdi3"), | |
2745 | REGULATOR_SUPPLY("vcore", "sdi4"), | |
2746 | REGULATOR_SUPPLY("v-dma", "dma40.0"), | |
2747 | REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"), | |
2748 | /* "v-uart" changed to "vcore" in the mainline kernel */ | |
2749 | REGULATOR_SUPPLY("vcore", "uart0"), | |
2750 | REGULATOR_SUPPLY("vcore", "uart1"), | |
2751 | REGULATOR_SUPPLY("vcore", "uart2"), | |
2752 | REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"), | |
992b133a | 2753 | REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"), |
1032fbfd BJ |
2754 | }; |
2755 | ||
2756 | static struct regulator_consumer_supply db8500_vsmps2_consumers[] = { | |
1032fbfd BJ |
2757 | REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"), |
2758 | /* AV8100 regulator */ | |
2759 | REGULATOR_SUPPLY("hdmi_1v8", "0-0070"), | |
2760 | }; | |
2761 | ||
2762 | static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = { | |
992b133a | 2763 | REGULATOR_SUPPLY("vsupply", "b2r2_bus"), |
624e87c2 BJ |
2764 | REGULATOR_SUPPLY("vsupply", "mcde"), |
2765 | }; | |
2766 | ||
2767 | /* SVA MMDSP regulator switch */ | |
2768 | static struct regulator_consumer_supply db8500_svammdsp_consumers[] = { | |
2769 | REGULATOR_SUPPLY("sva-mmdsp", "cm_control"), | |
2770 | }; | |
2771 | ||
2772 | /* SVA pipe regulator switch */ | |
2773 | static struct regulator_consumer_supply db8500_svapipe_consumers[] = { | |
2774 | REGULATOR_SUPPLY("sva-pipe", "cm_control"), | |
2775 | }; | |
2776 | ||
2777 | /* SIA MMDSP regulator switch */ | |
2778 | static struct regulator_consumer_supply db8500_siammdsp_consumers[] = { | |
2779 | REGULATOR_SUPPLY("sia-mmdsp", "cm_control"), | |
2780 | }; | |
2781 | ||
2782 | /* SIA pipe regulator switch */ | |
2783 | static struct regulator_consumer_supply db8500_siapipe_consumers[] = { | |
2784 | REGULATOR_SUPPLY("sia-pipe", "cm_control"), | |
2785 | }; | |
2786 | ||
2787 | static struct regulator_consumer_supply db8500_sga_consumers[] = { | |
2788 | REGULATOR_SUPPLY("v-mali", NULL), | |
2789 | }; | |
2790 | ||
2791 | /* ESRAM1 and 2 regulator switch */ | |
2792 | static struct regulator_consumer_supply db8500_esram12_consumers[] = { | |
2793 | REGULATOR_SUPPLY("esram12", "cm_control"), | |
2794 | }; | |
2795 | ||
2796 | /* ESRAM3 and 4 regulator switch */ | |
2797 | static struct regulator_consumer_supply db8500_esram34_consumers[] = { | |
2798 | REGULATOR_SUPPLY("v-esram34", "mcde"), | |
2799 | REGULATOR_SUPPLY("esram34", "cm_control"), | |
992b133a | 2800 | REGULATOR_SUPPLY("lcla_esram", "dma40.0"), |
1032fbfd BJ |
2801 | }; |
2802 | ||
2803 | static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = { | |
2804 | [DB8500_REGULATOR_VAPE] = { | |
2805 | .constraints = { | |
2806 | .name = "db8500-vape", | |
2807 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2808 | }, | |
2809 | .consumer_supplies = db8500_vape_consumers, | |
2810 | .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers), | |
2811 | }, | |
2812 | [DB8500_REGULATOR_VARM] = { | |
2813 | .constraints = { | |
2814 | .name = "db8500-varm", | |
2815 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2816 | }, | |
2817 | }, | |
2818 | [DB8500_REGULATOR_VMODEM] = { | |
2819 | .constraints = { | |
2820 | .name = "db8500-vmodem", | |
2821 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2822 | }, | |
2823 | }, | |
2824 | [DB8500_REGULATOR_VPLL] = { | |
2825 | .constraints = { | |
2826 | .name = "db8500-vpll", | |
2827 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2828 | }, | |
2829 | }, | |
2830 | [DB8500_REGULATOR_VSMPS1] = { | |
2831 | .constraints = { | |
2832 | .name = "db8500-vsmps1", | |
2833 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2834 | }, | |
2835 | }, | |
2836 | [DB8500_REGULATOR_VSMPS2] = { | |
2837 | .constraints = { | |
2838 | .name = "db8500-vsmps2", | |
2839 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2840 | }, | |
2841 | .consumer_supplies = db8500_vsmps2_consumers, | |
2842 | .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers), | |
2843 | }, | |
2844 | [DB8500_REGULATOR_VSMPS3] = { | |
2845 | .constraints = { | |
2846 | .name = "db8500-vsmps3", | |
2847 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2848 | }, | |
2849 | }, | |
2850 | [DB8500_REGULATOR_VRF1] = { | |
2851 | .constraints = { | |
2852 | .name = "db8500-vrf1", | |
2853 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2854 | }, | |
2855 | }, | |
2856 | [DB8500_REGULATOR_SWITCH_SVAMMDSP] = { | |
992b133a | 2857 | /* dependency to u8500-vape is handled outside regulator framework */ |
1032fbfd BJ |
2858 | .constraints = { |
2859 | .name = "db8500-sva-mmdsp", | |
2860 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2861 | }, | |
624e87c2 BJ |
2862 | .consumer_supplies = db8500_svammdsp_consumers, |
2863 | .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers), | |
1032fbfd BJ |
2864 | }, |
2865 | [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = { | |
2866 | .constraints = { | |
2867 | /* "ret" means "retention" */ | |
2868 | .name = "db8500-sva-mmdsp-ret", | |
2869 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2870 | }, | |
2871 | }, | |
2872 | [DB8500_REGULATOR_SWITCH_SVAPIPE] = { | |
992b133a | 2873 | /* dependency to u8500-vape is handled outside regulator framework */ |
1032fbfd BJ |
2874 | .constraints = { |
2875 | .name = "db8500-sva-pipe", | |
2876 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2877 | }, | |
624e87c2 BJ |
2878 | .consumer_supplies = db8500_svapipe_consumers, |
2879 | .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers), | |
1032fbfd BJ |
2880 | }, |
2881 | [DB8500_REGULATOR_SWITCH_SIAMMDSP] = { | |
992b133a | 2882 | /* dependency to u8500-vape is handled outside regulator framework */ |
1032fbfd BJ |
2883 | .constraints = { |
2884 | .name = "db8500-sia-mmdsp", | |
2885 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2886 | }, | |
624e87c2 BJ |
2887 | .consumer_supplies = db8500_siammdsp_consumers, |
2888 | .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers), | |
1032fbfd BJ |
2889 | }, |
2890 | [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = { | |
2891 | .constraints = { | |
2892 | .name = "db8500-sia-mmdsp-ret", | |
2893 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2894 | }, | |
2895 | }, | |
2896 | [DB8500_REGULATOR_SWITCH_SIAPIPE] = { | |
992b133a | 2897 | /* dependency to u8500-vape is handled outside regulator framework */ |
1032fbfd BJ |
2898 | .constraints = { |
2899 | .name = "db8500-sia-pipe", | |
2900 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2901 | }, | |
624e87c2 BJ |
2902 | .consumer_supplies = db8500_siapipe_consumers, |
2903 | .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers), | |
1032fbfd BJ |
2904 | }, |
2905 | [DB8500_REGULATOR_SWITCH_SGA] = { | |
2906 | .supply_regulator = "db8500-vape", | |
2907 | .constraints = { | |
2908 | .name = "db8500-sga", | |
2909 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2910 | }, | |
624e87c2 BJ |
2911 | .consumer_supplies = db8500_sga_consumers, |
2912 | .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers), | |
2913 | ||
1032fbfd BJ |
2914 | }, |
2915 | [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = { | |
2916 | .supply_regulator = "db8500-vape", | |
2917 | .constraints = { | |
2918 | .name = "db8500-b2r2-mcde", | |
2919 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2920 | }, | |
2921 | .consumer_supplies = db8500_b2r2_mcde_consumers, | |
2922 | .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers), | |
2923 | }, | |
2924 | [DB8500_REGULATOR_SWITCH_ESRAM12] = { | |
992b133a BJ |
2925 | /* |
2926 | * esram12 is set in retention and supplied by Vsafe when Vape is off, | |
2927 | * no need to hold Vape | |
2928 | */ | |
1032fbfd BJ |
2929 | .constraints = { |
2930 | .name = "db8500-esram12", | |
2931 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2932 | }, | |
624e87c2 BJ |
2933 | .consumer_supplies = db8500_esram12_consumers, |
2934 | .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers), | |
1032fbfd BJ |
2935 | }, |
2936 | [DB8500_REGULATOR_SWITCH_ESRAM12RET] = { | |
2937 | .constraints = { | |
2938 | .name = "db8500-esram12-ret", | |
2939 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2940 | }, | |
2941 | }, | |
2942 | [DB8500_REGULATOR_SWITCH_ESRAM34] = { | |
992b133a BJ |
2943 | /* |
2944 | * esram34 is set in retention and supplied by Vsafe when Vape is off, | |
2945 | * no need to hold Vape | |
2946 | */ | |
1032fbfd BJ |
2947 | .constraints = { |
2948 | .name = "db8500-esram34", | |
2949 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2950 | }, | |
624e87c2 BJ |
2951 | .consumer_supplies = db8500_esram34_consumers, |
2952 | .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers), | |
1032fbfd BJ |
2953 | }, |
2954 | [DB8500_REGULATOR_SWITCH_ESRAM34RET] = { | |
2955 | .constraints = { | |
2956 | .name = "db8500-esram34-ret", | |
2957 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
2958 | }, | |
2959 | }, | |
2960 | }; | |
2961 | ||
3df57bcf MN |
2962 | static struct mfd_cell db8500_prcmu_devs[] = { |
2963 | { | |
2964 | .name = "db8500-prcmu-regulators", | |
1ed7891f MW |
2965 | .platform_data = &db8500_regulators, |
2966 | .pdata_size = sizeof(db8500_regulators), | |
3df57bcf MN |
2967 | }, |
2968 | { | |
2969 | .name = "cpufreq-u8500", | |
2970 | }, | |
2971 | }; | |
2972 | ||
2973 | /** | |
2974 | * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic | |
2975 | * | |
2976 | */ | |
2977 | static int __init db8500_prcmu_probe(struct platform_device *pdev) | |
2978 | { | |
2979 | int err = 0; | |
2980 | ||
2981 | if (ux500_is_svp()) | |
2982 | return -ENODEV; | |
2983 | ||
0508901c | 2984 | init_prcm_registers(); |
d65e12d7 | 2985 | |
e3726fcf | 2986 | /* Clean up the mailbox interrupts after pre-kernel code. */ |
c553b3ca | 2987 | writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR); |
3df57bcf MN |
2988 | |
2989 | err = request_threaded_irq(IRQ_DB8500_PRCMU1, prcmu_irq_handler, | |
2990 | prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL); | |
2991 | if (err < 0) { | |
2992 | pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n"); | |
2993 | err = -EBUSY; | |
2994 | goto no_irq_return; | |
2995 | } | |
2996 | ||
2997 | if (cpu_is_u8500v20_or_later()) | |
2998 | prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET); | |
2999 | ||
3000 | err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs, | |
3001 | ARRAY_SIZE(db8500_prcmu_devs), NULL, | |
3002 | 0); | |
e3726fcf | 3003 | |
3df57bcf MN |
3004 | if (err) |
3005 | pr_err("prcmu: Failed to add subdevices\n"); | |
3006 | else | |
3007 | pr_info("DB8500 PRCMU initialized\n"); | |
3008 | ||
3009 | no_irq_return: | |
3010 | return err; | |
3011 | } | |
3012 | ||
3013 | static struct platform_driver db8500_prcmu_driver = { | |
3014 | .driver = { | |
3015 | .name = "db8500-prcmu", | |
3016 | .owner = THIS_MODULE, | |
3017 | }, | |
3018 | }; | |
3019 | ||
3020 | static int __init db8500_prcmu_init(void) | |
3021 | { | |
3022 | return platform_driver_probe(&db8500_prcmu_driver, db8500_prcmu_probe); | |
e3726fcf LW |
3023 | } |
3024 | ||
3df57bcf MN |
3025 | arch_initcall(db8500_prcmu_init); |
3026 | ||
3027 | MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>"); | |
3028 | MODULE_DESCRIPTION("DB8500 PRCM Unit driver"); | |
3029 | MODULE_LICENSE("GPL v2"); |