projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| 8317797c LW |
1 | /* |
| 2 | * Copyright (C) STMicroelectronics 2009 | |
| 3 | * Copyright (C) ST-Ericsson SA 2010 | |
| 4 | * | |
| 5 | * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> | |
| 6 | * Author: Sundar Iyer <sundar.iyer@stericsson.com> | |
| 7 | * | |
| 8 | * License Terms: GNU General Public License v2 | |
| 9 | * | |
| 10 | * PRCM Unit registers | |
| 11 | */ | |
| 12 | ||
| 13 | #ifndef __MACH_PRCMU_REGS_H | |
| 14 | #define __MACH_PRCMU_REGS_H | |
| 15 | ||
| 16 | #include <mach/hardware.h> | |
| 17 | ||
| 18 | #define PRCM_ARM_PLLDIVPS (_PRCMU_BASE + 0x118) | |
| 19 | #define PRCM_ARM_PLLDIVPS_ARM_BRM_RATE 0x3f | |
| 20 | #define PRCM_ARM_PLLDIVPS_MAX_MASK 0xf | |
| 21 | ||
| 22 | #define PRCM_PLLARM_LOCKP (_PRCMU_BASE + 0x0a8) | |
| 23 | #define PRCM_PLLARM_LOCKP_PRCM_PLLARM_LOCKP3 0x2 | |
| 24 | ||
| 25 | #define PRCM_ARM_CHGCLKREQ (_PRCMU_BASE + 0x114) | |
| 26 | #define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ 0x1 | |
| 27 | ||
| 28 | #define PRCM_PLLARM_ENABLE (_PRCMU_BASE + 0x98) | |
| 29 | #define PRCM_PLLARM_ENABLE_PRCM_PLLARM_ENABLE 0x1 | |
| 30 | #define PRCM_PLLARM_ENABLE_PRCM_PLLARM_COUNTON 0x100 | |
| 31 | ||
| 32 | #define PRCM_ARMCLKFIX_MGT (_PRCMU_BASE + 0x0) | |
| 33 | #define PRCM_A9_RESETN_CLR (_PRCMU_BASE + 0x1f4) | |
| 34 | #define PRCM_A9_RESETN_SET (_PRCMU_BASE + 0x1f0) | |
| 35 | #define PRCM_ARM_LS_CLAMP (_PRCMU_BASE + 0x30c) | |
| 36 | #define PRCM_SRAM_A9 (_PRCMU_BASE + 0x308) | |
| 37 | ||
| 38 | /* ARM WFI Standby signal register */ | |
| 39 | #define PRCM_ARM_WFI_STANDBY (_PRCMU_BASE + 0x130) | |
| 40 | #define PRCM_IOCR (_PRCMU_BASE + 0x310) | |
| 41 | #define PRCM_IOCR_IOFORCE 0x1 | |
| 42 | ||
| 43 | /* CPU mailbox registers */ | |
| 44 | #define PRCM_MBOX_CPU_VAL (_PRCMU_BASE + 0x0fc) | |
| 45 | #define PRCM_MBOX_CPU_SET (_PRCMU_BASE + 0x100) | |
| 46 | #define PRCM_MBOX_CPU_CLR (_PRCMU_BASE + 0x104) | |
| 47 | ||
| 48 | /* Dual A9 core interrupt management unit registers */ | |
| 49 | #define PRCM_A9_MASK_REQ (_PRCMU_BASE + 0x328) | |
| 50 | #define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ 0x1 | |
| 51 | ||
| 52 | #define PRCM_A9_MASK_ACK (_PRCMU_BASE + 0x32c) | |
| 53 | #define PRCM_ARMITMSK31TO0 (_PRCMU_BASE + 0x11c) | |
| 54 | #define PRCM_ARMITMSK63TO32 (_PRCMU_BASE + 0x120) | |
| 55 | #define PRCM_ARMITMSK95TO64 (_PRCMU_BASE + 0x124) | |
| 56 | #define PRCM_ARMITMSK127TO96 (_PRCMU_BASE + 0x128) | |
| 57 | #define PRCM_POWER_STATE_VAL (_PRCMU_BASE + 0x25C) | |
| 58 | #define PRCM_ARMITVAL31TO0 (_PRCMU_BASE + 0x260) | |
| 59 | #define PRCM_ARMITVAL63TO32 (_PRCMU_BASE + 0x264) | |
| 60 | #define PRCM_ARMITVAL95TO64 (_PRCMU_BASE + 0x268) | |
| 61 | #define PRCM_ARMITVAL127TO96 (_PRCMU_BASE + 0x26C) | |
| 62 | ||
| 63 | #define PRCM_HOSTACCESS_REQ (_PRCMU_BASE + 0x334) | |
| 64 | #define ARM_WAKEUP_MODEM 0x1 | |
| 65 | ||
| 66 | #define PRCM_ARM_IT1_CLEAR (_PRCMU_BASE + 0x48C) | |
| 67 | #define PRCM_ARM_IT1_VAL (_PRCMU_BASE + 0x494) | |
| 68 | #define PRCM_HOLD_EVT (_PRCMU_BASE + 0x174) | |
| 69 | ||
| 70 | #define PRCM_ITSTATUS0 (_PRCMU_BASE + 0x148) | |
| 71 | #define PRCM_ITSTATUS1 (_PRCMU_BASE + 0x150) | |
| 72 | #define PRCM_ITSTATUS2 (_PRCMU_BASE + 0x158) | |
| 73 | #define PRCM_ITSTATUS3 (_PRCMU_BASE + 0x160) | |
| 74 | #define PRCM_ITSTATUS4 (_PRCMU_BASE + 0x168) | |
| 75 | #define PRCM_ITSTATUS5 (_PRCMU_BASE + 0x484) | |
| 76 | #define PRCM_ITCLEAR5 (_PRCMU_BASE + 0x488) | |
| 77 | #define PRCM_ARMIT_MASKXP70_IT (_PRCMU_BASE + 0x1018) | |
| 78 | ||
| 79 | /* System reset register */ | |
| 80 | #define PRCM_APE_SOFTRST (_PRCMU_BASE + 0x228) | |
| 81 | ||
| 82 | /* Level shifter and clamp control registers */ | |
| 83 | #define PRCM_MMIP_LS_CLAMP_SET (_PRCMU_BASE + 0x420) | |
| 84 | #define PRCM_MMIP_LS_CLAMP_CLR (_PRCMU_BASE + 0x424) | |
| 85 | ||
| 86 | /* PRCMU clock/PLL/reset registers */ | |
| 87 | #define PRCM_PLLDSI_FREQ (_PRCMU_BASE + 0x500) | |
| 88 | #define PRCM_PLLDSI_ENABLE (_PRCMU_BASE + 0x504) | |
| 89 | #define PRCM_PLLDSI_LOCKP (_PRCMU_BASE + 0x508) | |
| 90 | #define PRCM_LCDCLK_MGT (_PRCMU_BASE + 0x044) | |
| 91 | #define PRCM_MCDECLK_MGT (_PRCMU_BASE + 0x064) | |
| 92 | #define PRCM_HDMICLK_MGT (_PRCMU_BASE + 0x058) | |
| 93 | #define PRCM_TVCLK_MGT (_PRCMU_BASE + 0x07c) | |
| 94 | #define PRCM_DSI_PLLOUT_SEL (_PRCMU_BASE + 0x530) | |
| 95 | #define PRCM_DSITVCLK_DIV (_PRCMU_BASE + 0x52C) | |
| 96 | #define PRCM_PLLDSI_LOCKP (_PRCMU_BASE + 0x508) | |
| 97 | #define PRCM_APE_RESETN_SET (_PRCMU_BASE + 0x1E4) | |
| 98 | #define PRCM_APE_RESETN_CLR (_PRCMU_BASE + 0x1E8) | |
| 99 | #define PRCM_CLKOCR (_PRCMU_BASE + 0x1CC) | |
| 100 | ||
| 101 | /* ePOD and memory power signal control registers */ | |
| 102 | #define PRCM_EPOD_C_SET (_PRCMU_BASE + 0x410) | |
| 103 | #define PRCM_SRAM_LS_SLEEP (_PRCMU_BASE + 0x304) | |
| 104 | ||
| 105 | /* Debug power control unit registers */ | |
| 106 | #define PRCM_POWER_STATE_SET (_PRCMU_BASE + 0x254) | |
| 107 | ||
| 108 | /* Miscellaneous unit registers */ | |
| 109 | #define PRCM_DSI_SW_RESET (_PRCMU_BASE + 0x324) | |
| 110 | #define PRCM_GPIOCR (_PRCMU_BASE + 0x138) | |
| 111 | #define PRCM_GPIOCR_DBG_STM_MOD_CMD1 0x800 | |
| 112 | #define PRCM_GPIOCR_DBG_UARTMOD_CMD0 0x1 | |
| 113 | ||
| 114 | ||
| 115 | #endif /* __MACH_PRCMU__REGS_H */ |