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7ec94453 A |
1 | /* |
2 | * EMIF driver | |
3 | * | |
4 | * Copyright (C) 2012 Texas Instruments, Inc. | |
5 | * | |
6 | * Aneesh V <aneesh@ti.com> | |
7 | * Santosh Shilimkar <santosh.shilimkar@ti.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/reboot.h> | |
15 | #include <linux/platform_data/emif_plat.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/device.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/slab.h> | |
21 | #include <linux/seq_file.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/list.h> | |
a93de288 | 24 | #include <linux/spinlock.h> |
7ec94453 A |
25 | #include <memory/jedec_ddr.h> |
26 | #include "emif.h" | |
27 | ||
28 | /** | |
29 | * struct emif_data - Per device static data for driver's use | |
30 | * @duplicate: Whether the DDR devices attached to this EMIF | |
31 | * instance are exactly same as that on EMIF1. In | |
32 | * this case we can save some memory and processing | |
33 | * @temperature_level: Maximum temperature of LPDDR2 devices attached | |
34 | * to this EMIF - read from MR4 register. If there | |
35 | * are two devices attached to this EMIF, this | |
36 | * value is the maximum of the two temperature | |
37 | * levels. | |
38 | * @node: node in the device list | |
39 | * @base: base address of memory-mapped IO registers. | |
40 | * @dev: device pointer. | |
a93de288 A |
41 | * @addressing table with addressing information from the spec |
42 | * @regs_cache: An array of 'struct emif_regs' that stores | |
43 | * calculated register values for different | |
44 | * frequencies, to avoid re-calculating them on | |
45 | * each DVFS transition. | |
46 | * @curr_regs: The set of register values used in the last | |
47 | * frequency change (i.e. corresponding to the | |
48 | * frequency in effect at the moment) | |
7ec94453 A |
49 | * @plat_data: Pointer to saved platform data. |
50 | */ | |
51 | struct emif_data { | |
52 | u8 duplicate; | |
53 | u8 temperature_level; | |
a93de288 | 54 | u8 lpmode; |
7ec94453 | 55 | struct list_head node; |
a93de288 | 56 | unsigned long irq_state; |
7ec94453 A |
57 | void __iomem *base; |
58 | struct device *dev; | |
a93de288 A |
59 | const struct lpddr2_addressing *addressing; |
60 | struct emif_regs *regs_cache[EMIF_MAX_NUM_FREQUENCIES]; | |
61 | struct emif_regs *curr_regs; | |
7ec94453 A |
62 | struct emif_platform_data *plat_data; |
63 | }; | |
64 | ||
65 | static struct emif_data *emif1; | |
a93de288 A |
66 | static spinlock_t emif_lock; |
67 | static unsigned long irq_state; | |
68 | static u32 t_ck; /* DDR clock period in ps */ | |
7ec94453 A |
69 | static LIST_HEAD(device_list); |
70 | ||
a93de288 A |
71 | /* |
72 | * Calculate the period of DDR clock from frequency value | |
73 | */ | |
74 | static void set_ddr_clk_period(u32 freq) | |
75 | { | |
76 | /* Divide 10^12 by frequency to get period in ps */ | |
77 | t_ck = (u32)DIV_ROUND_UP_ULL(1000000000000ull, freq); | |
78 | } | |
79 | ||
80 | /* | |
81 | * Get the CL from SDRAM_CONFIG register | |
82 | */ | |
83 | static u32 get_cl(struct emif_data *emif) | |
84 | { | |
85 | u32 cl; | |
86 | void __iomem *base = emif->base; | |
87 | ||
88 | cl = (readl(base + EMIF_SDRAM_CONFIG) & CL_MASK) >> CL_SHIFT; | |
89 | ||
90 | return cl; | |
91 | } | |
92 | ||
93 | static void set_lpmode(struct emif_data *emif, u8 lpmode) | |
94 | { | |
95 | u32 temp; | |
96 | void __iomem *base = emif->base; | |
97 | ||
98 | temp = readl(base + EMIF_POWER_MANAGEMENT_CONTROL); | |
99 | temp &= ~LP_MODE_MASK; | |
100 | temp |= (lpmode << LP_MODE_SHIFT); | |
101 | writel(temp, base + EMIF_POWER_MANAGEMENT_CONTROL); | |
102 | } | |
103 | ||
104 | static void do_freq_update(void) | |
105 | { | |
106 | struct emif_data *emif; | |
107 | ||
108 | /* | |
109 | * Workaround for errata i728: Disable LPMODE during FREQ_UPDATE | |
110 | * | |
111 | * i728 DESCRIPTION: | |
112 | * The EMIF automatically puts the SDRAM into self-refresh mode | |
113 | * after the EMIF has not performed accesses during | |
114 | * EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM number of DDR clock cycles | |
115 | * and the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set | |
116 | * to 0x2. If during a small window the following three events | |
117 | * occur: | |
118 | * - The SR_TIMING counter expires | |
119 | * - And frequency change is requested | |
120 | * - And OCP access is requested | |
121 | * Then it causes instable clock on the DDR interface. | |
122 | * | |
123 | * WORKAROUND | |
124 | * To avoid the occurrence of the three events, the workaround | |
125 | * is to disable the self-refresh when requesting a frequency | |
126 | * change. Before requesting a frequency change the software must | |
127 | * program EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x0. When the | |
128 | * frequency change has been done, the software can reprogram | |
129 | * EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x2 | |
130 | */ | |
131 | list_for_each_entry(emif, &device_list, node) { | |
132 | if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH) | |
133 | set_lpmode(emif, EMIF_LP_MODE_DISABLE); | |
134 | } | |
135 | ||
136 | /* | |
137 | * TODO: Do FREQ_UPDATE here when an API | |
138 | * is available for this as part of the new | |
139 | * clock framework | |
140 | */ | |
141 | ||
142 | list_for_each_entry(emif, &device_list, node) { | |
143 | if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH) | |
144 | set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH); | |
145 | } | |
146 | } | |
147 | ||
148 | /* Find addressing table entry based on the device's type and density */ | |
149 | static const struct lpddr2_addressing *get_addressing_table( | |
150 | const struct ddr_device_info *device_info) | |
151 | { | |
152 | u32 index, type, density; | |
153 | ||
154 | type = device_info->type; | |
155 | density = device_info->density; | |
156 | ||
157 | switch (type) { | |
158 | case DDR_TYPE_LPDDR2_S4: | |
159 | index = density - 1; | |
160 | break; | |
161 | case DDR_TYPE_LPDDR2_S2: | |
162 | switch (density) { | |
163 | case DDR_DENSITY_1Gb: | |
164 | case DDR_DENSITY_2Gb: | |
165 | index = density + 3; | |
166 | break; | |
167 | default: | |
168 | index = density - 1; | |
169 | } | |
170 | break; | |
171 | default: | |
172 | return NULL; | |
173 | } | |
174 | ||
175 | return &lpddr2_jedec_addressing_table[index]; | |
176 | } | |
177 | ||
178 | /* | |
179 | * Find the the right timing table from the array of timing | |
180 | * tables of the device using DDR clock frequency | |
181 | */ | |
182 | static const struct lpddr2_timings *get_timings_table(struct emif_data *emif, | |
183 | u32 freq) | |
184 | { | |
185 | u32 i, min, max, freq_nearest; | |
186 | const struct lpddr2_timings *timings = NULL; | |
187 | const struct lpddr2_timings *timings_arr = emif->plat_data->timings; | |
188 | struct device *dev = emif->dev; | |
189 | ||
190 | /* Start with a very high frequency - 1GHz */ | |
191 | freq_nearest = 1000000000; | |
192 | ||
193 | /* | |
194 | * Find the timings table such that: | |
195 | * 1. the frequency range covers the required frequency(safe) AND | |
196 | * 2. the max_freq is closest to the required frequency(optimal) | |
197 | */ | |
198 | for (i = 0; i < emif->plat_data->timings_arr_size; i++) { | |
199 | max = timings_arr[i].max_freq; | |
200 | min = timings_arr[i].min_freq; | |
201 | if ((freq >= min) && (freq <= max) && (max < freq_nearest)) { | |
202 | freq_nearest = max; | |
203 | timings = &timings_arr[i]; | |
204 | } | |
205 | } | |
206 | ||
207 | if (!timings) | |
208 | dev_err(dev, "%s: couldn't find timings for - %dHz\n", | |
209 | __func__, freq); | |
210 | ||
211 | dev_dbg(dev, "%s: timings table: freq %d, speed bin freq %d\n", | |
212 | __func__, freq, freq_nearest); | |
213 | ||
214 | return timings; | |
215 | } | |
216 | ||
217 | static u32 get_sdram_ref_ctrl_shdw(u32 freq, | |
218 | const struct lpddr2_addressing *addressing) | |
219 | { | |
220 | u32 ref_ctrl_shdw = 0, val = 0, freq_khz, t_refi; | |
221 | ||
222 | /* Scale down frequency and t_refi to avoid overflow */ | |
223 | freq_khz = freq / 1000; | |
224 | t_refi = addressing->tREFI_ns / 100; | |
225 | ||
226 | /* | |
227 | * refresh rate to be set is 'tREFI(in us) * freq in MHz | |
228 | * division by 10000 to account for change in units | |
229 | */ | |
230 | val = t_refi * freq_khz / 10000; | |
231 | ref_ctrl_shdw |= val << REFRESH_RATE_SHIFT; | |
232 | ||
233 | return ref_ctrl_shdw; | |
234 | } | |
235 | ||
236 | static u32 get_sdram_tim_1_shdw(const struct lpddr2_timings *timings, | |
237 | const struct lpddr2_min_tck *min_tck, | |
238 | const struct lpddr2_addressing *addressing) | |
239 | { | |
240 | u32 tim1 = 0, val = 0; | |
241 | ||
242 | val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1; | |
243 | tim1 |= val << T_WTR_SHIFT; | |
244 | ||
245 | if (addressing->num_banks == B8) | |
246 | val = DIV_ROUND_UP(timings->tFAW, t_ck*4); | |
247 | else | |
248 | val = max(min_tck->tRRD, DIV_ROUND_UP(timings->tRRD, t_ck)); | |
249 | tim1 |= (val - 1) << T_RRD_SHIFT; | |
250 | ||
251 | val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab, t_ck) - 1; | |
252 | tim1 |= val << T_RC_SHIFT; | |
253 | ||
254 | val = max(min_tck->tRASmin, DIV_ROUND_UP(timings->tRAS_min, t_ck)); | |
255 | tim1 |= (val - 1) << T_RAS_SHIFT; | |
256 | ||
257 | val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1; | |
258 | tim1 |= val << T_WR_SHIFT; | |
259 | ||
260 | val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD, t_ck)) - 1; | |
261 | tim1 |= val << T_RCD_SHIFT; | |
262 | ||
263 | val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab, t_ck)) - 1; | |
264 | tim1 |= val << T_RP_SHIFT; | |
265 | ||
266 | return tim1; | |
267 | } | |
268 | ||
269 | static u32 get_sdram_tim_1_shdw_derated(const struct lpddr2_timings *timings, | |
270 | const struct lpddr2_min_tck *min_tck, | |
271 | const struct lpddr2_addressing *addressing) | |
272 | { | |
273 | u32 tim1 = 0, val = 0; | |
274 | ||
275 | val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1; | |
276 | tim1 = val << T_WTR_SHIFT; | |
277 | ||
278 | /* | |
279 | * tFAW is approximately 4 times tRRD. So add 1875*4 = 7500ps | |
280 | * to tFAW for de-rating | |
281 | */ | |
282 | if (addressing->num_banks == B8) { | |
283 | val = DIV_ROUND_UP(timings->tFAW + 7500, 4 * t_ck) - 1; | |
284 | } else { | |
285 | val = DIV_ROUND_UP(timings->tRRD + 1875, t_ck); | |
286 | val = max(min_tck->tRRD, val) - 1; | |
287 | } | |
288 | tim1 |= val << T_RRD_SHIFT; | |
289 | ||
290 | val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab + 1875, t_ck); | |
291 | tim1 |= (val - 1) << T_RC_SHIFT; | |
292 | ||
293 | val = DIV_ROUND_UP(timings->tRAS_min + 1875, t_ck); | |
294 | val = max(min_tck->tRASmin, val) - 1; | |
295 | tim1 |= val << T_RAS_SHIFT; | |
296 | ||
297 | val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1; | |
298 | tim1 |= val << T_WR_SHIFT; | |
299 | ||
300 | val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD + 1875, t_ck)); | |
301 | tim1 |= (val - 1) << T_RCD_SHIFT; | |
302 | ||
303 | val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab + 1875, t_ck)); | |
304 | tim1 |= (val - 1) << T_RP_SHIFT; | |
305 | ||
306 | return tim1; | |
307 | } | |
308 | ||
309 | static u32 get_sdram_tim_2_shdw(const struct lpddr2_timings *timings, | |
310 | const struct lpddr2_min_tck *min_tck, | |
311 | const struct lpddr2_addressing *addressing, | |
312 | u32 type) | |
313 | { | |
314 | u32 tim2 = 0, val = 0; | |
315 | ||
316 | val = min_tck->tCKE - 1; | |
317 | tim2 |= val << T_CKE_SHIFT; | |
318 | ||
319 | val = max(min_tck->tRTP, DIV_ROUND_UP(timings->tRTP, t_ck)) - 1; | |
320 | tim2 |= val << T_RTP_SHIFT; | |
321 | ||
322 | /* tXSNR = tRFCab_ps + 10 ns(tRFCab_ps for LPDDR2). */ | |
323 | val = DIV_ROUND_UP(addressing->tRFCab_ps + 10000, t_ck) - 1; | |
324 | tim2 |= val << T_XSNR_SHIFT; | |
325 | ||
326 | /* XSRD same as XSNR for LPDDR2 */ | |
327 | tim2 |= val << T_XSRD_SHIFT; | |
328 | ||
329 | val = max(min_tck->tXP, DIV_ROUND_UP(timings->tXP, t_ck)) - 1; | |
330 | tim2 |= val << T_XP_SHIFT; | |
331 | ||
332 | return tim2; | |
333 | } | |
334 | ||
335 | static u32 get_sdram_tim_3_shdw(const struct lpddr2_timings *timings, | |
336 | const struct lpddr2_min_tck *min_tck, | |
337 | const struct lpddr2_addressing *addressing, | |
338 | u32 type, u32 ip_rev, u32 derated) | |
339 | { | |
340 | u32 tim3 = 0, val = 0, t_dqsck; | |
341 | ||
342 | val = timings->tRAS_max_ns / addressing->tREFI_ns - 1; | |
343 | val = val > 0xF ? 0xF : val; | |
344 | tim3 |= val << T_RAS_MAX_SHIFT; | |
345 | ||
346 | val = DIV_ROUND_UP(addressing->tRFCab_ps, t_ck) - 1; | |
347 | tim3 |= val << T_RFC_SHIFT; | |
348 | ||
349 | t_dqsck = (derated == EMIF_DERATED_TIMINGS) ? | |
350 | timings->tDQSCK_max_derated : timings->tDQSCK_max; | |
351 | if (ip_rev == EMIF_4D5) | |
352 | val = DIV_ROUND_UP(t_dqsck + 1000, t_ck) - 1; | |
353 | else | |
354 | val = DIV_ROUND_UP(t_dqsck, t_ck) - 1; | |
355 | ||
356 | tim3 |= val << T_TDQSCKMAX_SHIFT; | |
357 | ||
358 | val = DIV_ROUND_UP(timings->tZQCS, t_ck) - 1; | |
359 | tim3 |= val << ZQ_ZQCS_SHIFT; | |
360 | ||
361 | val = DIV_ROUND_UP(timings->tCKESR, t_ck); | |
362 | val = max(min_tck->tCKESR, val) - 1; | |
363 | tim3 |= val << T_CKESR_SHIFT; | |
364 | ||
365 | if (ip_rev == EMIF_4D5) { | |
366 | tim3 |= (EMIF_T_CSTA - 1) << T_CSTA_SHIFT; | |
367 | ||
368 | val = DIV_ROUND_UP(EMIF_T_PDLL_UL, 128) - 1; | |
369 | tim3 |= val << T_PDLL_UL_SHIFT; | |
370 | } | |
371 | ||
372 | return tim3; | |
373 | } | |
374 | ||
375 | static u32 get_read_idle_ctrl_shdw(u8 volt_ramp) | |
376 | { | |
377 | u32 idle = 0, val = 0; | |
378 | ||
379 | /* | |
380 | * Maximum value in normal conditions and increased frequency | |
381 | * when voltage is ramping | |
382 | */ | |
383 | if (volt_ramp) | |
384 | val = READ_IDLE_INTERVAL_DVFS / t_ck / 64 - 1; | |
385 | else | |
386 | val = 0x1FF; | |
387 | ||
388 | /* | |
389 | * READ_IDLE_CTRL register in EMIF4D has same offset and fields | |
390 | * as DLL_CALIB_CTRL in EMIF4D5, so use the same shifts | |
391 | */ | |
392 | idle |= val << DLL_CALIB_INTERVAL_SHIFT; | |
393 | idle |= EMIF_READ_IDLE_LEN_VAL << ACK_WAIT_SHIFT; | |
394 | ||
395 | return idle; | |
396 | } | |
397 | ||
398 | static u32 get_dll_calib_ctrl_shdw(u8 volt_ramp) | |
399 | { | |
400 | u32 calib = 0, val = 0; | |
401 | ||
402 | if (volt_ramp == DDR_VOLTAGE_RAMPING) | |
403 | val = DLL_CALIB_INTERVAL_DVFS / t_ck / 16 - 1; | |
404 | else | |
405 | val = 0; /* Disabled when voltage is stable */ | |
406 | ||
407 | calib |= val << DLL_CALIB_INTERVAL_SHIFT; | |
408 | calib |= DLL_CALIB_ACK_WAIT_VAL << ACK_WAIT_SHIFT; | |
409 | ||
410 | return calib; | |
411 | } | |
412 | ||
413 | static u32 get_ddr_phy_ctrl_1_attilaphy_4d(const struct lpddr2_timings *timings, | |
414 | u32 freq, u8 RL) | |
415 | { | |
416 | u32 phy = EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY, val = 0; | |
417 | ||
418 | val = RL + DIV_ROUND_UP(timings->tDQSCK_max, t_ck) - 1; | |
419 | phy |= val << READ_LATENCY_SHIFT_4D; | |
420 | ||
421 | if (freq <= 100000000) | |
422 | val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY; | |
423 | else if (freq <= 200000000) | |
424 | val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY; | |
425 | else | |
426 | val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY; | |
427 | ||
428 | phy |= val << DLL_SLAVE_DLY_CTRL_SHIFT_4D; | |
429 | ||
430 | return phy; | |
431 | } | |
432 | ||
433 | static u32 get_phy_ctrl_1_intelliphy_4d5(u32 freq, u8 cl) | |
434 | { | |
435 | u32 phy = EMIF_DDR_PHY_CTRL_1_BASE_VAL_INTELLIPHY, half_delay; | |
436 | ||
437 | /* | |
438 | * DLL operates at 266 MHz. If DDR frequency is near 266 MHz, | |
439 | * half-delay is not needed else set half-delay | |
440 | */ | |
441 | if (freq >= 265000000 && freq < 267000000) | |
442 | half_delay = 0; | |
443 | else | |
444 | half_delay = 1; | |
445 | ||
446 | phy |= half_delay << DLL_HALF_DELAY_SHIFT_4D5; | |
447 | phy |= ((cl + DIV_ROUND_UP(EMIF_PHY_TOTAL_READ_LATENCY_INTELLIPHY_PS, | |
448 | t_ck) - 1) << READ_LATENCY_SHIFT_4D5); | |
449 | ||
450 | return phy; | |
451 | } | |
452 | ||
453 | static u32 get_ext_phy_ctrl_2_intelliphy_4d5(void) | |
454 | { | |
455 | u32 fifo_we_slave_ratio; | |
456 | ||
457 | fifo_we_slave_ratio = DIV_ROUND_CLOSEST( | |
458 | EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck); | |
459 | ||
460 | return fifo_we_slave_ratio | fifo_we_slave_ratio << 11 | | |
461 | fifo_we_slave_ratio << 22; | |
462 | } | |
463 | ||
464 | static u32 get_ext_phy_ctrl_3_intelliphy_4d5(void) | |
465 | { | |
466 | u32 fifo_we_slave_ratio; | |
467 | ||
468 | fifo_we_slave_ratio = DIV_ROUND_CLOSEST( | |
469 | EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck); | |
470 | ||
471 | return fifo_we_slave_ratio >> 10 | fifo_we_slave_ratio << 1 | | |
472 | fifo_we_slave_ratio << 12 | fifo_we_slave_ratio << 23; | |
473 | } | |
474 | ||
475 | static u32 get_ext_phy_ctrl_4_intelliphy_4d5(void) | |
476 | { | |
477 | u32 fifo_we_slave_ratio; | |
478 | ||
479 | fifo_we_slave_ratio = DIV_ROUND_CLOSEST( | |
480 | EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck); | |
481 | ||
482 | return fifo_we_slave_ratio >> 9 | fifo_we_slave_ratio << 2 | | |
483 | fifo_we_slave_ratio << 13; | |
484 | } | |
485 | ||
486 | static u32 get_pwr_mgmt_ctrl(u32 freq, struct emif_data *emif, u32 ip_rev) | |
487 | { | |
488 | u32 pwr_mgmt_ctrl = 0, timeout; | |
489 | u32 lpmode = EMIF_LP_MODE_SELF_REFRESH; | |
490 | u32 timeout_perf = EMIF_LP_MODE_TIMEOUT_PERFORMANCE; | |
491 | u32 timeout_pwr = EMIF_LP_MODE_TIMEOUT_POWER; | |
492 | u32 freq_threshold = EMIF_LP_MODE_FREQ_THRESHOLD; | |
493 | ||
494 | struct emif_custom_configs *cust_cfgs = emif->plat_data->custom_configs; | |
495 | ||
496 | if (cust_cfgs && (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE)) { | |
497 | lpmode = cust_cfgs->lpmode; | |
498 | timeout_perf = cust_cfgs->lpmode_timeout_performance; | |
499 | timeout_pwr = cust_cfgs->lpmode_timeout_power; | |
500 | freq_threshold = cust_cfgs->lpmode_freq_threshold; | |
501 | } | |
502 | ||
503 | /* Timeout based on DDR frequency */ | |
504 | timeout = freq >= freq_threshold ? timeout_perf : timeout_pwr; | |
505 | ||
506 | /* The value to be set in register is "log2(timeout) - 3" */ | |
507 | if (timeout < 16) { | |
508 | timeout = 0; | |
509 | } else { | |
510 | timeout = __fls(timeout) - 3; | |
511 | if (timeout & (timeout - 1)) | |
512 | timeout++; | |
513 | } | |
514 | ||
515 | switch (lpmode) { | |
516 | case EMIF_LP_MODE_CLOCK_STOP: | |
517 | pwr_mgmt_ctrl = (timeout << CS_TIM_SHIFT) | | |
518 | SR_TIM_MASK | PD_TIM_MASK; | |
519 | break; | |
520 | case EMIF_LP_MODE_SELF_REFRESH: | |
521 | /* Workaround for errata i735 */ | |
522 | if (timeout < 6) | |
523 | timeout = 6; | |
524 | ||
525 | pwr_mgmt_ctrl = (timeout << SR_TIM_SHIFT) | | |
526 | CS_TIM_MASK | PD_TIM_MASK; | |
527 | break; | |
528 | case EMIF_LP_MODE_PWR_DN: | |
529 | pwr_mgmt_ctrl = (timeout << PD_TIM_SHIFT) | | |
530 | CS_TIM_MASK | SR_TIM_MASK; | |
531 | break; | |
532 | case EMIF_LP_MODE_DISABLE: | |
533 | default: | |
534 | pwr_mgmt_ctrl = CS_TIM_MASK | | |
535 | PD_TIM_MASK | SR_TIM_MASK; | |
536 | } | |
537 | ||
538 | /* No CS_TIM in EMIF_4D5 */ | |
539 | if (ip_rev == EMIF_4D5) | |
540 | pwr_mgmt_ctrl &= ~CS_TIM_MASK; | |
541 | ||
542 | pwr_mgmt_ctrl |= lpmode << LP_MODE_SHIFT; | |
543 | ||
544 | return pwr_mgmt_ctrl; | |
545 | } | |
546 | ||
547 | /* | |
548 | * Program EMIF shadow registers that are not dependent on temperature | |
549 | * or voltage | |
550 | */ | |
551 | static void setup_registers(struct emif_data *emif, struct emif_regs *regs) | |
552 | { | |
553 | void __iomem *base = emif->base; | |
554 | ||
555 | writel(regs->sdram_tim2_shdw, base + EMIF_SDRAM_TIMING_2_SHDW); | |
556 | writel(regs->phy_ctrl_1_shdw, base + EMIF_DDR_PHY_CTRL_1_SHDW); | |
557 | ||
558 | /* Settings specific for EMIF4D5 */ | |
559 | if (emif->plat_data->ip_rev != EMIF_4D5) | |
560 | return; | |
561 | writel(regs->ext_phy_ctrl_2_shdw, base + EMIF_EXT_PHY_CTRL_2_SHDW); | |
562 | writel(regs->ext_phy_ctrl_3_shdw, base + EMIF_EXT_PHY_CTRL_3_SHDW); | |
563 | writel(regs->ext_phy_ctrl_4_shdw, base + EMIF_EXT_PHY_CTRL_4_SHDW); | |
564 | } | |
565 | ||
566 | /* | |
567 | * When voltage ramps dll calibration and forced read idle should | |
568 | * happen more often | |
569 | */ | |
570 | static void setup_volt_sensitive_regs(struct emif_data *emif, | |
571 | struct emif_regs *regs, u32 volt_state) | |
572 | { | |
573 | u32 calib_ctrl; | |
574 | void __iomem *base = emif->base; | |
575 | ||
576 | /* | |
577 | * EMIF_READ_IDLE_CTRL in EMIF4D refers to the same register as | |
578 | * EMIF_DLL_CALIB_CTRL in EMIF4D5 and dll_calib_ctrl_shadow_* | |
579 | * is an alias of the respective read_idle_ctrl_shdw_* (members of | |
580 | * a union). So, the below code takes care of both cases | |
581 | */ | |
582 | if (volt_state == DDR_VOLTAGE_RAMPING) | |
583 | calib_ctrl = regs->dll_calib_ctrl_shdw_volt_ramp; | |
584 | else | |
585 | calib_ctrl = regs->dll_calib_ctrl_shdw_normal; | |
586 | ||
587 | writel(calib_ctrl, base + EMIF_DLL_CALIB_CTRL_SHDW); | |
588 | } | |
589 | ||
590 | /* | |
591 | * setup_temperature_sensitive_regs() - set the timings for temperature | |
592 | * sensitive registers. This happens once at initialisation time based | |
593 | * on the temperature at boot time and subsequently based on the temperature | |
594 | * alert interrupt. Temperature alert can happen when the temperature | |
595 | * increases or drops. So this function can have the effect of either | |
596 | * derating the timings or going back to nominal values. | |
597 | */ | |
598 | static void setup_temperature_sensitive_regs(struct emif_data *emif, | |
599 | struct emif_regs *regs) | |
600 | { | |
601 | u32 tim1, tim3, ref_ctrl, type; | |
602 | void __iomem *base = emif->base; | |
603 | u32 temperature; | |
604 | ||
605 | type = emif->plat_data->device_info->type; | |
606 | ||
607 | tim1 = regs->sdram_tim1_shdw; | |
608 | tim3 = regs->sdram_tim3_shdw; | |
609 | ref_ctrl = regs->ref_ctrl_shdw; | |
610 | ||
611 | /* No de-rating for non-lpddr2 devices */ | |
612 | if (type != DDR_TYPE_LPDDR2_S2 && type != DDR_TYPE_LPDDR2_S4) | |
613 | goto out; | |
614 | ||
615 | temperature = emif->temperature_level; | |
616 | if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH) { | |
617 | ref_ctrl = regs->ref_ctrl_shdw_derated; | |
618 | } else if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS) { | |
619 | tim1 = regs->sdram_tim1_shdw_derated; | |
620 | tim3 = regs->sdram_tim3_shdw_derated; | |
621 | ref_ctrl = regs->ref_ctrl_shdw_derated; | |
622 | } | |
623 | ||
624 | out: | |
625 | writel(tim1, base + EMIF_SDRAM_TIMING_1_SHDW); | |
626 | writel(tim3, base + EMIF_SDRAM_TIMING_3_SHDW); | |
627 | writel(ref_ctrl, base + EMIF_SDRAM_REFRESH_CTRL_SHDW); | |
628 | } | |
629 | ||
7ec94453 A |
630 | static void get_default_timings(struct emif_data *emif) |
631 | { | |
632 | struct emif_platform_data *pd = emif->plat_data; | |
633 | ||
634 | pd->timings = lpddr2_jedec_timings; | |
635 | pd->timings_arr_size = ARRAY_SIZE(lpddr2_jedec_timings); | |
636 | ||
637 | dev_warn(emif->dev, "%s: using default timings\n", __func__); | |
638 | } | |
639 | ||
640 | static int is_dev_data_valid(u32 type, u32 density, u32 io_width, u32 phy_type, | |
641 | u32 ip_rev, struct device *dev) | |
642 | { | |
643 | int valid; | |
644 | ||
645 | valid = (type == DDR_TYPE_LPDDR2_S4 || | |
646 | type == DDR_TYPE_LPDDR2_S2) | |
647 | && (density >= DDR_DENSITY_64Mb | |
648 | && density <= DDR_DENSITY_8Gb) | |
649 | && (io_width >= DDR_IO_WIDTH_8 | |
650 | && io_width <= DDR_IO_WIDTH_32); | |
651 | ||
652 | /* Combinations of EMIF and PHY revisions that we support today */ | |
653 | switch (ip_rev) { | |
654 | case EMIF_4D: | |
655 | valid = valid && (phy_type == EMIF_PHY_TYPE_ATTILAPHY); | |
656 | break; | |
657 | case EMIF_4D5: | |
658 | valid = valid && (phy_type == EMIF_PHY_TYPE_INTELLIPHY); | |
659 | break; | |
660 | default: | |
661 | valid = 0; | |
662 | } | |
663 | ||
664 | if (!valid) | |
665 | dev_err(dev, "%s: invalid DDR details\n", __func__); | |
666 | return valid; | |
667 | } | |
668 | ||
669 | static int is_custom_config_valid(struct emif_custom_configs *cust_cfgs, | |
670 | struct device *dev) | |
671 | { | |
672 | int valid = 1; | |
673 | ||
674 | if ((cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE) && | |
675 | (cust_cfgs->lpmode != EMIF_LP_MODE_DISABLE)) | |
676 | valid = cust_cfgs->lpmode_freq_threshold && | |
677 | cust_cfgs->lpmode_timeout_performance && | |
678 | cust_cfgs->lpmode_timeout_power; | |
679 | ||
680 | if (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL) | |
681 | valid = valid && cust_cfgs->temp_alert_poll_interval_ms; | |
682 | ||
683 | if (!valid) | |
684 | dev_warn(dev, "%s: invalid custom configs\n", __func__); | |
685 | ||
686 | return valid; | |
687 | } | |
688 | ||
689 | static struct emif_data *__init_or_module get_device_details( | |
690 | struct platform_device *pdev) | |
691 | { | |
692 | u32 size; | |
693 | struct emif_data *emif = NULL; | |
694 | struct ddr_device_info *dev_info; | |
695 | struct emif_custom_configs *cust_cfgs; | |
696 | struct emif_platform_data *pd; | |
697 | struct device *dev; | |
698 | void *temp; | |
699 | ||
700 | pd = pdev->dev.platform_data; | |
701 | dev = &pdev->dev; | |
702 | ||
703 | if (!(pd && pd->device_info && is_dev_data_valid(pd->device_info->type, | |
704 | pd->device_info->density, pd->device_info->io_width, | |
705 | pd->phy_type, pd->ip_rev, dev))) { | |
706 | dev_err(dev, "%s: invalid device data\n", __func__); | |
707 | goto error; | |
708 | } | |
709 | ||
710 | emif = devm_kzalloc(dev, sizeof(*emif), GFP_KERNEL); | |
711 | temp = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); | |
712 | dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL); | |
713 | ||
714 | if (!emif || !pd || !dev_info) { | |
715 | dev_err(dev, "%s:%d: allocation error\n", __func__, __LINE__); | |
716 | goto error; | |
717 | } | |
718 | ||
719 | memcpy(temp, pd, sizeof(*pd)); | |
720 | pd = temp; | |
721 | memcpy(dev_info, pd->device_info, sizeof(*dev_info)); | |
722 | ||
723 | pd->device_info = dev_info; | |
724 | emif->plat_data = pd; | |
725 | emif->dev = dev; | |
726 | emif->temperature_level = SDRAM_TEMP_NOMINAL; | |
727 | ||
728 | /* | |
729 | * For EMIF instances other than EMIF1 see if the devices connected | |
730 | * are exactly same as on EMIF1(which is typically the case). If so, | |
731 | * mark it as a duplicate of EMIF1 and skip copying timings data. | |
732 | * This will save some memory and some computation later. | |
733 | */ | |
734 | emif->duplicate = emif1 && (memcmp(dev_info, | |
735 | emif1->plat_data->device_info, | |
736 | sizeof(struct ddr_device_info)) == 0); | |
737 | ||
738 | if (emif->duplicate) { | |
739 | pd->timings = NULL; | |
740 | pd->min_tck = NULL; | |
741 | goto out; | |
742 | } else if (emif1) { | |
743 | dev_warn(emif->dev, "%s: Non-symmetric DDR geometry\n", | |
744 | __func__); | |
745 | } | |
746 | ||
747 | /* | |
748 | * Copy custom configs - ignore allocation error, if any, as | |
749 | * custom_configs is not very critical | |
750 | */ | |
751 | cust_cfgs = pd->custom_configs; | |
752 | if (cust_cfgs && is_custom_config_valid(cust_cfgs, dev)) { | |
753 | temp = devm_kzalloc(dev, sizeof(*cust_cfgs), GFP_KERNEL); | |
754 | if (temp) | |
755 | memcpy(temp, cust_cfgs, sizeof(*cust_cfgs)); | |
756 | else | |
757 | dev_warn(dev, "%s:%d: allocation error\n", __func__, | |
758 | __LINE__); | |
759 | pd->custom_configs = temp; | |
760 | } | |
761 | ||
762 | /* | |
763 | * Copy timings and min-tck values from platform data. If it is not | |
764 | * available or if memory allocation fails, use JEDEC defaults | |
765 | */ | |
766 | size = sizeof(struct lpddr2_timings) * pd->timings_arr_size; | |
767 | if (pd->timings) { | |
768 | temp = devm_kzalloc(dev, size, GFP_KERNEL); | |
769 | if (temp) { | |
770 | memcpy(temp, pd->timings, sizeof(*pd->timings)); | |
771 | pd->timings = temp; | |
772 | } else { | |
773 | dev_warn(dev, "%s:%d: allocation error\n", __func__, | |
774 | __LINE__); | |
775 | get_default_timings(emif); | |
776 | } | |
777 | } else { | |
778 | get_default_timings(emif); | |
779 | } | |
780 | ||
781 | if (pd->min_tck) { | |
782 | temp = devm_kzalloc(dev, sizeof(*pd->min_tck), GFP_KERNEL); | |
783 | if (temp) { | |
784 | memcpy(temp, pd->min_tck, sizeof(*pd->min_tck)); | |
785 | pd->min_tck = temp; | |
786 | } else { | |
787 | dev_warn(dev, "%s:%d: allocation error\n", __func__, | |
788 | __LINE__); | |
789 | pd->min_tck = &lpddr2_jedec_min_tck; | |
790 | } | |
791 | } else { | |
792 | pd->min_tck = &lpddr2_jedec_min_tck; | |
793 | } | |
794 | ||
795 | out: | |
796 | return emif; | |
797 | ||
798 | error: | |
799 | return NULL; | |
800 | } | |
801 | ||
802 | static int __init_or_module emif_probe(struct platform_device *pdev) | |
803 | { | |
804 | struct emif_data *emif; | |
805 | struct resource *res; | |
806 | ||
807 | emif = get_device_details(pdev); | |
808 | if (!emif) { | |
809 | pr_err("%s: error getting device data\n", __func__); | |
810 | goto error; | |
811 | } | |
812 | ||
7ec94453 | 813 | list_add(&emif->node, &device_list); |
a93de288 | 814 | emif->addressing = get_addressing_table(emif->plat_data->device_info); |
7ec94453 A |
815 | |
816 | /* Save pointers to each other in emif and device structures */ | |
817 | emif->dev = &pdev->dev; | |
818 | platform_set_drvdata(pdev, emif); | |
819 | ||
820 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
821 | if (!res) { | |
822 | dev_err(emif->dev, "%s: error getting memory resource\n", | |
823 | __func__); | |
824 | goto error; | |
825 | } | |
826 | ||
827 | emif->base = devm_request_and_ioremap(emif->dev, res); | |
828 | if (!emif->base) { | |
829 | dev_err(emif->dev, "%s: devm_request_and_ioremap() failed\n", | |
830 | __func__); | |
831 | goto error; | |
832 | } | |
833 | ||
a93de288 A |
834 | /* One-time actions taken on probing the first device */ |
835 | if (!emif1) { | |
836 | emif1 = emif; | |
837 | spin_lock_init(&emif_lock); | |
838 | ||
839 | /* | |
840 | * TODO: register notifiers for frequency and voltage | |
841 | * change here once the respective frameworks are | |
842 | * available | |
843 | */ | |
844 | } | |
845 | ||
7ec94453 A |
846 | dev_info(&pdev->dev, "%s: device configured with addr = %p\n", |
847 | __func__, emif->base); | |
848 | ||
849 | return 0; | |
850 | error: | |
851 | return -ENODEV; | |
852 | } | |
853 | ||
a93de288 A |
854 | static int get_emif_reg_values(struct emif_data *emif, u32 freq, |
855 | struct emif_regs *regs) | |
856 | { | |
857 | u32 cs1_used, ip_rev, phy_type; | |
858 | u32 cl, type; | |
859 | const struct lpddr2_timings *timings; | |
860 | const struct lpddr2_min_tck *min_tck; | |
861 | const struct ddr_device_info *device_info; | |
862 | const struct lpddr2_addressing *addressing; | |
863 | struct emif_data *emif_for_calc; | |
864 | struct device *dev; | |
865 | const struct emif_custom_configs *custom_configs; | |
866 | ||
867 | dev = emif->dev; | |
868 | /* | |
869 | * If the devices on this EMIF instance is duplicate of EMIF1, | |
870 | * use EMIF1 details for the calculation | |
871 | */ | |
872 | emif_for_calc = emif->duplicate ? emif1 : emif; | |
873 | timings = get_timings_table(emif_for_calc, freq); | |
874 | addressing = emif_for_calc->addressing; | |
875 | if (!timings || !addressing) { | |
876 | dev_err(dev, "%s: not enough data available for %dHz", | |
877 | __func__, freq); | |
878 | return -1; | |
879 | } | |
880 | ||
881 | device_info = emif_for_calc->plat_data->device_info; | |
882 | type = device_info->type; | |
883 | cs1_used = device_info->cs1_used; | |
884 | ip_rev = emif_for_calc->plat_data->ip_rev; | |
885 | phy_type = emif_for_calc->plat_data->phy_type; | |
886 | ||
887 | min_tck = emif_for_calc->plat_data->min_tck; | |
888 | custom_configs = emif_for_calc->plat_data->custom_configs; | |
889 | ||
890 | set_ddr_clk_period(freq); | |
891 | ||
892 | regs->ref_ctrl_shdw = get_sdram_ref_ctrl_shdw(freq, addressing); | |
893 | regs->sdram_tim1_shdw = get_sdram_tim_1_shdw(timings, min_tck, | |
894 | addressing); | |
895 | regs->sdram_tim2_shdw = get_sdram_tim_2_shdw(timings, min_tck, | |
896 | addressing, type); | |
897 | regs->sdram_tim3_shdw = get_sdram_tim_3_shdw(timings, min_tck, | |
898 | addressing, type, ip_rev, EMIF_NORMAL_TIMINGS); | |
899 | ||
900 | cl = get_cl(emif); | |
901 | ||
902 | if (phy_type == EMIF_PHY_TYPE_ATTILAPHY && ip_rev == EMIF_4D) { | |
903 | regs->phy_ctrl_1_shdw = get_ddr_phy_ctrl_1_attilaphy_4d( | |
904 | timings, freq, cl); | |
905 | } else if (phy_type == EMIF_PHY_TYPE_INTELLIPHY && ip_rev == EMIF_4D5) { | |
906 | regs->phy_ctrl_1_shdw = get_phy_ctrl_1_intelliphy_4d5(freq, cl); | |
907 | regs->ext_phy_ctrl_2_shdw = get_ext_phy_ctrl_2_intelliphy_4d5(); | |
908 | regs->ext_phy_ctrl_3_shdw = get_ext_phy_ctrl_3_intelliphy_4d5(); | |
909 | regs->ext_phy_ctrl_4_shdw = get_ext_phy_ctrl_4_intelliphy_4d5(); | |
910 | } else { | |
911 | return -1; | |
912 | } | |
913 | ||
914 | /* Only timeout values in pwr_mgmt_ctrl_shdw register */ | |
915 | regs->pwr_mgmt_ctrl_shdw = | |
916 | get_pwr_mgmt_ctrl(freq, emif_for_calc, ip_rev) & | |
917 | (CS_TIM_MASK | SR_TIM_MASK | PD_TIM_MASK); | |
918 | ||
919 | if (ip_rev & EMIF_4D) { | |
920 | regs->read_idle_ctrl_shdw_normal = | |
921 | get_read_idle_ctrl_shdw(DDR_VOLTAGE_STABLE); | |
922 | ||
923 | regs->read_idle_ctrl_shdw_volt_ramp = | |
924 | get_read_idle_ctrl_shdw(DDR_VOLTAGE_RAMPING); | |
925 | } else if (ip_rev & EMIF_4D5) { | |
926 | regs->dll_calib_ctrl_shdw_normal = | |
927 | get_dll_calib_ctrl_shdw(DDR_VOLTAGE_STABLE); | |
928 | ||
929 | regs->dll_calib_ctrl_shdw_volt_ramp = | |
930 | get_dll_calib_ctrl_shdw(DDR_VOLTAGE_RAMPING); | |
931 | } | |
932 | ||
933 | if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) { | |
934 | regs->ref_ctrl_shdw_derated = get_sdram_ref_ctrl_shdw(freq / 4, | |
935 | addressing); | |
936 | ||
937 | regs->sdram_tim1_shdw_derated = | |
938 | get_sdram_tim_1_shdw_derated(timings, min_tck, | |
939 | addressing); | |
940 | ||
941 | regs->sdram_tim3_shdw_derated = get_sdram_tim_3_shdw(timings, | |
942 | min_tck, addressing, type, ip_rev, | |
943 | EMIF_DERATED_TIMINGS); | |
944 | } | |
945 | ||
946 | regs->freq = freq; | |
947 | ||
948 | return 0; | |
949 | } | |
950 | ||
951 | /* | |
952 | * get_regs() - gets the cached emif_regs structure for a given EMIF instance | |
953 | * given frequency(freq): | |
954 | * | |
955 | * As an optimisation, every EMIF instance other than EMIF1 shares the | |
956 | * register cache with EMIF1 if the devices connected on this instance | |
957 | * are same as that on EMIF1(indicated by the duplicate flag) | |
958 | * | |
959 | * If we do not have an entry corresponding to the frequency given, we | |
960 | * allocate a new entry and calculate the values | |
961 | * | |
962 | * Upon finding the right reg dump, save it in curr_regs. It can be | |
963 | * directly used for thermal de-rating and voltage ramping changes. | |
964 | */ | |
965 | static struct emif_regs *get_regs(struct emif_data *emif, u32 freq) | |
966 | { | |
967 | int i; | |
968 | struct emif_regs **regs_cache; | |
969 | struct emif_regs *regs = NULL; | |
970 | struct device *dev; | |
971 | ||
972 | dev = emif->dev; | |
973 | if (emif->curr_regs && emif->curr_regs->freq == freq) { | |
974 | dev_dbg(dev, "%s: using curr_regs - %u Hz", __func__, freq); | |
975 | return emif->curr_regs; | |
976 | } | |
977 | ||
978 | if (emif->duplicate) | |
979 | regs_cache = emif1->regs_cache; | |
980 | else | |
981 | regs_cache = emif->regs_cache; | |
982 | ||
983 | for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) { | |
984 | if (regs_cache[i]->freq == freq) { | |
985 | regs = regs_cache[i]; | |
986 | dev_dbg(dev, | |
987 | "%s: reg dump found in reg cache for %u Hz\n", | |
988 | __func__, freq); | |
989 | break; | |
990 | } | |
991 | } | |
992 | ||
993 | /* | |
994 | * If we don't have an entry for this frequency in the cache create one | |
995 | * and calculate the values | |
996 | */ | |
997 | if (!regs) { | |
998 | regs = devm_kzalloc(emif->dev, sizeof(*regs), GFP_ATOMIC); | |
999 | if (!regs) | |
1000 | return NULL; | |
1001 | ||
1002 | if (get_emif_reg_values(emif, freq, regs)) { | |
1003 | devm_kfree(emif->dev, regs); | |
1004 | return NULL; | |
1005 | } | |
1006 | ||
1007 | /* | |
1008 | * Now look for an un-used entry in the cache and save the | |
1009 | * newly created struct. If there are no free entries | |
1010 | * over-write the last entry | |
1011 | */ | |
1012 | for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) | |
1013 | ; | |
1014 | ||
1015 | if (i >= EMIF_MAX_NUM_FREQUENCIES) { | |
1016 | dev_warn(dev, "%s: regs_cache full - reusing a slot!!\n", | |
1017 | __func__); | |
1018 | i = EMIF_MAX_NUM_FREQUENCIES - 1; | |
1019 | devm_kfree(emif->dev, regs_cache[i]); | |
1020 | } | |
1021 | regs_cache[i] = regs; | |
1022 | } | |
1023 | ||
1024 | return regs; | |
1025 | } | |
1026 | ||
1027 | static void do_volt_notify_handling(struct emif_data *emif, u32 volt_state) | |
1028 | { | |
1029 | dev_dbg(emif->dev, "%s: voltage notification : %d", __func__, | |
1030 | volt_state); | |
1031 | ||
1032 | if (!emif->curr_regs) { | |
1033 | dev_err(emif->dev, | |
1034 | "%s: volt-notify before registers are ready: %d\n", | |
1035 | __func__, volt_state); | |
1036 | return; | |
1037 | } | |
1038 | ||
1039 | setup_volt_sensitive_regs(emif, emif->curr_regs, volt_state); | |
1040 | } | |
1041 | ||
1042 | /* | |
1043 | * TODO: voltage notify handling should be hooked up to | |
1044 | * regulator framework as soon as the necessary support | |
1045 | * is available in mainline kernel. This function is un-used | |
1046 | * right now. | |
1047 | */ | |
1048 | static void __attribute__((unused)) volt_notify_handling(u32 volt_state) | |
1049 | { | |
1050 | struct emif_data *emif; | |
1051 | ||
1052 | spin_lock_irqsave(&emif_lock, irq_state); | |
1053 | ||
1054 | list_for_each_entry(emif, &device_list, node) | |
1055 | do_volt_notify_handling(emif, volt_state); | |
1056 | do_freq_update(); | |
1057 | ||
1058 | spin_unlock_irqrestore(&emif_lock, irq_state); | |
1059 | } | |
1060 | ||
1061 | static void do_freq_pre_notify_handling(struct emif_data *emif, u32 new_freq) | |
1062 | { | |
1063 | struct emif_regs *regs; | |
1064 | ||
1065 | regs = get_regs(emif, new_freq); | |
1066 | if (!regs) | |
1067 | return; | |
1068 | ||
1069 | emif->curr_regs = regs; | |
1070 | ||
1071 | /* | |
1072 | * Update the shadow registers: | |
1073 | * Temperature and voltage-ramp sensitive settings are also configured | |
1074 | * in terms of DDR cycles. So, we need to update them too when there | |
1075 | * is a freq change | |
1076 | */ | |
1077 | dev_dbg(emif->dev, "%s: setting up shadow registers for %uHz", | |
1078 | __func__, new_freq); | |
1079 | setup_registers(emif, regs); | |
1080 | setup_temperature_sensitive_regs(emif, regs); | |
1081 | setup_volt_sensitive_regs(emif, regs, DDR_VOLTAGE_STABLE); | |
1082 | ||
1083 | /* | |
1084 | * Part of workaround for errata i728. See do_freq_update() | |
1085 | * for more details | |
1086 | */ | |
1087 | if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH) | |
1088 | set_lpmode(emif, EMIF_LP_MODE_DISABLE); | |
1089 | } | |
1090 | ||
1091 | /* | |
1092 | * TODO: frequency notify handling should be hooked up to | |
1093 | * clock framework as soon as the necessary support is | |
1094 | * available in mainline kernel. This function is un-used | |
1095 | * right now. | |
1096 | */ | |
1097 | static void __attribute__((unused)) freq_pre_notify_handling(u32 new_freq) | |
1098 | { | |
1099 | struct emif_data *emif; | |
1100 | ||
1101 | /* | |
1102 | * NOTE: we are taking the spin-lock here and releases it | |
1103 | * only in post-notifier. This doesn't look good and | |
1104 | * Sparse complains about it, but this seems to be | |
1105 | * un-avoidable. We need to lock a sequence of events | |
1106 | * that is split between EMIF and clock framework. | |
1107 | * | |
1108 | * 1. EMIF driver updates EMIF timings in shadow registers in the | |
1109 | * frequency pre-notify callback from clock framework | |
1110 | * 2. clock framework sets up the registers for the new frequency | |
1111 | * 3. clock framework initiates a hw-sequence that updates | |
1112 | * the frequency EMIF timings synchronously. | |
1113 | * | |
1114 | * All these 3 steps should be performed as an atomic operation | |
1115 | * vis-a-vis similar sequence in the EMIF interrupt handler | |
1116 | * for temperature events. Otherwise, there could be race | |
1117 | * conditions that could result in incorrect EMIF timings for | |
1118 | * a given frequency | |
1119 | */ | |
1120 | spin_lock_irqsave(&emif_lock, irq_state); | |
1121 | ||
1122 | list_for_each_entry(emif, &device_list, node) | |
1123 | do_freq_pre_notify_handling(emif, new_freq); | |
1124 | } | |
1125 | ||
1126 | static void do_freq_post_notify_handling(struct emif_data *emif) | |
1127 | { | |
1128 | /* | |
1129 | * Part of workaround for errata i728. See do_freq_update() | |
1130 | * for more details | |
1131 | */ | |
1132 | if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH) | |
1133 | set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH); | |
1134 | } | |
1135 | ||
1136 | /* | |
1137 | * TODO: frequency notify handling should be hooked up to | |
1138 | * clock framework as soon as the necessary support is | |
1139 | * available in mainline kernel. This function is un-used | |
1140 | * right now. | |
1141 | */ | |
1142 | static void __attribute__((unused)) freq_post_notify_handling(void) | |
1143 | { | |
1144 | struct emif_data *emif; | |
1145 | ||
1146 | list_for_each_entry(emif, &device_list, node) | |
1147 | do_freq_post_notify_handling(emif); | |
1148 | ||
1149 | /* | |
1150 | * Lock is done in pre-notify handler. See freq_pre_notify_handling() | |
1151 | * for more details | |
1152 | */ | |
1153 | spin_unlock_irqrestore(&emif_lock, irq_state); | |
1154 | } | |
1155 | ||
7ec94453 A |
1156 | static struct platform_driver emif_driver = { |
1157 | .driver = { | |
1158 | .name = "emif", | |
1159 | }, | |
1160 | }; | |
1161 | ||
1162 | static int __init_or_module emif_register(void) | |
1163 | { | |
1164 | return platform_driver_probe(&emif_driver, emif_probe); | |
1165 | } | |
1166 | ||
1167 | static void __exit emif_unregister(void) | |
1168 | { | |
1169 | platform_driver_unregister(&emif_driver); | |
1170 | } | |
1171 | ||
1172 | module_init(emif_register); | |
1173 | module_exit(emif_unregister); | |
1174 | MODULE_DESCRIPTION("TI EMIF SDRAM Controller Driver"); | |
1175 | MODULE_LICENSE("GPL"); | |
1176 | MODULE_ALIAS("platform:emif"); | |
1177 | MODULE_AUTHOR("Texas Instruments Inc"); |