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Merge branch 'irq-cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / media / video / tvp5150.c
CommitLineData
cd4665c5 1/*
6ac48b45 2 * tvp5150 - Texas Instruments TVP5150A/AM1 video decoder driver
cd4665c5 3 *
6ac48b45
MCC		 4 * Copyright (c) 2005,2006 Mauro Carvalho Chehab (mchehab@infradead.org)
5 * This code is placed under the terms of the GNU General Public License v2
cd4665c5
MCC		 6 */
7
cd4665c5 8#include <linux/i2c.h>
5a0e3ad6 9#include <linux/slab.h>
33b687cf 10#include <linux/videodev2.h>
cd4665c5 11#include <linux/delay.h>
6b8fe025 12#include <media/v4l2-device.h>
c7c0b34c 13#include <media/tvp5150.h>
bc974305 14#include <media/v4l2-chip-ident.h>
6c45ec71 15#include <media/v4l2-ctrls.h>
cd4665c5
MCC		 16
17#include "tvp5150_reg.h"
18
6ac48b45 19MODULE_DESCRIPTION("Texas Instruments TVP5150A video decoder driver");
cd4665c5
MCC		 20MODULE_AUTHOR("Mauro Carvalho Chehab");
21MODULE_LICENSE("GPL");
22
cd4665c5 23
ff699e6b 24static int debug;
cd4665c5 25module_param(debug, int, 0);
6b8fe025 26MODULE_PARM_DESC(debug, "Debug level (0-2)");
cd4665c5
MCC		 27
28struct tvp5150 {
6b8fe025 29 struct v4l2_subdev sd;
6c45ec71 30 struct v4l2_ctrl_handler hdl;
84486d53 31
3ad96835 32 v4l2_std_id norm; /* Current set standard */
5325b427
HV		 33 u32 input;
34 u32 output;
84486d53 35 int enable;
cd4665c5
MCC		 36};
37
6b8fe025 38static inline struct tvp5150 *to_tvp5150(struct v4l2_subdev *sd)
cd4665c5 39{
6b8fe025
HV		 40 return container_of(sd, struct tvp5150, sd);
41}
42
6c45ec71
HV		 43static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
44{
45 return &container_of(ctrl->handler, struct tvp5150, hdl)->sd;
46}
47
6b8fe025
HV		 48static int tvp5150_read(struct v4l2_subdev *sd, unsigned char addr)
49{
50 struct i2c_client *c = v4l2_get_subdevdata(sd);
cd4665c5
MCC		 51 unsigned char buffer[1];
52 int rc;
cd4665c5
MCC		 53
54 buffer[0] = addr;
55 if (1 != (rc = i2c_master_send(c, buffer, 1)))
6b8fe025 56 v4l2_dbg(0, debug, sd, "i2c i/o error: rc == %d (should be 1)\n", rc);
cd4665c5
MCC		 57
58 msleep(10);
59
60 if (1 != (rc = i2c_master_recv(c, buffer, 1)))
6b8fe025 61 v4l2_dbg(0, debug, sd, "i2c i/o error: rc == %d (should be 1)\n", rc);
e1bc80ad 62
6b8fe025 63 v4l2_dbg(2, debug, sd, "tvp5150: read 0x%02x = 0x%02x\n", addr, buffer[0]);
cd4665c5
MCC		 64
65 return (buffer[0]);
66}
67
6b8fe025 68static inline void tvp5150_write(struct v4l2_subdev *sd, unsigned char addr,
84486d53 69 unsigned char value)
cd4665c5 70{
6b8fe025 71 struct i2c_client *c = v4l2_get_subdevdata(sd);
cd4665c5
MCC		 72 unsigned char buffer[2];
73 int rc;
cd4665c5
MCC		 74
75 buffer[0] = addr;
84486d53 76 buffer[1] = value;
6b8fe025 77 v4l2_dbg(2, debug, sd, "tvp5150: writing 0x%02x 0x%02x\n", buffer[0], buffer[1]);
cd4665c5 78 if (2 != (rc = i2c_master_send(c, buffer, 2)))
6b8fe025 79 v4l2_dbg(0, debug, sd, "i2c i/o error: rc == %d (should be 2)\n", rc);
cd4665c5
MCC		 80}
81
6b8fe025
HV		 82static void dump_reg_range(struct v4l2_subdev *sd, char *s, u8 init,
83 const u8 end, int max_line)
3ad96835 84{
6b8fe025 85 int i = 0;
3ad96835 86
6b8fe025
HV		 87 while (init != (u8)(end + 1)) {
88 if ((i % max_line) == 0) {
89 if (i > 0)
3ad96835 90 printk("\n");
6b8fe025 91 printk("tvp5150: %s reg 0x%02x = ", s, init);
3ad96835 92 }
6b8fe025 93 printk("%02x ", tvp5150_read(sd, init));
3ad96835
MCC		 94
95 init++;
96 i++;
97 }
98 printk("\n");
99}
100
6b8fe025 101static int tvp5150_log_status(struct v4l2_subdev *sd)
cd4665c5 102{
84486d53 103 printk("tvp5150: Video input source selection #1 = 0x%02x\n",
6b8fe025 104 tvp5150_read(sd, TVP5150_VD_IN_SRC_SEL_1));
84486d53 105 printk("tvp5150: Analog channel controls = 0x%02x\n",
6b8fe025 106 tvp5150_read(sd, TVP5150_ANAL_CHL_CTL));
84486d53 107 printk("tvp5150: Operation mode controls = 0x%02x\n",
6b8fe025 108 tvp5150_read(sd, TVP5150_OP_MODE_CTL));
84486d53 109 printk("tvp5150: Miscellaneous controls = 0x%02x\n",
6b8fe025 110 tvp5150_read(sd, TVP5150_MISC_CTL));
3ad96835 111 printk("tvp5150: Autoswitch mask= 0x%02x\n",
6b8fe025 112 tvp5150_read(sd, TVP5150_AUTOSW_MSK));
84486d53 113 printk("tvp5150: Color killer threshold control = 0x%02x\n",
6b8fe025 114 tvp5150_read(sd, TVP5150_COLOR_KIL_THSH_CTL));
3ad96835 115 printk("tvp5150: Luminance processing controls #1 #2 and #3 = %02x %02x %02x\n",
6b8fe025
HV		 116 tvp5150_read(sd, TVP5150_LUMA_PROC_CTL_1),
117 tvp5150_read(sd, TVP5150_LUMA_PROC_CTL_2),
118 tvp5150_read(sd, TVP5150_LUMA_PROC_CTL_3));
84486d53 119 printk("tvp5150: Brightness control = 0x%02x\n",
6b8fe025 120 tvp5150_read(sd, TVP5150_BRIGHT_CTL));
84486d53 121 printk("tvp5150: Color saturation control = 0x%02x\n",
6b8fe025 122 tvp5150_read(sd, TVP5150_SATURATION_CTL));
84486d53 123 printk("tvp5150: Hue control = 0x%02x\n",
6b8fe025 124 tvp5150_read(sd, TVP5150_HUE_CTL));
84486d53 125 printk("tvp5150: Contrast control = 0x%02x\n",
6b8fe025 126 tvp5150_read(sd, TVP5150_CONTRAST_CTL));
84486d53 127 printk("tvp5150: Outputs and data rates select = 0x%02x\n",
6b8fe025 128 tvp5150_read(sd, TVP5150_DATA_RATE_SEL));
84486d53 129 printk("tvp5150: Configuration shared pins = 0x%02x\n",
6b8fe025 130 tvp5150_read(sd, TVP5150_CONF_SHARED_PIN));
3ad96835 131 printk("tvp5150: Active video cropping start = 0x%02x%02x\n",
6b8fe025
HV		 132 tvp5150_read(sd, TVP5150_ACT_VD_CROP_ST_MSB),
133 tvp5150_read(sd, TVP5150_ACT_VD_CROP_ST_LSB));
3ad96835 134 printk("tvp5150: Active video cropping stop = 0x%02x%02x\n",
6b8fe025
HV		 135 tvp5150_read(sd, TVP5150_ACT_VD_CROP_STP_MSB),
136 tvp5150_read(sd, TVP5150_ACT_VD_CROP_STP_LSB));
84486d53 137 printk("tvp5150: Genlock/RTC = 0x%02x\n",
6b8fe025 138 tvp5150_read(sd, TVP5150_GENLOCK));
84486d53 139 printk("tvp5150: Horizontal sync start = 0x%02x\n",
6b8fe025 140 tvp5150_read(sd, TVP5150_HORIZ_SYNC_START));
84486d53 141 printk("tvp5150: Vertical blanking start = 0x%02x\n",
6b8fe025 142 tvp5150_read(sd, TVP5150_VERT_BLANKING_START));
84486d53 143 printk("tvp5150: Vertical blanking stop = 0x%02x\n",
6b8fe025 144 tvp5150_read(sd, TVP5150_VERT_BLANKING_STOP));
3ad96835 145 printk("tvp5150: Chrominance processing control #1 and #2 = %02x %02x\n",
6b8fe025
HV		 146 tvp5150_read(sd, TVP5150_CHROMA_PROC_CTL_1),
147 tvp5150_read(sd, TVP5150_CHROMA_PROC_CTL_2));
84486d53 148 printk("tvp5150: Interrupt reset register B = 0x%02x\n",
6b8fe025 149 tvp5150_read(sd, TVP5150_INT_RESET_REG_B));
84486d53 150 printk("tvp5150: Interrupt enable register B = 0x%02x\n",
6b8fe025 151 tvp5150_read(sd, TVP5150_INT_ENABLE_REG_B));
84486d53 152 printk("tvp5150: Interrupt configuration register B = 0x%02x\n",
6b8fe025 153 tvp5150_read(sd, TVP5150_INTT_CONFIG_REG_B));
84486d53 154 printk("tvp5150: Video standard = 0x%02x\n",
6b8fe025 155 tvp5150_read(sd, TVP5150_VIDEO_STD));
3ad96835 156 printk("tvp5150: Chroma gain factor: Cb=0x%02x Cr=0x%02x\n",
6b8fe025
HV		 157 tvp5150_read(sd, TVP5150_CB_GAIN_FACT),
158 tvp5150_read(sd, TVP5150_CR_GAIN_FACTOR));
84486d53 159 printk("tvp5150: Macrovision on counter = 0x%02x\n",
6b8fe025 160 tvp5150_read(sd, TVP5150_MACROVISION_ON_CTR));
84486d53 161 printk("tvp5150: Macrovision off counter = 0x%02x\n",
6b8fe025 162 tvp5150_read(sd, TVP5150_MACROVISION_OFF_CTR));
3ad96835 163 printk("tvp5150: ITU-R BT.656.%d timing(TVP5150AM1 only)\n",
6b8fe025 164 (tvp5150_read(sd, TVP5150_REV_SELECT) & 1) ? 3 : 4);
3ad96835 165 printk("tvp5150: Device ID = %02x%02x\n",
6b8fe025
HV		 166 tvp5150_read(sd, TVP5150_MSB_DEV_ID),
167 tvp5150_read(sd, TVP5150_LSB_DEV_ID));
3ad96835 168 printk("tvp5150: ROM version = (hex) %02x.%02x\n",
6b8fe025
HV		 169 tvp5150_read(sd, TVP5150_ROM_MAJOR_VER),
170 tvp5150_read(sd, TVP5150_ROM_MINOR_VER));
3ad96835 171 printk("tvp5150: Vertical line count = 0x%02x%02x\n",
6b8fe025
HV		 172 tvp5150_read(sd, TVP5150_VERT_LN_COUNT_MSB),
173 tvp5150_read(sd, TVP5150_VERT_LN_COUNT_LSB));
84486d53 174 printk("tvp5150: Interrupt status register B = 0x%02x\n",
6b8fe025 175 tvp5150_read(sd, TVP5150_INT_STATUS_REG_B));
84486d53 176 printk("tvp5150: Interrupt active register B = 0x%02x\n",
6b8fe025 177 tvp5150_read(sd, TVP5150_INT_ACTIVE_REG_B));
3ad96835 178 printk("tvp5150: Status regs #1 to #5 = %02x %02x %02x %02x %02x\n",
6b8fe025
HV		 179 tvp5150_read(sd, TVP5150_STATUS_REG_1),
180 tvp5150_read(sd, TVP5150_STATUS_REG_2),
181 tvp5150_read(sd, TVP5150_STATUS_REG_3),
182 tvp5150_read(sd, TVP5150_STATUS_REG_4),
183 tvp5150_read(sd, TVP5150_STATUS_REG_5));
3ad96835 184
6b8fe025
HV		 185 dump_reg_range(sd, "Teletext filter 1", TVP5150_TELETEXT_FIL1_INI,
186 TVP5150_TELETEXT_FIL1_END, 8);
187 dump_reg_range(sd, "Teletext filter 2", TVP5150_TELETEXT_FIL2_INI,
188 TVP5150_TELETEXT_FIL2_END, 8);
3ad96835 189
84486d53 190 printk("tvp5150: Teletext filter enable = 0x%02x\n",
6b8fe025 191 tvp5150_read(sd, TVP5150_TELETEXT_FIL_ENA));
84486d53 192 printk("tvp5150: Interrupt status register A = 0x%02x\n",
6b8fe025 193 tvp5150_read(sd, TVP5150_INT_STATUS_REG_A));
84486d53 194 printk("tvp5150: Interrupt enable register A = 0x%02x\n",
6b8fe025 195 tvp5150_read(sd, TVP5150_INT_ENABLE_REG_A));
84486d53 196 printk("tvp5150: Interrupt configuration = 0x%02x\n",
6b8fe025 197 tvp5150_read(sd, TVP5150_INT_CONF));
84486d53 198 printk("tvp5150: VDP status register = 0x%02x\n",
6b8fe025 199 tvp5150_read(sd, TVP5150_VDP_STATUS_REG));
84486d53 200 printk("tvp5150: FIFO word count = 0x%02x\n",
6b8fe025 201 tvp5150_read(sd, TVP5150_FIFO_WORD_COUNT));
84486d53 202 printk("tvp5150: FIFO interrupt threshold = 0x%02x\n",
6b8fe025 203 tvp5150_read(sd, TVP5150_FIFO_INT_THRESHOLD));
84486d53 204 printk("tvp5150: FIFO reset = 0x%02x\n",
6b8fe025 205 tvp5150_read(sd, TVP5150_FIFO_RESET));
84486d53 206 printk("tvp5150: Line number interrupt = 0x%02x\n",
6b8fe025 207 tvp5150_read(sd, TVP5150_LINE_NUMBER_INT));
3ad96835 208 printk("tvp5150: Pixel alignment register = 0x%02x%02x\n",
6b8fe025
HV		 209 tvp5150_read(sd, TVP5150_PIX_ALIGN_REG_HIGH),
210 tvp5150_read(sd, TVP5150_PIX_ALIGN_REG_LOW));
84486d53 211 printk("tvp5150: FIFO output control = 0x%02x\n",
6b8fe025 212 tvp5150_read(sd, TVP5150_FIFO_OUT_CTRL));
3ad96835 213 printk("tvp5150: Full field enable = 0x%02x\n",
6b8fe025 214 tvp5150_read(sd, TVP5150_FULL_FIELD_ENA));
84486d53 215 printk("tvp5150: Full field mode register = 0x%02x\n",
6b8fe025 216 tvp5150_read(sd, TVP5150_FULL_FIELD_MODE_REG));
3ad96835 217
6b8fe025
HV		 218 dump_reg_range(sd, "CC data", TVP5150_CC_DATA_INI,
219 TVP5150_CC_DATA_END, 8);
3ad96835 220
6b8fe025
HV		 221 dump_reg_range(sd, "WSS data", TVP5150_WSS_DATA_INI,
222 TVP5150_WSS_DATA_END, 8);
3ad96835 223
6b8fe025
HV		 224 dump_reg_range(sd, "VPS data", TVP5150_VPS_DATA_INI,
225 TVP5150_VPS_DATA_END, 8);
3ad96835 226
6b8fe025
HV		 227 dump_reg_range(sd, "VITC data", TVP5150_VITC_DATA_INI,
228 TVP5150_VITC_DATA_END, 10);
3ad96835 229
6b8fe025
HV		 230 dump_reg_range(sd, "Line mode", TVP5150_LINE_MODE_INI,
231 TVP5150_LINE_MODE_END, 8);
232 return 0;
cd4665c5
MCC		 233}
234
235/****************************************************************************
236 Basic functions
237 ****************************************************************************/
cd4665c5 238
6b8fe025 239static inline void tvp5150_selmux(struct v4l2_subdev *sd)
cd4665c5 240{
2962fc01 241 int opmode = 0;
6b8fe025 242 struct tvp5150 *decoder = to_tvp5150(sd);
c7c0b34c 243 int input = 0;
f4b8b3ae 244 unsigned char val;
84486d53 245
5325b427 246 if ((decoder->output & TVP5150_BLACK_SCREEN) || !decoder->enable)
c7c0b34c 247 input = 8;
4c86f973 248
5325b427 249 switch (decoder->input) {
c7c0b34c
HV		 250 case TVP5150_COMPOSITE1:
251 input |= 2;
252 /* fall through */
253 case TVP5150_COMPOSITE0:
c0477ad9 254 break;
c7c0b34c 255 case TVP5150_SVIDEO:
c0477ad9 256 default:
c7c0b34c 257 input |= 1;
c0477ad9
MCC		 258 break;
259 }
260
6b8fe025 261 v4l2_dbg(1, debug, sd, "Selecting video route: route input=%i, output=%i "
12500f07 262 "=> tvp5150 input=%i, opmode=%i\n",
5325b427
HV		 263 decoder->input, decoder->output,
264 input, opmode);
12500f07 265
6b8fe025
HV		 266 tvp5150_write(sd, TVP5150_OP_MODE_CTL, opmode);
267 tvp5150_write(sd, TVP5150_VD_IN_SRC_SEL_1, input);
f4b8b3ae
MCC		 268
269 /* Svideo should enable YCrCb output and disable GPCL output
270 * For Composite and TV, it should be the reverse
271 */
6b8fe025 272 val = tvp5150_read(sd, TVP5150_MISC_CTL);
5325b427 273 if (decoder->input == TVP5150_SVIDEO)
f4b8b3ae
MCC		 274 val = (val & ~0x40) | 0x10;
275 else
276 val = (val & ~0x10) | 0x40;
6b8fe025 277 tvp5150_write(sd, TVP5150_MISC_CTL, val);
cd4665c5
MCC		 278};
279
e1bc80ad
MCC		 280struct i2c_reg_value {
281 unsigned char reg;
282 unsigned char value;
283};
284
285/* Default values as sugested at TVP5150AM1 datasheet */
286static const struct i2c_reg_value tvp5150_init_default[] = {
287 { /* 0x00 */
288 TVP5150_VD_IN_SRC_SEL_1,0x00
289 },
290 { /* 0x01 */
291 TVP5150_ANAL_CHL_CTL,0x15
292 },
293 { /* 0x02 */
294 TVP5150_OP_MODE_CTL,0x00
295 },
296 { /* 0x03 */
297 TVP5150_MISC_CTL,0x01
298 },
299 { /* 0x06 */
300 TVP5150_COLOR_KIL_THSH_CTL,0x10
301 },
302 { /* 0x07 */
303 TVP5150_LUMA_PROC_CTL_1,0x60
304 },
305 { /* 0x08 */
306 TVP5150_LUMA_PROC_CTL_2,0x00
307 },
308 { /* 0x09 */
309 TVP5150_BRIGHT_CTL,0x80
310 },
311 { /* 0x0a */
312 TVP5150_SATURATION_CTL,0x80
313 },
314 { /* 0x0b */
315 TVP5150_HUE_CTL,0x00
316 },
317 { /* 0x0c */
318 TVP5150_CONTRAST_CTL,0x80
319 },
320 { /* 0x0d */
321 TVP5150_DATA_RATE_SEL,0x47
322 },
323 { /* 0x0e */
324 TVP5150_LUMA_PROC_CTL_3,0x00
325 },
326 { /* 0x0f */
327 TVP5150_CONF_SHARED_PIN,0x08
328 },
329 { /* 0x11 */
330 TVP5150_ACT_VD_CROP_ST_MSB,0x00
331 },
332 { /* 0x12 */
333 TVP5150_ACT_VD_CROP_ST_LSB,0x00
334 },
335 { /* 0x13 */
336 TVP5150_ACT_VD_CROP_STP_MSB,0x00
337 },
338 { /* 0x14 */
339 TVP5150_ACT_VD_CROP_STP_LSB,0x00
340 },
341 { /* 0x15 */
342 TVP5150_GENLOCK,0x01
343 },
344 { /* 0x16 */
345 TVP5150_HORIZ_SYNC_START,0x80
346 },
347 { /* 0x18 */
348 TVP5150_VERT_BLANKING_START,0x00
349 },
350 { /* 0x19 */
351 TVP5150_VERT_BLANKING_STOP,0x00
352 },
353 { /* 0x1a */
354 TVP5150_CHROMA_PROC_CTL_1,0x0c
355 },
356 { /* 0x1b */
357 TVP5150_CHROMA_PROC_CTL_2,0x14
358 },
359 { /* 0x1c */
360 TVP5150_INT_RESET_REG_B,0x00
361 },
362 { /* 0x1d */
363 TVP5150_INT_ENABLE_REG_B,0x00
364 },
365 { /* 0x1e */
366 TVP5150_INTT_CONFIG_REG_B,0x00
367 },
368 { /* 0x28 */
369 TVP5150_VIDEO_STD,0x00
370 },
371 { /* 0x2e */
372 TVP5150_MACROVISION_ON_CTR,0x0f
373 },
374 { /* 0x2f */
375 TVP5150_MACROVISION_OFF_CTR,0x01
376 },
377 { /* 0xbb */
378 TVP5150_TELETEXT_FIL_ENA,0x00
379 },
380 { /* 0xc0 */
381 TVP5150_INT_STATUS_REG_A,0x00
382 },
383 { /* 0xc1 */
384 TVP5150_INT_ENABLE_REG_A,0x00
385 },
386 { /* 0xc2 */
387 TVP5150_INT_CONF,0x04
388 },
389 { /* 0xc8 */
390 TVP5150_FIFO_INT_THRESHOLD,0x80
391 },
392 { /* 0xc9 */
393 TVP5150_FIFO_RESET,0x00
394 },
395 { /* 0xca */
396 TVP5150_LINE_NUMBER_INT,0x00
397 },
398 { /* 0xcb */
399 TVP5150_PIX_ALIGN_REG_LOW,0x4e
400 },
401 { /* 0xcc */
402 TVP5150_PIX_ALIGN_REG_HIGH,0x00
403 },
404 { /* 0xcd */
405 TVP5150_FIFO_OUT_CTRL,0x01
406 },
407 { /* 0xcf */
3ad96835 408 TVP5150_FULL_FIELD_ENA,0x00
e1bc80ad
MCC		 409 },
410 { /* 0xd0 */
3ad96835 411 TVP5150_LINE_MODE_INI,0x00
e1bc80ad
MCC		 412 },
413 { /* 0xfc */
414 TVP5150_FULL_FIELD_MODE_REG,0x7f
415 },
416 { /* end of data */
417 0xff,0xff
418 }
419};
420
421/* Default values as sugested at TVP5150AM1 datasheet */
422static const struct i2c_reg_value tvp5150_init_enable[] = {
423 {
424 TVP5150_CONF_SHARED_PIN, 2
425 },{ /* Automatic offset and AGC enabled */
426 TVP5150_ANAL_CHL_CTL, 0x15
427 },{ /* Activate YCrCb output 0x9 or 0xd ? */
428 TVP5150_MISC_CTL, 0x6f
429 },{ /* Activates video std autodetection for all standards */
430 TVP5150_AUTOSW_MSK, 0x0
431 },{ /* Default format: 0x47. For 4:2:2: 0x40 */
432 TVP5150_DATA_RATE_SEL, 0x47
433 },{
434 TVP5150_CHROMA_PROC_CTL_1, 0x0c
435 },{
436 TVP5150_CHROMA_PROC_CTL_2, 0x54
437 },{ /* Non documented, but initialized on WinTV USB2 */
438 0x27, 0x20
439 },{
440 0xff,0xff
441 }
442};
443
6ac48b45
MCC		 444struct tvp5150_vbi_type {
445 unsigned int vbi_type;
446 unsigned int ini_line;
447 unsigned int end_line;
448 unsigned int by_field :1;
449};
450
e1bc80ad
MCC		 451struct i2c_vbi_ram_value {
452 u16 reg;
6ac48b45
MCC		 453 struct tvp5150_vbi_type type;
454 unsigned char values[16];
e1bc80ad
MCC		 455};
456
6ac48b45
MCC		 457/* This struct have the values for each supported VBI Standard
458 * by
459 tvp5150_vbi_types should follow the same order as vbi_ram_default
3ad96835
MCC		 460 * value 0 means rom position 0x10, value 1 means rom position 0x30
461 * and so on. There are 16 possible locations from 0 to 15.
462 */
3ad96835 463
a9cff90e 464static struct i2c_vbi_ram_value vbi_ram_default[] =
cd4665c5 465{
9bc7400a
HV		 466 /* FIXME: Current api doesn't handle all VBI types, those not
467 yet supported are placed under #if 0 */
468#if 0
6ac48b45
MCC		 469 {0x010, /* Teletext, SECAM, WST System A */
470 {V4L2_SLICED_TELETEXT_SECAM,6,23,1},
471 { 0xaa, 0xaa, 0xff, 0xff, 0xe7, 0x2e, 0x20, 0x26,
472 0xe6, 0xb4, 0x0e, 0x00, 0x00, 0x00, 0x10, 0x00 }
e1bc80ad 473 },
9bc7400a 474#endif
6ac48b45 475 {0x030, /* Teletext, PAL, WST System B */
9bc7400a 476 {V4L2_SLICED_TELETEXT_B,6,22,1},
6ac48b45
MCC		 477 { 0xaa, 0xaa, 0xff, 0xff, 0x27, 0x2e, 0x20, 0x2b,
478 0xa6, 0x72, 0x10, 0x00, 0x00, 0x00, 0x10, 0x00 }
e1bc80ad 479 },
9bc7400a 480#if 0
6ac48b45
MCC		 481 {0x050, /* Teletext, PAL, WST System C */
482 {V4L2_SLICED_TELETEXT_PAL_C,6,22,1},
483 { 0xaa, 0xaa, 0xff, 0xff, 0xe7, 0x2e, 0x20, 0x22,
484 0xa6, 0x98, 0x0d, 0x00, 0x00, 0x00, 0x10, 0x00 }
e1bc80ad 485 },
6ac48b45
MCC		 486 {0x070, /* Teletext, NTSC, WST System B */
487 {V4L2_SLICED_TELETEXT_NTSC_B,10,21,1},
488 { 0xaa, 0xaa, 0xff, 0xff, 0x27, 0x2e, 0x20, 0x23,
489 0x69, 0x93, 0x0d, 0x00, 0x00, 0x00, 0x10, 0x00 }
e1bc80ad 490 },
6ac48b45
MCC		 491 {0x090, /* Tetetext, NTSC NABTS System C */
492 {V4L2_SLICED_TELETEXT_NTSC_C,10,21,1},
493 { 0xaa, 0xaa, 0xff, 0xff, 0xe7, 0x2e, 0x20, 0x22,
494 0x69, 0x93, 0x0d, 0x00, 0x00, 0x00, 0x15, 0x00 }
e1bc80ad 495 },
6ac48b45
MCC		 496 {0x0b0, /* Teletext, NTSC-J, NABTS System D */
497 {V4L2_SLICED_TELETEXT_NTSC_D,10,21,1},
498 { 0xaa, 0xaa, 0xff, 0xff, 0xa7, 0x2e, 0x20, 0x23,
499 0x69, 0x93, 0x0d, 0x00, 0x00, 0x00, 0x10, 0x00 }
e1bc80ad 500 },
6ac48b45
MCC		 501 {0x0d0, /* Closed Caption, PAL/SECAM */
502 {V4L2_SLICED_CAPTION_625,22,22,1},
503 { 0xaa, 0x2a, 0xff, 0x3f, 0x04, 0x51, 0x6e, 0x02,
504 0xa6, 0x7b, 0x09, 0x00, 0x00, 0x00, 0x27, 0x00 }
e1bc80ad 505 },
9bc7400a 506#endif
6ac48b45
MCC		 507 {0x0f0, /* Closed Caption, NTSC */
508 {V4L2_SLICED_CAPTION_525,21,21,1},
509 { 0xaa, 0x2a, 0xff, 0x3f, 0x04, 0x51, 0x6e, 0x02,
510 0x69, 0x8c, 0x09, 0x00, 0x00, 0x00, 0x27, 0x00 }
e1bc80ad 511 },
6ac48b45 512 {0x110, /* Wide Screen Signal, PAL/SECAM */
12db5607 513 {V4L2_SLICED_WSS_625,23,23,1},
6ac48b45
MCC		 514 { 0x5b, 0x55, 0xc5, 0xff, 0x00, 0x71, 0x6e, 0x42,
515 0xa6, 0xcd, 0x0f, 0x00, 0x00, 0x00, 0x3a, 0x00 }
e1bc80ad 516 },
9bc7400a 517#if 0
6ac48b45
MCC		 518 {0x130, /* Wide Screen Signal, NTSC C */
519 {V4L2_SLICED_WSS_525,20,20,1},
520 { 0x38, 0x00, 0x3f, 0x00, 0x00, 0x71, 0x6e, 0x43,
521 0x69, 0x7c, 0x08, 0x00, 0x00, 0x00, 0x39, 0x00 }
e1bc80ad 522 },
6ac48b45
MCC		 523 {0x150, /* Vertical Interval Timecode (VITC), PAL/SECAM */
524 {V4l2_SLICED_VITC_625,6,22,0},
525 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x8f, 0x6d, 0x49,
526 0xa6, 0x85, 0x08, 0x00, 0x00, 0x00, 0x4c, 0x00 }
e1bc80ad 527 },
6ac48b45
MCC		 528 {0x170, /* Vertical Interval Timecode (VITC), NTSC */
529 {V4l2_SLICED_VITC_525,10,20,0},
530 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x8f, 0x6d, 0x49,
531 0x69, 0x94, 0x08, 0x00, 0x00, 0x00, 0x4c, 0x00 }
e1bc80ad 532 },
9bc7400a 533#endif
6ac48b45
MCC		 534 {0x190, /* Video Program System (VPS), PAL */
535 {V4L2_SLICED_VPS,16,16,0},
536 { 0xaa, 0xaa, 0xff, 0xff, 0xba, 0xce, 0x2b, 0x0d,
537 0xa6, 0xda, 0x0b, 0x00, 0x00, 0x00, 0x60, 0x00 }
3ad96835 538 },
6ac48b45
MCC		 539 /* 0x1d0 User programmable */
540
541 /* End of struct */
542 { (u16)-1 }
e1bc80ad 543};
4c86f973 544
6b8fe025 545static int tvp5150_write_inittab(struct v4l2_subdev *sd,
6ac48b45 546 const struct i2c_reg_value *regs)
e1bc80ad
MCC		 547{
548 while (regs->reg != 0xff) {
6b8fe025 549 tvp5150_write(sd, regs->reg, regs->value);
e1bc80ad
MCC		 550 regs++;
551 }
552 return 0;
553}
84486d53 554
6b8fe025 555static int tvp5150_vdp_init(struct v4l2_subdev *sd,
6ac48b45 556 const struct i2c_vbi_ram_value *regs)
e1bc80ad
MCC		 557{
558 unsigned int i;
cd4665c5 559
e1bc80ad 560 /* Disable Full Field */
6b8fe025 561 tvp5150_write(sd, TVP5150_FULL_FIELD_ENA, 0);
cd4665c5 562
e1bc80ad 563 /* Before programming, Line mode should be at 0xff */
6b8fe025
HV		 564 for (i = TVP5150_LINE_MODE_INI; i <= TVP5150_LINE_MODE_END; i++)
565 tvp5150_write(sd, i, 0xff);
cd4665c5 566
e1bc80ad 567 /* Load Ram Table */
6b8fe025
HV		 568 while (regs->reg != (u16)-1) {
569 tvp5150_write(sd, TVP5150_CONF_RAM_ADDR_HIGH, regs->reg >> 8);
570 tvp5150_write(sd, TVP5150_CONF_RAM_ADDR_LOW, regs->reg);
cd4665c5 571
6b8fe025
HV		 572 for (i = 0; i < 16; i++)
573 tvp5150_write(sd, TVP5150_VDP_CONF_RAM_DATA, regs->values[i]);
84486d53 574
e1bc80ad
MCC		 575 regs++;
576 }
577 return 0;
578}
cd4665c5 579
6ac48b45 580/* Fills VBI capabilities based on i2c_vbi_ram_value struct */
6b8fe025 581static int tvp5150_g_sliced_vbi_cap(struct v4l2_subdev *sd,
6ac48b45
MCC		 582 struct v4l2_sliced_vbi_cap *cap)
583{
6b8fe025 584 const struct i2c_vbi_ram_value *regs = vbi_ram_default;
6ac48b45
MCC		 585 int line;
586
bccfa449 587 v4l2_dbg(1, debug, sd, "g_sliced_vbi_cap\n");
6ac48b45
MCC		 588 memset(cap, 0, sizeof *cap);
589
590 while (regs->reg != (u16)-1 ) {
591 for (line=regs->type.ini_line;line<=regs->type.end_line;line++) {
592 cap->service_lines[0][line] |= regs->type.vbi_type;
593 }
594 cap->service_set |= regs->type.vbi_type;
595
596 regs++;
597 }
6b8fe025 598 return 0;
6ac48b45
MCC		 599}
600
3ad96835
MCC		 601/* Set vbi processing
602 * type - one of tvp5150_vbi_types
603 * line - line to gather data
604 * fields: bit 0 field1, bit 1, field2
605 * flags (default=0xf0) is a bitmask, were set means:
606 * bit 7: enable filtering null bytes on CC
607 * bit 6: send data also to FIFO
608 * bit 5: don't allow data with errors on FIFO
609 * bit 4: enable ECC when possible
610 * pix_align = pix alignment:
611 * LSB = field1
612 * MSB = field2
613 */
6b8fe025 614static int tvp5150_set_vbi(struct v4l2_subdev *sd,
2701dacb
MCC		 615 const struct i2c_vbi_ram_value *regs,
616 unsigned int type,u8 flags, int line,
617 const int fields)
3ad96835 618{
6b8fe025
HV		 619 struct tvp5150 *decoder = to_tvp5150(sd);
620 v4l2_std_id std = decoder->norm;
3ad96835 621 u8 reg;
2701dacb 622 int pos=0;
3ad96835
MCC		 623
624 if (std == V4L2_STD_ALL) {
6b8fe025 625 v4l2_err(sd, "VBI can't be configured without knowing number of lines\n");
12db5607 626 return 0;
7d5b7b98 627 } else if (std & V4L2_STD_625_50) {
3ad96835
MCC		 628 /* Don't follow NTSC Line number convension */
629 line += 3;
630 }
631
632 if (line<6||line>27)
2701dacb
MCC		 633 return 0;
634
635 while (regs->reg != (u16)-1 ) {
636 if ((type & regs->type.vbi_type) &&
637 (line>=regs->type.ini_line) &&
638 (line<=regs->type.end_line)) {
639 type=regs->type.vbi_type;
640 break;
641 }
642
643 regs++;
644 pos++;
645 }
646 if (regs->reg == (u16)-1)
647 return 0;
3ad96835 648
2701dacb 649 type=pos | (flags & 0xf0);
3ad96835
MCC		 650 reg=((line-6)<<1)+TVP5150_LINE_MODE_INI;
651
652 if (fields&1) {
6b8fe025 653 tvp5150_write(sd, reg, type);
3ad96835
MCC		 654 }
655
656 if (fields&2) {
6b8fe025 657 tvp5150_write(sd, reg+1, type);
3ad96835
MCC		 658 }
659
2701dacb 660 return type;
3ad96835
MCC		 661}
662
6b8fe025 663static int tvp5150_get_vbi(struct v4l2_subdev *sd,
12db5607
MCC		 664 const struct i2c_vbi_ram_value *regs, int line)
665{
6b8fe025
HV		 666 struct tvp5150 *decoder = to_tvp5150(sd);
667 v4l2_std_id std = decoder->norm;
12db5607 668 u8 reg;
6b8fe025 669 int pos, type = 0;
12db5607
MCC		 670
671 if (std == V4L2_STD_ALL) {
6b8fe025 672 v4l2_err(sd, "VBI can't be configured without knowing number of lines\n");
12db5607 673 return 0;
7d5b7b98 674 } else if (std & V4L2_STD_625_50) {
12db5607
MCC		 675 /* Don't follow NTSC Line number convension */
676 line += 3;
677 }
678
6b8fe025 679 if (line < 6 || line > 27)
12db5607
MCC		 680 return 0;
681
6b8fe025 682 reg = ((line - 6) << 1) + TVP5150_LINE_MODE_INI;
12db5607 683
6b8fe025
HV		 684 pos = tvp5150_read(sd, reg) & 0x0f;
685 if (pos < 0x0f)
686 type = regs[pos].type.vbi_type;
12db5607 687
6b8fe025
HV		 688 pos = tvp5150_read(sd, reg + 1) & 0x0f;
689 if (pos < 0x0f)
690 type |= regs[pos].type.vbi_type;
12db5607
MCC		 691
692 return type;
693}
6b8fe025
HV		 694
695static int tvp5150_set_std(struct v4l2_subdev *sd, v4l2_std_id std)
e1bc80ad 696{
6b8fe025
HV		 697 struct tvp5150 *decoder = to_tvp5150(sd);
698 int fmt = 0;
e1bc80ad 699
6b8fe025 700 decoder->norm = std;
e1bc80ad
MCC		 701
702 /* First tests should be against specific std */
703
704 if (std == V4L2_STD_ALL) {
6b8fe025 705 fmt = 0; /* Autodetect mode */
e1bc80ad 706 } else if (std & V4L2_STD_NTSC_443) {
6b8fe025 707 fmt = 0xa;
e1bc80ad 708 } else if (std & V4L2_STD_PAL_M) {
6b8fe025
HV		 709 fmt = 0x6;
710 } else if (std & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) {
711 fmt = 0x8;
e1bc80ad
MCC		 712 } else {
713 /* Then, test against generic ones */
6b8fe025
HV		 714 if (std & V4L2_STD_NTSC)
715 fmt = 0x2;
716 else if (std & V4L2_STD_PAL)
717 fmt = 0x4;
718 else if (std & V4L2_STD_SECAM)
719 fmt = 0xc;
e1bc80ad 720 }
84486d53 721
6b8fe025
HV		 722 v4l2_dbg(1, debug, sd, "Set video std register to %d.\n", fmt);
723 tvp5150_write(sd, TVP5150_VIDEO_STD, fmt);
e1bc80ad
MCC		 724 return 0;
725}
726
6b8fe025
HV		 727static int tvp5150_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
728{
729 struct tvp5150 *decoder = to_tvp5150(sd);
730
731 if (decoder->norm == std)
732 return 0;
733
734 return tvp5150_set_std(sd, std);
735}
736
737static int tvp5150_reset(struct v4l2_subdev *sd, u32 val)
e1bc80ad 738{
6b8fe025 739 struct tvp5150 *decoder = to_tvp5150(sd);
84486d53 740
e1bc80ad 741 /* Initializes TVP5150 to its default values */
6b8fe025 742 tvp5150_write_inittab(sd, tvp5150_init_default);
e1bc80ad
MCC		 743
744 /* Initializes VDP registers */
6b8fe025 745 tvp5150_vdp_init(sd, vbi_ram_default);
e1bc80ad
MCC		 746
747 /* Selects decoder input */
6b8fe025 748 tvp5150_selmux(sd);
e1bc80ad
MCC		 749
750 /* Initializes TVP5150 to stream enabled values */
6b8fe025 751 tvp5150_write_inittab(sd, tvp5150_init_enable);
e1bc80ad
MCC		 752
753 /* Initialize image preferences */
6c45ec71 754 v4l2_ctrl_handler_setup(&decoder->hdl);
e1bc80ad 755
6b8fe025
HV		 756 tvp5150_set_std(sd, decoder->norm);
757 return 0;
cd4665c5
MCC		 758};
759
6c45ec71 760static int tvp5150_s_ctrl(struct v4l2_ctrl *ctrl)
a6c2ba28 761{
6c45ec71 762 struct v4l2_subdev *sd = to_sd(ctrl);
a6c2ba28
AM		 763
764 switch (ctrl->id) {
765 case V4L2_CID_BRIGHTNESS:
6c45ec71 766 tvp5150_write(sd, TVP5150_BRIGHT_CTL, ctrl->val);
a6c2ba28
AM		 767 return 0;
768 case V4L2_CID_CONTRAST:
6c45ec71 769 tvp5150_write(sd, TVP5150_CONTRAST_CTL, ctrl->val);
a6c2ba28
AM		 770 return 0;
771 case V4L2_CID_SATURATION:
6c45ec71 772 tvp5150_write(sd, TVP5150_SATURATION_CTL, ctrl->val);
a6c2ba28
AM		 773 return 0;
774 case V4L2_CID_HUE:
6c45ec71 775 tvp5150_write(sd, TVP5150_HUE_CTL, ctrl->val);
a6c2ba28 776 return 0;
a6c2ba28 777 }
c0477ad9 778 return -EINVAL;
a6c2ba28
AM		 779}
780
84486d53
MCC		 781/****************************************************************************
782 I2C Command
783 ****************************************************************************/
c7c0b34c 784
5325b427
HV		 785static int tvp5150_s_routing(struct v4l2_subdev *sd,
786 u32 input, u32 output, u32 config)
6b8fe025
HV		 787{
788 struct tvp5150 *decoder = to_tvp5150(sd);
84486d53 789
5325b427
HV		 790 decoder->input = input;
791 decoder->output = output;
6b8fe025
HV		 792 tvp5150_selmux(sd);
793 return 0;
794}
6ac48b45 795
d37dad49
HV		 796static int tvp5150_s_raw_fmt(struct v4l2_subdev *sd, struct v4l2_vbi_format *fmt)
797{
798 /* this is for capturing 36 raw vbi lines
799 if there's a way to cut off the beginning 2 vbi lines
800 with the tvp5150 then the vbi line count could be lowered
801 to 17 lines/field again, although I couldn't find a register
802 which could do that cropping */
803 if (fmt->sample_format == V4L2_PIX_FMT_GREY)
804 tvp5150_write(sd, TVP5150_LUMA_PROC_CTL_1, 0x70);
805 if (fmt->count[0] == 18 && fmt->count[1] == 18) {
806 tvp5150_write(sd, TVP5150_VERT_BLANKING_START, 0x00);
807 tvp5150_write(sd, TVP5150_VERT_BLANKING_STOP, 0x01);
808 }
809 return 0;
810}
811
812static int tvp5150_s_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *svbi)
6b8fe025 813{
6b8fe025
HV		 814 int i;
815
6b8fe025
HV		 816 if (svbi->service_set != 0) {
817 for (i = 0; i <= 23; i++) {
818 svbi->service_lines[1][i] = 0;
819 svbi->service_lines[0][i] =
820 tvp5150_set_vbi(sd, vbi_ram_default,
821 svbi->service_lines[0][i], 0xf0, i, 3);
2c5aacc6 822 }
6b8fe025
HV		 823 /* Enables FIFO */
824 tvp5150_write(sd, TVP5150_FIFO_OUT_CTRL, 1);
825 } else {
826 /* Disables FIFO*/
827 tvp5150_write(sd, TVP5150_FIFO_OUT_CTRL, 0);
12db5607 828
6b8fe025
HV		 829 /* Disable Full Field */
830 tvp5150_write(sd, TVP5150_FULL_FIELD_ENA, 0);
12db5607 831
6b8fe025
HV		 832 /* Disable Line modes */
833 for (i = TVP5150_LINE_MODE_INI; i <= TVP5150_LINE_MODE_END; i++)
834 tvp5150_write(sd, i, 0xff);
12db5607 835 }
6b8fe025
HV		 836 return 0;
837}
12db5607 838
d37dad49
HV		 839static int tvp5150_g_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *svbi)
840{
841 int i, mask = 0;
842
6b8fe025 843 memset(svbi, 0, sizeof(*svbi));
12db5607 844
6b8fe025
HV		 845 for (i = 0; i <= 23; i++) {
846 svbi->service_lines[0][i] =
847 tvp5150_get_vbi(sd, vbi_ram_default, i);
848 mask |= svbi->service_lines[0][i];
2701dacb 849 }
6b8fe025
HV		 850 svbi->service_set = mask;
851 return 0;
852}
853
bc974305 854static int tvp5150_g_chip_ident(struct v4l2_subdev *sd,
aecde8b5 855 struct v4l2_dbg_chip_ident *chip)
bc974305
MCC		 856{
857 int rev;
858 struct i2c_client *client = v4l2_get_subdevdata(sd);
859
860 rev = tvp5150_read(sd, TVP5150_ROM_MAJOR_VER) << 8 |
861 tvp5150_read(sd, TVP5150_ROM_MINOR_VER);
862
863 return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_TVP5150,
864 rev);
865}
866
867
21dcd8cc 868#ifdef CONFIG_VIDEO_ADV_DEBUG
aecde8b5 869static int tvp5150_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
6b8fe025
HV		 870{
871 struct i2c_client *client = v4l2_get_subdevdata(sd);
21dcd8cc 872
aecde8b5 873 if (!v4l2_chip_match_i2c_client(client, &reg->match))
6b8fe025
HV		 874 return -EINVAL;
875 if (!capable(CAP_SYS_ADMIN))
876 return -EPERM;
877 reg->val = tvp5150_read(sd, reg->reg & 0xff);
aecde8b5 878 reg->size = 1;
6b8fe025
HV		 879 return 0;
880}
84486d53 881
aecde8b5 882static int tvp5150_s_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
6b8fe025
HV		 883{
884 struct i2c_client *client = v4l2_get_subdevdata(sd);
84486d53 885
aecde8b5 886 if (!v4l2_chip_match_i2c_client(client, &reg->match))
6b8fe025
HV		 887 return -EINVAL;
888 if (!capable(CAP_SYS_ADMIN))
889 return -EPERM;
890 tvp5150_write(sd, reg->reg & 0xff, reg->val & 0xff);
891 return 0;
892}
893#endif
a6c2ba28 894
6b8fe025
HV		 895static int tvp5150_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
896{
897 int status = tvp5150_read(sd, 0x88);
a6c2ba28 898
6b8fe025
HV		 899 vt->signal = ((status & 0x04) && (status & 0x02)) ? 0xffff : 0x0;
900 return 0;
901}
a6c2ba28 902
6b8fe025
HV		 903/* ----------------------------------------------------------------------- */
904
6c45ec71
HV		 905static const struct v4l2_ctrl_ops tvp5150_ctrl_ops = {
906 .s_ctrl = tvp5150_s_ctrl,
907};
908
6b8fe025
HV		 909static const struct v4l2_subdev_core_ops tvp5150_core_ops = {
910 .log_status = tvp5150_log_status,
6c45ec71
HV		 911 .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
912 .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
913 .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
914 .g_ctrl = v4l2_subdev_g_ctrl,
915 .s_ctrl = v4l2_subdev_s_ctrl,
916 .queryctrl = v4l2_subdev_queryctrl,
917 .querymenu = v4l2_subdev_querymenu,
f41737ec 918 .s_std = tvp5150_s_std,
6b8fe025 919 .reset = tvp5150_reset,
bc974305 920 .g_chip_ident = tvp5150_g_chip_ident,
6b8fe025
HV		 921#ifdef CONFIG_VIDEO_ADV_DEBUG
922 .g_register = tvp5150_g_register,
923 .s_register = tvp5150_s_register,
924#endif
925};
926
927static const struct v4l2_subdev_tuner_ops tvp5150_tuner_ops = {
6b8fe025
HV		 928 .g_tuner = tvp5150_g_tuner,
929};
930
931static const struct v4l2_subdev_video_ops tvp5150_video_ops = {
932 .s_routing = tvp5150_s_routing,
32cd527f
HV		 933};
934
935static const struct v4l2_subdev_vbi_ops tvp5150_vbi_ops = {
6b8fe025 936 .g_sliced_vbi_cap = tvp5150_g_sliced_vbi_cap,
d37dad49
HV		 937 .g_sliced_fmt = tvp5150_g_sliced_fmt,
938 .s_sliced_fmt = tvp5150_s_sliced_fmt,
939 .s_raw_fmt = tvp5150_s_raw_fmt,
6b8fe025
HV		 940};
941
942static const struct v4l2_subdev_ops tvp5150_ops = {
943 .core = &tvp5150_core_ops,
944 .tuner = &tvp5150_tuner_ops,
945 .video = &tvp5150_video_ops,
32cd527f 946 .vbi = &tvp5150_vbi_ops,
6b8fe025
HV		 947};
948
949
cd4665c5
MCC		 950/****************************************************************************
951 I2C Client & Driver
952 ****************************************************************************/
cd4665c5 953
6b8fe025
HV		 954static int tvp5150_probe(struct i2c_client *c,
955 const struct i2c_device_id *id)
cd4665c5 956{
cd4665c5 957 struct tvp5150 *core;
6b8fe025 958 struct v4l2_subdev *sd;
0e09a3c9 959 u8 msb_id, lsb_id, msb_rom, lsb_rom;
cd4665c5
MCC		 960
961 /* Check if the adapter supports the needed features */
6b8fe025 962 if (!i2c_check_functionality(c->adapter,
cd4665c5 963 I2C_FUNC_SMBUS_READ_BYTE | I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
6b8fe025 964 return -EIO;
cd4665c5 965
7408187d 966 core = kzalloc(sizeof(struct tvp5150), GFP_KERNEL);
5fa1247a 967 if (!core) {
cd4665c5
MCC		 968 return -ENOMEM;
969 }
6b8fe025
HV		 970 sd = &core->sd;
971 v4l2_i2c_subdev_init(sd, c, &tvp5150_ops);
972 v4l_info(c, "chip found @ 0x%02x (%s)\n",
973 c->addr << 1, c->adapter->name);
cd4665c5 974
0e09a3c9
MCC		 975 msb_id = tvp5150_read(sd, TVP5150_MSB_DEV_ID);
976 lsb_id = tvp5150_read(sd, TVP5150_LSB_DEV_ID);
977 msb_rom = tvp5150_read(sd, TVP5150_ROM_MAJOR_VER);
978 lsb_rom = tvp5150_read(sd, TVP5150_ROM_MINOR_VER);
979
980 if (msb_rom == 4 && lsb_rom == 0) { /* Is TVP5150AM1 */
981 v4l2_info(sd, "tvp%02x%02xam1 detected.\n", msb_id, lsb_id);
982
983 /* ITU-T BT.656.4 timing */
984 tvp5150_write(sd, TVP5150_REV_SELECT, 0);
985 } else {
986 if (msb_rom == 3 || lsb_rom == 0x21) { /* Is TVP5150A */
987 v4l2_info(sd, "tvp%02x%02xa detected.\n", msb_id, lsb_id);
988 } else {
989 v4l2_info(sd, "*** unknown tvp%02x%02x chip detected.\n",
990 msb_id, lsb_id);
991 v4l2_info(sd, "*** Rom ver is %d.%d\n", msb_rom, lsb_rom);
992 }
993 }
994
3ad96835 995 core->norm = V4L2_STD_ALL; /* Default is autodetect */
5325b427 996 core->input = TVP5150_COMPOSITE1;
4c86f973 997 core->enable = 1;
6c45ec71
HV		 998
999 v4l2_ctrl_handler_init(&core->hdl, 4);
1000 v4l2_ctrl_new_std(&core->hdl, &tvp5150_ctrl_ops,
1001 V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
1002 v4l2_ctrl_new_std(&core->hdl, &tvp5150_ctrl_ops,
1003 V4L2_CID_CONTRAST, 0, 255, 1, 128);
1004 v4l2_ctrl_new_std(&core->hdl, &tvp5150_ctrl_ops,
1005 V4L2_CID_SATURATION, 0, 255, 1, 128);
1006 v4l2_ctrl_new_std(&core->hdl, &tvp5150_ctrl_ops,
1007 V4L2_CID_HUE, -128, 127, 1, 0);
1008 sd->ctrl_handler = &core->hdl;
1009 if (core->hdl.error) {
1010 int err = core->hdl.error;
1011
1012 v4l2_ctrl_handler_free(&core->hdl);
1013 kfree(core);
1014 return err;
1015 }
1016 v4l2_ctrl_handler_setup(&core->hdl);
4c86f973 1017
f1e5ee45 1018 if (debug > 1)
6b8fe025 1019 tvp5150_log_status(sd);
cd4665c5
MCC		 1020 return 0;
1021}
1022
6b8fe025 1023static int tvp5150_remove(struct i2c_client *c)
cd4665c5 1024{
6b8fe025 1025 struct v4l2_subdev *sd = i2c_get_clientdata(c);
6c45ec71 1026 struct tvp5150 *decoder = to_tvp5150(sd);
cd4665c5 1027
6b8fe025 1028 v4l2_dbg(1, debug, sd,
e1bc80ad
MCC		 1029 "tvp5150.c: removing tvp5150 adapter on address 0x%x\n",
1030 c->addr << 1);
1031
6b8fe025 1032 v4l2_device_unregister_subdev(sd);
6c45ec71 1033 v4l2_ctrl_handler_free(&decoder->hdl);
6b8fe025 1034 kfree(to_tvp5150(sd));
cd4665c5
MCC		 1035 return 0;
1036}
1037
1038/* ----------------------------------------------------------------------- */
1039
6b8fe025
HV		 1040static const struct i2c_device_id tvp5150_id[] = {
1041 { "tvp5150", 0 },
1042 { }
1043};
1044MODULE_DEVICE_TABLE(i2c, tvp5150_id);
84486d53 1045
c771145b
HV		 1046static struct i2c_driver tvp5150_driver = {
1047 .driver = {
1048 .owner = THIS_MODULE,
1049 .name = "tvp5150",
1050 },
1051 .probe = tvp5150_probe,
1052 .remove = tvp5150_remove,
1053 .id_table = tvp5150_id,
cd4665c5 1054};
c771145b
HV		 1055
1056static __init int init_tvp5150(void)
1057{
1058 return i2c_add_driver(&tvp5150_driver);
1059}
1060
1061static __exit void exit_tvp5150(void)
1062{
1063 i2c_del_driver(&tvp5150_driver);
1064}
1065
1066module_init(init_tvp5150);
1067module_exit(exit_tvp5150);
kernel source for telekom puls (alcatel/mediatek)