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V4L/DVB (9619): tvaudio: update initial comments
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / media / video / tvaudio.c
CommitLineData
1da177e4 1/*
b4ab114c 2 * Driver for simple i2c audio chips.
1da177e4
LT		 3 *
4 * Copyright (c) 2000 Gerd Knorr
5 * based on code by:
6 * Eric Sandeen (eric_sandeen@bigfoot.com)
7 * Steve VanDeBogart (vandebo@uclink.berkeley.edu)
8 * Greg Alexander (galexand@acm.org)
9 *
b4ab114c
MCC		 10 * Copyright(c) 2005-2008 Mauro Carvalho Chehab
11 * - Some cleanups, code fixes, etc
12 * - Convert it to V4L2 API
13 *
1da177e4
LT		 14 * This code is placed under the terms of the GNU General Public License
15 *
16 * OPTIONS:
17 * debug - set to 1 if you'd like to see debug messages
18 *
19 */
20
1da177e4 21#include <linux/module.h>
1da177e4
LT		 22#include <linux/kernel.h>
23#include <linux/sched.h>
24#include <linux/string.h>
25#include <linux/timer.h>
26#include <linux/delay.h>
27#include <linux/errno.h>
28#include <linux/slab.h>
29#include <linux/videodev.h>
30#include <linux/i2c.h>
1da177e4 31#include <linux/init.h>
bc282879 32#include <linux/kthread.h>
7dfb7103 33#include <linux/freezer.h>
1da177e4 34
8bf2f8e7 35#include <media/tvaudio.h>
5e453dc7 36#include <media/v4l2-common.h>
74cab31c 37#include <media/v4l2-chip-ident.h>
08e14054 38#include <media/v4l2-i2c-drv-legacy.h>
1da177e4 39
7c9b5048 40#include <media/i2c-addr.h>
1da177e4
LT		 41
42/* ---------------------------------------------------------------------- */
43/* insmod args */
44
ff699e6b 45static int debug; /* insmod parameter */
1da177e4
LT		 46module_param(debug, int, 0644);
47
48MODULE_DESCRIPTION("device driver for various i2c TV sound decoder / audiomux chips");
49MODULE_AUTHOR("Eric Sandeen, Steve VanDeBogart, Greg Alexander, Gerd Knorr");
50MODULE_LICENSE("GPL");
51
52#define UNSET (-1U)
18fc59e2 53
1da177e4
LT		 54/* ---------------------------------------------------------------------- */
55/* our structs */
56
57#define MAXREGS 64
58
59struct CHIPSTATE;
60typedef int (*getvalue)(int);
61typedef int (*checkit)(struct CHIPSTATE*);
62typedef int (*initialize)(struct CHIPSTATE*);
63typedef int (*getmode)(struct CHIPSTATE*);
64typedef void (*setmode)(struct CHIPSTATE*, int mode);
1da177e4
LT		 65
66/* i2c command */
67typedef struct AUDIOCMD {
68 int count; /* # of bytes to send */
69 unsigned char bytes[MAXREGS+1]; /* addr, data, data, ... */
70} audiocmd;
71
72/* chip description */
73struct CHIPDESC {
74 char *name; /* chip name */
1da177e4
LT		 75 int addr_lo, addr_hi; /* i2c address range */
76 int registers; /* # of registers */
77
78 int *insmodopt;
79 checkit checkit;
80 initialize initialize;
81 int flags;
82#define CHIP_HAS_VOLUME 1
83#define CHIP_HAS_BASSTREBLE 2
84#define CHIP_HAS_INPUTSEL 4
dd03e970 85#define CHIP_NEED_CHECKMODE 8
1da177e4
LT		 86
87 /* various i2c command sequences */
88 audiocmd init;
89
90 /* which register has which value */
91 int leftreg,rightreg,treblereg,bassreg;
92
93 /* initialize with (defaults to 65535/65535/32768/32768 */
94 int leftinit,rightinit,trebleinit,bassinit;
95
96 /* functions to convert the values (v4l -> chip) */
97 getvalue volfunc,treblefunc,bassfunc;
98
99 /* get/set mode */
100 getmode getmode;
101 setmode setmode;
102
1da177e4
LT		 103 /* input switch register + values for v4l inputs */
104 int inputreg;
8bf2f8e7 105 int inputmap[4];
1da177e4
LT		 106 int inputmute;
107 int inputmask;
108};
109static struct CHIPDESC chiplist[];
110
111/* current state of the chip */
112struct CHIPSTATE {
08e14054 113 struct i2c_client *c;
1da177e4
LT		 114
115 /* index into CHIPDESC array */
116 int type;
117
118 /* shadow register set */
119 audiocmd shadow;
120
121 /* current settings */
8bf2f8e7 122 __u16 left,right,treble,bass,muted,mode;
1da177e4 123 int prevmode;
8a854284 124 int radio;
8bf2f8e7 125 int input;
1da177e4
LT		 126
127 /* thread */
bc282879 128 struct task_struct *thread;
1da177e4 129 struct timer_list wt;
1da177e4 130 int watch_stereo;
8a4b275f 131 int audmode;
1da177e4
LT		 132};
133
1da177e4
LT		 134/* ---------------------------------------------------------------------- */
135/* i2c addresses */
136
137static unsigned short normal_i2c[] = {
09df1c16
MCC		 138 I2C_ADDR_TDA8425 >> 1,
139 I2C_ADDR_TEA6300 >> 1,
140 I2C_ADDR_TEA6420 >> 1,
141 I2C_ADDR_TDA9840 >> 1,
142 I2C_ADDR_TDA985x_L >> 1,
143 I2C_ADDR_TDA985x_H >> 1,
144 I2C_ADDR_TDA9874 >> 1,
145 I2C_ADDR_PIC16C54 >> 1,
1da177e4 146 I2C_CLIENT_END };
1da177e4
LT		 147I2C_CLIENT_INSMOD;
148
1da177e4
LT		 149/* ---------------------------------------------------------------------- */
150/* i2c I/O functions */
151
152static int chip_write(struct CHIPSTATE *chip, int subaddr, int val)
153{
154 unsigned char buffer[2];
155
156 if (-1 == subaddr) {
08e14054
HV		 157 v4l_dbg(1, debug, chip->c, "%s: chip_write: 0x%x\n",
158 chip->c->name, val);
1da177e4
LT		 159 chip->shadow.bytes[1] = val;
160 buffer[0] = val;
08e14054
HV		 161 if (1 != i2c_master_send(chip->c,buffer,1)) {
162 v4l_warn(chip->c, "%s: I/O error (write 0x%x)\n",
163 chip->c->name, val);
1da177e4
LT		 164 return -1;
165 }
166 } else {
08e14054
HV		 167 v4l_dbg(1, debug, chip->c, "%s: chip_write: reg%d=0x%x\n",
168 chip->c->name, subaddr, val);
1da177e4
LT		 169 chip->shadow.bytes[subaddr+1] = val;
170 buffer[0] = subaddr;
171 buffer[1] = val;
08e14054
HV		 172 if (2 != i2c_master_send(chip->c,buffer,2)) {
173 v4l_warn(chip->c, "%s: I/O error (write reg%d=0x%x)\n",
174 chip->c->name, subaddr, val);
1da177e4
LT		 175 return -1;
176 }
177 }
178 return 0;
179}
180
181static int chip_write_masked(struct CHIPSTATE *chip, int subaddr, int val, int mask)
182{
183 if (mask != 0) {
184 if (-1 == subaddr) {
185 val = (chip->shadow.bytes[1] & ~mask) | (val & mask);
186 } else {
187 val = (chip->shadow.bytes[subaddr+1] & ~mask) | (val & mask);
188 }
189 }
190 return chip_write(chip, subaddr, val);
191}
192
193static int chip_read(struct CHIPSTATE *chip)
194{
195 unsigned char buffer;
196
08e14054
HV		 197 if (1 != i2c_master_recv(chip->c,&buffer,1)) {
198 v4l_warn(chip->c, "%s: I/O error (read)\n",
199 chip->c->name);
1da177e4
LT		 200 return -1;
201 }
08e14054 202 v4l_dbg(1, debug, chip->c, "%s: chip_read: 0x%x\n",chip->c->name, buffer);
1da177e4
LT		 203 return buffer;
204}
205
206static int chip_read2(struct CHIPSTATE *chip, int subaddr)
207{
18fc59e2
MCC		 208 unsigned char write[1];
209 unsigned char read[1];
210 struct i2c_msg msgs[2] = {
08e14054
HV		 211 { chip->c->addr, 0, 1, write },
212 { chip->c->addr, I2C_M_RD, 1, read }
18fc59e2
MCC		 213 };
214 write[0] = subaddr;
1da177e4 215
08e14054
HV		 216 if (2 != i2c_transfer(chip->c->adapter,msgs,2)) {
217 v4l_warn(chip->c, "%s: I/O error (read2)\n", chip->c->name);
1da177e4
LT		 218 return -1;
219 }
08e14054
HV		 220 v4l_dbg(1, debug, chip->c, "%s: chip_read2: reg%d=0x%x\n",
221 chip->c->name, subaddr,read[0]);
1da177e4
LT		 222 return read[0];
223}
224
225static int chip_cmd(struct CHIPSTATE *chip, char *name, audiocmd *cmd)
226{
227 int i;
228
229 if (0 == cmd->count)
230 return 0;
231
232 /* update our shadow register set; print bytes if (debug > 0) */
08e14054
HV		 233 v4l_dbg(1, debug, chip->c, "%s: chip_cmd(%s): reg=%d, data:",
234 chip->c->name, name,cmd->bytes[0]);
1da177e4 235 for (i = 1; i < cmd->count; i++) {
18fc59e2
MCC		 236 if (debug)
237 printk(" 0x%x",cmd->bytes[i]);
1da177e4
LT		 238 chip->shadow.bytes[i+cmd->bytes[0]] = cmd->bytes[i];
239 }
18fc59e2
MCC		 240 if (debug)
241 printk("\n");
1da177e4
LT		 242
243 /* send data to the chip */
08e14054
HV		 244 if (cmd->count != i2c_master_send(chip->c,cmd->bytes,cmd->count)) {
245 v4l_warn(chip->c, "%s: I/O error (%s)\n", chip->c->name, name);
1da177e4
LT		 246 return -1;
247 }
248 return 0;
249}
250
251/* ---------------------------------------------------------------------- */
252/* kernel thread for doing i2c stuff asyncronly
253 * right now it is used only to check the audio mode (mono/stereo/whatever)
254 * some time after switching to another TV channel, then turn on stereo
255 * if available, ...
256 */
257
258static void chip_thread_wake(unsigned long data)
259{
18fc59e2 260 struct CHIPSTATE *chip = (struct CHIPSTATE*)data;
bc282879 261 wake_up_process(chip->thread);
1da177e4
LT		 262}
263
264static int chip_thread(void *data)
265{
18fc59e2 266 struct CHIPSTATE *chip = data;
1da177e4 267 struct CHIPDESC *desc = chiplist + chip->type;
dd03e970 268 int mode;
1da177e4 269
08e14054 270 v4l_dbg(1, debug, chip->c, "%s: thread started\n", chip->c->name);
83144186 271 set_freezable();
1da177e4 272 for (;;) {
bc282879
CLG		 273 set_current_state(TASK_INTERRUPTIBLE);
274 if (!kthread_should_stop())
1da177e4 275 schedule();
bc282879 276 set_current_state(TASK_RUNNING);
5e50e7a9 277 try_to_freeze();
bc282879 278 if (kthread_should_stop())
1da177e4 279 break;
08e14054 280 v4l_dbg(1, debug, chip->c, "%s: thread wakeup\n", chip->c->name);
1da177e4
LT		 281
282 /* don't do anything for radio or if mode != auto */
8a854284 283 if (chip->radio || chip->mode != 0)
1da177e4
LT		 284 continue;
285
286 /* have a look what's going on */
dd03e970
MCC		 287 mode = desc->getmode(chip);
288 if (mode == chip->prevmode)
289 continue;
290
291 /* chip detected a new audio mode - set it */
292 v4l_dbg(1, debug, chip->c, "%s: thread checkmode\n",
293 chip->c->name);
294
295 chip->prevmode = mode;
296
297 if (mode & V4L2_TUNER_MODE_STEREO)
298 desc->setmode(chip, V4L2_TUNER_MODE_STEREO);
299 if (mode & V4L2_TUNER_MODE_LANG1_LANG2)
300 desc->setmode(chip, V4L2_TUNER_MODE_STEREO);
301 else if (mode & V4L2_TUNER_MODE_LANG1)
302 desc->setmode(chip, V4L2_TUNER_MODE_LANG1);
303 else if (mode & V4L2_TUNER_MODE_LANG2)
304 desc->setmode(chip, V4L2_TUNER_MODE_LANG2);
305 else
306 desc->setmode(chip, V4L2_TUNER_MODE_MONO);
1da177e4
LT		 307
308 /* schedule next check */
09df5cbe 309 mod_timer(&chip->wt, jiffies+msecs_to_jiffies(2000));
1da177e4
LT		 310 }
311
08e14054 312 v4l_dbg(1, debug, chip->c, "%s: thread exiting\n", chip->c->name);
1da177e4
LT		 313 return 0;
314}
315
1da177e4
LT		 316/* ---------------------------------------------------------------------- */
317/* audio chip descriptions - defines+functions for tda9840 */
318
319#define TDA9840_SW 0x00
320#define TDA9840_LVADJ 0x02
321#define TDA9840_STADJ 0x03
322#define TDA9840_TEST 0x04
323
324#define TDA9840_MONO 0x10
325#define TDA9840_STEREO 0x2a
326#define TDA9840_DUALA 0x12
327#define TDA9840_DUALB 0x1e
328#define TDA9840_DUALAB 0x1a
329#define TDA9840_DUALBA 0x16
330#define TDA9840_EXTERNAL 0x7a
331
332#define TDA9840_DS_DUAL 0x20 /* Dual sound identified */
333#define TDA9840_ST_STEREO 0x40 /* Stereo sound identified */
334#define TDA9840_PONRES 0x80 /* Power-on reset detected if = 1 */
335
336#define TDA9840_TEST_INT1SN 0x1 /* Integration time 0.5s when set */
337#define TDA9840_TEST_INTFU 0x02 /* Disables integrator function */
338
339static int tda9840_getmode(struct CHIPSTATE *chip)
340{
341 int val, mode;
342
343 val = chip_read(chip);
dc3d75da 344 mode = V4L2_TUNER_MODE_MONO;
1da177e4 345 if (val & TDA9840_DS_DUAL)
dc3d75da 346 mode |= V4L2_TUNER_MODE_LANG1 | V4L2_TUNER_MODE_LANG2;
1da177e4 347 if (val & TDA9840_ST_STEREO)
dc3d75da 348 mode |= V4L2_TUNER_MODE_STEREO;
1da177e4 349
08e14054 350 v4l_dbg(1, debug, chip->c, "tda9840_getmode(): raw chip read: %d, return: %d\n",
18fc59e2 351 val, mode);
1da177e4
LT		 352 return mode;
353}
354
355static void tda9840_setmode(struct CHIPSTATE *chip, int mode)
356{
357 int update = 1;
358 int t = chip->shadow.bytes[TDA9840_SW + 1] & ~0x7e;
359
360 switch (mode) {
dc3d75da 361 case V4L2_TUNER_MODE_MONO:
1da177e4
LT		 362 t |= TDA9840_MONO;
363 break;
dc3d75da 364 case V4L2_TUNER_MODE_STEREO:
1da177e4
LT		 365 t |= TDA9840_STEREO;
366 break;
dc3d75da 367 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 368 t |= TDA9840_DUALA;
369 break;
dc3d75da 370 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 371 t |= TDA9840_DUALB;
372 break;
373 default:
374 update = 0;
375 }
376
377 if (update)
378 chip_write(chip, TDA9840_SW, t);
379}
380
94f9e56e
HV		 381static int tda9840_checkit(struct CHIPSTATE *chip)
382{
383 int rc;
384 rc = chip_read(chip);
385 /* lower 5 bits should be 0 */
386 return ((rc & 0x1f) == 0) ? 1 : 0;
387}
388
1da177e4
LT		 389/* ---------------------------------------------------------------------- */
390/* audio chip descriptions - defines+functions for tda985x */
391
392/* subaddresses for TDA9855 */
393#define TDA9855_VR 0x00 /* Volume, right */
394#define TDA9855_VL 0x01 /* Volume, left */
395#define TDA9855_BA 0x02 /* Bass */
396#define TDA9855_TR 0x03 /* Treble */
397#define TDA9855_SW 0x04 /* Subwoofer - not connected on DTV2000 */
398
399/* subaddresses for TDA9850 */
400#define TDA9850_C4 0x04 /* Control 1 for TDA9850 */
401
402/* subaddesses for both chips */
403#define TDA985x_C5 0x05 /* Control 2 for TDA9850, Control 1 for TDA9855 */
404#define TDA985x_C6 0x06 /* Control 3 for TDA9850, Control 2 for TDA9855 */
405#define TDA985x_C7 0x07 /* Control 4 for TDA9850, Control 3 for TDA9855 */
406#define TDA985x_A1 0x08 /* Alignment 1 for both chips */
407#define TDA985x_A2 0x09 /* Alignment 2 for both chips */
408#define TDA985x_A3 0x0a /* Alignment 3 for both chips */
409
410/* Masks for bits in TDA9855 subaddresses */
411/* 0x00 - VR in TDA9855 */
412/* 0x01 - VL in TDA9855 */
413/* lower 7 bits control gain from -71dB (0x28) to 16dB (0x7f)
414 * in 1dB steps - mute is 0x27 */
415
416
417/* 0x02 - BA in TDA9855 */
418/* lower 5 bits control bass gain from -12dB (0x06) to 16.5dB (0x19)
419 * in .5dB steps - 0 is 0x0E */
420
421
422/* 0x03 - TR in TDA9855 */
423/* 4 bits << 1 control treble gain from -12dB (0x3) to 12dB (0xb)
424 * in 3dB steps - 0 is 0x7 */
425
426/* Masks for bits in both chips' subaddresses */
427/* 0x04 - SW in TDA9855, C4/Control 1 in TDA9850 */
428/* Unique to TDA9855: */
429/* 4 bits << 2 control subwoofer/surround gain from -14db (0x1) to 14db (0xf)
430 * in 3dB steps - mute is 0x0 */
431
432/* Unique to TDA9850: */
433/* lower 4 bits control stereo noise threshold, over which stereo turns off
434 * set to values of 0x00 through 0x0f for Ster1 through Ster16 */
435
436
437/* 0x05 - C5 - Control 1 in TDA9855 , Control 2 in TDA9850*/
438/* Unique to TDA9855: */
439#define TDA9855_MUTE 1<<7 /* GMU, Mute at outputs */
440#define TDA9855_AVL 1<<6 /* AVL, Automatic Volume Level */
441#define TDA9855_LOUD 1<<5 /* Loudness, 1==off */
442#define TDA9855_SUR 1<<3 /* Surround / Subwoofer 1==.5(L-R) 0==.5(L+R) */
443 /* Bits 0 to 3 select various combinations
4ac97914
MCC		 444 * of line in and line out, only the
445 * interesting ones are defined */
1da177e4
LT		 446#define TDA9855_EXT 1<<2 /* Selects inputs LIR and LIL. Pins 41 & 12 */
447#define TDA9855_INT 0 /* Selects inputs LOR and LOL. (internal) */
448
449/* Unique to TDA9850: */
450/* lower 4 bits contol SAP noise threshold, over which SAP turns off
451 * set to values of 0x00 through 0x0f for SAP1 through SAP16 */
452
453
454/* 0x06 - C6 - Control 2 in TDA9855, Control 3 in TDA9850 */
455/* Common to TDA9855 and TDA9850: */
456#define TDA985x_SAP 3<<6 /* Selects SAP output, mute if not received */
457#define TDA985x_STEREO 1<<6 /* Selects Stereo ouput, mono if not received */
458#define TDA985x_MONO 0 /* Forces Mono output */
459#define TDA985x_LMU 1<<3 /* Mute (LOR/LOL for 9855, OUTL/OUTR for 9850) */
460
461/* Unique to TDA9855: */
462#define TDA9855_TZCM 1<<5 /* If set, don't mute till zero crossing */
463#define TDA9855_VZCM 1<<4 /* If set, don't change volume till zero crossing*/
464#define TDA9855_LINEAR 0 /* Linear Stereo */
465#define TDA9855_PSEUDO 1 /* Pseudo Stereo */
466#define TDA9855_SPAT_30 2 /* Spatial Stereo, 30% anti-phase crosstalk */
467#define TDA9855_SPAT_50 3 /* Spatial Stereo, 52% anti-phase crosstalk */
468#define TDA9855_E_MONO 7 /* Forced mono - mono select elseware, so useless*/
469
470/* 0x07 - C7 - Control 3 in TDA9855, Control 4 in TDA9850 */
471/* Common to both TDA9855 and TDA9850: */
472/* lower 4 bits control input gain from -3.5dB (0x0) to 4dB (0xF)
473 * in .5dB steps - 0dB is 0x7 */
474
475/* 0x08, 0x09 - A1 and A2 (read/write) */
476/* Common to both TDA9855 and TDA9850: */
477/* lower 5 bites are wideband and spectral expander alignment
478 * from 0x00 to 0x1f - nominal at 0x0f and 0x10 (read/write) */
479#define TDA985x_STP 1<<5 /* Stereo Pilot/detect (read-only) */
480#define TDA985x_SAPP 1<<6 /* SAP Pilot/detect (read-only) */
481#define TDA985x_STS 1<<7 /* Stereo trigger 1= <35mV 0= <30mV (write-only)*/
482
483/* 0x0a - A3 */
484/* Common to both TDA9855 and TDA9850: */
485/* lower 3 bits control timing current for alignment: -30% (0x0), -20% (0x1),
486 * -10% (0x2), nominal (0x3), +10% (0x6), +20% (0x5), +30% (0x4) */
487#define TDA985x_ADJ 1<<7 /* Stereo adjust on/off (wideband and spectral */
488
489static int tda9855_volume(int val) { return val/0x2e8+0x27; }
490static int tda9855_bass(int val) { return val/0xccc+0x06; }
491static int tda9855_treble(int val) { return (val/0x1c71+0x3)<<1; }
492
493static int tda985x_getmode(struct CHIPSTATE *chip)
494{
495 int mode;
496
497 mode = ((TDA985x_STP | TDA985x_SAPP) &
498 chip_read(chip)) >> 4;
499 /* Add mono mode regardless of SAP and stereo */
500 /* Allows forced mono */
dc3d75da 501 return mode | V4L2_TUNER_MODE_MONO;
1da177e4
LT		 502}
503
504static void tda985x_setmode(struct CHIPSTATE *chip, int mode)
505{
506 int update = 1;
507 int c6 = chip->shadow.bytes[TDA985x_C6+1] & 0x3f;
508
509 switch (mode) {
dc3d75da 510 case V4L2_TUNER_MODE_MONO:
1da177e4
LT		 511 c6 |= TDA985x_MONO;
512 break;
dc3d75da 513 case V4L2_TUNER_MODE_STEREO:
1da177e4
LT		 514 c6 |= TDA985x_STEREO;
515 break;
dc3d75da 516 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 517 c6 |= TDA985x_SAP;
518 break;
519 default:
520 update = 0;
521 }
522 if (update)
523 chip_write(chip,TDA985x_C6,c6);
524}
525
526
527/* ---------------------------------------------------------------------- */
528/* audio chip descriptions - defines+functions for tda9873h */
529
530/* Subaddresses for TDA9873H */
531
532#define TDA9873_SW 0x00 /* Switching */
533#define TDA9873_AD 0x01 /* Adjust */
534#define TDA9873_PT 0x02 /* Port */
535
536/* Subaddress 0x00: Switching Data
537 * B7..B0:
538 *
539 * B1, B0: Input source selection
540 * 0, 0 internal
541 * 1, 0 external stereo
542 * 0, 1 external mono
543 */
544#define TDA9873_INP_MASK 3
545#define TDA9873_INTERNAL 0
546#define TDA9873_EXT_STEREO 2
547#define TDA9873_EXT_MONO 1
548
549/* B3, B2: output signal select
550 * B4 : transmission mode
551 * 0, 0, 1 Mono
552 * 1, 0, 0 Stereo
553 * 1, 1, 1 Stereo (reversed channel)
554 * 0, 0, 0 Dual AB
555 * 0, 0, 1 Dual AA
556 * 0, 1, 0 Dual BB
557 * 0, 1, 1 Dual BA
558 */
559
560#define TDA9873_TR_MASK (7 << 2)
561#define TDA9873_TR_MONO 4
562#define TDA9873_TR_STEREO 1 << 4
563#define TDA9873_TR_REVERSE (1 << 3) & (1 << 2)
564#define TDA9873_TR_DUALA 1 << 2
565#define TDA9873_TR_DUALB 1 << 3
566
567/* output level controls
568 * B5: output level switch (0 = reduced gain, 1 = normal gain)
569 * B6: mute (1 = muted)
570 * B7: auto-mute (1 = auto-mute enabled)
571 */
572
573#define TDA9873_GAIN_NORMAL 1 << 5
574#define TDA9873_MUTE 1 << 6
575#define TDA9873_AUTOMUTE 1 << 7
576
577/* Subaddress 0x01: Adjust/standard */
578
579/* Lower 4 bits (C3..C0) control stereo adjustment on R channel (-0.6 - +0.7 dB)
580 * Recommended value is +0 dB
581 */
582
583#define TDA9873_STEREO_ADJ 0x06 /* 0dB gain */
584
585/* Bits C6..C4 control FM stantard
586 * C6, C5, C4
587 * 0, 0, 0 B/G (PAL FM)
588 * 0, 0, 1 M
589 * 0, 1, 0 D/K(1)
590 * 0, 1, 1 D/K(2)
591 * 1, 0, 0 D/K(3)
592 * 1, 0, 1 I
593 */
594#define TDA9873_BG 0
595#define TDA9873_M 1
596#define TDA9873_DK1 2
597#define TDA9873_DK2 3
598#define TDA9873_DK3 4
599#define TDA9873_I 5
600
601/* C7 controls identification response time (1=fast/0=normal)
602 */
603#define TDA9873_IDR_NORM 0
604#define TDA9873_IDR_FAST 1 << 7
605
606
607/* Subaddress 0x02: Port data */
608
609/* E1, E0 free programmable ports P1/P2
610 0, 0 both ports low
611 0, 1 P1 high
612 1, 0 P2 high
613 1, 1 both ports high
614*/
615
616#define TDA9873_PORTS 3
617
618/* E2: test port */
619#define TDA9873_TST_PORT 1 << 2
620
621/* E5..E3 control mono output channel (together with transmission mode bit B4)
622 *
623 * E5 E4 E3 B4 OUTM
624 * 0 0 0 0 mono
625 * 0 0 1 0 DUAL B
626 * 0 1 0 1 mono (from stereo decoder)
627 */
628#define TDA9873_MOUT_MONO 0
629#define TDA9873_MOUT_FMONO 0
630#define TDA9873_MOUT_DUALA 0
631#define TDA9873_MOUT_DUALB 1 << 3
632#define TDA9873_MOUT_ST 1 << 4
633#define TDA9873_MOUT_EXTM (1 << 4 ) & (1 << 3)
634#define TDA9873_MOUT_EXTL 1 << 5
635#define TDA9873_MOUT_EXTR (1 << 5 ) & (1 << 3)
636#define TDA9873_MOUT_EXTLR (1 << 5 ) & (1 << 4)
637#define TDA9873_MOUT_MUTE (1 << 5 ) & (1 << 4) & (1 << 3)
638
639/* Status bits: (chip read) */
640#define TDA9873_PONR 0 /* Power-on reset detected if = 1 */
641#define TDA9873_STEREO 2 /* Stereo sound is identified */
642#define TDA9873_DUAL 4 /* Dual sound is identified */
643
644static int tda9873_getmode(struct CHIPSTATE *chip)
645{
646 int val,mode;
647
648 val = chip_read(chip);
dc3d75da 649 mode = V4L2_TUNER_MODE_MONO;
1da177e4 650 if (val & TDA9873_STEREO)
dc3d75da 651 mode |= V4L2_TUNER_MODE_STEREO;
1da177e4 652 if (val & TDA9873_DUAL)
dc3d75da 653 mode |= V4L2_TUNER_MODE_LANG1 | V4L2_TUNER_MODE_LANG2;
08e14054 654 v4l_dbg(1, debug, chip->c, "tda9873_getmode(): raw chip read: %d, return: %d\n",
18fc59e2 655 val, mode);
1da177e4
LT		 656 return mode;
657}
658
659static void tda9873_setmode(struct CHIPSTATE *chip, int mode)
660{
661 int sw_data = chip->shadow.bytes[TDA9873_SW+1] & ~ TDA9873_TR_MASK;
662 /* int adj_data = chip->shadow.bytes[TDA9873_AD+1] ; */
663
664 if ((sw_data & TDA9873_INP_MASK) != TDA9873_INTERNAL) {
08e14054 665 v4l_dbg(1, debug, chip->c, "tda9873_setmode(): external input\n");
1da177e4
LT		 666 return;
667 }
668
08e14054
HV		 669 v4l_dbg(1, debug, chip->c, "tda9873_setmode(): chip->shadow.bytes[%d] = %d\n", TDA9873_SW+1, chip->shadow.bytes[TDA9873_SW+1]);
670 v4l_dbg(1, debug, chip->c, "tda9873_setmode(): sw_data = %d\n", sw_data);
1da177e4
LT		 671
672 switch (mode) {
dc3d75da 673 case V4L2_TUNER_MODE_MONO:
1da177e4
LT		 674 sw_data |= TDA9873_TR_MONO;
675 break;
dc3d75da 676 case V4L2_TUNER_MODE_STEREO:
1da177e4
LT		 677 sw_data |= TDA9873_TR_STEREO;
678 break;
dc3d75da 679 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 680 sw_data |= TDA9873_TR_DUALA;
681 break;
dc3d75da 682 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 683 sw_data |= TDA9873_TR_DUALB;
684 break;
685 default:
686 chip->mode = 0;
687 return;
688 }
689
690 chip_write(chip, TDA9873_SW, sw_data);
08e14054 691 v4l_dbg(1, debug, chip->c, "tda9873_setmode(): req. mode %d; chip_write: %d\n",
1da177e4
LT		 692 mode, sw_data);
693}
694
695static int tda9873_checkit(struct CHIPSTATE *chip)
696{
697 int rc;
698
699 if (-1 == (rc = chip_read2(chip,254)))
700 return 0;
701 return (rc & ~0x1f) == 0x80;
702}
703
704
705/* ---------------------------------------------------------------------- */
706/* audio chip description - defines+functions for tda9874h and tda9874a */
707/* Dariusz Kowalewski <darekk@automex.pl> */
708
709/* Subaddresses for TDA9874H and TDA9874A (slave rx) */
710#define TDA9874A_AGCGR 0x00 /* AGC gain */
711#define TDA9874A_GCONR 0x01 /* general config */
712#define TDA9874A_MSR 0x02 /* monitor select */
713#define TDA9874A_C1FRA 0x03 /* carrier 1 freq. */
714#define TDA9874A_C1FRB 0x04 /* carrier 1 freq. */
715#define TDA9874A_C1FRC 0x05 /* carrier 1 freq. */
716#define TDA9874A_C2FRA 0x06 /* carrier 2 freq. */
717#define TDA9874A_C2FRB 0x07 /* carrier 2 freq. */
718#define TDA9874A_C2FRC 0x08 /* carrier 2 freq. */
719#define TDA9874A_DCR 0x09 /* demodulator config */
720#define TDA9874A_FMER 0x0a /* FM de-emphasis */
721#define TDA9874A_FMMR 0x0b /* FM dematrix */
722#define TDA9874A_C1OLAR 0x0c /* ch.1 output level adj. */
723#define TDA9874A_C2OLAR 0x0d /* ch.2 output level adj. */
724#define TDA9874A_NCONR 0x0e /* NICAM config */
725#define TDA9874A_NOLAR 0x0f /* NICAM output level adj. */
726#define TDA9874A_NLELR 0x10 /* NICAM lower error limit */
727#define TDA9874A_NUELR 0x11 /* NICAM upper error limit */
728#define TDA9874A_AMCONR 0x12 /* audio mute control */
729#define TDA9874A_SDACOSR 0x13 /* stereo DAC output select */
730#define TDA9874A_AOSR 0x14 /* analog output select */
731#define TDA9874A_DAICONR 0x15 /* digital audio interface config */
732#define TDA9874A_I2SOSR 0x16 /* I2S-bus output select */
733#define TDA9874A_I2SOLAR 0x17 /* I2S-bus output level adj. */
734#define TDA9874A_MDACOSR 0x18 /* mono DAC output select (tda9874a) */
735#define TDA9874A_ESP 0xFF /* easy standard progr. (tda9874a) */
736
737/* Subaddresses for TDA9874H and TDA9874A (slave tx) */
738#define TDA9874A_DSR 0x00 /* device status */
739#define TDA9874A_NSR 0x01 /* NICAM status */
740#define TDA9874A_NECR 0x02 /* NICAM error count */
741#define TDA9874A_DR1 0x03 /* add. data LSB */
742#define TDA9874A_DR2 0x04 /* add. data MSB */
743#define TDA9874A_LLRA 0x05 /* monitor level read-out LSB */
744#define TDA9874A_LLRB 0x06 /* monitor level read-out MSB */
745#define TDA9874A_SIFLR 0x07 /* SIF level */
746#define TDA9874A_TR2 252 /* test reg. 2 */
747#define TDA9874A_TR1 253 /* test reg. 1 */
748#define TDA9874A_DIC 254 /* device id. code */
749#define TDA9874A_SIC 255 /* software id. code */
750
751
752static int tda9874a_mode = 1; /* 0: A2, 1: NICAM */
753static int tda9874a_GCONR = 0xc0; /* default config. input pin: SIFSEL=0 */
754static int tda9874a_NCONR = 0x01; /* default NICAM config.: AMSEL=0,AMUTE=1 */
755static int tda9874a_ESP = 0x07; /* default standard: NICAM D/K */
756static int tda9874a_dic = -1; /* device id. code */
757
758/* insmod options for tda9874a */
759static unsigned int tda9874a_SIF = UNSET;
760static unsigned int tda9874a_AMSEL = UNSET;
761static unsigned int tda9874a_STD = UNSET;
762module_param(tda9874a_SIF, int, 0444);
763module_param(tda9874a_AMSEL, int, 0444);
764module_param(tda9874a_STD, int, 0444);
765
766/*
767 * initialization table for tda9874 decoder:
768 * - carrier 1 freq. registers (3 bytes)
769 * - carrier 2 freq. registers (3 bytes)
770 * - demudulator config register
771 * - FM de-emphasis register (slow identification mode)
772 * Note: frequency registers must be written in single i2c transfer.
773 */
774static struct tda9874a_MODES {
775 char *name;
776 audiocmd cmd;
777} tda9874a_modelist[9] = {
04e6f990 778 { "A2, B/G", /* default */
1da177e4
LT		 779 { 9, { TDA9874A_C1FRA, 0x72,0x95,0x55, 0x77,0xA0,0x00, 0x00,0x00 }} },
780 { "A2, M (Korea)",
781 { 9, { TDA9874A_C1FRA, 0x5D,0xC0,0x00, 0x62,0x6A,0xAA, 0x20,0x22 }} },
782 { "A2, D/K (1)",
783 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x82,0x60,0x00, 0x00,0x00 }} },
784 { "A2, D/K (2)",
785 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x8C,0x75,0x55, 0x00,0x00 }} },
786 { "A2, D/K (3)",
787 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x77,0xA0,0x00, 0x00,0x00 }} },
788 { "NICAM, I",
789 { 9, { TDA9874A_C1FRA, 0x7D,0x00,0x00, 0x88,0x8A,0xAA, 0x08,0x33 }} },
790 { "NICAM, B/G",
791 { 9, { TDA9874A_C1FRA, 0x72,0x95,0x55, 0x79,0xEA,0xAA, 0x08,0x33 }} },
04e6f990 792 { "NICAM, D/K",
1da177e4
LT		 793 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x79,0xEA,0xAA, 0x08,0x33 }} },
794 { "NICAM, L",
795 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x79,0xEA,0xAA, 0x09,0x33 }} }
796};
797
798static int tda9874a_setup(struct CHIPSTATE *chip)
799{
800 chip_write(chip, TDA9874A_AGCGR, 0x00); /* 0 dB */
801 chip_write(chip, TDA9874A_GCONR, tda9874a_GCONR);
802 chip_write(chip, TDA9874A_MSR, (tda9874a_mode) ? 0x03:0x02);
803 if(tda9874a_dic == 0x11) {
804 chip_write(chip, TDA9874A_FMMR, 0x80);
805 } else { /* dic == 0x07 */
806 chip_cmd(chip,"tda9874_modelist",&tda9874a_modelist[tda9874a_STD].cmd);
807 chip_write(chip, TDA9874A_FMMR, 0x00);
808 }
809 chip_write(chip, TDA9874A_C1OLAR, 0x00); /* 0 dB */
810 chip_write(chip, TDA9874A_C2OLAR, 0x00); /* 0 dB */
811 chip_write(chip, TDA9874A_NCONR, tda9874a_NCONR);
812 chip_write(chip, TDA9874A_NOLAR, 0x00); /* 0 dB */
813 /* Note: If signal quality is poor you may want to change NICAM */
814 /* error limit registers (NLELR and NUELR) to some greater values. */
815 /* Then the sound would remain stereo, but won't be so clear. */
816 chip_write(chip, TDA9874A_NLELR, 0x14); /* default */
817 chip_write(chip, TDA9874A_NUELR, 0x50); /* default */
818
819 if(tda9874a_dic == 0x11) {
820 chip_write(chip, TDA9874A_AMCONR, 0xf9);
821 chip_write(chip, TDA9874A_SDACOSR, (tda9874a_mode) ? 0x81:0x80);
822 chip_write(chip, TDA9874A_AOSR, 0x80);
823 chip_write(chip, TDA9874A_MDACOSR, (tda9874a_mode) ? 0x82:0x80);
824 chip_write(chip, TDA9874A_ESP, tda9874a_ESP);
825 } else { /* dic == 0x07 */
826 chip_write(chip, TDA9874A_AMCONR, 0xfb);
827 chip_write(chip, TDA9874A_SDACOSR, (tda9874a_mode) ? 0x81:0x80);
18fc59e2 828 chip_write(chip, TDA9874A_AOSR, 0x00); /* or 0x10 */
1da177e4 829 }
08e14054 830 v4l_dbg(1, debug, chip->c, "tda9874a_setup(): %s [0x%02X].\n",
1da177e4
LT		 831 tda9874a_modelist[tda9874a_STD].name,tda9874a_STD);
832 return 1;
833}
834
835static int tda9874a_getmode(struct CHIPSTATE *chip)
836{
837 int dsr,nsr,mode;
838 int necr; /* just for debugging */
839
dc3d75da 840 mode = V4L2_TUNER_MODE_MONO;
1da177e4
LT		 841
842 if(-1 == (dsr = chip_read2(chip,TDA9874A_DSR)))
843 return mode;
844 if(-1 == (nsr = chip_read2(chip,TDA9874A_NSR)))
845 return mode;
846 if(-1 == (necr = chip_read2(chip,TDA9874A_NECR)))
847 return mode;
848
849 /* need to store dsr/nsr somewhere */
850 chip->shadow.bytes[MAXREGS-2] = dsr;
851 chip->shadow.bytes[MAXREGS-1] = nsr;
852
853 if(tda9874a_mode) {
854 /* Note: DSR.RSSF and DSR.AMSTAT bits are also checked.
855 * If NICAM auto-muting is enabled, DSR.AMSTAT=1 indicates
856 * that sound has (temporarily) switched from NICAM to
857 * mono FM (or AM) on 1st sound carrier due to high NICAM bit
858 * error count. So in fact there is no stereo in this case :-(
dc3d75da 859 * But changing the mode to V4L2_TUNER_MODE_MONO would switch
1da177e4
LT		 860 * external 4052 multiplexer in audio_hook().
861 */
1da177e4 862 if(nsr & 0x02) /* NSR.S/MB=1 */
dc3d75da 863 mode |= V4L2_TUNER_MODE_STEREO;
1da177e4 864 if(nsr & 0x01) /* NSR.D/SB=1 */
dc3d75da 865 mode |= V4L2_TUNER_MODE_LANG1 | V4L2_TUNER_MODE_LANG2;
1da177e4
LT		 866 } else {
867 if(dsr & 0x02) /* DSR.IDSTE=1 */
dc3d75da 868 mode |= V4L2_TUNER_MODE_STEREO;
1da177e4 869 if(dsr & 0x04) /* DSR.IDDUA=1 */
dc3d75da 870 mode |= V4L2_TUNER_MODE_LANG1 | V4L2_TUNER_MODE_LANG2;
1da177e4
LT		 871 }
872
08e14054 873 v4l_dbg(1, debug, chip->c, "tda9874a_getmode(): DSR=0x%X, NSR=0x%X, NECR=0x%X, return: %d.\n",
1da177e4
LT		 874 dsr, nsr, necr, mode);
875 return mode;
876}
877
878static void tda9874a_setmode(struct CHIPSTATE *chip, int mode)
879{
880 /* Disable/enable NICAM auto-muting (based on DSR.RSSF status bit). */
881 /* If auto-muting is disabled, we can hear a signal of degrading quality. */
882 if(tda9874a_mode) {
883 if(chip->shadow.bytes[MAXREGS-2] & 0x20) /* DSR.RSSF=1 */
884 tda9874a_NCONR &= 0xfe; /* enable */
885 else
886 tda9874a_NCONR |= 0x01; /* disable */
887 chip_write(chip, TDA9874A_NCONR, tda9874a_NCONR);
888 }
889
890 /* Note: TDA9874A supports automatic FM dematrixing (FMMR register)
891 * and has auto-select function for audio output (AOSR register).
892 * Old TDA9874H doesn't support these features.
893 * TDA9874A also has additional mono output pin (OUTM), which
894 * on same (all?) tv-cards is not used, anyway (as well as MONOIN).
895 */
896 if(tda9874a_dic == 0x11) {
897 int aosr = 0x80;
898 int mdacosr = (tda9874a_mode) ? 0x82:0x80;
899
900 switch(mode) {
dc3d75da
MCC		 901 case V4L2_TUNER_MODE_MONO:
902 case V4L2_TUNER_MODE_STEREO:
1da177e4 903 break;
dc3d75da 904 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 905 aosr = 0x80; /* auto-select, dual A/A */
906 mdacosr = (tda9874a_mode) ? 0x82:0x80;
907 break;
dc3d75da 908 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 909 aosr = 0xa0; /* auto-select, dual B/B */
910 mdacosr = (tda9874a_mode) ? 0x83:0x81;
911 break;
912 default:
913 chip->mode = 0;
914 return;
915 }
916 chip_write(chip, TDA9874A_AOSR, aosr);
917 chip_write(chip, TDA9874A_MDACOSR, mdacosr);
918
08e14054 919 v4l_dbg(1, debug, chip->c, "tda9874a_setmode(): req. mode %d; AOSR=0x%X, MDACOSR=0x%X.\n",
1da177e4
LT		 920 mode, aosr, mdacosr);
921
922 } else { /* dic == 0x07 */
923 int fmmr,aosr;
924
925 switch(mode) {
dc3d75da 926 case V4L2_TUNER_MODE_MONO:
1da177e4
LT		 927 fmmr = 0x00; /* mono */
928 aosr = 0x10; /* A/A */
929 break;
dc3d75da 930 case V4L2_TUNER_MODE_STEREO:
1da177e4
LT		 931 if(tda9874a_mode) {
932 fmmr = 0x00;
933 aosr = 0x00; /* handled by NICAM auto-mute */
934 } else {
935 fmmr = (tda9874a_ESP == 1) ? 0x05 : 0x04; /* stereo */
936 aosr = 0x00;
937 }
938 break;
dc3d75da 939 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 940 fmmr = 0x02; /* dual */
941 aosr = 0x10; /* dual A/A */
942 break;
dc3d75da 943 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 944 fmmr = 0x02; /* dual */
945 aosr = 0x20; /* dual B/B */
946 break;
947 default:
948 chip->mode = 0;
949 return;
950 }
951 chip_write(chip, TDA9874A_FMMR, fmmr);
952 chip_write(chip, TDA9874A_AOSR, aosr);
953
08e14054 954 v4l_dbg(1, debug, chip->c, "tda9874a_setmode(): req. mode %d; FMMR=0x%X, AOSR=0x%X.\n",
1da177e4
LT		 955 mode, fmmr, aosr);
956 }
957}
958
959static int tda9874a_checkit(struct CHIPSTATE *chip)
960{
961 int dic,sic; /* device id. and software id. codes */
962
963 if(-1 == (dic = chip_read2(chip,TDA9874A_DIC)))
964 return 0;
965 if(-1 == (sic = chip_read2(chip,TDA9874A_SIC)))
966 return 0;
967
08e14054 968 v4l_dbg(1, debug, chip->c, "tda9874a_checkit(): DIC=0x%X, SIC=0x%X.\n", dic, sic);
1da177e4
LT		 969
970 if((dic == 0x11)||(dic == 0x07)) {
08e14054 971 v4l_info(chip->c, "found tda9874%s.\n", (dic == 0x11) ? "a":"h");
1da177e4
LT		 972 tda9874a_dic = dic; /* remember device id. */
973 return 1;
974 }
975 return 0; /* not found */
976}
977
978static int tda9874a_initialize(struct CHIPSTATE *chip)
979{
980 if (tda9874a_SIF > 2)
981 tda9874a_SIF = 1;
04e6f990 982 if (tda9874a_STD >= ARRAY_SIZE(tda9874a_modelist))
1da177e4
LT		 983 tda9874a_STD = 0;
984 if(tda9874a_AMSEL > 1)
985 tda9874a_AMSEL = 0;
986
987 if(tda9874a_SIF == 1)
988 tda9874a_GCONR = 0xc0; /* sound IF input 1 */
989 else
990 tda9874a_GCONR = 0xc1; /* sound IF input 2 */
991
992 tda9874a_ESP = tda9874a_STD;
993 tda9874a_mode = (tda9874a_STD < 5) ? 0 : 1;
994
995 if(tda9874a_AMSEL == 0)
996 tda9874a_NCONR = 0x01; /* auto-mute: analog mono input */
997 else
998 tda9874a_NCONR = 0x05; /* auto-mute: 1st carrier FM or AM */
999
1000 tda9874a_setup(chip);
1001 return 0;
1002}
1003
1004
1005/* ---------------------------------------------------------------------- */
1006/* audio chip descriptions - defines+functions for tea6420 */
1007
1008#define TEA6300_VL 0x00 /* volume left */
1009#define TEA6300_VR 0x01 /* volume right */
1010#define TEA6300_BA 0x02 /* bass */
1011#define TEA6300_TR 0x03 /* treble */
1012#define TEA6300_FA 0x04 /* fader control */
1013#define TEA6300_S 0x05 /* switch register */
f2421ca3 1014 /* values for those registers: */
1da177e4
LT		 1015#define TEA6300_S_SA 0x01 /* stereo A input */
1016#define TEA6300_S_SB 0x02 /* stereo B */
1017#define TEA6300_S_SC 0x04 /* stereo C */
1018#define TEA6300_S_GMU 0x80 /* general mute */
1019
1020#define TEA6320_V 0x00 /* volume (0-5)/loudness off (6)/zero crossing mute(7) */
1021#define TEA6320_FFR 0x01 /* fader front right (0-5) */
1022#define TEA6320_FFL 0x02 /* fader front left (0-5) */
1023#define TEA6320_FRR 0x03 /* fader rear right (0-5) */
1024#define TEA6320_FRL 0x04 /* fader rear left (0-5) */
1025#define TEA6320_BA 0x05 /* bass (0-4) */
1026#define TEA6320_TR 0x06 /* treble (0-4) */
1027#define TEA6320_S 0x07 /* switch register */
f2421ca3 1028 /* values for those registers: */
1da177e4
LT		 1029#define TEA6320_S_SA 0x07 /* stereo A input */
1030#define TEA6320_S_SB 0x06 /* stereo B */
1031#define TEA6320_S_SC 0x05 /* stereo C */
1032#define TEA6320_S_SD 0x04 /* stereo D */
1033#define TEA6320_S_GMU 0x80 /* general mute */
1034
1035#define TEA6420_S_SA 0x00 /* stereo A input */
1036#define TEA6420_S_SB 0x01 /* stereo B */
1037#define TEA6420_S_SC 0x02 /* stereo C */
1038#define TEA6420_S_SD 0x03 /* stereo D */
1039#define TEA6420_S_SE 0x04 /* stereo E */
1040#define TEA6420_S_GMU 0x05 /* general mute */
1041
1042static int tea6300_shift10(int val) { return val >> 10; }
1043static int tea6300_shift12(int val) { return val >> 12; }
1044
1045/* Assumes 16bit input (values 0x3f to 0x0c are unique, values less than */
1046/* 0x0c mirror those immediately higher) */
1047static int tea6320_volume(int val) { return (val / (65535/(63-12)) + 12) & 0x3f; }
1048static int tea6320_shift11(int val) { return val >> 11; }
1049static int tea6320_initialize(struct CHIPSTATE * chip)
1050{
1051 chip_write(chip, TEA6320_FFR, 0x3f);
1052 chip_write(chip, TEA6320_FFL, 0x3f);
1053 chip_write(chip, TEA6320_FRR, 0x3f);
1054 chip_write(chip, TEA6320_FRL, 0x3f);
1055
1056 return 0;
1057}
1058
1059
1060/* ---------------------------------------------------------------------- */
1061/* audio chip descriptions - defines+functions for tda8425 */
1062
1063#define TDA8425_VL 0x00 /* volume left */
1064#define TDA8425_VR 0x01 /* volume right */
1065#define TDA8425_BA 0x02 /* bass */
1066#define TDA8425_TR 0x03 /* treble */
1067#define TDA8425_S1 0x08 /* switch functions */
f2421ca3 1068 /* values for those registers: */
1da177e4
LT		 1069#define TDA8425_S1_OFF 0xEE /* audio off (mute on) */
1070#define TDA8425_S1_CH1 0xCE /* audio channel 1 (mute off) - "linear stereo" mode */
1071#define TDA8425_S1_CH2 0xCF /* audio channel 2 (mute off) - "linear stereo" mode */
1072#define TDA8425_S1_MU 0x20 /* mute bit */
1073#define TDA8425_S1_STEREO 0x18 /* stereo bits */
1074#define TDA8425_S1_STEREO_SPATIAL 0x18 /* spatial stereo */
1075#define TDA8425_S1_STEREO_LINEAR 0x08 /* linear stereo */
1076#define TDA8425_S1_STEREO_PSEUDO 0x10 /* pseudo stereo */
1077#define TDA8425_S1_STEREO_MONO 0x00 /* forced mono */
1078#define TDA8425_S1_ML 0x06 /* language selector */
1079#define TDA8425_S1_ML_SOUND_A 0x02 /* sound a */
1080#define TDA8425_S1_ML_SOUND_B 0x04 /* sound b */
1081#define TDA8425_S1_ML_STEREO 0x06 /* stereo */
1082#define TDA8425_S1_IS 0x01 /* channel selector */
1083
1084
1085static int tda8425_shift10(int val) { return (val >> 10) | 0xc0; }
1086static int tda8425_shift12(int val) { return (val >> 12) | 0xf0; }
1087
1088static int tda8425_initialize(struct CHIPSTATE *chip)
1089{
1090 struct CHIPDESC *desc = chiplist + chip->type;
8bf2f8e7
HV		 1091 int inputmap[4] = { /* tuner */ TDA8425_S1_CH2, /* radio */ TDA8425_S1_CH1,
1092 /* extern */ TDA8425_S1_CH1, /* intern */ TDA8425_S1_OFF};
1da177e4 1093
08e14054 1094 if (chip->c->adapter->id == I2C_HW_B_RIVA) {
1da177e4
LT		 1095 memcpy (desc->inputmap, inputmap, sizeof (inputmap));
1096 }
1097 return 0;
1098}
1099
1100static void tda8425_setmode(struct CHIPSTATE *chip, int mode)
1101{
1102 int s1 = chip->shadow.bytes[TDA8425_S1+1] & 0xe1;
1103
dc3d75da 1104 if (mode & V4L2_TUNER_MODE_LANG1) {
1da177e4
LT		 1105 s1 |= TDA8425_S1_ML_SOUND_A;
1106 s1 |= TDA8425_S1_STEREO_PSEUDO;
1107
dc3d75da 1108 } else if (mode & V4L2_TUNER_MODE_LANG2) {
1da177e4
LT		 1109 s1 |= TDA8425_S1_ML_SOUND_B;
1110 s1 |= TDA8425_S1_STEREO_PSEUDO;
1111
1112 } else {
1113 s1 |= TDA8425_S1_ML_STEREO;
1114
dc3d75da 1115 if (mode & V4L2_TUNER_MODE_MONO)
1da177e4 1116 s1 |= TDA8425_S1_STEREO_MONO;
dc3d75da 1117 if (mode & V4L2_TUNER_MODE_STEREO)
1da177e4
LT		 1118 s1 |= TDA8425_S1_STEREO_SPATIAL;
1119 }
1120 chip_write(chip,TDA8425_S1,s1);
1121}
1122
1123
1124/* ---------------------------------------------------------------------- */
1125/* audio chip descriptions - defines+functions for pic16c54 (PV951) */
1126
1127/* the registers of 16C54, I2C sub address. */
1128#define PIC16C54_REG_KEY_CODE 0x01 /* Not use. */
1129#define PIC16C54_REG_MISC 0x02
1130
1131/* bit definition of the RESET register, I2C data. */
1132#define PIC16C54_MISC_RESET_REMOTE_CTL 0x01 /* bit 0, Reset to receive the key */
f2421ca3 1133 /* code of remote controller */
1da177e4
LT		 1134#define PIC16C54_MISC_MTS_MAIN 0x02 /* bit 1 */
1135#define PIC16C54_MISC_MTS_SAP 0x04 /* bit 2 */
1136#define PIC16C54_MISC_MTS_BOTH 0x08 /* bit 3 */
1137#define PIC16C54_MISC_SND_MUTE 0x10 /* bit 4, Mute Audio(Line-in and Tuner) */
1138#define PIC16C54_MISC_SND_NOTMUTE 0x20 /* bit 5 */
1139#define PIC16C54_MISC_SWITCH_TUNER 0x40 /* bit 6 , Switch to Line-in */
1140#define PIC16C54_MISC_SWITCH_LINE 0x80 /* bit 7 , Switch to Tuner */
1141
1142/* ---------------------------------------------------------------------- */
1143/* audio chip descriptions - defines+functions for TA8874Z */
1144
18fc59e2 1145/* write 1st byte */
1da177e4
LT		 1146#define TA8874Z_LED_STE 0x80
1147#define TA8874Z_LED_BIL 0x40
1148#define TA8874Z_LED_EXT 0x20
1149#define TA8874Z_MONO_SET 0x10
1150#define TA8874Z_MUTE 0x08
1151#define TA8874Z_F_MONO 0x04
1152#define TA8874Z_MODE_SUB 0x02
1153#define TA8874Z_MODE_MAIN 0x01
1154
18fc59e2
MCC		 1155/* write 2nd byte */
1156/*#define TA8874Z_TI 0x80 */ /* test mode */
1da177e4
LT		 1157#define TA8874Z_SEPARATION 0x3f
1158#define TA8874Z_SEPARATION_DEFAULT 0x10
1159
18fc59e2 1160/* read */
1da177e4
LT		 1161#define TA8874Z_B1 0x80
1162#define TA8874Z_B0 0x40
1163#define TA8874Z_CHAG_FLAG 0x20
1164
18fc59e2
MCC		 1165/*
1166 * B1 B0
1167 * mono L H
1168 * stereo L L
1169 * BIL H L
1170 */
1da177e4
LT		 1171static int ta8874z_getmode(struct CHIPSTATE *chip)
1172{
1173 int val, mode;
1174
1175 val = chip_read(chip);
dc3d75da 1176 mode = V4L2_TUNER_MODE_MONO;
1da177e4 1177 if (val & TA8874Z_B1){
dc3d75da 1178 mode |= V4L2_TUNER_MODE_LANG1 | V4L2_TUNER_MODE_LANG2;
1da177e4 1179 }else if (!(val & TA8874Z_B0)){
dc3d75da 1180 mode |= V4L2_TUNER_MODE_STEREO;
1da177e4 1181 }
08e14054 1182 /* v4l_dbg(1, debug, chip->c, "ta8874z_getmode(): raw chip read: 0x%02x, return: 0x%02x\n", val, mode); */
1da177e4
LT		 1183 return mode;
1184}
1185
1186static audiocmd ta8874z_stereo = { 2, {0, TA8874Z_SEPARATION_DEFAULT}};
1187static audiocmd ta8874z_mono = {2, { TA8874Z_MONO_SET, TA8874Z_SEPARATION_DEFAULT}};
1188static audiocmd ta8874z_main = {2, { 0, TA8874Z_SEPARATION_DEFAULT}};
1189static audiocmd ta8874z_sub = {2, { TA8874Z_MODE_SUB, TA8874Z_SEPARATION_DEFAULT}};
1190
1191static void ta8874z_setmode(struct CHIPSTATE *chip, int mode)
1192{
1193 int update = 1;
1194 audiocmd *t = NULL;
08e14054 1195 v4l_dbg(1, debug, chip->c, "ta8874z_setmode(): mode: 0x%02x\n", mode);
1da177e4
LT		 1196
1197 switch(mode){
dc3d75da 1198 case V4L2_TUNER_MODE_MONO:
1da177e4
LT		 1199 t = &ta8874z_mono;
1200 break;
dc3d75da 1201 case V4L2_TUNER_MODE_STEREO:
1da177e4
LT		 1202 t = &ta8874z_stereo;
1203 break;
dc3d75da 1204 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 1205 t = &ta8874z_main;
1206 break;
dc3d75da 1207 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 1208 t = &ta8874z_sub;
1209 break;
1210 default:
1211 update = 0;
1212 }
1213
1214 if(update)
1215 chip_cmd(chip, "TA8874Z", t);
1216}
1217
1218static int ta8874z_checkit(struct CHIPSTATE *chip)
1219{
1220 int rc;
1221 rc = chip_read(chip);
1222 return ((rc & 0x1f) == 0x1f) ? 1 : 0;
1223}
1224
1225/* ---------------------------------------------------------------------- */
1226/* audio chip descriptions - struct CHIPDESC */
1227
1228/* insmod options to enable/disable individual audio chips */
52c1da39
AB		 1229static int tda8425 = 1;
1230static int tda9840 = 1;
1231static int tda9850 = 1;
1232static int tda9855 = 1;
1233static int tda9873 = 1;
1234static int tda9874a = 1;
ff699e6b
DSL		 1235static int tea6300; /* default 0 - address clash with msp34xx */
1236static int tea6320; /* default 0 - address clash with msp34xx */
52c1da39
AB		 1237static int tea6420 = 1;
1238static int pic16c54 = 1;
ff699e6b 1239static int ta8874z; /* default 0 - address clash with tda9840 */
1da177e4
LT		 1240
1241module_param(tda8425, int, 0444);
1242module_param(tda9840, int, 0444);
1243module_param(tda9850, int, 0444);
1244module_param(tda9855, int, 0444);
1245module_param(tda9873, int, 0444);
1246module_param(tda9874a, int, 0444);
1247module_param(tea6300, int, 0444);
1248module_param(tea6320, int, 0444);
1249module_param(tea6420, int, 0444);
1250module_param(pic16c54, int, 0444);
1251module_param(ta8874z, int, 0444);
1252
1253static struct CHIPDESC chiplist[] = {
1254 {
1255 .name = "tda9840",
1da177e4 1256 .insmodopt = &tda9840,
09df1c16
MCC		 1257 .addr_lo = I2C_ADDR_TDA9840 >> 1,
1258 .addr_hi = I2C_ADDR_TDA9840 >> 1,
1da177e4 1259 .registers = 5,
dd03e970 1260 .flags = CHIP_NEED_CHECKMODE,
1da177e4 1261
af1a9951 1262 /* callbacks */
94f9e56e 1263 .checkit = tda9840_checkit,
1da177e4
LT		 1264 .getmode = tda9840_getmode,
1265 .setmode = tda9840_setmode,
1da177e4 1266
4ac97914 1267 .init = { 2, { TDA9840_TEST, TDA9840_TEST_INT1SN
1da177e4
LT		 1268 /* ,TDA9840_SW, TDA9840_MONO */} }
1269 },
1270 {
1271 .name = "tda9873h",
1da177e4 1272 .insmodopt = &tda9873,
09df1c16
MCC		 1273 .addr_lo = I2C_ADDR_TDA985x_L >> 1,
1274 .addr_hi = I2C_ADDR_TDA985x_H >> 1,
1da177e4 1275 .registers = 3,
dd03e970 1276 .flags = CHIP_HAS_INPUTSEL | CHIP_NEED_CHECKMODE,
1da177e4 1277
af1a9951
MCC		 1278 /* callbacks */
1279 .checkit = tda9873_checkit,
1da177e4
LT		 1280 .getmode = tda9873_getmode,
1281 .setmode = tda9873_setmode,
1da177e4
LT		 1282
1283 .init = { 4, { TDA9873_SW, 0xa4, 0x06, 0x03 } },
1284 .inputreg = TDA9873_SW,
1285 .inputmute = TDA9873_MUTE | TDA9873_AUTOMUTE,
8bf2f8e7 1286 .inputmap = {0xa0, 0xa2, 0xa0, 0xa0},
1da177e4
LT		 1287 .inputmask = TDA9873_INP_MASK|TDA9873_MUTE|TDA9873_AUTOMUTE,
1288
1289 },
1290 {
1291 .name = "tda9874h/a",
1da177e4 1292 .insmodopt = &tda9874a,
09df1c16
MCC		 1293 .addr_lo = I2C_ADDR_TDA9874 >> 1,
1294 .addr_hi = I2C_ADDR_TDA9874 >> 1,
dd03e970 1295 .flags = CHIP_NEED_CHECKMODE,
1da177e4 1296
af1a9951
MCC		 1297 /* callbacks */
1298 .initialize = tda9874a_initialize,
1299 .checkit = tda9874a_checkit,
1da177e4
LT		 1300 .getmode = tda9874a_getmode,
1301 .setmode = tda9874a_setmode,
1da177e4
LT		 1302 },
1303 {
1304 .name = "tda9850",
1da177e4 1305 .insmodopt = &tda9850,
09df1c16
MCC		 1306 .addr_lo = I2C_ADDR_TDA985x_L >> 1,
1307 .addr_hi = I2C_ADDR_TDA985x_H >> 1,
1da177e4
LT		 1308 .registers = 11,
1309
1310 .getmode = tda985x_getmode,
1311 .setmode = tda985x_setmode,
1312
1313 .init = { 8, { TDA9850_C4, 0x08, 0x08, TDA985x_STEREO, 0x07, 0x10, 0x10, 0x03 } }
1314 },
1315 {
1316 .name = "tda9855",
1da177e4 1317 .insmodopt = &tda9855,
09df1c16
MCC		 1318 .addr_lo = I2C_ADDR_TDA985x_L >> 1,
1319 .addr_hi = I2C_ADDR_TDA985x_H >> 1,
1da177e4
LT		 1320 .registers = 11,
1321 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE,
1322
1323 .leftreg = TDA9855_VL,
1324 .rightreg = TDA9855_VR,
1325 .bassreg = TDA9855_BA,
1326 .treblereg = TDA9855_TR,
af1a9951
MCC		 1327
1328 /* callbacks */
1da177e4
LT		 1329 .volfunc = tda9855_volume,
1330 .bassfunc = tda9855_bass,
1331 .treblefunc = tda9855_treble,
1da177e4
LT		 1332 .getmode = tda985x_getmode,
1333 .setmode = tda985x_setmode,
1334
1335 .init = { 12, { 0, 0x6f, 0x6f, 0x0e, 0x07<<1, 0x8<<2,
1336 TDA9855_MUTE | TDA9855_AVL | TDA9855_LOUD | TDA9855_INT,
1337 TDA985x_STEREO | TDA9855_LINEAR | TDA9855_TZCM | TDA9855_VZCM,
1338 0x07, 0x10, 0x10, 0x03 }}
1339 },
1340 {
1341 .name = "tea6300",
1da177e4 1342 .insmodopt = &tea6300,
09df1c16
MCC		 1343 .addr_lo = I2C_ADDR_TEA6300 >> 1,
1344 .addr_hi = I2C_ADDR_TEA6300 >> 1,
1da177e4
LT		 1345 .registers = 6,
1346 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE | CHIP_HAS_INPUTSEL,
1347
1348 .leftreg = TEA6300_VR,
1349 .rightreg = TEA6300_VL,
1350 .bassreg = TEA6300_BA,
1351 .treblereg = TEA6300_TR,
af1a9951
MCC		 1352
1353 /* callbacks */
1da177e4
LT		 1354 .volfunc = tea6300_shift10,
1355 .bassfunc = tea6300_shift12,
1356 .treblefunc = tea6300_shift12,
1357
1358 .inputreg = TEA6300_S,
1359 .inputmap = { TEA6300_S_SA, TEA6300_S_SB, TEA6300_S_SC },
1360 .inputmute = TEA6300_S_GMU,
1361 },
1362 {
1363 .name = "tea6320",
1da177e4 1364 .insmodopt = &tea6320,
09df1c16
MCC		 1365 .addr_lo = I2C_ADDR_TEA6300 >> 1,
1366 .addr_hi = I2C_ADDR_TEA6300 >> 1,
1da177e4
LT		 1367 .registers = 8,
1368 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE | CHIP_HAS_INPUTSEL,
1369
1370 .leftreg = TEA6320_V,
1371 .rightreg = TEA6320_V,
1372 .bassreg = TEA6320_BA,
1373 .treblereg = TEA6320_TR,
af1a9951
MCC		 1374
1375 /* callbacks */
1376 .initialize = tea6320_initialize,
1da177e4
LT		 1377 .volfunc = tea6320_volume,
1378 .bassfunc = tea6320_shift11,
1379 .treblefunc = tea6320_shift11,
1380
1381 .inputreg = TEA6320_S,
1382 .inputmap = { TEA6320_S_SA, TEA6420_S_SB, TEA6300_S_SC, TEA6320_S_SD },
1383 .inputmute = TEA6300_S_GMU,
1384 },
1385 {
1386 .name = "tea6420",
1da177e4 1387 .insmodopt = &tea6420,
09df1c16
MCC		 1388 .addr_lo = I2C_ADDR_TEA6420 >> 1,
1389 .addr_hi = I2C_ADDR_TEA6420 >> 1,
1da177e4
LT		 1390 .registers = 1,
1391 .flags = CHIP_HAS_INPUTSEL,
1392
1393 .inputreg = -1,
1394 .inputmap = { TEA6420_S_SA, TEA6420_S_SB, TEA6420_S_SC },
1395 .inputmute = TEA6300_S_GMU,
1396 },
1397 {
1398 .name = "tda8425",
1da177e4 1399 .insmodopt = &tda8425,
09df1c16
MCC		 1400 .addr_lo = I2C_ADDR_TDA8425 >> 1,
1401 .addr_hi = I2C_ADDR_TDA8425 >> 1,
1da177e4
LT		 1402 .registers = 9,
1403 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE | CHIP_HAS_INPUTSEL,
1404
1405 .leftreg = TDA8425_VL,
1406 .rightreg = TDA8425_VR,
1407 .bassreg = TDA8425_BA,
1408 .treblereg = TDA8425_TR,
af1a9951
MCC		 1409
1410 /* callbacks */
1411 .initialize = tda8425_initialize,
1da177e4
LT		 1412 .volfunc = tda8425_shift10,
1413 .bassfunc = tda8425_shift12,
1414 .treblefunc = tda8425_shift12,
af1a9951 1415 .setmode = tda8425_setmode,
1da177e4
LT		 1416
1417 .inputreg = TDA8425_S1,
1418 .inputmap = { TDA8425_S1_CH1, TDA8425_S1_CH1, TDA8425_S1_CH1 },
1419 .inputmute = TDA8425_S1_OFF,
1420
1da177e4
LT		 1421 },
1422 {
1423 .name = "pic16c54 (PV951)",
1da177e4 1424 .insmodopt = &pic16c54,
09df1c16
MCC		 1425 .addr_lo = I2C_ADDR_PIC16C54 >> 1,
1426 .addr_hi = I2C_ADDR_PIC16C54>> 1,
1da177e4
LT		 1427 .registers = 2,
1428 .flags = CHIP_HAS_INPUTSEL,
1429
1430 .inputreg = PIC16C54_REG_MISC,
1431 .inputmap = {PIC16C54_MISC_SND_NOTMUTE|PIC16C54_MISC_SWITCH_TUNER,
1432 PIC16C54_MISC_SND_NOTMUTE|PIC16C54_MISC_SWITCH_LINE,
1433 PIC16C54_MISC_SND_NOTMUTE|PIC16C54_MISC_SWITCH_LINE,
8bf2f8e7 1434 PIC16C54_MISC_SND_MUTE},
1da177e4
LT		 1435 .inputmute = PIC16C54_MISC_SND_MUTE,
1436 },
1437 {
1438 .name = "ta8874z",
1da177e4
LT		 1439 .checkit = ta8874z_checkit,
1440 .insmodopt = &ta8874z,
09df1c16
MCC		 1441 .addr_lo = I2C_ADDR_TDA9840 >> 1,
1442 .addr_hi = I2C_ADDR_TDA9840 >> 1,
1da177e4 1443 .registers = 2,
dd03e970 1444 .flags = CHIP_NEED_CHECKMODE,
1da177e4 1445
af1a9951 1446 /* callbacks */
1da177e4
LT		 1447 .getmode = ta8874z_getmode,
1448 .setmode = ta8874z_setmode,
1da177e4 1449
4ac97914 1450 .init = {2, { TA8874Z_MONO_SET, TA8874Z_SEPARATION_DEFAULT}},
1da177e4
LT		 1451 },
1452 { .name = NULL } /* EOF */
1453};
1454
1455
1456/* ---------------------------------------------------------------------- */
1457/* i2c registration */
1458
d2653e92 1459static int chip_probe(struct i2c_client *client, const struct i2c_device_id *id)
1da177e4
LT		 1460{
1461 struct CHIPSTATE *chip;
1462 struct CHIPDESC *desc;
1463
08e14054
HV		 1464 if (debug) {
1465 printk(KERN_INFO "tvaudio: TV audio decoder + audio/video mux driver\n");
1466 printk(KERN_INFO "tvaudio: known chips: ");
1467 for (desc = chiplist; desc->name != NULL; desc++)
1468 printk("%s%s", (desc == chiplist) ? "" : ", ", desc->name);
1469 printk("\n");
1470 }
1471
7408187d 1472 chip = kzalloc(sizeof(*chip),GFP_KERNEL);
1da177e4
LT		 1473 if (!chip)
1474 return -ENOMEM;
08e14054
HV		 1475 chip->c = client;
1476 i2c_set_clientdata(client, chip);
1da177e4
LT		 1477
1478 /* find description for the chip */
08e14054 1479 v4l_dbg(1, debug, client, "chip found @ 0x%x\n", client->addr<<1);
1da177e4
LT		 1480 for (desc = chiplist; desc->name != NULL; desc++) {
1481 if (0 == *(desc->insmodopt))
1482 continue;
08e14054
HV		 1483 if (client->addr < desc->addr_lo ||
1484 client->addr > desc->addr_hi)
1da177e4
LT		 1485 continue;
1486 if (desc->checkit && !desc->checkit(chip))
1487 continue;
1488 break;
1489 }
1490 if (desc->name == NULL) {
08e14054 1491 v4l_dbg(1, debug, client, "no matching chip description found\n");
5c653351 1492 kfree(chip);
1da177e4
LT		 1493 return -EIO;
1494 }
08e14054 1495 v4l_info(client, "%s found @ 0x%x (%s)\n", desc->name, client->addr<<1, client->adapter->name);
afd1a0c9 1496 if (desc->flags) {
08e14054 1497 v4l_dbg(1, debug, client, "matches:%s%s%s.\n",
674434c6
MCC		 1498 (desc->flags & CHIP_HAS_VOLUME) ? " volume" : "",
1499 (desc->flags & CHIP_HAS_BASSTREBLE) ? " bass/treble" : "",
1500 (desc->flags & CHIP_HAS_INPUTSEL) ? " audiomux" : "");
afd1a0c9 1501 }
1da177e4
LT		 1502
1503 /* fill required data structures */
ae429083
JD		 1504 if (!id)
1505 strlcpy(client->name, desc->name, I2C_NAME_SIZE);
1da177e4
LT		 1506 chip->type = desc-chiplist;
1507 chip->shadow.count = desc->registers+1;
afd1a0c9 1508 chip->prevmode = -1;
8a4b275f 1509 chip->audmode = V4L2_TUNER_MODE_LANG1;
1da177e4
LT		 1510
1511 /* initialization */
1512 if (desc->initialize != NULL)
1513 desc->initialize(chip);
1514 else
1515 chip_cmd(chip,"init",&desc->init);
1516
1517 if (desc->flags & CHIP_HAS_VOLUME) {
099b7fcc
MCC		 1518 if (!desc->volfunc) {
1519 /* This shouldn't be happen. Warn user, but keep working
1520 without volume controls
1521 */
1522 v4l_info(chip->c, "volume callback undefined!\n");
1523 desc->flags &= ~CHIP_HAS_VOLUME;
1524 } else {
1525 chip->left = desc->leftinit ? desc->leftinit : 65535;
1526 chip->right = desc->rightinit ? desc->rightinit : 65535;
1527 chip_write(chip, desc->leftreg,
1528 desc->volfunc(chip->left));
1529 chip_write(chip, desc->rightreg,
1530 desc->volfunc(chip->right));
1531 }
1da177e4
LT		 1532 }
1533 if (desc->flags & CHIP_HAS_BASSTREBLE) {
099b7fcc
MCC		 1534 if (!desc->bassfunc || !desc->treblefunc) {
1535 /* This shouldn't be happen. Warn user, but keep working
1536 without bass/treble controls
1537 */
1538 v4l_info(chip->c, "bass/treble callbacks undefined!\n");
1539 desc->flags &= ~CHIP_HAS_BASSTREBLE;
1540 } else {
1541 chip->treble = desc->trebleinit ?
1542 desc->trebleinit : 32768;
1543 chip->bass = desc->bassinit ?
1544 desc->bassinit : 32768;
1545 chip_write(chip, desc->bassreg,
1546 desc->bassfunc(chip->bass));
1547 chip_write(chip, desc->treblereg,
1548 desc->treblefunc(chip->treble));
1549 }
1da177e4
LT		 1550 }
1551
bc282879 1552 chip->thread = NULL;
dd03e970 1553 if (desc->flags & CHIP_NEED_CHECKMODE) {
099b7fcc
MCC		 1554 if (!desc->getmode || !desc->setmode) {
1555 /* This shouldn't be happen. Warn user, but keep working
1556 without kthread
1557 */
1558 v4l_info(chip->c, "set/get mode callbacks undefined!\n");
1559 return 0;
1560 }
1da177e4
LT		 1561 /* start async thread */
1562 init_timer(&chip->wt);
1563 chip->wt.function = chip_thread_wake;
1564 chip->wt.data = (unsigned long)chip;
08e14054 1565 chip->thread = kthread_run(chip_thread, chip, chip->c->name);
bc282879 1566 if (IS_ERR(chip->thread)) {
08e14054
HV		 1567 v4l_warn(chip->c, "%s: failed to create kthread\n",
1568 chip->c->name);
bc282879
CLG		 1569 chip->thread = NULL;
1570 }
1da177e4
LT		 1571 }
1572 return 0;
1573}
1574
08e14054 1575static int chip_remove(struct i2c_client *client)
1da177e4
LT		 1576{
1577 struct CHIPSTATE *chip = i2c_get_clientdata(client);
1578
1579 del_timer_sync(&chip->wt);
bc282879 1580 if (chip->thread) {
1da177e4 1581 /* shutdown async thread */
bc282879
CLG		 1582 kthread_stop(chip->thread);
1583 chip->thread = NULL;
1da177e4
LT		 1584 }
1585
1da177e4
LT		 1586 kfree(chip);
1587 return 0;
1588}
1589
dc3d75da
MCC		 1590static int tvaudio_get_ctrl(struct CHIPSTATE *chip,
1591 struct v4l2_control *ctrl)
1592{
1593 struct CHIPDESC *desc = chiplist + chip->type;
1594
1595 switch (ctrl->id) {
1596 case V4L2_CID_AUDIO_MUTE:
1597 ctrl->value=chip->muted;
1598 return 0;
1599 case V4L2_CID_AUDIO_VOLUME:
18c0ecf1 1600 if (!(desc->flags & CHIP_HAS_VOLUME))
dc3d75da
MCC		 1601 break;
1602 ctrl->value = max(chip->left,chip->right);
1603 return 0;
1604 case V4L2_CID_AUDIO_BALANCE:
1605 {
1606 int volume;
18c0ecf1 1607 if (!(desc->flags & CHIP_HAS_VOLUME))
dc3d75da
MCC		 1608 break;
1609 volume = max(chip->left,chip->right);
1610 if (volume)
1611 ctrl->value=(32768*min(chip->left,chip->right))/volume;
1612 else
1613 ctrl->value=32768;
1614 return 0;
1615 }
1616 case V4L2_CID_AUDIO_BASS:
1617 if (desc->flags & CHIP_HAS_BASSTREBLE)
1618 break;
1619 ctrl->value = chip->bass;
1620 return 0;
1621 case V4L2_CID_AUDIO_TREBLE:
1622 if (desc->flags & CHIP_HAS_BASSTREBLE)
1623 return -EINVAL;
1624 ctrl->value = chip->treble;
1625 return 0;
1626 }
1627 return -EINVAL;
1628}
1629
1630static int tvaudio_set_ctrl(struct CHIPSTATE *chip,
1631 struct v4l2_control *ctrl)
8bf2f8e7
HV		 1632{
1633 struct CHIPDESC *desc = chiplist + chip->type;
1634
1635 switch (ctrl->id) {
1636 case V4L2_CID_AUDIO_MUTE:
1637 if (ctrl->value < 0 || ctrl->value >= 2)
1638 return -ERANGE;
1639 chip->muted = ctrl->value;
1640 if (chip->muted)
1641 chip_write_masked(chip,desc->inputreg,desc->inputmute,desc->inputmask);
1642 else
1643 chip_write_masked(chip,desc->inputreg,
1644 desc->inputmap[chip->input],desc->inputmask);
dc3d75da
MCC		 1645 return 0;
1646 case V4L2_CID_AUDIO_VOLUME:
1647 {
1648 int volume,balance;
1649
18c0ecf1 1650 if (!(desc->flags & CHIP_HAS_VOLUME))
dc3d75da
MCC		 1651 break;
1652
1653 volume = max(chip->left,chip->right);
1654 if (volume)
1655 balance=(32768*min(chip->left,chip->right))/volume;
1656 else
1657 balance=32768;
1658
1659 volume=ctrl->value;
1660 chip->left = (min(65536 - balance,32768) * volume) / 32768;
1661 chip->right = (min(balance,volume *(__u16)32768)) / 32768;
1662
1663 chip_write(chip,desc->leftreg,desc->volfunc(chip->left));
1664 chip_write(chip,desc->rightreg,desc->volfunc(chip->right));
1665
1666 return 0;
8bf2f8e7 1667 }
dc3d75da
MCC		 1668 case V4L2_CID_AUDIO_BALANCE:
1669 {
1670 int volume, balance;
18c0ecf1 1671 if (!(desc->flags & CHIP_HAS_VOLUME))
dc3d75da
MCC		 1672 break;
1673
1674 volume = max(chip->left,chip->right);
1675 balance = ctrl->value;
1676
1677 chip_write(chip,desc->leftreg,desc->volfunc(chip->left));
1678 chip_write(chip,desc->rightreg,desc->volfunc(chip->right));
1679
1680 return 0;
1681 }
1682 case V4L2_CID_AUDIO_BASS:
1683 if (desc->flags & CHIP_HAS_BASSTREBLE)
1684 break;
1685 chip->bass = ctrl->value;
1686 chip_write(chip,desc->bassreg,desc->bassfunc(chip->bass));
1687
1688 return 0;
1689 case V4L2_CID_AUDIO_TREBLE:
1690 if (desc->flags & CHIP_HAS_BASSTREBLE)
1691 return -EINVAL;
1692
1693 chip->treble = ctrl->value;
1694 chip_write(chip,desc->treblereg,desc->treblefunc(chip->treble));
1695
1696 return 0;
1697 }
1698 return -EINVAL;
8bf2f8e7
HV		 1699}
1700
1701
1da177e4
LT		 1702/* ---------------------------------------------------------------------- */
1703/* video4linux interface */
1704
1705static int chip_command(struct i2c_client *client,
1706 unsigned int cmd, void *arg)
1707{
1da177e4
LT		 1708 struct CHIPSTATE *chip = i2c_get_clientdata(client);
1709 struct CHIPDESC *desc = chiplist + chip->type;
1710
08e14054 1711 v4l_dbg(1, debug, chip->c, "%s: chip_command 0x%x\n", chip->c->name, cmd);
1da177e4
LT		 1712
1713 switch (cmd) {
1da177e4 1714 case AUDC_SET_RADIO:
8a854284 1715 chip->radio = 1;
1da177e4
LT		 1716 chip->watch_stereo = 0;
1717 /* del_timer(&chip->wt); */
1718 break;
1da177e4
LT		 1719 /* --- v4l ioctls --- */
1720 /* take care: bttv does userspace copying, we'll get a
674434c6 1721 kernel pointer here... */
dc3d75da 1722 case VIDIOC_QUERYCTRL:
1da177e4 1723 {
dc3d75da
MCC		 1724 struct v4l2_queryctrl *qc = arg;
1725
1726 switch (qc->id) {
1727 case V4L2_CID_AUDIO_MUTE:
1728 break;
1729 case V4L2_CID_AUDIO_VOLUME:
1730 case V4L2_CID_AUDIO_BALANCE:
18c0ecf1 1731 if (!(desc->flags & CHIP_HAS_VOLUME))
dc3d75da
MCC		 1732 return -EINVAL;
1733 break;
1734 case V4L2_CID_AUDIO_BASS:
1735 case V4L2_CID_AUDIO_TREBLE:
1736 if (desc->flags & CHIP_HAS_BASSTREBLE)
1737 return -EINVAL;
1738 break;
1739 default:
1740 return -EINVAL;
1da177e4 1741 }
dc3d75da 1742 return v4l2_ctrl_query_fill_std(qc);
1da177e4 1743 }
8bf2f8e7
HV		 1744 case VIDIOC_S_CTRL:
1745 return tvaudio_set_ctrl(chip, arg);
1746
dc3d75da
MCC		 1747 case VIDIOC_G_CTRL:
1748 return tvaudio_get_ctrl(chip, arg);
2474ed44
HV		 1749 case VIDIOC_INT_G_AUDIO_ROUTING:
1750 {
1751 struct v4l2_routing *rt = arg;
1752
1753 rt->input = chip->input;
1754 rt->output = 0;
1755 break;
1756 }
2474ed44
HV		 1757 case VIDIOC_INT_S_AUDIO_ROUTING:
1758 {
1759 struct v4l2_routing *rt = arg;
1760
1761 if (!(desc->flags & CHIP_HAS_INPUTSEL) || rt->input >= 4)
1762 return -EINVAL;
1763 /* There are four inputs: tuner, radio, extern and intern. */
1764 chip->input = rt->input;
1765 if (chip->muted)
1766 break;
1767 chip_write_masked(chip, desc->inputreg,
1768 desc->inputmap[chip->input], desc->inputmask);
1769 break;
1770 }
8a854284 1771 case VIDIOC_S_TUNER:
1da177e4 1772 {
8a854284
HV		 1773 struct v4l2_tuner *vt = arg;
1774 int mode = 0;
1da177e4 1775
8a4b275f
HV		 1776 if (chip->radio)
1777 break;
8a854284
HV		 1778 switch (vt->audmode) {
1779 case V4L2_TUNER_MODE_MONO:
8a854284 1780 case V4L2_TUNER_MODE_STEREO:
8a854284 1781 case V4L2_TUNER_MODE_LANG1:
8a854284 1782 case V4L2_TUNER_MODE_LANG2:
dc3d75da
MCC		 1783 mode = vt->audmode;
1784 break;
1785 case V4L2_TUNER_MODE_LANG1_LANG2:
1786 mode = V4L2_TUNER_MODE_STEREO;
8a854284
HV		 1787 break;
1788 default:
8a4b275f 1789 return -EINVAL;
8a854284 1790 }
8a4b275f 1791 chip->audmode = vt->audmode;
8a854284
HV		 1792
1793 if (desc->setmode && mode) {
1794 chip->watch_stereo = 0;
1795 /* del_timer(&chip->wt); */
1796 chip->mode = mode;
1797 desc->setmode(chip, mode);
1798 }
1da177e4
LT		 1799 break;
1800 }
8a854284 1801 case VIDIOC_G_TUNER:
1da177e4 1802 {
8a854284 1803 struct v4l2_tuner *vt = arg;
dc3d75da 1804 int mode = V4L2_TUNER_MODE_MONO;
8a854284 1805
d3900bc4
HV		 1806 if (chip->radio)
1807 break;
8a4b275f 1808 vt->audmode = chip->audmode;
8a854284
HV		 1809 vt->rxsubchans = 0;
1810 vt->capability = V4L2_TUNER_CAP_STEREO |
1811 V4L2_TUNER_CAP_LANG1 | V4L2_TUNER_CAP_LANG2;
8a854284
HV		 1812
1813 if (desc->getmode)
1814 mode = desc->getmode(chip);
1815
dc3d75da 1816 if (mode & V4L2_TUNER_MODE_MONO)
8a854284 1817 vt->rxsubchans |= V4L2_TUNER_SUB_MONO;
dc3d75da 1818 if (mode & V4L2_TUNER_MODE_STEREO)
8a854284 1819 vt->rxsubchans |= V4L2_TUNER_SUB_STEREO;
8a4b275f
HV		 1820 /* Note: for SAP it should be mono/lang2 or stereo/lang2.
1821 When this module is converted fully to v4l2, then this
1822 should change for those chips that can detect SAP. */
dc3d75da 1823 if (mode & V4L2_TUNER_MODE_LANG1)
8a4b275f
HV		 1824 vt->rxsubchans = V4L2_TUNER_SUB_LANG1 |
1825 V4L2_TUNER_SUB_LANG2;
8a854284
HV		 1826 break;
1827 }
8a854284
HV		 1828 case VIDIOC_S_STD:
1829 chip->radio = 0;
1830 break;
8a854284 1831 case VIDIOC_S_FREQUENCY:
18fc59e2 1832 chip->mode = 0; /* automatic */
dd03e970
MCC		 1833
1834 /* For chips that provide getmode, setmode and checkmode,
1835 a kthread is created to automatically to set the audio
1836 standard. In this case, start with MONO and wait 2 seconds
1837 for the decoding to stablize. Then, run kthread to change
1838 to stereo, if carrier detected.
1839 */
1840 if (chip->thread) {
dc3d75da
MCC		 1841 desc->setmode(chip,V4L2_TUNER_MODE_MONO);
1842 if (chip->prevmode != V4L2_TUNER_MODE_MONO)
18fc59e2 1843 chip->prevmode = -1; /* reset previous mode */
09df5cbe 1844 mod_timer(&chip->wt, jiffies+msecs_to_jiffies(2000));
1da177e4 1845 }
8a854284 1846 break;
74cab31c
HV		 1847
1848 case VIDIOC_G_CHIP_IDENT:
1849 return v4l2_chip_ident_i2c_client(client, arg, V4L2_IDENT_TVAUDIO, 0);
1da177e4
LT		 1850 }
1851 return 0;
1852}
1853
08e14054 1854static int chip_legacy_probe(struct i2c_adapter *adap)
1da177e4 1855{
08e14054
HV		 1856 /* don't attach on saa7146 based cards,
1857 because dedicated drivers are used */
1858 if ((adap->id == I2C_HW_SAA7146))
1859 return 0;
1860 if (adap->class & I2C_CLASS_TV_ANALOG)
1861 return 1;
1862 return 0;
1da177e4
LT		 1863}
1864
ae429083
JD		 1865/* This driver supports many devices and the idea is to let the driver
1866 detect which device is present. So rather than listing all supported
1867 devices here, we pretend to support a single, fake device type. */
1868static const struct i2c_device_id chip_id[] = {
1869 { "tvaudio", 0 },
1870 { }
1871};
1872MODULE_DEVICE_TABLE(i2c, chip_id);
1873
08e14054
HV		 1874static struct v4l2_i2c_driver_data v4l2_i2c_data = {
1875 .name = "tvaudio",
1876 .driverid = I2C_DRIVERID_TVAUDIO,
1877 .command = chip_command,
1878 .probe = chip_probe,
1879 .remove = chip_remove,
1880 .legacy_probe = chip_legacy_probe,
ae429083 1881 .id_table = chip_id,
08e14054 1882};
1da177e4
LT		 1883
1884/*
1885 * Local variables:
1886 * c-basic-offset: 8
1887 * End:
1888 */
kernel source for telekom puls (alcatel/mediatek)